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drm/i915: remove unused WM defines
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
159f9875
VS		 118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
85208be0
ED		 127
128 /* enable it... */
993495ae
VS		 129 fbc_ctl = I915_READ(FBC_CONTROL);
130 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
131 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 132 if (IS_I945GM(dev))
133 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
134 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 135 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl);
137
84f44ce7
VS		 138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 140}
141
1fa61106 142static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145
146 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147}
148
993495ae 149static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 150{
151 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
85208be0
ED		 164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165
166 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
168
84f44ce7 169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 170}
171
1fa61106 172static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = I915_READ(DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182
183 DRM_DEBUG_KMS("disabled FBC\n");
184 }
185}
186
1fa61106 187static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 188{
189 struct drm_i915_private *dev_priv = dev->dev_private;
190
191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
192}
193
194static void sandybridge_blit_fbc_update(struct drm_device *dev)
195{
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 u32 blt_ecoskpd;
198
199 /* Make sure blitter notifies FBC of writes */
940aece4
D		 200
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 204
85208be0
ED		 205 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
206 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
211 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
212 GEN6_BLITTER_LOCK_SHIFT);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 215
940aece4 216 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 217}
218
993495ae 219static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 220{
221 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 228 u32 dpfc_ctl;
229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 dpfc_ctl &= DPFC_RESERVED;
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0
ED		 238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239
85208be0 240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
84f44ce7 252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 253}
254
1fa61106 255static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268}
269
1fa61106 270static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 271{
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275}
276
993495ae 277static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 278{
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
f343c5f6 286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
891348b2 292 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 295 } else {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
891348b2 299 }
b74ea102 300
abe959c7
RV		 301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
b19870ee 307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 308}
309
85208be0
ED		 310bool intel_fbc_enabled(struct drm_device *dev)
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318}
319
320static void intel_fbc_work_fn(struct work_struct *__work)
321{
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
5c3fe8b0 329 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
993495ae 334 dev_priv->display.enable_fbc(work->crtc);
85208be0 335
5c3fe8b0
BW		 336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 339 }
340
5c3fe8b0 341 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
5c3fe8b0 350 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 357 * entirely asynchronously.
358 */
5c3fe8b0 359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 360 /* tasklet was killed before being run, clean up */
5c3fe8b0 361 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
5c3fe8b0 368 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 369}
370
993495ae 371static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
b14c5679 382 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 383 if (work == NULL) {
6cdcb5e7 384 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 385 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
85208be0
ED		 391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
ef644fda 461 const struct drm_display_mode *adjusted_mode;
37327abd 462 unsigned int max_width, max_height;
85208be0 463
29ebf90f
CW		 464 if (!I915_HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 466 return;
29ebf90f 467 }
85208be0 468
29ebf90f
CW		 469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 472 return;
29ebf90f 473 }
85208be0
ED		 474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 485 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 486 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 487 if (crtc) {
29ebf90f
CW		 488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
ef644fda 506 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 507
8a5729a3
DL		 508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 512 goto out_disable;
85208be0 513 }
8a5729a3 514 if (!i915_enable_fbc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 517 goto out_disable;
518 }
ef644fda
VS		 519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
85208be0
ED		 524 goto out_disable;
525 }
f85da868
PZ		 526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 528 max_width = 4096;
529 max_height = 2048;
f85da868 530 } else {
37327abd
VS		 531 max_width = 2048;
532 max_height = 1536;
f85da868 533 }
37327abd
VS		 534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 538 goto out_disable;
539 }
c5a44aa0
VS		 540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
541 intel_crtc->plane != PLANE_A) {
29ebf90f 542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
11be49eb 561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 564 goto out_disable;
565 }
566
85208be0
ED		 567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
5c3fe8b0
BW		 572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
85208be0
ED		 575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
993495ae 605 intel_enable_fbc(crtc);
29ebf90f 606 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 607 return;
608
609out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
11be49eb 615 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 616}
617
c921aba8
DV		 618static void i915_pineview_get_mem_freq(struct drm_device *dev)
619{
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655}
656
657static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658{
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
20e4d407 685 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
20e4d407 717 dev_priv->ips.c_m = 0;
c921aba8 718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 719 dev_priv->ips.c_m = 1;
c921aba8 720 } else {
20e4d407 721 dev_priv->ips.c_m = 2;
c921aba8
DV		 722 }
723}
724
b445e3b0
ED		 725static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761};
762
63c62275 763static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 764 int is_ddr3,
765 int fsb,
766 int mem)
767{
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785}
786
1fa61106 787static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793}
794
795/*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809static const int latency_ns = 5000;
810
1fa61106 811static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825}
826
1fa61106 827static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 828{
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842}
843
1fa61106 844static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858}
859
1fa61106 860static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 861{
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dsparb = I915_READ(DSPARB);
864 int size;
865
866 size = dsparb & 0x7f;
867 size >>= 1; /* Convert to cachelines */
868
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
870 plane ? "B" : "A", size);
871
872 return size;
873}
874
875/* Pineview has different values for various configs */
876static const struct intel_watermark_params pineview_display_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_display_hplloff_wm = {
884 PINEVIEW_DISPLAY_FIFO,
885 PINEVIEW_MAX_WM,
886 PINEVIEW_DFT_HPLLOFF_WM,
887 PINEVIEW_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE
889};
890static const struct intel_watermark_params pineview_cursor_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE,
896};
897static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
898 PINEVIEW_CURSOR_FIFO,
899 PINEVIEW_CURSOR_MAX_WM,
900 PINEVIEW_CURSOR_DFT_WM,
901 PINEVIEW_CURSOR_GUARD_WM,
902 PINEVIEW_FIFO_LINE_SIZE
903};
904static const struct intel_watermark_params g4x_wm_info = {
905 G4X_FIFO_SIZE,
906 G4X_MAX_WM,
907 G4X_MAX_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params g4x_cursor_wm_info = {
912 I965_CURSOR_FIFO,
913 I965_CURSOR_MAX_WM,
914 I965_CURSOR_DFT_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_wm_info = {
919 VALLEYVIEW_FIFO_SIZE,
920 VALLEYVIEW_MAX_WM,
921 VALLEYVIEW_MAX_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params valleyview_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 VALLEYVIEW_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 G4X_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i965_cursor_wm_info = {
933 I965_CURSOR_FIFO,
934 I965_CURSOR_MAX_WM,
935 I965_CURSOR_DFT_WM,
936 2,
937 I915_FIFO_LINE_SIZE,
938};
939static const struct intel_watermark_params i945_wm_info = {
940 I945_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i915_wm_info = {
947 I915_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I915_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i855_wm_info = {
954 I855GM_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960static const struct intel_watermark_params i830_wm_info = {
961 I830_FIFO_SIZE,
962 I915_MAX_WM,
963 1,
964 2,
965 I830_FIFO_LINE_SIZE
966};
967
b445e3b0
ED		 968/**
969 * intel_calculate_wm - calculate watermark level
970 * @clock_in_khz: pixel clock
971 * @wm: chip FIFO params
972 * @pixel_size: display pixel size
973 * @latency_ns: memory latency for the platform
974 *
975 * Calculate the watermark level (the level at which the display plane will
976 * start fetching from memory again). Each chip has a different display
977 * FIFO size and allocation, so the caller needs to figure that out and pass
978 * in the correct intel_watermark_params structure.
979 *
980 * As the pixel clock runs, the FIFO will be drained at a rate that depends
981 * on the pixel size. When it reaches the watermark level, it'll start
982 * fetching FIFO line sized based chunks from memory until the FIFO fills
983 * past the watermark point. If the FIFO drains completely, a FIFO underrun
984 * will occur, and a display engine hang could result.
985 */
986static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
987 const struct intel_watermark_params *wm,
988 int fifo_size,
989 int pixel_size,
990 unsigned long latency_ns)
991{
992 long entries_required, wm_size;
993
994 /*
995 * Note: we need to make sure we don't overflow for various clock &
996 * latency values.
997 * clocks go from a few thousand to several hundred thousand.
998 * latency is usually a few thousand
999 */
1000 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1001 1000;
1002 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1003
1004 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1005
1006 wm_size = fifo_size - (entries_required + wm->guard_size);
1007
1008 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1009
1010 /* Don't promote wm_size to unsigned... */
1011 if (wm_size > (long)wm->max_wm)
1012 wm_size = wm->max_wm;
1013 if (wm_size <= 0)
1014 wm_size = wm->default_wm;
1015 return wm_size;
1016}
1017
1018static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1019{
1020 struct drm_crtc *crtc, *enabled = NULL;
1021
1022 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1023 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1024 if (enabled)
1025 return NULL;
1026 enabled = crtc;
1027 }
1028 }
1029
1030 return enabled;
1031}
1032
46ba614c 1033static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1034{
46ba614c 1035 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 struct drm_crtc *crtc;
1038 const struct cxsr_latency *latency;
1039 u32 reg;
1040 unsigned long wm;
1041
1042 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1043 dev_priv->fsb_freq, dev_priv->mem_freq);
1044 if (!latency) {
1045 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1046 pineview_disable_cxsr(dev);
1047 return;
1048 }
1049
1050 crtc = single_enabled_crtc(dev);
1051 if (crtc) {
241bfc38 1052 const struct drm_display_mode *adjusted_mode;
b445e3b0 1053 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1054 int clock;
1055
1056 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1057 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1058
1059 /* Display SR */
1060 wm = intel_calculate_wm(clock, &pineview_display_wm,
1061 pineview_display_wm.fifo_size,
1062 pixel_size, latency->display_sr);
1063 reg = I915_READ(DSPFW1);
1064 reg &= ~DSPFW_SR_MASK;
1065 reg |= wm << DSPFW_SR_SHIFT;
1066 I915_WRITE(DSPFW1, reg);
1067 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1068
1069 /* cursor SR */
1070 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1071 pineview_display_wm.fifo_size,
1072 pixel_size, latency->cursor_sr);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_CURSOR_SR_MASK;
1075 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* Display HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->display_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_SR_MASK;
1084 reg |= wm & DSPFW_HPLL_SR_MASK;
1085 I915_WRITE(DSPFW3, reg);
1086
1087 /* cursor HPLL off SR */
1088 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1089 pineview_display_hplloff_wm.fifo_size,
1090 pixel_size, latency->cursor_hpll_disable);
1091 reg = I915_READ(DSPFW3);
1092 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1093 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1094 I915_WRITE(DSPFW3, reg);
1095 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1096
1097 /* activate cxsr */
1098 I915_WRITE(DSPFW3,
1099 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1100 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1101 } else {
1102 pineview_disable_cxsr(dev);
1103 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1104 }
1105}
1106
1107static bool g4x_compute_wm0(struct drm_device *dev,
1108 int plane,
1109 const struct intel_watermark_params *display,
1110 int display_latency_ns,
1111 const struct intel_watermark_params *cursor,
1112 int cursor_latency_ns,
1113 int *plane_wm,
1114 int *cursor_wm)
1115{
1116 struct drm_crtc *crtc;
4fe8590a 1117 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1118 int htotal, hdisplay, clock, pixel_size;
1119 int line_time_us, line_count;
1120 int entries, tlb_miss;
1121
1122 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1123 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1124 *cursor_wm = cursor->guard_size;
1125 *plane_wm = display->guard_size;
1126 return false;
1127 }
1128
4fe8590a 1129 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1130 clock = adjusted_mode->crtc_clock;
4fe8590a 1131 htotal = adjusted_mode->htotal;
37327abd 1132 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1133 pixel_size = crtc->fb->bits_per_pixel / 8;
1134
1135 /* Use the small buffer method to calculate plane watermark */
1136 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1137 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1138 if (tlb_miss > 0)
1139 entries += tlb_miss;
1140 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1141 *plane_wm = entries + display->guard_size;
1142 if (*plane_wm > (int)display->max_wm)
1143 *plane_wm = display->max_wm;
1144
1145 /* Use the large buffer method to calculate cursor watermark */
1146 line_time_us = ((htotal * 1000) / clock);
1147 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1148 entries = line_count * 64 * pixel_size;
1149 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1150 if (tlb_miss > 0)
1151 entries += tlb_miss;
1152 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1153 *cursor_wm = entries + cursor->guard_size;
1154 if (*cursor_wm > (int)cursor->max_wm)
1155 *cursor_wm = (int)cursor->max_wm;
1156
1157 return true;
1158}
1159
1160/*
1161 * Check the wm result.
1162 *
1163 * If any calculated watermark values is larger than the maximum value that
1164 * can be programmed into the associated watermark register, that watermark
1165 * must be disabled.
1166 */
1167static bool g4x_check_srwm(struct drm_device *dev,
1168 int display_wm, int cursor_wm,
1169 const struct intel_watermark_params *display,
1170 const struct intel_watermark_params *cursor)
1171{
1172 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1173 display_wm, cursor_wm);
1174
1175 if (display_wm > display->max_wm) {
1176 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1177 display_wm, display->max_wm);
1178 return false;
1179 }
1180
1181 if (cursor_wm > cursor->max_wm) {
1182 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1183 cursor_wm, cursor->max_wm);
1184 return false;
1185 }
1186
1187 if (!(display_wm || cursor_wm)) {
1188 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1189 return false;
1190 }
1191
1192 return true;
1193}
1194
1195static bool g4x_compute_srwm(struct drm_device *dev,
1196 int plane,
1197 int latency_ns,
1198 const struct intel_watermark_params *display,
1199 const struct intel_watermark_params *cursor,
1200 int *display_wm, int *cursor_wm)
1201{
1202 struct drm_crtc *crtc;
4fe8590a 1203 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1204 int hdisplay, htotal, pixel_size, clock;
1205 unsigned long line_time_us;
1206 int line_count, line_size;
1207 int small, large;
1208 int entries;
1209
1210 if (!latency_ns) {
1211 *display_wm = *cursor_wm = 0;
1212 return false;
1213 }
1214
1215 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1216 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1217 clock = adjusted_mode->crtc_clock;
4fe8590a 1218 htotal = adjusted_mode->htotal;
37327abd 1219 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1220 pixel_size = crtc->fb->bits_per_pixel / 8;
1221
1222 line_time_us = (htotal * 1000) / clock;
1223 line_count = (latency_ns / line_time_us + 1000) / 1000;
1224 line_size = hdisplay * pixel_size;
1225
1226 /* Use the minimum of the small and large buffer method for primary */
1227 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1228 large = line_count * line_size;
1229
1230 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1231 *display_wm = entries + display->guard_size;
1232
1233 /* calculate the self-refresh watermark for display cursor */
1234 entries = line_count * pixel_size * 64;
1235 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1236 *cursor_wm = entries + cursor->guard_size;
1237
1238 return g4x_check_srwm(dev,
1239 *display_wm, *cursor_wm,
1240 display, cursor);
1241}
1242
1243static bool vlv_compute_drain_latency(struct drm_device *dev,
1244 int plane,
1245 int *plane_prec_mult,
1246 int *plane_dl,
1247 int *cursor_prec_mult,
1248 int *cursor_dl)
1249{
1250 struct drm_crtc *crtc;
1251 int clock, pixel_size;
1252 int entries;
1253
1254 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1255 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1256 return false;
1257
241bfc38 1258 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1259 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1260
1261 entries = (clock / 1000) * pixel_size;
1262 *plane_prec_mult = (entries > 256) ?
1263 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1264 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1265 pixel_size);
1266
1267 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1268 *cursor_prec_mult = (entries > 256) ?
1269 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1270 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1271
1272 return true;
1273}
1274
1275/*
1276 * Update drain latency registers of memory arbiter
1277 *
1278 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1279 * to be programmed. Each plane has a drain latency multiplier and a drain
1280 * latency value.
1281 */
1282
1283static void vlv_update_drain_latency(struct drm_device *dev)
1284{
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1287 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1288 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1289 either 16 or 32 */
1290
1291 /* For plane A, Cursor A */
1292 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1293 &cursor_prec_mult, &cursora_dl)) {
1294 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1295 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1296 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1297 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1298
1299 I915_WRITE(VLV_DDL1, cursora_prec |
1300 (cursora_dl << DDL_CURSORA_SHIFT) |
1301 planea_prec | planea_dl);
1302 }
1303
1304 /* For plane B, Cursor B */
1305 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1306 &cursor_prec_mult, &cursorb_dl)) {
1307 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1308 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1309 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1310 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1311
1312 I915_WRITE(VLV_DDL2, cursorb_prec |
1313 (cursorb_dl << DDL_CURSORB_SHIFT) |
1314 planeb_prec | planeb_dl);
1315 }
1316}
1317
1318#define single_plane_enabled(mask) is_power_of_2(mask)
1319
46ba614c 1320static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1321{
46ba614c 1322 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1323 static const int sr_latency_ns = 12000;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1326 int plane_sr, cursor_sr;
af6c4575 1327 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1328 unsigned int enabled = 0;
1329
1330 vlv_update_drain_latency(dev);
1331
51cea1f4 1332 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1333 &valleyview_wm_info, latency_ns,
1334 &valleyview_cursor_wm_info, latency_ns,
1335 &planea_wm, &cursora_wm))
51cea1f4 1336 enabled |= 1 << PIPE_A;
b445e3b0 1337
51cea1f4 1338 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1339 &valleyview_wm_info, latency_ns,
1340 &valleyview_cursor_wm_info, latency_ns,
1341 &planeb_wm, &cursorb_wm))
51cea1f4 1342 enabled |= 1 << PIPE_B;
b445e3b0 1343
b445e3b0
ED		 1344 if (single_plane_enabled(enabled) &&
1345 g4x_compute_srwm(dev, ffs(enabled) - 1,
1346 sr_latency_ns,
1347 &valleyview_wm_info,
1348 &valleyview_cursor_wm_info,
af6c4575
CW		 1349 &plane_sr, &ignore_cursor_sr) &&
1350 g4x_compute_srwm(dev, ffs(enabled) - 1,
1351 2*sr_latency_ns,
1352 &valleyview_wm_info,
1353 &valleyview_cursor_wm_info,
52bd02d8 1354 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1355 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1356 } else {
b445e3b0
ED		 1357 I915_WRITE(FW_BLC_SELF_VLV,
1358 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1359 plane_sr = cursor_sr = 0;
1360 }
b445e3b0
ED		 1361
1362 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1363 planea_wm, cursora_wm,
1364 planeb_wm, cursorb_wm,
1365 plane_sr, cursor_sr);
1366
1367 I915_WRITE(DSPFW1,
1368 (plane_sr << DSPFW_SR_SHIFT) |
1369 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1370 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1371 planea_wm);
1372 I915_WRITE(DSPFW2,
8c919b28 1373 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1374 (cursora_wm << DSPFW_CURSORA_SHIFT));
1375 I915_WRITE(DSPFW3,
8c919b28
CW		 1376 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1377 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1378}
1379
46ba614c 1380static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1381{
46ba614c 1382 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1383 static const int sr_latency_ns = 12000;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1390 &g4x_wm_info, latency_ns,
1391 &g4x_cursor_wm_info, latency_ns,
1392 &planea_wm, &cursora_wm))
51cea1f4 1393 enabled |= 1 << PIPE_A;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1396 &g4x_wm_info, latency_ns,
1397 &g4x_cursor_wm_info, latency_ns,
1398 &planeb_wm, &cursorb_wm))
51cea1f4 1399 enabled |= 1 << PIPE_B;
b445e3b0 1400
b445e3b0
ED		 1401 if (single_plane_enabled(enabled) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 sr_latency_ns,
1404 &g4x_wm_info,
1405 &g4x_cursor_wm_info,
52bd02d8 1406 &plane_sr, &cursor_sr)) {
b445e3b0 1407 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1408 } else {
b445e3b0
ED		 1409 I915_WRITE(FW_BLC_SELF,
1410 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1411 plane_sr = cursor_sr = 0;
1412 }
b445e3b0
ED		 1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm, cursora_wm,
1416 planeb_wm, cursorb_wm,
1417 plane_sr, cursor_sr);
1418
1419 I915_WRITE(DSPFW1,
1420 (plane_sr << DSPFW_SR_SHIFT) |
1421 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1422 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1423 planea_wm);
1424 I915_WRITE(DSPFW2,
8c919b28 1425 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1426 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 /* HPLL off in SR has some issues on G4x... disable it */
1428 I915_WRITE(DSPFW3,
8c919b28 1429 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1430 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1431}
1432
46ba614c 1433static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1434{
46ba614c 1435 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct drm_crtc *crtc;
1438 int srwm = 1;
1439 int cursor_sr = 16;
1440
1441 /* Calc sr entries for one plane configs */
1442 crtc = single_enabled_crtc(dev);
1443 if (crtc) {
1444 /* self-refresh has much higher latency */
1445 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1446 const struct drm_display_mode *adjusted_mode =
1447 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1448 int clock = adjusted_mode->crtc_clock;
4fe8590a 1449 int htotal = adjusted_mode->htotal;
37327abd 1450 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1451 int pixel_size = crtc->fb->bits_per_pixel / 8;
1452 unsigned long line_time_us;
1453 int entries;
1454
1455 line_time_us = ((htotal * 1000) / clock);
1456
1457 /* Use ns/us then divide to preserve precision */
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 pixel_size * hdisplay;
1460 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1461 srwm = I965_FIFO_SIZE - entries;
1462 if (srwm < 0)
1463 srwm = 1;
1464 srwm &= 0x1ff;
1465 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1466 entries, srwm);
1467
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469 pixel_size * 64;
1470 entries = DIV_ROUND_UP(entries,
1471 i965_cursor_wm_info.cacheline_size);
1472 cursor_sr = i965_cursor_wm_info.fifo_size -
1473 (entries + i965_cursor_wm_info.guard_size);
1474
1475 if (cursor_sr > i965_cursor_wm_info.max_wm)
1476 cursor_sr = i965_cursor_wm_info.max_wm;
1477
1478 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1479 "cursor %d\n", srwm, cursor_sr);
1480
1481 if (IS_CRESTLINE(dev))
1482 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1483 } else {
1484 /* Turn off self refresh if both pipes are enabled */
1485 if (IS_CRESTLINE(dev))
1486 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1487 & ~FW_BLC_SELF_EN);
1488 }
1489
1490 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1491 srwm);
1492
1493 /* 965 has limitations... */
1494 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1495 (8 << 16) | (8 << 8) | (8 << 0));
1496 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1497 /* update cursor SR watermark */
1498 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1499}
1500
46ba614c 1501static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1502{
46ba614c 1503 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 const struct intel_watermark_params *wm_info;
1506 uint32_t fwater_lo;
1507 uint32_t fwater_hi;
1508 int cwm, srwm = 1;
1509 int fifo_size;
1510 int planea_wm, planeb_wm;
1511 struct drm_crtc *crtc, *enabled = NULL;
1512
1513 if (IS_I945GM(dev))
1514 wm_info = &i945_wm_info;
1515 else if (!IS_GEN2(dev))
1516 wm_info = &i915_wm_info;
1517 else
1518 wm_info = &i855_wm_info;
1519
1520 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1521 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1522 if (intel_crtc_active(crtc)) {
241bfc38 1523 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1524 int cpp = crtc->fb->bits_per_pixel / 8;
1525 if (IS_GEN2(dev))
1526 cpp = 4;
1527
241bfc38
DL		 1528 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1529 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1530 wm_info, fifo_size, cpp,
b445e3b0
ED		 1531 latency_ns);
1532 enabled = crtc;
1533 } else
1534 planea_wm = fifo_size - wm_info->guard_size;
1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1537 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1540 int cpp = crtc->fb->bits_per_pixel / 8;
1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
241bfc38
DL		 1544 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1545 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
b445e3b0
ED		 1547 latency_ns);
1548 if (enabled == NULL)
1549 enabled = crtc;
1550 else
1551 enabled = NULL;
1552 } else
1553 planeb_wm = fifo_size - wm_info->guard_size;
1554
1555 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1556
1557 /*
1558 * Overlay gets an aggressive default since video jitter is bad.
1559 */
1560 cwm = 2;
1561
1562 /* Play safe and disable self-refresh before adjusting watermarks. */
1563 if (IS_I945G(dev) || IS_I945GM(dev))
1564 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1565 else if (IS_I915GM(dev))
1566 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1567
1568 /* Calc sr entries for one plane configs */
1569 if (HAS_FW_BLC(dev) && enabled) {
1570 /* self-refresh has much higher latency */
1571 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1572 const struct drm_display_mode *adjusted_mode =
1573 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1574 int clock = adjusted_mode->crtc_clock;
4fe8590a 1575 int htotal = adjusted_mode->htotal;
f727b490 1576 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
b445e3b0
ED		 1577 int pixel_size = enabled->fb->bits_per_pixel / 8;
1578 unsigned long line_time_us;
1579 int entries;
1580
1581 line_time_us = (htotal * 1000) / clock;
1582
1583 /* Use ns/us then divide to preserve precision */
1584 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1585 pixel_size * hdisplay;
1586 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1587 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1588 srwm = wm_info->fifo_size - entries;
1589 if (srwm < 0)
1590 srwm = 1;
1591
1592 if (IS_I945G(dev) || IS_I945GM(dev))
1593 I915_WRITE(FW_BLC_SELF,
1594 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1595 else if (IS_I915GM(dev))
1596 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1597 }
1598
1599 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1600 planea_wm, planeb_wm, cwm, srwm);
1601
1602 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1603 fwater_hi = (cwm & 0x1f);
1604
1605 /* Set request length to 8 cachelines per fetch */
1606 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1607 fwater_hi = fwater_hi | (1 << 8);
1608
1609 I915_WRITE(FW_BLC, fwater_lo);
1610 I915_WRITE(FW_BLC2, fwater_hi);
1611
1612 if (HAS_FW_BLC(dev)) {
1613 if (enabled) {
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF,
1616 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1619 DRM_DEBUG_KMS("memory self refresh enabled\n");
1620 } else
1621 DRM_DEBUG_KMS("memory self refresh disabled\n");
1622 }
1623}
1624
46ba614c 1625static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1626{
46ba614c 1627 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 struct drm_crtc *crtc;
241bfc38 1630 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1631 uint32_t fwater_lo;
1632 int planea_wm;
1633
1634 crtc = single_enabled_crtc(dev);
1635 if (crtc == NULL)
1636 return;
1637
241bfc38
DL		 1638 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1639 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1640 &i830_wm_info,
b445e3b0 1641 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1642 4, latency_ns);
b445e3b0
ED		 1643 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1644 fwater_lo |= (3<<8) | planea_wm;
1645
1646 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1647
1648 I915_WRITE(FW_BLC, fwater_lo);
1649}
1650
3658729a
VS		 1651static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1652 struct drm_crtc *crtc)
801bcfff
PZ		 1653{
1654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1655 uint32_t pixel_rate;
801bcfff 1656
241bfc38 1657 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
fd4daa9c 1662 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1664 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1665
37327abd
VS		 1666 pipe_w = intel_crtc->config.pipe_src_w;
1667 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676 pfit_w * pfit_h);
1677 }
1678
1679 return pixel_rate;
1680}
1681
37126462 1682/* latency must be in 0.1us units. */
23297044 1683static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1684 uint32_t latency)
1685{
1686 uint64_t ret;
1687
3312ba65
VS		 1688 if (WARN(latency == 0, "Latency value missing\n"))
1689 return UINT_MAX;
1690
801bcfff
PZ		 1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694 return ret;
1695}
1696
37126462 1697/* latency must be in 0.1us units. */
23297044 1698static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700 uint32_t latency)
1701{
1702 uint32_t ret;
1703
3312ba65
VS		 1704 if (WARN(latency == 0, "Latency value missing\n"))
1705 return UINT_MAX;
1706
801bcfff
PZ		 1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1710 return ret;
1711}
1712
23297044 1713static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1714 uint8_t bytes_per_pixel)
1715{
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717}
1718
801bcfff
PZ		 1719struct hsw_pipe_wm_parameters {
1720 bool active;
801bcfff
PZ		 1721 uint32_t pipe_htotal;
1722 uint32_t pixel_rate;
c35426d2
VS		 1723 struct intel_plane_wm_parameters pri;
1724 struct intel_plane_wm_parameters spr;
1725 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1726};
1727
cca32e9a
PZ		 1728struct hsw_wm_maximums {
1729 uint16_t pri;
1730 uint16_t spr;
1731 uint16_t cur;
1732 uint16_t fbc;
1733};
1734
240264f4
VS		 1735/* used in computing the new watermarks state */
1736struct intel_wm_config {
1737 unsigned int num_pipes_active;
1738 bool sprites_enabled;
1739 bool sprites_scaled;
240264f4
VS		 1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
ac830fe1 1746static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 1747 uint32_t mem_value,
1748 bool is_lp)
801bcfff 1749{
cca32e9a
PZ		 1750 uint32_t method1, method2;
1751
c35426d2 1752 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1753 return 0;
1754
23297044 1755 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1756 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1757 mem_value);
1758
1759 if (!is_lp)
1760 return method1;
1761
23297044 1762 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1763 params->pipe_htotal,
c35426d2
VS		 1764 params->pri.horiz_pixels,
1765 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1766 mem_value);
1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
ac830fe1 1775static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 1776 uint32_t mem_value)
1777{
1778 uint32_t method1, method2;
1779
c35426d2 1780 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1781 return 0;
1782
23297044 1783 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1784 params->spr.bytes_per_pixel,
801bcfff 1785 mem_value);
23297044 1786 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1787 params->pipe_htotal,
c35426d2
VS		 1788 params->spr.horiz_pixels,
1789 params->spr.bytes_per_pixel,
801bcfff
PZ		 1790 mem_value);
1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
ac830fe1 1798static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 1799 uint32_t mem_value)
1800{
c35426d2 1801 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1802 return 0;
1803
23297044 1804 return ilk_wm_method2(params->pixel_rate,
801bcfff 1805 params->pipe_htotal,
c35426d2
VS		 1806 params->cur.horiz_pixels,
1807 params->cur.bytes_per_pixel,
801bcfff
PZ		 1808 mem_value);
1809}
1810
cca32e9a 1811/* Only for WM_LP. */
ac830fe1 1812static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 1813 uint32_t pri_val)
cca32e9a 1814{
c35426d2 1815 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1816 return 0;
1817
23297044 1818 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1819 params->pri.horiz_pixels,
1820 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1821}
1822
158ae64f
VS		 1823static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1824{
416f4727
VS		 1825 if (INTEL_INFO(dev)->gen >= 8)
1826 return 3072;
1827 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1828 return 768;
1829 else
1830 return 512;
1831}
1832
1833/* Calculate the maximum primary/sprite plane watermark */
1834static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1835 int level,
240264f4 1836 const struct intel_wm_config *config,
158ae64f
VS		 1837 enum intel_ddb_partitioning ddb_partitioning,
1838 bool is_sprite)
1839{
1840 unsigned int fifo_size = ilk_display_fifo_size(dev);
1841 unsigned int max;
1842
1843 /* if sprites aren't enabled, sprites get nothing */
240264f4 1844 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1845 return 0;
1846
1847 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1848 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1849 fifo_size /= INTEL_INFO(dev)->num_pipes;
1850
1851 /*
1852 * For some reason the non self refresh
1853 * FIFO size is only half of the self
1854 * refresh FIFO size on ILK/SNB.
1855 */
1856 if (INTEL_INFO(dev)->gen <= 6)
1857 fifo_size /= 2;
1858 }
1859
240264f4 1860 if (config->sprites_enabled) {
158ae64f
VS		 1861 /* level 0 is always calculated with 1:1 split */
1862 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1863 if (is_sprite)
1864 fifo_size *= 5;
1865 fifo_size /= 6;
1866 } else {
1867 fifo_size /= 2;
1868 }
1869 }
1870
1871 /* clamp to max that the registers can hold */
416f4727
VS		 1872 if (INTEL_INFO(dev)->gen >= 8)
1873 max = level == 0 ? 255 : 2047;
1874 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1875 /* IVB/HSW primary/sprite plane watermarks */
1876 max = level == 0 ? 127 : 1023;
1877 else if (!is_sprite)
1878 /* ILK/SNB primary plane watermarks */
1879 max = level == 0 ? 127 : 511;
1880 else
1881 /* ILK/SNB sprite plane watermarks */
1882 max = level == 0 ? 63 : 255;
1883
1884 return min(fifo_size, max);
1885}
1886
1887/* Calculate the maximum cursor plane watermark */
1888static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1889 int level,
1890 const struct intel_wm_config *config)
158ae64f
VS		 1891{
1892 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1893 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1894 return 64;
1895
1896 /* otherwise just report max that registers can hold */
1897 if (INTEL_INFO(dev)->gen >= 7)
1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901}
1902
1903/* Calculate the maximum FBC watermark */
416f4727 1904static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 1905{
1906 /* max that registers can hold */
416f4727
VS		 1907 if (INTEL_INFO(dev)->gen >= 8)
1908 return 31;
1909 else
1910 return 15;
158ae64f
VS		 1911}
1912
34982fe1
VS		 1913static void ilk_compute_wm_maximums(struct drm_device *dev,
1914 int level,
1915 const struct intel_wm_config *config,
1916 enum intel_ddb_partitioning ddb_partitioning,
1917 struct hsw_wm_maximums *max)
158ae64f 1918{
240264f4
VS		 1919 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1920 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1921 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 1922 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 1923}
1924
d9395655
VS		 1925static bool ilk_validate_wm_level(int level,
1926 const struct hsw_wm_maximums *max,
1927 struct intel_wm_level *result)
a9786a11
VS		 1928{
1929 bool ret;
1930
1931 /* already determined to be invalid? */
1932 if (!result->enable)
1933 return false;
1934
1935 result->enable = result->pri_val <= max->pri &&
1936 result->spr_val <= max->spr &&
1937 result->cur_val <= max->cur;
1938
1939 ret = result->enable;
1940
1941 /*
1942 * HACK until we can pre-compute everything,
1943 * and thus fail gracefully if LP0 watermarks
1944 * are exceeded...
1945 */
1946 if (level == 0 && !result->enable) {
1947 if (result->pri_val > max->pri)
1948 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1949 level, result->pri_val, max->pri);
1950 if (result->spr_val > max->spr)
1951 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1952 level, result->spr_val, max->spr);
1953 if (result->cur_val > max->cur)
1954 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1955 level, result->cur_val, max->cur);
1956
1957 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1958 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1959 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1960 result->enable = true;
1961 }
1962
a9786a11
VS		 1963 return ret;
1964}
1965
6f5ddd17
VS		 1966static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
1967 int level,
ac830fe1 1968 const struct hsw_pipe_wm_parameters *p,
1fd527cc 1969 struct intel_wm_level *result)
6f5ddd17
VS		 1970{
1971 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1972 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1973 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1974
1975 /* WM1+ latency values stored in 0.5us units */
1976 if (level > 0) {
1977 pri_latency *= 5;
1978 spr_latency *= 5;
1979 cur_latency *= 5;
1980 }
1981
1982 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1983 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1984 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1985 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1986 result->enable = true;
1987}
1988
801bcfff
PZ		 1989static uint32_t
1990hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1991{
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 1994 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 1995 u32 linetime, ips_linetime;
1f8eeabf 1996
801bcfff
PZ		 1997 if (!intel_crtc_active(crtc))
1998 return 0;
1011d8c4 1999
1f8eeabf
ED		 2000 /* The WM are computed with base on how long it takes to fill a single
2001 * row at the given clock rate, multiplied by 8.
2002 * */
85a02deb
PZ		 2003 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2004 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2005 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2006
801bcfff
PZ		 2007 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2008 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2009}
2010
12b134df
VS		 2011static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2012{
2013 struct drm_i915_private *dev_priv = dev->dev_private;
2014
2015 if (IS_HASWELL(dev)) {
2016 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2017
2018 wm[0] = (sskpd >> 56) & 0xFF;
2019 if (wm[0] == 0)
2020 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2021 wm[1] = (sskpd >> 4) & 0xFF;
2022 wm[2] = (sskpd >> 12) & 0xFF;
2023 wm[3] = (sskpd >> 20) & 0x1FF;
2024 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2025 } else if (INTEL_INFO(dev)->gen >= 6) {
2026 uint32_t sskpd = I915_READ(MCH_SSKPD);
2027
2028 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2029 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2030 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2031 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2032 } else if (INTEL_INFO(dev)->gen >= 5) {
2033 uint32_t mltr = I915_READ(MLTR_ILK);
2034
2035 /* ILK primary LP0 latency is 700 ns */
2036 wm[0] = 7;
2037 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2038 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2039 }
2040}
2041
53615a5e
VS		 2042static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2043{
2044 /* ILK sprite LP0 latency is 1300 ns */
2045 if (INTEL_INFO(dev)->gen == 5)
2046 wm[0] = 13;
2047}
2048
2049static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2050{
2051 /* ILK cursor LP0 latency is 1300 ns */
2052 if (INTEL_INFO(dev)->gen == 5)
2053 wm[0] = 13;
2054
2055 /* WaDoubleCursorLP3Latency:ivb */
2056 if (IS_IVYBRIDGE(dev))
2057 wm[3] *= 2;
2058}
2059
ad0d6dc4 2060static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2061{
26ec971e
VS		 2062 /* how many WM levels are we expecting */
2063 if (IS_HASWELL(dev))
ad0d6dc4 2064 return 4;
26ec971e 2065 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2066 return 3;
26ec971e 2067 else
ad0d6dc4
VS		 2068 return 2;
2069}
2070
2071static void intel_print_wm_latency(struct drm_device *dev,
2072 const char *name,
2073 const uint16_t wm[5])
2074{
2075 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2076
2077 for (level = 0; level <= max_level; level++) {
2078 unsigned int latency = wm[level];
2079
2080 if (latency == 0) {
2081 DRM_ERROR("%s WM%d latency not provided\n",
2082 name, level);
2083 continue;
2084 }
2085
2086 /* WM1+ latency values in 0.5us units */
2087 if (level > 0)
2088 latency *= 5;
2089
2090 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2091 name, level, wm[level],
2092 latency / 10, latency % 10);
2093 }
2094}
2095
53615a5e
VS		 2096static void intel_setup_wm_latency(struct drm_device *dev)
2097{
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099
2100 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2101
2102 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2103 sizeof(dev_priv->wm.pri_latency));
2104 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2105 sizeof(dev_priv->wm.pri_latency));
2106
2107 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2108 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2109
2110 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2111 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2112 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2113}
2114
7c4a395f
VS		 2115static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2116 struct hsw_pipe_wm_parameters *p,
a485bfb8 2117 struct intel_wm_config *config)
1011d8c4 2118{
7c4a395f
VS		 2119 struct drm_device *dev = crtc->dev;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2122 struct drm_plane *plane;
1011d8c4 2123
7c4a395f
VS		 2124 p->active = intel_crtc_active(crtc);
2125 if (p->active) {
801bcfff 2126 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2127 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2128 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2129 p->cur.bytes_per_pixel = 4;
37327abd 2130 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2131 p->cur.horiz_pixels = 64;
2132 /* TODO: for now, assume primary and cursor planes are always enabled. */
2133 p->pri.enabled = true;
2134 p->cur.enabled = true;
801bcfff
PZ		 2135 }
2136
7c4a395f 2137 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2138 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2139
801bcfff
PZ		 2140 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2141 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2142
7c4a395f
VS		 2143 if (intel_plane->pipe == pipe)
2144 p->spr = intel_plane->wm;
cca32e9a 2145
a485bfb8
VS		 2146 config->sprites_enabled |= intel_plane->wm.enabled;
2147 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2148 }
801bcfff
PZ		 2149}
2150
0b2ae6d7
VS		 2151/* Compute new watermarks for the pipe */
2152static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2153 const struct hsw_pipe_wm_parameters *params,
2154 struct intel_pipe_wm *pipe_wm)
2155{
2156 struct drm_device *dev = crtc->dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 int level, max_level = ilk_wm_max_level(dev);
2159 /* LP0 watermark maximums depend on this pipe alone */
2160 struct intel_wm_config config = {
2161 .num_pipes_active = 1,
2162 .sprites_enabled = params->spr.enabled,
2163 .sprites_scaled = params->spr.scaled,
2164 };
2165 struct hsw_wm_maximums max;
2166
0b2ae6d7 2167 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2168 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2169
7b39a0b7
VS		 2170 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2171 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2172 max_level = 1;
2173
2174 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2175 if (params->spr.scaled)
2176 max_level = 0;
2177
0b2ae6d7
VS		 2178 for (level = 0; level <= max_level; level++)
2179 ilk_compute_wm_level(dev_priv, level, params,
2180 &pipe_wm->wm[level]);
2181
ce0e0713
VS		 2182 if (IS_HASWELL(dev))
2183 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2184
2185 /* At least LP0 must be valid */
d9395655 2186 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2187}
2188
2189/*
2190 * Merge the watermarks from all active pipes for a specific level.
2191 */
2192static void ilk_merge_wm_level(struct drm_device *dev,
2193 int level,
2194 struct intel_wm_level *ret_wm)
2195{
2196 const struct intel_crtc *intel_crtc;
2197
2198 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2199 const struct intel_wm_level *wm =
2200 &intel_crtc->wm.active.wm[level];
2201
2202 if (!wm->enable)
2203 return;
2204
2205 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2206 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2207 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2208 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2209 }
2210
2211 ret_wm->enable = true;
2212}
2213
2214/*
2215 * Merge all low power watermarks for all active pipes.
2216 */
2217static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2218 const struct intel_wm_config *config,
0b2ae6d7
VS		 2219 const struct hsw_wm_maximums *max,
2220 struct intel_pipe_wm *merged)
2221{
2222 int level, max_level = ilk_wm_max_level(dev);
2223
0ba22e26
VS		 2224 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2225 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2226 config->num_pipes_active > 1)
2227 return;
2228
6c8b6c28
VS		 2229 /* ILK: FBC WM must be disabled always */
2230 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2231
2232 /* merge each WM1+ level */
2233 for (level = 1; level <= max_level; level++) {
2234 struct intel_wm_level *wm = &merged->wm[level];
2235
2236 ilk_merge_wm_level(dev, level, wm);
2237
d9395655 2238 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2239 break;
2240
2241 /*
2242 * The spec says it is preferred to disable
2243 * FBC WMs instead of disabling a WM level.
2244 */
2245 if (wm->fbc_val > max->fbc) {
2246 merged->fbc_wm_enabled = false;
2247 wm->fbc_val = 0;
2248 }
2249 }
6c8b6c28
VS		 2250
2251 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2252 /*
2253 * FIXME this is racy. FBC might get enabled later.
2254 * What we should check here is whether FBC can be
2255 * enabled sometime later.
2256 */
2257 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2258 for (level = 2; level <= max_level; level++) {
2259 struct intel_wm_level *wm = &merged->wm[level];
2260
2261 wm->enable = false;
2262 }
2263 }
0b2ae6d7
VS		 2264}
2265
b380ca3c
VS		 2266static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2267{
2268 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2269 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2270}
2271
a68d68ee
VS		 2272/* The value we need to program into the WM_LPx latency field */
2273static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 if (IS_HASWELL(dev))
2278 return 2 * level;
2279 else
2280 return dev_priv->wm.pri_latency[level];
2281}
2282
801bcfff 2283static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2284 const struct intel_pipe_wm *merged,
609cedef 2285 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2286 struct hsw_wm_values *results)
2287{
0b2ae6d7
VS		 2288 struct intel_crtc *intel_crtc;
2289 int level, wm_lp;
cca32e9a 2290
0362c781 2291 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2292 results->partitioning = partitioning;
cca32e9a 2293
0b2ae6d7 2294 /* LP1+ register values */
cca32e9a 2295 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2296 const struct intel_wm_level *r;
801bcfff 2297
b380ca3c 2298 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2299
0362c781 2300 r = &merged->wm[level];
0b2ae6d7 2301 if (!r->enable)
cca32e9a
PZ		 2302 break;
2303
416f4727 2304 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2305 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2306 (r->pri_val << WM1_LP_SR_SHIFT) |
2307 r->cur_val;
2308
2309 if (INTEL_INFO(dev)->gen >= 8)
2310 results->wm_lp[wm_lp - 1] |=
2311 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2312 else
2313 results->wm_lp[wm_lp - 1] |=
2314 r->fbc_val << WM1_LP_FBC_SHIFT;
2315
6cef2b8a
VS		 2316 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2317 WARN_ON(wm_lp != 1);
2318 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2319 } else
2320 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2321 }
801bcfff 2322
0b2ae6d7
VS		 2323 /* LP0 register values */
2324 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2325 enum pipe pipe = intel_crtc->pipe;
2326 const struct intel_wm_level *r =
2327 &intel_crtc->wm.active.wm[0];
2328
2329 if (WARN_ON(!r->enable))
2330 continue;
2331
2332 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2333
0b2ae6d7
VS		 2334 results->wm_pipe[pipe] =
2335 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2336 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2337 r->cur_val;
801bcfff
PZ		 2338 }
2339}
2340
861f3389
PZ		 2341/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2342 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2343static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2344 struct intel_pipe_wm *r1,
2345 struct intel_pipe_wm *r2)
861f3389 2346{
198a1e9b
VS		 2347 int level, max_level = ilk_wm_max_level(dev);
2348 int level1 = 0, level2 = 0;
861f3389 2349
198a1e9b
VS		 2350 for (level = 1; level <= max_level; level++) {
2351 if (r1->wm[level].enable)
2352 level1 = level;
2353 if (r2->wm[level].enable)
2354 level2 = level;
861f3389
PZ		 2355 }
2356
198a1e9b
VS		 2357 if (level1 == level2) {
2358 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2359 return r2;
2360 else
2361 return r1;
198a1e9b 2362 } else if (level1 > level2) {
861f3389
PZ		 2363 return r1;
2364 } else {
2365 return r2;
2366 }
2367}
2368
49a687c4
VS		 2369/* dirty bits used to track which watermarks need changes */
2370#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2371#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2372#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2373#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2374#define WM_DIRTY_FBC (1 << 24)
2375#define WM_DIRTY_DDB (1 << 25)
2376
2377static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2378 const struct hsw_wm_values *old,
2379 const struct hsw_wm_values *new)
2380{
2381 unsigned int dirty = 0;
2382 enum pipe pipe;
2383 int wm_lp;
2384
2385 for_each_pipe(pipe) {
2386 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2387 dirty |= WM_DIRTY_LINETIME(pipe);
2388 /* Must disable LP1+ watermarks too */
2389 dirty |= WM_DIRTY_LP_ALL;
2390 }
2391
2392 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2393 dirty |= WM_DIRTY_PIPE(pipe);
2394 /* Must disable LP1+ watermarks too */
2395 dirty |= WM_DIRTY_LP_ALL;
2396 }
2397 }
2398
2399 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2400 dirty |= WM_DIRTY_FBC;
2401 /* Must disable LP1+ watermarks too */
2402 dirty |= WM_DIRTY_LP_ALL;
2403 }
2404
2405 if (old->partitioning != new->partitioning) {
2406 dirty |= WM_DIRTY_DDB;
2407 /* Must disable LP1+ watermarks too */
2408 dirty |= WM_DIRTY_LP_ALL;
2409 }
2410
2411 /* LP1+ watermarks already deemed dirty, no need to continue */
2412 if (dirty & WM_DIRTY_LP_ALL)
2413 return dirty;
2414
2415 /* Find the lowest numbered LP1+ watermark in need of an update... */
2416 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2417 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2418 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2419 break;
2420 }
2421
2422 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2423 for (; wm_lp <= 3; wm_lp++)
2424 dirty |= WM_DIRTY_LP(wm_lp);
2425
2426 return dirty;
2427}
2428
8553c18e
VS		 2429static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2430 unsigned int dirty)
801bcfff 2431{
243e6a44 2432 struct hsw_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2433 bool changed = false;
801bcfff 2434
facd619b
VS		 2435 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2436 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2437 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2438 changed = true;
facd619b
VS		 2439 }
2440 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2441 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2442 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2443 changed = true;
facd619b
VS		 2444 }
2445 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2446 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2447 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2448 changed = true;
facd619b 2449 }
801bcfff 2450
facd619b
VS		 2451 /*
2452 * Don't touch WM1S_LP_EN here.
2453 * Doing so could cause underruns.
2454 */
6cef2b8a 2455
8553c18e
VS		 2456 return changed;
2457}
2458
2459/*
2460 * The spec says we shouldn't write when we don't need, because every write
2461 * causes WMs to be re-evaluated, expending some power.
2462 */
2463static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2464 struct hsw_wm_values *results)
2465{
2466 struct drm_device *dev = dev_priv->dev;
2467 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2468 unsigned int dirty;
2469 uint32_t val;
2470
2471 dirty = ilk_compute_wm_dirty(dev, previous, results);
2472 if (!dirty)
2473 return;
2474
2475 _ilk_disable_lp_wm(dev_priv, dirty);
2476
49a687c4 2477 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2478 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2479 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2480 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2481 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2482 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2483
49a687c4 2484 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2485 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2486 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2487 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2488 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2489 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2490
49a687c4 2491 if (dirty & WM_DIRTY_DDB) {
ac9545fd
VS		 2492 if (IS_HASWELL(dev)) {
2493 val = I915_READ(WM_MISC);
2494 if (results->partitioning == INTEL_DDB_PART_1_2)
2495 val &= ~WM_MISC_DATA_PARTITION_5_6;
2496 else
2497 val |= WM_MISC_DATA_PARTITION_5_6;
2498 I915_WRITE(WM_MISC, val);
2499 } else {
2500 val = I915_READ(DISP_ARB_CTL2);
2501 if (results->partitioning == INTEL_DDB_PART_1_2)
2502 val &= ~DISP_DATA_PARTITION_5_6;
2503 else
2504 val |= DISP_DATA_PARTITION_5_6;
2505 I915_WRITE(DISP_ARB_CTL2, val);
2506 }
1011d8c4
PZ		 2507 }
2508
49a687c4 2509 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2510 val = I915_READ(DISP_ARB_CTL);
2511 if (results->enable_fbc_wm)
2512 val &= ~DISP_FBC_WM_DIS;
2513 else
2514 val |= DISP_FBC_WM_DIS;
2515 I915_WRITE(DISP_ARB_CTL, val);
2516 }
2517
954911eb
ID		 2518 if (dirty & WM_DIRTY_LP(1) &&
2519 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2520 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2521
2522 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2523 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2524 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2525 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2526 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2527 }
801bcfff 2528
facd619b 2529 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2530 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2531 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2532 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2533 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2534 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2535
2536 dev_priv->wm.hw = *results;
801bcfff
PZ		 2537}
2538
8553c18e
VS		 2539static bool ilk_disable_lp_wm(struct drm_device *dev)
2540{
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542
2543 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2544}
2545
46ba614c 2546static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2547{
7c4a395f 2548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2549 struct drm_device *dev = crtc->dev;
801bcfff 2550 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2551 struct hsw_wm_maximums max;
7c4a395f 2552 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2553 struct hsw_wm_values results = {};
77c122bc 2554 enum intel_ddb_partitioning partitioning;
7c4a395f 2555 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2556 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2557 struct intel_wm_config config = {};
7c4a395f 2558
a485bfb8 2559 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2560
2561 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2562
2563 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2564 return;
861f3389 2565
7c4a395f 2566 intel_crtc->wm.active = pipe_wm;
861f3389 2567
34982fe1 2568 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2569 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2570
2571 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2572 if (INTEL_INFO(dev)->gen >= 7 &&
2573 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2574 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2575 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2576
198a1e9b 2577 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2578 } else {
198a1e9b 2579 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2580 }
2581
198a1e9b 2582 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2583 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2584
609cedef
VS		 2585 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2586
2587 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2588}
2589
adf3d35e
VS		 2590static void haswell_update_sprite_wm(struct drm_plane *plane,
2591 struct drm_crtc *crtc,
526682e9 2592 uint32_t sprite_width, int pixel_size,
bdd57d03 2593 bool enabled, bool scaled)
526682e9 2594{
8553c18e 2595 struct drm_device *dev = plane->dev;
adf3d35e 2596 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2597
adf3d35e
VS		 2598 intel_plane->wm.enabled = enabled;
2599 intel_plane->wm.scaled = scaled;
2600 intel_plane->wm.horiz_pixels = sprite_width;
2601 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2602
8553c18e
VS		 2603 /*
2604 * IVB workaround: must disable low power watermarks for at least
2605 * one frame before enabling scaling. LP watermarks can be re-enabled
2606 * when scaling is disabled.
2607 *
2608 * WaCxSRDisabledForSpriteScaling:ivb
2609 */
2610 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2611 intel_wait_for_vblank(dev, intel_plane->pipe);
2612
46ba614c 2613 haswell_update_wm(crtc);
526682e9
PZ		 2614}
2615
243e6a44
VS		 2616static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2617{
2618 struct drm_device *dev = crtc->dev;
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 struct hsw_wm_values *hw = &dev_priv->wm.hw;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2623 enum pipe pipe = intel_crtc->pipe;
2624 static const unsigned int wm0_pipe_reg[] = {
2625 [PIPE_A] = WM0_PIPEA_ILK,
2626 [PIPE_B] = WM0_PIPEB_ILK,
2627 [PIPE_C] = WM0_PIPEC_IVB,
2628 };
2629
2630 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
ce0e0713
VS		 2631 if (IS_HASWELL(dev))
2632 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44
VS		 2633
2634 if (intel_crtc_active(crtc)) {
2635 u32 tmp = hw->wm_pipe[pipe];
2636
2637 /*
2638 * For active pipes LP0 watermark is marked as
2639 * enabled, and LP1+ watermaks as disabled since
2640 * we can't really reverse compute them in case
2641 * multiple pipes are active.
2642 */
2643 active->wm[0].enable = true;
2644 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2645 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2646 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2647 active->linetime = hw->wm_linetime[pipe];
2648 } else {
2649 int level, max_level = ilk_wm_max_level(dev);
2650
2651 /*
2652 * For inactive pipes, all watermark levels
2653 * should be marked as enabled but zeroed,
2654 * which is what we'd compute them to.
2655 */
2656 for (level = 0; level <= max_level; level++)
2657 active->wm[level].enable = true;
2658 }
2659}
2660
2661void ilk_wm_get_hw_state(struct drm_device *dev)
2662{
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct hsw_wm_values *hw = &dev_priv->wm.hw;
2665 struct drm_crtc *crtc;
2666
2667 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2668 ilk_pipe_wm_get_hw_state(crtc);
2669
2670 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2671 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2672 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2673
2674 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2675 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2676 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2677
ac9545fd
VS		 2678 if (IS_HASWELL(dev))
2679 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2680 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2681 else if (IS_IVYBRIDGE(dev))
2682 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2683 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2684
2685 hw->enable_fbc_wm =
2686 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2687}
2688
b445e3b0
ED		 2689/**
2690 * intel_update_watermarks - update FIFO watermark values based on current modes
2691 *
2692 * Calculate watermark values for the various WM regs based on current mode
2693 * and plane configuration.
2694 *
2695 * There are several cases to deal with here:
2696 * - normal (i.e. non-self-refresh)
2697 * - self-refresh (SR) mode
2698 * - lines are large relative to FIFO size (buffer can hold up to 2)
2699 * - lines are small relative to FIFO size (buffer can hold more than 2
2700 * lines), so need to account for TLB latency
2701 *
2702 * The normal calculation is:
2703 * watermark = dotclock * bytes per pixel * latency
2704 * where latency is platform & configuration dependent (we assume pessimal
2705 * values here).
2706 *
2707 * The SR calculation is:
2708 * watermark = (trunc(latency/line time)+1) * surface width *
2709 * bytes per pixel
2710 * where
2711 * line time = htotal / dotclock
2712 * surface width = hdisplay for normal plane and 64 for cursor
2713 * and latency is assumed to be high, as above.
2714 *
2715 * The final value programmed to the register should always be rounded up,
2716 * and include an extra 2 entries to account for clock crossings.
2717 *
2718 * We don't use the sprite, so we can ignore that. And on Crestline we have
2719 * to set the non-SR watermarks to 8.
2720 */
46ba614c 2721void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2722{
46ba614c 2723 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2724
2725 if (dev_priv->display.update_wm)
46ba614c 2726 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2727}
2728
adf3d35e
VS		 2729void intel_update_sprite_watermarks(struct drm_plane *plane,
2730 struct drm_crtc *crtc,
4c4ff43a 2731 uint32_t sprite_width, int pixel_size,
39db4a4d 2732 bool enabled, bool scaled)
b445e3b0 2733{
adf3d35e 2734 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2735
2736 if (dev_priv->display.update_sprite_wm)
adf3d35e 2737 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2738 pixel_size, enabled, scaled);
b445e3b0
ED		 2739}
2740
2b4e57bd
ED		 2741static struct drm_i915_gem_object *
2742intel_alloc_context_page(struct drm_device *dev)
2743{
2744 struct drm_i915_gem_object *ctx;
2745 int ret;
2746
2747 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2748
2749 ctx = i915_gem_alloc_object(dev, 4096);
2750 if (!ctx) {
2751 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2752 return NULL;
2753 }
2754
c37e2204 2755 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2756 if (ret) {
2757 DRM_ERROR("failed to pin power context: %d\n", ret);
2758 goto err_unref;
2759 }
2760
2761 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2762 if (ret) {
2763 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2764 goto err_unpin;
2765 }
2766
2767 return ctx;
2768
2769err_unpin:
2770 i915_gem_object_unpin(ctx);
2771err_unref:
2772 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2773 return NULL;
2774}
2775
9270388e
DV		 2776/**
2777 * Lock protecting IPS related data structures
9270388e
DV		 2778 */
2779DEFINE_SPINLOCK(mchdev_lock);
2780
2781/* Global for IPS driver to get at the current i915 device. Protected by
2782 * mchdev_lock. */
2783static struct drm_i915_private *i915_mch_dev;
2784
2b4e57bd
ED		 2785bool ironlake_set_drps(struct drm_device *dev, u8 val)
2786{
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u16 rgvswctl;
2789
9270388e
DV		 2790 assert_spin_locked(&mchdev_lock);
2791
2b4e57bd
ED		 2792 rgvswctl = I915_READ16(MEMSWCTL);
2793 if (rgvswctl & MEMCTL_CMD_STS) {
2794 DRM_DEBUG("gpu busy, RCS change rejected\n");
2795 return false; /* still busy with another command */
2796 }
2797
2798 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2799 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2800 I915_WRITE16(MEMSWCTL, rgvswctl);
2801 POSTING_READ16(MEMSWCTL);
2802
2803 rgvswctl |= MEMCTL_CMD_STS;
2804 I915_WRITE16(MEMSWCTL, rgvswctl);
2805
2806 return true;
2807}
2808
8090c6b9 2809static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2810{
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 u32 rgvmodectl = I915_READ(MEMMODECTL);
2813 u8 fmax, fmin, fstart, vstart;
2814
9270388e
DV		 2815 spin_lock_irq(&mchdev_lock);
2816
2b4e57bd
ED		 2817 /* Enable temp reporting */
2818 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2819 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2820
2821 /* 100ms RC evaluation intervals */
2822 I915_WRITE(RCUPEI, 100000);
2823 I915_WRITE(RCDNEI, 100000);
2824
2825 /* Set max/min thresholds to 90ms and 80ms respectively */
2826 I915_WRITE(RCBMAXAVG, 90000);
2827 I915_WRITE(RCBMINAVG, 80000);
2828
2829 I915_WRITE(MEMIHYST, 1);
2830
2831 /* Set up min, max, and cur for interrupt handling */
2832 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2833 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2834 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2835 MEMMODE_FSTART_SHIFT;
2836
2837 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2838 PXVFREQ_PX_SHIFT;
2839
20e4d407
DV		 2840 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2841 dev_priv->ips.fstart = fstart;
2b4e57bd 2842
20e4d407
DV		 2843 dev_priv->ips.max_delay = fstart;
2844 dev_priv->ips.min_delay = fmin;
2845 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2846
2847 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2848 fmax, fmin, fstart);
2849
2850 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2851
2852 /*
2853 * Interrupts will be enabled in ironlake_irq_postinstall
2854 */
2855
2856 I915_WRITE(VIDSTART, vstart);
2857 POSTING_READ(VIDSTART);
2858
2859 rgvmodectl |= MEMMODE_SWMODE_EN;
2860 I915_WRITE(MEMMODECTL, rgvmodectl);
2861
9270388e 2862 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2863 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2864 mdelay(1);
2b4e57bd
ED		 2865
2866 ironlake_set_drps(dev, fstart);
2867
20e4d407 2868 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2869 I915_READ(0x112e0);
20e4d407
DV		 2870 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2871 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2872 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2873
2874 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2875}
2876
8090c6b9 2877static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2878{
2879 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2880 u16 rgvswctl;
2881
2882 spin_lock_irq(&mchdev_lock);
2883
2884 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2885
2886 /* Ack interrupts, disable EFC interrupt */
2887 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2888 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2889 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2890 I915_WRITE(DEIIR, DE_PCU_EVENT);
2891 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2892
2893 /* Go back to the starting frequency */
20e4d407 2894 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2895 mdelay(1);
2b4e57bd
ED		 2896 rgvswctl |= MEMCTL_CMD_STS;
2897 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2898 mdelay(1);
2b4e57bd 2899
9270388e 2900 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2901}
2902
acbe9475
DV		 2903/* There's a funny hw issue where the hw returns all 0 when reading from
2904 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2905 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2906 * all limits and the gpu stuck at whatever frequency it is at atm).
2907 */
6917c7b9 2908static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2909{
7b9e0ae6 2910 u32 limits;
2b4e57bd 2911
20b46e59
DV		 2912 /* Only set the down limit when we've reached the lowest level to avoid
2913 * getting more interrupts, otherwise leave this clear. This prevents a
2914 * race in the hw when coming out of rc6: There's a tiny window where
2915 * the hw runs at the minimal clock before selecting the desired
2916 * frequency, if the down threshold expires in that window we will not
2917 * receive a down interrupt. */
6917c7b9
CW		 2918 limits = dev_priv->rps.max_delay << 24;
2919 if (val <= dev_priv->rps.min_delay)
c6a828d3 2920 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2921
2922 return limits;
2923}
2924
dd75fdc8
CW		 2925static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2926{
2927 int new_power;
2928
2929 new_power = dev_priv->rps.power;
2930 switch (dev_priv->rps.power) {
2931 case LOW_POWER:
2932 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2933 new_power = BETWEEN;
2934 break;
2935
2936 case BETWEEN:
2937 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2938 new_power = LOW_POWER;
2939 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2940 new_power = HIGH_POWER;
2941 break;
2942
2943 case HIGH_POWER:
2944 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2945 new_power = BETWEEN;
2946 break;
2947 }
2948 /* Max/min bins are special */
2949 if (val == dev_priv->rps.min_delay)
2950 new_power = LOW_POWER;
2951 if (val == dev_priv->rps.max_delay)
2952 new_power = HIGH_POWER;
2953 if (new_power == dev_priv->rps.power)
2954 return;
2955
2956 /* Note the units here are not exactly 1us, but 1280ns. */
2957 switch (new_power) {
2958 case LOW_POWER:
2959 /* Upclock if more than 95% busy over 16ms */
2960 I915_WRITE(GEN6_RP_UP_EI, 12500);
2961 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2962
2963 /* Downclock if less than 85% busy over 32ms */
2964 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2965 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2966
2967 I915_WRITE(GEN6_RP_CONTROL,
2968 GEN6_RP_MEDIA_TURBO |
2969 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2970 GEN6_RP_MEDIA_IS_GFX |
2971 GEN6_RP_ENABLE |
2972 GEN6_RP_UP_BUSY_AVG |
2973 GEN6_RP_DOWN_IDLE_AVG);
2974 break;
2975
2976 case BETWEEN:
2977 /* Upclock if more than 90% busy over 13ms */
2978 I915_WRITE(GEN6_RP_UP_EI, 10250);
2979 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2980
2981 /* Downclock if less than 75% busy over 32ms */
2982 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2983 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2984
2985 I915_WRITE(GEN6_RP_CONTROL,
2986 GEN6_RP_MEDIA_TURBO |
2987 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2988 GEN6_RP_MEDIA_IS_GFX |
2989 GEN6_RP_ENABLE |
2990 GEN6_RP_UP_BUSY_AVG |
2991 GEN6_RP_DOWN_IDLE_AVG);
2992 break;
2993
2994 case HIGH_POWER:
2995 /* Upclock if more than 85% busy over 10ms */
2996 I915_WRITE(GEN6_RP_UP_EI, 8000);
2997 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2998
2999 /* Downclock if less than 60% busy over 32ms */
3000 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3001 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3002
3003 I915_WRITE(GEN6_RP_CONTROL,
3004 GEN6_RP_MEDIA_TURBO |
3005 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3006 GEN6_RP_MEDIA_IS_GFX |
3007 GEN6_RP_ENABLE |
3008 GEN6_RP_UP_BUSY_AVG |
3009 GEN6_RP_DOWN_IDLE_AVG);
3010 break;
3011 }
3012
3013 dev_priv->rps.power = new_power;
3014 dev_priv->rps.last_adj = 0;
3015}
3016
20b46e59
DV		 3017void gen6_set_rps(struct drm_device *dev, u8 val)
3018{
3019 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3020
4fc688ce 3021 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3022 WARN_ON(val > dev_priv->rps.max_delay);
3023 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3024
c6a828d3 3025 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3026 return;
3027
dd75fdc8
CW		 3028 gen6_set_rps_thresholds(dev_priv, val);
3029
92bd1bf0
RV		 3030 if (IS_HASWELL(dev))
3031 I915_WRITE(GEN6_RPNSWREQ,
3032 HSW_FREQUENCY(val));
3033 else
3034 I915_WRITE(GEN6_RPNSWREQ,
3035 GEN6_FREQUENCY(val) |
3036 GEN6_OFFSET(0) |
3037 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3038
3039 /* Make sure we continue to get interrupts
3040 * until we hit the minimum or maximum frequencies.
3041 */
6917c7b9
CW		 3042 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3043 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3044
d5570a72
BW		 3045 POSTING_READ(GEN6_RPNSWREQ);
3046
c6a828d3 3047 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3048
3049 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3050}
3051
b29c19b6
CW		 3052void gen6_rps_idle(struct drm_i915_private *dev_priv)
3053{
691bb717
DL		 3054 struct drm_device *dev = dev_priv->dev;
3055
b29c19b6 3056 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3057 if (dev_priv->rps.enabled) {
691bb717 3058 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3059 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3060 else
3061 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3062 dev_priv->rps.last_adj = 0;
3063 }
b29c19b6
CW		 3064 mutex_unlock(&dev_priv->rps.hw_lock);
3065}
3066
3067void gen6_rps_boost(struct drm_i915_private *dev_priv)
3068{
691bb717
DL		 3069 struct drm_device *dev = dev_priv->dev;
3070
b29c19b6 3071 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3072 if (dev_priv->rps.enabled) {
691bb717 3073 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3074 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3075 else
3076 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3077 dev_priv->rps.last_adj = 0;
3078 }
b29c19b6
CW		 3079 mutex_unlock(&dev_priv->rps.hw_lock);
3080}
3081
0a073b84
JB		 3082void valleyview_set_rps(struct drm_device *dev, u8 val)
3083{
3084 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3085
0a073b84
JB		 3086 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3087 WARN_ON(val > dev_priv->rps.max_delay);
3088 WARN_ON(val < dev_priv->rps.min_delay);
3089
73008b98 3090 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3091 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3092 dev_priv->rps.cur_delay,
2ec3815f 3093 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3094
3095 if (val == dev_priv->rps.cur_delay)
3096 return;
3097
ae99258f 3098 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3099
80814ae4 3100 dev_priv->rps.cur_delay = val;
0a073b84 3101
2ec3815f 3102 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3103}
3104
44fc7d5c 3105static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3106{
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108
2b4e57bd 3109 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3110 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3111 /* Complete PM interrupt masking here doesn't race with the rps work
3112 * item again unmasking PM interrupts because that is using a different
3113 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3114 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3115
59cdb63d 3116 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3117 dev_priv->rps.pm_iir = 0;
59cdb63d 3118 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3119
4848405c 3120 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3121}
3122
44fc7d5c 3123static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3124{
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126
3127 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3128 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3129
44fc7d5c
DV		 3130 gen6_disable_rps_interrupts(dev);
3131}
3132
3133static void valleyview_disable_rps(struct drm_device *dev)
3134{
3135 struct drm_i915_private *dev_priv = dev->dev_private;
3136
3137 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3138
44fc7d5c 3139 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3140
3141 if (dev_priv->vlv_pctx) {
3142 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3143 dev_priv->vlv_pctx = NULL;
3144 }
d20d4f0c
JB		 3145}
3146
dc39fff7
BW		 3147static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3148{
3149 if (IS_GEN6(dev))
3150 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3151
3152 if (IS_HASWELL(dev))
3153 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3154
3155 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3156 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3157 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3158 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3159}
3160
2b4e57bd
ED		 3161int intel_enable_rc6(const struct drm_device *dev)
3162{
eb4926e4
DL		 3163 /* No RC6 before Ironlake */
3164 if (INTEL_INFO(dev)->gen < 5)
3165 return 0;
3166
456470eb 3167 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3168 if (i915_enable_rc6 >= 0)
3169 return i915_enable_rc6;
3170
6567d748
CW		 3171 /* Disable RC6 on Ironlake */
3172 if (INTEL_INFO(dev)->gen == 5)
3173 return 0;
2b4e57bd 3174
dc39fff7 3175 if (IS_HASWELL(dev))
4a637c2c 3176 return INTEL_RC6_ENABLE;
2b4e57bd 3177
456470eb 3178 /* snb/ivb have more than one rc6 state. */
dc39fff7 3179 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3180 return INTEL_RC6_ENABLE;
456470eb 3181
2b4e57bd
ED		 3182 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3183}
3184
44fc7d5c
DV		 3185static void gen6_enable_rps_interrupts(struct drm_device *dev)
3186{
3187 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3188 u32 enabled_intrs;
44fc7d5c
DV		 3189
3190 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3191 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3192 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3193 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3194 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3195
fd547d25 3196 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3197 enabled_intrs = GEN6_PM_RPS_EVENTS;
3198
3199 /* IVB and SNB hard hangs on looping batchbuffer
3200 * if GEN6_PM_UP_EI_EXPIRED is masked.
3201 */
3202 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3203 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3204
3205 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3206}
3207
6edee7f3
BW		 3208static void gen8_enable_rps(struct drm_device *dev)
3209{
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_ring_buffer *ring;
3212 uint32_t rc6_mask = 0, rp_state_cap;
3213 int unused;
3214
3215 /* 1a: Software RC state - RC0 */
3216 I915_WRITE(GEN6_RC_STATE, 0);
3217
3218 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3219 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3220 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3221
3222 /* 2a: Disable RC states. */
3223 I915_WRITE(GEN6_RC_CONTROL, 0);
3224
3225 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3226
3227 /* 2b: Program RC6 thresholds.*/
3228 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3229 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3230 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3231 for_each_ring(ring, dev_priv, unused)
3232 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3233 I915_WRITE(GEN6_RC_SLEEP, 0);
3234 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3235
3236 /* 3: Enable RC6 */
3237 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3238 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3239 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3240 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3241 GEN6_RC_CTL_EI_MODE(1) |
3242 rc6_mask);
3243
3244 /* 4 Program defaults and thresholds for RPS*/
3245 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3246 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3247 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3248 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3249
3250 /* Docs recommend 900MHz, and 300 MHz respectively */
3251 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3252 dev_priv->rps.max_delay << 24 |
3253 dev_priv->rps.min_delay << 16);
3254
3255 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3256 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3257 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3258 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3259
3260 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3261
3262 /* 5: Enable RPS */
3263 I915_WRITE(GEN6_RP_CONTROL,
3264 GEN6_RP_MEDIA_TURBO |
3265 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3266 GEN6_RP_MEDIA_IS_GFX |
3267 GEN6_RP_ENABLE |
3268 GEN6_RP_UP_BUSY_AVG |
3269 GEN6_RP_DOWN_IDLE_AVG);
3270
3271 /* 6: Ring frequency + overclocking (our driver does this later */
3272
3273 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3274
3275 gen6_enable_rps_interrupts(dev);
3276
c8d9a590 3277 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3278}
3279
79f5b2c7 3280static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3281{
79f5b2c7 3282 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3283 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3284 u32 rp_state_cap;
3285 u32 gt_perf_status;
31643d54 3286 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3287 u32 gtfifodbg;
2b4e57bd 3288 int rc6_mode;
42c0526c 3289 int i, ret;
2b4e57bd 3290
4fc688ce 3291 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3292
2b4e57bd
ED		 3293 /* Here begins a magic sequence of register writes to enable
3294 * auto-downclocking.
3295 *
3296 * Perhaps there might be some value in exposing these to
3297 * userspace...
3298 */
3299 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3300
3301 /* Clear the DBG now so we don't confuse earlier errors */
3302 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3303 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3304 I915_WRITE(GTFIFODBG, gtfifodbg);
3305 }
3306
c8d9a590 3307 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3308
7b9e0ae6
CW		 3309 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3310 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3311
31c77388
BW		 3312 /* In units of 50MHz */
3313 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3314 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3315 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3316 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3317 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3318 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3319
2b4e57bd
ED		 3320 /* disable the counters and set deterministic thresholds */
3321 I915_WRITE(GEN6_RC_CONTROL, 0);
3322
3323 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3324 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3325 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3326 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3327 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3328
b4519513
CW		 3329 for_each_ring(ring, dev_priv, i)
3330 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3331
3332 I915_WRITE(GEN6_RC_SLEEP, 0);
3333 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3334 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3335 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3336 else
3337 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3338 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3339 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3340
5a7dc92a 3341 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3342 rc6_mode = intel_enable_rc6(dev_priv->dev);
3343 if (rc6_mode & INTEL_RC6_ENABLE)
3344 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3345
5a7dc92a
ED		 3346 /* We don't use those on Haswell */
3347 if (!IS_HASWELL(dev)) {
3348 if (rc6_mode & INTEL_RC6p_ENABLE)
3349 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3350
5a7dc92a
ED		 3351 if (rc6_mode & INTEL_RC6pp_ENABLE)
3352 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3353 }
2b4e57bd 3354
dc39fff7 3355 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3356
3357 I915_WRITE(GEN6_RC_CONTROL,
3358 rc6_mask |
3359 GEN6_RC_CTL_EI_MODE(1) |
3360 GEN6_RC_CTL_HW_ENABLE);
3361
dd75fdc8
CW		 3362 /* Power down if completely idle for over 50ms */
3363 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3364 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3365
42c0526c 3366 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3367 if (!ret) {
42c0526c
BW		 3368 pcu_mbox = 0;
3369 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3370 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3371 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3372 (dev_priv->rps.max_delay & 0xff) * 50,
3373 (pcu_mbox & 0xff) * 50);
31c77388 3374 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3375 }
3376 } else {
3377 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3378 }
3379
dd75fdc8
CW		 3380 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3381 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3382
44fc7d5c 3383 gen6_enable_rps_interrupts(dev);
2b4e57bd 3384
31643d54
BW		 3385 rc6vids = 0;
3386 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3387 if (IS_GEN6(dev) && ret) {
3388 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3389 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3390 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3391 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3392 rc6vids &= 0xffff00;
3393 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3394 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3395 if (ret)
3396 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3397 }
3398
c8d9a590 3399 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3400}
3401
c67a470b 3402void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3403{
79f5b2c7 3404 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3405 int min_freq = 15;
3ebecd07
CW		 3406 unsigned int gpu_freq;
3407 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3408 int scaling_factor = 180;
eda79642 3409 struct cpufreq_policy *policy;
2b4e57bd 3410
4fc688ce 3411 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3412
eda79642
BW		 3413 policy = cpufreq_cpu_get(0);
3414 if (policy) {
3415 max_ia_freq = policy->cpuinfo.max_freq;
3416 cpufreq_cpu_put(policy);
3417 } else {
3418 /*
3419 * Default to measured freq if none found, PCU will ensure we
3420 * don't go over
3421 */
2b4e57bd 3422 max_ia_freq = tsc_khz;
eda79642 3423 }
2b4e57bd
ED		 3424
3425 /* Convert from kHz to MHz */
3426 max_ia_freq /= 1000;
3427
153b4b95 3428 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3429 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3430 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3431
2b4e57bd
ED		 3432 /*
3433 * For each potential GPU frequency, load a ring frequency we'd like
3434 * to use for memory access. We do this by specifying the IA frequency
3435 * the PCU should use as a reference to determine the ring frequency.
3436 */
c6a828d3 3437 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3438 gpu_freq--) {
c6a828d3 3439 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3440 unsigned int ia_freq = 0, ring_freq = 0;
3441
46c764d4
BW		 3442 if (INTEL_INFO(dev)->gen >= 8) {
3443 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3444 ring_freq = max(min_ring_freq, gpu_freq);
3445 } else if (IS_HASWELL(dev)) {
f6aca45c 3446 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3447 ring_freq = max(min_ring_freq, ring_freq);
3448 /* leave ia_freq as the default, chosen by cpufreq */
3449 } else {
3450 /* On older processors, there is no separate ring
3451 * clock domain, so in order to boost the bandwidth
3452 * of the ring, we need to upclock the CPU (ia_freq).
3453 *
3454 * For GPU frequencies less than 750MHz,
3455 * just use the lowest ring freq.
3456 */
3457 if (gpu_freq < min_freq)
3458 ia_freq = 800;
3459 else
3460 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3461 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3462 }
2b4e57bd 3463
42c0526c
BW		 3464 sandybridge_pcode_write(dev_priv,
3465 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3466 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3467 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3468 gpu_freq);
2b4e57bd 3469 }
2b4e57bd
ED		 3470}
3471
0a073b84
JB		 3472int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3473{
3474 u32 val, rp0;
3475
64936258 3476 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3477
3478 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3479 /* Clamp to max */
3480 rp0 = min_t(u32, rp0, 0xea);
3481
3482 return rp0;
3483}
3484
3485static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3486{
3487 u32 val, rpe;
3488
64936258 3489 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3490 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3491 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3492 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3493
3494 return rpe;
3495}
3496
3497int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3498{
64936258 3499 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3500}
3501
c9cddffc
JB		 3502static void valleyview_setup_pctx(struct drm_device *dev)
3503{
3504 struct drm_i915_private *dev_priv = dev->dev_private;
3505 struct drm_i915_gem_object *pctx;
3506 unsigned long pctx_paddr;
3507 u32 pcbr;
3508 int pctx_size = 24*1024;
3509
3510 pcbr = I915_READ(VLV_PCBR);
3511 if (pcbr) {
3512 /* BIOS set it up already, grab the pre-alloc'd space */
3513 int pcbr_offset;
3514
3515 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3516 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3517 pcbr_offset,
190d6cd5 3518 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3519 pctx_size);
3520 goto out;
3521 }
3522
3523 /*
3524 * From the Gunit register HAS:
3525 * The Gfx driver is expected to program this register and ensure
3526 * proper allocation within Gfx stolen memory. For example, this
3527 * register should be programmed such than the PCBR range does not
3528 * overlap with other ranges, such as the frame buffer, protected
3529 * memory, or any other relevant ranges.
3530 */
3531 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3532 if (!pctx) {
3533 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3534 return;
3535 }
3536
3537 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3538 I915_WRITE(VLV_PCBR, pctx_paddr);
3539
3540out:
3541 dev_priv->vlv_pctx = pctx;
3542}
3543
0a073b84
JB		 3544static void valleyview_enable_rps(struct drm_device *dev)
3545{
3546 struct drm_i915_private *dev_priv = dev->dev_private;
3547 struct intel_ring_buffer *ring;
a2b23fe0 3548 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3549 int i;
3550
3551 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3552
3553 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3554 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3555 gtfifodbg);
0a073b84
JB		 3556 I915_WRITE(GTFIFODBG, gtfifodbg);
3557 }
3558
c9cddffc
JB		 3559 valleyview_setup_pctx(dev);
3560
c8d9a590
D		 3561 /* If VLV, Forcewake all wells, else re-direct to regular path */
3562 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3563
3564 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3565 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3566 I915_WRITE(GEN6_RP_UP_EI, 66000);
3567 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3568
3569 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3570
3571 I915_WRITE(GEN6_RP_CONTROL,
3572 GEN6_RP_MEDIA_TURBO |
3573 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3574 GEN6_RP_MEDIA_IS_GFX |
3575 GEN6_RP_ENABLE |
3576 GEN6_RP_UP_BUSY_AVG |
3577 GEN6_RP_DOWN_IDLE_CONT);
3578
3579 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3580 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3581 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3582
3583 for_each_ring(ring, dev_priv, i)
3584 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3585
2f0aa304 3586 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3587
3588 /* allows RC6 residency counter to work */
49798eb2
JB		 3589 I915_WRITE(VLV_COUNTER_CONTROL,
3590 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3591 VLV_MEDIA_RC6_COUNT_EN |
3592 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3593 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3594 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3595
3596 intel_print_rc6_info(dev, rc6_mode);
3597
a2b23fe0 3598 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3599
64936258 3600 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3601
3602 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3603 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3604
0a073b84 3605 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 3606 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 3607 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3608 dev_priv->rps.cur_delay);
0a073b84
JB		 3609
3610 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3611 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 3612 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 3613 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 3614 dev_priv->rps.max_delay);
0a073b84 3615
73008b98
VS		 3616 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3617 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 3618 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3619 dev_priv->rps.rpe_delay);
0a073b84 3620
73008b98
VS		 3621 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3622 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 3623 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 3624 dev_priv->rps.min_delay);
0a073b84 3625
73008b98 3626 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 3627 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3628 dev_priv->rps.rpe_delay);
0a073b84 3629
73008b98 3630 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3631
44fc7d5c 3632 gen6_enable_rps_interrupts(dev);
0a073b84 3633
c8d9a590 3634 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3635}
3636
930ebb46 3637void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3638{
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640
3e373948
DV		 3641 if (dev_priv->ips.renderctx) {
3642 i915_gem_object_unpin(dev_priv->ips.renderctx);
3643 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3644 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3645 }
3646
3e373948
DV		 3647 if (dev_priv->ips.pwrctx) {
3648 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3649 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3650 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3651 }
3652}
3653
930ebb46 3654static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3655{
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657
3658 if (I915_READ(PWRCTXA)) {
3659 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3660 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3661 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3662 50);
3663
3664 I915_WRITE(PWRCTXA, 0);
3665 POSTING_READ(PWRCTXA);
3666
3667 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3668 POSTING_READ(RSTDBYCTL);
3669 }
2b4e57bd
ED		 3670}
3671
3672static int ironlake_setup_rc6(struct drm_device *dev)
3673{
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675
3e373948
DV		 3676 if (dev_priv->ips.renderctx == NULL)
3677 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3678 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3679 return -ENOMEM;
3680
3e373948
DV		 3681 if (dev_priv->ips.pwrctx == NULL)
3682 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3683 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3684 ironlake_teardown_rc6(dev);
3685 return -ENOMEM;
3686 }
3687
3688 return 0;
3689}
3690
930ebb46 3691static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3692{
3693 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3694 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3695 bool was_interruptible;
2b4e57bd
ED		 3696 int ret;
3697
3698 /* rc6 disabled by default due to repeated reports of hanging during
3699 * boot and resume.
3700 */
3701 if (!intel_enable_rc6(dev))
3702 return;
3703
79f5b2c7
DV		 3704 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3705
2b4e57bd 3706 ret = ironlake_setup_rc6(dev);
79f5b2c7 3707 if (ret)
2b4e57bd 3708 return;
2b4e57bd 3709
3e960501
CW		 3710 was_interruptible = dev_priv->mm.interruptible;
3711 dev_priv->mm.interruptible = false;
3712
2b4e57bd
ED		 3713 /*
3714 * GPU can automatically power down the render unit if given a page
3715 * to save state.
3716 */
6d90c952 3717 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3718 if (ret) {
3719 ironlake_teardown_rc6(dev);
3e960501 3720 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3721 return;
3722 }
3723
6d90c952
DV		 3724 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3725 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3726 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3727 MI_MM_SPACE_GTT |
3728 MI_SAVE_EXT_STATE_EN |
3729 MI_RESTORE_EXT_STATE_EN |
3730 MI_RESTORE_INHIBIT);
3731 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3732 intel_ring_emit(ring, MI_NOOP);
3733 intel_ring_emit(ring, MI_FLUSH);
3734 intel_ring_advance(ring);
2b4e57bd
ED		 3735
3736 /*
3737 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3738 * does an implicit flush, combined with MI_FLUSH above, it should be
3739 * safe to assume that renderctx is valid
3740 */
3e960501
CW		 3741 ret = intel_ring_idle(ring);
3742 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3743 if (ret) {
def27a58 3744 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3745 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3746 return;
3747 }
3748
f343c5f6 3749 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3750 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 3751
3752 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 3753}
3754
dde18883
ED		 3755static unsigned long intel_pxfreq(u32 vidfreq)
3756{
3757 unsigned long freq;
3758 int div = (vidfreq & 0x3f0000) >> 16;
3759 int post = (vidfreq & 0x3000) >> 12;
3760 int pre = (vidfreq & 0x7);
3761
3762 if (!pre)
3763 return 0;
3764
3765 freq = ((div * 133333) / ((1<<post) * pre));
3766
3767 return freq;
3768}
3769
eb48eb00
DV		 3770static const struct cparams {
3771 u16 i;
3772 u16 t;
3773 u16 m;
3774 u16 c;
3775} cparams[] = {
3776 { 1, 1333, 301, 28664 },
3777 { 1, 1066, 294, 24460 },
3778 { 1, 800, 294, 25192 },
3779 { 0, 1333, 276, 27605 },
3780 { 0, 1066, 276, 27605 },
3781 { 0, 800, 231, 23784 },
3782};
3783
f531dcb2 3784static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3785{
3786 u64 total_count, diff, ret;
3787 u32 count1, count2, count3, m = 0, c = 0;
3788 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3789 int i;
3790
02d71956
DV		 3791 assert_spin_locked(&mchdev_lock);
3792
20e4d407 3793 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3794
3795 /* Prevent division-by-zero if we are asking too fast.
3796 * Also, we don't get interesting results if we are polling
3797 * faster than once in 10ms, so just return the saved value
3798 * in such cases.
3799 */
3800 if (diff1 <= 10)
20e4d407 3801 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3802
3803 count1 = I915_READ(DMIEC);
3804 count2 = I915_READ(DDREC);
3805 count3 = I915_READ(CSIEC);
3806
3807 total_count = count1 + count2 + count3;
3808
3809 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3810 if (total_count < dev_priv->ips.last_count1) {
3811 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3812 diff += total_count;
3813 } else {
20e4d407 3814 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3815 }
3816
3817 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3818 if (cparams[i].i == dev_priv->ips.c_m &&
3819 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3820 m = cparams[i].m;
3821 c = cparams[i].c;
3822 break;
3823 }
3824 }
3825
3826 diff = div_u64(diff, diff1);
3827 ret = ((m * diff) + c);
3828 ret = div_u64(ret, 10);
3829
20e4d407
DV		 3830 dev_priv->ips.last_count1 = total_count;
3831 dev_priv->ips.last_time1 = now;
eb48eb00 3832
20e4d407 3833 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3834
3835 return ret;
3836}
3837
f531dcb2
CW		 3838unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3839{
3840 unsigned long val;
3841
3842 if (dev_priv->info->gen != 5)
3843 return 0;
3844
3845 spin_lock_irq(&mchdev_lock);
3846
3847 val = __i915_chipset_val(dev_priv);
3848
3849 spin_unlock_irq(&mchdev_lock);
3850
3851 return val;
3852}
3853
eb48eb00
DV		 3854unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3855{
3856 unsigned long m, x, b;
3857 u32 tsfs;
3858
3859 tsfs = I915_READ(TSFS);
3860
3861 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3862 x = I915_READ8(TR1);
3863
3864 b = tsfs & TSFS_INTR_MASK;
3865
3866 return ((m * x) / 127) - b;
3867}
3868
3869static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3870{
3871 static const struct v_table {
3872 u16 vd; /* in .1 mil */
3873 u16 vm; /* in .1 mil */
3874 } v_table[] = {
3875 { 0, 0, },
3876 { 375, 0, },
3877 { 500, 0, },
3878 { 625, 0, },
3879 { 750, 0, },
3880 { 875, 0, },
3881 { 1000, 0, },
3882 { 1125, 0, },
3883 { 4125, 3000, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4125, 3000, },
3888 { 4125, 3000, },
3889 { 4125, 3000, },
3890 { 4125, 3000, },
3891 { 4125, 3000, },
3892 { 4125, 3000, },
3893 { 4125, 3000, },
3894 { 4125, 3000, },
3895 { 4125, 3000, },
3896 { 4125, 3000, },
3897 { 4125, 3000, },
3898 { 4125, 3000, },
3899 { 4125, 3000, },
3900 { 4125, 3000, },
3901 { 4125, 3000, },
3902 { 4125, 3000, },
3903 { 4125, 3000, },
3904 { 4125, 3000, },
3905 { 4125, 3000, },
3906 { 4125, 3000, },
3907 { 4250, 3125, },
3908 { 4375, 3250, },
3909 { 4500, 3375, },
3910 { 4625, 3500, },
3911 { 4750, 3625, },
3912 { 4875, 3750, },
3913 { 5000, 3875, },
3914 { 5125, 4000, },
3915 { 5250, 4125, },
3916 { 5375, 4250, },
3917 { 5500, 4375, },
3918 { 5625, 4500, },
3919 { 5750, 4625, },
3920 { 5875, 4750, },
3921 { 6000, 4875, },
3922 { 6125, 5000, },
3923 { 6250, 5125, },
3924 { 6375, 5250, },
3925 { 6500, 5375, },
3926 { 6625, 5500, },
3927 { 6750, 5625, },
3928 { 6875, 5750, },
3929 { 7000, 5875, },
3930 { 7125, 6000, },
3931 { 7250, 6125, },
3932 { 7375, 6250, },
3933 { 7500, 6375, },
3934 { 7625, 6500, },
3935 { 7750, 6625, },
3936 { 7875, 6750, },
3937 { 8000, 6875, },
3938 { 8125, 7000, },
3939 { 8250, 7125, },
3940 { 8375, 7250, },
3941 { 8500, 7375, },
3942 { 8625, 7500, },
3943 { 8750, 7625, },
3944 { 8875, 7750, },
3945 { 9000, 7875, },
3946 { 9125, 8000, },
3947 { 9250, 8125, },
3948 { 9375, 8250, },
3949 { 9500, 8375, },
3950 { 9625, 8500, },
3951 { 9750, 8625, },
3952 { 9875, 8750, },
3953 { 10000, 8875, },
3954 { 10125, 9000, },
3955 { 10250, 9125, },
3956 { 10375, 9250, },
3957 { 10500, 9375, },
3958 { 10625, 9500, },
3959 { 10750, 9625, },
3960 { 10875, 9750, },
3961 { 11000, 9875, },
3962 { 11125, 10000, },
3963 { 11250, 10125, },
3964 { 11375, 10250, },
3965 { 11500, 10375, },
3966 { 11625, 10500, },
3967 { 11750, 10625, },
3968 { 11875, 10750, },
3969 { 12000, 10875, },
3970 { 12125, 11000, },
3971 { 12250, 11125, },
3972 { 12375, 11250, },
3973 { 12500, 11375, },
3974 { 12625, 11500, },
3975 { 12750, 11625, },
3976 { 12875, 11750, },
3977 { 13000, 11875, },
3978 { 13125, 12000, },
3979 { 13250, 12125, },
3980 { 13375, 12250, },
3981 { 13500, 12375, },
3982 { 13625, 12500, },
3983 { 13750, 12625, },
3984 { 13875, 12750, },
3985 { 14000, 12875, },
3986 { 14125, 13000, },
3987 { 14250, 13125, },
3988 { 14375, 13250, },
3989 { 14500, 13375, },
3990 { 14625, 13500, },
3991 { 14750, 13625, },
3992 { 14875, 13750, },
3993 { 15000, 13875, },
3994 { 15125, 14000, },
3995 { 15250, 14125, },
3996 { 15375, 14250, },
3997 { 15500, 14375, },
3998 { 15625, 14500, },
3999 { 15750, 14625, },
4000 { 15875, 14750, },
4001 { 16000, 14875, },
4002 { 16125, 15000, },
4003 };
4004 if (dev_priv->info->is_mobile)
4005 return v_table[pxvid].vm;
4006 else
4007 return v_table[pxvid].vd;
4008}
4009
02d71956 4010static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4011{
4012 struct timespec now, diff1;
4013 u64 diff;
4014 unsigned long diffms;
4015 u32 count;
4016
02d71956 4017 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4018
4019 getrawmonotonic(&now);
20e4d407 4020 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4021
4022 /* Don't divide by 0 */
4023 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4024 if (!diffms)
4025 return;
4026
4027 count = I915_READ(GFXEC);
4028
20e4d407
DV		 4029 if (count < dev_priv->ips.last_count2) {
4030 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4031 diff += count;
4032 } else {
20e4d407 4033 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4034 }
4035
20e4d407
DV		 4036 dev_priv->ips.last_count2 = count;
4037 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4038
4039 /* More magic constants... */
4040 diff = diff * 1181;
4041 diff = div_u64(diff, diffms * 10);
20e4d407 4042 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4043}
4044
02d71956
DV		 4045void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4046{
4047 if (dev_priv->info->gen != 5)
4048 return;
4049
9270388e 4050 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4051
4052 __i915_update_gfx_val(dev_priv);
4053
9270388e 4054 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4055}
4056
f531dcb2 4057static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4058{
4059 unsigned long t, corr, state1, corr2, state2;
4060 u32 pxvid, ext_v;
4061
02d71956
DV		 4062 assert_spin_locked(&mchdev_lock);
4063
c6a828d3 4064 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4065 pxvid = (pxvid >> 24) & 0x7f;
4066 ext_v = pvid_to_extvid(dev_priv, pxvid);
4067
4068 state1 = ext_v;
4069
4070 t = i915_mch_val(dev_priv);
4071
4072 /* Revel in the empirically derived constants */
4073
4074 /* Correction factor in 1/100000 units */
4075 if (t > 80)
4076 corr = ((t * 2349) + 135940);
4077 else if (t >= 50)
4078 corr = ((t * 964) + 29317);
4079 else /* < 50 */
4080 corr = ((t * 301) + 1004);
4081
4082 corr = corr * ((150142 * state1) / 10000 - 78642);
4083 corr /= 100000;
20e4d407 4084 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4085
4086 state2 = (corr2 * state1) / 10000;
4087 state2 /= 100; /* convert to mW */
4088
02d71956 4089 __i915_update_gfx_val(dev_priv);
eb48eb00 4090
20e4d407 4091 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4092}
4093
f531dcb2
CW		 4094unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4095{
4096 unsigned long val;
4097
4098 if (dev_priv->info->gen != 5)
4099 return 0;
4100
4101 spin_lock_irq(&mchdev_lock);
4102
4103 val = __i915_gfx_val(dev_priv);
4104
4105 spin_unlock_irq(&mchdev_lock);
4106
4107 return val;
4108}
4109
eb48eb00
DV		 4110/**
4111 * i915_read_mch_val - return value for IPS use
4112 *
4113 * Calculate and return a value for the IPS driver to use when deciding whether
4114 * we have thermal and power headroom to increase CPU or GPU power budget.
4115 */
4116unsigned long i915_read_mch_val(void)
4117{
4118 struct drm_i915_private *dev_priv;
4119 unsigned long chipset_val, graphics_val, ret = 0;
4120
9270388e 4121 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4122 if (!i915_mch_dev)
4123 goto out_unlock;
4124 dev_priv = i915_mch_dev;
4125
f531dcb2
CW		 4126 chipset_val = __i915_chipset_val(dev_priv);
4127 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4128
4129 ret = chipset_val + graphics_val;
4130
4131out_unlock:
9270388e 4132 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4133
4134 return ret;
4135}
4136EXPORT_SYMBOL_GPL(i915_read_mch_val);
4137
4138/**
4139 * i915_gpu_raise - raise GPU frequency limit
4140 *
4141 * Raise the limit; IPS indicates we have thermal headroom.
4142 */
4143bool i915_gpu_raise(void)
4144{
4145 struct drm_i915_private *dev_priv;
4146 bool ret = true;
4147
9270388e 4148 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4149 if (!i915_mch_dev) {
4150 ret = false;
4151 goto out_unlock;
4152 }
4153 dev_priv = i915_mch_dev;
4154
20e4d407
DV		 4155 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4156 dev_priv->ips.max_delay--;
eb48eb00
DV		 4157
4158out_unlock:
9270388e 4159 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4160
4161 return ret;
4162}
4163EXPORT_SYMBOL_GPL(i915_gpu_raise);
4164
4165/**
4166 * i915_gpu_lower - lower GPU frequency limit
4167 *
4168 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4169 * frequency maximum.
4170 */
4171bool i915_gpu_lower(void)
4172{
4173 struct drm_i915_private *dev_priv;
4174 bool ret = true;
4175
9270388e 4176 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4177 if (!i915_mch_dev) {
4178 ret = false;
4179 goto out_unlock;
4180 }
4181 dev_priv = i915_mch_dev;
4182
20e4d407
DV		 4183 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4184 dev_priv->ips.max_delay++;
eb48eb00
DV		 4185
4186out_unlock:
9270388e 4187 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4188
4189 return ret;
4190}
4191EXPORT_SYMBOL_GPL(i915_gpu_lower);
4192
4193/**
4194 * i915_gpu_busy - indicate GPU business to IPS
4195 *
4196 * Tell the IPS driver whether or not the GPU is busy.
4197 */
4198bool i915_gpu_busy(void)
4199{
4200 struct drm_i915_private *dev_priv;
f047e395 4201 struct intel_ring_buffer *ring;
eb48eb00 4202 bool ret = false;
f047e395 4203 int i;
eb48eb00 4204
9270388e 4205 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4206 if (!i915_mch_dev)
4207 goto out_unlock;
4208 dev_priv = i915_mch_dev;
4209
f047e395
CW		 4210 for_each_ring(ring, dev_priv, i)
4211 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4212
4213out_unlock:
9270388e 4214 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4215
4216 return ret;
4217}
4218EXPORT_SYMBOL_GPL(i915_gpu_busy);
4219
4220/**
4221 * i915_gpu_turbo_disable - disable graphics turbo
4222 *
4223 * Disable graphics turbo by resetting the max frequency and setting the
4224 * current frequency to the default.
4225 */
4226bool i915_gpu_turbo_disable(void)
4227{
4228 struct drm_i915_private *dev_priv;
4229 bool ret = true;
4230
9270388e 4231 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4232 if (!i915_mch_dev) {
4233 ret = false;
4234 goto out_unlock;
4235 }
4236 dev_priv = i915_mch_dev;
4237
20e4d407 4238 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4239
20e4d407 4240 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4241 ret = false;
4242
4243out_unlock:
9270388e 4244 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4245
4246 return ret;
4247}
4248EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4249
4250/**
4251 * Tells the intel_ips driver that the i915 driver is now loaded, if
4252 * IPS got loaded first.
4253 *
4254 * This awkward dance is so that neither module has to depend on the
4255 * other in order for IPS to do the appropriate communication of
4256 * GPU turbo limits to i915.
4257 */
4258static void
4259ips_ping_for_i915_load(void)
4260{
4261 void (*link)(void);
4262
4263 link = symbol_get(ips_link_to_i915_driver);
4264 if (link) {
4265 link();
4266 symbol_put(ips_link_to_i915_driver);
4267 }
4268}
4269
4270void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4271{
02d71956
DV		 4272 /* We only register the i915 ips part with intel-ips once everything is
4273 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4274 spin_lock_irq(&mchdev_lock);
eb48eb00 4275 i915_mch_dev = dev_priv;
9270388e 4276 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4277
4278 ips_ping_for_i915_load();
4279}
4280
4281void intel_gpu_ips_teardown(void)
4282{
9270388e 4283 spin_lock_irq(&mchdev_lock);
eb48eb00 4284 i915_mch_dev = NULL;
9270388e 4285 spin_unlock_irq(&mchdev_lock);
eb48eb00 4286}
8090c6b9 4287static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4288{
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 u32 lcfuse;
4291 u8 pxw[16];
4292 int i;
4293
4294 /* Disable to program */
4295 I915_WRITE(ECR, 0);
4296 POSTING_READ(ECR);
4297
4298 /* Program energy weights for various events */
4299 I915_WRITE(SDEW, 0x15040d00);
4300 I915_WRITE(CSIEW0, 0x007f0000);
4301 I915_WRITE(CSIEW1, 0x1e220004);
4302 I915_WRITE(CSIEW2, 0x04000004);
4303
4304 for (i = 0; i < 5; i++)
4305 I915_WRITE(PEW + (i * 4), 0);
4306 for (i = 0; i < 3; i++)
4307 I915_WRITE(DEW + (i * 4), 0);
4308
4309 /* Program P-state weights to account for frequency power adjustment */
4310 for (i = 0; i < 16; i++) {
4311 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4312 unsigned long freq = intel_pxfreq(pxvidfreq);
4313 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4314 PXVFREQ_PX_SHIFT;
4315 unsigned long val;
4316
4317 val = vid * vid;
4318 val *= (freq / 1000);
4319 val *= 255;
4320 val /= (127*127*900);
4321 if (val > 0xff)
4322 DRM_ERROR("bad pxval: %ld\n", val);
4323 pxw[i] = val;
4324 }
4325 /* Render standby states get 0 weight */
4326 pxw[14] = 0;
4327 pxw[15] = 0;
4328
4329 for (i = 0; i < 4; i++) {
4330 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4331 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4332 I915_WRITE(PXW + (i * 4), val);
4333 }
4334
4335 /* Adjust magic regs to magic values (more experimental results) */
4336 I915_WRITE(OGW0, 0);
4337 I915_WRITE(OGW1, 0);
4338 I915_WRITE(EG0, 0x00007f00);
4339 I915_WRITE(EG1, 0x0000000e);
4340 I915_WRITE(EG2, 0x000e0000);
4341 I915_WRITE(EG3, 0x68000300);
4342 I915_WRITE(EG4, 0x42000000);
4343 I915_WRITE(EG5, 0x00140031);
4344 I915_WRITE(EG6, 0);
4345 I915_WRITE(EG7, 0);
4346
4347 for (i = 0; i < 8; i++)
4348 I915_WRITE(PXWL + (i * 4), 0);
4349
4350 /* Enable PMON + select events */
4351 I915_WRITE(ECR, 0x80000019);
4352
4353 lcfuse = I915_READ(LCFUSE02);
4354
20e4d407 4355 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4356}
4357
8090c6b9
DV		 4358void intel_disable_gt_powersave(struct drm_device *dev)
4359{
1a01ab3b
JB		 4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361
fd0c0642
DV		 4362 /* Interrupts should be disabled already to avoid re-arming. */
4363 WARN_ON(dev->irq_enabled);
4364
930ebb46 4365 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4366 ironlake_disable_drps(dev);
930ebb46 4367 ironlake_disable_rc6(dev);
0a073b84 4368 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4369 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4370 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4371 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4372 if (IS_VALLEYVIEW(dev))
4373 valleyview_disable_rps(dev);
4374 else
4375 gen6_disable_rps(dev);
c0951f0c 4376 dev_priv->rps.enabled = false;
4fc688ce 4377 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4378 }
8090c6b9
DV		 4379}
4380
1a01ab3b
JB		 4381static void intel_gen6_powersave_work(struct work_struct *work)
4382{
4383 struct drm_i915_private *dev_priv =
4384 container_of(work, struct drm_i915_private,
4385 rps.delayed_resume_work.work);
4386 struct drm_device *dev = dev_priv->dev;
4387
4fc688ce 4388 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4389
4390 if (IS_VALLEYVIEW(dev)) {
4391 valleyview_enable_rps(dev);
6edee7f3
BW		 4392 } else if (IS_BROADWELL(dev)) {
4393 gen8_enable_rps(dev);
4394 gen6_update_ring_freq(dev);
0a073b84
JB		 4395 } else {
4396 gen6_enable_rps(dev);
4397 gen6_update_ring_freq(dev);
4398 }
c0951f0c 4399 dev_priv->rps.enabled = true;
4fc688ce 4400 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4401}
4402
8090c6b9
DV		 4403void intel_enable_gt_powersave(struct drm_device *dev)
4404{
1a01ab3b
JB		 4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406
8090c6b9
DV		 4407 if (IS_IRONLAKE_M(dev)) {
4408 ironlake_enable_drps(dev);
4409 ironlake_enable_rc6(dev);
4410 intel_init_emon(dev);
0a073b84 4411 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4412 /*
4413 * PCU communication is slow and this doesn't need to be
4414 * done at any specific time, so do this out of our fast path
4415 * to make resume and init faster.
4416 */
4417 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4418 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4419 }
4420}
4421
3107bd48
DV		 4422static void ibx_init_clock_gating(struct drm_device *dev)
4423{
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425
4426 /*
4427 * On Ibex Peak and Cougar Point, we need to disable clock
4428 * gating for the panel power sequencer or it will fail to
4429 * start up when no ports are active.
4430 */
4431 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4432}
4433
0e088b8f
VS		 4434static void g4x_disable_trickle_feed(struct drm_device *dev)
4435{
4436 struct drm_i915_private *dev_priv = dev->dev_private;
4437 int pipe;
4438
4439 for_each_pipe(pipe) {
4440 I915_WRITE(DSPCNTR(pipe),
4441 I915_READ(DSPCNTR(pipe)) |
4442 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4443 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4444 }
4445}
4446
017636cc
VS		 4447static void ilk_init_lp_watermarks(struct drm_device *dev)
4448{
4449 struct drm_i915_private *dev_priv = dev->dev_private;
4450
4451 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4452 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4453 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4454
4455 /*
4456 * Don't touch WM1S_LP_EN here.
4457 * Doing so could cause underruns.
4458 */
4459}
4460
1fa61106 4461static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4462{
4463 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4464 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4465
f1e8fa56
DL		 4466 /*
4467 * Required for FBC
4468 * WaFbcDisableDpfcClockGating:ilk
4469 */
4d47e4f5
DL		 4470 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4471 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4472 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4473
4474 I915_WRITE(PCH_3DCGDIS0,
4475 MARIUNIT_CLOCK_GATE_DISABLE |
4476 SVSMUNIT_CLOCK_GATE_DISABLE);
4477 I915_WRITE(PCH_3DCGDIS1,
4478 VFMUNIT_CLOCK_GATE_DISABLE);
4479
6f1d69b0
ED		 4480 /*
4481 * According to the spec the following bits should be set in
4482 * order to enable memory self-refresh
4483 * The bit 22/21 of 0x42004
4484 * The bit 5 of 0x42020
4485 * The bit 15 of 0x45000
4486 */
4487 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4488 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4489 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4490 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4491 I915_WRITE(DISP_ARB_CTL,
4492 (I915_READ(DISP_ARB_CTL) |
4493 DISP_FBC_WM_DIS));
017636cc
VS		 4494
4495 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4496
4497 /*
4498 * Based on the document from hardware guys the following bits
4499 * should be set unconditionally in order to enable FBC.
4500 * The bit 22 of 0x42000
4501 * The bit 22 of 0x42004
4502 * The bit 7,8,9 of 0x42020.
4503 */
4504 if (IS_IRONLAKE_M(dev)) {
4bb35334 4505 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4506 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4507 I915_READ(ILK_DISPLAY_CHICKEN1) |
4508 ILK_FBCQ_DIS);
4509 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4510 I915_READ(ILK_DISPLAY_CHICKEN2) |
4511 ILK_DPARB_GATE);
6f1d69b0
ED		 4512 }
4513
4d47e4f5
DL		 4514 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4515
6f1d69b0
ED		 4516 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4517 I915_READ(ILK_DISPLAY_CHICKEN2) |
4518 ILK_ELPIN_409_SELECT);
4519 I915_WRITE(_3D_CHICKEN2,
4520 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4521 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4522
ecdb4eb7 4523 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4524 I915_WRITE(CACHE_MODE_0,
4525 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4526
0e088b8f 4527 g4x_disable_trickle_feed(dev);
bdad2b2f 4528
3107bd48
DV		 4529 ibx_init_clock_gating(dev);
4530}
4531
4532static void cpt_init_clock_gating(struct drm_device *dev)
4533{
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 int pipe;
3f704fa2 4536 uint32_t val;
3107bd48
DV		 4537
4538 /*
4539 * On Ibex Peak and Cougar Point, we need to disable clock
4540 * gating for the panel power sequencer or it will fail to
4541 * start up when no ports are active.
4542 */
cd664078
JB		 4543 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4544 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4545 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4546 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4547 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4548 /* The below fixes the weird display corruption, a few pixels shifted
4549 * downward, on (only) LVDS of some HP laptops with IVY.
4550 */
3f704fa2 4551 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4552 val = I915_READ(TRANS_CHICKEN2(pipe));
4553 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4554 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4555 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4556 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4557 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4558 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4559 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4560 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4561 }
3107bd48
DV		 4562 /* WADP0ClockGatingDisable */
4563 for_each_pipe(pipe) {
4564 I915_WRITE(TRANS_CHICKEN1(pipe),
4565 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4566 }
6f1d69b0
ED		 4567}
4568
1d7aaa0c
DV		 4569static void gen6_check_mch_setup(struct drm_device *dev)
4570{
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 uint32_t tmp;
4573
4574 tmp = I915_READ(MCH_SSKPD);
4575 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4576 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4577 DRM_INFO("This can cause pipe underruns and display issues.\n");
4578 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4579 }
4580}
4581
1fa61106 4582static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4583{
4584 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4585 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4586
231e54f6 4587 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4588
4589 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4590 I915_READ(ILK_DISPLAY_CHICKEN2) |
4591 ILK_ELPIN_409_SELECT);
4592
ecdb4eb7 4593 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4594 I915_WRITE(_3D_CHICKEN,
4595 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4596
ecdb4eb7 4597 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4598 if (IS_SNB_GT1(dev))
4599 I915_WRITE(GEN6_GT_MODE,
4600 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4601
017636cc 4602 ilk_init_lp_watermarks(dev);
6f1d69b0 4603
6f1d69b0 4604 I915_WRITE(CACHE_MODE_0,
50743298 4605 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4606
4607 I915_WRITE(GEN6_UCGCTL1,
4608 I915_READ(GEN6_UCGCTL1) |
4609 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4610 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4611
4612 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4613 * gating disable must be set. Failure to set it results in
4614 * flickering pixels due to Z write ordering failures after
4615 * some amount of runtime in the Mesa "fire" demo, and Unigine
4616 * Sanctuary and Tropics, and apparently anything else with
4617 * alpha test or pixel discard.
4618 *
4619 * According to the spec, bit 11 (RCCUNIT) must also be set,
4620 * but we didn't debug actual testcases to find it out.
0f846f81 4621 *
ecdb4eb7
DL		 4622 * Also apply WaDisableVDSUnitClockGating:snb and
4623 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4624 */
4625 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4626 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4627 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4628 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4629
4630 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4631 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4632 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4633
4634 /*
4635 * According to the spec the following bits should be
4636 * set in order to enable memory self-refresh and fbc:
4637 * The bit21 and bit22 of 0x42000
4638 * The bit21 and bit22 of 0x42004
4639 * The bit5 and bit7 of 0x42020
4640 * The bit14 of 0x70180
4641 * The bit14 of 0x71180
4bb35334
DL		 4642 *
4643 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4644 */
4645 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4646 I915_READ(ILK_DISPLAY_CHICKEN1) |
4647 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4648 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4649 I915_READ(ILK_DISPLAY_CHICKEN2) |
4650 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4651 I915_WRITE(ILK_DSPCLK_GATE_D,
4652 I915_READ(ILK_DSPCLK_GATE_D) |
4653 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4654 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4655
0e088b8f 4656 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4657
4658 /* The default value should be 0x200 according to docs, but the two
4659 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4660 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4661 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4662
4663 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4664
4665 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4666}
4667
4668static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4669{
4670 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4671
4672 reg &= ~GEN7_FF_SCHED_MASK;
4673 reg |= GEN7_FF_TS_SCHED_HW;
4674 reg |= GEN7_FF_VS_SCHED_HW;
4675 reg |= GEN7_FF_DS_SCHED_HW;
4676
41c0b3a8
BW		 4677 if (IS_HASWELL(dev_priv->dev))
4678 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4679
6f1d69b0
ED		 4680 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4681}
4682
17a303ec
PZ		 4683static void lpt_init_clock_gating(struct drm_device *dev)
4684{
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686
4687 /*
4688 * TODO: this bit should only be enabled when really needed, then
4689 * disabled when not needed anymore in order to save power.
4690 */
4691 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4692 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4693 I915_READ(SOUTH_DSPCLK_GATE_D) |
4694 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4695
4696 /* WADPOClockGatingDisable:hsw */
4697 I915_WRITE(_TRANSA_CHICKEN1,
4698 I915_READ(_TRANSA_CHICKEN1) |
4699 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4700}
4701
7d708ee4
ID		 4702static void lpt_suspend_hw(struct drm_device *dev)
4703{
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705
4706 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4707 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4708
4709 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4710 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4711 }
4712}
4713
1020a5c2
BW		 4714static void gen8_init_clock_gating(struct drm_device *dev)
4715{
4716 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 4717 enum pipe i;
1020a5c2
BW		 4718
4719 I915_WRITE(WM3_LP_ILK, 0);
4720 I915_WRITE(WM2_LP_ILK, 0);
4721 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 4722
4723 /* FIXME(BDW): Check all the w/a, some might only apply to
4724 * pre-production hw. */
4725
fd392b60
BW		 4726 WARN(!i915_preliminary_hw_support,
4727 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
4728 I915_WRITE(HALF_SLICE_CHICKEN3,
4729 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 4730 I915_WRITE(HALF_SLICE_CHICKEN3,
4731 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 4732 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4733
7f88da0c
BW		 4734 I915_WRITE(_3D_CHICKEN3,
4735 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4736
a75f3628
BW		 4737 I915_WRITE(COMMON_SLICE_CHICKEN2,
4738 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4739
4c2e7a5f
BW		 4740 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4741 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4742
ab57fff1 4743 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 4744 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 4745
ab57fff1 4746 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4747 I915_WRITE(CHICKEN_PAR1_1,
4748 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4749
ab57fff1 4750 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4751 for_each_pipe(i) {
4752 I915_WRITE(CHICKEN_PIPESL_1(i),
4753 I915_READ(CHICKEN_PIPESL_1(i) |
4754 DPRS_MASK_VBLANK_SRD));
4755 }
63801f21
BW		 4756
4757 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4758 * workaround for for a possible hang in the unlikely event a TLB
4759 * invalidation occurs during a PSD flush.
4760 */
4761 I915_WRITE(HDC_CHICKEN0,
4762 I915_READ(HDC_CHICKEN0) |
4763 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 4764
4765 /* WaVSRefCountFullforceMissDisable:bdw */
4766 /* WaDSRefCountFullforceMissDisable:bdw */
4767 I915_WRITE(GEN7_FF_THREAD_MODE,
4768 I915_READ(GEN7_FF_THREAD_MODE) &
4769 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
1020a5c2
BW		 4770}
4771
cad2a2d7
ED		 4772static void haswell_init_clock_gating(struct drm_device *dev)
4773{
4774 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 4775
017636cc 4776 ilk_init_lp_watermarks(dev);
cad2a2d7
ED		 4777
4778 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4779 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4780 */
4781 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4782
ecdb4eb7 4783 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4784 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4785 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4786
ecdb4eb7 4787 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4788 I915_WRITE(GEN7_L3CNTLREG1,
4789 GEN7_WA_FOR_GEN7_L3_CONTROL);
4790 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4791 GEN7_WA_L3_CHICKEN_MODE);
4792
f3fc4884
FJ		 4793 /* L3 caching of data atomics doesn't work -- disable it. */
4794 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4795 I915_WRITE(HSW_ROW_CHICKEN3,
4796 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4797
ecdb4eb7 4798 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4799 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4800 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4801 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4802
ecdb4eb7 4803 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4804 gen7_setup_fixed_func_scheduler(dev_priv);
4805
ecdb4eb7 4806 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4807 I915_WRITE(CACHE_MODE_1,
4808 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4809
ecdb4eb7 4810 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4811 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4812
90a88643
PZ		 4813 /* WaRsPkgCStateDisplayPMReq:hsw */
4814 I915_WRITE(CHICKEN_PAR1_1,
4815 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4816
17a303ec 4817 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4818}
4819
1fa61106 4820static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4821{
4822 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4823 uint32_t snpcr;
6f1d69b0 4824
017636cc 4825 ilk_init_lp_watermarks(dev);
6f1d69b0 4826
231e54f6 4827 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4828
ecdb4eb7 4829 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4830 I915_WRITE(_3D_CHICKEN3,
4831 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4832
ecdb4eb7 4833 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4834 I915_WRITE(IVB_CHICKEN3,
4835 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4836 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4837
ecdb4eb7 4838 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4839 if (IS_IVB_GT1(dev))
4840 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4841 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4842 else
4843 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4844 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4845
ecdb4eb7 4846 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4847 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4848 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4849
ecdb4eb7 4850 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4851 I915_WRITE(GEN7_L3CNTLREG1,
4852 GEN7_WA_FOR_GEN7_L3_CONTROL);
4853 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4854 GEN7_WA_L3_CHICKEN_MODE);
4855 if (IS_IVB_GT1(dev))
4856 I915_WRITE(GEN7_ROW_CHICKEN2,
4857 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4858 else
4859 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4860 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4861
6f1d69b0 4862
ecdb4eb7 4863 /* WaForceL3Serialization:ivb */
61939d97
JB		 4864 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4865 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4866
0f846f81
JB		 4867 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4868 * gating disable must be set. Failure to set it results in
4869 * flickering pixels due to Z write ordering failures after
4870 * some amount of runtime in the Mesa "fire" demo, and Unigine
4871 * Sanctuary and Tropics, and apparently anything else with
4872 * alpha test or pixel discard.
4873 *
4874 * According to the spec, bit 11 (RCCUNIT) must also be set,
4875 * but we didn't debug actual testcases to find it out.
4876 *
4877 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4878 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4879 */
4880 I915_WRITE(GEN6_UCGCTL2,
4881 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4882 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4883
ecdb4eb7 4884 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4885 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4886 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4887 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4888
0e088b8f 4889 g4x_disable_trickle_feed(dev);
6f1d69b0 4890
ecdb4eb7 4891 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4892 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4893
ecdb4eb7 4894 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4895 I915_WRITE(CACHE_MODE_1,
4896 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4897
4898 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4899 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4900 snpcr |= GEN6_MBC_SNPCR_MED;
4901 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4902
ab5c608b
BW		 4903 if (!HAS_PCH_NOP(dev))
4904 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4905
4906 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4907}
4908
1fa61106 4909static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4910{
4911 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 4912 u32 val;
4913
4914 mutex_lock(&dev_priv->rps.hw_lock);
4915 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4916 mutex_unlock(&dev_priv->rps.hw_lock);
4917 switch ((val >> 6) & 3) {
4918 case 0:
85b1d7b3
JB		 4919 dev_priv->mem_freq = 800;
4920 break;
f64a28a7 4921 case 1:
85b1d7b3
JB		 4922 dev_priv->mem_freq = 1066;
4923 break;
f64a28a7 4924 case 2:
85b1d7b3
JB		 4925 dev_priv->mem_freq = 1333;
4926 break;
f64a28a7 4927 case 3:
2325991e 4928 dev_priv->mem_freq = 1333;
f64a28a7 4929 break;
85b1d7b3
JB		 4930 }
4931 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 4932
d7fe0cc0 4933 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4934
ecdb4eb7 4935 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4936 I915_WRITE(_3D_CHICKEN3,
4937 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4938
ecdb4eb7 4939 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4940 I915_WRITE(IVB_CHICKEN3,
4941 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4942 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4943
ecdb4eb7 4944 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4945 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4946 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4947 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4948
ecdb4eb7 4949 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4950 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4951 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4952
ecdb4eb7 4953 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4954 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4955 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4956
ecdb4eb7 4957 /* WaForceL3Serialization:vlv */
61939d97
JB		 4958 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4959 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4960
ecdb4eb7 4961 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4962 I915_WRITE(GEN7_ROW_CHICKEN2,
4963 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4964
ecdb4eb7 4965 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4966 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4967 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4968 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4969
0f846f81
JB		 4970 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4971 * gating disable must be set. Failure to set it results in
4972 * flickering pixels due to Z write ordering failures after
4973 * some amount of runtime in the Mesa "fire" demo, and Unigine
4974 * Sanctuary and Tropics, and apparently anything else with
4975 * alpha test or pixel discard.
4976 *
4977 * According to the spec, bit 11 (RCCUNIT) must also be set,
4978 * but we didn't debug actual testcases to find it out.
4979 *
4980 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4981 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4982 *
ecdb4eb7
DL		 4983 * Also apply WaDisableVDSUnitClockGating:vlv and
4984 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4985 */
4986 I915_WRITE(GEN6_UCGCTL2,
4987 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4988 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4989 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4990 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4991 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4992
e3f33d46
JB		 4993 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4994
e0d8d59b 4995 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4996
6b26c86d
DV		 4997 I915_WRITE(CACHE_MODE_1,
4998 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4999
2d809570 5000 /*
ecdb4eb7 5001 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5002 * Disable clock gating on th GCFG unit to prevent a delay
5003 * in the reporting of vblank events.
5004 */
4e8c84a5
JB		 5005 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5006
5007 /* Conservative clock gating settings for now */
5008 I915_WRITE(0x9400, 0xffffffff);
5009 I915_WRITE(0x9404, 0xffffffff);
5010 I915_WRITE(0x9408, 0xffffffff);
5011 I915_WRITE(0x940c, 0xffffffff);
5012 I915_WRITE(0x9410, 0xffffffff);
5013 I915_WRITE(0x9414, 0xffffffff);
5014 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5015}
5016
1fa61106 5017static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5018{
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 uint32_t dspclk_gate;
5021
5022 I915_WRITE(RENCLK_GATE_D1, 0);
5023 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5024 GS_UNIT_CLOCK_GATE_DISABLE |
5025 CL_UNIT_CLOCK_GATE_DISABLE);
5026 I915_WRITE(RAMCLK_GATE_D, 0);
5027 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5028 OVRUNIT_CLOCK_GATE_DISABLE |
5029 OVCUNIT_CLOCK_GATE_DISABLE;
5030 if (IS_GM45(dev))
5031 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5032 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5033
5034 /* WaDisableRenderCachePipelinedFlush */
5035 I915_WRITE(CACHE_MODE_0,
5036 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5037
0e088b8f 5038 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5039}
5040
1fa61106 5041static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5042{
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044
5045 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5046 I915_WRITE(RENCLK_GATE_D2, 0);
5047 I915_WRITE(DSPCLK_GATE_D, 0);
5048 I915_WRITE(RAMCLK_GATE_D, 0);
5049 I915_WRITE16(DEUC, 0);
20f94967
VS		 5050 I915_WRITE(MI_ARB_STATE,
5051 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5052}
5053
1fa61106 5054static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5055{
5056 struct drm_i915_private *dev_priv = dev->dev_private;
5057
5058 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5059 I965_RCC_CLOCK_GATE_DISABLE |
5060 I965_RCPB_CLOCK_GATE_DISABLE |
5061 I965_ISC_CLOCK_GATE_DISABLE |
5062 I965_FBC_CLOCK_GATE_DISABLE);
5063 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5064 I915_WRITE(MI_ARB_STATE,
5065 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5066}
5067
1fa61106 5068static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5069{
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 u32 dstate = I915_READ(D_STATE);
5072
5073 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5074 DSTATE_DOT_CLOCK_GATING;
5075 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5076
5077 if (IS_PINEVIEW(dev))
5078 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5079
5080 /* IIR "flip pending" means done if this bit is set */
5081 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5082}
5083
1fa61106 5084static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5085{
5086 struct drm_i915_private *dev_priv = dev->dev_private;
5087
5088 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5089}
5090
1fa61106 5091static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5092{
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094
5095 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5096}
5097
6f1d69b0
ED		 5098void intel_init_clock_gating(struct drm_device *dev)
5099{
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101
5102 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5103}
5104
7d708ee4
ID		 5105void intel_suspend_hw(struct drm_device *dev)
5106{
5107 if (HAS_PCH_LPT(dev))
5108 lpt_suspend_hw(dev);
5109}
5110
c1ca727f
ID		 5111#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5112 for (i = 0; \
5113 i < (power_domains)->power_well_count && \
5114 ((power_well) = &(power_domains)->power_wells[i]); \
5115 i++) \
5116 if ((power_well)->domains & (domain_mask))
5117
5118#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5119 for (i = (power_domains)->power_well_count - 1; \
5120 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5121 i--) \
5122 if ((power_well)->domains & (domain_mask))
5123
15d199ea
PZ		 5124/**
5125 * We should only use the power well if we explicitly asked the hardware to
5126 * enable it, so check if it's enabled and also check if we've requested it to
5127 * be enabled.
5128 */
c1ca727f
ID		 5129static bool hsw_power_well_enabled(struct drm_device *dev,
5130 struct i915_power_well *power_well)
5131{
5132 struct drm_i915_private *dev_priv = dev->dev_private;
5133
5134 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5135 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5136}
5137
ddf9c536
ID		 5138bool intel_display_power_enabled_sw(struct drm_device *dev,
5139 enum intel_display_power_domain domain)
5140{
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142 struct i915_power_domains *power_domains;
5143
5144 power_domains = &dev_priv->power_domains;
5145
5146 return power_domains->domain_use_count[domain];
5147}
5148
b97186f0
PZ		 5149bool intel_display_power_enabled(struct drm_device *dev,
5150 enum intel_display_power_domain domain)
15d199ea
PZ		 5151{
5152 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5153 struct i915_power_domains *power_domains;
5154 struct i915_power_well *power_well;
5155 bool is_enabled;
5156 int i;
15d199ea 5157
c1ca727f
ID		 5158 power_domains = &dev_priv->power_domains;
5159
5160 is_enabled = true;
5161
5162 mutex_lock(&power_domains->lock);
5163 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5164 if (power_well->always_on)
5165 continue;
5166
c1ca727f
ID		 5167 if (!power_well->is_enabled(dev, power_well)) {
5168 is_enabled = false;
5169 break;
5170 }
5171 }
5172 mutex_unlock(&power_domains->lock);
5173
5174 return is_enabled;
15d199ea
PZ		 5175}
5176
d5e8fdc8
PZ		 5177static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5178{
5179 struct drm_device *dev = dev_priv->dev;
5180 unsigned long irqflags;
5181
f9dcb0df
PZ		 5182 /*
5183 * After we re-enable the power well, if we touch VGA register 0x3d5
5184 * we'll get unclaimed register interrupts. This stops after we write
5185 * anything to the VGA MSR register. The vgacon module uses this
5186 * register all the time, so if we unbind our driver and, as a
5187 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5188 * console_unlock(). So make here we touch the VGA MSR register, making
5189 * sure vgacon can keep working normally without triggering interrupts
5190 * and error messages.
5191 */
5192 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5193 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5194 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5195
d5e8fdc8
PZ		 5196 if (IS_BROADWELL(dev)) {
5197 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5198 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5199 dev_priv->de_irq_mask[PIPE_B]);
5200 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5201 ~dev_priv->de_irq_mask[PIPE_B] |
5202 GEN8_PIPE_VBLANK);
5203 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5204 dev_priv->de_irq_mask[PIPE_C]);
5205 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5206 ~dev_priv->de_irq_mask[PIPE_C] |
5207 GEN8_PIPE_VBLANK);
5208 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5209 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5210 }
5211}
5212
5213static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5214{
5215 struct drm_device *dev = dev_priv->dev;
5216 enum pipe p;
5217 unsigned long irqflags;
5218
5219 /*
5220 * After this, the registers on the pipes that are part of the power
5221 * well will become zero, so we have to adjust our counters according to
5222 * that.
5223 *
5224 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5225 */
5226 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5227 for_each_pipe(p)
5228 if (p != PIPE_A)
5229 dev->vblank[p].last = 0;
5230 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5231}
5232
c1ca727f
ID		 5233static void hsw_set_power_well(struct drm_device *dev,
5234 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5235{
5236 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5237 bool is_enabled, enable_requested;
5238 uint32_t tmp;
d0d3e513 5239
d62292c8
PZ		 5240 WARN_ON(dev_priv->pc8.enabled);
5241
fa42e23c 5242 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5243 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5244 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5245
fa42e23c
PZ		 5246 if (enable) {
5247 if (!enable_requested)
6aedd1f5
PZ		 5248 I915_WRITE(HSW_PWR_WELL_DRIVER,
5249 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5250
fa42e23c
PZ		 5251 if (!is_enabled) {
5252 DRM_DEBUG_KMS("Enabling power well\n");
5253 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5254 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5255 DRM_ERROR("Timeout enabling power well\n");
5256 }
596cc11e 5257
d5e8fdc8 5258 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5259 } else {
5260 if (enable_requested) {
5261 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5262 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5263 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5264
d5e8fdc8 5265 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5266 }
5267 }
fa42e23c 5268}
d0d3e513 5269
b4ed4484
ID		 5270static void __intel_power_well_get(struct drm_device *dev,
5271 struct i915_power_well *power_well)
2d66aef5 5272{
d62292c8
PZ		 5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274
5275 if (!power_well->count++ && power_well->set) {
5276 hsw_disable_package_c8(dev_priv);
c1ca727f 5277 power_well->set(dev, power_well, true);
d62292c8 5278 }
2d66aef5
VS		 5279}
5280
b4ed4484
ID		 5281static void __intel_power_well_put(struct drm_device *dev,
5282 struct i915_power_well *power_well)
2d66aef5 5283{
d62292c8
PZ		 5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285
2d66aef5 5286 WARN_ON(!power_well->count);
c1ca727f 5287
d62292c8
PZ		 5288 if (!--power_well->count && power_well->set &&
5289 i915_disable_power_well) {
c1ca727f 5290 power_well->set(dev, power_well, false);
d62292c8
PZ		 5291 hsw_enable_package_c8(dev_priv);
5292 }
2d66aef5
VS		 5293}
5294
6765625e
VS		 5295void intel_display_power_get(struct drm_device *dev,
5296 enum intel_display_power_domain domain)
5297{
5298 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5299 struct i915_power_domains *power_domains;
c1ca727f
ID		 5300 struct i915_power_well *power_well;
5301 int i;
6765625e 5302
83c00f55
ID		 5303 power_domains = &dev_priv->power_domains;
5304
5305 mutex_lock(&power_domains->lock);
1da51581 5306
c1ca727f
ID		 5307 for_each_power_well(i, power_well, BIT(domain), power_domains)
5308 __intel_power_well_get(dev, power_well);
1da51581 5309
ddf9c536
ID		 5310 power_domains->domain_use_count[domain]++;
5311
83c00f55 5312 mutex_unlock(&power_domains->lock);
6765625e
VS		 5313}
5314
5315void intel_display_power_put(struct drm_device *dev,
5316 enum intel_display_power_domain domain)
5317{
5318 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5319 struct i915_power_domains *power_domains;
c1ca727f
ID		 5320 struct i915_power_well *power_well;
5321 int i;
6765625e 5322
83c00f55
ID		 5323 power_domains = &dev_priv->power_domains;
5324
5325 mutex_lock(&power_domains->lock);
1da51581 5326
1da51581
ID		 5327 WARN_ON(!power_domains->domain_use_count[domain]);
5328 power_domains->domain_use_count[domain]--;
ddf9c536
ID		 5329
5330 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5331 __intel_power_well_put(dev, power_well);
1da51581 5332
83c00f55 5333 mutex_unlock(&power_domains->lock);
6765625e
VS		 5334}
5335
83c00f55 5336static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5337
5338/* Display audio driver power well request */
5339void i915_request_power_well(void)
5340{
b4ed4484
ID		 5341 struct drm_i915_private *dev_priv;
5342
a38911a3
WX		 5343 if (WARN_ON(!hsw_pwr))
5344 return;
5345
b4ed4484
ID		 5346 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5347 power_domains);
fbeeaa23 5348 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5349}
5350EXPORT_SYMBOL_GPL(i915_request_power_well);
5351
5352/* Display audio driver power well release */
5353void i915_release_power_well(void)
5354{
b4ed4484
ID		 5355 struct drm_i915_private *dev_priv;
5356
a38911a3
WX		 5357 if (WARN_ON(!hsw_pwr))
5358 return;
5359
b4ed4484
ID		 5360 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5361 power_domains);
fbeeaa23 5362 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5363}
5364EXPORT_SYMBOL_GPL(i915_release_power_well);
5365
1c2256df
ID		 5366static struct i915_power_well i9xx_always_on_power_well[] = {
5367 {
5368 .name = "always-on",
5369 .always_on = 1,
5370 .domains = POWER_DOMAIN_MASK,
5371 },
5372};
5373
c1ca727f 5374static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5375 {
5376 .name = "always-on",
5377 .always_on = 1,
5378 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5379 },
c1ca727f
ID		 5380 {
5381 .name = "display",
5382 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5383 .is_enabled = hsw_power_well_enabled,
5384 .set = hsw_set_power_well,
5385 },
5386};
5387
5388static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5389 {
5390 .name = "always-on",
5391 .always_on = 1,
5392 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5393 },
c1ca727f
ID		 5394 {
5395 .name = "display",
5396 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5397 .is_enabled = hsw_power_well_enabled,
5398 .set = hsw_set_power_well,
5399 },
5400};
5401
5402#define set_power_wells(power_domains, __power_wells) ({ \
5403 (power_domains)->power_wells = (__power_wells); \
5404 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5405})
5406
ddb642fb 5407int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5410 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5411
83c00f55 5412 mutex_init(&power_domains->lock);
a38911a3 5413
c1ca727f
ID		 5414 /*
5415 * The enabling order will be from lower to higher indexed wells,
5416 * the disabling order is reversed.
5417 */
5418 if (IS_HASWELL(dev)) {
5419 set_power_wells(power_domains, hsw_power_wells);
5420 hsw_pwr = power_domains;
5421 } else if (IS_BROADWELL(dev)) {
5422 set_power_wells(power_domains, bdw_power_wells);
5423 hsw_pwr = power_domains;
5424 } else {
1c2256df 5425 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5426 }
a38911a3
WX		 5427
5428 return 0;
5429}
5430
ddb642fb 5431void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5432{
5433 hsw_pwr = NULL;
5434}
5435
ddb642fb 5436static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5437{
5438 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5439 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5440 struct i915_power_well *power_well;
c1ca727f 5441 int i;
9cdb826c 5442
83c00f55 5443 mutex_lock(&power_domains->lock);
c1ca727f
ID		 5444 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5445 if (power_well->set)
5446 power_well->set(dev, power_well, power_well->count > 0);
5447 }
83c00f55 5448 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5449}
5450
fa42e23c
PZ		 5451/*
5452 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5453 * when not needed anymore. We have 4 registers that can request the power well
5454 * to be enabled, and it will only be disabled if none of the registers is
5455 * requesting it to be enabled.
d0d3e513 5456 */
ddb642fb 5457void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5460
fa42e23c 5461 /* For now, we need the power well to be always enabled. */
baa70707 5462 intel_display_set_init_power(dev, true);
ddb642fb 5463 intel_power_domains_resume(dev);
d0d3e513 5464
f7243ac9
ID		 5465 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5466 return;
5467
fa42e23c
PZ		 5468 /* We're taking over the BIOS, so clear any requests made by it since
5469 * the driver is in charge now. */
6aedd1f5 5470 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5471 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5472}
5473
c67a470b
PZ		 5474/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5475void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5476{
5477 hsw_disable_package_c8(dev_priv);
5478}
5479
5480void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5481{
5482 hsw_enable_package_c8(dev_priv);
5483}
5484
8a187455
PZ		 5485void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5486{
5487 struct drm_device *dev = dev_priv->dev;
5488 struct device *device = &dev->pdev->dev;
5489
5490 if (!HAS_RUNTIME_PM(dev))
5491 return;
5492
5493 pm_runtime_get_sync(device);
5494 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5495}
5496
5497void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5498{
5499 struct drm_device *dev = dev_priv->dev;
5500 struct device *device = &dev->pdev->dev;
5501
5502 if (!HAS_RUNTIME_PM(dev))
5503 return;
5504
5505 pm_runtime_mark_last_busy(device);
5506 pm_runtime_put_autosuspend(device);
5507}
5508
5509void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5510{
5511 struct drm_device *dev = dev_priv->dev;
5512 struct device *device = &dev->pdev->dev;
5513
5514 dev_priv->pm.suspended = false;
5515
5516 if (!HAS_RUNTIME_PM(dev))
5517 return;
5518
5519 pm_runtime_set_active(device);
5520
5521 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5522 pm_runtime_mark_last_busy(device);
5523 pm_runtime_use_autosuspend(device);
5524}
5525
5526void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5527{
5528 struct drm_device *dev = dev_priv->dev;
5529 struct device *device = &dev->pdev->dev;
5530
5531 if (!HAS_RUNTIME_PM(dev))
5532 return;
5533
5534 /* Make sure we're not suspended first. */
5535 pm_runtime_get_sync(device);
5536 pm_runtime_disable(device);
5537}
5538
1fa61106
ED		 5539/* Set up chip specific power management-related functions */
5540void intel_init_pm(struct drm_device *dev)
5541{
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543
5544 if (I915_HAS_FBC(dev)) {
40045465 5545 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 5546 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 5547 dev_priv->display.enable_fbc = gen7_enable_fbc;
5548 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5549 } else if (INTEL_INFO(dev)->gen >= 5) {
5550 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5551 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 5552 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5553 } else if (IS_GM45(dev)) {
5554 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5555 dev_priv->display.enable_fbc = g4x_enable_fbc;
5556 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 5557 } else {
1fa61106
ED		 5558 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5559 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5560 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 5561
5562 /* This value was pulled out of someone's hat */
5563 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 5564 }
1fa61106
ED		 5565 }
5566
c921aba8
DV		 5567 /* For cxsr */
5568 if (IS_PINEVIEW(dev))
5569 i915_pineview_get_mem_freq(dev);
5570 else if (IS_GEN5(dev))
5571 i915_ironlake_get_mem_freq(dev);
5572
1fa61106
ED		 5573 /* For FIFO watermark updates */
5574 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5575 intel_setup_wm_latency(dev);
5576
1fa61106 5577 if (IS_GEN5(dev)) {
53615a5e
VS		 5578 if (dev_priv->wm.pri_latency[1] &&
5579 dev_priv->wm.spr_latency[1] &&
96f90c54
VS		 5580 dev_priv->wm.cur_latency[1]) {
5581 dev_priv->display.update_wm = haswell_update_wm;
5582 dev_priv->display.update_sprite_wm =
5583 haswell_update_sprite_wm;
5584 } else {
1fa61106
ED		 5585 DRM_DEBUG_KMS("Failed to get proper latency. "
5586 "Disable CxSR\n");
5587 dev_priv->display.update_wm = NULL;
5588 }
5589 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5590 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5591 if (dev_priv->wm.pri_latency[0] &&
5592 dev_priv->wm.spr_latency[0] &&
5593 dev_priv->wm.cur_latency[0]) {
96f90c54
VS		 5594 dev_priv->display.update_wm = haswell_update_wm;
5595 dev_priv->display.update_sprite_wm =
5596 haswell_update_sprite_wm;
1fa61106
ED		 5597 } else {
5598 DRM_DEBUG_KMS("Failed to read display plane latency. "
5599 "Disable CxSR\n");
5600 dev_priv->display.update_wm = NULL;
5601 }
5602 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5603 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5604 if (dev_priv->wm.pri_latency[0] &&
5605 dev_priv->wm.spr_latency[0] &&
5606 dev_priv->wm.cur_latency[0]) {
96f90c54
VS		 5607 dev_priv->display.update_wm = haswell_update_wm;
5608 dev_priv->display.update_sprite_wm =
5609 haswell_update_sprite_wm;
1fa61106
ED		 5610 } else {
5611 DRM_DEBUG_KMS("Failed to read display plane latency. "
5612 "Disable CxSR\n");
5613 dev_priv->display.update_wm = NULL;
5614 }
5615 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5616 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5617 if (dev_priv->wm.pri_latency[0] &&
5618 dev_priv->wm.spr_latency[0] &&
5619 dev_priv->wm.cur_latency[0]) {
1011d8c4 5620 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5621 dev_priv->display.update_sprite_wm =
5622 haswell_update_sprite_wm;
6b8a5eeb
ED		 5623 } else {
5624 DRM_DEBUG_KMS("Failed to read display plane latency. "
5625 "Disable CxSR\n");
5626 dev_priv->display.update_wm = NULL;
5627 }
cad2a2d7 5628 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 5629 } else if (INTEL_INFO(dev)->gen == 8) {
5630 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 5631 } else
5632 dev_priv->display.update_wm = NULL;
5633 } else if (IS_VALLEYVIEW(dev)) {
5634 dev_priv->display.update_wm = valleyview_update_wm;
5635 dev_priv->display.init_clock_gating =
5636 valleyview_init_clock_gating;
1fa61106
ED		 5637 } else if (IS_PINEVIEW(dev)) {
5638 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5639 dev_priv->is_ddr3,
5640 dev_priv->fsb_freq,
5641 dev_priv->mem_freq)) {
5642 DRM_INFO("failed to find known CxSR latency "
5643 "(found ddr%s fsb freq %d, mem freq %d), "
5644 "disabling CxSR\n",
5645 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5646 dev_priv->fsb_freq, dev_priv->mem_freq);
5647 /* Disable CxSR and never update its watermark again */
5648 pineview_disable_cxsr(dev);
5649 dev_priv->display.update_wm = NULL;
5650 } else
5651 dev_priv->display.update_wm = pineview_update_wm;
5652 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5653 } else if (IS_G4X(dev)) {
5654 dev_priv->display.update_wm = g4x_update_wm;
5655 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5656 } else if (IS_GEN4(dev)) {
5657 dev_priv->display.update_wm = i965_update_wm;
5658 if (IS_CRESTLINE(dev))
5659 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5660 else if (IS_BROADWATER(dev))
5661 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5662 } else if (IS_GEN3(dev)) {
5663 dev_priv->display.update_wm = i9xx_update_wm;
5664 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5665 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5666 } else if (IS_I865G(dev)) {
5667 dev_priv->display.update_wm = i830_update_wm;
5668 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5669 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5670 } else if (IS_I85X(dev)) {
5671 dev_priv->display.update_wm = i9xx_update_wm;
5672 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5673 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5674 } else {
5675 dev_priv->display.update_wm = i830_update_wm;
5676 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5677 if (IS_845G(dev))
5678 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5679 else
5680 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5681 }
5682}
5683
42c0526c
BW		 5684int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5685{
4fc688ce 5686 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5687
5688 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5689 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5690 return -EAGAIN;
5691 }
5692
5693 I915_WRITE(GEN6_PCODE_DATA, *val);
5694 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5695
5696 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5697 500)) {
5698 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5699 return -ETIMEDOUT;
5700 }
5701
5702 *val = I915_READ(GEN6_PCODE_DATA);
5703 I915_WRITE(GEN6_PCODE_DATA, 0);
5704
5705 return 0;
5706}
5707
5708int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5709{
4fc688ce 5710 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5711
5712 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5713 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5714 return -EAGAIN;
5715 }
5716
5717 I915_WRITE(GEN6_PCODE_DATA, val);
5718 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5719
5720 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5721 500)) {
5722 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5723 return -ETIMEDOUT;
5724 }
5725
5726 I915_WRITE(GEN6_PCODE_DATA, 0);
5727
5728 return 0;
5729}
a0e4e199 5730
2ec3815f 5731int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 5732{
07ab118b 5733 int div;
855ba3be 5734
07ab118b 5735 /* 4 x czclk */
2ec3815f 5736 switch (dev_priv->mem_freq) {
855ba3be 5737 case 800:
07ab118b 5738 div = 10;
855ba3be
JB		 5739 break;
5740 case 1066:
07ab118b 5741 div = 12;
855ba3be
JB		 5742 break;
5743 case 1333:
07ab118b 5744 div = 16;
855ba3be
JB		 5745 break;
5746 default:
5747 return -1;
5748 }
5749
2ec3815f 5750 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 5751}
5752
2ec3815f 5753int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 5754{
07ab118b 5755 int mul;
855ba3be 5756
07ab118b 5757 /* 4 x czclk */
2ec3815f 5758 switch (dev_priv->mem_freq) {
855ba3be 5759 case 800:
07ab118b 5760 mul = 10;
855ba3be
JB		 5761 break;
5762 case 1066:
07ab118b 5763 mul = 12;
855ba3be
JB		 5764 break;
5765 case 1333:
07ab118b 5766 mul = 16;
855ba3be
JB		 5767 break;
5768 default:
5769 return -1;
5770 }
5771
2ec3815f 5772 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 5773}
5774
907b28c5
CW		 5775void intel_pm_init(struct drm_device *dev)
5776{
5777 struct drm_i915_private *dev_priv = dev->dev_private;
5778
5779 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5780 intel_gen6_powersave_work);
5781}
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