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drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
50227e1c 112 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
50227e1c 151 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
5209b1f4
ID		 322 struct drm_device *dev = dev_priv->dev;
323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 342 } else if (IS_I915GM(dev)) {
343 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
344 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
345 I915_WRITE(INSTPM, val);
a7a6c498 346 POSTING_READ(INSTPM);
5209b1f4
ID		 347 } else {
348 return;
349 }
b445e3b0 350
5209b1f4
ID		 351 DRM_DEBUG_KMS("memory self-refresh is %s\n",
352 enable ? "enabled" : "disabled");
b445e3b0
ED		 353}
354
fc1ac8de 355
b445e3b0
ED		 356/*
357 * Latency for FIFO fetches is dependent on several factors:
358 * - memory configuration (speed, channels)
359 * - chipset
360 * - current MCH state
361 * It can be fairly high in some situations, so here we assume a fairly
362 * pessimal value. It's a tradeoff between extra memory fetches (if we
363 * set this value too high, the FIFO will fetch frequently to stay full)
364 * and power consumption (set it too low to save power and we might see
365 * FIFO underruns and display "flicker").
366 *
367 * A value of 5us seems to be a good balance; safe for very low end
368 * platforms but not overly aggressive on lower latency configs.
369 */
5aef6003 370static const int pessimal_latency_ns = 5000;
b445e3b0 371
b5004720
VS		 372#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
373 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
374
375static int vlv_get_fifo_size(struct drm_device *dev,
376 enum pipe pipe, int plane)
377{
378 struct drm_i915_private *dev_priv = dev->dev_private;
379 int sprite0_start, sprite1_start, size;
380
381 switch (pipe) {
382 uint32_t dsparb, dsparb2, dsparb3;
383 case PIPE_A:
384 dsparb = I915_READ(DSPARB);
385 dsparb2 = I915_READ(DSPARB2);
386 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
387 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
388 break;
389 case PIPE_B:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
394 break;
395 case PIPE_C:
396 dsparb2 = I915_READ(DSPARB2);
397 dsparb3 = I915_READ(DSPARB3);
398 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
399 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
400 break;
401 default:
402 return 0;
403 }
404
405 switch (plane) {
406 case 0:
407 size = sprite0_start;
408 break;
409 case 1:
410 size = sprite1_start - sprite0_start;
411 break;
412 case 2:
413 size = 512 - 1 - sprite1_start;
414 break;
415 default:
416 return 0;
417 }
418
419 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
420 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
421 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
422 size);
423
424 return size;
425}
426
1fa61106 427static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 428{
429 struct drm_i915_private *dev_priv = dev->dev_private;
430 uint32_t dsparb = I915_READ(DSPARB);
431 int size;
432
433 size = dsparb & 0x7f;
434 if (plane)
435 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
436
437 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
438 plane ? "B" : "A", size);
439
440 return size;
441}
442
feb56b93 443static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 uint32_t dsparb = I915_READ(DSPARB);
447 int size;
448
449 size = dsparb & 0x1ff;
450 if (plane)
451 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
452 size >>= 1; /* Convert to cachelines */
453
454 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
455 plane ? "B" : "A", size);
456
457 return size;
458}
459
1fa61106 460static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 461{
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 uint32_t dsparb = I915_READ(DSPARB);
464 int size;
465
466 size = dsparb & 0x7f;
467 size >>= 2; /* Convert to cachelines */
468
469 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
470 plane ? "B" : "A",
471 size);
472
473 return size;
474}
475
b445e3b0
ED		 476/* Pineview has different values for various configs */
477static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 478 .fifo_size = PINEVIEW_DISPLAY_FIFO,
479 .max_wm = PINEVIEW_MAX_WM,
480 .default_wm = PINEVIEW_DFT_WM,
481 .guard_size = PINEVIEW_GUARD_WM,
482 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 483};
484static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 485 .fifo_size = PINEVIEW_DISPLAY_FIFO,
486 .max_wm = PINEVIEW_MAX_WM,
487 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
488 .guard_size = PINEVIEW_GUARD_WM,
489 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 490};
491static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 492 .fifo_size = PINEVIEW_CURSOR_FIFO,
493 .max_wm = PINEVIEW_CURSOR_MAX_WM,
494 .default_wm = PINEVIEW_CURSOR_DFT_WM,
495 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
496 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 497};
498static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 499 .fifo_size = PINEVIEW_CURSOR_FIFO,
500 .max_wm = PINEVIEW_CURSOR_MAX_WM,
501 .default_wm = PINEVIEW_CURSOR_DFT_WM,
502 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
503 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 504};
505static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 506 .fifo_size = G4X_FIFO_SIZE,
507 .max_wm = G4X_MAX_WM,
508 .default_wm = G4X_MAX_WM,
509 .guard_size = 2,
510 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 511};
512static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 513 .fifo_size = I965_CURSOR_FIFO,
514 .max_wm = I965_CURSOR_MAX_WM,
515 .default_wm = I965_CURSOR_DFT_WM,
516 .guard_size = 2,
517 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 518};
b445e3b0 519static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 520 .fifo_size = I965_CURSOR_FIFO,
521 .max_wm = I965_CURSOR_MAX_WM,
522 .default_wm = I965_CURSOR_DFT_WM,
523 .guard_size = 2,
524 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 525};
526static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 527 .fifo_size = I945_FIFO_SIZE,
528 .max_wm = I915_MAX_WM,
529 .default_wm = 1,
530 .guard_size = 2,
531 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 532};
533static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 534 .fifo_size = I915_FIFO_SIZE,
535 .max_wm = I915_MAX_WM,
536 .default_wm = 1,
537 .guard_size = 2,
538 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 539};
9d539105 540static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 541 .fifo_size = I855GM_FIFO_SIZE,
542 .max_wm = I915_MAX_WM,
543 .default_wm = 1,
544 .guard_size = 2,
545 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 546};
9d539105
VS		 547static const struct intel_watermark_params i830_bc_wm_info = {
548 .fifo_size = I855GM_FIFO_SIZE,
549 .max_wm = I915_MAX_WM/2,
550 .default_wm = 1,
551 .guard_size = 2,
552 .cacheline_size = I830_FIFO_LINE_SIZE,
553};
feb56b93 554static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 555 .fifo_size = I830_FIFO_SIZE,
556 .max_wm = I915_MAX_WM,
557 .default_wm = 1,
558 .guard_size = 2,
559 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 560};
561
b445e3b0
ED		 562/**
563 * intel_calculate_wm - calculate watermark level
564 * @clock_in_khz: pixel clock
565 * @wm: chip FIFO params
ac484963 566 * @cpp: bytes per pixel
b445e3b0
ED		 567 * @latency_ns: memory latency for the platform
568 *
569 * Calculate the watermark level (the level at which the display plane will
570 * start fetching from memory again). Each chip has a different display
571 * FIFO size and allocation, so the caller needs to figure that out and pass
572 * in the correct intel_watermark_params structure.
573 *
574 * As the pixel clock runs, the FIFO will be drained at a rate that depends
575 * on the pixel size. When it reaches the watermark level, it'll start
576 * fetching FIFO line sized based chunks from memory until the FIFO fills
577 * past the watermark point. If the FIFO drains completely, a FIFO underrun
578 * will occur, and a display engine hang could result.
579 */
580static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
581 const struct intel_watermark_params *wm,
ac484963 582 int fifo_size, int cpp,
b445e3b0
ED		 583 unsigned long latency_ns)
584{
585 long entries_required, wm_size;
586
587 /*
588 * Note: we need to make sure we don't overflow for various clock &
589 * latency values.
590 * clocks go from a few thousand to several hundred thousand.
591 * latency is usually a few thousand
592 */
ac484963 593 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 594 1000;
595 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
596
597 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
598
599 wm_size = fifo_size - (entries_required + wm->guard_size);
600
601 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
602
603 /* Don't promote wm_size to unsigned... */
604 if (wm_size > (long)wm->max_wm)
605 wm_size = wm->max_wm;
606 if (wm_size <= 0)
607 wm_size = wm->default_wm;
d6feb196
VS		 608
609 /*
610 * Bspec seems to indicate that the value shouldn't be lower than
611 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
612 * Lets go for 8 which is the burst size since certain platforms
613 * already use a hardcoded 8 (which is what the spec says should be
614 * done).
615 */
616 if (wm_size <= 8)
617 wm_size = 8;
618
b445e3b0
ED		 619 return wm_size;
620}
621
622static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
623{
624 struct drm_crtc *crtc, *enabled = NULL;
625
70e1e0ec 626 for_each_crtc(dev, crtc) {
3490ea5d 627 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 628 if (enabled)
629 return NULL;
630 enabled = crtc;
631 }
632 }
633
634 return enabled;
635}
636
46ba614c 637static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 638{
46ba614c 639 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_crtc *crtc;
642 const struct cxsr_latency *latency;
643 u32 reg;
644 unsigned long wm;
645
646 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
647 dev_priv->fsb_freq, dev_priv->mem_freq);
648 if (!latency) {
649 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 650 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 651 return;
652 }
653
654 crtc = single_enabled_crtc(dev);
655 if (crtc) {
7c5f93b0 656 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 657 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 658 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 659
660 /* Display SR */
661 wm = intel_calculate_wm(clock, &pineview_display_wm,
662 pineview_display_wm.fifo_size,
ac484963 663 cpp, latency->display_sr);
b445e3b0
ED		 664 reg = I915_READ(DSPFW1);
665 reg &= ~DSPFW_SR_MASK;
f4998963 666 reg |= FW_WM(wm, SR);
b445e3b0
ED		 667 I915_WRITE(DSPFW1, reg);
668 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
669
670 /* cursor SR */
671 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
672 pineview_display_wm.fifo_size,
ac484963 673 cpp, latency->cursor_sr);
b445e3b0
ED		 674 reg = I915_READ(DSPFW3);
675 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 676 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 677 I915_WRITE(DSPFW3, reg);
678
679 /* Display HPLL off SR */
680 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
681 pineview_display_hplloff_wm.fifo_size,
ac484963 682 cpp, latency->display_hpll_disable);
b445e3b0
ED		 683 reg = I915_READ(DSPFW3);
684 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 685 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 686 I915_WRITE(DSPFW3, reg);
687
688 /* cursor HPLL off SR */
689 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
690 pineview_display_hplloff_wm.fifo_size,
ac484963 691 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 692 reg = I915_READ(DSPFW3);
693 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 694 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 695 I915_WRITE(DSPFW3, reg);
696 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
697
5209b1f4 698 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 699 } else {
5209b1f4 700 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 701 }
702}
703
704static bool g4x_compute_wm0(struct drm_device *dev,
705 int plane,
706 const struct intel_watermark_params *display,
707 int display_latency_ns,
708 const struct intel_watermark_params *cursor,
709 int cursor_latency_ns,
710 int *plane_wm,
711 int *cursor_wm)
712{
713 struct drm_crtc *crtc;
4fe8590a 714 const struct drm_display_mode *adjusted_mode;
ac484963 715 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 716 int line_time_us, line_count;
717 int entries, tlb_miss;
718
719 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 720 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 721 *cursor_wm = cursor->guard_size;
722 *plane_wm = display->guard_size;
723 return false;
724 }
725
6e3c9717 726 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 727 clock = adjusted_mode->crtc_clock;
fec8cba3 728 htotal = adjusted_mode->crtc_htotal;
6e3c9717 729 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 730 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 731
732 /* Use the small buffer method to calculate plane watermark */
ac484963 733 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 734 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
735 if (tlb_miss > 0)
736 entries += tlb_miss;
737 entries = DIV_ROUND_UP(entries, display->cacheline_size);
738 *plane_wm = entries + display->guard_size;
739 if (*plane_wm > (int)display->max_wm)
740 *plane_wm = display->max_wm;
741
742 /* Use the large buffer method to calculate cursor watermark */
922044c9 743 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 744 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 745 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 746 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
750 *cursor_wm = entries + cursor->guard_size;
751 if (*cursor_wm > (int)cursor->max_wm)
752 *cursor_wm = (int)cursor->max_wm;
753
754 return true;
755}
756
757/*
758 * Check the wm result.
759 *
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
762 * must be disabled.
763 */
764static bool g4x_check_srwm(struct drm_device *dev,
765 int display_wm, int cursor_wm,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor)
768{
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm, cursor_wm);
771
772 if (display_wm > display->max_wm) {
773 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
774 display_wm, display->max_wm);
775 return false;
776 }
777
778 if (cursor_wm > cursor->max_wm) {
779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
780 cursor_wm, cursor->max_wm);
781 return false;
782 }
783
784 if (!(display_wm || cursor_wm)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
786 return false;
787 }
788
789 return true;
790}
791
792static bool g4x_compute_srwm(struct drm_device *dev,
793 int plane,
794 int latency_ns,
795 const struct intel_watermark_params *display,
796 const struct intel_watermark_params *cursor,
797 int *display_wm, int *cursor_wm)
798{
799 struct drm_crtc *crtc;
4fe8590a 800 const struct drm_display_mode *adjusted_mode;
ac484963 801 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 802 unsigned long line_time_us;
803 int line_count, line_size;
804 int small, large;
805 int entries;
806
807 if (!latency_ns) {
808 *display_wm = *cursor_wm = 0;
809 return false;
810 }
811
812 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 813 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 814 clock = adjusted_mode->crtc_clock;
fec8cba3 815 htotal = adjusted_mode->crtc_htotal;
6e3c9717 816 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 817 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 818
922044c9 819 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 820 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 821 line_size = hdisplay * cpp;
b445e3b0
ED		 822
823 /* Use the minimum of the small and large buffer method for primary */
ac484963 824 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 825 large = line_count * line_size;
826
827 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
828 *display_wm = entries + display->guard_size;
829
830 /* calculate the self-refresh watermark for display cursor */
ac484963 831 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 832 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
833 *cursor_wm = entries + cursor->guard_size;
834
835 return g4x_check_srwm(dev,
836 *display_wm, *cursor_wm,
837 display, cursor);
838}
839
15665979
VS		 840#define FW_WM_VLV(value, plane) \
841 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
842
0018fda1
VS		 843static void vlv_write_wm_values(struct intel_crtc *crtc,
844 const struct vlv_wm_values *wm)
845{
846 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
847 enum pipe pipe = crtc->pipe;
848
849 I915_WRITE(VLV_DDL(pipe),
850 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
851 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
852 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
853 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
854
ae80152d 855 I915_WRITE(DSPFW1,
15665979
VS		 856 FW_WM(wm->sr.plane, SR) |
857 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
858 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
859 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 860 I915_WRITE(DSPFW2,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
862 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
863 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 864 I915_WRITE(DSPFW3,
15665979 865 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 866
867 if (IS_CHERRYVIEW(dev_priv)) {
868 I915_WRITE(DSPFW7_CHV,
15665979
VS		 869 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
870 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 871 I915_WRITE(DSPFW8_CHV,
15665979
VS		 872 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
873 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 874 I915_WRITE(DSPFW9_CHV,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
876 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 877 I915_WRITE(DSPHOWM,
15665979
VS		 878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
880 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
881 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
882 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
883 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
884 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
885 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
886 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
887 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 888 } else {
889 I915_WRITE(DSPFW7,
15665979
VS		 890 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
891 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 892 I915_WRITE(DSPHOWM,
15665979
VS		 893 FW_WM(wm->sr.plane >> 9, SR_HI) |
894 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
895 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
896 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
897 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
898 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
899 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 900 }
901
2cb389b7
VS		 902 /* zero (unused) WM1 watermarks */
903 I915_WRITE(DSPFW4, 0);
904 I915_WRITE(DSPFW5, 0);
905 I915_WRITE(DSPFW6, 0);
906 I915_WRITE(DSPHOWM1, 0);
907
ae80152d 908 POSTING_READ(DSPFW1);
0018fda1
VS		 909}
910
15665979
VS		 911#undef FW_WM_VLV
912
6eb1a681
VS		 913enum vlv_wm_level {
914 VLV_WM_LEVEL_PM2,
915 VLV_WM_LEVEL_PM5,
916 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 917};
918
262cd2e1
VS		 919/* latency must be in 0.1us units. */
920static unsigned int vlv_wm_method2(unsigned int pixel_rate,
921 unsigned int pipe_htotal,
922 unsigned int horiz_pixels,
ac484963 923 unsigned int cpp,
262cd2e1
VS		 924 unsigned int latency)
925{
926 unsigned int ret;
927
928 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 929 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 930 ret = DIV_ROUND_UP(ret, 64);
931
932 return ret;
933}
934
935static void vlv_setup_wm_latency(struct drm_device *dev)
936{
937 struct drm_i915_private *dev_priv = dev->dev_private;
938
939 /* all latencies in usec */
940 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
941
58590c14
VS		 942 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
943
262cd2e1
VS		 944 if (IS_CHERRYVIEW(dev_priv)) {
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
946 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 947
948 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 949 }
950}
951
952static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
953 struct intel_crtc *crtc,
954 const struct intel_plane_state *state,
955 int level)
956{
957 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 958 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 959
960 if (dev_priv->wm.pri_latency[level] == 0)
961 return USHRT_MAX;
962
963 if (!state->visible)
964 return 0;
965
ac484963 966 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 967 clock = crtc->config->base.adjusted_mode.crtc_clock;
968 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
969 width = crtc->config->pipe_src_w;
970 if (WARN_ON(htotal == 0))
971 htotal = 1;
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
974 /*
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
979 */
980 wm = 63;
981 } else {
ac484963 982 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 983 dev_priv->wm.pri_latency[level] * 10);
984 }
985
986 return min_t(int, wm, USHRT_MAX);
987}
988
54f1b6e1
VS		 989static void vlv_compute_fifo(struct intel_crtc *crtc)
990{
991 struct drm_device *dev = crtc->base.dev;
992 struct vlv_wm_state *wm_state = &crtc->wm_state;
993 struct intel_plane *plane;
994 unsigned int total_rate = 0;
995 const int fifo_size = 512 - 1;
996 int fifo_extra, fifo_left = fifo_size;
997
998 for_each_intel_plane_on_crtc(dev, crtc, plane) {
999 struct intel_plane_state *state =
1000 to_intel_plane_state(plane->base.state);
1001
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
1004
1005 if (state->visible) {
1006 wm_state->num_active_planes++;
1007 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008 }
1009 }
1010
1011 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012 struct intel_plane_state *state =
1013 to_intel_plane_state(plane->base.state);
1014 unsigned int rate;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 plane->wm.fifo_size = 63;
1018 continue;
1019 }
1020
1021 if (!state->visible) {
1022 plane->wm.fifo_size = 0;
1023 continue;
1024 }
1025
1026 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1027 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028 fifo_left -= plane->wm.fifo_size;
1029 }
1030
1031 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035 int plane_extra;
1036
1037 if (fifo_left == 0)
1038 break;
1039
1040 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041 continue;
1042
1043 /* give it all to the first plane if none are active */
1044 if (plane->wm.fifo_size == 0 &&
1045 wm_state->num_active_planes)
1046 continue;
1047
1048 plane_extra = min(fifo_extra, fifo_left);
1049 plane->wm.fifo_size += plane_extra;
1050 fifo_left -= plane_extra;
1051 }
1052
1053 WARN_ON(fifo_left != 0);
1054}
1055
262cd2e1
VS		 1056static void vlv_invert_wms(struct intel_crtc *crtc)
1057{
1058 struct vlv_wm_state *wm_state = &crtc->wm_state;
1059 int level;
1060
1061 for (level = 0; level < wm_state->num_levels; level++) {
1062 struct drm_device *dev = crtc->base.dev;
1063 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1064 struct intel_plane *plane;
1065
1066 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1067 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1068
1069 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1070 switch (plane->base.type) {
1071 int sprite;
1072 case DRM_PLANE_TYPE_CURSOR:
1073 wm_state->wm[level].cursor = plane->wm.fifo_size -
1074 wm_state->wm[level].cursor;
1075 break;
1076 case DRM_PLANE_TYPE_PRIMARY:
1077 wm_state->wm[level].primary = plane->wm.fifo_size -
1078 wm_state->wm[level].primary;
1079 break;
1080 case DRM_PLANE_TYPE_OVERLAY:
1081 sprite = plane->plane;
1082 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1083 wm_state->wm[level].sprite[sprite];
1084 break;
1085 }
1086 }
1087 }
1088}
1089
26e1fe4f 1090static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1091{
1092 struct drm_device *dev = crtc->base.dev;
1093 struct vlv_wm_state *wm_state = &crtc->wm_state;
1094 struct intel_plane *plane;
1095 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1096 int level;
1097
1098 memset(wm_state, 0, sizeof(*wm_state));
1099
852eb00d 1100 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1101 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1102
1103 wm_state->num_active_planes = 0;
262cd2e1 1104
54f1b6e1 1105 vlv_compute_fifo(crtc);
262cd2e1
VS		 1106
1107 if (wm_state->num_active_planes != 1)
1108 wm_state->cxsr = false;
1109
1110 if (wm_state->cxsr) {
1111 for (level = 0; level < wm_state->num_levels; level++) {
1112 wm_state->sr[level].plane = sr_fifo_size;
1113 wm_state->sr[level].cursor = 63;
1114 }
1115 }
1116
1117 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1118 struct intel_plane_state *state =
1119 to_intel_plane_state(plane->base.state);
1120
1121 if (!state->visible)
1122 continue;
1123
1124 /* normal watermarks */
1125 for (level = 0; level < wm_state->num_levels; level++) {
1126 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1127 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1128
1129 /* hack */
1130 if (WARN_ON(level == 0 && wm > max_wm))
1131 wm = max_wm;
1132
1133 if (wm > plane->wm.fifo_size)
1134 break;
1135
1136 switch (plane->base.type) {
1137 int sprite;
1138 case DRM_PLANE_TYPE_CURSOR:
1139 wm_state->wm[level].cursor = wm;
1140 break;
1141 case DRM_PLANE_TYPE_PRIMARY:
1142 wm_state->wm[level].primary = wm;
1143 break;
1144 case DRM_PLANE_TYPE_OVERLAY:
1145 sprite = plane->plane;
1146 wm_state->wm[level].sprite[sprite] = wm;
1147 break;
1148 }
1149 }
1150
1151 wm_state->num_levels = level;
1152
1153 if (!wm_state->cxsr)
1154 continue;
1155
1156 /* maxfifo watermarks */
1157 switch (plane->base.type) {
1158 int sprite, level;
1159 case DRM_PLANE_TYPE_CURSOR:
1160 for (level = 0; level < wm_state->num_levels; level++)
1161 wm_state->sr[level].cursor =
5a37ed0a 1162 wm_state->wm[level].cursor;
262cd2e1
VS		 1163 break;
1164 case DRM_PLANE_TYPE_PRIMARY:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].plane =
1167 min(wm_state->sr[level].plane,
1168 wm_state->wm[level].primary);
1169 break;
1170 case DRM_PLANE_TYPE_OVERLAY:
1171 sprite = plane->plane;
1172 for (level = 0; level < wm_state->num_levels; level++)
1173 wm_state->sr[level].plane =
1174 min(wm_state->sr[level].plane,
1175 wm_state->wm[level].sprite[sprite]);
1176 break;
1177 }
1178 }
1179
1180 /* clear any (partially) filled invalid levels */
58590c14 1181 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1182 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1183 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1184 }
1185
1186 vlv_invert_wms(crtc);
1187}
1188
54f1b6e1
VS		 1189#define VLV_FIFO(plane, value) \
1190 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1191
1192static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1193{
1194 struct drm_device *dev = crtc->base.dev;
1195 struct drm_i915_private *dev_priv = to_i915(dev);
1196 struct intel_plane *plane;
1197 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1198
1199 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1200 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1201 WARN_ON(plane->wm.fifo_size != 63);
1202 continue;
1203 }
1204
1205 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1206 sprite0_start = plane->wm.fifo_size;
1207 else if (plane->plane == 0)
1208 sprite1_start = sprite0_start + plane->wm.fifo_size;
1209 else
1210 fifo_size = sprite1_start + plane->wm.fifo_size;
1211 }
1212
1213 WARN_ON(fifo_size != 512 - 1);
1214
1215 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1216 pipe_name(crtc->pipe), sprite0_start,
1217 sprite1_start, fifo_size);
1218
1219 switch (crtc->pipe) {
1220 uint32_t dsparb, dsparb2, dsparb3;
1221 case PIPE_A:
1222 dsparb = I915_READ(DSPARB);
1223 dsparb2 = I915_READ(DSPARB2);
1224
1225 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1226 VLV_FIFO(SPRITEB, 0xff));
1227 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1228 VLV_FIFO(SPRITEB, sprite1_start));
1229
1230 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1231 VLV_FIFO(SPRITEB_HI, 0x1));
1232 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1233 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1234
1235 I915_WRITE(DSPARB, dsparb);
1236 I915_WRITE(DSPARB2, dsparb2);
1237 break;
1238 case PIPE_B:
1239 dsparb = I915_READ(DSPARB);
1240 dsparb2 = I915_READ(DSPARB2);
1241
1242 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1243 VLV_FIFO(SPRITED, 0xff));
1244 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1245 VLV_FIFO(SPRITED, sprite1_start));
1246
1247 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1248 VLV_FIFO(SPRITED_HI, 0xff));
1249 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1250 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1251
1252 I915_WRITE(DSPARB, dsparb);
1253 I915_WRITE(DSPARB2, dsparb2);
1254 break;
1255 case PIPE_C:
1256 dsparb3 = I915_READ(DSPARB3);
1257 dsparb2 = I915_READ(DSPARB2);
1258
1259 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1260 VLV_FIFO(SPRITEF, 0xff));
1261 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1262 VLV_FIFO(SPRITEF, sprite1_start));
1263
1264 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1265 VLV_FIFO(SPRITEF_HI, 0xff));
1266 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1267 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1268
1269 I915_WRITE(DSPARB3, dsparb3);
1270 I915_WRITE(DSPARB2, dsparb2);
1271 break;
1272 default:
1273 break;
1274 }
1275}
1276
1277#undef VLV_FIFO
1278
262cd2e1
VS		 1279static void vlv_merge_wm(struct drm_device *dev,
1280 struct vlv_wm_values *wm)
1281{
1282 struct intel_crtc *crtc;
1283 int num_active_crtcs = 0;
1284
58590c14 1285 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1286 wm->cxsr = true;
1287
1288 for_each_intel_crtc(dev, crtc) {
1289 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1290
1291 if (!crtc->active)
1292 continue;
1293
1294 if (!wm_state->cxsr)
1295 wm->cxsr = false;
1296
1297 num_active_crtcs++;
1298 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1299 }
1300
1301 if (num_active_crtcs != 1)
1302 wm->cxsr = false;
1303
6f9c784b
VS		 1304 if (num_active_crtcs > 1)
1305 wm->level = VLV_WM_LEVEL_PM2;
1306
262cd2e1
VS		 1307 for_each_intel_crtc(dev, crtc) {
1308 struct vlv_wm_state *wm_state = &crtc->wm_state;
1309 enum pipe pipe = crtc->pipe;
1310
1311 if (!crtc->active)
1312 continue;
1313
1314 wm->pipe[pipe] = wm_state->wm[wm->level];
1315 if (wm->cxsr)
1316 wm->sr = wm_state->sr[wm->level];
1317
1318 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1319 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1320 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1321 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1322 }
1323}
1324
1325static void vlv_update_wm(struct drm_crtc *crtc)
1326{
1327 struct drm_device *dev = crtc->dev;
1328 struct drm_i915_private *dev_priv = dev->dev_private;
1329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1330 enum pipe pipe = intel_crtc->pipe;
1331 struct vlv_wm_values wm = {};
1332
26e1fe4f 1333 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1334 vlv_merge_wm(dev, &wm);
1335
54f1b6e1
VS		 1336 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1339 return;
54f1b6e1 1340 }
262cd2e1
VS		 1341
1342 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, false);
1345
1346 if (wm.level < VLV_WM_LEVEL_PM5 &&
1347 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1348 chv_set_memory_pm5(dev_priv, false);
1349
852eb00d 1350 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1351 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1352
54f1b6e1
VS		 1353 /* FIXME should be part of crtc atomic commit */
1354 vlv_pipe_set_fifo_size(intel_crtc);
1355
262cd2e1
VS		 1356 vlv_write_wm_values(intel_crtc, &wm);
1357
1358 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1359 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1360 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1361 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1362 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1363
852eb00d 1364 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1365 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1366
1367 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1368 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1369 chv_set_memory_pm5(dev_priv, true);
1370
1371 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1372 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1373 chv_set_memory_dvfs(dev_priv, true);
1374
1375 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1376}
1377
ae80152d
VS		 1378#define single_plane_enabled(mask) is_power_of_2(mask)
1379
46ba614c 1380static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1381{
46ba614c 1382 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1383 static const int sr_latency_ns = 12000;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
9858425c 1388 bool cxsr_enabled;
b445e3b0 1389
51cea1f4 1390 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1391 &g4x_wm_info, pessimal_latency_ns,
1392 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1393 &planea_wm, &cursora_wm))
51cea1f4 1394 enabled |= 1 << PIPE_A;
b445e3b0 1395
51cea1f4 1396 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1397 &g4x_wm_info, pessimal_latency_ns,
1398 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1399 &planeb_wm, &cursorb_wm))
51cea1f4 1400 enabled |= 1 << PIPE_B;
b445e3b0 1401
b445e3b0
ED		 1402 if (single_plane_enabled(enabled) &&
1403 g4x_compute_srwm(dev, ffs(enabled) - 1,
1404 sr_latency_ns,
1405 &g4x_wm_info,
1406 &g4x_cursor_wm_info,
52bd02d8 1407 &plane_sr, &cursor_sr)) {
9858425c 1408 cxsr_enabled = true;
52bd02d8 1409 } else {
9858425c 1410 cxsr_enabled = false;
5209b1f4 1411 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1412 plane_sr = cursor_sr = 0;
1413 }
b445e3b0 1414
a5043453
VS		 1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1417 planea_wm, cursora_wm,
1418 planeb_wm, cursorb_wm,
1419 plane_sr, cursor_sr);
1420
1421 I915_WRITE(DSPFW1,
f4998963
VS		 1422 FW_WM(plane_sr, SR) |
1423 FW_WM(cursorb_wm, CURSORB) |
1424 FW_WM(planeb_wm, PLANEB) |
1425 FW_WM(planea_wm, PLANEA));
b445e3b0 1426 I915_WRITE(DSPFW2,
8c919b28 1427 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1428 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1429 /* HPLL off in SR has some issues on G4x... disable it */
1430 I915_WRITE(DSPFW3,
8c919b28 1431 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1432 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1433
1434 if (cxsr_enabled)
1435 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1436}
1437
46ba614c 1438static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1439{
46ba614c 1440 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1441 struct drm_i915_private *dev_priv = dev->dev_private;
1442 struct drm_crtc *crtc;
1443 int srwm = 1;
1444 int cursor_sr = 16;
9858425c 1445 bool cxsr_enabled;
b445e3b0
ED		 1446
1447 /* Calc sr entries for one plane configs */
1448 crtc = single_enabled_crtc(dev);
1449 if (crtc) {
1450 /* self-refresh has much higher latency */
1451 static const int sr_latency_ns = 12000;
124abe07 1452 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1453 int clock = adjusted_mode->crtc_clock;
fec8cba3 1454 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1455 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1456 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1457 unsigned long line_time_us;
1458 int entries;
1459
922044c9 1460 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1461
1462 /* Use ns/us then divide to preserve precision */
1463 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1464 cpp * hdisplay;
b445e3b0
ED		 1465 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1466 srwm = I965_FIFO_SIZE - entries;
1467 if (srwm < 0)
1468 srwm = 1;
1469 srwm &= 0x1ff;
1470 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1471 entries, srwm);
1472
1473 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1474 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1475 entries = DIV_ROUND_UP(entries,
1476 i965_cursor_wm_info.cacheline_size);
1477 cursor_sr = i965_cursor_wm_info.fifo_size -
1478 (entries + i965_cursor_wm_info.guard_size);
1479
1480 if (cursor_sr > i965_cursor_wm_info.max_wm)
1481 cursor_sr = i965_cursor_wm_info.max_wm;
1482
1483 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1484 "cursor %d\n", srwm, cursor_sr);
1485
9858425c 1486 cxsr_enabled = true;
b445e3b0 1487 } else {
9858425c 1488 cxsr_enabled = false;
b445e3b0 1489 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1490 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1491 }
1492
1493 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1494 srwm);
1495
1496 /* 965 has limitations... */
f4998963
VS		 1497 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1498 FW_WM(8, CURSORB) |
1499 FW_WM(8, PLANEB) |
1500 FW_WM(8, PLANEA));
1501 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1502 FW_WM(8, PLANEC_OLD));
b445e3b0 1503 /* update cursor SR watermark */
f4998963 1504 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1505
1506 if (cxsr_enabled)
1507 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1508}
1509
f4998963
VS		 1510#undef FW_WM
1511
46ba614c 1512static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1513{
46ba614c 1514 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1515 struct drm_i915_private *dev_priv = dev->dev_private;
1516 const struct intel_watermark_params *wm_info;
1517 uint32_t fwater_lo;
1518 uint32_t fwater_hi;
1519 int cwm, srwm = 1;
1520 int fifo_size;
1521 int planea_wm, planeb_wm;
1522 struct drm_crtc *crtc, *enabled = NULL;
1523
1524 if (IS_I945GM(dev))
1525 wm_info = &i945_wm_info;
1526 else if (!IS_GEN2(dev))
1527 wm_info = &i915_wm_info;
1528 else
9d539105 1529 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1530
1531 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1532 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1533 if (intel_crtc_active(crtc)) {
241bfc38 1534 const struct drm_display_mode *adjusted_mode;
ac484963 1535 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1536 if (IS_GEN2(dev))
1537 cpp = 4;
1538
6e3c9717 1539 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1540 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1541 wm_info, fifo_size, cpp,
5aef6003 1542 pessimal_latency_ns);
b445e3b0 1543 enabled = crtc;
9d539105 1544 } else {
b445e3b0 1545 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1546 if (planea_wm > (long)wm_info->max_wm)
1547 planea_wm = wm_info->max_wm;
1548 }
1549
1550 if (IS_GEN2(dev))
1551 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1552
1553 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1555 if (intel_crtc_active(crtc)) {
241bfc38 1556 const struct drm_display_mode *adjusted_mode;
ac484963 1557 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1558 if (IS_GEN2(dev))
1559 cpp = 4;
1560
6e3c9717 1561 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1562 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1563 wm_info, fifo_size, cpp,
5aef6003 1564 pessimal_latency_ns);
b445e3b0
ED		 1565 if (enabled == NULL)
1566 enabled = crtc;
1567 else
1568 enabled = NULL;
9d539105 1569 } else {
b445e3b0 1570 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1571 if (planeb_wm > (long)wm_info->max_wm)
1572 planeb_wm = wm_info->max_wm;
1573 }
b445e3b0
ED		 1574
1575 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1576
2ab1bc9d 1577 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1578 struct drm_i915_gem_object *obj;
2ab1bc9d 1579
59bea882 1580 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1581
1582 /* self-refresh seems busted with untiled */
2ff8fde1 1583 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1584 enabled = NULL;
1585 }
1586
b445e3b0
ED		 1587 /*
1588 * Overlay gets an aggressive default since video jitter is bad.
1589 */
1590 cwm = 2;
1591
1592 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1593 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1594
1595 /* Calc sr entries for one plane configs */
1596 if (HAS_FW_BLC(dev) && enabled) {
1597 /* self-refresh has much higher latency */
1598 static const int sr_latency_ns = 6000;
124abe07 1599 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1600 int clock = adjusted_mode->crtc_clock;
fec8cba3 1601 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1602 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1603 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1604 unsigned long line_time_us;
1605 int entries;
1606
922044c9 1607 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1608
1609 /* Use ns/us then divide to preserve precision */
1610 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1611 cpp * hdisplay;
b445e3b0
ED		 1612 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1613 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1614 srwm = wm_info->fifo_size - entries;
1615 if (srwm < 0)
1616 srwm = 1;
1617
1618 if (IS_I945G(dev) || IS_I945GM(dev))
1619 I915_WRITE(FW_BLC_SELF,
1620 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1621 else if (IS_I915GM(dev))
1622 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1623 }
1624
1625 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1626 planea_wm, planeb_wm, cwm, srwm);
1627
1628 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1629 fwater_hi = (cwm & 0x1f);
1630
1631 /* Set request length to 8 cachelines per fetch */
1632 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1633 fwater_hi = fwater_hi | (1 << 8);
1634
1635 I915_WRITE(FW_BLC, fwater_lo);
1636 I915_WRITE(FW_BLC2, fwater_hi);
1637
5209b1f4
ID		 1638 if (enabled)
1639 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1640}
1641
feb56b93 1642static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1643{
46ba614c 1644 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646 struct drm_crtc *crtc;
241bfc38 1647 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1648 uint32_t fwater_lo;
1649 int planea_wm;
1650
1651 crtc = single_enabled_crtc(dev);
1652 if (crtc == NULL)
1653 return;
1654
6e3c9717 1655 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1656 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1657 &i845_wm_info,
b445e3b0 1658 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1659 4, pessimal_latency_ns);
b445e3b0
ED		 1660 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1661 fwater_lo |= (3<<8) | planea_wm;
1662
1663 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1664
1665 I915_WRITE(FW_BLC, fwater_lo);
1666}
1667
8cfb3407 1668uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1669{
fd4daa9c 1670 uint32_t pixel_rate;
801bcfff 1671
8cfb3407 1672 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1673
1674 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1675 * adjust the pixel_rate here. */
1676
8cfb3407 1677 if (pipe_config->pch_pfit.enabled) {
801bcfff 1678 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1679 uint32_t pfit_size = pipe_config->pch_pfit.size;
1680
1681 pipe_w = pipe_config->pipe_src_w;
1682 pipe_h = pipe_config->pipe_src_h;
801bcfff 1683
801bcfff
PZ		 1684 pfit_w = (pfit_size >> 16) & 0xFFFF;
1685 pfit_h = pfit_size & 0xFFFF;
1686 if (pipe_w < pfit_w)
1687 pipe_w = pfit_w;
1688 if (pipe_h < pfit_h)
1689 pipe_h = pfit_h;
1690
15126882
MR		 1691 if (WARN_ON(!pfit_w || !pfit_h))
1692 return pixel_rate;
1693
801bcfff
PZ		 1694 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1695 pfit_w * pfit_h);
1696 }
1697
1698 return pixel_rate;
1699}
1700
37126462 1701/* latency must be in 0.1us units. */
ac484963 1702static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1703{
1704 uint64_t ret;
1705
3312ba65
VS		 1706 if (WARN(latency == 0, "Latency value missing\n"))
1707 return UINT_MAX;
1708
ac484963 1709 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1710 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1711
1712 return ret;
1713}
1714
37126462 1715/* latency must be in 0.1us units. */
23297044 1716static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1717 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1718 uint32_t latency)
1719{
1720 uint32_t ret;
1721
3312ba65
VS		 1722 if (WARN(latency == 0, "Latency value missing\n"))
1723 return UINT_MAX;
15126882
MR		 1724 if (WARN_ON(!pipe_htotal))
1725 return UINT_MAX;
3312ba65 1726
801bcfff 1727 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1728 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1729 ret = DIV_ROUND_UP(ret, 64) + 2;
1730 return ret;
1731}
1732
23297044 1733static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1734 uint8_t cpp)
cca32e9a 1735{
15126882
MR		 1736 /*
1737 * Neither of these should be possible since this function shouldn't be
1738 * called if the CRTC is off or the plane is invisible. But let's be
1739 * extra paranoid to avoid a potential divide-by-zero if we screw up
1740 * elsewhere in the driver.
1741 */
ac484963 1742 if (WARN_ON(!cpp))
15126882
MR		 1743 return 0;
1744 if (WARN_ON(!horiz_pixels))
1745 return 0;
1746
ac484963 1747 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1748}
1749
820c1980 1750struct ilk_wm_maximums {
cca32e9a
PZ		 1751 uint16_t pri;
1752 uint16_t spr;
1753 uint16_t cur;
1754 uint16_t fbc;
1755};
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1763 uint32_t mem_value,
1764 bool is_lp)
801bcfff 1765{
ac484963
VS		 1766 int cpp = pstate->base.fb ?
1767 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1768 uint32_t method1, method2;
1769
7221fc33 1770 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1771 return 0;
1772
ac484963 1773 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1774
1775 if (!is_lp)
1776 return method1;
1777
7221fc33
MR		 1778 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1779 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1780 drm_rect_width(&pstate->dst),
ac484963 1781 cpp, mem_value);
cca32e9a
PZ		 1782
1783 return min(method1, method2);
801bcfff
PZ		 1784}
1785
37126462
VS		 1786/*
1787 * For both WM_PIPE and WM_LP.
1788 * mem_value must be in 0.1us units.
1789 */
7221fc33 1790static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1791 const struct intel_plane_state *pstate,
801bcfff
PZ		 1792 uint32_t mem_value)
1793{
ac484963
VS		 1794 int cpp = pstate->base.fb ?
1795 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1796 uint32_t method1, method2;
1797
7221fc33 1798 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1799 return 0;
1800
ac484963 1801 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1802 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1803 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1804 drm_rect_width(&pstate->dst),
ac484963 1805 cpp, mem_value);
801bcfff
PZ		 1806 return min(method1, method2);
1807}
1808
37126462
VS		 1809/*
1810 * For both WM_PIPE and WM_LP.
1811 * mem_value must be in 0.1us units.
1812 */
7221fc33 1813static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1814 const struct intel_plane_state *pstate,
801bcfff
PZ		 1815 uint32_t mem_value)
1816{
b2435692
MR		 1817 /*
1818 * We treat the cursor plane as always-on for the purposes of watermark
1819 * calculation. Until we have two-stage watermark programming merged,
1820 * this is necessary to avoid flickering.
1821 */
1822 int cpp = 4;
1823 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1824
b2435692 1825 if (!cstate->base.active)
801bcfff
PZ		 1826 return 0;
1827
7221fc33
MR		 1828 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1829 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1830 width, cpp, mem_value);
801bcfff
PZ		 1831}
1832
cca32e9a 1833/* Only for WM_LP. */
7221fc33 1834static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1835 const struct intel_plane_state *pstate,
1fda9882 1836 uint32_t pri_val)
cca32e9a 1837{
ac484963
VS		 1838 int cpp = pstate->base.fb ?
1839 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1840
7221fc33 1841 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1842 return 0;
1843
ac484963 1844 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1845}
1846
158ae64f
VS		 1847static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1848{
416f4727
VS		 1849 if (INTEL_INFO(dev)->gen >= 8)
1850 return 3072;
1851 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1852 return 768;
1853 else
1854 return 512;
1855}
1856
4e975081
VS		 1857static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1858 int level, bool is_sprite)
1859{
1860 if (INTEL_INFO(dev)->gen >= 8)
1861 /* BDW primary/sprite plane watermarks */
1862 return level == 0 ? 255 : 2047;
1863 else if (INTEL_INFO(dev)->gen >= 7)
1864 /* IVB/HSW primary/sprite plane watermarks */
1865 return level == 0 ? 127 : 1023;
1866 else if (!is_sprite)
1867 /* ILK/SNB primary plane watermarks */
1868 return level == 0 ? 127 : 511;
1869 else
1870 /* ILK/SNB sprite plane watermarks */
1871 return level == 0 ? 63 : 255;
1872}
1873
1874static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1875 int level)
1876{
1877 if (INTEL_INFO(dev)->gen >= 7)
1878 return level == 0 ? 63 : 255;
1879 else
1880 return level == 0 ? 31 : 63;
1881}
1882
1883static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1884{
1885 if (INTEL_INFO(dev)->gen >= 8)
1886 return 31;
1887 else
1888 return 15;
1889}
1890
158ae64f
VS		 1891/* Calculate the maximum primary/sprite plane watermark */
1892static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1893 int level,
240264f4 1894 const struct intel_wm_config *config,
158ae64f
VS		 1895 enum intel_ddb_partitioning ddb_partitioning,
1896 bool is_sprite)
1897{
1898 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1899
1900 /* if sprites aren't enabled, sprites get nothing */
240264f4 1901 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1902 return 0;
1903
1904 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1905 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1906 fifo_size /= INTEL_INFO(dev)->num_pipes;
1907
1908 /*
1909 * For some reason the non self refresh
1910 * FIFO size is only half of the self
1911 * refresh FIFO size on ILK/SNB.
1912 */
1913 if (INTEL_INFO(dev)->gen <= 6)
1914 fifo_size /= 2;
1915 }
1916
240264f4 1917 if (config->sprites_enabled) {
158ae64f
VS		 1918 /* level 0 is always calculated with 1:1 split */
1919 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1920 if (is_sprite)
1921 fifo_size *= 5;
1922 fifo_size /= 6;
1923 } else {
1924 fifo_size /= 2;
1925 }
1926 }
1927
1928 /* clamp to max that the registers can hold */
4e975081 1929 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1930}
1931
1932/* Calculate the maximum cursor plane watermark */
1933static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1934 int level,
1935 const struct intel_wm_config *config)
158ae64f
VS		 1936{
1937 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1938 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1939 return 64;
1940
1941 /* otherwise just report max that registers can hold */
4e975081 1942 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1943}
1944
d34ff9c6 1945static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1946 int level,
1947 const struct intel_wm_config *config,
1948 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1949 struct ilk_wm_maximums *max)
158ae64f 1950{
240264f4
VS		 1951 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1952 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1953 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1954 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1955}
1956
a3cb4048
VS		 1957static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1958 int level,
1959 struct ilk_wm_maximums *max)
1960{
1961 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1962 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1963 max->cur = ilk_cursor_wm_reg_max(dev, level);
1964 max->fbc = ilk_fbc_wm_reg_max(dev);
1965}
1966
d9395655 1967static bool ilk_validate_wm_level(int level,
820c1980 1968 const struct ilk_wm_maximums *max,
d9395655 1969 struct intel_wm_level *result)
a9786a11
VS		 1970{
1971 bool ret;
1972
1973 /* already determined to be invalid? */
1974 if (!result->enable)
1975 return false;
1976
1977 result->enable = result->pri_val <= max->pri &&
1978 result->spr_val <= max->spr &&
1979 result->cur_val <= max->cur;
1980
1981 ret = result->enable;
1982
1983 /*
1984 * HACK until we can pre-compute everything,
1985 * and thus fail gracefully if LP0 watermarks
1986 * are exceeded...
1987 */
1988 if (level == 0 && !result->enable) {
1989 if (result->pri_val > max->pri)
1990 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1991 level, result->pri_val, max->pri);
1992 if (result->spr_val > max->spr)
1993 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1994 level, result->spr_val, max->spr);
1995 if (result->cur_val > max->cur)
1996 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1997 level, result->cur_val, max->cur);
1998
1999 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2000 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2001 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2002 result->enable = true;
2003 }
2004
a9786a11
VS		 2005 return ret;
2006}
2007
d34ff9c6 2008static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2009 const struct intel_crtc *intel_crtc,
6f5ddd17 2010 int level,
7221fc33 2011 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2012 struct intel_plane_state *pristate,
2013 struct intel_plane_state *sprstate,
2014 struct intel_plane_state *curstate,
1fd527cc 2015 struct intel_wm_level *result)
6f5ddd17
VS		 2016{
2017 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2018 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2019 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2020
2021 /* WM1+ latency values stored in 0.5us units */
2022 if (level > 0) {
2023 pri_latency *= 5;
2024 spr_latency *= 5;
2025 cur_latency *= 5;
2026 }
2027
e3bddded
ML		 2028 if (pristate) {
2029 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2030 pri_latency, level);
2031 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2032 }
2033
2034 if (sprstate)
2035 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2036
2037 if (curstate)
2038 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2039
6f5ddd17
VS		 2040 result->enable = true;
2041}
2042
801bcfff 2043static uint32_t
532f7a7f 2044hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2045{
532f7a7f
VS		 2046 const struct intel_atomic_state *intel_state =
2047 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2048 const struct drm_display_mode *adjusted_mode =
2049 &cstate->base.adjusted_mode;
85a02deb 2050 u32 linetime, ips_linetime;
1f8eeabf 2051
ee91a159
MR		 2052 if (!cstate->base.active)
2053 return 0;
2054 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2055 return 0;
532f7a7f 2056 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2057 return 0;
1011d8c4 2058
1f8eeabf
ED		 2059 /* The WM are computed with base on how long it takes to fill a single
2060 * row at the given clock rate, multiplied by 8.
2061 * */
124abe07
VS		 2062 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2063 adjusted_mode->crtc_clock);
2064 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2065 intel_state->cdclk);
1f8eeabf 2066
801bcfff
PZ		 2067 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2068 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2069}
2070
2af30a5c 2071static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2072{
2073 struct drm_i915_private *dev_priv = dev->dev_private;
2074
2af30a5c
PB		 2075 if (IS_GEN9(dev)) {
2076 uint32_t val;
4f947386 2077 int ret, i;
367294be 2078 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2079
2080 /* read the first set of memory latencies[0:3] */
2081 val = 0; /* data0 to be programmed to 0 for first set */
2082 mutex_lock(&dev_priv->rps.hw_lock);
2083 ret = sandybridge_pcode_read(dev_priv,
2084 GEN9_PCODE_READ_MEM_LATENCY,
2085 &val);
2086 mutex_unlock(&dev_priv->rps.hw_lock);
2087
2088 if (ret) {
2089 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2090 return;
2091 }
2092
2093 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2097 GEN9_MEM_LATENCY_LEVEL_MASK;
2098 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2099 GEN9_MEM_LATENCY_LEVEL_MASK;
2100
2101 /* read the second set of memory latencies[4:7] */
2102 val = 1; /* data0 to be programmed to 1 for second set */
2103 mutex_lock(&dev_priv->rps.hw_lock);
2104 ret = sandybridge_pcode_read(dev_priv,
2105 GEN9_PCODE_READ_MEM_LATENCY,
2106 &val);
2107 mutex_unlock(&dev_priv->rps.hw_lock);
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
367294be 2121 /*
6f97235b
DL		 2122 * WaWmMemoryReadLatency:skl
2123 *
367294be
VK		 2124 * punit doesn't take into account the read latency so we need
2125 * to add 2us to the various latency levels we retrieve from
2126 * the punit.
2127 * - W0 is a bit special in that it's the only level that
2128 * can't be disabled if we want to have display working, so
2129 * we always add 2us there.
2130 * - For levels >=1, punit returns 0us latency when they are
2131 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2132 *
2133 * Additionally, if a level n (n > 1) has a 0us latency, all
2134 * levels m (m >= n) need to be disabled. We make sure to
2135 * sanitize the values out of the punit to satisfy this
2136 * requirement.
367294be
VK		 2137 */
2138 wm[0] += 2;
2139 for (level = 1; level <= max_level; level++)
2140 if (wm[level] != 0)
2141 wm[level] += 2;
4f947386
VK		 2142 else {
2143 for (i = level + 1; i <= max_level; i++)
2144 wm[i] = 0;
367294be 2145
4f947386
VK		 2146 break;
2147 }
2af30a5c 2148 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2149 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2150
2151 wm[0] = (sskpd >> 56) & 0xFF;
2152 if (wm[0] == 0)
2153 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2154 wm[1] = (sskpd >> 4) & 0xFF;
2155 wm[2] = (sskpd >> 12) & 0xFF;
2156 wm[3] = (sskpd >> 20) & 0x1FF;
2157 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2158 } else if (INTEL_INFO(dev)->gen >= 6) {
2159 uint32_t sskpd = I915_READ(MCH_SSKPD);
2160
2161 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2162 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2163 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2164 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2165 } else if (INTEL_INFO(dev)->gen >= 5) {
2166 uint32_t mltr = I915_READ(MLTR_ILK);
2167
2168 /* ILK primary LP0 latency is 700 ns */
2169 wm[0] = 7;
2170 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2171 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2172 }
2173}
2174
53615a5e
VS		 2175static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2176{
2177 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2178 if (IS_GEN5(dev))
53615a5e
VS		 2179 wm[0] = 13;
2180}
2181
2182static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2183{
2184 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2185 if (IS_GEN5(dev))
53615a5e
VS		 2186 wm[0] = 13;
2187
2188 /* WaDoubleCursorLP3Latency:ivb */
2189 if (IS_IVYBRIDGE(dev))
2190 wm[3] *= 2;
2191}
2192
546c81fd 2193int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2194{
26ec971e 2195 /* how many WM levels are we expecting */
b6e742f6 2196 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2197 return 7;
2198 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2199 return 4;
26ec971e 2200 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2201 return 3;
26ec971e 2202 else
ad0d6dc4
VS		 2203 return 2;
2204}
7526ed79 2205
ad0d6dc4
VS		 2206static void intel_print_wm_latency(struct drm_device *dev,
2207 const char *name,
2af30a5c 2208 const uint16_t wm[8])
ad0d6dc4
VS		 2209{
2210 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2211
2212 for (level = 0; level <= max_level; level++) {
2213 unsigned int latency = wm[level];
2214
2215 if (latency == 0) {
2216 DRM_ERROR("%s WM%d latency not provided\n",
2217 name, level);
2218 continue;
2219 }
2220
2af30a5c
PB		 2221 /*
2222 * - latencies are in us on gen9.
2223 * - before then, WM1+ latency values are in 0.5us units
2224 */
2225 if (IS_GEN9(dev))
2226 latency *= 10;
2227 else if (level > 0)
26ec971e
VS		 2228 latency *= 5;
2229
2230 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2231 name, level, wm[level],
2232 latency / 10, latency % 10);
2233 }
2234}
2235
e95a2f75
VS		 2236static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2237 uint16_t wm[5], uint16_t min)
2238{
2239 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2240
2241 if (wm[0] >= min)
2242 return false;
2243
2244 wm[0] = max(wm[0], min);
2245 for (level = 1; level <= max_level; level++)
2246 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2247
2248 return true;
2249}
2250
2251static void snb_wm_latency_quirk(struct drm_device *dev)
2252{
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 bool changed;
2255
2256 /*
2257 * The BIOS provided WM memory latency values are often
2258 * inadequate for high resolution displays. Adjust them.
2259 */
2260 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2261 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2262 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2263
2264 if (!changed)
2265 return;
2266
2267 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2268 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2269 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2270 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2271}
2272
fa50ad61 2273static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2278
2279 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2280 sizeof(dev_priv->wm.pri_latency));
2281 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2282 sizeof(dev_priv->wm.pri_latency));
2283
2284 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2285 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2286
2287 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2288 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2289 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2290
2291 if (IS_GEN6(dev))
2292 snb_wm_latency_quirk(dev);
53615a5e
VS		 2293}
2294
2af30a5c
PB		 2295static void skl_setup_wm_latency(struct drm_device *dev)
2296{
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298
2299 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2300 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2301}
2302
ed4a6a7c
MR		 2303static bool ilk_validate_pipe_wm(struct drm_device *dev,
2304 struct intel_pipe_wm *pipe_wm)
2305{
2306 /* LP0 watermark maximums depend on this pipe alone */
2307 const struct intel_wm_config config = {
2308 .num_pipes_active = 1,
2309 .sprites_enabled = pipe_wm->sprites_enabled,
2310 .sprites_scaled = pipe_wm->sprites_scaled,
2311 };
2312 struct ilk_wm_maximums max;
2313
2314 /* LP0 watermarks always use 1/2 DDB partitioning */
2315 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2316
2317 /* At least LP0 must be valid */
2318 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2319 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2320 return false;
2321 }
2322
2323 return true;
2324}
2325
0b2ae6d7 2326/* Compute new watermarks for the pipe */
e3bddded 2327static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2328{
e3bddded
ML		 2329 struct drm_atomic_state *state = cstate->base.state;
2330 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2331 struct intel_pipe_wm *pipe_wm;
e3bddded 2332 struct drm_device *dev = state->dev;
d34ff9c6 2333 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2334 struct intel_plane *intel_plane;
86c8bbbe 2335 struct intel_plane_state *pristate = NULL;
43d59eda 2336 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2337 struct intel_plane_state *curstate = NULL;
d81f04c5 2338 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2339 struct ilk_wm_maximums max;
0b2ae6d7 2340
e8f1f02e 2341 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2342
43d59eda 2343 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2344 struct intel_plane_state *ps;
2345
2346 ps = intel_atomic_get_existing_plane_state(state,
2347 intel_plane);
2348 if (!ps)
2349 continue;
86c8bbbe
MR		 2350
2351 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2352 pristate = ps;
86c8bbbe 2353 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2354 sprstate = ps;
86c8bbbe 2355 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2356 curstate = ps;
43d59eda
MR		 2357 }
2358
ed4a6a7c 2359 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2360 if (sprstate) {
2361 pipe_wm->sprites_enabled = sprstate->visible;
2362 pipe_wm->sprites_scaled = sprstate->visible &&
2363 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2364 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2365 }
2366
d81f04c5
ML		 2367 usable_level = max_level;
2368
7b39a0b7 2369 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2370 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2371 usable_level = 1;
7b39a0b7
VS		 2372
2373 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2374 if (pipe_wm->sprites_scaled)
d81f04c5 2375 usable_level = 0;
7b39a0b7 2376
86c8bbbe 2377 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2378 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2379
2380 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2381 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2382
a42a5719 2383 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2384 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2385
ed4a6a7c 2386 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2387 return -EINVAL;
a3cb4048
VS		 2388
2389 ilk_compute_wm_reg_maximums(dev, 1, &max);
2390
2391 for (level = 1; level <= max_level; level++) {
71f0a626 2392 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2393
86c8bbbe 2394 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2395 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2396
2397 /*
2398 * Disable any watermark level that exceeds the
2399 * register maximums since such watermarks are
2400 * always invalid.
2401 */
71f0a626
ML		 2402 if (level > usable_level)
2403 continue;
2404
2405 if (ilk_validate_wm_level(level, &max, wm))
2406 pipe_wm->wm[level] = *wm;
2407 else
d81f04c5 2408 usable_level = level;
a3cb4048
VS		 2409 }
2410
86c8bbbe 2411 return 0;
0b2ae6d7
VS		 2412}
2413
ed4a6a7c
MR		 2414/*
2415 * Build a set of 'intermediate' watermark values that satisfy both the old
2416 * state and the new state. These can be programmed to the hardware
2417 * immediately.
2418 */
2419static int ilk_compute_intermediate_wm(struct drm_device *dev,
2420 struct intel_crtc *intel_crtc,
2421 struct intel_crtc_state *newstate)
2422{
e8f1f02e 2423 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2424 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2425 int level, max_level = ilk_wm_max_level(dev);
2426
2427 /*
2428 * Start with the final, target watermarks, then combine with the
2429 * currently active watermarks to get values that are safe both before
2430 * and after the vblank.
2431 */
e8f1f02e 2432 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2433 a->pipe_enabled |= b->pipe_enabled;
2434 a->sprites_enabled |= b->sprites_enabled;
2435 a->sprites_scaled |= b->sprites_scaled;
2436
2437 for (level = 0; level <= max_level; level++) {
2438 struct intel_wm_level *a_wm = &a->wm[level];
2439 const struct intel_wm_level *b_wm = &b->wm[level];
2440
2441 a_wm->enable &= b_wm->enable;
2442 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2443 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2444 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2445 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2446 }
2447
2448 /*
2449 * We need to make sure that these merged watermark values are
2450 * actually a valid configuration themselves. If they're not,
2451 * there's no safe way to transition from the old state to
2452 * the new state, so we need to fail the atomic transaction.
2453 */
2454 if (!ilk_validate_pipe_wm(dev, a))
2455 return -EINVAL;
2456
2457 /*
2458 * If our intermediate WM are identical to the final WM, then we can
2459 * omit the post-vblank programming; only update if it's different.
2460 */
e8f1f02e 2461 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2462 newstate->wm.need_postvbl_update = false;
2463
2464 return 0;
2465}
2466
0b2ae6d7
VS		 2467/*
2468 * Merge the watermarks from all active pipes for a specific level.
2469 */
2470static void ilk_merge_wm_level(struct drm_device *dev,
2471 int level,
2472 struct intel_wm_level *ret_wm)
2473{
2474 const struct intel_crtc *intel_crtc;
2475
d52fea5b
VS		 2476 ret_wm->enable = true;
2477
d3fcc808 2478 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2479 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2480 const struct intel_wm_level *wm = &active->wm[level];
2481
2482 if (!active->pipe_enabled)
2483 continue;
0b2ae6d7 2484
d52fea5b
VS		 2485 /*
2486 * The watermark values may have been used in the past,
2487 * so we must maintain them in the registers for some
2488 * time even if the level is now disabled.
2489 */
0b2ae6d7 2490 if (!wm->enable)
d52fea5b 2491 ret_wm->enable = false;
0b2ae6d7
VS		 2492
2493 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2494 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2495 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2496 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2497 }
0b2ae6d7
VS		 2498}
2499
2500/*
2501 * Merge all low power watermarks for all active pipes.
2502 */
2503static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2504 const struct intel_wm_config *config,
820c1980 2505 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2506 struct intel_pipe_wm *merged)
2507{
7733b49b 2508 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2509 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2510 int last_enabled_level = max_level;
0b2ae6d7 2511
0ba22e26
VS		 2512 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2513 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2514 config->num_pipes_active > 1)
1204d5ba 2515 last_enabled_level = 0;
0ba22e26 2516
6c8b6c28
VS		 2517 /* ILK: FBC WM must be disabled always */
2518 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2519
2520 /* merge each WM1+ level */
2521 for (level = 1; level <= max_level; level++) {
2522 struct intel_wm_level *wm = &merged->wm[level];
2523
2524 ilk_merge_wm_level(dev, level, wm);
2525
d52fea5b
VS		 2526 if (level > last_enabled_level)
2527 wm->enable = false;
2528 else if (!ilk_validate_wm_level(level, max, wm))
2529 /* make sure all following levels get disabled */
2530 last_enabled_level = level - 1;
0b2ae6d7
VS		 2531
2532 /*
2533 * The spec says it is preferred to disable
2534 * FBC WMs instead of disabling a WM level.
2535 */
2536 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2537 if (wm->enable)
2538 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2539 wm->fbc_val = 0;
2540 }
2541 }
6c8b6c28
VS		 2542
2543 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2544 /*
2545 * FIXME this is racy. FBC might get enabled later.
2546 * What we should check here is whether FBC can be
2547 * enabled sometime later.
2548 */
7733b49b 2549 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2550 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2551 for (level = 2; level <= max_level; level++) {
2552 struct intel_wm_level *wm = &merged->wm[level];
2553
2554 wm->enable = false;
2555 }
2556 }
0b2ae6d7
VS		 2557}
2558
b380ca3c
VS		 2559static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2560{
2561 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2562 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2563}
2564
a68d68ee
VS		 2565/* The value we need to program into the WM_LPx latency field */
2566static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2567{
2568 struct drm_i915_private *dev_priv = dev->dev_private;
2569
a42a5719 2570 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2571 return 2 * level;
2572 else
2573 return dev_priv->wm.pri_latency[level];
2574}
2575
820c1980 2576static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2577 const struct intel_pipe_wm *merged,
609cedef 2578 enum intel_ddb_partitioning partitioning,
820c1980 2579 struct ilk_wm_values *results)
801bcfff 2580{
0b2ae6d7
VS		 2581 struct intel_crtc *intel_crtc;
2582 int level, wm_lp;
cca32e9a 2583
0362c781 2584 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2585 results->partitioning = partitioning;
cca32e9a 2586
0b2ae6d7 2587 /* LP1+ register values */
cca32e9a 2588 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2589 const struct intel_wm_level *r;
801bcfff 2590
b380ca3c 2591 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2592
0362c781 2593 r = &merged->wm[level];
cca32e9a 2594
d52fea5b
VS		 2595 /*
2596 * Maintain the watermark values even if the level is
2597 * disabled. Doing otherwise could cause underruns.
2598 */
2599 results->wm_lp[wm_lp - 1] =
a68d68ee 2600 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2601 (r->pri_val << WM1_LP_SR_SHIFT) |
2602 r->cur_val;
2603
d52fea5b
VS		 2604 if (r->enable)
2605 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2606
416f4727
VS		 2607 if (INTEL_INFO(dev)->gen >= 8)
2608 results->wm_lp[wm_lp - 1] |=
2609 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2610 else
2611 results->wm_lp[wm_lp - 1] |=
2612 r->fbc_val << WM1_LP_FBC_SHIFT;
2613
d52fea5b
VS		 2614 /*
2615 * Always set WM1S_LP_EN when spr_val != 0, even if the
2616 * level is disabled. Doing otherwise could cause underruns.
2617 */
6cef2b8a
VS		 2618 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2619 WARN_ON(wm_lp != 1);
2620 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2621 } else
2622 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2623 }
801bcfff 2624
0b2ae6d7 2625 /* LP0 register values */
d3fcc808 2626 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2627 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2628 const struct intel_wm_level *r =
2629 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2630
2631 if (WARN_ON(!r->enable))
2632 continue;
2633
ed4a6a7c 2634 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2635
0b2ae6d7
VS		 2636 results->wm_pipe[pipe] =
2637 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2638 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2639 r->cur_val;
801bcfff
PZ		 2640 }
2641}
2642
861f3389
PZ		 2643/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2644 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2645static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2646 struct intel_pipe_wm *r1,
2647 struct intel_pipe_wm *r2)
861f3389 2648{
198a1e9b
VS		 2649 int level, max_level = ilk_wm_max_level(dev);
2650 int level1 = 0, level2 = 0;
861f3389 2651
198a1e9b
VS		 2652 for (level = 1; level <= max_level; level++) {
2653 if (r1->wm[level].enable)
2654 level1 = level;
2655 if (r2->wm[level].enable)
2656 level2 = level;
861f3389
PZ		 2657 }
2658
198a1e9b
VS		 2659 if (level1 == level2) {
2660 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2661 return r2;
2662 else
2663 return r1;
198a1e9b 2664 } else if (level1 > level2) {
861f3389
PZ		 2665 return r1;
2666 } else {
2667 return r2;
2668 }
2669}
2670
49a687c4
VS		 2671/* dirty bits used to track which watermarks need changes */
2672#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2673#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2674#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2675#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2676#define WM_DIRTY_FBC (1 << 24)
2677#define WM_DIRTY_DDB (1 << 25)
2678
055e393f 2679static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2680 const struct ilk_wm_values *old,
2681 const struct ilk_wm_values *new)
49a687c4
VS		 2682{
2683 unsigned int dirty = 0;
2684 enum pipe pipe;
2685 int wm_lp;
2686
055e393f 2687 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2688 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2689 dirty |= WM_DIRTY_LINETIME(pipe);
2690 /* Must disable LP1+ watermarks too */
2691 dirty |= WM_DIRTY_LP_ALL;
2692 }
2693
2694 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2695 dirty |= WM_DIRTY_PIPE(pipe);
2696 /* Must disable LP1+ watermarks too */
2697 dirty |= WM_DIRTY_LP_ALL;
2698 }
2699 }
2700
2701 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2702 dirty |= WM_DIRTY_FBC;
2703 /* Must disable LP1+ watermarks too */
2704 dirty |= WM_DIRTY_LP_ALL;
2705 }
2706
2707 if (old->partitioning != new->partitioning) {
2708 dirty |= WM_DIRTY_DDB;
2709 /* Must disable LP1+ watermarks too */
2710 dirty |= WM_DIRTY_LP_ALL;
2711 }
2712
2713 /* LP1+ watermarks already deemed dirty, no need to continue */
2714 if (dirty & WM_DIRTY_LP_ALL)
2715 return dirty;
2716
2717 /* Find the lowest numbered LP1+ watermark in need of an update... */
2718 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2719 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2720 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2721 break;
2722 }
2723
2724 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2725 for (; wm_lp <= 3; wm_lp++)
2726 dirty |= WM_DIRTY_LP(wm_lp);
2727
2728 return dirty;
2729}
2730
8553c18e
VS		 2731static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2732 unsigned int dirty)
801bcfff 2733{
820c1980 2734 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2735 bool changed = false;
801bcfff 2736
facd619b
VS		 2737 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2738 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2739 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2740 changed = true;
facd619b
VS		 2741 }
2742 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2743 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2744 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2745 changed = true;
facd619b
VS		 2746 }
2747 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2748 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2749 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2750 changed = true;
facd619b 2751 }
801bcfff 2752
facd619b
VS		 2753 /*
2754 * Don't touch WM1S_LP_EN here.
2755 * Doing so could cause underruns.
2756 */
6cef2b8a 2757
8553c18e
VS		 2758 return changed;
2759}
2760
2761/*
2762 * The spec says we shouldn't write when we don't need, because every write
2763 * causes WMs to be re-evaluated, expending some power.
2764 */
820c1980
ID		 2765static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2766 struct ilk_wm_values *results)
8553c18e
VS		 2767{
2768 struct drm_device *dev = dev_priv->dev;
820c1980 2769 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2770 unsigned int dirty;
2771 uint32_t val;
2772
055e393f 2773 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2774 if (!dirty)
2775 return;
2776
2777 _ilk_disable_lp_wm(dev_priv, dirty);
2778
49a687c4 2779 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2780 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2781 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2782 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2783 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2784 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2785
49a687c4 2786 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2787 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2788 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2789 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2790 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2791 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2792
49a687c4 2793 if (dirty & WM_DIRTY_DDB) {
a42a5719 2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2795 val = I915_READ(WM_MISC);
2796 if (results->partitioning == INTEL_DDB_PART_1_2)
2797 val &= ~WM_MISC_DATA_PARTITION_5_6;
2798 else
2799 val |= WM_MISC_DATA_PARTITION_5_6;
2800 I915_WRITE(WM_MISC, val);
2801 } else {
2802 val = I915_READ(DISP_ARB_CTL2);
2803 if (results->partitioning == INTEL_DDB_PART_1_2)
2804 val &= ~DISP_DATA_PARTITION_5_6;
2805 else
2806 val |= DISP_DATA_PARTITION_5_6;
2807 I915_WRITE(DISP_ARB_CTL2, val);
2808 }
1011d8c4
PZ		 2809 }
2810
49a687c4 2811 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2812 val = I915_READ(DISP_ARB_CTL);
2813 if (results->enable_fbc_wm)
2814 val &= ~DISP_FBC_WM_DIS;
2815 else
2816 val |= DISP_FBC_WM_DIS;
2817 I915_WRITE(DISP_ARB_CTL, val);
2818 }
2819
954911eb
ID		 2820 if (dirty & WM_DIRTY_LP(1) &&
2821 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2822 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2823
2824 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2825 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2826 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2827 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2828 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2829 }
801bcfff 2830
facd619b 2831 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2832 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2834 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2836 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2837
2838 dev_priv->wm.hw = *results;
801bcfff
PZ		 2839}
2840
ed4a6a7c 2841bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2842{
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844
2845 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2846}
2847
b9cec075
DL		 2848/*
2849 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2850 * different active planes.
2851 */
2852
2853#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2854#define BXT_DDB_SIZE 512
b9cec075 2855
024c9045
MR		 2856/*
2857 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2858 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2859 * other universal planes are in indices 1..n. Note that this may leave unused
2860 * indices between the top "sprite" plane and the cursor.
2861 */
2862static int
2863skl_wm_plane_id(const struct intel_plane *plane)
2864{
2865 switch (plane->base.type) {
2866 case DRM_PLANE_TYPE_PRIMARY:
2867 return 0;
2868 case DRM_PLANE_TYPE_CURSOR:
2869 return PLANE_CURSOR;
2870 case DRM_PLANE_TYPE_OVERLAY:
2871 return plane->plane + 1;
2872 default:
2873 MISSING_CASE(plane->base.type);
2874 return plane->plane;
2875 }
2876}
2877
b9cec075
DL		 2878static void
2879skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2880 const struct intel_crtc_state *cstate,
c107acfe
MR		 2881 struct skl_ddb_entry *alloc, /* out */
2882 int *num_active /* out */)
b9cec075 2883{
c107acfe
MR		 2884 struct drm_atomic_state *state = cstate->base.state;
2885 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2886 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2887 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2888 unsigned int pipe_size, ddb_size;
2889 int nth_active_pipe;
c107acfe
MR		 2890 int pipe = to_intel_crtc(for_crtc)->pipe;
2891
a6d3460e 2892 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2893 alloc->start = 0;
2894 alloc->end = 0;
a6d3460e 2895 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2896 return;
2897 }
2898
a6d3460e
MR		 2899 if (intel_state->active_pipe_changes)
2900 *num_active = hweight32(intel_state->active_crtcs);
2901 else
2902 *num_active = hweight32(dev_priv->active_crtcs);
2903
43d735a6
DL		 2904 if (IS_BROXTON(dev))
2905 ddb_size = BXT_DDB_SIZE;
2906 else
2907 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2908
2909 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2910
c107acfe 2911 /*
a6d3460e
MR		 2912 * If the state doesn't change the active CRTC's, then there's
2913 * no need to recalculate; the existing pipe allocation limits
2914 * should remain unchanged. Note that we're safe from racing
2915 * commits since any racing commit that changes the active CRTC
2916 * list would need to grab _all_ crtc locks, including the one
2917 * we currently hold.
c107acfe 2918 */
a6d3460e
MR		 2919 if (!intel_state->active_pipe_changes) {
2920 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2921 return;
c107acfe 2922 }
a6d3460e
MR		 2923
2924 nth_active_pipe = hweight32(intel_state->active_crtcs &
2925 (drm_crtc_mask(for_crtc) - 1));
2926 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2927 alloc->start = nth_active_pipe * ddb_size / *num_active;
2928 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2929}
2930
c107acfe 2931static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2932{
c107acfe 2933 if (num_active == 1)
b9cec075
DL		 2934 return 32;
2935
2936 return 8;
2937}
2938
a269c583
DL		 2939static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2940{
2941 entry->start = reg & 0x3ff;
2942 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2943 if (entry->end)
2944 entry->end += 1;
a269c583
DL		 2945}
2946
08db6652
DL		 2947void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2948 struct skl_ddb_allocation *ddb /* out */)
a269c583 2949{
a269c583
DL		 2950 enum pipe pipe;
2951 int plane;
2952 u32 val;
2953
b10f1b20
ML		 2954 memset(ddb, 0, sizeof(*ddb));
2955
a269c583 2956 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2957 enum intel_display_power_domain power_domain;
2958
2959 power_domain = POWER_DOMAIN_PIPE(pipe);
2960 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2961 continue;
2962
dd740780 2963 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2964 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2965 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2966 val);
2967 }
2968
2969 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2970 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2971 val);
4d800030
ID		 2972
2973 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2974 }
2975}
2976
9c2f7a9d
KM		 2977/*
2978 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2979 * The bspec defines downscale amount as:
2980 *
2981 * """
2982 * Horizontal down scale amount = maximum[1, Horizontal source size /
2983 * Horizontal destination size]
2984 * Vertical down scale amount = maximum[1, Vertical source size /
2985 * Vertical destination size]
2986 * Total down scale amount = Horizontal down scale amount *
2987 * Vertical down scale amount
2988 * """
2989 *
2990 * Return value is provided in 16.16 fixed point form to retain fractional part.
2991 * Caller should take care of dividing & rounding off the value.
2992 */
2993static uint32_t
2994skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2995{
2996 uint32_t downscale_h, downscale_w;
2997 uint32_t src_w, src_h, dst_w, dst_h;
2998
2999 if (WARN_ON(!pstate->visible))
3000 return DRM_PLANE_HELPER_NO_SCALING;
3001
3002 /* n.b., src is 16.16 fixed point, dst is whole integer */
3003 src_w = drm_rect_width(&pstate->src);
3004 src_h = drm_rect_height(&pstate->src);
3005 dst_w = drm_rect_width(&pstate->dst);
3006 dst_h = drm_rect_height(&pstate->dst);
3007 if (intel_rotation_90_or_270(pstate->base.rotation))
3008 swap(dst_w, dst_h);
3009
3010 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3011 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3012
3013 /* Provide result in 16.16 fixed point */
3014 return (uint64_t)downscale_w * downscale_h >> 16;
3015}
3016
b9cec075 3017static unsigned int
024c9045
MR		 3018skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3019 const struct drm_plane_state *pstate,
3020 int y)
b9cec075 3021{
a280f7dd 3022 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3023 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3024 uint32_t down_scale_amount, data_rate;
a280f7dd 3025 uint32_t width = 0, height = 0;
a1de91e5
MR		 3026 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3027
3028 if (!intel_pstate->visible)
3029 return 0;
3030 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3031 return 0;
3032 if (y && format != DRM_FORMAT_NV12)
3033 return 0;
a280f7dd
KM		 3034
3035 width = drm_rect_width(&intel_pstate->src) >> 16;
3036 height = drm_rect_height(&intel_pstate->src) >> 16;
3037
3038 if (intel_rotation_90_or_270(pstate->rotation))
3039 swap(width, height);
2cd601c6
CK		 3040
3041 /* for planar format */
a1de91e5 3042 if (format == DRM_FORMAT_NV12) {
2cd601c6 3043 if (y) /* y-plane data rate */
8d19d7d9 3044 data_rate = width * height *
a1de91e5 3045 drm_format_plane_cpp(format, 0);
2cd601c6 3046 else /* uv-plane data rate */
8d19d7d9 3047 data_rate = (width / 2) * (height / 2) *
a1de91e5 3048 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3049 } else {
3050 /* for packed formats */
3051 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3052 }
3053
8d19d7d9
KM		 3054 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3055
3056 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3057}
3058
3059/*
3060 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3061 * a 8192x4096@32bpp framebuffer:
3062 * 3 * 4096 * 8192 * 4 < 2^32
3063 */
3064static unsigned int
9c74d826 3065skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3066{
9c74d826
MR		 3067 struct drm_crtc_state *cstate = &intel_cstate->base;
3068 struct drm_atomic_state *state = cstate->state;
3069 struct drm_crtc *crtc = cstate->crtc;
3070 struct drm_device *dev = crtc->dev;
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3072 const struct drm_plane *plane;
024c9045 3073 const struct intel_plane *intel_plane;
a6d3460e 3074 struct drm_plane_state *pstate;
a1de91e5 3075 unsigned int rate, total_data_rate = 0;
9c74d826 3076 int id;
a6d3460e
MR		 3077 int i;
3078
3079 if (WARN_ON(!state))
3080 return 0;
b9cec075 3081
a1de91e5 3082 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3083 for_each_plane_in_state(state, plane, pstate, i) {
3084 id = skl_wm_plane_id(to_intel_plane(plane));
3085 intel_plane = to_intel_plane(plane);
3086
3087 if (intel_plane->pipe != intel_crtc->pipe)
3088 continue;
3089
3090 /* packed/uv */
3091 rate = skl_plane_relative_data_rate(intel_cstate,
3092 pstate, 0);
3093 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3094
3095 /* y-plane */
3096 rate = skl_plane_relative_data_rate(intel_cstate,
3097 pstate, 1);
3098 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3099 }
024c9045 3100
a1de91e5
MR		 3101 /* Calculate CRTC's total data rate from cached values */
3102 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3103 int id = skl_wm_plane_id(intel_plane);
024c9045 3104
a1de91e5 3105 /* packed/uv */
9c74d826
MR		 3106 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3107 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3108 }
3109
9c74d826
MR		 3110 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3111
b9cec075
DL		 3112 return total_data_rate;
3113}
3114
cbcfd14b
KM		 3115static uint16_t
3116skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3117 const int y)
3118{
3119 struct drm_framebuffer *fb = pstate->fb;
3120 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3121 uint32_t src_w, src_h;
3122 uint32_t min_scanlines = 8;
3123 uint8_t plane_bpp;
3124
3125 if (WARN_ON(!fb))
3126 return 0;
3127
3128 /* For packed formats, no y-plane, return 0 */
3129 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3130 return 0;
3131
3132 /* For Non Y-tile return 8-blocks */
3133 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3134 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3135 return 8;
3136
3137 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3138 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3139
3140 if (intel_rotation_90_or_270(pstate->rotation))
3141 swap(src_w, src_h);
3142
3143 /* Halve UV plane width and height for NV12 */
3144 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3145 src_w /= 2;
3146 src_h /= 2;
3147 }
3148
3149 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3150 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3151 else
3152 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3153
3154 if (intel_rotation_90_or_270(pstate->rotation)) {
3155 switch (plane_bpp) {
3156 case 1:
3157 min_scanlines = 32;
3158 break;
3159 case 2:
3160 min_scanlines = 16;
3161 break;
3162 case 4:
3163 min_scanlines = 8;
3164 break;
3165 case 8:
3166 min_scanlines = 4;
3167 break;
3168 default:
3169 WARN(1, "Unsupported pixel depth %u for rotation",
3170 plane_bpp);
3171 min_scanlines = 32;
3172 }
3173 }
3174
3175 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3176}
3177
c107acfe 3178static int
024c9045 3179skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3180 struct skl_ddb_allocation *ddb /* out */)
3181{
c107acfe 3182 struct drm_atomic_state *state = cstate->base.state;
024c9045 3183 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3184 struct drm_device *dev = crtc->dev;
3185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3186 struct intel_plane *intel_plane;
c107acfe
MR		 3187 struct drm_plane *plane;
3188 struct drm_plane_state *pstate;
b9cec075 3189 enum pipe pipe = intel_crtc->pipe;
34bb56af 3190 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3191 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3192 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3193 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3194 unsigned int total_data_rate;
c107acfe
MR		 3195 int num_active;
3196 int id, i;
b9cec075 3197
a6d3460e
MR		 3198 if (WARN_ON(!state))
3199 return 0;
3200
c107acfe
MR		 3201 if (!cstate->base.active) {
3202 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3203 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3204 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3205 return 0;
3206 }
3207
a6d3460e 3208 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3209 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3210 if (alloc_size == 0) {
3211 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3212 return 0;
b9cec075
DL		 3213 }
3214
c107acfe 3215 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3216 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3217 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3218
3219 alloc_size -= cursor_blocks;
b9cec075 3220
80958155 3221 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3222 for_each_plane_in_state(state, plane, pstate, i) {
3223 intel_plane = to_intel_plane(plane);
3224 id = skl_wm_plane_id(intel_plane);
c107acfe 3225
a6d3460e
MR		 3226 if (intel_plane->pipe != pipe)
3227 continue;
c107acfe 3228
a6d3460e
MR		 3229 if (!to_intel_plane_state(pstate)->visible) {
3230 minimum[id] = 0;
3231 y_minimum[id] = 0;
3232 continue;
3233 }
3234 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3235 minimum[id] = 0;
3236 y_minimum[id] = 0;
3237 continue;
c107acfe 3238 }
a6d3460e 3239
cbcfd14b
KM		 3240 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3241 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3242 }
80958155 3243
c107acfe
MR		 3244 for (i = 0; i < PLANE_CURSOR; i++) {
3245 alloc_size -= minimum[i];
3246 alloc_size -= y_minimum[i];
80958155
DL		 3247 }
3248
b9cec075 3249 /*
80958155
DL		 3250 * 2. Distribute the remaining space in proportion to the amount of
3251 * data each plane needs to fetch from memory.
b9cec075
DL		 3252 *
3253 * FIXME: we may not allocate every single block here.
3254 */
024c9045 3255 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3256 if (total_data_rate == 0)
c107acfe 3257 return 0;
b9cec075 3258
34bb56af 3259 start = alloc->start;
024c9045 3260 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3261 unsigned int data_rate, y_data_rate;
3262 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3263 int id = skl_wm_plane_id(intel_plane);
b9cec075 3264
a1de91e5 3265 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3266
3267 /*
2cd601c6 3268 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3269 * promote the expression to 64 bits to avoid overflowing, the
3270 * result is < available as data_rate / total_data_rate < 1
3271 */
024c9045 3272 plane_blocks = minimum[id];
80958155
DL		 3273 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3274 total_data_rate);
b9cec075 3275
c107acfe
MR		 3276 /* Leave disabled planes at (0,0) */
3277 if (data_rate) {
3278 ddb->plane[pipe][id].start = start;
3279 ddb->plane[pipe][id].end = start + plane_blocks;
3280 }
b9cec075
DL		 3281
3282 start += plane_blocks;
2cd601c6
CK		 3283
3284 /*
3285 * allocation for y_plane part of planar format:
3286 */
a1de91e5
MR		 3287 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3288
3289 y_plane_blocks = y_minimum[id];
3290 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3291 total_data_rate);
2cd601c6 3292
c107acfe
MR		 3293 if (y_data_rate) {
3294 ddb->y_plane[pipe][id].start = start;
3295 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3296 }
a1de91e5
MR		 3297
3298 start += y_plane_blocks;
b9cec075
DL		 3299 }
3300
c107acfe 3301 return 0;
b9cec075
DL		 3302}
3303
5cec258b 3304static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3305{
3306 /* TODO: Take into account the scalers once we support them */
2d112de7 3307 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3308}
3309
3310/*
3311 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3312 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3313 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3314 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3315*/
ac484963 3316static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3317{
3318 uint32_t wm_intermediate_val, ret;
3319
3320 if (latency == 0)
3321 return UINT_MAX;
3322
ac484963 3323 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3324 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3325
3326 return ret;
3327}
3328
3329static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3330 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3331 uint64_t tiling, uint32_t latency)
2d41c0b5 3332{
d4c2aa60
TU		 3333 uint32_t ret;
3334 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3335 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3336
3337 if (latency == 0)
3338 return UINT_MAX;
3339
ac484963 3340 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3341
3342 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3343 tiling == I915_FORMAT_MOD_Yf_TILED) {
3344 plane_bytes_per_line *= 4;
3345 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3346 plane_blocks_per_line /= 4;
3347 } else {
3348 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3349 }
3350
2d41c0b5
PB		 3351 wm_intermediate_val = latency * pixel_rate;
3352 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3353 plane_blocks_per_line;
2d41c0b5
PB		 3354
3355 return ret;
3356}
3357
9c2f7a9d
KM		 3358static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3359 struct intel_plane_state *pstate)
3360{
3361 uint64_t adjusted_pixel_rate;
3362 uint64_t downscale_amount;
3363 uint64_t pixel_rate;
3364
3365 /* Shouldn't reach here on disabled planes... */
3366 if (WARN_ON(!pstate->visible))
3367 return 0;
3368
3369 /*
3370 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3371 * with additional adjustments for plane-specific scaling.
3372 */
3373 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3374 downscale_amount = skl_plane_downscale_amount(pstate);
3375
3376 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3377 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3378
3379 return pixel_rate;
3380}
3381
55994c2c
MR		 3382static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3383 struct intel_crtc_state *cstate,
3384 struct intel_plane_state *intel_pstate,
3385 uint16_t ddb_allocation,
3386 int level,
3387 uint16_t *out_blocks, /* out */
3388 uint8_t *out_lines, /* out */
3389 bool *enabled /* out */)
2d41c0b5 3390{
33815fa5
MR		 3391 struct drm_plane_state *pstate = &intel_pstate->base;
3392 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3393 uint32_t latency = dev_priv->wm.skl_latency[level];
3394 uint32_t method1, method2;
3395 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3396 uint32_t res_blocks, res_lines;
3397 uint32_t selected_result;
ac484963 3398 uint8_t cpp;
a280f7dd 3399 uint32_t width = 0, height = 0;
9c2f7a9d 3400 uint32_t plane_pixel_rate;
2d41c0b5 3401
55994c2c
MR		 3402 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3403 *enabled = false;
3404 return 0;
3405 }
2d41c0b5 3406
a280f7dd
KM		 3407 width = drm_rect_width(&intel_pstate->src) >> 16;
3408 height = drm_rect_height(&intel_pstate->src) >> 16;
3409
33815fa5 3410 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3411 swap(width, height);
3412
ac484963 3413 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3414 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3415
3416 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3417 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3418 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3419 width,
3420 cpp,
3421 fb->modifier[0],
d4c2aa60 3422 latency);
2d41c0b5 3423
a280f7dd 3424 plane_bytes_per_line = width * cpp;
d4c2aa60 3425 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3426
024c9045
MR		 3427 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3428 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3429 uint32_t min_scanlines = 4;
3430 uint32_t y_tile_minimum;
33815fa5 3431 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3432 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3433 drm_format_plane_cpp(fb->pixel_format, 1) :
3434 drm_format_plane_cpp(fb->pixel_format, 0);
3435
ac484963 3436 switch (cpp) {
1fc0a8f7
TU		 3437 case 1:
3438 min_scanlines = 16;
3439 break;
3440 case 2:
3441 min_scanlines = 8;
3442 break;
3443 case 8:
3444 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3445 }
1fc0a8f7
TU		 3446 }
3447 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3448 selected_result = max(method2, y_tile_minimum);
3449 } else {
3450 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3451 selected_result = min(method1, method2);
3452 else
3453 selected_result = method1;
3454 }
2d41c0b5 3455
d4c2aa60
TU		 3456 res_blocks = selected_result + 1;
3457 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3458
0fda6568 3459 if (level >= 1 && level <= 7) {
024c9045
MR		 3460 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3461 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3462 res_lines += 4;
3463 else
3464 res_blocks++;
3465 }
e6d66171 3466
55994c2c
MR		 3467 if (res_blocks >= ddb_allocation || res_lines > 31) {
3468 *enabled = false;
6b6bada7
MR		 3469
3470 /*
3471 * If there are no valid level 0 watermarks, then we can't
3472 * support this display configuration.
3473 */
3474 if (level) {
3475 return 0;
3476 } else {
3477 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3478 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3479 to_intel_crtc(cstate->base.crtc)->pipe,
3480 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3481 res_blocks, ddb_allocation, res_lines);
3482
3483 return -EINVAL;
3484 }
55994c2c 3485 }
e6d66171
DL		 3486
3487 *out_blocks = res_blocks;
3488 *out_lines = res_lines;
55994c2c 3489 *enabled = true;
2d41c0b5 3490
55994c2c 3491 return 0;
2d41c0b5
PB		 3492}
3493
f4a96752
MR		 3494static int
3495skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3496 struct skl_ddb_allocation *ddb,
3497 struct intel_crtc_state *cstate,
3498 int level,
3499 struct skl_wm_level *result)
2d41c0b5 3500{
024c9045 3501 struct drm_device *dev = dev_priv->dev;
f4a96752 3502 struct drm_atomic_state *state = cstate->base.state;
024c9045 3503 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3504 struct drm_plane *plane;
024c9045 3505 struct intel_plane *intel_plane;
33815fa5 3506 struct intel_plane_state *intel_pstate;
2d41c0b5 3507 uint16_t ddb_blocks;
024c9045 3508 enum pipe pipe = intel_crtc->pipe;
55994c2c 3509 int ret;
024c9045 3510
f4a96752
MR		 3511 /*
3512 * We'll only calculate watermarks for planes that are actually
3513 * enabled, so make sure all other planes are set as disabled.
3514 */
3515 memset(result, 0, sizeof(*result));
3516
3517 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
024c9045 3518 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3519
f4a96752
MR		 3520 plane = &intel_plane->base;
3521 intel_pstate = NULL;
3522 if (state)
3523 intel_pstate =
3524 intel_atomic_get_existing_plane_state(state,
3525 intel_plane);
3526
3527 /*
3528 * Note: If we start supporting multiple pending atomic commits
3529 * against the same planes/CRTC's in the future, plane->state
3530 * will no longer be the correct pre-state to use for the
3531 * calculations here and we'll need to change where we get the
3532 * 'unchanged' plane data from.
3533 *
3534 * For now this is fine because we only allow one queued commit
3535 * against a CRTC. Even if the plane isn't modified by this
3536 * transaction and we don't have a plane lock, we still have
3537 * the CRTC's lock, so we know that no other transactions are
3538 * racing with us to update it.
3539 */
3540 if (!intel_pstate)
3541 intel_pstate = to_intel_plane_state(plane->state);
3542
3543 WARN_ON(!intel_pstate->base.fb);
3544
2d41c0b5
PB		 3545 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3546
55994c2c
MR		 3547 ret = skl_compute_plane_wm(dev_priv,
3548 cstate,
3549 intel_pstate,
3550 ddb_blocks,
3551 level,
3552 &result->plane_res_b[i],
3553 &result->plane_res_l[i],
3554 &result->plane_en[i]);
3555 if (ret)
3556 return ret;
2d41c0b5 3557 }
f4a96752
MR		 3558
3559 return 0;
2d41c0b5
PB		 3560}
3561
407b50f3 3562static uint32_t
024c9045 3563skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3564{
024c9045 3565 if (!cstate->base.active)
407b50f3
DL		 3566 return 0;
3567
024c9045 3568 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3569 return 0;
407b50f3 3570
024c9045
MR		 3571 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3572 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3573}
3574
024c9045 3575static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3576 struct skl_wm_level *trans_wm /* out */)
407b50f3 3577{
024c9045 3578 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3580 struct intel_plane *intel_plane;
9414f563 3581
024c9045 3582 if (!cstate->base.active)
407b50f3 3583 return;
9414f563
DL		 3584
3585 /* Until we know more, just disable transition WMs */
024c9045
MR		 3586 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3587 int i = skl_wm_plane_id(intel_plane);
3588
9414f563 3589 trans_wm->plane_en[i] = false;
024c9045 3590 }
407b50f3
DL		 3591}
3592
55994c2c
MR		 3593static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3594 struct skl_ddb_allocation *ddb,
3595 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3596{
024c9045 3597 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3598 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3599 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3600 int ret;
2d41c0b5
PB		 3601
3602 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3603 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3604 level, &pipe_wm->wm[level]);
3605 if (ret)
3606 return ret;
2d41c0b5 3607 }
024c9045 3608 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3609
024c9045 3610 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3611
3612 return 0;
2d41c0b5
PB		 3613}
3614
3615static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3616 struct skl_pipe_wm *p_wm,
3617 struct skl_wm_values *r,
3618 struct intel_crtc *intel_crtc)
3619{
3620 int level, max_level = ilk_wm_max_level(dev);
3621 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3622 uint32_t temp;
3623 int i;
2d41c0b5
PB		 3624
3625 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3626 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3627 temp = 0;
2d41c0b5
PB		 3628
3629 temp |= p_wm->wm[level].plane_res_l[i] <<
3630 PLANE_WM_LINES_SHIFT;
3631 temp |= p_wm->wm[level].plane_res_b[i];
3632 if (p_wm->wm[level].plane_en[i])
3633 temp |= PLANE_WM_EN;
3634
3635 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3636 }
3637
3638 temp = 0;
2d41c0b5 3639
4969d33e
MR		 3640 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3641 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3642
4969d33e 3643 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3644 temp |= PLANE_WM_EN;
3645
4969d33e 3646 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3647
3648 }
3649
9414f563
DL		 3650 /* transition WMs */
3651 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3652 temp = 0;
3653 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3654 temp |= p_wm->trans_wm.plane_res_b[i];
3655 if (p_wm->trans_wm.plane_en[i])
3656 temp |= PLANE_WM_EN;
3657
3658 r->plane_trans[pipe][i] = temp;
3659 }
3660
3661 temp = 0;
4969d33e
MR		 3662 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3663 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3664 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3665 temp |= PLANE_WM_EN;
3666
4969d33e 3667 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3668
2d41c0b5
PB		 3669 r->wm_linetime[pipe] = p_wm->linetime;
3670}
3671
f0f59a00
VS		 3672static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3673 i915_reg_t reg,
16160e3d
DL		 3674 const struct skl_ddb_entry *entry)
3675{
3676 if (entry->end)
3677 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3678 else
3679 I915_WRITE(reg, 0);
3680}
3681
2d41c0b5
PB		 3682static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3683 const struct skl_wm_values *new)
3684{
3685 struct drm_device *dev = dev_priv->dev;
3686 struct intel_crtc *crtc;
3687
19c8054c 3688 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3689 int i, level, max_level = ilk_wm_max_level(dev);
3690 enum pipe pipe = crtc->pipe;
3691
2b4b9f35 3692 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3693 continue;
734fa01f
MR		 3694 if (!crtc->active)
3695 continue;
8211bd5b 3696
5d374d96 3697 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3698
5d374d96
DL		 3699 for (level = 0; level <= max_level; level++) {
3700 for (i = 0; i < intel_num_planes(crtc); i++)
3701 I915_WRITE(PLANE_WM(pipe, i, level),
3702 new->plane[pipe][i][level]);
3703 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3704 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3705 }
5d374d96
DL		 3706 for (i = 0; i < intel_num_planes(crtc); i++)
3707 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3708 new->plane_trans[pipe][i]);
4969d33e
MR		 3709 I915_WRITE(CUR_WM_TRANS(pipe),
3710 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3711
2cd601c6 3712 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3713 skl_ddb_entry_write(dev_priv,
3714 PLANE_BUF_CFG(pipe, i),
3715 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3716 skl_ddb_entry_write(dev_priv,
3717 PLANE_NV12_BUF_CFG(pipe, i),
3718 &new->ddb.y_plane[pipe][i]);
3719 }
5d374d96
DL		 3720
3721 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3722 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3723 }
2d41c0b5
PB		 3724}
3725
0e8fb7ba
DL		 3726/*
3727 * When setting up a new DDB allocation arrangement, we need to correctly
3728 * sequence the times at which the new allocations for the pipes are taken into
3729 * account or we'll have pipes fetching from space previously allocated to
3730 * another pipe.
3731 *
3732 * Roughly the sequence looks like:
3733 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3734 * overlapping with a previous light-up pipe (another way to put it is:
3735 * pipes with their new allocation strickly included into their old ones).
3736 * 2. re-allocate the other pipes that get their allocation reduced
3737 * 3. allocate the pipes having their allocation increased
3738 *
3739 * Steps 1. and 2. are here to take care of the following case:
3740 * - Initially DDB looks like this:
3741 * | B | C |
3742 * - enable pipe A.
3743 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3744 * allocation
3745 * | A | B | C |
3746 *
3747 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3748 */
3749
d21b795c
DL		 3750static void
3751skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3752{
0e8fb7ba
DL		 3753 int plane;
3754
d21b795c
DL		 3755 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3756
dd740780 3757 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3758 I915_WRITE(PLANE_SURF(pipe, plane),
3759 I915_READ(PLANE_SURF(pipe, plane)));
3760 }
3761 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3762}
3763
3764static bool
3765skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3766 const struct skl_ddb_allocation *new,
3767 enum pipe pipe)
3768{
3769 uint16_t old_size, new_size;
3770
3771 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3772 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3773
3774 return old_size != new_size &&
3775 new->pipe[pipe].start >= old->pipe[pipe].start &&
3776 new->pipe[pipe].end <= old->pipe[pipe].end;
3777}
3778
3779static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3780 struct skl_wm_values *new_values)
3781{
3782 struct drm_device *dev = dev_priv->dev;
3783 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3784 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3785 struct intel_crtc *crtc;
3786 enum pipe pipe;
3787
3788 new_ddb = &new_values->ddb;
3789 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3790
3791 /*
3792 * First pass: flush the pipes with the new allocation contained into
3793 * the old space.
3794 *
3795 * We'll wait for the vblank on those pipes to ensure we can safely
3796 * re-allocate the freed space without this pipe fetching from it.
3797 */
3798 for_each_intel_crtc(dev, crtc) {
3799 if (!crtc->active)
3800 continue;
3801
3802 pipe = crtc->pipe;
3803
3804 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3805 continue;
3806
d21b795c 3807 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3808 intel_wait_for_vblank(dev, pipe);
3809
3810 reallocated[pipe] = true;
3811 }
3812
3813
3814 /*
3815 * Second pass: flush the pipes that are having their allocation
3816 * reduced, but overlapping with a previous allocation.
3817 *
3818 * Here as well we need to wait for the vblank to make sure the freed
3819 * space is not used anymore.
3820 */
3821 for_each_intel_crtc(dev, crtc) {
3822 if (!crtc->active)
3823 continue;
3824
3825 pipe = crtc->pipe;
3826
3827 if (reallocated[pipe])
3828 continue;
3829
3830 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3831 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3832 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3833 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3834 reallocated[pipe] = true;
0e8fb7ba 3835 }
0e8fb7ba
DL		 3836 }
3837
3838 /*
3839 * Third pass: flush the pipes that got more space allocated.
3840 *
3841 * We don't need to actively wait for the update here, next vblank
3842 * will just get more DDB space with the correct WM values.
3843 */
3844 for_each_intel_crtc(dev, crtc) {
3845 if (!crtc->active)
3846 continue;
3847
3848 pipe = crtc->pipe;
3849
3850 /*
3851 * At this point, only the pipes more space than before are
3852 * left to re-allocate.
3853 */
3854 if (reallocated[pipe])
3855 continue;
3856
d21b795c 3857 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3858 }
3859}
3860
55994c2c
MR		 3861static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3862 struct skl_ddb_allocation *ddb, /* out */
3863 struct skl_pipe_wm *pipe_wm, /* out */
3864 bool *changed /* out */)
2d41c0b5 3865{
f4a96752
MR		 3866 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3867 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3868 int ret;
2d41c0b5 3869
55994c2c
MR		 3870 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3871 if (ret)
3872 return ret;
2d41c0b5 3873
4e0963c7 3874 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3875 *changed = false;
3876 else
3877 *changed = true;
2d41c0b5 3878
55994c2c 3879 return 0;
2d41c0b5
PB		 3880}
3881
98d39494
MR		 3882static int
3883skl_compute_ddb(struct drm_atomic_state *state)
3884{
3885 struct drm_device *dev = state->dev;
3886 struct drm_i915_private *dev_priv = to_i915(dev);
3887 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3888 struct intel_crtc *intel_crtc;
734fa01f 3889 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
98d39494
MR		 3890 unsigned realloc_pipes = dev_priv->active_crtcs;
3891 int ret;
3892
3893 /*
3894 * If this is our first atomic update following hardware readout,
3895 * we can't trust the DDB that the BIOS programmed for us. Let's
3896 * pretend that all pipes switched active status so that we'll
3897 * ensure a full DDB recompute.
3898 */
3899 if (dev_priv->wm.distrust_bios_wm)
3900 intel_state->active_pipe_changes = ~0;
3901
3902 /*
3903 * If the modeset changes which CRTC's are active, we need to
3904 * recompute the DDB allocation for *all* active pipes, even
3905 * those that weren't otherwise being modified in any way by this
3906 * atomic commit. Due to the shrinking of the per-pipe allocations
3907 * when new active CRTC's are added, it's possible for a pipe that
3908 * we were already using and aren't changing at all here to suddenly
3909 * become invalid if its DDB needs exceeds its new allocation.
3910 *
3911 * Note that if we wind up doing a full DDB recompute, we can't let
3912 * any other display updates race with this transaction, so we need
3913 * to grab the lock on *all* CRTC's.
3914 */
734fa01f 3915 if (intel_state->active_pipe_changes) {
98d39494 3916 realloc_pipes = ~0;
734fa01f
MR		 3917 intel_state->wm_results.dirty_pipes = ~0;
3918 }
98d39494
MR		 3919
3920 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3921 struct intel_crtc_state *cstate;
3922
3923 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3924 if (IS_ERR(cstate))
3925 return PTR_ERR(cstate);
3926
734fa01f 3927 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 3928 if (ret)
3929 return ret;
3930 }
3931
3932 return 0;
3933}
3934
3935static int
3936skl_compute_wm(struct drm_atomic_state *state)
3937{
3938 struct drm_crtc *crtc;
3939 struct drm_crtc_state *cstate;
734fa01f
MR		 3940 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3941 struct skl_wm_values *results = &intel_state->wm_results;
3942 struct skl_pipe_wm *pipe_wm;
98d39494 3943 bool changed = false;
734fa01f 3944 int ret, i;
98d39494
MR		 3945
3946 /*
3947 * If this transaction isn't actually touching any CRTC's, don't
3948 * bother with watermark calculation. Note that if we pass this
3949 * test, we're guaranteed to hold at least one CRTC state mutex,
3950 * which means we can safely use values like dev_priv->active_crtcs
3951 * since any racing commits that want to update them would need to
3952 * hold _all_ CRTC state mutexes.
3953 */
3954 for_each_crtc_in_state(state, crtc, cstate, i)
3955 changed = true;
3956 if (!changed)
3957 return 0;
3958
734fa01f
MR		 3959 /* Clear all dirty flags */
3960 results->dirty_pipes = 0;
3961
98d39494
MR		 3962 ret = skl_compute_ddb(state);
3963 if (ret)
3964 return ret;
3965
734fa01f
MR		 3966 /*
3967 * Calculate WM's for all pipes that are part of this transaction.
3968 * Note that the DDB allocation above may have added more CRTC's that
3969 * weren't otherwise being modified (and set bits in dirty_pipes) if
3970 * pipe allocations had to change.
3971 *
3972 * FIXME: Now that we're doing this in the atomic check phase, we
3973 * should allow skl_update_pipe_wm() to return failure in cases where
3974 * no suitable watermark values can be found.
3975 */
3976 for_each_crtc_in_state(state, crtc, cstate, i) {
3977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3978 struct intel_crtc_state *intel_cstate =
3979 to_intel_crtc_state(cstate);
3980
3981 pipe_wm = &intel_cstate->wm.skl.optimal;
3982 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3983 &changed);
3984 if (ret)
3985 return ret;
3986
3987 if (changed)
3988 results->dirty_pipes |= drm_crtc_mask(crtc);
3989
3990 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3991 /* This pipe's WM's did not change */
3992 continue;
3993
3994 intel_cstate->update_wm_pre = true;
3995 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3996 }
3997
98d39494
MR		 3998 return 0;
3999}
4000
2d41c0b5
PB		 4001static void skl_update_wm(struct drm_crtc *crtc)
4002{
4003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4004 struct drm_device *dev = crtc->dev;
4005 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 4006 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 4007 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4008 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
adda50b8 4009
734fa01f 4010 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4011 return;
4012
734fa01f
MR		 4013 intel_crtc->wm.active.skl = *pipe_wm;
4014
4015 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4016
2d41c0b5 4017 skl_write_wm_values(dev_priv, results);
0e8fb7ba 4018 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 4019
4020 /* store the new configuration */
4021 dev_priv->wm.skl_hw = *results;
734fa01f
MR		 4022
4023 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4024}
4025
d890565c
VS		 4026static void ilk_compute_wm_config(struct drm_device *dev,
4027 struct intel_wm_config *config)
4028{
4029 struct intel_crtc *crtc;
4030
4031 /* Compute the currently _active_ config */
4032 for_each_intel_crtc(dev, crtc) {
4033 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4034
4035 if (!wm->pipe_enabled)
4036 continue;
4037
4038 config->sprites_enabled |= wm->sprites_enabled;
4039 config->sprites_scaled |= wm->sprites_scaled;
4040 config->num_pipes_active++;
4041 }
4042}
4043
ed4a6a7c 4044static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4045{
ed4a6a7c 4046 struct drm_device *dev = dev_priv->dev;
b9d5c839 4047 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4048 struct ilk_wm_maximums max;
d890565c 4049 struct intel_wm_config config = {};
820c1980 4050 struct ilk_wm_values results = {};
77c122bc 4051 enum intel_ddb_partitioning partitioning;
261a27d1 4052
d890565c
VS		 4053 ilk_compute_wm_config(dev, &config);
4054
4055 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4056 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4057
4058 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4059 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4060 config.num_pipes_active == 1 && config.sprites_enabled) {
4061 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4062 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4063
820c1980 4064 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4065 } else {
198a1e9b 4066 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4067 }
4068
198a1e9b 4069 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4070 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4071
820c1980 4072 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4073
820c1980 4074 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4075}
4076
ed4a6a7c 4077static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4078{
ed4a6a7c
MR		 4079 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4080 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4081
ed4a6a7c 4082 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4083 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4084 ilk_program_watermarks(dev_priv);
4085 mutex_unlock(&dev_priv->wm.wm_mutex);
4086}
bf220452 4087
ed4a6a7c
MR		 4088static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4089{
4090 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4091 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4092
ed4a6a7c
MR		 4093 mutex_lock(&dev_priv->wm.wm_mutex);
4094 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4095 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4096 ilk_program_watermarks(dev_priv);
4097 }
4098 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4099}
4100
3078999f
PB		 4101static void skl_pipe_wm_active_state(uint32_t val,
4102 struct skl_pipe_wm *active,
4103 bool is_transwm,
4104 bool is_cursor,
4105 int i,
4106 int level)
4107{
4108 bool is_enabled = (val & PLANE_WM_EN) != 0;
4109
4110 if (!is_transwm) {
4111 if (!is_cursor) {
4112 active->wm[level].plane_en[i] = is_enabled;
4113 active->wm[level].plane_res_b[i] =
4114 val & PLANE_WM_BLOCKS_MASK;
4115 active->wm[level].plane_res_l[i] =
4116 (val >> PLANE_WM_LINES_SHIFT) &
4117 PLANE_WM_LINES_MASK;
4118 } else {
4969d33e
MR		 4119 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4120 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4121 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4122 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4123 (val >> PLANE_WM_LINES_SHIFT) &
4124 PLANE_WM_LINES_MASK;
4125 }
4126 } else {
4127 if (!is_cursor) {
4128 active->trans_wm.plane_en[i] = is_enabled;
4129 active->trans_wm.plane_res_b[i] =
4130 val & PLANE_WM_BLOCKS_MASK;
4131 active->trans_wm.plane_res_l[i] =
4132 (val >> PLANE_WM_LINES_SHIFT) &
4133 PLANE_WM_LINES_MASK;
4134 } else {
4969d33e
MR		 4135 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4136 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4137 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4138 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4139 (val >> PLANE_WM_LINES_SHIFT) &
4140 PLANE_WM_LINES_MASK;
4141 }
4142 }
4143}
4144
4145static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4151 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4152 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4153 enum pipe pipe = intel_crtc->pipe;
4154 int level, i, max_level;
4155 uint32_t temp;
4156
4157 max_level = ilk_wm_max_level(dev);
4158
4159 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4160
4161 for (level = 0; level <= max_level; level++) {
4162 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4163 hw->plane[pipe][i][level] =
4164 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4165 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4166 }
4167
4168 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4169 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4170 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4171
3ef00284 4172 if (!intel_crtc->active)
3078999f
PB		 4173 return;
4174
2b4b9f35 4175 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4176
4177 active->linetime = hw->wm_linetime[pipe];
4178
4179 for (level = 0; level <= max_level; level++) {
4180 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4181 temp = hw->plane[pipe][i][level];
4182 skl_pipe_wm_active_state(temp, active, false,
4183 false, i, level);
4184 }
4969d33e 4185 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4186 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4187 }
4188
4189 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4190 temp = hw->plane_trans[pipe][i];
4191 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4192 }
4193
4969d33e 4194 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4195 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4196
4197 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4198}
4199
4200void skl_wm_get_hw_state(struct drm_device *dev)
4201{
a269c583
DL		 4202 struct drm_i915_private *dev_priv = dev->dev_private;
4203 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4204 struct drm_crtc *crtc;
4205
a269c583 4206 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4207 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4208 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4209
279e99d7
MR		 4210 if (dev_priv->active_crtcs) {
4211 /* Fully recompute DDB on first atomic commit */
4212 dev_priv->wm.distrust_bios_wm = true;
4213 } else {
4214 /* Easy/common case; just sanitize DDB now if everything off */
4215 memset(ddb, 0, sizeof(*ddb));
4216 }
3078999f
PB		 4217}
4218
243e6a44
VS		 4219static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4220{
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4223 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4225 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4226 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4227 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4228 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4229 [PIPE_A] = WM0_PIPEA_ILK,
4230 [PIPE_B] = WM0_PIPEB_ILK,
4231 [PIPE_C] = WM0_PIPEC_IVB,
4232 };
4233
4234 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4235 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4236 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4237
15606534
VS		 4238 memset(active, 0, sizeof(*active));
4239
3ef00284 4240 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4241
4242 if (active->pipe_enabled) {
243e6a44
VS		 4243 u32 tmp = hw->wm_pipe[pipe];
4244
4245 /*
4246 * For active pipes LP0 watermark is marked as
4247 * enabled, and LP1+ watermaks as disabled since
4248 * we can't really reverse compute them in case
4249 * multiple pipes are active.
4250 */
4251 active->wm[0].enable = true;
4252 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4253 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4254 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4255 active->linetime = hw->wm_linetime[pipe];
4256 } else {
4257 int level, max_level = ilk_wm_max_level(dev);
4258
4259 /*
4260 * For inactive pipes, all watermark levels
4261 * should be marked as enabled but zeroed,
4262 * which is what we'd compute them to.
4263 */
4264 for (level = 0; level <= max_level; level++)
4265 active->wm[level].enable = true;
4266 }
4e0963c7
MR		 4267
4268 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4269}
4270
6eb1a681
VS		 4271#define _FW_WM(value, plane) \
4272 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4273#define _FW_WM_VLV(value, plane) \
4274 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4275
4276static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4277 struct vlv_wm_values *wm)
4278{
4279 enum pipe pipe;
4280 uint32_t tmp;
4281
4282 for_each_pipe(dev_priv, pipe) {
4283 tmp = I915_READ(VLV_DDL(pipe));
4284
4285 wm->ddl[pipe].primary =
4286 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4287 wm->ddl[pipe].cursor =
4288 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4289 wm->ddl[pipe].sprite[0] =
4290 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4291 wm->ddl[pipe].sprite[1] =
4292 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4293 }
4294
4295 tmp = I915_READ(DSPFW1);
4296 wm->sr.plane = _FW_WM(tmp, SR);
4297 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4298 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4299 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4300
4301 tmp = I915_READ(DSPFW2);
4302 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4303 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4304 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4305
4306 tmp = I915_READ(DSPFW3);
4307 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4308
4309 if (IS_CHERRYVIEW(dev_priv)) {
4310 tmp = I915_READ(DSPFW7_CHV);
4311 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4312 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4313
4314 tmp = I915_READ(DSPFW8_CHV);
4315 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4316 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4317
4318 tmp = I915_READ(DSPFW9_CHV);
4319 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4320 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4321
4322 tmp = I915_READ(DSPHOWM);
4323 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4324 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4325 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4326 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4327 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4328 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4329 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4330 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4331 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4332 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4333 } else {
4334 tmp = I915_READ(DSPFW7);
4335 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4336 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4337
4338 tmp = I915_READ(DSPHOWM);
4339 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4340 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4341 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4342 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4343 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4344 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4345 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4346 }
4347}
4348
4349#undef _FW_WM
4350#undef _FW_WM_VLV
4351
4352void vlv_wm_get_hw_state(struct drm_device *dev)
4353{
4354 struct drm_i915_private *dev_priv = to_i915(dev);
4355 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4356 struct intel_plane *plane;
4357 enum pipe pipe;
4358 u32 val;
4359
4360 vlv_read_wm_values(dev_priv, wm);
4361
4362 for_each_intel_plane(dev, plane) {
4363 switch (plane->base.type) {
4364 int sprite;
4365 case DRM_PLANE_TYPE_CURSOR:
4366 plane->wm.fifo_size = 63;
4367 break;
4368 case DRM_PLANE_TYPE_PRIMARY:
4369 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4370 break;
4371 case DRM_PLANE_TYPE_OVERLAY:
4372 sprite = plane->plane;
4373 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4374 break;
4375 }
4376 }
4377
4378 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4379 wm->level = VLV_WM_LEVEL_PM2;
4380
4381 if (IS_CHERRYVIEW(dev_priv)) {
4382 mutex_lock(&dev_priv->rps.hw_lock);
4383
4384 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4385 if (val & DSP_MAXFIFO_PM5_ENABLE)
4386 wm->level = VLV_WM_LEVEL_PM5;
4387
58590c14
VS		 4388 /*
4389 * If DDR DVFS is disabled in the BIOS, Punit
4390 * will never ack the request. So if that happens
4391 * assume we don't have to enable/disable DDR DVFS
4392 * dynamically. To test that just set the REQ_ACK
4393 * bit to poke the Punit, but don't change the
4394 * HIGH/LOW bits so that we don't actually change
4395 * the current state.
4396 */
6eb1a681 4397 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4398 val |= FORCE_DDR_FREQ_REQ_ACK;
4399 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4400
4401 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4402 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4403 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4404 "assuming DDR DVFS is disabled\n");
4405 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4406 } else {
4407 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4408 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4409 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4410 }
6eb1a681
VS		 4411
4412 mutex_unlock(&dev_priv->rps.hw_lock);
4413 }
4414
4415 for_each_pipe(dev_priv, pipe)
4416 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4417 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4418 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4419
4420 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4421 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4422}
4423
243e6a44
VS		 4424void ilk_wm_get_hw_state(struct drm_device *dev)
4425{
4426 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4427 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4428 struct drm_crtc *crtc;
4429
70e1e0ec 4430 for_each_crtc(dev, crtc)
243e6a44
VS		 4431 ilk_pipe_wm_get_hw_state(crtc);
4432
4433 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4434 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4435 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4436
4437 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4438 if (INTEL_INFO(dev)->gen >= 7) {
4439 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4440 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4441 }
243e6a44 4442
a42a5719 4443 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4444 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4445 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4446 else if (IS_IVYBRIDGE(dev))
4447 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4448 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4449
4450 hw->enable_fbc_wm =
4451 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4452}
4453
b445e3b0
ED		 4454/**
4455 * intel_update_watermarks - update FIFO watermark values based on current modes
4456 *
4457 * Calculate watermark values for the various WM regs based on current mode
4458 * and plane configuration.
4459 *
4460 * There are several cases to deal with here:
4461 * - normal (i.e. non-self-refresh)
4462 * - self-refresh (SR) mode
4463 * - lines are large relative to FIFO size (buffer can hold up to 2)
4464 * - lines are small relative to FIFO size (buffer can hold more than 2
4465 * lines), so need to account for TLB latency
4466 *
4467 * The normal calculation is:
4468 * watermark = dotclock * bytes per pixel * latency
4469 * where latency is platform & configuration dependent (we assume pessimal
4470 * values here).
4471 *
4472 * The SR calculation is:
4473 * watermark = (trunc(latency/line time)+1) * surface width *
4474 * bytes per pixel
4475 * where
4476 * line time = htotal / dotclock
4477 * surface width = hdisplay for normal plane and 64 for cursor
4478 * and latency is assumed to be high, as above.
4479 *
4480 * The final value programmed to the register should always be rounded up,
4481 * and include an extra 2 entries to account for clock crossings.
4482 *
4483 * We don't use the sprite, so we can ignore that. And on Crestline we have
4484 * to set the non-SR watermarks to 8.
4485 */
46ba614c 4486void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4487{
46ba614c 4488 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4489
4490 if (dev_priv->display.update_wm)
46ba614c 4491 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4492}
4493
e2828914 4494/*
9270388e 4495 * Lock protecting IPS related data structures
9270388e
DV		 4496 */
4497DEFINE_SPINLOCK(mchdev_lock);
4498
4499/* Global for IPS driver to get at the current i915 device. Protected by
4500 * mchdev_lock. */
4501static struct drm_i915_private *i915_mch_dev;
4502
91d14251 4503bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4504{
2b4e57bd
ED		 4505 u16 rgvswctl;
4506
9270388e
DV		 4507 assert_spin_locked(&mchdev_lock);
4508
2b4e57bd
ED		 4509 rgvswctl = I915_READ16(MEMSWCTL);
4510 if (rgvswctl & MEMCTL_CMD_STS) {
4511 DRM_DEBUG("gpu busy, RCS change rejected\n");
4512 return false; /* still busy with another command */
4513 }
4514
4515 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4516 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4517 I915_WRITE16(MEMSWCTL, rgvswctl);
4518 POSTING_READ16(MEMSWCTL);
4519
4520 rgvswctl |= MEMCTL_CMD_STS;
4521 I915_WRITE16(MEMSWCTL, rgvswctl);
4522
4523 return true;
4524}
4525
91d14251 4526static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4527{
84f1b20f 4528 u32 rgvmodectl;
2b4e57bd
ED		 4529 u8 fmax, fmin, fstart, vstart;
4530
9270388e
DV		 4531 spin_lock_irq(&mchdev_lock);
4532
84f1b20f
TU		 4533 rgvmodectl = I915_READ(MEMMODECTL);
4534
2b4e57bd
ED		 4535 /* Enable temp reporting */
4536 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4537 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4538
4539 /* 100ms RC evaluation intervals */
4540 I915_WRITE(RCUPEI, 100000);
4541 I915_WRITE(RCDNEI, 100000);
4542
4543 /* Set max/min thresholds to 90ms and 80ms respectively */
4544 I915_WRITE(RCBMAXAVG, 90000);
4545 I915_WRITE(RCBMINAVG, 80000);
4546
4547 I915_WRITE(MEMIHYST, 1);
4548
4549 /* Set up min, max, and cur for interrupt handling */
4550 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4551 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4552 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4553 MEMMODE_FSTART_SHIFT;
4554
616847e7 4555 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4556 PXVFREQ_PX_SHIFT;
4557
20e4d407
DV		 4558 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4559 dev_priv->ips.fstart = fstart;
2b4e57bd 4560
20e4d407
DV		 4561 dev_priv->ips.max_delay = fstart;
4562 dev_priv->ips.min_delay = fmin;
4563 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4564
4565 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4566 fmax, fmin, fstart);
4567
4568 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4569
4570 /*
4571 * Interrupts will be enabled in ironlake_irq_postinstall
4572 */
4573
4574 I915_WRITE(VIDSTART, vstart);
4575 POSTING_READ(VIDSTART);
4576
4577 rgvmodectl |= MEMMODE_SWMODE_EN;
4578 I915_WRITE(MEMMODECTL, rgvmodectl);
4579
9270388e 4580 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4581 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4582 mdelay(1);
2b4e57bd 4583
91d14251 4584 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4585
7d81c3e0
VS		 4586 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4587 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4588 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4589 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4590 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4591
4592 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4593}
4594
91d14251 4595static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4596{
9270388e
DV		 4597 u16 rgvswctl;
4598
4599 spin_lock_irq(&mchdev_lock);
4600
4601 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4602
4603 /* Ack interrupts, disable EFC interrupt */
4604 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4605 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4606 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4607 I915_WRITE(DEIIR, DE_PCU_EVENT);
4608 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4609
4610 /* Go back to the starting frequency */
91d14251 4611 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4612 mdelay(1);
2b4e57bd
ED		 4613 rgvswctl |= MEMCTL_CMD_STS;
4614 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4615 mdelay(1);
2b4e57bd 4616
9270388e 4617 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4618}
4619
acbe9475
DV		 4620/* There's a funny hw issue where the hw returns all 0 when reading from
4621 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4622 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4623 * all limits and the gpu stuck at whatever frequency it is at atm).
4624 */
74ef1173 4625static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4626{
7b9e0ae6 4627 u32 limits;
2b4e57bd 4628
20b46e59
DV		 4629 /* Only set the down limit when we've reached the lowest level to avoid
4630 * getting more interrupts, otherwise leave this clear. This prevents a
4631 * race in the hw when coming out of rc6: There's a tiny window where
4632 * the hw runs at the minimal clock before selecting the desired
4633 * frequency, if the down threshold expires in that window we will not
4634 * receive a down interrupt. */
2d1fe073 4635 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4636 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4637 if (val <= dev_priv->rps.min_freq_softlimit)
4638 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4639 } else {
4640 limits = dev_priv->rps.max_freq_softlimit << 24;
4641 if (val <= dev_priv->rps.min_freq_softlimit)
4642 limits |= dev_priv->rps.min_freq_softlimit << 16;
4643 }
20b46e59
DV		 4644
4645 return limits;
4646}
4647
dd75fdc8
CW		 4648static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4649{
4650 int new_power;
8a586437
AG		 4651 u32 threshold_up = 0, threshold_down = 0; /* in % */
4652 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4653
4654 new_power = dev_priv->rps.power;
4655 switch (dev_priv->rps.power) {
4656 case LOW_POWER:
b39fb297 4657 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4658 new_power = BETWEEN;
4659 break;
4660
4661 case BETWEEN:
b39fb297 4662 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4663 new_power = LOW_POWER;
b39fb297 4664 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4665 new_power = HIGH_POWER;
4666 break;
4667
4668 case HIGH_POWER:
b39fb297 4669 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4670 new_power = BETWEEN;
4671 break;
4672 }
4673 /* Max/min bins are special */
aed242ff 4674 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4675 new_power = LOW_POWER;
aed242ff 4676 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4677 new_power = HIGH_POWER;
4678 if (new_power == dev_priv->rps.power)
4679 return;
4680
4681 /* Note the units here are not exactly 1us, but 1280ns. */
4682 switch (new_power) {
4683 case LOW_POWER:
4684 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4685 ei_up = 16000;
4686 threshold_up = 95;
dd75fdc8
CW		 4687
4688 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4689 ei_down = 32000;
4690 threshold_down = 85;
dd75fdc8
CW		 4691 break;
4692
4693 case BETWEEN:
4694 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4695 ei_up = 13000;
4696 threshold_up = 90;
dd75fdc8
CW		 4697
4698 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4699 ei_down = 32000;
4700 threshold_down = 75;
dd75fdc8
CW		 4701 break;
4702
4703 case HIGH_POWER:
4704 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4705 ei_up = 10000;
4706 threshold_up = 85;
dd75fdc8
CW		 4707
4708 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4709 ei_down = 32000;
4710 threshold_down = 60;
dd75fdc8
CW		 4711 break;
4712 }
4713
8a586437
AG		 4714 I915_WRITE(GEN6_RP_UP_EI,
4715 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4716 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4717 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4718
4719 I915_WRITE(GEN6_RP_DOWN_EI,
4720 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4721 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4722 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4723
4724 I915_WRITE(GEN6_RP_CONTROL,
4725 GEN6_RP_MEDIA_TURBO |
4726 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4727 GEN6_RP_MEDIA_IS_GFX |
4728 GEN6_RP_ENABLE |
4729 GEN6_RP_UP_BUSY_AVG |
4730 GEN6_RP_DOWN_IDLE_AVG);
4731
dd75fdc8 4732 dev_priv->rps.power = new_power;
8fb55197
CW		 4733 dev_priv->rps.up_threshold = threshold_up;
4734 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4735 dev_priv->rps.last_adj = 0;
4736}
4737
2876ce73
CW		 4738static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4739{
4740 u32 mask = 0;
4741
4742 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4743 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4744 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4745 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4746
7b3c29f6
CW		 4747 mask &= dev_priv->pm_rps_events;
4748
59d02a1f 4749 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4750}
4751
b8a5ff8d
JM		 4752/* gen6_set_rps is called to update the frequency request, but should also be
4753 * called when the range (min_delay and max_delay) is modified so that we can
4754 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4755static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4756{
23eafea6 4757 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4758 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4759 return;
4760
4fc688ce 4761 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4762 WARN_ON(val > dev_priv->rps.max_freq);
4763 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4764
eb64cad1
CW		 4765 /* min/max delay may still have been modified so be sure to
4766 * write the limits value.
4767 */
4768 if (val != dev_priv->rps.cur_freq) {
4769 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4770
dc97997a 4771 if (IS_GEN9(dev_priv))
5704195c
AG		 4772 I915_WRITE(GEN6_RPNSWREQ,
4773 GEN9_FREQUENCY(val));
dc97997a 4774 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4775 I915_WRITE(GEN6_RPNSWREQ,
4776 HSW_FREQUENCY(val));
4777 else
4778 I915_WRITE(GEN6_RPNSWREQ,
4779 GEN6_FREQUENCY(val) |
4780 GEN6_OFFSET(0) |
4781 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4782 }
7b9e0ae6 4783
7b9e0ae6
CW		 4784 /* Make sure we continue to get interrupts
4785 * until we hit the minimum or maximum frequencies.
4786 */
74ef1173 4787 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4788 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4789
d5570a72
BW		 4790 POSTING_READ(GEN6_RPNSWREQ);
4791
b39fb297 4792 dev_priv->rps.cur_freq = val;
0f94592e 4793 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4794}
4795
dc97997a 4796static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4797{
ffe02b40 4798 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4799 WARN_ON(val > dev_priv->rps.max_freq);
4800 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4801
dc97997a 4802 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4803 "Odd GPU freq value\n"))
4804 val &= ~1;
4805
cd25dd5b
D		 4806 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4807
8fb55197 4808 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4809 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4810 if (!IS_CHERRYVIEW(dev_priv))
4811 gen6_set_rps_thresholds(dev_priv, val);
4812 }
ffe02b40 4813
ffe02b40
VS		 4814 dev_priv->rps.cur_freq = val;
4815 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4816}
4817
a7f6e231 4818/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4819 *
4820 * * If Gfx is Idle, then
a7f6e231
D		 4821 * 1. Forcewake Media well.
4822 * 2. Request idle freq.
4823 * 3. Release Forcewake of Media well.
76c3552f
D		 4824*/
4825static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4826{
aed242ff 4827 u32 val = dev_priv->rps.idle_freq;
5549d25f 4828
aed242ff 4829 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4830 return;
4831
a7f6e231
D		 4832 /* Wake up the media well, as that takes a lot less
4833 * power than the Render well. */
4834 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4835 valleyview_set_rps(dev_priv, val);
a7f6e231 4836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4837}
4838
43cf3bf0
CW		 4839void gen6_rps_busy(struct drm_i915_private *dev_priv)
4840{
4841 mutex_lock(&dev_priv->rps.hw_lock);
4842 if (dev_priv->rps.enabled) {
4843 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4844 gen6_rps_reset_ei(dev_priv);
4845 I915_WRITE(GEN6_PMINTRMSK,
4846 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4847 }
4848 mutex_unlock(&dev_priv->rps.hw_lock);
4849}
4850
b29c19b6
CW		 4851void gen6_rps_idle(struct drm_i915_private *dev_priv)
4852{
4853 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4854 if (dev_priv->rps.enabled) {
dc97997a 4855 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4856 vlv_set_rps_idle(dev_priv);
7526ed79 4857 else
dc97997a 4858 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4859 dev_priv->rps.last_adj = 0;
43cf3bf0 4860 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4861 }
8d3afd7d 4862 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4863
8d3afd7d 4864 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4865 while (!list_empty(&dev_priv->rps.clients))
4866 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4867 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4868}
4869
1854d5ca 4870void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4871 struct intel_rps_client *rps,
4872 unsigned long submitted)
b29c19b6 4873{
8d3afd7d
CW		 4874 /* This is intentionally racy! We peek at the state here, then
4875 * validate inside the RPS worker.
4876 */
4877 if (!(dev_priv->mm.busy &&
4878 dev_priv->rps.enabled &&
4879 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4880 return;
43cf3bf0 4881
e61b9958
CW		 4882 /* Force a RPS boost (and don't count it against the client) if
4883 * the GPU is severely congested.
4884 */
d0bc54f2 4885 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4886 rps = NULL;
4887
8d3afd7d
CW		 4888 spin_lock(&dev_priv->rps.client_lock);
4889 if (rps == NULL || list_empty(&rps->link)) {
4890 spin_lock_irq(&dev_priv->irq_lock);
4891 if (dev_priv->rps.interrupts_enabled) {
4892 dev_priv->rps.client_boost = true;
4893 queue_work(dev_priv->wq, &dev_priv->rps.work);
4894 }
4895 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4896
2e1b8730
CW		 4897 if (rps != NULL) {
4898 list_add(&rps->link, &dev_priv->rps.clients);
4899 rps->boosts++;
1854d5ca
CW		 4900 } else
4901 dev_priv->rps.boosts++;
c0951f0c 4902 }
8d3afd7d 4903 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4904}
4905
dc97997a 4906void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4907{
dc97997a
CW		 4908 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4909 valleyview_set_rps(dev_priv, val);
ffe02b40 4910 else
dc97997a 4911 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4912}
4913
dc97997a 4914static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4915{
20e49366 4916 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4917 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4918}
4919
dc97997a 4920static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4921{
2030d684
AG		 4922 I915_WRITE(GEN6_RP_CONTROL, 0);
4923}
4924
dc97997a 4925static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4926{
d20d4f0c 4927 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4928 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4929 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4930}
4931
dc97997a 4932static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4933{
38807746
D		 4934 I915_WRITE(GEN6_RC_CONTROL, 0);
4935}
4936
dc97997a 4937static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4938{
98a2e5f9
D		 4939 /* we're doing forcewake before Disabling RC6,
4940 * This what the BIOS expects when going into suspend */
59bad947 4941 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4942
44fc7d5c 4943 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4944
59bad947 4945 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4946}
4947
dc97997a 4948static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4949{
dc97997a 4950 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4951 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4952 mode = GEN6_RC_CTL_RC6_ENABLE;
4953 else
4954 mode = 0;
4955 }
dc97997a 4956 if (HAS_RC6p(dev_priv))
58abf1da 4957 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4958 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4959 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4960 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4961
4962 else
4963 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4964 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4965}
4966
dc97997a 4967static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 4968{
72e96d64 4969 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4970 bool enable_rc6 = true;
4971 unsigned long rc6_ctx_base;
4972
4973 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4974 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4975 enable_rc6 = false;
4976 }
4977
4978 /*
4979 * The exact context size is not known for BXT, so assume a page size
4980 * for this check.
4981 */
4982 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4983 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4984 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4985 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4986 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4987 enable_rc6 = false;
4988 }
4989
4990 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4991 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4992 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4993 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4994 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4995 enable_rc6 = false;
4996 }
4997
4998 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4999 GEN6_RC_CTL_HW_ENABLE)) &&
5000 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
5001 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
5002 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
5003 enable_rc6 = false;
5004 }
5005
5006 return enable_rc6;
5007}
5008
dc97997a 5009int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5010{
e7d66d89 5011 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5012 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5013 return 0;
5014
274008e8
SAK		 5015 if (!enable_rc6)
5016 return 0;
5017
dc97997a 5018 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5019 DRM_INFO("RC6 disabled by BIOS\n");
5020 return 0;
5021 }
5022
456470eb 5023 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5024 if (enable_rc6 >= 0) {
5025 int mask;
5026
dc97997a 5027 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5028 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5029 INTEL_RC6pp_ENABLE;
5030 else
5031 mask = INTEL_RC6_ENABLE;
5032
5033 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 5034 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5035 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5036
5037 return enable_rc6 & mask;
5038 }
2b4e57bd 5039
dc97997a 5040 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5041 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5042
5043 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5044}
5045
dc97997a 5046static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0 5047{
93ee2920
TR		 5048 uint32_t rp_state_cap;
5049 u32 ddcc_status = 0;
5050 int ret;
5051
3280e8b0
BW		 5052 /* All of these values are in units of 50MHz */
5053 dev_priv->rps.cur_freq = 0;
93ee2920 5054 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5055 if (IS_BROXTON(dev_priv)) {
35040562
BP		 5056 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5057 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5058 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5059 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5060 } else {
5061 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5062 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5063 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5064 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5065 }
5066
3280e8b0
BW		 5067 /* hw_max = RP0 until we check for overclocking */
5068 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5069
93ee2920 5070 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5071 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5072 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
93ee2920
TR		 5073 ret = sandybridge_pcode_read(dev_priv,
5074 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5075 &ddcc_status);
5076 if (0 == ret)
5077 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5078 clamp_t(u8,
5079 ((ddcc_status >> 8) & 0xff),
5080 dev_priv->rps.min_freq,
5081 dev_priv->rps.max_freq);
93ee2920
TR		 5082 }
5083
dc97997a 5084 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c
AG		 5085 /* Store the frequency values in 16.66 MHZ units, which is
5086 the natural hardware unit for SKL */
5087 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5088 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5089 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5090 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5091 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5092 }
5093
aed242ff
CW		 5094 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5095
3280e8b0
BW		 5096 /* Preserve min/max settings in case of re-init */
5097 if (dev_priv->rps.max_freq_softlimit == 0)
5098 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5099
93ee2920 5100 if (dev_priv->rps.min_freq_softlimit == 0) {
dc97997a 5101 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
93ee2920 5102 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 5103 max_t(int, dev_priv->rps.efficient_freq,
5104 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 5105 else
5106 dev_priv->rps.min_freq_softlimit =
5107 dev_priv->rps.min_freq;
5108 }
3280e8b0
BW		 5109}
5110
b6fef0ef 5111/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5112static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5113{
b6fef0ef
JB		 5114 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5115
dc97997a 5116 gen6_init_rps_frequencies(dev_priv);
ba1c554c 5117
23eafea6 5118 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5119 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5120 /*
5121 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5122 * clear out the Control register just to avoid inconsitency
5123 * with debugfs interface, which will show Turbo as enabled
5124 * only and that is not expected by the User after adding the
5125 * WaGsvDisableTurbo. Apart from this there is no problem even
5126 * if the Turbo is left enabled in the Control register, as the
5127 * Up/Down interrupts would remain masked.
5128 */
dc97997a 5129 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5130 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5131 return;
5132 }
5133
0beb059a
AG		 5134 /* Program defaults and thresholds for RPS*/
5135 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5136 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5137
5138 /* 1 second timeout*/
5139 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5140 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5141
b6fef0ef 5142 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5143
0beb059a
AG		 5144 /* Leaning on the below call to gen6_set_rps to program/setup the
5145 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5146 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5147 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5148 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
b6fef0ef
JB		 5149
5150 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5151}
5152
dc97997a 5153static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5154{
e2f80391 5155 struct intel_engine_cs *engine;
20e49366 5156 uint32_t rc6_mask = 0;
20e49366
ZW		 5157
5158 /* 1a: Software RC state - RC0 */
5159 I915_WRITE(GEN6_RC_STATE, 0);
5160
5161 /* 1b: Get forcewake during program sequence. Although the driver
5162 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5163 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5164
5165 /* 2a: Disable RC states. */
5166 I915_WRITE(GEN6_RC_CONTROL, 0);
5167
5168 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5169
5170 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5171 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5172 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5173 else
5174 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5175 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5176 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5177 for_each_engine(engine, dev_priv)
e2f80391 5178 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5179
1a3d1898 5180 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5181 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5182
20e49366 5183 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5184
38c23527
ZW		 5185 /* 2c: Program Coarse Power Gating Policies. */
5186 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5187 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5188
20e49366 5189 /* 3a: Enable RC6 */
dc97997a 5190 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5191 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5192 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5193 /* WaRsUseTimeoutMode */
dc97997a
CW		 5194 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5195 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5196 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5197 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5198 GEN7_RC_CTL_TO_MODE |
5199 rc6_mask);
3e7732a0
SAK		 5200 } else {
5201 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5202 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5203 GEN6_RC_CTL_EI_MODE(1) |
5204 rc6_mask);
3e7732a0 5205 }
20e49366 5206
cb07bae0
SK		 5207 /*
5208 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5209 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5210 */
dc97997a 5211 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5212 I915_WRITE(GEN9_PG_ENABLE, 0);
5213 else
5214 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5215 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5216
59bad947 5217 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5218}
5219
dc97997a 5220static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5221{
e2f80391 5222 struct intel_engine_cs *engine;
93ee2920 5223 uint32_t rc6_mask = 0;
6edee7f3
BW		 5224
5225 /* 1a: Software RC state - RC0 */
5226 I915_WRITE(GEN6_RC_STATE, 0);
5227
5228 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5229 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5230 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5231
5232 /* 2a: Disable RC states. */
5233 I915_WRITE(GEN6_RC_CONTROL, 0);
5234
93ee2920 5235 /* Initialize rps frequencies */
dc97997a 5236 gen6_init_rps_frequencies(dev_priv);
6edee7f3
BW		 5237
5238 /* 2b: Program RC6 thresholds.*/
5239 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5240 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5241 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5242 for_each_engine(engine, dev_priv)
e2f80391 5243 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5244 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5245 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5246 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5247 else
5248 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5249
5250 /* 3: Enable RC6 */
dc97997a 5251 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5252 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5253 intel_print_rc6_info(dev_priv, rc6_mask);
5254 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5255 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5256 GEN7_RC_CTL_TO_MODE |
5257 rc6_mask);
5258 else
5259 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5260 GEN6_RC_CTL_EI_MODE(1) |
5261 rc6_mask);
6edee7f3
BW		 5262
5263 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5264 I915_WRITE(GEN6_RPNSWREQ,
5265 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5266 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5267 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5268 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5269 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5270
5271 /* Docs recommend 900MHz, and 300 MHz respectively */
5272 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5273 dev_priv->rps.max_freq_softlimit << 24 |
5274 dev_priv->rps.min_freq_softlimit << 16);
5275
5276 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5277 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5278 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5279 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5280
5281 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5282
5283 /* 5: Enable RPS */
7526ed79
DV		 5284 I915_WRITE(GEN6_RP_CONTROL,
5285 GEN6_RP_MEDIA_TURBO |
5286 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5287 GEN6_RP_MEDIA_IS_GFX |
5288 GEN6_RP_ENABLE |
5289 GEN6_RP_UP_BUSY_AVG |
5290 GEN6_RP_DOWN_IDLE_AVG);
5291
5292 /* 6: Ring frequency + overclocking (our driver does this later */
5293
c7f3153a 5294 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5295 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
7526ed79 5296
59bad947 5297 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5298}
5299
dc97997a 5300static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5301{
e2f80391 5302 struct intel_engine_cs *engine;
d060c169 5303 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5304 u32 gtfifodbg;
2b4e57bd 5305 int rc6_mode;
b4ac5afc 5306 int ret;
2b4e57bd 5307
4fc688ce 5308 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5309
2b4e57bd
ED		 5310 /* Here begins a magic sequence of register writes to enable
5311 * auto-downclocking.
5312 *
5313 * Perhaps there might be some value in exposing these to
5314 * userspace...
5315 */
5316 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5317
5318 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5319 gtfifodbg = I915_READ(GTFIFODBG);
5320 if (gtfifodbg) {
2b4e57bd
ED		 5321 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5322 I915_WRITE(GTFIFODBG, gtfifodbg);
5323 }
5324
59bad947 5325 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5326
93ee2920 5327 /* Initialize rps frequencies */
dc97997a 5328 gen6_init_rps_frequencies(dev_priv);
dd0a1aa1 5329
2b4e57bd
ED		 5330 /* disable the counters and set deterministic thresholds */
5331 I915_WRITE(GEN6_RC_CONTROL, 0);
5332
5333 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5334 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5335 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5336 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5337 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5338
b4ac5afc 5339 for_each_engine(engine, dev_priv)
e2f80391 5340 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5341
5342 I915_WRITE(GEN6_RC_SLEEP, 0);
5343 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5344 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5345 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5346 else
5347 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5348 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5349 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5350
5a7dc92a 5351 /* Check if we are enabling RC6 */
dc97997a 5352 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5353 if (rc6_mode & INTEL_RC6_ENABLE)
5354 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5355
5a7dc92a 5356 /* We don't use those on Haswell */
dc97997a 5357 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5358 if (rc6_mode & INTEL_RC6p_ENABLE)
5359 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5360
5a7dc92a
ED		 5361 if (rc6_mode & INTEL_RC6pp_ENABLE)
5362 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5363 }
2b4e57bd 5364
dc97997a 5365 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5366
5367 I915_WRITE(GEN6_RC_CONTROL,
5368 rc6_mask |
5369 GEN6_RC_CTL_EI_MODE(1) |
5370 GEN6_RC_CTL_HW_ENABLE);
5371
dd75fdc8
CW		 5372 /* Power down if completely idle for over 50ms */
5373 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5374 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5375
42c0526c 5376 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5377 if (ret)
42c0526c 5378 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5379
5380 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5381 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5382 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5383 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5384 (pcu_mbox & 0xff) * 50);
b39fb297 5385 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5386 }
5387
dd75fdc8 5388 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5389 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b4e57bd 5390
31643d54
BW		 5391 rc6vids = 0;
5392 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5393 if (IS_GEN6(dev_priv) && ret) {
31643d54 5394 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5395 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5396 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5397 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5398 rc6vids &= 0xffff00;
5399 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5400 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5401 if (ret)
5402 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5403 }
5404
59bad947 5405 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5406}
5407
dc97997a 5408static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5409{
5410 int min_freq = 15;
3ebecd07
CW		 5411 unsigned int gpu_freq;
5412 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5413 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5414 int scaling_factor = 180;
eda79642 5415 struct cpufreq_policy *policy;
2b4e57bd 5416
4fc688ce 5417 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5418
eda79642
BW		 5419 policy = cpufreq_cpu_get(0);
5420 if (policy) {
5421 max_ia_freq = policy->cpuinfo.max_freq;
5422 cpufreq_cpu_put(policy);
5423 } else {
5424 /*
5425 * Default to measured freq if none found, PCU will ensure we
5426 * don't go over
5427 */
2b4e57bd 5428 max_ia_freq = tsc_khz;
eda79642 5429 }
2b4e57bd
ED		 5430
5431 /* Convert from kHz to MHz */
5432 max_ia_freq /= 1000;
5433
153b4b95 5434 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5435 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5436 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5437
dc97997a 5438 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5439 /* Convert GT frequency to 50 HZ units */
5440 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5441 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5442 } else {
5443 min_gpu_freq = dev_priv->rps.min_freq;
5444 max_gpu_freq = dev_priv->rps.max_freq;
5445 }
5446
2b4e57bd
ED		 5447 /*
5448 * For each potential GPU frequency, load a ring frequency we'd like
5449 * to use for memory access. We do this by specifying the IA frequency
5450 * the PCU should use as a reference to determine the ring frequency.
5451 */
4c8c7743
AG		 5452 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5453 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5454 unsigned int ia_freq = 0, ring_freq = 0;
5455
dc97997a 5456 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5457 /*
5458 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5459 * No floor required for ring frequency on SKL.
5460 */
5461 ring_freq = gpu_freq;
dc97997a 5462 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5463 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5464 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5465 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5466 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5467 ring_freq = max(min_ring_freq, ring_freq);
5468 /* leave ia_freq as the default, chosen by cpufreq */
5469 } else {
5470 /* On older processors, there is no separate ring
5471 * clock domain, so in order to boost the bandwidth
5472 * of the ring, we need to upclock the CPU (ia_freq).
5473 *
5474 * For GPU frequencies less than 750MHz,
5475 * just use the lowest ring freq.
5476 */
5477 if (gpu_freq < min_freq)
5478 ia_freq = 800;
5479 else
5480 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5481 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5482 }
2b4e57bd 5483
42c0526c
BW		 5484 sandybridge_pcode_write(dev_priv,
5485 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5486 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5487 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5488 gpu_freq);
2b4e57bd 5489 }
2b4e57bd
ED		 5490}
5491
dc97997a 5492void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
c2bc2fc5 5493{
dc97997a 5494 if (!HAS_CORE_RING_FREQ(dev_priv))
c2bc2fc5
ID		 5495 return;
5496
5497 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a 5498 __gen6_update_ring_freq(dev_priv);
c2bc2fc5
ID		 5499 mutex_unlock(&dev_priv->rps.hw_lock);
5500}
5501
03af2045 5502static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5503{
5504 u32 val, rp0;
5505
5b5929cb 5506 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5507
dc97997a 5508 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5509 case 8:
5510 /* (2 * 4) config */
5511 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5512 break;
5513 case 12:
5514 /* (2 * 6) config */
5515 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5516 break;
5517 case 16:
5518 /* (2 * 8) config */
5519 default:
5520 /* Setting (2 * 8) Min RP0 for any other combination */
5521 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5522 break;
095acd5f 5523 }
5b5929cb
JN		 5524
5525 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5526
2b6b3a09
D		 5527 return rp0;
5528}
5529
5530static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5531{
5532 u32 val, rpe;
5533
5534 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5535 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5536
5537 return rpe;
5538}
5539
7707df4a
D		 5540static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5541{
5542 u32 val, rp1;
5543
5b5929cb
JN		 5544 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5545 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5546
7707df4a
D		 5547 return rp1;
5548}
5549
f8f2b001
D		 5550static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5551{
5552 u32 val, rp1;
5553
5554 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5555
5556 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5557
5558 return rp1;
5559}
5560
03af2045 5561static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5562{
5563 u32 val, rp0;
5564
64936258 5565 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5566
5567 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5568 /* Clamp to max */
5569 rp0 = min_t(u32, rp0, 0xea);
5570
5571 return rp0;
5572}
5573
5574static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5575{
5576 u32 val, rpe;
5577
64936258 5578 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5579 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5580 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5581 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5582
5583 return rpe;
5584}
5585
03af2045 5586static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5587{
36146035
ID		 5588 u32 val;
5589
5590 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5591 /*
5592 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5593 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5594 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5595 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5596 * to make sure it matches what Punit accepts.
5597 */
5598 return max_t(u32, val, 0xc0);
0a073b84
JB		 5599}
5600
ae48434c
ID		 5601/* Check that the pctx buffer wasn't move under us. */
5602static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5603{
5604 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5605
5606 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5607 dev_priv->vlv_pctx->stolen->start);
5608}
5609
38807746
D		 5610
5611/* Check that the pcbr address is not empty. */
5612static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5613{
5614 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5615
5616 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5617}
5618
dc97997a 5619static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5620{
62106b4f 5621 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5622 unsigned long pctx_paddr, paddr;
38807746
D		 5623 u32 pcbr;
5624 int pctx_size = 32*1024;
5625
38807746
D		 5626 pcbr = I915_READ(VLV_PCBR);
5627 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5628 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5629 paddr = (dev_priv->mm.stolen_base +
62106b4f 5630 (ggtt->stolen_size - pctx_size));
38807746
D		 5631
5632 pctx_paddr = (paddr & (~4095));
5633 I915_WRITE(VLV_PCBR, pctx_paddr);
5634 }
ce611ef8
VS		 5635
5636 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5637}
5638
dc97997a 5639static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5640{
c9cddffc
JB		 5641 struct drm_i915_gem_object *pctx;
5642 unsigned long pctx_paddr;
5643 u32 pcbr;
5644 int pctx_size = 24*1024;
5645
dc97997a 5646 mutex_lock(&dev_priv->dev->struct_mutex);
17b0c1f7 5647
c9cddffc
JB		 5648 pcbr = I915_READ(VLV_PCBR);
5649 if (pcbr) {
5650 /* BIOS set it up already, grab the pre-alloc'd space */
5651 int pcbr_offset;
5652
5653 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5654 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5655 pcbr_offset,
190d6cd5 5656 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5657 pctx_size);
5658 goto out;
5659 }
5660
ce611ef8
VS		 5661 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5662
c9cddffc
JB		 5663 /*
5664 * From the Gunit register HAS:
5665 * The Gfx driver is expected to program this register and ensure
5666 * proper allocation within Gfx stolen memory. For example, this
5667 * register should be programmed such than the PCBR range does not
5668 * overlap with other ranges, such as the frame buffer, protected
5669 * memory, or any other relevant ranges.
5670 */
dc97997a 5671 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
c9cddffc
JB		 5672 if (!pctx) {
5673 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5674 goto out;
c9cddffc
JB		 5675 }
5676
5677 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5678 I915_WRITE(VLV_PCBR, pctx_paddr);
5679
5680out:
ce611ef8 5681 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5682 dev_priv->vlv_pctx = pctx;
dc97997a 5683 mutex_unlock(&dev_priv->dev->struct_mutex);
c9cddffc
JB		 5684}
5685
dc97997a 5686static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5687{
ae48434c
ID		 5688 if (WARN_ON(!dev_priv->vlv_pctx))
5689 return;
5690
ee504898 5691 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5692 dev_priv->vlv_pctx = NULL;
5693}
5694
c30fec65
VS		 5695static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5696{
5697 dev_priv->rps.gpll_ref_freq =
5698 vlv_get_cck_clock(dev_priv, "GPLL ref",
5699 CCK_GPLL_CLOCK_CONTROL,
5700 dev_priv->czclk_freq);
5701
5702 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5703 dev_priv->rps.gpll_ref_freq);
5704}
5705
dc97997a 5706static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5707{
2bb25c17 5708 u32 val;
4e80519e 5709
dc97997a 5710 valleyview_setup_pctx(dev_priv);
4e80519e 5711
c30fec65
VS		 5712 vlv_init_gpll_ref_freq(dev_priv);
5713
4e80519e
ID		 5714 mutex_lock(&dev_priv->rps.hw_lock);
5715
2bb25c17
VS		 5716 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5717 switch ((val >> 6) & 3) {
5718 case 0:
5719 case 1:
5720 dev_priv->mem_freq = 800;
5721 break;
5722 case 2:
5723 dev_priv->mem_freq = 1066;
5724 break;
5725 case 3:
5726 dev_priv->mem_freq = 1333;
5727 break;
5728 }
80b83b62 5729 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5730
4e80519e
ID		 5731 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5732 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5733 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5734 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5735 dev_priv->rps.max_freq);
5736
5737 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5738 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5739 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5740 dev_priv->rps.efficient_freq);
5741
f8f2b001
D		 5742 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5743 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5744 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5745 dev_priv->rps.rp1_freq);
5746
4e80519e
ID		 5747 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5748 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5749 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5750 dev_priv->rps.min_freq);
5751
aed242ff
CW		 5752 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5753
4e80519e
ID		 5754 /* Preserve min/max settings in case of re-init */
5755 if (dev_priv->rps.max_freq_softlimit == 0)
5756 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5757
5758 if (dev_priv->rps.min_freq_softlimit == 0)
5759 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5760
5761 mutex_unlock(&dev_priv->rps.hw_lock);
5762}
5763
dc97997a 5764static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5765{
2bb25c17 5766 u32 val;
2b6b3a09 5767
dc97997a 5768 cherryview_setup_pctx(dev_priv);
2b6b3a09 5769
c30fec65
VS		 5770 vlv_init_gpll_ref_freq(dev_priv);
5771
2b6b3a09
D		 5772 mutex_lock(&dev_priv->rps.hw_lock);
5773
a580516d 5774 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5775 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5776 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5777
2bb25c17 5778 switch ((val >> 2) & 0x7) {
2bb25c17 5779 case 3:
2bb25c17
VS		 5780 dev_priv->mem_freq = 2000;
5781 break;
bfa7df01 5782 default:
2bb25c17
VS		 5783 dev_priv->mem_freq = 1600;
5784 break;
5785 }
80b83b62 5786 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5787
2b6b3a09
D		 5788 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5789 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5790 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5791 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5792 dev_priv->rps.max_freq);
5793
5794 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5795 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5796 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5797 dev_priv->rps.efficient_freq);
5798
7707df4a
D		 5799 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5800 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5801 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5802 dev_priv->rps.rp1_freq);
5803
5b7c91b7
D		 5804 /* PUnit validated range is only [RPe, RP0] */
5805 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5806 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5807 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5808 dev_priv->rps.min_freq);
5809
1c14762d
VS		 5810 WARN_ONCE((dev_priv->rps.max_freq |
5811 dev_priv->rps.efficient_freq |
5812 dev_priv->rps.rp1_freq |
5813 dev_priv->rps.min_freq) & 1,
5814 "Odd GPU freq values\n");
5815
aed242ff
CW		 5816 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5817
2b6b3a09
D		 5818 /* Preserve min/max settings in case of re-init */
5819 if (dev_priv->rps.max_freq_softlimit == 0)
5820 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5821
5822 if (dev_priv->rps.min_freq_softlimit == 0)
5823 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5824
5825 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5826}
5827
dc97997a 5828static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5829{
dc97997a 5830 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5831}
5832
dc97997a 5833static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5834{
e2f80391 5835 struct intel_engine_cs *engine;
2b6b3a09 5836 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5837
5838 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5839
297b32ec
VS		 5840 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5841 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5842 if (gtfifodbg) {
5843 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5844 gtfifodbg);
5845 I915_WRITE(GTFIFODBG, gtfifodbg);
5846 }
5847
5848 cherryview_check_pctx(dev_priv);
5849
5850 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5851 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5852 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5853
160614a2
VS		 5854 /* Disable RC states. */
5855 I915_WRITE(GEN6_RC_CONTROL, 0);
5856
38807746
D		 5857 /* 2a: Program RC6 thresholds.*/
5858 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5859 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5860 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5861
b4ac5afc 5862 for_each_engine(engine, dev_priv)
e2f80391 5863 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5864 I915_WRITE(GEN6_RC_SLEEP, 0);
5865
f4f71c7d
D		 5866 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5867 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5868
5869 /* allows RC6 residency counter to work */
5870 I915_WRITE(VLV_COUNTER_CONTROL,
5871 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5872 VLV_MEDIA_RC6_COUNT_EN |
5873 VLV_RENDER_RC6_COUNT_EN));
5874
5875 /* For now we assume BIOS is allocating and populating the PCBR */
5876 pcbr = I915_READ(VLV_PCBR);
5877
38807746 5878 /* 3: Enable RC6 */
dc97997a
CW		 5879 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5880 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5881 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5882
5883 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5884
2b6b3a09 5885 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5887 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5888 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5889 I915_WRITE(GEN6_RP_UP_EI, 66000);
5890 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5891
5892 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5893
5894 /* 5: Enable RPS */
5895 I915_WRITE(GEN6_RP_CONTROL,
5896 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5897 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5898 GEN6_RP_ENABLE |
5899 GEN6_RP_UP_BUSY_AVG |
5900 GEN6_RP_DOWN_IDLE_AVG);
5901
3ef62342
D		 5902 /* Setting Fixed Bias */
5903 val = VLV_OVERRIDE_EN |
5904 VLV_SOC_TDP_EN |
5905 CHV_BIAS_CPU_50_SOC_50;
5906 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5907
2b6b3a09
D		 5908 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5909
8d40c3ae
VS		 5910 /* RPS code assumes GPLL is used */
5911 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5912
742f491d 5913 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5914 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5915
5916 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5917 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5918 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5919 dev_priv->rps.cur_freq);
5920
5921 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5922 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5923 dev_priv->rps.idle_freq);
2b6b3a09 5924
dc97997a 5925 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b6b3a09 5926
59bad947 5927 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5928}
5929
dc97997a 5930static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5931{
e2f80391 5932 struct intel_engine_cs *engine;
2a5913a8 5933 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5934
5935 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5936
ae48434c
ID		 5937 valleyview_check_pctx(dev_priv);
5938
297b32ec
VS		 5939 gtfifodbg = I915_READ(GTFIFODBG);
5940 if (gtfifodbg) {
f7d85c1e
JB		 5941 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5942 gtfifodbg);
0a073b84
JB		 5943 I915_WRITE(GTFIFODBG, gtfifodbg);
5944 }
5945
c8d9a590 5946 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5947 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5948
160614a2
VS		 5949 /* Disable RC states. */
5950 I915_WRITE(GEN6_RC_CONTROL, 0);
5951
cad725fe 5952 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5953 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5954 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5955 I915_WRITE(GEN6_RP_UP_EI, 66000);
5956 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5957
5958 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5959
5960 I915_WRITE(GEN6_RP_CONTROL,
5961 GEN6_RP_MEDIA_TURBO |
5962 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5963 GEN6_RP_MEDIA_IS_GFX |
5964 GEN6_RP_ENABLE |
5965 GEN6_RP_UP_BUSY_AVG |
5966 GEN6_RP_DOWN_IDLE_CONT);
5967
5968 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5969 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5970 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5971
b4ac5afc 5972 for_each_engine(engine, dev_priv)
e2f80391 5973 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5974
2f0aa304 5975 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5976
5977 /* allows RC6 residency counter to work */
49798eb2 5978 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5979 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5980 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5981 VLV_MEDIA_RC6_COUNT_EN |
5982 VLV_RENDER_RC6_COUNT_EN));
31685c25 5983
dc97997a 5984 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5985 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5986
dc97997a 5987 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5988
a2b23fe0 5989 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5990
3ef62342
D		 5991 /* Setting Fixed Bias */
5992 val = VLV_OVERRIDE_EN |
5993 VLV_SOC_TDP_EN |
5994 VLV_BIAS_CPU_125_SOC_875;
5995 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5996
64936258 5997 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5998
8d40c3ae
VS		 5999 /* RPS code assumes GPLL is used */
6000 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6001
742f491d 6002 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6003 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6004
b39fb297 6005 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 6006 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 6007 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 6008 dev_priv->rps.cur_freq);
0a073b84 6009
73008b98 6010 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 6011 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
6012 dev_priv->rps.idle_freq);
0a073b84 6013
dc97997a 6014 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
0a073b84 6015
59bad947 6016 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6017}
6018
dde18883
ED		 6019static unsigned long intel_pxfreq(u32 vidfreq)
6020{
6021 unsigned long freq;
6022 int div = (vidfreq & 0x3f0000) >> 16;
6023 int post = (vidfreq & 0x3000) >> 12;
6024 int pre = (vidfreq & 0x7);
6025
6026 if (!pre)
6027 return 0;
6028
6029 freq = ((div * 133333) / ((1<<post) * pre));
6030
6031 return freq;
6032}
6033
eb48eb00
DV		 6034static const struct cparams {
6035 u16 i;
6036 u16 t;
6037 u16 m;
6038 u16 c;
6039} cparams[] = {
6040 { 1, 1333, 301, 28664 },
6041 { 1, 1066, 294, 24460 },
6042 { 1, 800, 294, 25192 },
6043 { 0, 1333, 276, 27605 },
6044 { 0, 1066, 276, 27605 },
6045 { 0, 800, 231, 23784 },
6046};
6047
f531dcb2 6048static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6049{
6050 u64 total_count, diff, ret;
6051 u32 count1, count2, count3, m = 0, c = 0;
6052 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6053 int i;
6054
02d71956
DV		 6055 assert_spin_locked(&mchdev_lock);
6056
20e4d407 6057 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6058
6059 /* Prevent division-by-zero if we are asking too fast.
6060 * Also, we don't get interesting results if we are polling
6061 * faster than once in 10ms, so just return the saved value
6062 * in such cases.
6063 */
6064 if (diff1 <= 10)
20e4d407 6065 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6066
6067 count1 = I915_READ(DMIEC);
6068 count2 = I915_READ(DDREC);
6069 count3 = I915_READ(CSIEC);
6070
6071 total_count = count1 + count2 + count3;
6072
6073 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6074 if (total_count < dev_priv->ips.last_count1) {
6075 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6076 diff += total_count;
6077 } else {
20e4d407 6078 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6079 }
6080
6081 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6082 if (cparams[i].i == dev_priv->ips.c_m &&
6083 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6084 m = cparams[i].m;
6085 c = cparams[i].c;
6086 break;
6087 }
6088 }
6089
6090 diff = div_u64(diff, diff1);
6091 ret = ((m * diff) + c);
6092 ret = div_u64(ret, 10);
6093
20e4d407
DV		 6094 dev_priv->ips.last_count1 = total_count;
6095 dev_priv->ips.last_time1 = now;
eb48eb00 6096
20e4d407 6097 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6098
6099 return ret;
6100}
6101
f531dcb2
CW		 6102unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6103{
6104 unsigned long val;
6105
dc97997a 6106 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6107 return 0;
6108
6109 spin_lock_irq(&mchdev_lock);
6110
6111 val = __i915_chipset_val(dev_priv);
6112
6113 spin_unlock_irq(&mchdev_lock);
6114
6115 return val;
6116}
6117
eb48eb00
DV		 6118unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6119{
6120 unsigned long m, x, b;
6121 u32 tsfs;
6122
6123 tsfs = I915_READ(TSFS);
6124
6125 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6126 x = I915_READ8(TR1);
6127
6128 b = tsfs & TSFS_INTR_MASK;
6129
6130 return ((m * x) / 127) - b;
6131}
6132
d972d6ee
MK		 6133static int _pxvid_to_vd(u8 pxvid)
6134{
6135 if (pxvid == 0)
6136 return 0;
6137
6138 if (pxvid >= 8 && pxvid < 31)
6139 pxvid = 31;
6140
6141 return (pxvid + 2) * 125;
6142}
6143
6144static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6145{
d972d6ee
MK		 6146 const int vd = _pxvid_to_vd(pxvid);
6147 const int vm = vd - 1125;
6148
dc97997a 6149 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6150 return vm > 0 ? vm : 0;
6151
6152 return vd;
eb48eb00
DV		 6153}
6154
02d71956 6155static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6156{
5ed0bdf2 6157 u64 now, diff, diffms;
eb48eb00
DV		 6158 u32 count;
6159
02d71956 6160 assert_spin_locked(&mchdev_lock);
eb48eb00 6161
5ed0bdf2
TG		 6162 now = ktime_get_raw_ns();
6163 diffms = now - dev_priv->ips.last_time2;
6164 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6165
6166 /* Don't divide by 0 */
eb48eb00
DV		 6167 if (!diffms)
6168 return;
6169
6170 count = I915_READ(GFXEC);
6171
20e4d407
DV		 6172 if (count < dev_priv->ips.last_count2) {
6173 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6174 diff += count;
6175 } else {
20e4d407 6176 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6177 }
6178
20e4d407
DV		 6179 dev_priv->ips.last_count2 = count;
6180 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6181
6182 /* More magic constants... */
6183 diff = diff * 1181;
6184 diff = div_u64(diff, diffms * 10);
20e4d407 6185 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6186}
6187
02d71956
DV		 6188void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6189{
dc97997a 6190 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6191 return;
6192
9270388e 6193 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6194
6195 __i915_update_gfx_val(dev_priv);
6196
9270388e 6197 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6198}
6199
f531dcb2 6200static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6201{
6202 unsigned long t, corr, state1, corr2, state2;
6203 u32 pxvid, ext_v;
6204
02d71956
DV		 6205 assert_spin_locked(&mchdev_lock);
6206
616847e7 6207 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6208 pxvid = (pxvid >> 24) & 0x7f;
6209 ext_v = pvid_to_extvid(dev_priv, pxvid);
6210
6211 state1 = ext_v;
6212
6213 t = i915_mch_val(dev_priv);
6214
6215 /* Revel in the empirically derived constants */
6216
6217 /* Correction factor in 1/100000 units */
6218 if (t > 80)
6219 corr = ((t * 2349) + 135940);
6220 else if (t >= 50)
6221 corr = ((t * 964) + 29317);
6222 else /* < 50 */
6223 corr = ((t * 301) + 1004);
6224
6225 corr = corr * ((150142 * state1) / 10000 - 78642);
6226 corr /= 100000;
20e4d407 6227 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6228
6229 state2 = (corr2 * state1) / 10000;
6230 state2 /= 100; /* convert to mW */
6231
02d71956 6232 __i915_update_gfx_val(dev_priv);
eb48eb00 6233
20e4d407 6234 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6235}
6236
f531dcb2
CW		 6237unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6238{
6239 unsigned long val;
6240
dc97997a 6241 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6242 return 0;
6243
6244 spin_lock_irq(&mchdev_lock);
6245
6246 val = __i915_gfx_val(dev_priv);
6247
6248 spin_unlock_irq(&mchdev_lock);
6249
6250 return val;
6251}
6252
eb48eb00
DV		 6253/**
6254 * i915_read_mch_val - return value for IPS use
6255 *
6256 * Calculate and return a value for the IPS driver to use when deciding whether
6257 * we have thermal and power headroom to increase CPU or GPU power budget.
6258 */
6259unsigned long i915_read_mch_val(void)
6260{
6261 struct drm_i915_private *dev_priv;
6262 unsigned long chipset_val, graphics_val, ret = 0;
6263
9270388e 6264 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6265 if (!i915_mch_dev)
6266 goto out_unlock;
6267 dev_priv = i915_mch_dev;
6268
f531dcb2
CW		 6269 chipset_val = __i915_chipset_val(dev_priv);
6270 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6271
6272 ret = chipset_val + graphics_val;
6273
6274out_unlock:
9270388e 6275 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6276
6277 return ret;
6278}
6279EXPORT_SYMBOL_GPL(i915_read_mch_val);
6280
6281/**
6282 * i915_gpu_raise - raise GPU frequency limit
6283 *
6284 * Raise the limit; IPS indicates we have thermal headroom.
6285 */
6286bool i915_gpu_raise(void)
6287{
6288 struct drm_i915_private *dev_priv;
6289 bool ret = true;
6290
9270388e 6291 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6292 if (!i915_mch_dev) {
6293 ret = false;
6294 goto out_unlock;
6295 }
6296 dev_priv = i915_mch_dev;
6297
20e4d407
DV		 6298 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6299 dev_priv->ips.max_delay--;
eb48eb00
DV		 6300
6301out_unlock:
9270388e 6302 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6303
6304 return ret;
6305}
6306EXPORT_SYMBOL_GPL(i915_gpu_raise);
6307
6308/**
6309 * i915_gpu_lower - lower GPU frequency limit
6310 *
6311 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6312 * frequency maximum.
6313 */
6314bool i915_gpu_lower(void)
6315{
6316 struct drm_i915_private *dev_priv;
6317 bool ret = true;
6318
9270388e 6319 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6320 if (!i915_mch_dev) {
6321 ret = false;
6322 goto out_unlock;
6323 }
6324 dev_priv = i915_mch_dev;
6325
20e4d407
DV		 6326 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6327 dev_priv->ips.max_delay++;
eb48eb00
DV		 6328
6329out_unlock:
9270388e 6330 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6331
6332 return ret;
6333}
6334EXPORT_SYMBOL_GPL(i915_gpu_lower);
6335
6336/**
6337 * i915_gpu_busy - indicate GPU business to IPS
6338 *
6339 * Tell the IPS driver whether or not the GPU is busy.
6340 */
6341bool i915_gpu_busy(void)
6342{
6343 struct drm_i915_private *dev_priv;
e2f80391 6344 struct intel_engine_cs *engine;
eb48eb00
DV		 6345 bool ret = false;
6346
9270388e 6347 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6348 if (!i915_mch_dev)
6349 goto out_unlock;
6350 dev_priv = i915_mch_dev;
6351
b4ac5afc 6352 for_each_engine(engine, dev_priv)
e2f80391 6353 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6354
6355out_unlock:
9270388e 6356 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6357
6358 return ret;
6359}
6360EXPORT_SYMBOL_GPL(i915_gpu_busy);
6361
6362/**
6363 * i915_gpu_turbo_disable - disable graphics turbo
6364 *
6365 * Disable graphics turbo by resetting the max frequency and setting the
6366 * current frequency to the default.
6367 */
6368bool i915_gpu_turbo_disable(void)
6369{
6370 struct drm_i915_private *dev_priv;
6371 bool ret = true;
6372
9270388e 6373 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6374 if (!i915_mch_dev) {
6375 ret = false;
6376 goto out_unlock;
6377 }
6378 dev_priv = i915_mch_dev;
6379
20e4d407 6380 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6381
91d14251 6382 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6383 ret = false;
6384
6385out_unlock:
9270388e 6386 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6387
6388 return ret;
6389}
6390EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6391
6392/**
6393 * Tells the intel_ips driver that the i915 driver is now loaded, if
6394 * IPS got loaded first.
6395 *
6396 * This awkward dance is so that neither module has to depend on the
6397 * other in order for IPS to do the appropriate communication of
6398 * GPU turbo limits to i915.
6399 */
6400static void
6401ips_ping_for_i915_load(void)
6402{
6403 void (*link)(void);
6404
6405 link = symbol_get(ips_link_to_i915_driver);
6406 if (link) {
6407 link();
6408 symbol_put(ips_link_to_i915_driver);
6409 }
6410}
6411
6412void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6413{
02d71956
DV		 6414 /* We only register the i915 ips part with intel-ips once everything is
6415 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6416 spin_lock_irq(&mchdev_lock);
eb48eb00 6417 i915_mch_dev = dev_priv;
9270388e 6418 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6419
6420 ips_ping_for_i915_load();
6421}
6422
6423void intel_gpu_ips_teardown(void)
6424{
9270388e 6425 spin_lock_irq(&mchdev_lock);
eb48eb00 6426 i915_mch_dev = NULL;
9270388e 6427 spin_unlock_irq(&mchdev_lock);
eb48eb00 6428}
76c3552f 6429
dc97997a 6430static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6431{
dde18883
ED		 6432 u32 lcfuse;
6433 u8 pxw[16];
6434 int i;
6435
6436 /* Disable to program */
6437 I915_WRITE(ECR, 0);
6438 POSTING_READ(ECR);
6439
6440 /* Program energy weights for various events */
6441 I915_WRITE(SDEW, 0x15040d00);
6442 I915_WRITE(CSIEW0, 0x007f0000);
6443 I915_WRITE(CSIEW1, 0x1e220004);
6444 I915_WRITE(CSIEW2, 0x04000004);
6445
6446 for (i = 0; i < 5; i++)
616847e7 6447 I915_WRITE(PEW(i), 0);
dde18883 6448 for (i = 0; i < 3; i++)
616847e7 6449 I915_WRITE(DEW(i), 0);
dde18883
ED		 6450
6451 /* Program P-state weights to account for frequency power adjustment */
6452 for (i = 0; i < 16; i++) {
616847e7 6453 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6454 unsigned long freq = intel_pxfreq(pxvidfreq);
6455 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6456 PXVFREQ_PX_SHIFT;
6457 unsigned long val;
6458
6459 val = vid * vid;
6460 val *= (freq / 1000);
6461 val *= 255;
6462 val /= (127*127*900);
6463 if (val > 0xff)
6464 DRM_ERROR("bad pxval: %ld\n", val);
6465 pxw[i] = val;
6466 }
6467 /* Render standby states get 0 weight */
6468 pxw[14] = 0;
6469 pxw[15] = 0;
6470
6471 for (i = 0; i < 4; i++) {
6472 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6473 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6474 I915_WRITE(PXW(i), val);
dde18883
ED		 6475 }
6476
6477 /* Adjust magic regs to magic values (more experimental results) */
6478 I915_WRITE(OGW0, 0);
6479 I915_WRITE(OGW1, 0);
6480 I915_WRITE(EG0, 0x00007f00);
6481 I915_WRITE(EG1, 0x0000000e);
6482 I915_WRITE(EG2, 0x000e0000);
6483 I915_WRITE(EG3, 0x68000300);
6484 I915_WRITE(EG4, 0x42000000);
6485 I915_WRITE(EG5, 0x00140031);
6486 I915_WRITE(EG6, 0);
6487 I915_WRITE(EG7, 0);
6488
6489 for (i = 0; i < 8; i++)
616847e7 6490 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6491
6492 /* Enable PMON + select events */
6493 I915_WRITE(ECR, 0x80000019);
6494
6495 lcfuse = I915_READ(LCFUSE02);
6496
20e4d407 6497 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6498}
6499
dc97997a 6500void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6501{
b268c699
ID		 6502 /*
6503 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6504 * requirement.
6505 */
6506 if (!i915.enable_rc6) {
6507 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6508 intel_runtime_pm_get(dev_priv);
6509 }
e6069ca8 6510
dc97997a
CW		 6511 if (IS_CHERRYVIEW(dev_priv))
6512 cherryview_init_gt_powersave(dev_priv);
6513 else if (IS_VALLEYVIEW(dev_priv))
6514 valleyview_init_gt_powersave(dev_priv);
ae48434c
ID		 6515}
6516
dc97997a 6517void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6518{
dc97997a 6519 if (IS_CHERRYVIEW(dev_priv))
38807746 6520 return;
dc97997a
CW		 6521 else if (IS_VALLEYVIEW(dev_priv))
6522 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6523
6524 if (!i915.enable_rc6)
6525 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6526}
6527
91d14251 6528static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
dbea3cea 6529{
dbea3cea
ID		 6530 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6531
91d14251 6532 gen6_disable_rps_interrupts(dev_priv);
dbea3cea
ID		 6533}
6534
156c7ca0
JB		 6535/**
6536 * intel_suspend_gt_powersave - suspend PM work and helper threads
dc97997a 6537 * @dev_priv: i915 device
156c7ca0
JB		 6538 *
6539 * We don't want to disable RC6 or other features here, we just want
6540 * to make sure any work we've queued has finished and won't bother
6541 * us while we're suspended.
6542 */
dc97997a 6543void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
156c7ca0 6544{
91d14251 6545 if (INTEL_GEN(dev_priv) < 6)
d4d70aa5
ID		 6546 return;
6547
91d14251 6548 gen6_suspend_rps(dev_priv);
b47adc17
D		 6549
6550 /* Force GPU to min freq during suspend */
6551 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6552}
6553
dc97997a 6554void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6555{
dc97997a 6556 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6557 ironlake_disable_drps(dev_priv);
dc97997a
CW		 6558 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6559 intel_suspend_gt_powersave(dev_priv);
e494837a 6560
4fc688ce 6561 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6562 if (INTEL_INFO(dev_priv)->gen >= 9) {
6563 gen9_disable_rc6(dev_priv);
6564 gen9_disable_rps(dev_priv);
6565 } else if (IS_CHERRYVIEW(dev_priv))
6566 cherryview_disable_rps(dev_priv);
6567 else if (IS_VALLEYVIEW(dev_priv))
6568 valleyview_disable_rps(dev_priv);
d20d4f0c 6569 else
dc97997a 6570 gen6_disable_rps(dev_priv);
e534770a 6571
c0951f0c 6572 dev_priv->rps.enabled = false;
4fc688ce 6573 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6574 }
8090c6b9
DV		 6575}
6576
1a01ab3b
JB		 6577static void intel_gen6_powersave_work(struct work_struct *work)
6578{
6579 struct drm_i915_private *dev_priv =
6580 container_of(work, struct drm_i915_private,
6581 rps.delayed_resume_work.work);
1a01ab3b 6582
4fc688ce 6583 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6584
dc97997a
CW		 6585 gen6_reset_rps_interrupts(dev_priv);
6586
6587 if (IS_CHERRYVIEW(dev_priv)) {
6588 cherryview_enable_rps(dev_priv);
6589 } else if (IS_VALLEYVIEW(dev_priv)) {
6590 valleyview_enable_rps(dev_priv);
6591 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6592 gen9_enable_rc6(dev_priv);
6593 gen9_enable_rps(dev_priv);
6594 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6595 __gen6_update_ring_freq(dev_priv);
6596 } else if (IS_BROADWELL(dev_priv)) {
6597 gen8_enable_rps(dev_priv);
6598 __gen6_update_ring_freq(dev_priv);
0a073b84 6599 } else {
dc97997a
CW		 6600 gen6_enable_rps(dev_priv);
6601 __gen6_update_ring_freq(dev_priv);
0a073b84 6602 }
aed242ff
CW		 6603
6604 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6605 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6606
6607 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6608 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6609
c0951f0c 6610 dev_priv->rps.enabled = true;
3cc134e3 6611
91d14251 6612 gen6_enable_rps_interrupts(dev_priv);
3cc134e3 6613
4fc688ce 6614 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6615
6616 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6617}
6618
dc97997a 6619void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6620{
f61018b1 6621 /* Powersaving is controlled by the host when inside a VM */
c033666a 6622 if (intel_vgpu_active(dev_priv))
f61018b1
YZ		 6623 return;
6624
dc97997a 6625 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6626 ironlake_enable_drps(dev_priv);
dc97997a
CW		 6627 mutex_lock(&dev_priv->dev->struct_mutex);
6628 intel_init_emon(dev_priv);
6629 mutex_unlock(&dev_priv->dev->struct_mutex);
6630 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
1a01ab3b
JB		 6631 /*
6632 * PCU communication is slow and this doesn't need to be
6633 * done at any specific time, so do this out of our fast path
6634 * to make resume and init faster.
c6df39b5
ID		 6635 *
6636 * We depend on the HW RC6 power context save/restore
6637 * mechanism when entering D3 through runtime PM suspend. So
6638 * disable RPM until RPS/RC6 is properly setup. We can only
6639 * get here via the driver load/system resume/runtime resume
6640 * paths, so the _noresume version is enough (and in case of
6641 * runtime resume it's necessary).
1a01ab3b 6642 */
c6df39b5
ID		 6643 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6644 round_jiffies_up_relative(HZ)))
6645 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6646 }
6647}
6648
dc97997a 6649void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
c6df39b5 6650{
dc97997a 6651 if (INTEL_INFO(dev_priv)->gen < 6)
dbea3cea
ID		 6652 return;
6653
91d14251 6654 gen6_suspend_rps(dev_priv);
c6df39b5 6655 dev_priv->rps.enabled = false;
c6df39b5
ID		 6656}
6657
3107bd48
DV		 6658static void ibx_init_clock_gating(struct drm_device *dev)
6659{
6660 struct drm_i915_private *dev_priv = dev->dev_private;
6661
6662 /*
6663 * On Ibex Peak and Cougar Point, we need to disable clock
6664 * gating for the panel power sequencer or it will fail to
6665 * start up when no ports are active.
6666 */
6667 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6668}
6669
0e088b8f
VS		 6670static void g4x_disable_trickle_feed(struct drm_device *dev)
6671{
6672 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6673 enum pipe pipe;
0e088b8f 6674
055e393f 6675 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6676 I915_WRITE(DSPCNTR(pipe),
6677 I915_READ(DSPCNTR(pipe)) |
6678 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6679
6680 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6681 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6682 }
6683}
6684
017636cc
VS		 6685static void ilk_init_lp_watermarks(struct drm_device *dev)
6686{
6687 struct drm_i915_private *dev_priv = dev->dev_private;
6688
6689 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6690 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6691 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6692
6693 /*
6694 * Don't touch WM1S_LP_EN here.
6695 * Doing so could cause underruns.
6696 */
6697}
6698
1fa61106 6699static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6700{
6701 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6702 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6703
f1e8fa56
DL		 6704 /*
6705 * Required for FBC
6706 * WaFbcDisableDpfcClockGating:ilk
6707 */
4d47e4f5
DL		 6708 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6709 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6710 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6711
6712 I915_WRITE(PCH_3DCGDIS0,
6713 MARIUNIT_CLOCK_GATE_DISABLE |
6714 SVSMUNIT_CLOCK_GATE_DISABLE);
6715 I915_WRITE(PCH_3DCGDIS1,
6716 VFMUNIT_CLOCK_GATE_DISABLE);
6717
6f1d69b0
ED		 6718 /*
6719 * According to the spec the following bits should be set in
6720 * order to enable memory self-refresh
6721 * The bit 22/21 of 0x42004
6722 * The bit 5 of 0x42020
6723 * The bit 15 of 0x45000
6724 */
6725 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6726 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6727 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6728 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6729 I915_WRITE(DISP_ARB_CTL,
6730 (I915_READ(DISP_ARB_CTL) |
6731 DISP_FBC_WM_DIS));
017636cc
VS		 6732
6733 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6734
6735 /*
6736 * Based on the document from hardware guys the following bits
6737 * should be set unconditionally in order to enable FBC.
6738 * The bit 22 of 0x42000
6739 * The bit 22 of 0x42004
6740 * The bit 7,8,9 of 0x42020.
6741 */
6742 if (IS_IRONLAKE_M(dev)) {
4bb35334 6743 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6744 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6745 I915_READ(ILK_DISPLAY_CHICKEN1) |
6746 ILK_FBCQ_DIS);
6747 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6748 I915_READ(ILK_DISPLAY_CHICKEN2) |
6749 ILK_DPARB_GATE);
6f1d69b0
ED		 6750 }
6751
4d47e4f5
DL		 6752 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6753
6f1d69b0
ED		 6754 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6755 I915_READ(ILK_DISPLAY_CHICKEN2) |
6756 ILK_ELPIN_409_SELECT);
6757 I915_WRITE(_3D_CHICKEN2,
6758 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6759 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6760
ecdb4eb7 6761 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6762 I915_WRITE(CACHE_MODE_0,
6763 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6764
4e04632e
AG		 6765 /* WaDisable_RenderCache_OperationalFlush:ilk */
6766 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6767
0e088b8f 6768 g4x_disable_trickle_feed(dev);
bdad2b2f 6769
3107bd48
DV		 6770 ibx_init_clock_gating(dev);
6771}
6772
6773static void cpt_init_clock_gating(struct drm_device *dev)
6774{
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 int pipe;
3f704fa2 6777 uint32_t val;
3107bd48
DV		 6778
6779 /*
6780 * On Ibex Peak and Cougar Point, we need to disable clock
6781 * gating for the panel power sequencer or it will fail to
6782 * start up when no ports are active.
6783 */
cd664078
JB		 6784 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6785 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6786 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6787 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6788 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6789 /* The below fixes the weird display corruption, a few pixels shifted
6790 * downward, on (only) LVDS of some HP laptops with IVY.
6791 */
055e393f 6792 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6793 val = I915_READ(TRANS_CHICKEN2(pipe));
6794 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6795 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6796 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6797 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6798 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6799 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6800 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6801 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6802 }
3107bd48 6803 /* WADP0ClockGatingDisable */
055e393f 6804 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6805 I915_WRITE(TRANS_CHICKEN1(pipe),
6806 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6807 }
6f1d69b0
ED		 6808}
6809
1d7aaa0c
DV		 6810static void gen6_check_mch_setup(struct drm_device *dev)
6811{
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813 uint32_t tmp;
6814
6815 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6816 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6817 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6818 tmp);
1d7aaa0c
DV		 6819}
6820
1fa61106 6821static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6822{
6823 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6824 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6825
231e54f6 6826 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6827
6828 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6829 I915_READ(ILK_DISPLAY_CHICKEN2) |
6830 ILK_ELPIN_409_SELECT);
6831
ecdb4eb7 6832 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6833 I915_WRITE(_3D_CHICKEN,
6834 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6835
4e04632e
AG		 6836 /* WaDisable_RenderCache_OperationalFlush:snb */
6837 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6838
8d85d272
VS		 6839 /*
6840 * BSpec recoomends 8x4 when MSAA is used,
6841 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6842 *
6843 * Note that PS/WM thread counts depend on the WIZ hashing
6844 * disable bit, which we don't touch here, but it's good
6845 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6846 */
6847 I915_WRITE(GEN6_GT_MODE,
98533251 6848 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6849
017636cc 6850 ilk_init_lp_watermarks(dev);
6f1d69b0 6851
6f1d69b0 6852 I915_WRITE(CACHE_MODE_0,
50743298 6853 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6854
6855 I915_WRITE(GEN6_UCGCTL1,
6856 I915_READ(GEN6_UCGCTL1) |
6857 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6858 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6859
6860 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6861 * gating disable must be set. Failure to set it results in
6862 * flickering pixels due to Z write ordering failures after
6863 * some amount of runtime in the Mesa "fire" demo, and Unigine
6864 * Sanctuary and Tropics, and apparently anything else with
6865 * alpha test or pixel discard.
6866 *
6867 * According to the spec, bit 11 (RCCUNIT) must also be set,
6868 * but we didn't debug actual testcases to find it out.
0f846f81 6869 *
ef59318c
VS		 6870 * WaDisableRCCUnitClockGating:snb
6871 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6872 */
6873 I915_WRITE(GEN6_UCGCTL2,
6874 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6875 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6876
5eb146dd 6877 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6878 I915_WRITE(_3D_CHICKEN3,
6879 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6880
e927ecde
VS		 6881 /*
6882 * Bspec says:
6883 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6884 * 3DSTATE_SF number of SF output attributes is more than 16."
6885 */
6886 I915_WRITE(_3D_CHICKEN3,
6887 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6888
6f1d69b0
ED		 6889 /*
6890 * According to the spec the following bits should be
6891 * set in order to enable memory self-refresh and fbc:
6892 * The bit21 and bit22 of 0x42000
6893 * The bit21 and bit22 of 0x42004
6894 * The bit5 and bit7 of 0x42020
6895 * The bit14 of 0x70180
6896 * The bit14 of 0x71180
4bb35334
DL		 6897 *
6898 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6899 */
6900 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6901 I915_READ(ILK_DISPLAY_CHICKEN1) |
6902 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6903 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6904 I915_READ(ILK_DISPLAY_CHICKEN2) |
6905 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6906 I915_WRITE(ILK_DSPCLK_GATE_D,
6907 I915_READ(ILK_DSPCLK_GATE_D) |
6908 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6909 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6910
0e088b8f 6911 g4x_disable_trickle_feed(dev);
f8f2ac9a 6912
3107bd48 6913 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6914
6915 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6916}
6917
6918static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6919{
6920 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6921
3aad9059 6922 /*
46680e0a 6923 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6924 *
6925 * This actually overrides the dispatch
6926 * mode for all thread types.
6927 */
6f1d69b0
ED		 6928 reg &= ~GEN7_FF_SCHED_MASK;
6929 reg |= GEN7_FF_TS_SCHED_HW;
6930 reg |= GEN7_FF_VS_SCHED_HW;
6931 reg |= GEN7_FF_DS_SCHED_HW;
6932
6933 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6934}
6935
17a303ec
PZ		 6936static void lpt_init_clock_gating(struct drm_device *dev)
6937{
6938 struct drm_i915_private *dev_priv = dev->dev_private;
6939
6940 /*
6941 * TODO: this bit should only be enabled when really needed, then
6942 * disabled when not needed anymore in order to save power.
6943 */
c2699524 6944 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6945 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6946 I915_READ(SOUTH_DSPCLK_GATE_D) |
6947 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6948
6949 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6950 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6951 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6952 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6953}
6954
7d708ee4
ID		 6955static void lpt_suspend_hw(struct drm_device *dev)
6956{
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958
c2699524 6959 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6960 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6961
6962 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6963 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6964 }
6965}
6966
450174fe
ID		 6967static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6968 int general_prio_credits,
6969 int high_prio_credits)
6970{
6971 u32 misccpctl;
6972
6973 /* WaTempDisableDOPClkGating:bdw */
6974 misccpctl = I915_READ(GEN7_MISCCPCTL);
6975 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6976
6977 I915_WRITE(GEN8_L3SQCREG1,
6978 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6979 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6980
6981 /*
6982 * Wait at least 100 clocks before re-enabling clock gating.
6983 * See the definition of L3SQCREG1 in BSpec.
6984 */
6985 POSTING_READ(GEN8_L3SQCREG1);
6986 udelay(1);
6987 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6988}
6989
9498dba7
MK		 6990static void kabylake_init_clock_gating(struct drm_device *dev)
6991{
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993
b033bb6d 6994 gen9_init_clock_gating(dev);
9498dba7
MK		 6995
6996 /* WaDisableSDEUnitClockGating:kbl */
6997 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6998 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6999 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7000
7001 /* WaDisableGamClockGating:kbl */
7002 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7003 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7004 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7005
7006 /* WaFbcNukeOnHostModify:kbl */
7007 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7008 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7009}
7010
dc00b6a0
DV		 7011static void skylake_init_clock_gating(struct drm_device *dev)
7012{
44fff99f
MK		 7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014
b033bb6d 7015 gen9_init_clock_gating(dev);
44fff99f
MK		 7016
7017 /* WAC6entrylatency:skl */
7018 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7019 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7020
7021 /* WaFbcNukeOnHostModify:skl */
7022 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7023 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7024}
7025
47c2bd97 7026static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 7027{
7028 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 7029 enum pipe pipe;
1020a5c2 7030
7ad0dbab 7031 ilk_init_lp_watermarks(dev);
50ed5fbd 7032
ab57fff1 7033 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7034 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7035
ab57fff1 7036 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7037 I915_WRITE(CHICKEN_PAR1_1,
7038 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7039
ab57fff1 7040 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7041 for_each_pipe(dev_priv, pipe) {
07d27e20 7042 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7043 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7044 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7045 }
63801f21 7046
ab57fff1
BW		 7047 /* WaVSRefCountFullforceMissDisable:bdw */
7048 /* WaDSRefCountFullforceMissDisable:bdw */
7049 I915_WRITE(GEN7_FF_THREAD_MODE,
7050 I915_READ(GEN7_FF_THREAD_MODE) &
7051 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7052
295e8bb7
VS		 7053 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7054 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7055
7056 /* WaDisableSDEUnitClockGating:bdw */
7057 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7058 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7059
450174fe
ID		 7060 /* WaProgramL3SqcReg1Default:bdw */
7061 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7062
6d50b065
VS		 7063 /*
7064 * WaGttCachingOffByDefault:bdw
7065 * GTT cache may not work with big pages, so if those
7066 * are ever enabled GTT cache may need to be disabled.
7067 */
7068 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7069
17e0adf0
MK		 7070 /* WaKVMNotificationOnConfigChange:bdw */
7071 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7072 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7073
89d6b2b8 7074 lpt_init_clock_gating(dev);
1020a5c2
BW		 7075}
7076
cad2a2d7
ED		 7077static void haswell_init_clock_gating(struct drm_device *dev)
7078{
7079 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 7080
017636cc 7081 ilk_init_lp_watermarks(dev);
cad2a2d7 7082
f3fc4884
FJ		 7083 /* L3 caching of data atomics doesn't work -- disable it. */
7084 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7085 I915_WRITE(HSW_ROW_CHICKEN3,
7086 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7087
ecdb4eb7 7088 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7089 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7090 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7091 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7092
e36ea7ff
VS		 7093 /* WaVSRefCountFullforceMissDisable:hsw */
7094 I915_WRITE(GEN7_FF_THREAD_MODE,
7095 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7096
4e04632e
AG		 7097 /* WaDisable_RenderCache_OperationalFlush:hsw */
7098 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7099
fe27c606
CW		 7100 /* enable HiZ Raw Stall Optimization */
7101 I915_WRITE(CACHE_MODE_0_GEN7,
7102 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7103
ecdb4eb7 7104 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7105 I915_WRITE(CACHE_MODE_1,
7106 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7107
a12c4967
VS		 7108 /*
7109 * BSpec recommends 8x4 when MSAA is used,
7110 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7111 *
7112 * Note that PS/WM thread counts depend on the WIZ hashing
7113 * disable bit, which we don't touch here, but it's good
7114 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7115 */
7116 I915_WRITE(GEN7_GT_MODE,
98533251 7117 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7118
94411593
KG		 7119 /* WaSampleCChickenBitEnable:hsw */
7120 I915_WRITE(HALF_SLICE_CHICKEN3,
7121 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7122
ecdb4eb7 7123 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7124 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7125
90a88643
PZ		 7126 /* WaRsPkgCStateDisplayPMReq:hsw */
7127 I915_WRITE(CHICKEN_PAR1_1,
7128 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7129
17a303ec 7130 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7131}
7132
1fa61106 7133static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7134{
7135 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 7136 uint32_t snpcr;
6f1d69b0 7137
017636cc 7138 ilk_init_lp_watermarks(dev);
6f1d69b0 7139
231e54f6 7140 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7141
ecdb4eb7 7142 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7143 I915_WRITE(_3D_CHICKEN3,
7144 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7145
ecdb4eb7 7146 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7147 I915_WRITE(IVB_CHICKEN3,
7148 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7149 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7150
ecdb4eb7 7151 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7152 if (IS_IVB_GT1(dev))
7153 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7154 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7155
4e04632e
AG		 7156 /* WaDisable_RenderCache_OperationalFlush:ivb */
7157 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7158
ecdb4eb7 7159 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7160 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7161 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7162
ecdb4eb7 7163 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7164 I915_WRITE(GEN7_L3CNTLREG1,
7165 GEN7_WA_FOR_GEN7_L3_CONTROL);
7166 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7167 GEN7_WA_L3_CHICKEN_MODE);
7168 if (IS_IVB_GT1(dev))
7169 I915_WRITE(GEN7_ROW_CHICKEN2,
7170 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7171 else {
7172 /* must write both registers */
7173 I915_WRITE(GEN7_ROW_CHICKEN2,
7174 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7175 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7176 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7177 }
6f1d69b0 7178
ecdb4eb7 7179 /* WaForceL3Serialization:ivb */
61939d97
JB		 7180 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7181 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7182
1b80a19a 7183 /*
0f846f81 7184 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7185 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7186 */
7187 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7188 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7189
ecdb4eb7 7190 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7191 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7192 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7193 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7194
0e088b8f 7195 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7196
7197 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7198
22721343
CW		 7199 if (0) { /* causes HiZ corruption on ivb:gt1 */
7200 /* enable HiZ Raw Stall Optimization */
7201 I915_WRITE(CACHE_MODE_0_GEN7,
7202 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7203 }
116f2b6d 7204
ecdb4eb7 7205 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7206 I915_WRITE(CACHE_MODE_1,
7207 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7208
a607c1a4
VS		 7209 /*
7210 * BSpec recommends 8x4 when MSAA is used,
7211 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7212 *
7213 * Note that PS/WM thread counts depend on the WIZ hashing
7214 * disable bit, which we don't touch here, but it's good
7215 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7216 */
7217 I915_WRITE(GEN7_GT_MODE,
98533251 7218 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7219
20848223
BW		 7220 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7221 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7222 snpcr |= GEN6_MBC_SNPCR_MED;
7223 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7224
ab5c608b
BW		 7225 if (!HAS_PCH_NOP(dev))
7226 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7227
7228 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7229}
7230
1fa61106 7231static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7232{
7233 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 7234
ecdb4eb7 7235 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7236 I915_WRITE(_3D_CHICKEN3,
7237 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7238
ecdb4eb7 7239 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7240 I915_WRITE(IVB_CHICKEN3,
7241 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7242 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7243
fad7d36e 7244 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7245 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7246 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7247 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7248 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7249
4e04632e
AG		 7250 /* WaDisable_RenderCache_OperationalFlush:vlv */
7251 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7252
ecdb4eb7 7253 /* WaForceL3Serialization:vlv */
61939d97
JB		 7254 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7255 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7256
ecdb4eb7 7257 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7258 I915_WRITE(GEN7_ROW_CHICKEN2,
7259 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7260
ecdb4eb7 7261 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7262 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7263 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7264 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7265
46680e0a
VS		 7266 gen7_setup_fixed_func_scheduler(dev_priv);
7267
3c0edaeb 7268 /*
0f846f81 7269 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7270 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7271 */
7272 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7273 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7274
c98f5062
AG		 7275 /* WaDisableL3Bank2xClockGate:vlv
7276 * Disabling L3 clock gating- MMIO 940c[25] = 1
7277 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7278 I915_WRITE(GEN7_UCGCTL4,
7279 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7280
afd58e79
VS		 7281 /*
7282 * BSpec says this must be set, even though
7283 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7284 */
6b26c86d
DV		 7285 I915_WRITE(CACHE_MODE_1,
7286 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7287
da2518f9
VS		 7288 /*
7289 * BSpec recommends 8x4 when MSAA is used,
7290 * however in practice 16x4 seems fastest.
7291 *
7292 * Note that PS/WM thread counts depend on the WIZ hashing
7293 * disable bit, which we don't touch here, but it's good
7294 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7295 */
7296 I915_WRITE(GEN7_GT_MODE,
7297 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7298
031994ee
VS		 7299 /*
7300 * WaIncreaseL3CreditsForVLVB0:vlv
7301 * This is the hardware default actually.
7302 */
7303 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7304
2d809570 7305 /*
ecdb4eb7 7306 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7307 * Disable clock gating on th GCFG unit to prevent a delay
7308 * in the reporting of vblank events.
7309 */
7a0d1eed 7310 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7311}
7312
a4565da8
VS		 7313static void cherryview_init_clock_gating(struct drm_device *dev)
7314{
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316
232ce337
VS		 7317 /* WaVSRefCountFullforceMissDisable:chv */
7318 /* WaDSRefCountFullforceMissDisable:chv */
7319 I915_WRITE(GEN7_FF_THREAD_MODE,
7320 I915_READ(GEN7_FF_THREAD_MODE) &
7321 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7322
7323 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7324 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7325 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7326
7327 /* WaDisableCSUnitClockGating:chv */
7328 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7329 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7330
7331 /* WaDisableSDEUnitClockGating:chv */
7332 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7333 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7334
450174fe
ID		 7335 /*
7336 * WaProgramL3SqcReg1Default:chv
7337 * See gfxspecs/Related Documents/Performance Guide/
7338 * LSQC Setting Recommendations.
7339 */
7340 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7341
6d50b065
VS		 7342 /*
7343 * GTT cache may not work with big pages, so if those
7344 * are ever enabled GTT cache may need to be disabled.
7345 */
7346 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7347}
7348
1fa61106 7349static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7350{
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 uint32_t dspclk_gate;
7353
7354 I915_WRITE(RENCLK_GATE_D1, 0);
7355 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7356 GS_UNIT_CLOCK_GATE_DISABLE |
7357 CL_UNIT_CLOCK_GATE_DISABLE);
7358 I915_WRITE(RAMCLK_GATE_D, 0);
7359 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7360 OVRUNIT_CLOCK_GATE_DISABLE |
7361 OVCUNIT_CLOCK_GATE_DISABLE;
7362 if (IS_GM45(dev))
7363 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7364 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7365
7366 /* WaDisableRenderCachePipelinedFlush */
7367 I915_WRITE(CACHE_MODE_0,
7368 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7369
4e04632e
AG		 7370 /* WaDisable_RenderCache_OperationalFlush:g4x */
7371 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7372
0e088b8f 7373 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7374}
7375
1fa61106 7376static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7377{
7378 struct drm_i915_private *dev_priv = dev->dev_private;
7379
7380 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7381 I915_WRITE(RENCLK_GATE_D2, 0);
7382 I915_WRITE(DSPCLK_GATE_D, 0);
7383 I915_WRITE(RAMCLK_GATE_D, 0);
7384 I915_WRITE16(DEUC, 0);
20f94967
VS		 7385 I915_WRITE(MI_ARB_STATE,
7386 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7387
7388 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7389 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7390}
7391
1fa61106 7392static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7393{
7394 struct drm_i915_private *dev_priv = dev->dev_private;
7395
7396 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7397 I965_RCC_CLOCK_GATE_DISABLE |
7398 I965_RCPB_CLOCK_GATE_DISABLE |
7399 I965_ISC_CLOCK_GATE_DISABLE |
7400 I965_FBC_CLOCK_GATE_DISABLE);
7401 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7402 I915_WRITE(MI_ARB_STATE,
7403 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7404
7405 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7406 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7407}
7408
1fa61106 7409static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7410{
7411 struct drm_i915_private *dev_priv = dev->dev_private;
7412 u32 dstate = I915_READ(D_STATE);
7413
7414 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7415 DSTATE_DOT_CLOCK_GATING;
7416 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7417
7418 if (IS_PINEVIEW(dev))
7419 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7420
7421 /* IIR "flip pending" means done if this bit is set */
7422 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7423
7424 /* interrupts should cause a wake up from C3 */
3299254f 7425 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7426
7427 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7428 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7429
7430 I915_WRITE(MI_ARB_STATE,
7431 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7432}
7433
1fa61106 7434static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7435{
7436 struct drm_i915_private *dev_priv = dev->dev_private;
7437
7438 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7439
7440 /* interrupts should cause a wake up from C3 */
7441 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7442 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7443
7444 I915_WRITE(MEM_MODE,
7445 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7446}
7447
1fa61106 7448static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7449{
7450 struct drm_i915_private *dev_priv = dev->dev_private;
7451
7452 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7453
7454 I915_WRITE(MEM_MODE,
7455 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7456 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7457}
7458
6f1d69b0
ED		 7459void intel_init_clock_gating(struct drm_device *dev)
7460{
7461 struct drm_i915_private *dev_priv = dev->dev_private;
7462
bb400da9 7463 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7464}
7465
7d708ee4
ID		 7466void intel_suspend_hw(struct drm_device *dev)
7467{
7468 if (HAS_PCH_LPT(dev))
7469 lpt_suspend_hw(dev);
7470}
7471
bb400da9
ID		 7472static void nop_init_clock_gating(struct drm_device *dev)
7473{
7474 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7475}
7476
7477/**
7478 * intel_init_clock_gating_hooks - setup the clock gating hooks
7479 * @dev_priv: device private
7480 *
7481 * Setup the hooks that configure which clocks of a given platform can be
7482 * gated and also apply various GT and display specific workarounds for these
7483 * platforms. Note that some GT specific workarounds are applied separately
7484 * when GPU contexts or batchbuffers start their execution.
7485 */
7486void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7487{
7488 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7489 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7490 else if (IS_KABYLAKE(dev_priv))
9498dba7 7491 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7492 else if (IS_BROXTON(dev_priv))
7493 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7494 else if (IS_BROADWELL(dev_priv))
7495 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7496 else if (IS_CHERRYVIEW(dev_priv))
7497 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7498 else if (IS_HASWELL(dev_priv))
7499 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7500 else if (IS_IVYBRIDGE(dev_priv))
7501 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7502 else if (IS_VALLEYVIEW(dev_priv))
7503 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7504 else if (IS_GEN6(dev_priv))
7505 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7506 else if (IS_GEN5(dev_priv))
7507 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7508 else if (IS_G4X(dev_priv))
7509 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7510 else if (IS_CRESTLINE(dev_priv))
7511 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7512 else if (IS_BROADWATER(dev_priv))
7513 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7514 else if (IS_GEN3(dev_priv))
7515 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7516 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7517 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7518 else if (IS_GEN2(dev_priv))
7519 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7520 else {
7521 MISSING_CASE(INTEL_DEVID(dev_priv));
7522 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7523 }
7524}
7525
1fa61106
ED		 7526/* Set up chip specific power management-related functions */
7527void intel_init_pm(struct drm_device *dev)
7528{
7529 struct drm_i915_private *dev_priv = dev->dev_private;
7530
7ff0ebcc 7531 intel_fbc_init(dev_priv);
1fa61106 7532
c921aba8
DV		 7533 /* For cxsr */
7534 if (IS_PINEVIEW(dev))
7535 i915_pineview_get_mem_freq(dev);
7536 else if (IS_GEN5(dev))
7537 i915_ironlake_get_mem_freq(dev);
7538
1fa61106 7539 /* For FIFO watermark updates */
f5ed50cb 7540 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7541 skl_setup_wm_latency(dev);
2d41c0b5 7542 dev_priv->display.update_wm = skl_update_wm;
98d39494 7543 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7544 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7545 ilk_setup_wm_latency(dev);
53615a5e 7546
bd602544
VS		 7547 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7548 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7549 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7550 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7551 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7552 dev_priv->display.compute_intermediate_wm =
7553 ilk_compute_intermediate_wm;
7554 dev_priv->display.initial_watermarks =
7555 ilk_initial_watermarks;
7556 dev_priv->display.optimize_watermarks =
7557 ilk_optimize_watermarks;
bd602544
VS		 7558 } else {
7559 DRM_DEBUG_KMS("Failed to read display plane latency. "
7560 "Disable CxSR\n");
7561 }
a4565da8 7562 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7563 vlv_setup_wm_latency(dev);
262cd2e1 7564 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7565 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7566 vlv_setup_wm_latency(dev);
26e1fe4f 7567 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7568 } else if (IS_PINEVIEW(dev)) {
7569 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7570 dev_priv->is_ddr3,
7571 dev_priv->fsb_freq,
7572 dev_priv->mem_freq)) {
7573 DRM_INFO("failed to find known CxSR latency "
7574 "(found ddr%s fsb freq %d, mem freq %d), "
7575 "disabling CxSR\n",
7576 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7577 dev_priv->fsb_freq, dev_priv->mem_freq);
7578 /* Disable CxSR and never update its watermark again */
5209b1f4 7579 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7580 dev_priv->display.update_wm = NULL;
7581 } else
7582 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7583 } else if (IS_G4X(dev)) {
7584 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7585 } else if (IS_GEN4(dev)) {
7586 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7587 } else if (IS_GEN3(dev)) {
7588 dev_priv->display.update_wm = i9xx_update_wm;
7589 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7590 } else if (IS_GEN2(dev)) {
7591 if (INTEL_INFO(dev)->num_pipes == 1) {
7592 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7593 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7594 } else {
7595 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7596 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7597 }
feb56b93
DV		 7598 } else {
7599 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7600 }
7601}
7602
151a49d0 7603int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7604{
4fc688ce 7605 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7606
7607 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7608 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7609 return -EAGAIN;
7610 }
7611
7612 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7613 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7614 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7615
7616 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7617 500)) {
7618 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7619 return -ETIMEDOUT;
7620 }
7621
7622 *val = I915_READ(GEN6_PCODE_DATA);
7623 I915_WRITE(GEN6_PCODE_DATA, 0);
7624
7625 return 0;
7626}
7627
151a49d0 7628int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7629{
4fc688ce 7630 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7631
7632 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7633 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7634 return -EAGAIN;
7635 }
7636
7637 I915_WRITE(GEN6_PCODE_DATA, val);
7638 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7639
7640 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7641 500)) {
7642 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7643 return -ETIMEDOUT;
7644 }
7645
7646 I915_WRITE(GEN6_PCODE_DATA, 0);
7647
7648 return 0;
7649}
a0e4e199 7650
dd06f88c
VS		 7651static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7652{
c30fec65
VS		 7653 /*
7654 * N = val - 0xb7
7655 * Slow = Fast = GPLL ref * N
7656 */
7657 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7658}
7659
b55dd647 7660static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7661{
c30fec65 7662 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7663}
7664
b55dd647 7665static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7666{
c30fec65
VS		 7667 /*
7668 * N = val / 2
7669 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7670 */
7671 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7672}
7673
b55dd647 7674static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7675{
1c14762d 7676 /* CHV needs even values */
c30fec65 7677 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7678}
7679
616bc820 7680int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7681{
2d1fe073 7682 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7683 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7684 GEN9_FREQ_SCALER);
2d1fe073 7685 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7686 return chv_gpu_freq(dev_priv, val);
2d1fe073 7687 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7688 return byt_gpu_freq(dev_priv, val);
7689 else
7690 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7691}
7692
616bc820
VS		 7693int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7694{
2d1fe073 7695 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7696 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7697 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7698 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7699 return chv_freq_opcode(dev_priv, val);
2d1fe073 7700 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7701 return byt_freq_opcode(dev_priv, val);
7702 else
500a3d2e 7703 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7704}
22b1b2f8 7705
6ad790c0
CW		 7706struct request_boost {
7707 struct work_struct work;
eed29a5b 7708 struct drm_i915_gem_request *req;
6ad790c0
CW		 7709};
7710
7711static void __intel_rps_boost_work(struct work_struct *work)
7712{
7713 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7714 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7715
e61b9958 7716 if (!i915_gem_request_completed(req, true))
c033666a 7717 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7718
73db04cf 7719 i915_gem_request_unreference(req);
6ad790c0
CW		 7720 kfree(boost);
7721}
7722
91d14251 7723void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7724{
7725 struct request_boost *boost;
7726
91d14251 7727 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7728 return;
7729
e61b9958
CW		 7730 if (i915_gem_request_completed(req, true))
7731 return;
7732
6ad790c0
CW		 7733 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7734 if (boost == NULL)
7735 return;
7736
eed29a5b
DV		 7737 i915_gem_request_reference(req);
7738 boost->req = req;
6ad790c0
CW		 7739
7740 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7741 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7742}
7743
f742a552 7744void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7745{
7746 struct drm_i915_private *dev_priv = dev->dev_private;
7747
f742a552 7748 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7749 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7750
907b28c5
CW		 7751 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7752 intel_gen6_powersave_work);
1854d5ca 7753 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7754 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7755 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7756
33688d95 7757 dev_priv->pm.suspended = false;
1f814dac 7758 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7759 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7760}
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