]>
Commit | Line | Data |
---|---|---|
85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
77719d28 DL |
55 | static void gen9_init_clock_gating(struct drm_device *dev) |
56 | { | |
57 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58 | ||
59 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ | |
60 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
61 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
62 | } | |
63 | ||
45db2194 | 64 | static void skl_init_clock_gating(struct drm_device *dev) |
da2078cd | 65 | { |
acd5c346 DL |
66 | struct drm_i915_private *dev_priv = dev->dev_private; |
67 | ||
77719d28 DL |
68 | gen9_init_clock_gating(dev); |
69 | ||
3dcd020a HN |
70 | if (INTEL_REVID(dev) == SKL_REVID_A0) { |
71 | /* | |
72 | * WaDisableSDEUnitClockGating:skl | |
9253c2e5 | 73 | * WaSetGAPSunitClckGateDisable:skl |
3dcd020a HN |
74 | */ |
75 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
9253c2e5 | 76 | GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | |
3dcd020a HN |
77 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
78 | } | |
8bc0ccf6 | 79 | |
2caa3b26 | 80 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
81e231af DL |
81 | /* WaDisableHDCInvalidation:skl */ |
82 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
83 | BDW_DISABLE_HDC_INVALIDATION); | |
84 | ||
2caa3b26 DL |
85 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
86 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
87 | I915_READ(FF_SLICE_CS_CHICKEN2) | | |
88 | GEN9_TSG_BARRIER_ACK_DISABLE); | |
89 | } | |
81e231af | 90 | |
8bc0ccf6 DL |
91 | if (INTEL_REVID(dev) <= SKL_REVID_E0) |
92 | /* WaDisableLSQCROPERFforOCL:skl */ | |
93 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
94 | GEN8_LQSC_RO_PERF_DIS); | |
da2078cd DL |
95 | } |
96 | ||
c921aba8 DV |
97 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
98 | { | |
50227e1c | 99 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
100 | u32 tmp; |
101 | ||
102 | tmp = I915_READ(CLKCFG); | |
103 | ||
104 | switch (tmp & CLKCFG_FSB_MASK) { | |
105 | case CLKCFG_FSB_533: | |
106 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
107 | break; | |
108 | case CLKCFG_FSB_800: | |
109 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
110 | break; | |
111 | case CLKCFG_FSB_667: | |
112 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
113 | break; | |
114 | case CLKCFG_FSB_400: | |
115 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
116 | break; | |
117 | } | |
118 | ||
119 | switch (tmp & CLKCFG_MEM_MASK) { | |
120 | case CLKCFG_MEM_533: | |
121 | dev_priv->mem_freq = 533; | |
122 | break; | |
123 | case CLKCFG_MEM_667: | |
124 | dev_priv->mem_freq = 667; | |
125 | break; | |
126 | case CLKCFG_MEM_800: | |
127 | dev_priv->mem_freq = 800; | |
128 | break; | |
129 | } | |
130 | ||
131 | /* detect pineview DDR3 setting */ | |
132 | tmp = I915_READ(CSHRDDR3CTL); | |
133 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
134 | } | |
135 | ||
136 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
137 | { | |
50227e1c | 138 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
139 | u16 ddrpll, csipll; |
140 | ||
141 | ddrpll = I915_READ16(DDRMPLL1); | |
142 | csipll = I915_READ16(CSIPLL0); | |
143 | ||
144 | switch (ddrpll & 0xff) { | |
145 | case 0xc: | |
146 | dev_priv->mem_freq = 800; | |
147 | break; | |
148 | case 0x10: | |
149 | dev_priv->mem_freq = 1066; | |
150 | break; | |
151 | case 0x14: | |
152 | dev_priv->mem_freq = 1333; | |
153 | break; | |
154 | case 0x18: | |
155 | dev_priv->mem_freq = 1600; | |
156 | break; | |
157 | default: | |
158 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
159 | ddrpll & 0xff); | |
160 | dev_priv->mem_freq = 0; | |
161 | break; | |
162 | } | |
163 | ||
20e4d407 | 164 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
165 | |
166 | switch (csipll & 0x3ff) { | |
167 | case 0x00c: | |
168 | dev_priv->fsb_freq = 3200; | |
169 | break; | |
170 | case 0x00e: | |
171 | dev_priv->fsb_freq = 3733; | |
172 | break; | |
173 | case 0x010: | |
174 | dev_priv->fsb_freq = 4266; | |
175 | break; | |
176 | case 0x012: | |
177 | dev_priv->fsb_freq = 4800; | |
178 | break; | |
179 | case 0x014: | |
180 | dev_priv->fsb_freq = 5333; | |
181 | break; | |
182 | case 0x016: | |
183 | dev_priv->fsb_freq = 5866; | |
184 | break; | |
185 | case 0x018: | |
186 | dev_priv->fsb_freq = 6400; | |
187 | break; | |
188 | default: | |
189 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
190 | csipll & 0x3ff); | |
191 | dev_priv->fsb_freq = 0; | |
192 | break; | |
193 | } | |
194 | ||
195 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 196 | dev_priv->ips.c_m = 0; |
c921aba8 | 197 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 198 | dev_priv->ips.c_m = 1; |
c921aba8 | 199 | } else { |
20e4d407 | 200 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
201 | } |
202 | } | |
203 | ||
b445e3b0 ED |
204 | static const struct cxsr_latency cxsr_latency_table[] = { |
205 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
206 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
207 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
208 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
209 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
210 | ||
211 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
212 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
213 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
214 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
215 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
216 | ||
217 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
218 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
219 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
220 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
221 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
222 | ||
223 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
224 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
225 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
226 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
227 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
228 | ||
229 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
230 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
231 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
232 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
233 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
234 | ||
235 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
236 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
237 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
238 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
239 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
240 | }; | |
241 | ||
63c62275 | 242 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
243 | int is_ddr3, |
244 | int fsb, | |
245 | int mem) | |
246 | { | |
247 | const struct cxsr_latency *latency; | |
248 | int i; | |
249 | ||
250 | if (fsb == 0 || mem == 0) | |
251 | return NULL; | |
252 | ||
253 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
254 | latency = &cxsr_latency_table[i]; | |
255 | if (is_desktop == latency->is_desktop && | |
256 | is_ddr3 == latency->is_ddr3 && | |
257 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
258 | return latency; | |
259 | } | |
260 | ||
261 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
262 | ||
263 | return NULL; | |
264 | } | |
265 | ||
5209b1f4 | 266 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 267 | { |
5209b1f4 ID |
268 | struct drm_device *dev = dev_priv->dev; |
269 | u32 val; | |
b445e3b0 | 270 | |
5209b1f4 ID |
271 | if (IS_VALLEYVIEW(dev)) { |
272 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
273 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { | |
274 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
275 | } else if (IS_PINEVIEW(dev)) { | |
276 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
277 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
278 | I915_WRITE(DSPFW3, val); | |
279 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
280 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
281 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
282 | I915_WRITE(FW_BLC_SELF, val); | |
283 | } else if (IS_I915GM(dev)) { | |
284 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
285 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
286 | I915_WRITE(INSTPM, val); | |
287 | } else { | |
288 | return; | |
289 | } | |
b445e3b0 | 290 | |
5209b1f4 ID |
291 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
292 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
293 | } |
294 | ||
295 | /* | |
296 | * Latency for FIFO fetches is dependent on several factors: | |
297 | * - memory configuration (speed, channels) | |
298 | * - chipset | |
299 | * - current MCH state | |
300 | * It can be fairly high in some situations, so here we assume a fairly | |
301 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
302 | * set this value too high, the FIFO will fetch frequently to stay full) | |
303 | * and power consumption (set it too low to save power and we might see | |
304 | * FIFO underruns and display "flicker"). | |
305 | * | |
306 | * A value of 5us seems to be a good balance; safe for very low end | |
307 | * platforms but not overly aggressive on lower latency configs. | |
308 | */ | |
5aef6003 | 309 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 310 | |
1fa61106 | 311 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
312 | { |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
314 | uint32_t dsparb = I915_READ(DSPARB); | |
315 | int size; | |
316 | ||
317 | size = dsparb & 0x7f; | |
318 | if (plane) | |
319 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
320 | ||
321 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
322 | plane ? "B" : "A", size); | |
323 | ||
324 | return size; | |
325 | } | |
326 | ||
feb56b93 | 327 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
328 | { |
329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
330 | uint32_t dsparb = I915_READ(DSPARB); | |
331 | int size; | |
332 | ||
333 | size = dsparb & 0x1ff; | |
334 | if (plane) | |
335 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
336 | size >>= 1; /* Convert to cachelines */ | |
337 | ||
338 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
339 | plane ? "B" : "A", size); | |
340 | ||
341 | return size; | |
342 | } | |
343 | ||
1fa61106 | 344 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
345 | { |
346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
347 | uint32_t dsparb = I915_READ(DSPARB); | |
348 | int size; | |
349 | ||
350 | size = dsparb & 0x7f; | |
351 | size >>= 2; /* Convert to cachelines */ | |
352 | ||
353 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
354 | plane ? "B" : "A", | |
355 | size); | |
356 | ||
357 | return size; | |
358 | } | |
359 | ||
b445e3b0 ED |
360 | /* Pineview has different values for various configs */ |
361 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
362 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
363 | .max_wm = PINEVIEW_MAX_WM, | |
364 | .default_wm = PINEVIEW_DFT_WM, | |
365 | .guard_size = PINEVIEW_GUARD_WM, | |
366 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
367 | }; |
368 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
369 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
370 | .max_wm = PINEVIEW_MAX_WM, | |
371 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
372 | .guard_size = PINEVIEW_GUARD_WM, | |
373 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
374 | }; |
375 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
376 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
377 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
378 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
379 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
380 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
381 | }; |
382 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
383 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
384 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
385 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
386 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
387 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
388 | }; |
389 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
390 | .fifo_size = G4X_FIFO_SIZE, |
391 | .max_wm = G4X_MAX_WM, | |
392 | .default_wm = G4X_MAX_WM, | |
393 | .guard_size = 2, | |
394 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
395 | }; |
396 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
397 | .fifo_size = I965_CURSOR_FIFO, |
398 | .max_wm = I965_CURSOR_MAX_WM, | |
399 | .default_wm = I965_CURSOR_DFT_WM, | |
400 | .guard_size = 2, | |
401 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
402 | }; |
403 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
404 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
405 | .max_wm = VALLEYVIEW_MAX_WM, | |
406 | .default_wm = VALLEYVIEW_MAX_WM, | |
407 | .guard_size = 2, | |
408 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
409 | }; |
410 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
411 | .fifo_size = I965_CURSOR_FIFO, |
412 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
413 | .default_wm = I965_CURSOR_DFT_WM, | |
414 | .guard_size = 2, | |
415 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
416 | }; |
417 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
418 | .fifo_size = I965_CURSOR_FIFO, |
419 | .max_wm = I965_CURSOR_MAX_WM, | |
420 | .default_wm = I965_CURSOR_DFT_WM, | |
421 | .guard_size = 2, | |
422 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
423 | }; |
424 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
425 | .fifo_size = I945_FIFO_SIZE, |
426 | .max_wm = I915_MAX_WM, | |
427 | .default_wm = 1, | |
428 | .guard_size = 2, | |
429 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
430 | }; |
431 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
432 | .fifo_size = I915_FIFO_SIZE, |
433 | .max_wm = I915_MAX_WM, | |
434 | .default_wm = 1, | |
435 | .guard_size = 2, | |
436 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 437 | }; |
9d539105 | 438 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
439 | .fifo_size = I855GM_FIFO_SIZE, |
440 | .max_wm = I915_MAX_WM, | |
441 | .default_wm = 1, | |
442 | .guard_size = 2, | |
443 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 444 | }; |
9d539105 VS |
445 | static const struct intel_watermark_params i830_bc_wm_info = { |
446 | .fifo_size = I855GM_FIFO_SIZE, | |
447 | .max_wm = I915_MAX_WM/2, | |
448 | .default_wm = 1, | |
449 | .guard_size = 2, | |
450 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
451 | }; | |
feb56b93 | 452 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
453 | .fifo_size = I830_FIFO_SIZE, |
454 | .max_wm = I915_MAX_WM, | |
455 | .default_wm = 1, | |
456 | .guard_size = 2, | |
457 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
458 | }; |
459 | ||
b445e3b0 ED |
460 | /** |
461 | * intel_calculate_wm - calculate watermark level | |
462 | * @clock_in_khz: pixel clock | |
463 | * @wm: chip FIFO params | |
464 | * @pixel_size: display pixel size | |
465 | * @latency_ns: memory latency for the platform | |
466 | * | |
467 | * Calculate the watermark level (the level at which the display plane will | |
468 | * start fetching from memory again). Each chip has a different display | |
469 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
470 | * in the correct intel_watermark_params structure. | |
471 | * | |
472 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
473 | * on the pixel size. When it reaches the watermark level, it'll start | |
474 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
475 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
476 | * will occur, and a display engine hang could result. | |
477 | */ | |
478 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
479 | const struct intel_watermark_params *wm, | |
480 | int fifo_size, | |
481 | int pixel_size, | |
482 | unsigned long latency_ns) | |
483 | { | |
484 | long entries_required, wm_size; | |
485 | ||
486 | /* | |
487 | * Note: we need to make sure we don't overflow for various clock & | |
488 | * latency values. | |
489 | * clocks go from a few thousand to several hundred thousand. | |
490 | * latency is usually a few thousand | |
491 | */ | |
492 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
493 | 1000; | |
494 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
495 | ||
496 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
497 | ||
498 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
499 | ||
500 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
501 | ||
502 | /* Don't promote wm_size to unsigned... */ | |
503 | if (wm_size > (long)wm->max_wm) | |
504 | wm_size = wm->max_wm; | |
505 | if (wm_size <= 0) | |
506 | wm_size = wm->default_wm; | |
d6feb196 VS |
507 | |
508 | /* | |
509 | * Bspec seems to indicate that the value shouldn't be lower than | |
510 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
511 | * Lets go for 8 which is the burst size since certain platforms | |
512 | * already use a hardcoded 8 (which is what the spec says should be | |
513 | * done). | |
514 | */ | |
515 | if (wm_size <= 8) | |
516 | wm_size = 8; | |
517 | ||
b445e3b0 ED |
518 | return wm_size; |
519 | } | |
520 | ||
521 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
522 | { | |
523 | struct drm_crtc *crtc, *enabled = NULL; | |
524 | ||
70e1e0ec | 525 | for_each_crtc(dev, crtc) { |
3490ea5d | 526 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
527 | if (enabled) |
528 | return NULL; | |
529 | enabled = crtc; | |
530 | } | |
531 | } | |
532 | ||
533 | return enabled; | |
534 | } | |
535 | ||
46ba614c | 536 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 537 | { |
46ba614c | 538 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
539 | struct drm_i915_private *dev_priv = dev->dev_private; |
540 | struct drm_crtc *crtc; | |
541 | const struct cxsr_latency *latency; | |
542 | u32 reg; | |
543 | unsigned long wm; | |
544 | ||
545 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
546 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
547 | if (!latency) { | |
548 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 549 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
550 | return; |
551 | } | |
552 | ||
553 | crtc = single_enabled_crtc(dev); | |
554 | if (crtc) { | |
241bfc38 | 555 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 556 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
241bfc38 DL |
557 | int clock; |
558 | ||
6e3c9717 | 559 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 560 | clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
561 | |
562 | /* Display SR */ | |
563 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
564 | pineview_display_wm.fifo_size, | |
565 | pixel_size, latency->display_sr); | |
566 | reg = I915_READ(DSPFW1); | |
567 | reg &= ~DSPFW_SR_MASK; | |
568 | reg |= wm << DSPFW_SR_SHIFT; | |
569 | I915_WRITE(DSPFW1, reg); | |
570 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
571 | ||
572 | /* cursor SR */ | |
573 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
574 | pineview_display_wm.fifo_size, | |
575 | pixel_size, latency->cursor_sr); | |
576 | reg = I915_READ(DSPFW3); | |
577 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
578 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
579 | I915_WRITE(DSPFW3, reg); | |
580 | ||
581 | /* Display HPLL off SR */ | |
582 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
583 | pineview_display_hplloff_wm.fifo_size, | |
584 | pixel_size, latency->display_hpll_disable); | |
585 | reg = I915_READ(DSPFW3); | |
586 | reg &= ~DSPFW_HPLL_SR_MASK; | |
587 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
588 | I915_WRITE(DSPFW3, reg); | |
589 | ||
590 | /* cursor HPLL off SR */ | |
591 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
592 | pineview_display_hplloff_wm.fifo_size, | |
593 | pixel_size, latency->cursor_hpll_disable); | |
594 | reg = I915_READ(DSPFW3); | |
595 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
596 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
597 | I915_WRITE(DSPFW3, reg); | |
598 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
599 | ||
5209b1f4 | 600 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 601 | } else { |
5209b1f4 | 602 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
603 | } |
604 | } | |
605 | ||
606 | static bool g4x_compute_wm0(struct drm_device *dev, | |
607 | int plane, | |
608 | const struct intel_watermark_params *display, | |
609 | int display_latency_ns, | |
610 | const struct intel_watermark_params *cursor, | |
611 | int cursor_latency_ns, | |
612 | int *plane_wm, | |
613 | int *cursor_wm) | |
614 | { | |
615 | struct drm_crtc *crtc; | |
4fe8590a | 616 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
617 | int htotal, hdisplay, clock, pixel_size; |
618 | int line_time_us, line_count; | |
619 | int entries, tlb_miss; | |
620 | ||
621 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 622 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
623 | *cursor_wm = cursor->guard_size; |
624 | *plane_wm = display->guard_size; | |
625 | return false; | |
626 | } | |
627 | ||
6e3c9717 | 628 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 629 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 630 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 631 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
f4510a27 | 632 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
633 | |
634 | /* Use the small buffer method to calculate plane watermark */ | |
635 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
636 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
637 | if (tlb_miss > 0) | |
638 | entries += tlb_miss; | |
639 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
640 | *plane_wm = entries + display->guard_size; | |
641 | if (*plane_wm > (int)display->max_wm) | |
642 | *plane_wm = display->max_wm; | |
643 | ||
644 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 645 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 646 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
7bb836dd | 647 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
b445e3b0 ED |
648 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
649 | if (tlb_miss > 0) | |
650 | entries += tlb_miss; | |
651 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
652 | *cursor_wm = entries + cursor->guard_size; | |
653 | if (*cursor_wm > (int)cursor->max_wm) | |
654 | *cursor_wm = (int)cursor->max_wm; | |
655 | ||
656 | return true; | |
657 | } | |
658 | ||
659 | /* | |
660 | * Check the wm result. | |
661 | * | |
662 | * If any calculated watermark values is larger than the maximum value that | |
663 | * can be programmed into the associated watermark register, that watermark | |
664 | * must be disabled. | |
665 | */ | |
666 | static bool g4x_check_srwm(struct drm_device *dev, | |
667 | int display_wm, int cursor_wm, | |
668 | const struct intel_watermark_params *display, | |
669 | const struct intel_watermark_params *cursor) | |
670 | { | |
671 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
672 | display_wm, cursor_wm); | |
673 | ||
674 | if (display_wm > display->max_wm) { | |
675 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
676 | display_wm, display->max_wm); | |
677 | return false; | |
678 | } | |
679 | ||
680 | if (cursor_wm > cursor->max_wm) { | |
681 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
682 | cursor_wm, cursor->max_wm); | |
683 | return false; | |
684 | } | |
685 | ||
686 | if (!(display_wm || cursor_wm)) { | |
687 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
688 | return false; | |
689 | } | |
690 | ||
691 | return true; | |
692 | } | |
693 | ||
694 | static bool g4x_compute_srwm(struct drm_device *dev, | |
695 | int plane, | |
696 | int latency_ns, | |
697 | const struct intel_watermark_params *display, | |
698 | const struct intel_watermark_params *cursor, | |
699 | int *display_wm, int *cursor_wm) | |
700 | { | |
701 | struct drm_crtc *crtc; | |
4fe8590a | 702 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
703 | int hdisplay, htotal, pixel_size, clock; |
704 | unsigned long line_time_us; | |
705 | int line_count, line_size; | |
706 | int small, large; | |
707 | int entries; | |
708 | ||
709 | if (!latency_ns) { | |
710 | *display_wm = *cursor_wm = 0; | |
711 | return false; | |
712 | } | |
713 | ||
714 | crtc = intel_get_crtc_for_plane(dev, plane); | |
6e3c9717 | 715 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 716 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 717 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 718 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
f4510a27 | 719 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 | 720 | |
922044c9 | 721 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
722 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
723 | line_size = hdisplay * pixel_size; | |
724 | ||
725 | /* Use the minimum of the small and large buffer method for primary */ | |
726 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
727 | large = line_count * line_size; | |
728 | ||
729 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
730 | *display_wm = entries + display->guard_size; | |
731 | ||
732 | /* calculate the self-refresh watermark for display cursor */ | |
7bb836dd | 733 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
734 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
735 | *cursor_wm = entries + cursor->guard_size; | |
736 | ||
737 | return g4x_check_srwm(dev, | |
738 | *display_wm, *cursor_wm, | |
739 | display, cursor); | |
740 | } | |
741 | ||
0948c265 GB |
742 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, |
743 | int pixel_size, | |
744 | int *prec_mult, | |
745 | int *drain_latency) | |
b445e3b0 | 746 | { |
5e56ba45 | 747 | struct drm_device *dev = crtc->dev; |
b445e3b0 | 748 | int entries; |
6e3c9717 | 749 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
b445e3b0 | 750 | |
0948c265 | 751 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
b445e3b0 ED |
752 | return false; |
753 | ||
0948c265 GB |
754 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
755 | return false; | |
b445e3b0 | 756 | |
a398e9c7 | 757 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
5e56ba45 RV |
758 | if (IS_CHERRYVIEW(dev)) |
759 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 : | |
760 | DRAIN_LATENCY_PRECISION_16; | |
761 | else | |
762 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : | |
763 | DRAIN_LATENCY_PRECISION_32; | |
0948c265 | 764 | *drain_latency = (64 * (*prec_mult) * 4) / entries; |
b445e3b0 | 765 | |
a398e9c7 GB |
766 | if (*drain_latency > DRAIN_LATENCY_MASK) |
767 | *drain_latency = DRAIN_LATENCY_MASK; | |
b445e3b0 ED |
768 | |
769 | return true; | |
770 | } | |
771 | ||
772 | /* | |
773 | * Update drain latency registers of memory arbiter | |
774 | * | |
775 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
776 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
777 | * latency value. | |
778 | */ | |
779 | ||
41aad816 | 780 | static void vlv_update_drain_latency(struct drm_crtc *crtc) |
b445e3b0 | 781 | { |
5e56ba45 RV |
782 | struct drm_device *dev = crtc->dev; |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0948c265 GB |
784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
785 | int pixel_size; | |
786 | int drain_latency; | |
787 | enum pipe pipe = intel_crtc->pipe; | |
788 | int plane_prec, prec_mult, plane_dl; | |
5e56ba45 RV |
789 | const int high_precision = IS_CHERRYVIEW(dev) ? |
790 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
b445e3b0 | 791 | |
5e56ba45 RV |
792 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH | |
793 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH | | |
0948c265 GB |
794 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); |
795 | ||
796 | if (!intel_crtc_active(crtc)) { | |
797 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
798 | return; | |
799 | } | |
b445e3b0 | 800 | |
0948c265 GB |
801 | /* Primary plane Drain Latency */ |
802 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ | |
803 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
5e56ba45 RV |
804 | plane_prec = (prec_mult == high_precision) ? |
805 | DDL_PLANE_PRECISION_HIGH : | |
806 | DDL_PLANE_PRECISION_LOW; | |
0948c265 | 807 | plane_dl |= plane_prec | drain_latency; |
b445e3b0 ED |
808 | } |
809 | ||
0948c265 GB |
810 | /* Cursor Drain Latency |
811 | * BPP is always 4 for cursor | |
812 | */ | |
813 | pixel_size = 4; | |
b445e3b0 | 814 | |
0948c265 GB |
815 | /* Program cursor DL only if it is enabled */ |
816 | if (intel_crtc->cursor_base && | |
817 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
5e56ba45 RV |
818 | plane_prec = (prec_mult == high_precision) ? |
819 | DDL_CURSOR_PRECISION_HIGH : | |
820 | DDL_CURSOR_PRECISION_LOW; | |
0948c265 | 821 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); |
b445e3b0 | 822 | } |
0948c265 GB |
823 | |
824 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
b445e3b0 ED |
825 | } |
826 | ||
827 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
828 | ||
46ba614c | 829 | static void valleyview_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 830 | { |
46ba614c | 831 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
832 | static const int sr_latency_ns = 12000; |
833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
834 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
835 | int plane_sr, cursor_sr; | |
af6c4575 | 836 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 | 837 | unsigned int enabled = 0; |
9858425c | 838 | bool cxsr_enabled; |
b445e3b0 | 839 | |
41aad816 | 840 | vlv_update_drain_latency(crtc); |
b445e3b0 | 841 | |
51cea1f4 | 842 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
843 | &valleyview_wm_info, pessimal_latency_ns, |
844 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 845 | &planea_wm, &cursora_wm)) |
51cea1f4 | 846 | enabled |= 1 << PIPE_A; |
b445e3b0 | 847 | |
51cea1f4 | 848 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
849 | &valleyview_wm_info, pessimal_latency_ns, |
850 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 851 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 852 | enabled |= 1 << PIPE_B; |
b445e3b0 | 853 | |
b445e3b0 ED |
854 | if (single_plane_enabled(enabled) && |
855 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
856 | sr_latency_ns, | |
857 | &valleyview_wm_info, | |
858 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
859 | &plane_sr, &ignore_cursor_sr) && |
860 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
861 | 2*sr_latency_ns, | |
862 | &valleyview_wm_info, | |
863 | &valleyview_cursor_wm_info, | |
52bd02d8 | 864 | &ignore_plane_sr, &cursor_sr)) { |
9858425c | 865 | cxsr_enabled = true; |
52bd02d8 | 866 | } else { |
9858425c | 867 | cxsr_enabled = false; |
5209b1f4 | 868 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
869 | plane_sr = cursor_sr = 0; |
870 | } | |
b445e3b0 | 871 | |
a5043453 VS |
872 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
873 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
874 | planea_wm, cursora_wm, |
875 | planeb_wm, cursorb_wm, | |
876 | plane_sr, cursor_sr); | |
877 | ||
878 | I915_WRITE(DSPFW1, | |
879 | (plane_sr << DSPFW_SR_SHIFT) | | |
880 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
881 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 882 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 883 | I915_WRITE(DSPFW2, |
8c919b28 | 884 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
885 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
886 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
887 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
888 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
889 | |
890 | if (cxsr_enabled) | |
891 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
892 | } |
893 | ||
3c2777fd VS |
894 | static void cherryview_update_wm(struct drm_crtc *crtc) |
895 | { | |
896 | struct drm_device *dev = crtc->dev; | |
897 | static const int sr_latency_ns = 12000; | |
898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
899 | int planea_wm, planeb_wm, planec_wm; | |
900 | int cursora_wm, cursorb_wm, cursorc_wm; | |
901 | int plane_sr, cursor_sr; | |
902 | int ignore_plane_sr, ignore_cursor_sr; | |
903 | unsigned int enabled = 0; | |
904 | bool cxsr_enabled; | |
905 | ||
906 | vlv_update_drain_latency(crtc); | |
907 | ||
908 | if (g4x_compute_wm0(dev, PIPE_A, | |
5aef6003 CW |
909 | &valleyview_wm_info, pessimal_latency_ns, |
910 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
911 | &planea_wm, &cursora_wm)) |
912 | enabled |= 1 << PIPE_A; | |
913 | ||
914 | if (g4x_compute_wm0(dev, PIPE_B, | |
5aef6003 CW |
915 | &valleyview_wm_info, pessimal_latency_ns, |
916 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
917 | &planeb_wm, &cursorb_wm)) |
918 | enabled |= 1 << PIPE_B; | |
919 | ||
920 | if (g4x_compute_wm0(dev, PIPE_C, | |
5aef6003 CW |
921 | &valleyview_wm_info, pessimal_latency_ns, |
922 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
923 | &planec_wm, &cursorc_wm)) |
924 | enabled |= 1 << PIPE_C; | |
925 | ||
926 | if (single_plane_enabled(enabled) && | |
927 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
928 | sr_latency_ns, | |
929 | &valleyview_wm_info, | |
930 | &valleyview_cursor_wm_info, | |
931 | &plane_sr, &ignore_cursor_sr) && | |
932 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
933 | 2*sr_latency_ns, | |
934 | &valleyview_wm_info, | |
935 | &valleyview_cursor_wm_info, | |
936 | &ignore_plane_sr, &cursor_sr)) { | |
937 | cxsr_enabled = true; | |
938 | } else { | |
939 | cxsr_enabled = false; | |
940 | intel_set_memory_cxsr(dev_priv, false); | |
941 | plane_sr = cursor_sr = 0; | |
942 | } | |
943 | ||
944 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
945 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " | |
946 | "SR: plane=%d, cursor=%d\n", | |
947 | planea_wm, cursora_wm, | |
948 | planeb_wm, cursorb_wm, | |
949 | planec_wm, cursorc_wm, | |
950 | plane_sr, cursor_sr); | |
951 | ||
952 | I915_WRITE(DSPFW1, | |
953 | (plane_sr << DSPFW_SR_SHIFT) | | |
954 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
955 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
956 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
957 | I915_WRITE(DSPFW2, | |
958 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
959 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
960 | I915_WRITE(DSPFW3, | |
961 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | | |
962 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
963 | I915_WRITE(DSPFW9_CHV, | |
964 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | | |
965 | DSPFW_CURSORC_MASK)) | | |
966 | (planec_wm << DSPFW_PLANEC_SHIFT) | | |
967 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); | |
968 | ||
969 | if (cxsr_enabled) | |
970 | intel_set_memory_cxsr(dev_priv, true); | |
971 | } | |
972 | ||
01e184cc GB |
973 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
974 | struct drm_crtc *crtc, | |
975 | uint32_t sprite_width, | |
976 | uint32_t sprite_height, | |
977 | int pixel_size, | |
978 | bool enabled, bool scaled) | |
979 | { | |
980 | struct drm_device *dev = crtc->dev; | |
981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
982 | int pipe = to_intel_plane(plane)->pipe; | |
983 | int sprite = to_intel_plane(plane)->plane; | |
984 | int drain_latency; | |
985 | int plane_prec; | |
986 | int sprite_dl; | |
987 | int prec_mult; | |
5e56ba45 RV |
988 | const int high_precision = IS_CHERRYVIEW(dev) ? |
989 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
01e184cc | 990 | |
5e56ba45 | 991 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) | |
01e184cc GB |
992 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); |
993 | ||
994 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, | |
995 | &drain_latency)) { | |
5e56ba45 RV |
996 | plane_prec = (prec_mult == high_precision) ? |
997 | DDL_SPRITE_PRECISION_HIGH(sprite) : | |
998 | DDL_SPRITE_PRECISION_LOW(sprite); | |
01e184cc GB |
999 | sprite_dl |= plane_prec | |
1000 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); | |
1001 | } | |
1002 | ||
1003 | I915_WRITE(VLV_DDL(pipe), sprite_dl); | |
1004 | } | |
1005 | ||
46ba614c | 1006 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1007 | { |
46ba614c | 1008 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1009 | static const int sr_latency_ns = 12000; |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1012 | int plane_sr, cursor_sr; | |
1013 | unsigned int enabled = 0; | |
9858425c | 1014 | bool cxsr_enabled; |
b445e3b0 | 1015 | |
51cea1f4 | 1016 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1017 | &g4x_wm_info, pessimal_latency_ns, |
1018 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1019 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1020 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1021 | |
51cea1f4 | 1022 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1023 | &g4x_wm_info, pessimal_latency_ns, |
1024 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1025 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1026 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1027 | |
b445e3b0 ED |
1028 | if (single_plane_enabled(enabled) && |
1029 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1030 | sr_latency_ns, | |
1031 | &g4x_wm_info, | |
1032 | &g4x_cursor_wm_info, | |
52bd02d8 | 1033 | &plane_sr, &cursor_sr)) { |
9858425c | 1034 | cxsr_enabled = true; |
52bd02d8 | 1035 | } else { |
9858425c | 1036 | cxsr_enabled = false; |
5209b1f4 | 1037 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1038 | plane_sr = cursor_sr = 0; |
1039 | } | |
b445e3b0 | 1040 | |
a5043453 VS |
1041 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1042 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1043 | planea_wm, cursora_wm, |
1044 | planeb_wm, cursorb_wm, | |
1045 | plane_sr, cursor_sr); | |
1046 | ||
1047 | I915_WRITE(DSPFW1, | |
1048 | (plane_sr << DSPFW_SR_SHIFT) | | |
1049 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1050 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1051 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1052 | I915_WRITE(DSPFW2, |
8c919b28 | 1053 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1054 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1055 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1056 | I915_WRITE(DSPFW3, | |
8c919b28 | 1057 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 | 1058 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
9858425c ID |
1059 | |
1060 | if (cxsr_enabled) | |
1061 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1062 | } |
1063 | ||
46ba614c | 1064 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1065 | { |
46ba614c | 1066 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1067 | struct drm_i915_private *dev_priv = dev->dev_private; |
1068 | struct drm_crtc *crtc; | |
1069 | int srwm = 1; | |
1070 | int cursor_sr = 16; | |
9858425c | 1071 | bool cxsr_enabled; |
b445e3b0 ED |
1072 | |
1073 | /* Calc sr entries for one plane configs */ | |
1074 | crtc = single_enabled_crtc(dev); | |
1075 | if (crtc) { | |
1076 | /* self-refresh has much higher latency */ | |
1077 | static const int sr_latency_ns = 12000; | |
4fe8590a | 1078 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1079 | &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1080 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1081 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1082 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
f4510a27 | 1083 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1084 | unsigned long line_time_us; |
1085 | int entries; | |
1086 | ||
922044c9 | 1087 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1088 | |
1089 | /* Use ns/us then divide to preserve precision */ | |
1090 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1091 | pixel_size * hdisplay; | |
1092 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1093 | srwm = I965_FIFO_SIZE - entries; | |
1094 | if (srwm < 0) | |
1095 | srwm = 1; | |
1096 | srwm &= 0x1ff; | |
1097 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1098 | entries, srwm); | |
1099 | ||
1100 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
7bb836dd | 1101 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1102 | entries = DIV_ROUND_UP(entries, |
1103 | i965_cursor_wm_info.cacheline_size); | |
1104 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1105 | (entries + i965_cursor_wm_info.guard_size); | |
1106 | ||
1107 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1108 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1109 | ||
1110 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1111 | "cursor %d\n", srwm, cursor_sr); | |
1112 | ||
9858425c | 1113 | cxsr_enabled = true; |
b445e3b0 | 1114 | } else { |
9858425c | 1115 | cxsr_enabled = false; |
b445e3b0 | 1116 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1117 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1118 | } |
1119 | ||
1120 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1121 | srwm); | |
1122 | ||
1123 | /* 965 has limitations... */ | |
1124 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
0a560674 VS |
1125 | (8 << DSPFW_CURSORB_SHIFT) | |
1126 | (8 << DSPFW_PLANEB_SHIFT) | | |
1127 | (8 << DSPFW_PLANEA_SHIFT)); | |
1128 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | | |
1129 | (8 << DSPFW_PLANEC_SHIFT_OLD)); | |
b445e3b0 ED |
1130 | /* update cursor SR watermark */ |
1131 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1132 | |
1133 | if (cxsr_enabled) | |
1134 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1135 | } |
1136 | ||
46ba614c | 1137 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1138 | { |
46ba614c | 1139 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
1141 | const struct intel_watermark_params *wm_info; | |
1142 | uint32_t fwater_lo; | |
1143 | uint32_t fwater_hi; | |
1144 | int cwm, srwm = 1; | |
1145 | int fifo_size; | |
1146 | int planea_wm, planeb_wm; | |
1147 | struct drm_crtc *crtc, *enabled = NULL; | |
1148 | ||
1149 | if (IS_I945GM(dev)) | |
1150 | wm_info = &i945_wm_info; | |
1151 | else if (!IS_GEN2(dev)) | |
1152 | wm_info = &i915_wm_info; | |
1153 | else | |
9d539105 | 1154 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1155 | |
1156 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1157 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1158 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1159 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1160 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1161 | if (IS_GEN2(dev)) |
1162 | cpp = 4; | |
1163 | ||
6e3c9717 | 1164 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1165 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1166 | wm_info, fifo_size, cpp, |
5aef6003 | 1167 | pessimal_latency_ns); |
b445e3b0 | 1168 | enabled = crtc; |
9d539105 | 1169 | } else { |
b445e3b0 | 1170 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1171 | if (planea_wm > (long)wm_info->max_wm) |
1172 | planea_wm = wm_info->max_wm; | |
1173 | } | |
1174 | ||
1175 | if (IS_GEN2(dev)) | |
1176 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1177 | |
1178 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1179 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1180 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1181 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1182 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1183 | if (IS_GEN2(dev)) |
1184 | cpp = 4; | |
1185 | ||
6e3c9717 | 1186 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1187 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1188 | wm_info, fifo_size, cpp, |
5aef6003 | 1189 | pessimal_latency_ns); |
b445e3b0 ED |
1190 | if (enabled == NULL) |
1191 | enabled = crtc; | |
1192 | else | |
1193 | enabled = NULL; | |
9d539105 | 1194 | } else { |
b445e3b0 | 1195 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1196 | if (planeb_wm > (long)wm_info->max_wm) |
1197 | planeb_wm = wm_info->max_wm; | |
1198 | } | |
b445e3b0 ED |
1199 | |
1200 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1201 | ||
2ab1bc9d | 1202 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1203 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1204 | |
2ff8fde1 | 1205 | obj = intel_fb_obj(enabled->primary->fb); |
2ab1bc9d DV |
1206 | |
1207 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1208 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1209 | enabled = NULL; |
1210 | } | |
1211 | ||
b445e3b0 ED |
1212 | /* |
1213 | * Overlay gets an aggressive default since video jitter is bad. | |
1214 | */ | |
1215 | cwm = 2; | |
1216 | ||
1217 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1218 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1219 | |
1220 | /* Calc sr entries for one plane configs */ | |
1221 | if (HAS_FW_BLC(dev) && enabled) { | |
1222 | /* self-refresh has much higher latency */ | |
1223 | static const int sr_latency_ns = 6000; | |
4fe8590a | 1224 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1225 | &to_intel_crtc(enabled)->config->base.adjusted_mode; |
241bfc38 | 1226 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1227 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1228 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
f4510a27 | 1229 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1230 | unsigned long line_time_us; |
1231 | int entries; | |
1232 | ||
922044c9 | 1233 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1234 | |
1235 | /* Use ns/us then divide to preserve precision */ | |
1236 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1237 | pixel_size * hdisplay; | |
1238 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1239 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1240 | srwm = wm_info->fifo_size - entries; | |
1241 | if (srwm < 0) | |
1242 | srwm = 1; | |
1243 | ||
1244 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1245 | I915_WRITE(FW_BLC_SELF, | |
1246 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1247 | else if (IS_I915GM(dev)) | |
1248 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1249 | } | |
1250 | ||
1251 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1252 | planea_wm, planeb_wm, cwm, srwm); | |
1253 | ||
1254 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1255 | fwater_hi = (cwm & 0x1f); | |
1256 | ||
1257 | /* Set request length to 8 cachelines per fetch */ | |
1258 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1259 | fwater_hi = fwater_hi | (1 << 8); | |
1260 | ||
1261 | I915_WRITE(FW_BLC, fwater_lo); | |
1262 | I915_WRITE(FW_BLC2, fwater_hi); | |
1263 | ||
5209b1f4 ID |
1264 | if (enabled) |
1265 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1266 | } |
1267 | ||
feb56b93 | 1268 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1269 | { |
46ba614c | 1270 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1271 | struct drm_i915_private *dev_priv = dev->dev_private; |
1272 | struct drm_crtc *crtc; | |
241bfc38 | 1273 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1274 | uint32_t fwater_lo; |
1275 | int planea_wm; | |
1276 | ||
1277 | crtc = single_enabled_crtc(dev); | |
1278 | if (crtc == NULL) | |
1279 | return; | |
1280 | ||
6e3c9717 | 1281 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1282 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1283 | &i845_wm_info, |
b445e3b0 | 1284 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1285 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1286 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1287 | fwater_lo |= (3<<8) | planea_wm; | |
1288 | ||
1289 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1290 | ||
1291 | I915_WRITE(FW_BLC, fwater_lo); | |
1292 | } | |
1293 | ||
3658729a VS |
1294 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1295 | struct drm_crtc *crtc) | |
801bcfff PZ |
1296 | { |
1297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1298 | uint32_t pixel_rate; |
801bcfff | 1299 | |
6e3c9717 | 1300 | pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; |
801bcfff PZ |
1301 | |
1302 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1303 | * adjust the pixel_rate here. */ | |
1304 | ||
6e3c9717 | 1305 | if (intel_crtc->config->pch_pfit.enabled) { |
801bcfff | 1306 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
6e3c9717 | 1307 | uint32_t pfit_size = intel_crtc->config->pch_pfit.size; |
801bcfff | 1308 | |
6e3c9717 ACO |
1309 | pipe_w = intel_crtc->config->pipe_src_w; |
1310 | pipe_h = intel_crtc->config->pipe_src_h; | |
801bcfff PZ |
1311 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1312 | pfit_h = pfit_size & 0xFFFF; | |
1313 | if (pipe_w < pfit_w) | |
1314 | pipe_w = pfit_w; | |
1315 | if (pipe_h < pfit_h) | |
1316 | pipe_h = pfit_h; | |
1317 | ||
1318 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1319 | pfit_w * pfit_h); | |
1320 | } | |
1321 | ||
1322 | return pixel_rate; | |
1323 | } | |
1324 | ||
37126462 | 1325 | /* latency must be in 0.1us units. */ |
23297044 | 1326 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1327 | uint32_t latency) |
1328 | { | |
1329 | uint64_t ret; | |
1330 | ||
3312ba65 VS |
1331 | if (WARN(latency == 0, "Latency value missing\n")) |
1332 | return UINT_MAX; | |
1333 | ||
801bcfff PZ |
1334 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1335 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1336 | ||
1337 | return ret; | |
1338 | } | |
1339 | ||
37126462 | 1340 | /* latency must be in 0.1us units. */ |
23297044 | 1341 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1342 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1343 | uint32_t latency) | |
1344 | { | |
1345 | uint32_t ret; | |
1346 | ||
3312ba65 VS |
1347 | if (WARN(latency == 0, "Latency value missing\n")) |
1348 | return UINT_MAX; | |
1349 | ||
801bcfff PZ |
1350 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1351 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1352 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1353 | return ret; | |
1354 | } | |
1355 | ||
23297044 | 1356 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1357 | uint8_t bytes_per_pixel) |
1358 | { | |
1359 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1360 | } | |
1361 | ||
2ac96d2a PB |
1362 | struct skl_pipe_wm_parameters { |
1363 | bool active; | |
1364 | uint32_t pipe_htotal; | |
1365 | uint32_t pixel_rate; /* in KHz */ | |
1366 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1367 | struct intel_plane_wm_parameters cursor; | |
1368 | }; | |
1369 | ||
820c1980 | 1370 | struct ilk_pipe_wm_parameters { |
801bcfff | 1371 | bool active; |
801bcfff PZ |
1372 | uint32_t pipe_htotal; |
1373 | uint32_t pixel_rate; | |
c35426d2 VS |
1374 | struct intel_plane_wm_parameters pri; |
1375 | struct intel_plane_wm_parameters spr; | |
1376 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1377 | }; |
1378 | ||
820c1980 | 1379 | struct ilk_wm_maximums { |
cca32e9a PZ |
1380 | uint16_t pri; |
1381 | uint16_t spr; | |
1382 | uint16_t cur; | |
1383 | uint16_t fbc; | |
1384 | }; | |
1385 | ||
240264f4 VS |
1386 | /* used in computing the new watermarks state */ |
1387 | struct intel_wm_config { | |
1388 | unsigned int num_pipes_active; | |
1389 | bool sprites_enabled; | |
1390 | bool sprites_scaled; | |
240264f4 VS |
1391 | }; |
1392 | ||
37126462 VS |
1393 | /* |
1394 | * For both WM_PIPE and WM_LP. | |
1395 | * mem_value must be in 0.1us units. | |
1396 | */ | |
820c1980 | 1397 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1398 | uint32_t mem_value, |
1399 | bool is_lp) | |
801bcfff | 1400 | { |
cca32e9a PZ |
1401 | uint32_t method1, method2; |
1402 | ||
c35426d2 | 1403 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1404 | return 0; |
1405 | ||
23297044 | 1406 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1407 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1408 | mem_value); |
1409 | ||
1410 | if (!is_lp) | |
1411 | return method1; | |
1412 | ||
23297044 | 1413 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1414 | params->pipe_htotal, |
c35426d2 VS |
1415 | params->pri.horiz_pixels, |
1416 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1417 | mem_value); |
1418 | ||
1419 | return min(method1, method2); | |
801bcfff PZ |
1420 | } |
1421 | ||
37126462 VS |
1422 | /* |
1423 | * For both WM_PIPE and WM_LP. | |
1424 | * mem_value must be in 0.1us units. | |
1425 | */ | |
820c1980 | 1426 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1427 | uint32_t mem_value) |
1428 | { | |
1429 | uint32_t method1, method2; | |
1430 | ||
c35426d2 | 1431 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1432 | return 0; |
1433 | ||
23297044 | 1434 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1435 | params->spr.bytes_per_pixel, |
801bcfff | 1436 | mem_value); |
23297044 | 1437 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1438 | params->pipe_htotal, |
c35426d2 VS |
1439 | params->spr.horiz_pixels, |
1440 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1441 | mem_value); |
1442 | return min(method1, method2); | |
1443 | } | |
1444 | ||
37126462 VS |
1445 | /* |
1446 | * For both WM_PIPE and WM_LP. | |
1447 | * mem_value must be in 0.1us units. | |
1448 | */ | |
820c1980 | 1449 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1450 | uint32_t mem_value) |
1451 | { | |
c35426d2 | 1452 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1453 | return 0; |
1454 | ||
23297044 | 1455 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1456 | params->pipe_htotal, |
c35426d2 VS |
1457 | params->cur.horiz_pixels, |
1458 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
1459 | mem_value); |
1460 | } | |
1461 | ||
cca32e9a | 1462 | /* Only for WM_LP. */ |
820c1980 | 1463 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 1464 | uint32_t pri_val) |
cca32e9a | 1465 | { |
c35426d2 | 1466 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
1467 | return 0; |
1468 | ||
23297044 | 1469 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
1470 | params->pri.horiz_pixels, |
1471 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
1472 | } |
1473 | ||
158ae64f VS |
1474 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1475 | { | |
416f4727 VS |
1476 | if (INTEL_INFO(dev)->gen >= 8) |
1477 | return 3072; | |
1478 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1479 | return 768; |
1480 | else | |
1481 | return 512; | |
1482 | } | |
1483 | ||
4e975081 VS |
1484 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1485 | int level, bool is_sprite) | |
1486 | { | |
1487 | if (INTEL_INFO(dev)->gen >= 8) | |
1488 | /* BDW primary/sprite plane watermarks */ | |
1489 | return level == 0 ? 255 : 2047; | |
1490 | else if (INTEL_INFO(dev)->gen >= 7) | |
1491 | /* IVB/HSW primary/sprite plane watermarks */ | |
1492 | return level == 0 ? 127 : 1023; | |
1493 | else if (!is_sprite) | |
1494 | /* ILK/SNB primary plane watermarks */ | |
1495 | return level == 0 ? 127 : 511; | |
1496 | else | |
1497 | /* ILK/SNB sprite plane watermarks */ | |
1498 | return level == 0 ? 63 : 255; | |
1499 | } | |
1500 | ||
1501 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1502 | int level) | |
1503 | { | |
1504 | if (INTEL_INFO(dev)->gen >= 7) | |
1505 | return level == 0 ? 63 : 255; | |
1506 | else | |
1507 | return level == 0 ? 31 : 63; | |
1508 | } | |
1509 | ||
1510 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1511 | { | |
1512 | if (INTEL_INFO(dev)->gen >= 8) | |
1513 | return 31; | |
1514 | else | |
1515 | return 15; | |
1516 | } | |
1517 | ||
158ae64f VS |
1518 | /* Calculate the maximum primary/sprite plane watermark */ |
1519 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1520 | int level, | |
240264f4 | 1521 | const struct intel_wm_config *config, |
158ae64f VS |
1522 | enum intel_ddb_partitioning ddb_partitioning, |
1523 | bool is_sprite) | |
1524 | { | |
1525 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1526 | |
1527 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1528 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1529 | return 0; |
1530 | ||
1531 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1532 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1533 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1534 | ||
1535 | /* | |
1536 | * For some reason the non self refresh | |
1537 | * FIFO size is only half of the self | |
1538 | * refresh FIFO size on ILK/SNB. | |
1539 | */ | |
1540 | if (INTEL_INFO(dev)->gen <= 6) | |
1541 | fifo_size /= 2; | |
1542 | } | |
1543 | ||
240264f4 | 1544 | if (config->sprites_enabled) { |
158ae64f VS |
1545 | /* level 0 is always calculated with 1:1 split */ |
1546 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1547 | if (is_sprite) | |
1548 | fifo_size *= 5; | |
1549 | fifo_size /= 6; | |
1550 | } else { | |
1551 | fifo_size /= 2; | |
1552 | } | |
1553 | } | |
1554 | ||
1555 | /* clamp to max that the registers can hold */ | |
4e975081 | 1556 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1557 | } |
1558 | ||
1559 | /* Calculate the maximum cursor plane watermark */ | |
1560 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1561 | int level, |
1562 | const struct intel_wm_config *config) | |
158ae64f VS |
1563 | { |
1564 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1565 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1566 | return 64; |
1567 | ||
1568 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1569 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1570 | } |
1571 | ||
d34ff9c6 | 1572 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1573 | int level, |
1574 | const struct intel_wm_config *config, | |
1575 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1576 | struct ilk_wm_maximums *max) |
158ae64f | 1577 | { |
240264f4 VS |
1578 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1579 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1580 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1581 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1582 | } |
1583 | ||
a3cb4048 VS |
1584 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1585 | int level, | |
1586 | struct ilk_wm_maximums *max) | |
1587 | { | |
1588 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1589 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1590 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1591 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1592 | } | |
1593 | ||
d9395655 | 1594 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1595 | const struct ilk_wm_maximums *max, |
d9395655 | 1596 | struct intel_wm_level *result) |
a9786a11 VS |
1597 | { |
1598 | bool ret; | |
1599 | ||
1600 | /* already determined to be invalid? */ | |
1601 | if (!result->enable) | |
1602 | return false; | |
1603 | ||
1604 | result->enable = result->pri_val <= max->pri && | |
1605 | result->spr_val <= max->spr && | |
1606 | result->cur_val <= max->cur; | |
1607 | ||
1608 | ret = result->enable; | |
1609 | ||
1610 | /* | |
1611 | * HACK until we can pre-compute everything, | |
1612 | * and thus fail gracefully if LP0 watermarks | |
1613 | * are exceeded... | |
1614 | */ | |
1615 | if (level == 0 && !result->enable) { | |
1616 | if (result->pri_val > max->pri) | |
1617 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1618 | level, result->pri_val, max->pri); | |
1619 | if (result->spr_val > max->spr) | |
1620 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1621 | level, result->spr_val, max->spr); | |
1622 | if (result->cur_val > max->cur) | |
1623 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1624 | level, result->cur_val, max->cur); | |
1625 | ||
1626 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1627 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1628 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1629 | result->enable = true; | |
1630 | } | |
1631 | ||
a9786a11 VS |
1632 | return ret; |
1633 | } | |
1634 | ||
d34ff9c6 | 1635 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 1636 | int level, |
820c1980 | 1637 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 1638 | struct intel_wm_level *result) |
6f5ddd17 VS |
1639 | { |
1640 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1641 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1642 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1643 | ||
1644 | /* WM1+ latency values stored in 0.5us units */ | |
1645 | if (level > 0) { | |
1646 | pri_latency *= 5; | |
1647 | spr_latency *= 5; | |
1648 | cur_latency *= 5; | |
1649 | } | |
1650 | ||
1651 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
1652 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
1653 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
1654 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
1655 | result->enable = true; | |
1656 | } | |
1657 | ||
801bcfff PZ |
1658 | static uint32_t |
1659 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
1660 | { |
1661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 1662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 1663 | struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
85a02deb | 1664 | u32 linetime, ips_linetime; |
1f8eeabf | 1665 | |
801bcfff PZ |
1666 | if (!intel_crtc_active(crtc)) |
1667 | return 0; | |
1011d8c4 | 1668 | |
1f8eeabf ED |
1669 | /* The WM are computed with base on how long it takes to fill a single |
1670 | * row at the given clock rate, multiplied by 8. | |
1671 | * */ | |
fec8cba3 JB |
1672 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
1673 | mode->crtc_clock); | |
1674 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 1675 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 1676 | |
801bcfff PZ |
1677 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
1678 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
1679 | } |
1680 | ||
2af30a5c | 1681 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
1682 | { |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | ||
2af30a5c PB |
1685 | if (IS_GEN9(dev)) { |
1686 | uint32_t val; | |
4f947386 | 1687 | int ret, i; |
367294be | 1688 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
1689 | |
1690 | /* read the first set of memory latencies[0:3] */ | |
1691 | val = 0; /* data0 to be programmed to 0 for first set */ | |
1692 | mutex_lock(&dev_priv->rps.hw_lock); | |
1693 | ret = sandybridge_pcode_read(dev_priv, | |
1694 | GEN9_PCODE_READ_MEM_LATENCY, | |
1695 | &val); | |
1696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1697 | ||
1698 | if (ret) { | |
1699 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1700 | return; | |
1701 | } | |
1702 | ||
1703 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1704 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1705 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1706 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1707 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1708 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1709 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1710 | ||
1711 | /* read the second set of memory latencies[4:7] */ | |
1712 | val = 1; /* data0 to be programmed to 1 for second set */ | |
1713 | mutex_lock(&dev_priv->rps.hw_lock); | |
1714 | ret = sandybridge_pcode_read(dev_priv, | |
1715 | GEN9_PCODE_READ_MEM_LATENCY, | |
1716 | &val); | |
1717 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1718 | if (ret) { | |
1719 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1720 | return; | |
1721 | } | |
1722 | ||
1723 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1724 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1725 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1726 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1727 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1728 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1729 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1730 | ||
367294be | 1731 | /* |
6f97235b DL |
1732 | * WaWmMemoryReadLatency:skl |
1733 | * | |
367294be VK |
1734 | * punit doesn't take into account the read latency so we need |
1735 | * to add 2us to the various latency levels we retrieve from | |
1736 | * the punit. | |
1737 | * - W0 is a bit special in that it's the only level that | |
1738 | * can't be disabled if we want to have display working, so | |
1739 | * we always add 2us there. | |
1740 | * - For levels >=1, punit returns 0us latency when they are | |
1741 | * disabled, so we respect that and don't add 2us then | |
4f947386 VK |
1742 | * |
1743 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
1744 | * levels m (m >= n) need to be disabled. We make sure to | |
1745 | * sanitize the values out of the punit to satisfy this | |
1746 | * requirement. | |
367294be VK |
1747 | */ |
1748 | wm[0] += 2; | |
1749 | for (level = 1; level <= max_level; level++) | |
1750 | if (wm[level] != 0) | |
1751 | wm[level] += 2; | |
4f947386 VK |
1752 | else { |
1753 | for (i = level + 1; i <= max_level; i++) | |
1754 | wm[i] = 0; | |
367294be | 1755 | |
4f947386 VK |
1756 | break; |
1757 | } | |
2af30a5c | 1758 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
1759 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
1760 | ||
1761 | wm[0] = (sskpd >> 56) & 0xFF; | |
1762 | if (wm[0] == 0) | |
1763 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
1764 | wm[1] = (sskpd >> 4) & 0xFF; |
1765 | wm[2] = (sskpd >> 12) & 0xFF; | |
1766 | wm[3] = (sskpd >> 20) & 0x1FF; | |
1767 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
1768 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1769 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
1770 | ||
1771 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
1772 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
1773 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
1774 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
1775 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1776 | uint32_t mltr = I915_READ(MLTR_ILK); | |
1777 | ||
1778 | /* ILK primary LP0 latency is 700 ns */ | |
1779 | wm[0] = 7; | |
1780 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
1781 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
1782 | } |
1783 | } | |
1784 | ||
53615a5e VS |
1785 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
1786 | { | |
1787 | /* ILK sprite LP0 latency is 1300 ns */ | |
1788 | if (INTEL_INFO(dev)->gen == 5) | |
1789 | wm[0] = 13; | |
1790 | } | |
1791 | ||
1792 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
1793 | { | |
1794 | /* ILK cursor LP0 latency is 1300 ns */ | |
1795 | if (INTEL_INFO(dev)->gen == 5) | |
1796 | wm[0] = 13; | |
1797 | ||
1798 | /* WaDoubleCursorLP3Latency:ivb */ | |
1799 | if (IS_IVYBRIDGE(dev)) | |
1800 | wm[3] *= 2; | |
1801 | } | |
1802 | ||
546c81fd | 1803 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 1804 | { |
26ec971e | 1805 | /* how many WM levels are we expecting */ |
2af30a5c PB |
1806 | if (IS_GEN9(dev)) |
1807 | return 7; | |
1808 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 1809 | return 4; |
26ec971e | 1810 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 1811 | return 3; |
26ec971e | 1812 | else |
ad0d6dc4 VS |
1813 | return 2; |
1814 | } | |
7526ed79 | 1815 | |
ad0d6dc4 VS |
1816 | static void intel_print_wm_latency(struct drm_device *dev, |
1817 | const char *name, | |
2af30a5c | 1818 | const uint16_t wm[8]) |
ad0d6dc4 VS |
1819 | { |
1820 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
1821 | |
1822 | for (level = 0; level <= max_level; level++) { | |
1823 | unsigned int latency = wm[level]; | |
1824 | ||
1825 | if (latency == 0) { | |
1826 | DRM_ERROR("%s WM%d latency not provided\n", | |
1827 | name, level); | |
1828 | continue; | |
1829 | } | |
1830 | ||
2af30a5c PB |
1831 | /* |
1832 | * - latencies are in us on gen9. | |
1833 | * - before then, WM1+ latency values are in 0.5us units | |
1834 | */ | |
1835 | if (IS_GEN9(dev)) | |
1836 | latency *= 10; | |
1837 | else if (level > 0) | |
26ec971e VS |
1838 | latency *= 5; |
1839 | ||
1840 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
1841 | name, level, wm[level], | |
1842 | latency / 10, latency % 10); | |
1843 | } | |
1844 | } | |
1845 | ||
e95a2f75 VS |
1846 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
1847 | uint16_t wm[5], uint16_t min) | |
1848 | { | |
1849 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
1850 | ||
1851 | if (wm[0] >= min) | |
1852 | return false; | |
1853 | ||
1854 | wm[0] = max(wm[0], min); | |
1855 | for (level = 1; level <= max_level; level++) | |
1856 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
1857 | ||
1858 | return true; | |
1859 | } | |
1860 | ||
1861 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
1862 | { | |
1863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1864 | bool changed; | |
1865 | ||
1866 | /* | |
1867 | * The BIOS provided WM memory latency values are often | |
1868 | * inadequate for high resolution displays. Adjust them. | |
1869 | */ | |
1870 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
1871 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
1872 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
1873 | ||
1874 | if (!changed) | |
1875 | return; | |
1876 | ||
1877 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
1878 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
1879 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
1880 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
1881 | } | |
1882 | ||
fa50ad61 | 1883 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
1884 | { |
1885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1886 | ||
1887 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
1888 | ||
1889 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
1890 | sizeof(dev_priv->wm.pri_latency)); | |
1891 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
1892 | sizeof(dev_priv->wm.pri_latency)); | |
1893 | ||
1894 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
1895 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
1896 | |
1897 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
1898 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
1899 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
1900 | |
1901 | if (IS_GEN6(dev)) | |
1902 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
1903 | } |
1904 | ||
2af30a5c PB |
1905 | static void skl_setup_wm_latency(struct drm_device *dev) |
1906 | { | |
1907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1908 | ||
1909 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
1910 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
1911 | } | |
1912 | ||
820c1980 | 1913 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 1914 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 1915 | { |
7c4a395f VS |
1916 | struct drm_device *dev = crtc->dev; |
1917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1918 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 1919 | struct drm_plane *plane; |
1011d8c4 | 1920 | |
2a44b76b VS |
1921 | if (!intel_crtc_active(crtc)) |
1922 | return; | |
801bcfff | 1923 | |
2a44b76b | 1924 | p->active = true; |
6e3c9717 | 1925 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
2a44b76b VS |
1926 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
1927 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; | |
1928 | p->cur.bytes_per_pixel = 4; | |
6e3c9717 | 1929 | p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; |
2a44b76b VS |
1930 | p->cur.horiz_pixels = intel_crtc->cursor_width; |
1931 | /* TODO: for now, assume primary and cursor planes are always enabled. */ | |
1932 | p->pri.enabled = true; | |
1933 | p->cur.enabled = true; | |
7c4a395f | 1934 | |
af2b653b | 1935 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 1936 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 1937 | |
2a44b76b | 1938 | if (intel_plane->pipe == pipe) { |
7c4a395f | 1939 | p->spr = intel_plane->wm; |
2a44b76b VS |
1940 | break; |
1941 | } | |
1942 | } | |
1943 | } | |
1944 | ||
1945 | static void ilk_compute_wm_config(struct drm_device *dev, | |
1946 | struct intel_wm_config *config) | |
1947 | { | |
1948 | struct intel_crtc *intel_crtc; | |
1949 | ||
1950 | /* Compute the currently _active_ config */ | |
d3fcc808 | 1951 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 1952 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 1953 | |
2a44b76b VS |
1954 | if (!wm->pipe_enabled) |
1955 | continue; | |
cca32e9a | 1956 | |
2a44b76b VS |
1957 | config->sprites_enabled |= wm->sprites_enabled; |
1958 | config->sprites_scaled |= wm->sprites_scaled; | |
1959 | config->num_pipes_active++; | |
cca32e9a | 1960 | } |
801bcfff PZ |
1961 | } |
1962 | ||
0b2ae6d7 VS |
1963 | /* Compute new watermarks for the pipe */ |
1964 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 1965 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
1966 | struct intel_pipe_wm *pipe_wm) |
1967 | { | |
1968 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 1969 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
1970 | int level, max_level = ilk_wm_max_level(dev); |
1971 | /* LP0 watermark maximums depend on this pipe alone */ | |
1972 | struct intel_wm_config config = { | |
1973 | .num_pipes_active = 1, | |
1974 | .sprites_enabled = params->spr.enabled, | |
1975 | .sprites_scaled = params->spr.scaled, | |
1976 | }; | |
820c1980 | 1977 | struct ilk_wm_maximums max; |
0b2ae6d7 | 1978 | |
2a44b76b VS |
1979 | pipe_wm->pipe_enabled = params->active; |
1980 | pipe_wm->sprites_enabled = params->spr.enabled; | |
1981 | pipe_wm->sprites_scaled = params->spr.scaled; | |
1982 | ||
7b39a0b7 VS |
1983 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
1984 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
1985 | max_level = 1; | |
1986 | ||
1987 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
1988 | if (params->spr.scaled) | |
1989 | max_level = 0; | |
1990 | ||
a3cb4048 | 1991 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 1992 | |
a42a5719 | 1993 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 1994 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 1995 | |
a3cb4048 VS |
1996 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
1997 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
1998 | ||
0b2ae6d7 | 1999 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2000 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2001 | return false; | |
2002 | ||
2003 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2004 | ||
2005 | for (level = 1; level <= max_level; level++) { | |
2006 | struct intel_wm_level wm = {}; | |
2007 | ||
2008 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2009 | ||
2010 | /* | |
2011 | * Disable any watermark level that exceeds the | |
2012 | * register maximums since such watermarks are | |
2013 | * always invalid. | |
2014 | */ | |
2015 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2016 | break; | |
2017 | ||
2018 | pipe_wm->wm[level] = wm; | |
2019 | } | |
2020 | ||
2021 | return true; | |
0b2ae6d7 VS |
2022 | } |
2023 | ||
2024 | /* | |
2025 | * Merge the watermarks from all active pipes for a specific level. | |
2026 | */ | |
2027 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2028 | int level, | |
2029 | struct intel_wm_level *ret_wm) | |
2030 | { | |
2031 | const struct intel_crtc *intel_crtc; | |
2032 | ||
d52fea5b VS |
2033 | ret_wm->enable = true; |
2034 | ||
d3fcc808 | 2035 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2036 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2037 | const struct intel_wm_level *wm = &active->wm[level]; | |
2038 | ||
2039 | if (!active->pipe_enabled) | |
2040 | continue; | |
0b2ae6d7 | 2041 | |
d52fea5b VS |
2042 | /* |
2043 | * The watermark values may have been used in the past, | |
2044 | * so we must maintain them in the registers for some | |
2045 | * time even if the level is now disabled. | |
2046 | */ | |
0b2ae6d7 | 2047 | if (!wm->enable) |
d52fea5b | 2048 | ret_wm->enable = false; |
0b2ae6d7 VS |
2049 | |
2050 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2051 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2052 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2053 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2054 | } | |
0b2ae6d7 VS |
2055 | } |
2056 | ||
2057 | /* | |
2058 | * Merge all low power watermarks for all active pipes. | |
2059 | */ | |
2060 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2061 | const struct intel_wm_config *config, |
820c1980 | 2062 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2063 | struct intel_pipe_wm *merged) |
2064 | { | |
2065 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2066 | int last_enabled_level = max_level; |
0b2ae6d7 | 2067 | |
0ba22e26 VS |
2068 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2069 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2070 | config->num_pipes_active > 1) | |
2071 | return; | |
2072 | ||
6c8b6c28 VS |
2073 | /* ILK: FBC WM must be disabled always */ |
2074 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2075 | |
2076 | /* merge each WM1+ level */ | |
2077 | for (level = 1; level <= max_level; level++) { | |
2078 | struct intel_wm_level *wm = &merged->wm[level]; | |
2079 | ||
2080 | ilk_merge_wm_level(dev, level, wm); | |
2081 | ||
d52fea5b VS |
2082 | if (level > last_enabled_level) |
2083 | wm->enable = false; | |
2084 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2085 | /* make sure all following levels get disabled */ | |
2086 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2087 | |
2088 | /* | |
2089 | * The spec says it is preferred to disable | |
2090 | * FBC WMs instead of disabling a WM level. | |
2091 | */ | |
2092 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2093 | if (wm->enable) |
2094 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2095 | wm->fbc_val = 0; |
2096 | } | |
2097 | } | |
6c8b6c28 VS |
2098 | |
2099 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2100 | /* | |
2101 | * FIXME this is racy. FBC might get enabled later. | |
2102 | * What we should check here is whether FBC can be | |
2103 | * enabled sometime later. | |
2104 | */ | |
2105 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2106 | for (level = 2; level <= max_level; level++) { | |
2107 | struct intel_wm_level *wm = &merged->wm[level]; | |
2108 | ||
2109 | wm->enable = false; | |
2110 | } | |
2111 | } | |
0b2ae6d7 VS |
2112 | } |
2113 | ||
b380ca3c VS |
2114 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2115 | { | |
2116 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2117 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2118 | } | |
2119 | ||
a68d68ee VS |
2120 | /* The value we need to program into the WM_LPx latency field */ |
2121 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2122 | { | |
2123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2124 | ||
a42a5719 | 2125 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2126 | return 2 * level; |
2127 | else | |
2128 | return dev_priv->wm.pri_latency[level]; | |
2129 | } | |
2130 | ||
820c1980 | 2131 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2132 | const struct intel_pipe_wm *merged, |
609cedef | 2133 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2134 | struct ilk_wm_values *results) |
801bcfff | 2135 | { |
0b2ae6d7 VS |
2136 | struct intel_crtc *intel_crtc; |
2137 | int level, wm_lp; | |
cca32e9a | 2138 | |
0362c781 | 2139 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2140 | results->partitioning = partitioning; |
cca32e9a | 2141 | |
0b2ae6d7 | 2142 | /* LP1+ register values */ |
cca32e9a | 2143 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2144 | const struct intel_wm_level *r; |
801bcfff | 2145 | |
b380ca3c | 2146 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2147 | |
0362c781 | 2148 | r = &merged->wm[level]; |
cca32e9a | 2149 | |
d52fea5b VS |
2150 | /* |
2151 | * Maintain the watermark values even if the level is | |
2152 | * disabled. Doing otherwise could cause underruns. | |
2153 | */ | |
2154 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2155 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2156 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2157 | r->cur_val; | |
2158 | ||
d52fea5b VS |
2159 | if (r->enable) |
2160 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2161 | ||
416f4727 VS |
2162 | if (INTEL_INFO(dev)->gen >= 8) |
2163 | results->wm_lp[wm_lp - 1] |= | |
2164 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2165 | else | |
2166 | results->wm_lp[wm_lp - 1] |= | |
2167 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2168 | ||
d52fea5b VS |
2169 | /* |
2170 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2171 | * level is disabled. Doing otherwise could cause underruns. | |
2172 | */ | |
6cef2b8a VS |
2173 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2174 | WARN_ON(wm_lp != 1); | |
2175 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2176 | } else | |
2177 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2178 | } |
801bcfff | 2179 | |
0b2ae6d7 | 2180 | /* LP0 register values */ |
d3fcc808 | 2181 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2182 | enum pipe pipe = intel_crtc->pipe; |
2183 | const struct intel_wm_level *r = | |
2184 | &intel_crtc->wm.active.wm[0]; | |
2185 | ||
2186 | if (WARN_ON(!r->enable)) | |
2187 | continue; | |
2188 | ||
2189 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2190 | |
0b2ae6d7 VS |
2191 | results->wm_pipe[pipe] = |
2192 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2193 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2194 | r->cur_val; | |
801bcfff PZ |
2195 | } |
2196 | } | |
2197 | ||
861f3389 PZ |
2198 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2199 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2200 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2201 | struct intel_pipe_wm *r1, |
2202 | struct intel_pipe_wm *r2) | |
861f3389 | 2203 | { |
198a1e9b VS |
2204 | int level, max_level = ilk_wm_max_level(dev); |
2205 | int level1 = 0, level2 = 0; | |
861f3389 | 2206 | |
198a1e9b VS |
2207 | for (level = 1; level <= max_level; level++) { |
2208 | if (r1->wm[level].enable) | |
2209 | level1 = level; | |
2210 | if (r2->wm[level].enable) | |
2211 | level2 = level; | |
861f3389 PZ |
2212 | } |
2213 | ||
198a1e9b VS |
2214 | if (level1 == level2) { |
2215 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2216 | return r2; |
2217 | else | |
2218 | return r1; | |
198a1e9b | 2219 | } else if (level1 > level2) { |
861f3389 PZ |
2220 | return r1; |
2221 | } else { | |
2222 | return r2; | |
2223 | } | |
2224 | } | |
2225 | ||
49a687c4 VS |
2226 | /* dirty bits used to track which watermarks need changes */ |
2227 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2228 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2229 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2230 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2231 | #define WM_DIRTY_FBC (1 << 24) | |
2232 | #define WM_DIRTY_DDB (1 << 25) | |
2233 | ||
055e393f | 2234 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2235 | const struct ilk_wm_values *old, |
2236 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2237 | { |
2238 | unsigned int dirty = 0; | |
2239 | enum pipe pipe; | |
2240 | int wm_lp; | |
2241 | ||
055e393f | 2242 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2243 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2244 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2245 | /* Must disable LP1+ watermarks too */ | |
2246 | dirty |= WM_DIRTY_LP_ALL; | |
2247 | } | |
2248 | ||
2249 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2250 | dirty |= WM_DIRTY_PIPE(pipe); | |
2251 | /* Must disable LP1+ watermarks too */ | |
2252 | dirty |= WM_DIRTY_LP_ALL; | |
2253 | } | |
2254 | } | |
2255 | ||
2256 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2257 | dirty |= WM_DIRTY_FBC; | |
2258 | /* Must disable LP1+ watermarks too */ | |
2259 | dirty |= WM_DIRTY_LP_ALL; | |
2260 | } | |
2261 | ||
2262 | if (old->partitioning != new->partitioning) { | |
2263 | dirty |= WM_DIRTY_DDB; | |
2264 | /* Must disable LP1+ watermarks too */ | |
2265 | dirty |= WM_DIRTY_LP_ALL; | |
2266 | } | |
2267 | ||
2268 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2269 | if (dirty & WM_DIRTY_LP_ALL) | |
2270 | return dirty; | |
2271 | ||
2272 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2273 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2274 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2275 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2276 | break; | |
2277 | } | |
2278 | ||
2279 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2280 | for (; wm_lp <= 3; wm_lp++) | |
2281 | dirty |= WM_DIRTY_LP(wm_lp); | |
2282 | ||
2283 | return dirty; | |
2284 | } | |
2285 | ||
8553c18e VS |
2286 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2287 | unsigned int dirty) | |
801bcfff | 2288 | { |
820c1980 | 2289 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2290 | bool changed = false; |
801bcfff | 2291 | |
facd619b VS |
2292 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2293 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2294 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2295 | changed = true; |
facd619b VS |
2296 | } |
2297 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2298 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2299 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2300 | changed = true; |
facd619b VS |
2301 | } |
2302 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2303 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2304 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2305 | changed = true; |
facd619b | 2306 | } |
801bcfff | 2307 | |
facd619b VS |
2308 | /* |
2309 | * Don't touch WM1S_LP_EN here. | |
2310 | * Doing so could cause underruns. | |
2311 | */ | |
6cef2b8a | 2312 | |
8553c18e VS |
2313 | return changed; |
2314 | } | |
2315 | ||
2316 | /* | |
2317 | * The spec says we shouldn't write when we don't need, because every write | |
2318 | * causes WMs to be re-evaluated, expending some power. | |
2319 | */ | |
820c1980 ID |
2320 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2321 | struct ilk_wm_values *results) | |
8553c18e VS |
2322 | { |
2323 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2324 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2325 | unsigned int dirty; |
2326 | uint32_t val; | |
2327 | ||
055e393f | 2328 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2329 | if (!dirty) |
2330 | return; | |
2331 | ||
2332 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2333 | ||
49a687c4 | 2334 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2335 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2336 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2337 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2338 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2339 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2340 | ||
49a687c4 | 2341 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2342 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2343 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2344 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2345 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2346 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2347 | ||
49a687c4 | 2348 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2349 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2350 | val = I915_READ(WM_MISC); |
2351 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2352 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2353 | else | |
2354 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2355 | I915_WRITE(WM_MISC, val); | |
2356 | } else { | |
2357 | val = I915_READ(DISP_ARB_CTL2); | |
2358 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2359 | val &= ~DISP_DATA_PARTITION_5_6; | |
2360 | else | |
2361 | val |= DISP_DATA_PARTITION_5_6; | |
2362 | I915_WRITE(DISP_ARB_CTL2, val); | |
2363 | } | |
1011d8c4 PZ |
2364 | } |
2365 | ||
49a687c4 | 2366 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2367 | val = I915_READ(DISP_ARB_CTL); |
2368 | if (results->enable_fbc_wm) | |
2369 | val &= ~DISP_FBC_WM_DIS; | |
2370 | else | |
2371 | val |= DISP_FBC_WM_DIS; | |
2372 | I915_WRITE(DISP_ARB_CTL, val); | |
2373 | } | |
2374 | ||
954911eb ID |
2375 | if (dirty & WM_DIRTY_LP(1) && |
2376 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2377 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2378 | ||
2379 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2380 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2381 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2382 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2383 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2384 | } | |
801bcfff | 2385 | |
facd619b | 2386 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2387 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2388 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2389 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2390 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2391 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2392 | |
2393 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2394 | } |
2395 | ||
8553c18e VS |
2396 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2397 | { | |
2398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2399 | ||
2400 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2401 | } | |
2402 | ||
b9cec075 DL |
2403 | /* |
2404 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2405 | * different active planes. | |
2406 | */ | |
2407 | ||
2408 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
2409 | ||
2410 | static void | |
2411 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
2412 | struct drm_crtc *for_crtc, | |
2413 | const struct intel_wm_config *config, | |
2414 | const struct skl_pipe_wm_parameters *params, | |
2415 | struct skl_ddb_entry *alloc /* out */) | |
2416 | { | |
2417 | struct drm_crtc *crtc; | |
2418 | unsigned int pipe_size, ddb_size; | |
2419 | int nth_active_pipe; | |
2420 | ||
2421 | if (!params->active) { | |
2422 | alloc->start = 0; | |
2423 | alloc->end = 0; | |
2424 | return; | |
2425 | } | |
2426 | ||
2427 | ddb_size = SKL_DDB_SIZE; | |
2428 | ||
2429 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2430 | ||
2431 | nth_active_pipe = 0; | |
2432 | for_each_crtc(dev, crtc) { | |
2433 | if (!intel_crtc_active(crtc)) | |
2434 | continue; | |
2435 | ||
2436 | if (crtc == for_crtc) | |
2437 | break; | |
2438 | ||
2439 | nth_active_pipe++; | |
2440 | } | |
2441 | ||
2442 | pipe_size = ddb_size / config->num_pipes_active; | |
2443 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
16160e3d | 2444 | alloc->end = alloc->start + pipe_size; |
b9cec075 DL |
2445 | } |
2446 | ||
2447 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2448 | { | |
2449 | if (config->num_pipes_active == 1) | |
2450 | return 32; | |
2451 | ||
2452 | return 8; | |
2453 | } | |
2454 | ||
a269c583 DL |
2455 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2456 | { | |
2457 | entry->start = reg & 0x3ff; | |
2458 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
2459 | if (entry->end) |
2460 | entry->end += 1; | |
a269c583 DL |
2461 | } |
2462 | ||
08db6652 DL |
2463 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2464 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 DL |
2465 | { |
2466 | struct drm_device *dev = dev_priv->dev; | |
2467 | enum pipe pipe; | |
2468 | int plane; | |
2469 | u32 val; | |
2470 | ||
2471 | for_each_pipe(dev_priv, pipe) { | |
2472 | for_each_plane(pipe, plane) { | |
2473 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); | |
2474 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2475 | val); | |
2476 | } | |
2477 | ||
2478 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
2479 | skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); | |
2480 | } | |
2481 | } | |
2482 | ||
b9cec075 DL |
2483 | static unsigned int |
2484 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) | |
2485 | { | |
2486 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; | |
2487 | } | |
2488 | ||
2489 | /* | |
2490 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2491 | * a 8192x4096@32bpp framebuffer: | |
2492 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2493 | */ | |
2494 | static unsigned int | |
2495 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, | |
2496 | const struct skl_pipe_wm_parameters *params) | |
2497 | { | |
2498 | unsigned int total_data_rate = 0; | |
2499 | int plane; | |
2500 | ||
2501 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
2502 | const struct intel_plane_wm_parameters *p; | |
2503 | ||
2504 | p = ¶ms->plane[plane]; | |
2505 | if (!p->enabled) | |
2506 | continue; | |
2507 | ||
2508 | total_data_rate += skl_plane_relative_data_rate(p); | |
2509 | } | |
2510 | ||
2511 | return total_data_rate; | |
2512 | } | |
2513 | ||
2514 | static void | |
2515 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, | |
2516 | const struct intel_wm_config *config, | |
2517 | const struct skl_pipe_wm_parameters *params, | |
2518 | struct skl_ddb_allocation *ddb /* out */) | |
2519 | { | |
2520 | struct drm_device *dev = crtc->dev; | |
2521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2522 | enum pipe pipe = intel_crtc->pipe; | |
34bb56af | 2523 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
b9cec075 | 2524 | uint16_t alloc_size, start, cursor_blocks; |
80958155 | 2525 | uint16_t minimum[I915_MAX_PLANES]; |
b9cec075 DL |
2526 | unsigned int total_data_rate; |
2527 | int plane; | |
2528 | ||
34bb56af DL |
2529 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
2530 | alloc_size = skl_ddb_entry_size(alloc); | |
b9cec075 DL |
2531 | if (alloc_size == 0) { |
2532 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
2533 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); | |
2534 | return; | |
2535 | } | |
2536 | ||
2537 | cursor_blocks = skl_cursor_allocation(config); | |
34bb56af DL |
2538 | ddb->cursor[pipe].start = alloc->end - cursor_blocks; |
2539 | ddb->cursor[pipe].end = alloc->end; | |
b9cec075 DL |
2540 | |
2541 | alloc_size -= cursor_blocks; | |
34bb56af | 2542 | alloc->end -= cursor_blocks; |
b9cec075 | 2543 | |
80958155 DL |
2544 | /* 1. Allocate the mininum required blocks for each active plane */ |
2545 | for_each_plane(pipe, plane) { | |
2546 | const struct intel_plane_wm_parameters *p; | |
2547 | ||
2548 | p = ¶ms->plane[plane]; | |
2549 | if (!p->enabled) | |
2550 | continue; | |
2551 | ||
2552 | minimum[plane] = 8; | |
2553 | alloc_size -= minimum[plane]; | |
2554 | } | |
2555 | ||
b9cec075 | 2556 | /* |
80958155 DL |
2557 | * 2. Distribute the remaining space in proportion to the amount of |
2558 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
2559 | * |
2560 | * FIXME: we may not allocate every single block here. | |
2561 | */ | |
2562 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); | |
2563 | ||
34bb56af | 2564 | start = alloc->start; |
b9cec075 DL |
2565 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2566 | const struct intel_plane_wm_parameters *p; | |
2567 | unsigned int data_rate; | |
2568 | uint16_t plane_blocks; | |
2569 | ||
2570 | p = ¶ms->plane[plane]; | |
2571 | if (!p->enabled) | |
2572 | continue; | |
2573 | ||
2574 | data_rate = skl_plane_relative_data_rate(p); | |
2575 | ||
2576 | /* | |
2577 | * promote the expression to 64 bits to avoid overflowing, the | |
2578 | * result is < available as data_rate / total_data_rate < 1 | |
2579 | */ | |
80958155 DL |
2580 | plane_blocks = minimum[plane]; |
2581 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, | |
2582 | total_data_rate); | |
b9cec075 DL |
2583 | |
2584 | ddb->plane[pipe][plane].start = start; | |
16160e3d | 2585 | ddb->plane[pipe][plane].end = start + plane_blocks; |
b9cec075 DL |
2586 | |
2587 | start += plane_blocks; | |
2588 | } | |
2589 | ||
2590 | } | |
2591 | ||
5cec258b | 2592 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2d41c0b5 PB |
2593 | { |
2594 | /* TODO: Take into account the scalers once we support them */ | |
2d112de7 | 2595 | return config->base.adjusted_mode.crtc_clock; |
2d41c0b5 PB |
2596 | } |
2597 | ||
2598 | /* | |
2599 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
2600 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
2601 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
2602 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
2603 | */ | |
2604 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
2605 | uint32_t latency) | |
2606 | { | |
2607 | uint32_t wm_intermediate_val, ret; | |
2608 | ||
2609 | if (latency == 0) | |
2610 | return UINT_MAX; | |
2611 | ||
d4c2aa60 | 2612 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
2d41c0b5 PB |
2613 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
2614 | ||
2615 | return ret; | |
2616 | } | |
2617 | ||
2618 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
2619 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
2620 | uint32_t latency) | |
2621 | { | |
d4c2aa60 TU |
2622 | uint32_t ret; |
2623 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2624 | uint32_t wm_intermediate_val; | |
2d41c0b5 PB |
2625 | |
2626 | if (latency == 0) | |
2627 | return UINT_MAX; | |
2628 | ||
2629 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
d4c2aa60 | 2630 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 PB |
2631 | wm_intermediate_val = latency * pixel_rate; |
2632 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
d4c2aa60 | 2633 | plane_blocks_per_line; |
2d41c0b5 PB |
2634 | |
2635 | return ret; | |
2636 | } | |
2637 | ||
2d41c0b5 PB |
2638 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
2639 | const struct intel_crtc *intel_crtc) | |
2640 | { | |
2641 | struct drm_device *dev = intel_crtc->base.dev; | |
2642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2643 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
2644 | enum pipe pipe = intel_crtc->pipe; | |
2645 | ||
2646 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
2647 | sizeof(new_ddb->plane[pipe]))) | |
2648 | return true; | |
2649 | ||
2650 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], | |
2651 | sizeof(new_ddb->cursor[pipe]))) | |
2652 | return true; | |
2653 | ||
2654 | return false; | |
2655 | } | |
2656 | ||
2657 | static void skl_compute_wm_global_parameters(struct drm_device *dev, | |
2658 | struct intel_wm_config *config) | |
2659 | { | |
2660 | struct drm_crtc *crtc; | |
2661 | struct drm_plane *plane; | |
2662 | ||
2663 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
2664 | config->num_pipes_active += intel_crtc_active(crtc); | |
2665 | ||
2666 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
2667 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2668 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2669 | ||
2670 | config->sprites_enabled |= intel_plane->wm.enabled; | |
2671 | config->sprites_scaled |= intel_plane->wm.scaled; | |
2672 | } | |
2673 | } | |
2674 | ||
2675 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
2676 | struct skl_pipe_wm_parameters *p) | |
2677 | { | |
2678 | struct drm_device *dev = crtc->dev; | |
2679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2680 | enum pipe pipe = intel_crtc->pipe; | |
2681 | struct drm_plane *plane; | |
2682 | int i = 1; /* Index for sprite planes start */ | |
2683 | ||
2684 | p->active = intel_crtc_active(crtc); | |
2685 | if (p->active) { | |
6e3c9717 ACO |
2686 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
2687 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); | |
2d41c0b5 PB |
2688 | |
2689 | /* | |
2690 | * For now, assume primary and cursor planes are always enabled. | |
2691 | */ | |
2692 | p->plane[0].enabled = true; | |
2693 | p->plane[0].bytes_per_pixel = | |
2694 | crtc->primary->fb->bits_per_pixel / 8; | |
6e3c9717 ACO |
2695 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; |
2696 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; | |
2d41c0b5 PB |
2697 | |
2698 | p->cursor.enabled = true; | |
2699 | p->cursor.bytes_per_pixel = 4; | |
2700 | p->cursor.horiz_pixels = intel_crtc->cursor_width ? | |
2701 | intel_crtc->cursor_width : 64; | |
2702 | } | |
2703 | ||
2704 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2705 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2706 | ||
a712f8eb SJ |
2707 | if (intel_plane->pipe == pipe && |
2708 | plane->type == DRM_PLANE_TYPE_OVERLAY) | |
2d41c0b5 PB |
2709 | p->plane[i++] = intel_plane->wm; |
2710 | } | |
2711 | } | |
2712 | ||
d4c2aa60 TU |
2713 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
2714 | struct skl_pipe_wm_parameters *p, | |
afb024aa DL |
2715 | struct intel_plane_wm_parameters *p_params, |
2716 | uint16_t ddb_allocation, | |
d4c2aa60 | 2717 | int level, |
afb024aa DL |
2718 | uint16_t *out_blocks, /* out */ |
2719 | uint8_t *out_lines /* out */) | |
2d41c0b5 | 2720 | { |
d4c2aa60 TU |
2721 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
2722 | uint32_t method1, method2; | |
2723 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2724 | uint32_t res_blocks, res_lines; | |
2725 | uint32_t selected_result; | |
2d41c0b5 | 2726 | |
d4c2aa60 | 2727 | if (latency == 0 || !p->active || !p_params->enabled) |
2d41c0b5 PB |
2728 | return false; |
2729 | ||
2730 | method1 = skl_wm_method1(p->pixel_rate, | |
2731 | p_params->bytes_per_pixel, | |
d4c2aa60 | 2732 | latency); |
2d41c0b5 PB |
2733 | method2 = skl_wm_method2(p->pixel_rate, |
2734 | p->pipe_htotal, | |
2735 | p_params->horiz_pixels, | |
2736 | p_params->bytes_per_pixel, | |
d4c2aa60 | 2737 | latency); |
2d41c0b5 PB |
2738 | |
2739 | plane_bytes_per_line = p_params->horiz_pixels * | |
2740 | p_params->bytes_per_pixel; | |
d4c2aa60 | 2741 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 PB |
2742 | |
2743 | /* For now xtile and linear */ | |
d4c2aa60 TU |
2744 | if ((ddb_allocation / plane_blocks_per_line) >= 1) |
2745 | selected_result = min(method1, method2); | |
2d41c0b5 | 2746 | else |
d4c2aa60 TU |
2747 | selected_result = method1; |
2748 | ||
2749 | res_blocks = selected_result + 1; | |
2750 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); | |
2d41c0b5 | 2751 | |
d4c2aa60 TU |
2752 | if (level >= 1 && level <= 7) |
2753 | res_blocks++; | |
e6d66171 | 2754 | |
d4c2aa60 | 2755 | if (res_blocks >= ddb_allocation || res_lines > 31) |
e6d66171 DL |
2756 | return false; |
2757 | ||
2758 | *out_blocks = res_blocks; | |
2759 | *out_lines = res_lines; | |
2d41c0b5 PB |
2760 | |
2761 | return true; | |
2762 | } | |
2763 | ||
2764 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
2765 | struct skl_ddb_allocation *ddb, | |
2766 | struct skl_pipe_wm_parameters *p, | |
2767 | enum pipe pipe, | |
2768 | int level, | |
2769 | int num_planes, | |
2770 | struct skl_wm_level *result) | |
2771 | { | |
2d41c0b5 PB |
2772 | uint16_t ddb_blocks; |
2773 | int i; | |
2774 | ||
2775 | for (i = 0; i < num_planes; i++) { | |
2776 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); | |
2777 | ||
d4c2aa60 TU |
2778 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
2779 | p, &p->plane[i], | |
2d41c0b5 | 2780 | ddb_blocks, |
d4c2aa60 | 2781 | level, |
2d41c0b5 PB |
2782 | &result->plane_res_b[i], |
2783 | &result->plane_res_l[i]); | |
2784 | } | |
2785 | ||
2786 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); | |
d4c2aa60 TU |
2787 | result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor, |
2788 | ddb_blocks, level, | |
2789 | &result->cursor_res_b, | |
2d41c0b5 PB |
2790 | &result->cursor_res_l); |
2791 | } | |
2792 | ||
407b50f3 DL |
2793 | static uint32_t |
2794 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) | |
2795 | { | |
2796 | if (!intel_crtc_active(crtc)) | |
2797 | return 0; | |
2798 | ||
2799 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); | |
2800 | ||
2801 | } | |
2802 | ||
2803 | static void skl_compute_transition_wm(struct drm_crtc *crtc, | |
2804 | struct skl_pipe_wm_parameters *params, | |
9414f563 | 2805 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 2806 | { |
9414f563 DL |
2807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2808 | int i; | |
2809 | ||
407b50f3 DL |
2810 | if (!params->active) |
2811 | return; | |
9414f563 DL |
2812 | |
2813 | /* Until we know more, just disable transition WMs */ | |
2814 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
2815 | trans_wm->plane_en[i] = false; | |
2816 | trans_wm->cursor_en = false; | |
407b50f3 DL |
2817 | } |
2818 | ||
2d41c0b5 PB |
2819 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
2820 | struct skl_ddb_allocation *ddb, | |
2821 | struct skl_pipe_wm_parameters *params, | |
2822 | struct skl_pipe_wm *pipe_wm) | |
2823 | { | |
2824 | struct drm_device *dev = crtc->dev; | |
2825 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
2826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2827 | int level, max_level = ilk_wm_max_level(dev); | |
2828 | ||
2829 | for (level = 0; level <= max_level; level++) { | |
2830 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, | |
2831 | level, intel_num_planes(intel_crtc), | |
2832 | &pipe_wm->wm[level]); | |
2833 | } | |
2834 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); | |
2835 | ||
9414f563 | 2836 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
2d41c0b5 PB |
2837 | } |
2838 | ||
2839 | static void skl_compute_wm_results(struct drm_device *dev, | |
2840 | struct skl_pipe_wm_parameters *p, | |
2841 | struct skl_pipe_wm *p_wm, | |
2842 | struct skl_wm_values *r, | |
2843 | struct intel_crtc *intel_crtc) | |
2844 | { | |
2845 | int level, max_level = ilk_wm_max_level(dev); | |
2846 | enum pipe pipe = intel_crtc->pipe; | |
9414f563 DL |
2847 | uint32_t temp; |
2848 | int i; | |
2d41c0b5 PB |
2849 | |
2850 | for (level = 0; level <= max_level; level++) { | |
2d41c0b5 PB |
2851 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
2852 | temp = 0; | |
2d41c0b5 PB |
2853 | |
2854 | temp |= p_wm->wm[level].plane_res_l[i] << | |
2855 | PLANE_WM_LINES_SHIFT; | |
2856 | temp |= p_wm->wm[level].plane_res_b[i]; | |
2857 | if (p_wm->wm[level].plane_en[i]) | |
2858 | temp |= PLANE_WM_EN; | |
2859 | ||
2860 | r->plane[pipe][i][level] = temp; | |
2d41c0b5 PB |
2861 | } |
2862 | ||
2863 | temp = 0; | |
2d41c0b5 PB |
2864 | |
2865 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; | |
2866 | temp |= p_wm->wm[level].cursor_res_b; | |
2867 | ||
2868 | if (p_wm->wm[level].cursor_en) | |
2869 | temp |= PLANE_WM_EN; | |
2870 | ||
2871 | r->cursor[pipe][level] = temp; | |
2d41c0b5 PB |
2872 | |
2873 | } | |
2874 | ||
9414f563 DL |
2875 | /* transition WMs */ |
2876 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
2877 | temp = 0; | |
2878 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
2879 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
2880 | if (p_wm->trans_wm.plane_en[i]) | |
2881 | temp |= PLANE_WM_EN; | |
2882 | ||
2883 | r->plane_trans[pipe][i] = temp; | |
2884 | } | |
2885 | ||
2886 | temp = 0; | |
2887 | temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; | |
2888 | temp |= p_wm->trans_wm.cursor_res_b; | |
2889 | if (p_wm->trans_wm.cursor_en) | |
2890 | temp |= PLANE_WM_EN; | |
2891 | ||
2892 | r->cursor_trans[pipe] = temp; | |
2893 | ||
2d41c0b5 PB |
2894 | r->wm_linetime[pipe] = p_wm->linetime; |
2895 | } | |
2896 | ||
16160e3d DL |
2897 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
2898 | const struct skl_ddb_entry *entry) | |
2899 | { | |
2900 | if (entry->end) | |
2901 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
2902 | else | |
2903 | I915_WRITE(reg, 0); | |
2904 | } | |
2905 | ||
2d41c0b5 PB |
2906 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
2907 | const struct skl_wm_values *new) | |
2908 | { | |
2909 | struct drm_device *dev = dev_priv->dev; | |
2910 | struct intel_crtc *crtc; | |
2911 | ||
2912 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
2913 | int i, level, max_level = ilk_wm_max_level(dev); | |
2914 | enum pipe pipe = crtc->pipe; | |
2915 | ||
5d374d96 DL |
2916 | if (!new->dirty[pipe]) |
2917 | continue; | |
8211bd5b | 2918 | |
5d374d96 | 2919 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
8211bd5b | 2920 | |
5d374d96 DL |
2921 | for (level = 0; level <= max_level; level++) { |
2922 | for (i = 0; i < intel_num_planes(crtc); i++) | |
2923 | I915_WRITE(PLANE_WM(pipe, i, level), | |
2924 | new->plane[pipe][i][level]); | |
2925 | I915_WRITE(CUR_WM(pipe, level), | |
2926 | new->cursor[pipe][level]); | |
2d41c0b5 | 2927 | } |
5d374d96 DL |
2928 | for (i = 0; i < intel_num_planes(crtc); i++) |
2929 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
2930 | new->plane_trans[pipe][i]); | |
2931 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); | |
2932 | ||
2933 | for (i = 0; i < intel_num_planes(crtc); i++) | |
2934 | skl_ddb_entry_write(dev_priv, | |
2935 | PLANE_BUF_CFG(pipe, i), | |
2936 | &new->ddb.plane[pipe][i]); | |
2937 | ||
2938 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
2939 | &new->ddb.cursor[pipe]); | |
2d41c0b5 | 2940 | } |
2d41c0b5 PB |
2941 | } |
2942 | ||
0e8fb7ba DL |
2943 | /* |
2944 | * When setting up a new DDB allocation arrangement, we need to correctly | |
2945 | * sequence the times at which the new allocations for the pipes are taken into | |
2946 | * account or we'll have pipes fetching from space previously allocated to | |
2947 | * another pipe. | |
2948 | * | |
2949 | * Roughly the sequence looks like: | |
2950 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
2951 | * overlapping with a previous light-up pipe (another way to put it is: | |
2952 | * pipes with their new allocation strickly included into their old ones). | |
2953 | * 2. re-allocate the other pipes that get their allocation reduced | |
2954 | * 3. allocate the pipes having their allocation increased | |
2955 | * | |
2956 | * Steps 1. and 2. are here to take care of the following case: | |
2957 | * - Initially DDB looks like this: | |
2958 | * | B | C | | |
2959 | * - enable pipe A. | |
2960 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
2961 | * allocation | |
2962 | * | A | B | C | | |
2963 | * | |
2964 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
2965 | */ | |
2966 | ||
d21b795c DL |
2967 | static void |
2968 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
0e8fb7ba DL |
2969 | { |
2970 | struct drm_device *dev = dev_priv->dev; | |
2971 | int plane; | |
2972 | ||
d21b795c DL |
2973 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
2974 | ||
0e8fb7ba DL |
2975 | for_each_plane(pipe, plane) { |
2976 | I915_WRITE(PLANE_SURF(pipe, plane), | |
2977 | I915_READ(PLANE_SURF(pipe, plane))); | |
2978 | } | |
2979 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
2980 | } | |
2981 | ||
2982 | static bool | |
2983 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
2984 | const struct skl_ddb_allocation *new, | |
2985 | enum pipe pipe) | |
2986 | { | |
2987 | uint16_t old_size, new_size; | |
2988 | ||
2989 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
2990 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
2991 | ||
2992 | return old_size != new_size && | |
2993 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
2994 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
2995 | } | |
2996 | ||
2997 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
2998 | struct skl_wm_values *new_values) | |
2999 | { | |
3000 | struct drm_device *dev = dev_priv->dev; | |
3001 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
3002 | bool reallocated[I915_MAX_PIPES] = {false, false, false}; | |
3003 | struct intel_crtc *crtc; | |
3004 | enum pipe pipe; | |
3005 | ||
3006 | new_ddb = &new_values->ddb; | |
3007 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3008 | ||
3009 | /* | |
3010 | * First pass: flush the pipes with the new allocation contained into | |
3011 | * the old space. | |
3012 | * | |
3013 | * We'll wait for the vblank on those pipes to ensure we can safely | |
3014 | * re-allocate the freed space without this pipe fetching from it. | |
3015 | */ | |
3016 | for_each_intel_crtc(dev, crtc) { | |
3017 | if (!crtc->active) | |
3018 | continue; | |
3019 | ||
3020 | pipe = crtc->pipe; | |
3021 | ||
3022 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
3023 | continue; | |
3024 | ||
d21b795c | 3025 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
0e8fb7ba DL |
3026 | intel_wait_for_vblank(dev, pipe); |
3027 | ||
3028 | reallocated[pipe] = true; | |
3029 | } | |
3030 | ||
3031 | ||
3032 | /* | |
3033 | * Second pass: flush the pipes that are having their allocation | |
3034 | * reduced, but overlapping with a previous allocation. | |
3035 | * | |
3036 | * Here as well we need to wait for the vblank to make sure the freed | |
3037 | * space is not used anymore. | |
3038 | */ | |
3039 | for_each_intel_crtc(dev, crtc) { | |
3040 | if (!crtc->active) | |
3041 | continue; | |
3042 | ||
3043 | pipe = crtc->pipe; | |
3044 | ||
3045 | if (reallocated[pipe]) | |
3046 | continue; | |
3047 | ||
3048 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3049 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
d21b795c | 3050 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
0e8fb7ba | 3051 | intel_wait_for_vblank(dev, pipe); |
d9d8e6b3 | 3052 | reallocated[pipe] = true; |
0e8fb7ba | 3053 | } |
0e8fb7ba DL |
3054 | } |
3055 | ||
3056 | /* | |
3057 | * Third pass: flush the pipes that got more space allocated. | |
3058 | * | |
3059 | * We don't need to actively wait for the update here, next vblank | |
3060 | * will just get more DDB space with the correct WM values. | |
3061 | */ | |
3062 | for_each_intel_crtc(dev, crtc) { | |
3063 | if (!crtc->active) | |
3064 | continue; | |
3065 | ||
3066 | pipe = crtc->pipe; | |
3067 | ||
3068 | /* | |
3069 | * At this point, only the pipes more space than before are | |
3070 | * left to re-allocate. | |
3071 | */ | |
3072 | if (reallocated[pipe]) | |
3073 | continue; | |
3074 | ||
d21b795c | 3075 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
0e8fb7ba DL |
3076 | } |
3077 | } | |
3078 | ||
2d41c0b5 PB |
3079 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
3080 | struct skl_pipe_wm_parameters *params, | |
3081 | struct intel_wm_config *config, | |
3082 | struct skl_ddb_allocation *ddb, /* out */ | |
3083 | struct skl_pipe_wm *pipe_wm /* out */) | |
3084 | { | |
3085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3086 | ||
3087 | skl_compute_wm_pipe_parameters(crtc, params); | |
b9cec075 | 3088 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
2d41c0b5 PB |
3089 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
3090 | ||
3091 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) | |
3092 | return false; | |
3093 | ||
3094 | intel_crtc->wm.skl_active = *pipe_wm; | |
3095 | return true; | |
3096 | } | |
3097 | ||
3098 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3099 | struct drm_crtc *crtc, | |
3100 | struct intel_wm_config *config, | |
3101 | struct skl_wm_values *r) | |
3102 | { | |
3103 | struct intel_crtc *intel_crtc; | |
3104 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3105 | ||
3106 | /* | |
3107 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3108 | * crtc we are currently computing the new WM values for), other | |
3109 | * enabled crtcs will keep the same allocation and we don't need to | |
3110 | * recompute anything for them. | |
3111 | */ | |
3112 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3113 | return; | |
3114 | ||
3115 | /* | |
3116 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3117 | * other active pipes need new DDB allocation and WM values. | |
3118 | */ | |
3119 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3120 | base.head) { | |
3121 | struct skl_pipe_wm_parameters params = {}; | |
3122 | struct skl_pipe_wm pipe_wm = {}; | |
3123 | bool wm_changed; | |
3124 | ||
3125 | if (this_crtc->pipe == intel_crtc->pipe) | |
3126 | continue; | |
3127 | ||
3128 | if (!intel_crtc->active) | |
3129 | continue; | |
3130 | ||
3131 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, | |
3132 | ¶ms, config, | |
3133 | &r->ddb, &pipe_wm); | |
3134 | ||
3135 | /* | |
3136 | * If we end up re-computing the other pipe WM values, it's | |
3137 | * because it was really needed, so we expect the WM values to | |
3138 | * be different. | |
3139 | */ | |
3140 | WARN_ON(!wm_changed); | |
3141 | ||
3142 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); | |
3143 | r->dirty[intel_crtc->pipe] = true; | |
3144 | } | |
3145 | } | |
3146 | ||
3147 | static void skl_update_wm(struct drm_crtc *crtc) | |
3148 | { | |
3149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3150 | struct drm_device *dev = crtc->dev; | |
3151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3152 | struct skl_pipe_wm_parameters params = {}; | |
3153 | struct skl_wm_values *results = &dev_priv->wm.skl_results; | |
3154 | struct skl_pipe_wm pipe_wm = {}; | |
3155 | struct intel_wm_config config = {}; | |
3156 | ||
3157 | memset(results, 0, sizeof(*results)); | |
3158 | ||
3159 | skl_compute_wm_global_parameters(dev, &config); | |
3160 | ||
3161 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, | |
3162 | &results->ddb, &pipe_wm)) | |
3163 | return; | |
3164 | ||
3165 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); | |
3166 | results->dirty[intel_crtc->pipe] = true; | |
3167 | ||
3168 | skl_update_other_pipe_wm(dev, crtc, &config, results); | |
3169 | skl_write_wm_values(dev_priv, results); | |
0e8fb7ba | 3170 | skl_flush_wm_values(dev_priv, results); |
53b0deb4 DL |
3171 | |
3172 | /* store the new configuration */ | |
3173 | dev_priv->wm.skl_hw = *results; | |
2d41c0b5 PB |
3174 | } |
3175 | ||
3176 | static void | |
3177 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3178 | uint32_t sprite_width, uint32_t sprite_height, | |
3179 | int pixel_size, bool enabled, bool scaled) | |
3180 | { | |
3181 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3182 | ||
3183 | intel_plane->wm.enabled = enabled; | |
3184 | intel_plane->wm.scaled = scaled; | |
3185 | intel_plane->wm.horiz_pixels = sprite_width; | |
3186 | intel_plane->wm.vert_pixels = sprite_height; | |
3187 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
3188 | ||
3189 | skl_update_wm(crtc); | |
3190 | } | |
3191 | ||
820c1980 | 3192 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 3193 | { |
7c4a395f | 3194 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 3195 | struct drm_device *dev = crtc->dev; |
801bcfff | 3196 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
3197 | struct ilk_wm_maximums max; |
3198 | struct ilk_pipe_wm_parameters params = {}; | |
3199 | struct ilk_wm_values results = {}; | |
77c122bc | 3200 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 3201 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 3202 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 3203 | struct intel_wm_config config = {}; |
7c4a395f | 3204 | |
2a44b76b | 3205 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
3206 | |
3207 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
3208 | ||
3209 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3210 | return; | |
861f3389 | 3211 | |
7c4a395f | 3212 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 3213 | |
2a44b76b VS |
3214 | ilk_compute_wm_config(dev, &config); |
3215 | ||
34982fe1 | 3216 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 3217 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
3218 | |
3219 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
3220 | if (INTEL_INFO(dev)->gen >= 7 && |
3221 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 3222 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 3223 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 3224 | |
820c1980 | 3225 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3226 | } else { |
198a1e9b | 3227 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3228 | } |
3229 | ||
198a1e9b | 3230 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3231 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3232 | |
820c1980 | 3233 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3234 | |
820c1980 | 3235 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3236 | } |
3237 | ||
ed57cb8a DL |
3238 | static void |
3239 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3240 | struct drm_crtc *crtc, | |
3241 | uint32_t sprite_width, uint32_t sprite_height, | |
3242 | int pixel_size, bool enabled, bool scaled) | |
526682e9 | 3243 | { |
8553c18e | 3244 | struct drm_device *dev = plane->dev; |
adf3d35e | 3245 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 3246 | |
adf3d35e VS |
3247 | intel_plane->wm.enabled = enabled; |
3248 | intel_plane->wm.scaled = scaled; | |
3249 | intel_plane->wm.horiz_pixels = sprite_width; | |
ed57cb8a | 3250 | intel_plane->wm.vert_pixels = sprite_width; |
adf3d35e | 3251 | intel_plane->wm.bytes_per_pixel = pixel_size; |
526682e9 | 3252 | |
8553c18e VS |
3253 | /* |
3254 | * IVB workaround: must disable low power watermarks for at least | |
3255 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3256 | * when scaling is disabled. | |
3257 | * | |
3258 | * WaCxSRDisabledForSpriteScaling:ivb | |
3259 | */ | |
3260 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3261 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3262 | ||
820c1980 | 3263 | ilk_update_wm(crtc); |
526682e9 PZ |
3264 | } |
3265 | ||
3078999f PB |
3266 | static void skl_pipe_wm_active_state(uint32_t val, |
3267 | struct skl_pipe_wm *active, | |
3268 | bool is_transwm, | |
3269 | bool is_cursor, | |
3270 | int i, | |
3271 | int level) | |
3272 | { | |
3273 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3274 | ||
3275 | if (!is_transwm) { | |
3276 | if (!is_cursor) { | |
3277 | active->wm[level].plane_en[i] = is_enabled; | |
3278 | active->wm[level].plane_res_b[i] = | |
3279 | val & PLANE_WM_BLOCKS_MASK; | |
3280 | active->wm[level].plane_res_l[i] = | |
3281 | (val >> PLANE_WM_LINES_SHIFT) & | |
3282 | PLANE_WM_LINES_MASK; | |
3283 | } else { | |
3284 | active->wm[level].cursor_en = is_enabled; | |
3285 | active->wm[level].cursor_res_b = | |
3286 | val & PLANE_WM_BLOCKS_MASK; | |
3287 | active->wm[level].cursor_res_l = | |
3288 | (val >> PLANE_WM_LINES_SHIFT) & | |
3289 | PLANE_WM_LINES_MASK; | |
3290 | } | |
3291 | } else { | |
3292 | if (!is_cursor) { | |
3293 | active->trans_wm.plane_en[i] = is_enabled; | |
3294 | active->trans_wm.plane_res_b[i] = | |
3295 | val & PLANE_WM_BLOCKS_MASK; | |
3296 | active->trans_wm.plane_res_l[i] = | |
3297 | (val >> PLANE_WM_LINES_SHIFT) & | |
3298 | PLANE_WM_LINES_MASK; | |
3299 | } else { | |
3300 | active->trans_wm.cursor_en = is_enabled; | |
3301 | active->trans_wm.cursor_res_b = | |
3302 | val & PLANE_WM_BLOCKS_MASK; | |
3303 | active->trans_wm.cursor_res_l = | |
3304 | (val >> PLANE_WM_LINES_SHIFT) & | |
3305 | PLANE_WM_LINES_MASK; | |
3306 | } | |
3307 | } | |
3308 | } | |
3309 | ||
3310 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3311 | { | |
3312 | struct drm_device *dev = crtc->dev; | |
3313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3314 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3316 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; | |
3317 | enum pipe pipe = intel_crtc->pipe; | |
3318 | int level, i, max_level; | |
3319 | uint32_t temp; | |
3320 | ||
3321 | max_level = ilk_wm_max_level(dev); | |
3322 | ||
3323 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3324 | ||
3325 | for (level = 0; level <= max_level; level++) { | |
3326 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3327 | hw->plane[pipe][i][level] = | |
3328 | I915_READ(PLANE_WM(pipe, i, level)); | |
3329 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); | |
3330 | } | |
3331 | ||
3332 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3333 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
3334 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); | |
3335 | ||
3336 | if (!intel_crtc_active(crtc)) | |
3337 | return; | |
3338 | ||
3339 | hw->dirty[pipe] = true; | |
3340 | ||
3341 | active->linetime = hw->wm_linetime[pipe]; | |
3342 | ||
3343 | for (level = 0; level <= max_level; level++) { | |
3344 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3345 | temp = hw->plane[pipe][i][level]; | |
3346 | skl_pipe_wm_active_state(temp, active, false, | |
3347 | false, i, level); | |
3348 | } | |
3349 | temp = hw->cursor[pipe][level]; | |
3350 | skl_pipe_wm_active_state(temp, active, false, true, i, level); | |
3351 | } | |
3352 | ||
3353 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3354 | temp = hw->plane_trans[pipe][i]; | |
3355 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3356 | } | |
3357 | ||
3358 | temp = hw->cursor_trans[pipe]; | |
3359 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); | |
3360 | } | |
3361 | ||
3362 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3363 | { | |
a269c583 DL |
3364 | struct drm_i915_private *dev_priv = dev->dev_private; |
3365 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3078999f PB |
3366 | struct drm_crtc *crtc; |
3367 | ||
a269c583 | 3368 | skl_ddb_get_hw_state(dev_priv, ddb); |
3078999f PB |
3369 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3370 | skl_pipe_wm_get_hw_state(crtc); | |
3371 | } | |
3372 | ||
243e6a44 VS |
3373 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3374 | { | |
3375 | struct drm_device *dev = crtc->dev; | |
3376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3377 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3379 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
3380 | enum pipe pipe = intel_crtc->pipe; | |
3381 | static const unsigned int wm0_pipe_reg[] = { | |
3382 | [PIPE_A] = WM0_PIPEA_ILK, | |
3383 | [PIPE_B] = WM0_PIPEB_ILK, | |
3384 | [PIPE_C] = WM0_PIPEC_IVB, | |
3385 | }; | |
3386 | ||
3387 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3388 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3389 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3390 | |
2a44b76b VS |
3391 | active->pipe_enabled = intel_crtc_active(crtc); |
3392 | ||
3393 | if (active->pipe_enabled) { | |
243e6a44 VS |
3394 | u32 tmp = hw->wm_pipe[pipe]; |
3395 | ||
3396 | /* | |
3397 | * For active pipes LP0 watermark is marked as | |
3398 | * enabled, and LP1+ watermaks as disabled since | |
3399 | * we can't really reverse compute them in case | |
3400 | * multiple pipes are active. | |
3401 | */ | |
3402 | active->wm[0].enable = true; | |
3403 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3404 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3405 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3406 | active->linetime = hw->wm_linetime[pipe]; | |
3407 | } else { | |
3408 | int level, max_level = ilk_wm_max_level(dev); | |
3409 | ||
3410 | /* | |
3411 | * For inactive pipes, all watermark levels | |
3412 | * should be marked as enabled but zeroed, | |
3413 | * which is what we'd compute them to. | |
3414 | */ | |
3415 | for (level = 0; level <= max_level; level++) | |
3416 | active->wm[level].enable = true; | |
3417 | } | |
3418 | } | |
3419 | ||
3420 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
3421 | { | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3423 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3424 | struct drm_crtc *crtc; |
3425 | ||
70e1e0ec | 3426 | for_each_crtc(dev, crtc) |
243e6a44 VS |
3427 | ilk_pipe_wm_get_hw_state(crtc); |
3428 | ||
3429 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3430 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3431 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3432 | ||
3433 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
3434 | if (INTEL_INFO(dev)->gen >= 7) { |
3435 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3436 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3437 | } | |
243e6a44 | 3438 | |
a42a5719 | 3439 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
3440 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
3441 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3442 | else if (IS_IVYBRIDGE(dev)) | |
3443 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3444 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3445 | |
3446 | hw->enable_fbc_wm = | |
3447 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3448 | } | |
3449 | ||
b445e3b0 ED |
3450 | /** |
3451 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3452 | * | |
3453 | * Calculate watermark values for the various WM regs based on current mode | |
3454 | * and plane configuration. | |
3455 | * | |
3456 | * There are several cases to deal with here: | |
3457 | * - normal (i.e. non-self-refresh) | |
3458 | * - self-refresh (SR) mode | |
3459 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3460 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3461 | * lines), so need to account for TLB latency | |
3462 | * | |
3463 | * The normal calculation is: | |
3464 | * watermark = dotclock * bytes per pixel * latency | |
3465 | * where latency is platform & configuration dependent (we assume pessimal | |
3466 | * values here). | |
3467 | * | |
3468 | * The SR calculation is: | |
3469 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3470 | * bytes per pixel | |
3471 | * where | |
3472 | * line time = htotal / dotclock | |
3473 | * surface width = hdisplay for normal plane and 64 for cursor | |
3474 | * and latency is assumed to be high, as above. | |
3475 | * | |
3476 | * The final value programmed to the register should always be rounded up, | |
3477 | * and include an extra 2 entries to account for clock crossings. | |
3478 | * | |
3479 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3480 | * to set the non-SR watermarks to 8. | |
3481 | */ | |
46ba614c | 3482 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 3483 | { |
46ba614c | 3484 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
3485 | |
3486 | if (dev_priv->display.update_wm) | |
46ba614c | 3487 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
3488 | } |
3489 | ||
adf3d35e VS |
3490 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
3491 | struct drm_crtc *crtc, | |
ed57cb8a DL |
3492 | uint32_t sprite_width, |
3493 | uint32_t sprite_height, | |
3494 | int pixel_size, | |
39db4a4d | 3495 | bool enabled, bool scaled) |
b445e3b0 | 3496 | { |
adf3d35e | 3497 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
3498 | |
3499 | if (dev_priv->display.update_sprite_wm) | |
ed57cb8a DL |
3500 | dev_priv->display.update_sprite_wm(plane, crtc, |
3501 | sprite_width, sprite_height, | |
39db4a4d | 3502 | pixel_size, enabled, scaled); |
b445e3b0 ED |
3503 | } |
3504 | ||
2b4e57bd ED |
3505 | static struct drm_i915_gem_object * |
3506 | intel_alloc_context_page(struct drm_device *dev) | |
3507 | { | |
3508 | struct drm_i915_gem_object *ctx; | |
3509 | int ret; | |
3510 | ||
3511 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
3512 | ||
3513 | ctx = i915_gem_alloc_object(dev, 4096); | |
3514 | if (!ctx) { | |
3515 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
3516 | return NULL; | |
3517 | } | |
3518 | ||
c69766f2 | 3519 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
2b4e57bd ED |
3520 | if (ret) { |
3521 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
3522 | goto err_unref; | |
3523 | } | |
3524 | ||
3525 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
3526 | if (ret) { | |
3527 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
3528 | goto err_unpin; | |
3529 | } | |
3530 | ||
3531 | return ctx; | |
3532 | ||
3533 | err_unpin: | |
d7f46fc4 | 3534 | i915_gem_object_ggtt_unpin(ctx); |
2b4e57bd ED |
3535 | err_unref: |
3536 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
3537 | return NULL; |
3538 | } | |
3539 | ||
9270388e DV |
3540 | /** |
3541 | * Lock protecting IPS related data structures | |
9270388e DV |
3542 | */ |
3543 | DEFINE_SPINLOCK(mchdev_lock); | |
3544 | ||
3545 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3546 | * mchdev_lock. */ | |
3547 | static struct drm_i915_private *i915_mch_dev; | |
3548 | ||
2b4e57bd ED |
3549 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
3550 | { | |
3551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3552 | u16 rgvswctl; | |
3553 | ||
9270388e DV |
3554 | assert_spin_locked(&mchdev_lock); |
3555 | ||
2b4e57bd ED |
3556 | rgvswctl = I915_READ16(MEMSWCTL); |
3557 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3558 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3559 | return false; /* still busy with another command */ | |
3560 | } | |
3561 | ||
3562 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3563 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3564 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3565 | POSTING_READ16(MEMSWCTL); | |
3566 | ||
3567 | rgvswctl |= MEMCTL_CMD_STS; | |
3568 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3569 | ||
3570 | return true; | |
3571 | } | |
3572 | ||
8090c6b9 | 3573 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
3574 | { |
3575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3576 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3577 | u8 fmax, fmin, fstart, vstart; | |
3578 | ||
9270388e DV |
3579 | spin_lock_irq(&mchdev_lock); |
3580 | ||
2b4e57bd ED |
3581 | /* Enable temp reporting */ |
3582 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3583 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3584 | ||
3585 | /* 100ms RC evaluation intervals */ | |
3586 | I915_WRITE(RCUPEI, 100000); | |
3587 | I915_WRITE(RCDNEI, 100000); | |
3588 | ||
3589 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3590 | I915_WRITE(RCBMAXAVG, 90000); | |
3591 | I915_WRITE(RCBMINAVG, 80000); | |
3592 | ||
3593 | I915_WRITE(MEMIHYST, 1); | |
3594 | ||
3595 | /* Set up min, max, and cur for interrupt handling */ | |
3596 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3597 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3598 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3599 | MEMMODE_FSTART_SHIFT; | |
3600 | ||
3601 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3602 | PXVFREQ_PX_SHIFT; | |
3603 | ||
20e4d407 DV |
3604 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
3605 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 3606 | |
20e4d407 DV |
3607 | dev_priv->ips.max_delay = fstart; |
3608 | dev_priv->ips.min_delay = fmin; | |
3609 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
3610 | |
3611 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3612 | fmax, fmin, fstart); | |
3613 | ||
3614 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3615 | ||
3616 | /* | |
3617 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3618 | */ | |
3619 | ||
3620 | I915_WRITE(VIDSTART, vstart); | |
3621 | POSTING_READ(VIDSTART); | |
3622 | ||
3623 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3624 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3625 | ||
9270388e | 3626 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 3627 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 3628 | mdelay(1); |
2b4e57bd ED |
3629 | |
3630 | ironlake_set_drps(dev, fstart); | |
3631 | ||
20e4d407 | 3632 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 3633 | I915_READ(0x112e0); |
20e4d407 DV |
3634 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
3635 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
5ed0bdf2 | 3636 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
3637 | |
3638 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
3639 | } |
3640 | ||
8090c6b9 | 3641 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
3642 | { |
3643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
3644 | u16 rgvswctl; |
3645 | ||
3646 | spin_lock_irq(&mchdev_lock); | |
3647 | ||
3648 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
3649 | |
3650 | /* Ack interrupts, disable EFC interrupt */ | |
3651 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3652 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3653 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3654 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3655 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3656 | ||
3657 | /* Go back to the starting frequency */ | |
20e4d407 | 3658 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 3659 | mdelay(1); |
2b4e57bd ED |
3660 | rgvswctl |= MEMCTL_CMD_STS; |
3661 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 3662 | mdelay(1); |
2b4e57bd | 3663 | |
9270388e | 3664 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
3665 | } |
3666 | ||
acbe9475 DV |
3667 | /* There's a funny hw issue where the hw returns all 0 when reading from |
3668 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3669 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3670 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3671 | */ | |
6917c7b9 | 3672 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 3673 | { |
7b9e0ae6 | 3674 | u32 limits; |
2b4e57bd | 3675 | |
20b46e59 DV |
3676 | /* Only set the down limit when we've reached the lowest level to avoid |
3677 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3678 | * race in the hw when coming out of rc6: There's a tiny window where | |
3679 | * the hw runs at the minimal clock before selecting the desired | |
3680 | * frequency, if the down threshold expires in that window we will not | |
3681 | * receive a down interrupt. */ | |
b39fb297 BW |
3682 | limits = dev_priv->rps.max_freq_softlimit << 24; |
3683 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3684 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
3685 | |
3686 | return limits; | |
3687 | } | |
3688 | ||
dd75fdc8 CW |
3689 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
3690 | { | |
3691 | int new_power; | |
3692 | ||
3693 | new_power = dev_priv->rps.power; | |
3694 | switch (dev_priv->rps.power) { | |
3695 | case LOW_POWER: | |
b39fb297 | 3696 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3697 | new_power = BETWEEN; |
3698 | break; | |
3699 | ||
3700 | case BETWEEN: | |
b39fb297 | 3701 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 3702 | new_power = LOW_POWER; |
b39fb297 | 3703 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3704 | new_power = HIGH_POWER; |
3705 | break; | |
3706 | ||
3707 | case HIGH_POWER: | |
b39fb297 | 3708 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3709 | new_power = BETWEEN; |
3710 | break; | |
3711 | } | |
3712 | /* Max/min bins are special */ | |
b39fb297 | 3713 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 3714 | new_power = LOW_POWER; |
b39fb297 | 3715 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
3716 | new_power = HIGH_POWER; |
3717 | if (new_power == dev_priv->rps.power) | |
3718 | return; | |
3719 | ||
3720 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3721 | switch (new_power) { | |
3722 | case LOW_POWER: | |
3723 | /* Upclock if more than 95% busy over 16ms */ | |
3724 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
3725 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
3726 | ||
3727 | /* Downclock if less than 85% busy over 32ms */ | |
3728 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3729 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
3730 | ||
3731 | I915_WRITE(GEN6_RP_CONTROL, | |
3732 | GEN6_RP_MEDIA_TURBO | | |
3733 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3734 | GEN6_RP_MEDIA_IS_GFX | | |
3735 | GEN6_RP_ENABLE | | |
3736 | GEN6_RP_UP_BUSY_AVG | | |
3737 | GEN6_RP_DOWN_IDLE_AVG); | |
3738 | break; | |
3739 | ||
3740 | case BETWEEN: | |
3741 | /* Upclock if more than 90% busy over 13ms */ | |
3742 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
3743 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
3744 | ||
3745 | /* Downclock if less than 75% busy over 32ms */ | |
3746 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3747 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
3748 | ||
3749 | I915_WRITE(GEN6_RP_CONTROL, | |
3750 | GEN6_RP_MEDIA_TURBO | | |
3751 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3752 | GEN6_RP_MEDIA_IS_GFX | | |
3753 | GEN6_RP_ENABLE | | |
3754 | GEN6_RP_UP_BUSY_AVG | | |
3755 | GEN6_RP_DOWN_IDLE_AVG); | |
3756 | break; | |
3757 | ||
3758 | case HIGH_POWER: | |
3759 | /* Upclock if more than 85% busy over 10ms */ | |
3760 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
3761 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
3762 | ||
3763 | /* Downclock if less than 60% busy over 32ms */ | |
3764 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3765 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
3766 | ||
3767 | I915_WRITE(GEN6_RP_CONTROL, | |
3768 | GEN6_RP_MEDIA_TURBO | | |
3769 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3770 | GEN6_RP_MEDIA_IS_GFX | | |
3771 | GEN6_RP_ENABLE | | |
3772 | GEN6_RP_UP_BUSY_AVG | | |
3773 | GEN6_RP_DOWN_IDLE_AVG); | |
3774 | break; | |
3775 | } | |
3776 | ||
3777 | dev_priv->rps.power = new_power; | |
3778 | dev_priv->rps.last_adj = 0; | |
3779 | } | |
3780 | ||
2876ce73 CW |
3781 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
3782 | { | |
3783 | u32 mask = 0; | |
3784 | ||
3785 | if (val > dev_priv->rps.min_freq_softlimit) | |
3786 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
3787 | if (val < dev_priv->rps.max_freq_softlimit) | |
3788 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
3789 | ||
7b3c29f6 CW |
3790 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
3791 | mask &= dev_priv->pm_rps_events; | |
3792 | ||
59d02a1f | 3793 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
3794 | } |
3795 | ||
b8a5ff8d JM |
3796 | /* gen6_set_rps is called to update the frequency request, but should also be |
3797 | * called when the range (min_delay and max_delay) is modified so that we can | |
3798 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
ffe02b40 | 3799 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
20b46e59 DV |
3800 | { |
3801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 3802 | |
4fc688ce | 3803 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3804 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3805 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 3806 | |
eb64cad1 CW |
3807 | /* min/max delay may still have been modified so be sure to |
3808 | * write the limits value. | |
3809 | */ | |
3810 | if (val != dev_priv->rps.cur_freq) { | |
3811 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 3812 | |
50e6a2a7 | 3813 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
eb64cad1 CW |
3814 | I915_WRITE(GEN6_RPNSWREQ, |
3815 | HSW_FREQUENCY(val)); | |
3816 | else | |
3817 | I915_WRITE(GEN6_RPNSWREQ, | |
3818 | GEN6_FREQUENCY(val) | | |
3819 | GEN6_OFFSET(0) | | |
3820 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 3821 | } |
7b9e0ae6 | 3822 | |
7b9e0ae6 CW |
3823 | /* Make sure we continue to get interrupts |
3824 | * until we hit the minimum or maximum frequencies. | |
3825 | */ | |
eb64cad1 | 3826 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
2876ce73 | 3827 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 3828 | |
d5570a72 BW |
3829 | POSTING_READ(GEN6_RPNSWREQ); |
3830 | ||
b39fb297 | 3831 | dev_priv->rps.cur_freq = val; |
be2cde9a | 3832 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
3833 | } |
3834 | ||
ffe02b40 VS |
3835 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
3836 | { | |
3837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3838 | ||
3839 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
3840 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); | |
3841 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
3842 | ||
3843 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
3844 | "Odd GPU freq value\n")) | |
3845 | val &= ~1; | |
3846 | ||
3847 | if (val != dev_priv->rps.cur_freq) | |
3848 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
3849 | ||
3850 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); | |
3851 | ||
3852 | dev_priv->rps.cur_freq = val; | |
3853 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
3854 | } | |
3855 | ||
76c3552f D |
3856 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
3857 | * | |
3858 | * * If Gfx is Idle, then | |
3859 | * 1. Mask Turbo interrupts | |
3860 | * 2. Bring up Gfx clock | |
3861 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3862 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3863 | * 5. Unmask Turbo interrupts | |
3864 | */ | |
3865 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
3866 | { | |
5549d25f D |
3867 | struct drm_device *dev = dev_priv->dev; |
3868 | ||
21a11fff VS |
3869 | /* CHV and latest VLV don't need to force the gfx clock */ |
3870 | if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) { | |
5549d25f D |
3871 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
3872 | return; | |
3873 | } | |
3874 | ||
76c3552f D |
3875 | /* |
3876 | * When we are idle. Drop to min voltage state. | |
3877 | */ | |
3878 | ||
b39fb297 | 3879 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
3880 | return; |
3881 | ||
3882 | /* Mask turbo interrupt so that they will not come in between */ | |
f24eeb19 ID |
3883 | I915_WRITE(GEN6_PMINTRMSK, |
3884 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
76c3552f | 3885 | |
650ad970 | 3886 | vlv_force_gfx_clock(dev_priv, true); |
76c3552f | 3887 | |
b39fb297 | 3888 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
3889 | |
3890 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 3891 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
3892 | |
3893 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
2837ac40 | 3894 | & GENFREQSTATUS) == 0, 100)) |
76c3552f D |
3895 | DRM_ERROR("timed out waiting for Punit\n"); |
3896 | ||
650ad970 | 3897 | vlv_force_gfx_clock(dev_priv, false); |
76c3552f | 3898 | |
2876ce73 CW |
3899 | I915_WRITE(GEN6_PMINTRMSK, |
3900 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
76c3552f D |
3901 | } |
3902 | ||
b29c19b6 CW |
3903 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
3904 | { | |
691bb717 DL |
3905 | struct drm_device *dev = dev_priv->dev; |
3906 | ||
b29c19b6 | 3907 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3908 | if (dev_priv->rps.enabled) { |
21a11fff | 3909 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 3910 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 3911 | else |
b39fb297 | 3912 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c0951f0c CW |
3913 | dev_priv->rps.last_adj = 0; |
3914 | } | |
b29c19b6 CW |
3915 | mutex_unlock(&dev_priv->rps.hw_lock); |
3916 | } | |
3917 | ||
3918 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
3919 | { | |
3920 | mutex_lock(&dev_priv->rps.hw_lock); | |
c0951f0c | 3921 | if (dev_priv->rps.enabled) { |
ffe02b40 | 3922 | intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c CW |
3923 | dev_priv->rps.last_adj = 0; |
3924 | } | |
b29c19b6 CW |
3925 | mutex_unlock(&dev_priv->rps.hw_lock); |
3926 | } | |
3927 | ||
ffe02b40 | 3928 | void intel_set_rps(struct drm_device *dev, u8 val) |
0a073b84 | 3929 | { |
ffe02b40 VS |
3930 | if (IS_VALLEYVIEW(dev)) |
3931 | valleyview_set_rps(dev, val); | |
3932 | else | |
3933 | gen6_set_rps(dev, val); | |
0a073b84 JB |
3934 | } |
3935 | ||
20e49366 ZW |
3936 | static void gen9_disable_rps(struct drm_device *dev) |
3937 | { | |
3938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3939 | ||
3940 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
38c23527 | 3941 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
3942 | } |
3943 | ||
44fc7d5c | 3944 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
3945 | { |
3946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3947 | ||
3948 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 3949 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
44fc7d5c DV |
3950 | } |
3951 | ||
38807746 D |
3952 | static void cherryview_disable_rps(struct drm_device *dev) |
3953 | { | |
3954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3955 | ||
3956 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3957 | } | |
3958 | ||
44fc7d5c DV |
3959 | static void valleyview_disable_rps(struct drm_device *dev) |
3960 | { | |
3961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3962 | ||
98a2e5f9 D |
3963 | /* we're doing forcewake before Disabling RC6, |
3964 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 3965 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 3966 | |
44fc7d5c | 3967 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 3968 | |
59bad947 | 3969 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
3970 | } |
3971 | ||
dc39fff7 BW |
3972 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
3973 | { | |
91ca689a ID |
3974 | if (IS_VALLEYVIEW(dev)) { |
3975 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
3976 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
3977 | else | |
3978 | mode = 0; | |
3979 | } | |
58abf1da RV |
3980 | if (HAS_RC6p(dev)) |
3981 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
3982 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
3983 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
3984 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
3985 | ||
3986 | else | |
3987 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
3988 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
3989 | } |
3990 | ||
e6069ca8 | 3991 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 3992 | { |
eb4926e4 DL |
3993 | /* No RC6 before Ironlake */ |
3994 | if (INTEL_INFO(dev)->gen < 5) | |
3995 | return 0; | |
3996 | ||
e6069ca8 ID |
3997 | /* RC6 is only on Ironlake mobile not on desktop */ |
3998 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
3999 | return 0; | |
4000 | ||
456470eb | 4001 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4002 | if (enable_rc6 >= 0) { |
4003 | int mask; | |
4004 | ||
58abf1da | 4005 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4006 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4007 | INTEL_RC6pp_ENABLE; | |
4008 | else | |
4009 | mask = INTEL_RC6_ENABLE; | |
4010 | ||
4011 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4012 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4013 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4014 | |
4015 | return enable_rc6 & mask; | |
4016 | } | |
2b4e57bd | 4017 | |
6567d748 CW |
4018 | /* Disable RC6 on Ironlake */ |
4019 | if (INTEL_INFO(dev)->gen == 5) | |
4020 | return 0; | |
2b4e57bd | 4021 | |
8bade1ad | 4022 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4023 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4024 | |
4025 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4026 | } |
4027 | ||
e6069ca8 ID |
4028 | int intel_enable_rc6(const struct drm_device *dev) |
4029 | { | |
4030 | return i915.enable_rc6; | |
4031 | } | |
4032 | ||
93ee2920 | 4033 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
3280e8b0 | 4034 | { |
93ee2920 TR |
4035 | struct drm_i915_private *dev_priv = dev->dev_private; |
4036 | uint32_t rp_state_cap; | |
4037 | u32 ddcc_status = 0; | |
4038 | int ret; | |
4039 | ||
4040 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3280e8b0 BW |
4041 | /* All of these values are in units of 50MHz */ |
4042 | dev_priv->rps.cur_freq = 0; | |
93ee2920 | 4043 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
3280e8b0 | 4044 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
93ee2920 | 4045 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
3280e8b0 | 4046 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
3280e8b0 BW |
4047 | /* hw_max = RP0 until we check for overclocking */ |
4048 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4049 | ||
93ee2920 TR |
4050 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
4051 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
4052 | ret = sandybridge_pcode_read(dev_priv, | |
4053 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4054 | &ddcc_status); | |
4055 | if (0 == ret) | |
4056 | dev_priv->rps.efficient_freq = | |
4057 | (ddcc_status >> 8) & 0xff; | |
4058 | } | |
4059 | ||
3280e8b0 BW |
4060 | /* Preserve min/max settings in case of re-init */ |
4061 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4062 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4063 | ||
93ee2920 TR |
4064 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4065 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4066 | dev_priv->rps.min_freq_softlimit = | |
f4ab408c TR |
4067 | /* max(RPe, 450 MHz) */ |
4068 | max(dev_priv->rps.efficient_freq, (u8) 9); | |
93ee2920 TR |
4069 | else |
4070 | dev_priv->rps.min_freq_softlimit = | |
4071 | dev_priv->rps.min_freq; | |
4072 | } | |
3280e8b0 BW |
4073 | } |
4074 | ||
b6fef0ef | 4075 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
20e49366 | 4076 | static void gen9_enable_rps(struct drm_device *dev) |
b6fef0ef JB |
4077 | { |
4078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4079 | ||
4080 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4081 | ||
ba1c554c DL |
4082 | gen6_init_rps_frequencies(dev); |
4083 | ||
b6fef0ef JB |
4084 | I915_WRITE(GEN6_RPNSWREQ, 0xc800000); |
4085 | I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); | |
4086 | ||
4087 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); | |
4088 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); | |
4089 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); | |
4090 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); | |
4091 | I915_WRITE(GEN6_RP_UP_EI, 0x101d0); | |
4092 | I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); | |
4093 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); | |
4094 | I915_WRITE(GEN6_PMINTRMSK, 0x6); | |
4095 | I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | | |
4096 | GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | | |
4097 | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | | |
4098 | GEN6_RP_DOWN_IDLE_AVG); | |
4099 | ||
4100 | gen6_enable_rps_interrupts(dev); | |
4101 | ||
4102 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4103 | } | |
4104 | ||
4105 | static void gen9_enable_rc6(struct drm_device *dev) | |
20e49366 ZW |
4106 | { |
4107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4108 | struct intel_engine_cs *ring; | |
4109 | uint32_t rc6_mask = 0; | |
4110 | int unused; | |
4111 | ||
4112 | /* 1a: Software RC state - RC0 */ | |
4113 | I915_WRITE(GEN6_RC_STATE, 0); | |
4114 | ||
4115 | /* 1b: Get forcewake during program sequence. Although the driver | |
4116 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4117 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4118 | |
4119 | /* 2a: Disable RC states. */ | |
4120 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4121 | ||
4122 | /* 2b: Program RC6 thresholds.*/ | |
4123 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
4124 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4125 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4126 | for_each_ring(ring, dev_priv, unused) | |
4127 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4128 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4129 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
4130 | ||
38c23527 ZW |
4131 | /* 2c: Program Coarse Power Gating Policies. */ |
4132 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4133 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4134 | ||
20e49366 ZW |
4135 | /* 3a: Enable RC6 */ |
4136 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4137 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4138 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4139 | "on" : "off"); | |
4140 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4141 | GEN6_RC_CTL_EI_MODE(1) | | |
4142 | rc6_mask); | |
4143 | ||
38c23527 ZW |
4144 | /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ |
4145 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); | |
4146 | ||
59bad947 | 4147 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4148 | |
4149 | } | |
4150 | ||
6edee7f3 BW |
4151 | static void gen8_enable_rps(struct drm_device *dev) |
4152 | { | |
4153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4154 | struct intel_engine_cs *ring; |
93ee2920 | 4155 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
4156 | int unused; |
4157 | ||
4158 | /* 1a: Software RC state - RC0 */ | |
4159 | I915_WRITE(GEN6_RC_STATE, 0); | |
4160 | ||
4161 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4162 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4163 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4164 | |
4165 | /* 2a: Disable RC states. */ | |
4166 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4167 | ||
93ee2920 TR |
4168 | /* Initialize rps frequencies */ |
4169 | gen6_init_rps_frequencies(dev); | |
6edee7f3 BW |
4170 | |
4171 | /* 2b: Program RC6 thresholds.*/ | |
4172 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4173 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4174 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4175 | for_each_ring(ring, dev_priv, unused) | |
4176 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4177 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4178 | if (IS_BROADWELL(dev)) |
4179 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4180 | else | |
4181 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4182 | |
4183 | /* 3: Enable RC6 */ | |
4184 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4185 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4186 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4187 | if (IS_BROADWELL(dev)) |
4188 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4189 | GEN7_RC_CTL_TO_MODE | | |
4190 | rc6_mask); | |
4191 | else | |
4192 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4193 | GEN6_RC_CTL_EI_MODE(1) | | |
4194 | rc6_mask); | |
6edee7f3 BW |
4195 | |
4196 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4197 | I915_WRITE(GEN6_RPNSWREQ, |
4198 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4199 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4200 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4201 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4202 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4203 | ||
4204 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4205 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4206 | dev_priv->rps.max_freq_softlimit << 24 | | |
4207 | dev_priv->rps.min_freq_softlimit << 16); | |
4208 | ||
4209 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4210 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4211 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4212 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4213 | ||
4214 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4215 | |
4216 | /* 5: Enable RPS */ | |
7526ed79 DV |
4217 | I915_WRITE(GEN6_RP_CONTROL, |
4218 | GEN6_RP_MEDIA_TURBO | | |
4219 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4220 | GEN6_RP_MEDIA_IS_GFX | | |
4221 | GEN6_RP_ENABLE | | |
4222 | GEN6_RP_UP_BUSY_AVG | | |
4223 | GEN6_RP_DOWN_IDLE_AVG); | |
4224 | ||
4225 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4226 | ||
c7f3153a TR |
4227 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4228 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
7526ed79 | 4229 | |
59bad947 | 4230 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4231 | } |
4232 | ||
79f5b2c7 | 4233 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4234 | { |
79f5b2c7 | 4235 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4236 | struct intel_engine_cs *ring; |
d060c169 | 4237 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4238 | u32 gtfifodbg; |
2b4e57bd | 4239 | int rc6_mode; |
42c0526c | 4240 | int i, ret; |
2b4e57bd | 4241 | |
4fc688ce | 4242 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4243 | |
2b4e57bd ED |
4244 | /* Here begins a magic sequence of register writes to enable |
4245 | * auto-downclocking. | |
4246 | * | |
4247 | * Perhaps there might be some value in exposing these to | |
4248 | * userspace... | |
4249 | */ | |
4250 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4251 | |
4252 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4253 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4254 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4255 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4256 | } | |
4257 | ||
59bad947 | 4258 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4259 | |
93ee2920 TR |
4260 | /* Initialize rps frequencies */ |
4261 | gen6_init_rps_frequencies(dev); | |
dd0a1aa1 | 4262 | |
2b4e57bd ED |
4263 | /* disable the counters and set deterministic thresholds */ |
4264 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4265 | ||
4266 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4267 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4268 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4269 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4270 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4271 | ||
b4519513 CW |
4272 | for_each_ring(ring, dev_priv, i) |
4273 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4274 | |
4275 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4276 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4277 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4278 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4279 | else | |
4280 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4281 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4282 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4283 | ||
5a7dc92a | 4284 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4285 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4286 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4287 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4288 | ||
5a7dc92a ED |
4289 | /* We don't use those on Haswell */ |
4290 | if (!IS_HASWELL(dev)) { | |
4291 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4292 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4293 | |
5a7dc92a ED |
4294 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4295 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4296 | } | |
2b4e57bd | 4297 | |
dc39fff7 | 4298 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4299 | |
4300 | I915_WRITE(GEN6_RC_CONTROL, | |
4301 | rc6_mask | | |
4302 | GEN6_RC_CTL_EI_MODE(1) | | |
4303 | GEN6_RC_CTL_HW_ENABLE); | |
4304 | ||
dd75fdc8 CW |
4305 | /* Power down if completely idle for over 50ms */ |
4306 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4307 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4308 | |
42c0526c | 4309 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4310 | if (ret) |
42c0526c | 4311 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4312 | |
4313 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4314 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4315 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4316 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4317 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4318 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4319 | } |
4320 | ||
dd75fdc8 | 4321 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 4322 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 4323 | |
31643d54 BW |
4324 | rc6vids = 0; |
4325 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4326 | if (IS_GEN6(dev) && ret) { | |
4327 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4328 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4329 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4330 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4331 | rc6vids &= 0xffff00; | |
4332 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4333 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4334 | if (ret) | |
4335 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4336 | } | |
4337 | ||
59bad947 | 4338 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4339 | } |
4340 | ||
c2bc2fc5 | 4341 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4342 | { |
79f5b2c7 | 4343 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4344 | int min_freq = 15; |
3ebecd07 CW |
4345 | unsigned int gpu_freq; |
4346 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 4347 | int scaling_factor = 180; |
eda79642 | 4348 | struct cpufreq_policy *policy; |
2b4e57bd | 4349 | |
4fc688ce | 4350 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4351 | |
eda79642 BW |
4352 | policy = cpufreq_cpu_get(0); |
4353 | if (policy) { | |
4354 | max_ia_freq = policy->cpuinfo.max_freq; | |
4355 | cpufreq_cpu_put(policy); | |
4356 | } else { | |
4357 | /* | |
4358 | * Default to measured freq if none found, PCU will ensure we | |
4359 | * don't go over | |
4360 | */ | |
2b4e57bd | 4361 | max_ia_freq = tsc_khz; |
eda79642 | 4362 | } |
2b4e57bd ED |
4363 | |
4364 | /* Convert from kHz to MHz */ | |
4365 | max_ia_freq /= 1000; | |
4366 | ||
153b4b95 | 4367 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4368 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4369 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4370 | |
2b4e57bd ED |
4371 | /* |
4372 | * For each potential GPU frequency, load a ring frequency we'd like | |
4373 | * to use for memory access. We do this by specifying the IA frequency | |
4374 | * the PCU should use as a reference to determine the ring frequency. | |
4375 | */ | |
6985b352 | 4376 | for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; |
2b4e57bd | 4377 | gpu_freq--) { |
6985b352 | 4378 | int diff = dev_priv->rps.max_freq - gpu_freq; |
3ebecd07 CW |
4379 | unsigned int ia_freq = 0, ring_freq = 0; |
4380 | ||
46c764d4 BW |
4381 | if (INTEL_INFO(dev)->gen >= 8) { |
4382 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4383 | ring_freq = max(min_ring_freq, gpu_freq); | |
4384 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4385 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4386 | ring_freq = max(min_ring_freq, ring_freq); |
4387 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4388 | } else { | |
4389 | /* On older processors, there is no separate ring | |
4390 | * clock domain, so in order to boost the bandwidth | |
4391 | * of the ring, we need to upclock the CPU (ia_freq). | |
4392 | * | |
4393 | * For GPU frequencies less than 750MHz, | |
4394 | * just use the lowest ring freq. | |
4395 | */ | |
4396 | if (gpu_freq < min_freq) | |
4397 | ia_freq = 800; | |
4398 | else | |
4399 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4400 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4401 | } | |
2b4e57bd | 4402 | |
42c0526c BW |
4403 | sandybridge_pcode_write(dev_priv, |
4404 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4405 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4406 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4407 | gpu_freq); | |
2b4e57bd | 4408 | } |
2b4e57bd ED |
4409 | } |
4410 | ||
c2bc2fc5 ID |
4411 | void gen6_update_ring_freq(struct drm_device *dev) |
4412 | { | |
4413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4414 | ||
4415 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4416 | return; | |
4417 | ||
4418 | mutex_lock(&dev_priv->rps.hw_lock); | |
4419 | __gen6_update_ring_freq(dev); | |
4420 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4421 | } | |
4422 | ||
03af2045 | 4423 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 4424 | { |
095acd5f | 4425 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
4426 | u32 val, rp0; |
4427 | ||
095acd5f D |
4428 | if (dev->pdev->revision >= 0x20) { |
4429 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
2b6b3a09 | 4430 | |
095acd5f D |
4431 | switch (INTEL_INFO(dev)->eu_total) { |
4432 | case 8: | |
4433 | /* (2 * 4) config */ | |
4434 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
4435 | break; | |
4436 | case 12: | |
4437 | /* (2 * 6) config */ | |
4438 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
4439 | break; | |
4440 | case 16: | |
4441 | /* (2 * 8) config */ | |
4442 | default: | |
4443 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
4444 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
4445 | break; | |
4446 | } | |
4447 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
4448 | } else { | |
4449 | /* For pre-production hardware */ | |
4450 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4451 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4452 | PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4453 | } | |
2b6b3a09 D |
4454 | return rp0; |
4455 | } | |
4456 | ||
4457 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4458 | { | |
4459 | u32 val, rpe; | |
4460 | ||
4461 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4462 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4463 | ||
4464 | return rpe; | |
4465 | } | |
4466 | ||
7707df4a D |
4467 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4468 | { | |
095acd5f | 4469 | struct drm_device *dev = dev_priv->dev; |
7707df4a D |
4470 | u32 val, rp1; |
4471 | ||
095acd5f D |
4472 | if (dev->pdev->revision >= 0x20) { |
4473 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
4474 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
4475 | } else { | |
4476 | /* For pre-production hardware */ | |
4477 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4478 | rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4479 | PUNIT_GPU_STATUS_MAX_FREQ_MASK); | |
4480 | } | |
7707df4a D |
4481 | return rp1; |
4482 | } | |
4483 | ||
03af2045 | 4484 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 4485 | { |
095acd5f | 4486 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
4487 | u32 val, rpn; |
4488 | ||
095acd5f D |
4489 | if (dev->pdev->revision >= 0x20) { |
4490 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
4491 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
4492 | FB_GFX_FREQ_FUSE_MASK); | |
4493 | } else { /* For pre-production hardware */ | |
4494 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4495 | rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & | |
4496 | PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK); | |
4497 | } | |
4498 | ||
2b6b3a09 D |
4499 | return rpn; |
4500 | } | |
4501 | ||
f8f2b001 D |
4502 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4503 | { | |
4504 | u32 val, rp1; | |
4505 | ||
4506 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4507 | ||
4508 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4509 | ||
4510 | return rp1; | |
4511 | } | |
4512 | ||
03af2045 | 4513 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
4514 | { |
4515 | u32 val, rp0; | |
4516 | ||
64936258 | 4517 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
4518 | |
4519 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4520 | /* Clamp to max */ | |
4521 | rp0 = min_t(u32, rp0, 0xea); | |
4522 | ||
4523 | return rp0; | |
4524 | } | |
4525 | ||
4526 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4527 | { | |
4528 | u32 val, rpe; | |
4529 | ||
64936258 | 4530 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 4531 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 4532 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
4533 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
4534 | ||
4535 | return rpe; | |
4536 | } | |
4537 | ||
03af2045 | 4538 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 4539 | { |
64936258 | 4540 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
4541 | } |
4542 | ||
ae48434c ID |
4543 | /* Check that the pctx buffer wasn't move under us. */ |
4544 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4545 | { | |
4546 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4547 | ||
4548 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4549 | dev_priv->vlv_pctx->stolen->start); | |
4550 | } | |
4551 | ||
38807746 D |
4552 | |
4553 | /* Check that the pcbr address is not empty. */ | |
4554 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4555 | { | |
4556 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4557 | ||
4558 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4559 | } | |
4560 | ||
4561 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4562 | { | |
4563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4564 | unsigned long pctx_paddr, paddr; | |
4565 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4566 | u32 pcbr; | |
4567 | int pctx_size = 32*1024; | |
4568 | ||
4569 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4570 | ||
4571 | pcbr = I915_READ(VLV_PCBR); | |
4572 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 4573 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 D |
4574 | paddr = (dev_priv->mm.stolen_base + |
4575 | (gtt->stolen_size - pctx_size)); | |
4576 | ||
4577 | pctx_paddr = (paddr & (~4095)); | |
4578 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4579 | } | |
ce611ef8 VS |
4580 | |
4581 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
4582 | } |
4583 | ||
c9cddffc JB |
4584 | static void valleyview_setup_pctx(struct drm_device *dev) |
4585 | { | |
4586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4587 | struct drm_i915_gem_object *pctx; | |
4588 | unsigned long pctx_paddr; | |
4589 | u32 pcbr; | |
4590 | int pctx_size = 24*1024; | |
4591 | ||
17b0c1f7 ID |
4592 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4593 | ||
c9cddffc JB |
4594 | pcbr = I915_READ(VLV_PCBR); |
4595 | if (pcbr) { | |
4596 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4597 | int pcbr_offset; | |
4598 | ||
4599 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4600 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4601 | pcbr_offset, | |
190d6cd5 | 4602 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
4603 | pctx_size); |
4604 | goto out; | |
4605 | } | |
4606 | ||
ce611ef8 VS |
4607 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
4608 | ||
c9cddffc JB |
4609 | /* |
4610 | * From the Gunit register HAS: | |
4611 | * The Gfx driver is expected to program this register and ensure | |
4612 | * proper allocation within Gfx stolen memory. For example, this | |
4613 | * register should be programmed such than the PCBR range does not | |
4614 | * overlap with other ranges, such as the frame buffer, protected | |
4615 | * memory, or any other relevant ranges. | |
4616 | */ | |
4617 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4618 | if (!pctx) { | |
4619 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4620 | return; | |
4621 | } | |
4622 | ||
4623 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4624 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4625 | ||
4626 | out: | |
ce611ef8 | 4627 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
4628 | dev_priv->vlv_pctx = pctx; |
4629 | } | |
4630 | ||
ae48434c ID |
4631 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
4632 | { | |
4633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4634 | ||
4635 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4636 | return; | |
4637 | ||
4638 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4639 | dev_priv->vlv_pctx = NULL; | |
4640 | } | |
4641 | ||
4e80519e ID |
4642 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
4643 | { | |
4644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 4645 | u32 val; |
4e80519e ID |
4646 | |
4647 | valleyview_setup_pctx(dev); | |
4648 | ||
4649 | mutex_lock(&dev_priv->rps.hw_lock); | |
4650 | ||
2bb25c17 VS |
4651 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
4652 | switch ((val >> 6) & 3) { | |
4653 | case 0: | |
4654 | case 1: | |
4655 | dev_priv->mem_freq = 800; | |
4656 | break; | |
4657 | case 2: | |
4658 | dev_priv->mem_freq = 1066; | |
4659 | break; | |
4660 | case 3: | |
4661 | dev_priv->mem_freq = 1333; | |
4662 | break; | |
4663 | } | |
80b83b62 | 4664 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4665 | |
4e80519e ID |
4666 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
4667 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4668 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4669 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
4670 | dev_priv->rps.max_freq); |
4671 | ||
4672 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4673 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4674 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
4675 | dev_priv->rps.efficient_freq); |
4676 | ||
f8f2b001 D |
4677 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
4678 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4679 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
4680 | dev_priv->rps.rp1_freq); |
4681 | ||
4e80519e ID |
4682 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
4683 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4684 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e ID |
4685 | dev_priv->rps.min_freq); |
4686 | ||
4687 | /* Preserve min/max settings in case of re-init */ | |
4688 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4689 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4690 | ||
4691 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4692 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4693 | ||
4694 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4695 | } | |
4696 | ||
38807746 D |
4697 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
4698 | { | |
2b6b3a09 | 4699 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 4700 | u32 val; |
2b6b3a09 | 4701 | |
38807746 | 4702 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
4703 | |
4704 | mutex_lock(&dev_priv->rps.hw_lock); | |
4705 | ||
c6e8f39d VS |
4706 | mutex_lock(&dev_priv->dpio_lock); |
4707 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); | |
4708 | mutex_unlock(&dev_priv->dpio_lock); | |
4709 | ||
2bb25c17 VS |
4710 | switch ((val >> 2) & 0x7) { |
4711 | case 0: | |
4712 | case 1: | |
4713 | dev_priv->rps.cz_freq = 200; | |
4714 | dev_priv->mem_freq = 1600; | |
4715 | break; | |
4716 | case 2: | |
4717 | dev_priv->rps.cz_freq = 267; | |
4718 | dev_priv->mem_freq = 1600; | |
4719 | break; | |
4720 | case 3: | |
4721 | dev_priv->rps.cz_freq = 333; | |
4722 | dev_priv->mem_freq = 2000; | |
4723 | break; | |
4724 | case 4: | |
4725 | dev_priv->rps.cz_freq = 320; | |
4726 | dev_priv->mem_freq = 1600; | |
4727 | break; | |
4728 | case 5: | |
4729 | dev_priv->rps.cz_freq = 400; | |
4730 | dev_priv->mem_freq = 1600; | |
4731 | break; | |
4732 | } | |
80b83b62 | 4733 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4734 | |
2b6b3a09 D |
4735 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
4736 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4737 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4738 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
4739 | dev_priv->rps.max_freq); |
4740 | ||
4741 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
4742 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4743 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
4744 | dev_priv->rps.efficient_freq); |
4745 | ||
7707df4a D |
4746 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
4747 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4748 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
4749 | dev_priv->rps.rp1_freq); |
4750 | ||
2b6b3a09 D |
4751 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
4752 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4753 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
4754 | dev_priv->rps.min_freq); |
4755 | ||
1c14762d VS |
4756 | WARN_ONCE((dev_priv->rps.max_freq | |
4757 | dev_priv->rps.efficient_freq | | |
4758 | dev_priv->rps.rp1_freq | | |
4759 | dev_priv->rps.min_freq) & 1, | |
4760 | "Odd GPU freq values\n"); | |
4761 | ||
2b6b3a09 D |
4762 | /* Preserve min/max settings in case of re-init */ |
4763 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4764 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4765 | ||
4766 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4767 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4768 | ||
4769 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
4770 | } |
4771 | ||
4e80519e ID |
4772 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
4773 | { | |
4774 | valleyview_cleanup_pctx(dev); | |
4775 | } | |
4776 | ||
38807746 D |
4777 | static void cherryview_enable_rps(struct drm_device *dev) |
4778 | { | |
4779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4780 | struct intel_engine_cs *ring; | |
2b6b3a09 | 4781 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
4782 | int i; |
4783 | ||
4784 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4785 | ||
4786 | gtfifodbg = I915_READ(GTFIFODBG); | |
4787 | if (gtfifodbg) { | |
4788 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4789 | gtfifodbg); | |
4790 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4791 | } | |
4792 | ||
4793 | cherryview_check_pctx(dev_priv); | |
4794 | ||
4795 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
4796 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4797 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 4798 | |
160614a2 VS |
4799 | /* Disable RC states. */ |
4800 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4801 | ||
38807746 D |
4802 | /* 2a: Program RC6 thresholds.*/ |
4803 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4804 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4805 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4806 | ||
4807 | for_each_ring(ring, dev_priv, i) | |
4808 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4809 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4810 | ||
af5a75a3 VS |
4811 | /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ |
4812 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); | |
38807746 D |
4813 | |
4814 | /* allows RC6 residency counter to work */ | |
4815 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4816 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4817 | VLV_MEDIA_RC6_COUNT_EN | | |
4818 | VLV_RENDER_RC6_COUNT_EN)); | |
4819 | ||
4820 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
4821 | pcbr = I915_READ(VLV_PCBR); | |
4822 | ||
38807746 D |
4823 | /* 3: Enable RC6 */ |
4824 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
4825 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 4826 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
4827 | |
4828 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4829 | ||
2b6b3a09 | 4830 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 4831 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
4832 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
4833 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4834 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4835 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4836 | ||
4837 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4838 | ||
4839 | /* 5: Enable RPS */ | |
4840 | I915_WRITE(GEN6_RP_CONTROL, | |
4841 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 4842 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
4843 | GEN6_RP_ENABLE | |
4844 | GEN6_RP_UP_BUSY_AVG | | |
4845 | GEN6_RP_DOWN_IDLE_AVG); | |
4846 | ||
4847 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4848 | ||
8d40c3ae VS |
4849 | /* RPS code assumes GPLL is used */ |
4850 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
4851 | ||
c8e9627d | 4852 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
2b6b3a09 D |
4853 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
4854 | ||
4855 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4856 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4857 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
2b6b3a09 D |
4858 | dev_priv->rps.cur_freq); |
4859 | ||
4860 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
7c59a9c1 | 4861 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
4862 | dev_priv->rps.efficient_freq); |
4863 | ||
4864 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
4865 | ||
59bad947 | 4866 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
4867 | } |
4868 | ||
0a073b84 JB |
4869 | static void valleyview_enable_rps(struct drm_device *dev) |
4870 | { | |
4871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4872 | struct intel_engine_cs *ring; |
2a5913a8 | 4873 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
4874 | int i; |
4875 | ||
4876 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4877 | ||
ae48434c ID |
4878 | valleyview_check_pctx(dev_priv); |
4879 | ||
0a073b84 | 4880 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
4881 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
4882 | gtfifodbg); | |
0a073b84 JB |
4883 | I915_WRITE(GTFIFODBG, gtfifodbg); |
4884 | } | |
4885 | ||
c8d9a590 | 4886 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 4887 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 4888 | |
160614a2 VS |
4889 | /* Disable RC states. */ |
4890 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4891 | ||
cad725fe | 4892 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
4893 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
4894 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4895 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4896 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4897 | ||
4898 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4899 | ||
4900 | I915_WRITE(GEN6_RP_CONTROL, | |
4901 | GEN6_RP_MEDIA_TURBO | | |
4902 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4903 | GEN6_RP_MEDIA_IS_GFX | | |
4904 | GEN6_RP_ENABLE | | |
4905 | GEN6_RP_UP_BUSY_AVG | | |
4906 | GEN6_RP_DOWN_IDLE_CONT); | |
4907 | ||
4908 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
4909 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4910 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4911 | ||
4912 | for_each_ring(ring, dev_priv, i) | |
4913 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4914 | ||
2f0aa304 | 4915 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
4916 | |
4917 | /* allows RC6 residency counter to work */ | |
49798eb2 | 4918 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
4919 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
4920 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
4921 | VLV_MEDIA_RC6_COUNT_EN | |
4922 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 4923 | |
a2b23fe0 | 4924 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 4925 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
4926 | |
4927 | intel_print_rc6_info(dev, rc6_mode); | |
4928 | ||
a2b23fe0 | 4929 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 4930 | |
64936258 | 4931 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 4932 | |
8d40c3ae VS |
4933 | /* RPS code assumes GPLL is used */ |
4934 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
4935 | ||
c8e9627d | 4936 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
0a073b84 JB |
4937 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
4938 | ||
b39fb297 | 4939 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 4940 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 4941 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
b39fb297 | 4942 | dev_priv->rps.cur_freq); |
0a073b84 | 4943 | |
73008b98 | 4944 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
7c59a9c1 | 4945 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
b39fb297 | 4946 | dev_priv->rps.efficient_freq); |
0a073b84 | 4947 | |
b39fb297 | 4948 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 4949 | |
59bad947 | 4950 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
4951 | } |
4952 | ||
930ebb46 | 4953 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
4954 | { |
4955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4956 | ||
3e373948 | 4957 | if (dev_priv->ips.renderctx) { |
d7f46fc4 | 4958 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
3e373948 DV |
4959 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
4960 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
4961 | } |
4962 | ||
3e373948 | 4963 | if (dev_priv->ips.pwrctx) { |
d7f46fc4 | 4964 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
3e373948 DV |
4965 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
4966 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
4967 | } |
4968 | } | |
4969 | ||
930ebb46 | 4970 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
4971 | { |
4972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4973 | ||
4974 | if (I915_READ(PWRCTXA)) { | |
4975 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
4976 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
4977 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
4978 | 50); | |
4979 | ||
4980 | I915_WRITE(PWRCTXA, 0); | |
4981 | POSTING_READ(PWRCTXA); | |
4982 | ||
4983 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
4984 | POSTING_READ(RSTDBYCTL); | |
4985 | } | |
2b4e57bd ED |
4986 | } |
4987 | ||
4988 | static int ironlake_setup_rc6(struct drm_device *dev) | |
4989 | { | |
4990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4991 | ||
3e373948 DV |
4992 | if (dev_priv->ips.renderctx == NULL) |
4993 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
4994 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
4995 | return -ENOMEM; |
4996 | ||
3e373948 DV |
4997 | if (dev_priv->ips.pwrctx == NULL) |
4998 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
4999 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
5000 | ironlake_teardown_rc6(dev); |
5001 | return -ENOMEM; | |
5002 | } | |
5003 | ||
5004 | return 0; | |
5005 | } | |
5006 | ||
930ebb46 | 5007 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
5008 | { |
5009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5010 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e960501 | 5011 | bool was_interruptible; |
2b4e57bd ED |
5012 | int ret; |
5013 | ||
5014 | /* rc6 disabled by default due to repeated reports of hanging during | |
5015 | * boot and resume. | |
5016 | */ | |
5017 | if (!intel_enable_rc6(dev)) | |
5018 | return; | |
5019 | ||
79f5b2c7 DV |
5020 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5021 | ||
2b4e57bd | 5022 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 5023 | if (ret) |
2b4e57bd | 5024 | return; |
2b4e57bd | 5025 | |
3e960501 CW |
5026 | was_interruptible = dev_priv->mm.interruptible; |
5027 | dev_priv->mm.interruptible = false; | |
5028 | ||
2b4e57bd ED |
5029 | /* |
5030 | * GPU can automatically power down the render unit if given a page | |
5031 | * to save state. | |
5032 | */ | |
6d90c952 | 5033 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
5034 | if (ret) { |
5035 | ironlake_teardown_rc6(dev); | |
3e960501 | 5036 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
5037 | return; |
5038 | } | |
5039 | ||
6d90c952 DV |
5040 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
5041 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 5042 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
6d90c952 DV |
5043 | MI_MM_SPACE_GTT | |
5044 | MI_SAVE_EXT_STATE_EN | | |
5045 | MI_RESTORE_EXT_STATE_EN | | |
5046 | MI_RESTORE_INHIBIT); | |
5047 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
5048 | intel_ring_emit(ring, MI_NOOP); | |
5049 | intel_ring_emit(ring, MI_FLUSH); | |
5050 | intel_ring_advance(ring); | |
2b4e57bd ED |
5051 | |
5052 | /* | |
5053 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
5054 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
5055 | * safe to assume that renderctx is valid | |
5056 | */ | |
3e960501 CW |
5057 | ret = intel_ring_idle(ring); |
5058 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 5059 | if (ret) { |
def27a58 | 5060 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 5061 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
5062 | return; |
5063 | } | |
5064 | ||
f343c5f6 | 5065 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
2b4e57bd | 5066 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
dc39fff7 | 5067 | |
91ca689a | 5068 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
2b4e57bd ED |
5069 | } |
5070 | ||
dde18883 ED |
5071 | static unsigned long intel_pxfreq(u32 vidfreq) |
5072 | { | |
5073 | unsigned long freq; | |
5074 | int div = (vidfreq & 0x3f0000) >> 16; | |
5075 | int post = (vidfreq & 0x3000) >> 12; | |
5076 | int pre = (vidfreq & 0x7); | |
5077 | ||
5078 | if (!pre) | |
5079 | return 0; | |
5080 | ||
5081 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5082 | ||
5083 | return freq; | |
5084 | } | |
5085 | ||
eb48eb00 DV |
5086 | static const struct cparams { |
5087 | u16 i; | |
5088 | u16 t; | |
5089 | u16 m; | |
5090 | u16 c; | |
5091 | } cparams[] = { | |
5092 | { 1, 1333, 301, 28664 }, | |
5093 | { 1, 1066, 294, 24460 }, | |
5094 | { 1, 800, 294, 25192 }, | |
5095 | { 0, 1333, 276, 27605 }, | |
5096 | { 0, 1066, 276, 27605 }, | |
5097 | { 0, 800, 231, 23784 }, | |
5098 | }; | |
5099 | ||
f531dcb2 | 5100 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5101 | { |
5102 | u64 total_count, diff, ret; | |
5103 | u32 count1, count2, count3, m = 0, c = 0; | |
5104 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5105 | int i; | |
5106 | ||
02d71956 DV |
5107 | assert_spin_locked(&mchdev_lock); |
5108 | ||
20e4d407 | 5109 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5110 | |
5111 | /* Prevent division-by-zero if we are asking too fast. | |
5112 | * Also, we don't get interesting results if we are polling | |
5113 | * faster than once in 10ms, so just return the saved value | |
5114 | * in such cases. | |
5115 | */ | |
5116 | if (diff1 <= 10) | |
20e4d407 | 5117 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5118 | |
5119 | count1 = I915_READ(DMIEC); | |
5120 | count2 = I915_READ(DDREC); | |
5121 | count3 = I915_READ(CSIEC); | |
5122 | ||
5123 | total_count = count1 + count2 + count3; | |
5124 | ||
5125 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5126 | if (total_count < dev_priv->ips.last_count1) { |
5127 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5128 | diff += total_count; |
5129 | } else { | |
20e4d407 | 5130 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5131 | } |
5132 | ||
5133 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5134 | if (cparams[i].i == dev_priv->ips.c_m && |
5135 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5136 | m = cparams[i].m; |
5137 | c = cparams[i].c; | |
5138 | break; | |
5139 | } | |
5140 | } | |
5141 | ||
5142 | diff = div_u64(diff, diff1); | |
5143 | ret = ((m * diff) + c); | |
5144 | ret = div_u64(ret, 10); | |
5145 | ||
20e4d407 DV |
5146 | dev_priv->ips.last_count1 = total_count; |
5147 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5148 | |
20e4d407 | 5149 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5150 | |
5151 | return ret; | |
5152 | } | |
5153 | ||
f531dcb2 CW |
5154 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5155 | { | |
3d13ef2e | 5156 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5157 | unsigned long val; |
5158 | ||
3d13ef2e | 5159 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5160 | return 0; |
5161 | ||
5162 | spin_lock_irq(&mchdev_lock); | |
5163 | ||
5164 | val = __i915_chipset_val(dev_priv); | |
5165 | ||
5166 | spin_unlock_irq(&mchdev_lock); | |
5167 | ||
5168 | return val; | |
5169 | } | |
5170 | ||
eb48eb00 DV |
5171 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5172 | { | |
5173 | unsigned long m, x, b; | |
5174 | u32 tsfs; | |
5175 | ||
5176 | tsfs = I915_READ(TSFS); | |
5177 | ||
5178 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5179 | x = I915_READ8(TR1); | |
5180 | ||
5181 | b = tsfs & TSFS_INTR_MASK; | |
5182 | ||
5183 | return ((m * x) / 127) - b; | |
5184 | } | |
5185 | ||
d972d6ee MK |
5186 | static int _pxvid_to_vd(u8 pxvid) |
5187 | { | |
5188 | if (pxvid == 0) | |
5189 | return 0; | |
5190 | ||
5191 | if (pxvid >= 8 && pxvid < 31) | |
5192 | pxvid = 31; | |
5193 | ||
5194 | return (pxvid + 2) * 125; | |
5195 | } | |
5196 | ||
5197 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 5198 | { |
3d13ef2e | 5199 | struct drm_device *dev = dev_priv->dev; |
d972d6ee MK |
5200 | const int vd = _pxvid_to_vd(pxvid); |
5201 | const int vm = vd - 1125; | |
5202 | ||
3d13ef2e | 5203 | if (INTEL_INFO(dev)->is_mobile) |
d972d6ee MK |
5204 | return vm > 0 ? vm : 0; |
5205 | ||
5206 | return vd; | |
eb48eb00 DV |
5207 | } |
5208 | ||
02d71956 | 5209 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5210 | { |
5ed0bdf2 | 5211 | u64 now, diff, diffms; |
eb48eb00 DV |
5212 | u32 count; |
5213 | ||
02d71956 | 5214 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5215 | |
5ed0bdf2 TG |
5216 | now = ktime_get_raw_ns(); |
5217 | diffms = now - dev_priv->ips.last_time2; | |
5218 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5219 | |
5220 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5221 | if (!diffms) |
5222 | return; | |
5223 | ||
5224 | count = I915_READ(GFXEC); | |
5225 | ||
20e4d407 DV |
5226 | if (count < dev_priv->ips.last_count2) { |
5227 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5228 | diff += count; |
5229 | } else { | |
20e4d407 | 5230 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5231 | } |
5232 | ||
20e4d407 DV |
5233 | dev_priv->ips.last_count2 = count; |
5234 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5235 | |
5236 | /* More magic constants... */ | |
5237 | diff = diff * 1181; | |
5238 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5239 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5240 | } |
5241 | ||
02d71956 DV |
5242 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5243 | { | |
3d13ef2e DL |
5244 | struct drm_device *dev = dev_priv->dev; |
5245 | ||
5246 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5247 | return; |
5248 | ||
9270388e | 5249 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5250 | |
5251 | __i915_update_gfx_val(dev_priv); | |
5252 | ||
9270388e | 5253 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5254 | } |
5255 | ||
f531dcb2 | 5256 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5257 | { |
5258 | unsigned long t, corr, state1, corr2, state2; | |
5259 | u32 pxvid, ext_v; | |
5260 | ||
02d71956 DV |
5261 | assert_spin_locked(&mchdev_lock); |
5262 | ||
b39fb297 | 5263 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
5264 | pxvid = (pxvid >> 24) & 0x7f; |
5265 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5266 | ||
5267 | state1 = ext_v; | |
5268 | ||
5269 | t = i915_mch_val(dev_priv); | |
5270 | ||
5271 | /* Revel in the empirically derived constants */ | |
5272 | ||
5273 | /* Correction factor in 1/100000 units */ | |
5274 | if (t > 80) | |
5275 | corr = ((t * 2349) + 135940); | |
5276 | else if (t >= 50) | |
5277 | corr = ((t * 964) + 29317); | |
5278 | else /* < 50 */ | |
5279 | corr = ((t * 301) + 1004); | |
5280 | ||
5281 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5282 | corr /= 100000; | |
20e4d407 | 5283 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5284 | |
5285 | state2 = (corr2 * state1) / 10000; | |
5286 | state2 /= 100; /* convert to mW */ | |
5287 | ||
02d71956 | 5288 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5289 | |
20e4d407 | 5290 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5291 | } |
5292 | ||
f531dcb2 CW |
5293 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5294 | { | |
3d13ef2e | 5295 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5296 | unsigned long val; |
5297 | ||
3d13ef2e | 5298 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5299 | return 0; |
5300 | ||
5301 | spin_lock_irq(&mchdev_lock); | |
5302 | ||
5303 | val = __i915_gfx_val(dev_priv); | |
5304 | ||
5305 | spin_unlock_irq(&mchdev_lock); | |
5306 | ||
5307 | return val; | |
5308 | } | |
5309 | ||
eb48eb00 DV |
5310 | /** |
5311 | * i915_read_mch_val - return value for IPS use | |
5312 | * | |
5313 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5314 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5315 | */ | |
5316 | unsigned long i915_read_mch_val(void) | |
5317 | { | |
5318 | struct drm_i915_private *dev_priv; | |
5319 | unsigned long chipset_val, graphics_val, ret = 0; | |
5320 | ||
9270388e | 5321 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5322 | if (!i915_mch_dev) |
5323 | goto out_unlock; | |
5324 | dev_priv = i915_mch_dev; | |
5325 | ||
f531dcb2 CW |
5326 | chipset_val = __i915_chipset_val(dev_priv); |
5327 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5328 | |
5329 | ret = chipset_val + graphics_val; | |
5330 | ||
5331 | out_unlock: | |
9270388e | 5332 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5333 | |
5334 | return ret; | |
5335 | } | |
5336 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5337 | ||
5338 | /** | |
5339 | * i915_gpu_raise - raise GPU frequency limit | |
5340 | * | |
5341 | * Raise the limit; IPS indicates we have thermal headroom. | |
5342 | */ | |
5343 | bool i915_gpu_raise(void) | |
5344 | { | |
5345 | struct drm_i915_private *dev_priv; | |
5346 | bool ret = true; | |
5347 | ||
9270388e | 5348 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5349 | if (!i915_mch_dev) { |
5350 | ret = false; | |
5351 | goto out_unlock; | |
5352 | } | |
5353 | dev_priv = i915_mch_dev; | |
5354 | ||
20e4d407 DV |
5355 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5356 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5357 | |
5358 | out_unlock: | |
9270388e | 5359 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5360 | |
5361 | return ret; | |
5362 | } | |
5363 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5364 | ||
5365 | /** | |
5366 | * i915_gpu_lower - lower GPU frequency limit | |
5367 | * | |
5368 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5369 | * frequency maximum. | |
5370 | */ | |
5371 | bool i915_gpu_lower(void) | |
5372 | { | |
5373 | struct drm_i915_private *dev_priv; | |
5374 | bool ret = true; | |
5375 | ||
9270388e | 5376 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5377 | if (!i915_mch_dev) { |
5378 | ret = false; | |
5379 | goto out_unlock; | |
5380 | } | |
5381 | dev_priv = i915_mch_dev; | |
5382 | ||
20e4d407 DV |
5383 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5384 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5385 | |
5386 | out_unlock: | |
9270388e | 5387 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5388 | |
5389 | return ret; | |
5390 | } | |
5391 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5392 | ||
5393 | /** | |
5394 | * i915_gpu_busy - indicate GPU business to IPS | |
5395 | * | |
5396 | * Tell the IPS driver whether or not the GPU is busy. | |
5397 | */ | |
5398 | bool i915_gpu_busy(void) | |
5399 | { | |
5400 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5401 | struct intel_engine_cs *ring; |
eb48eb00 | 5402 | bool ret = false; |
f047e395 | 5403 | int i; |
eb48eb00 | 5404 | |
9270388e | 5405 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5406 | if (!i915_mch_dev) |
5407 | goto out_unlock; | |
5408 | dev_priv = i915_mch_dev; | |
5409 | ||
f047e395 CW |
5410 | for_each_ring(ring, dev_priv, i) |
5411 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5412 | |
5413 | out_unlock: | |
9270388e | 5414 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5415 | |
5416 | return ret; | |
5417 | } | |
5418 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5419 | ||
5420 | /** | |
5421 | * i915_gpu_turbo_disable - disable graphics turbo | |
5422 | * | |
5423 | * Disable graphics turbo by resetting the max frequency and setting the | |
5424 | * current frequency to the default. | |
5425 | */ | |
5426 | bool i915_gpu_turbo_disable(void) | |
5427 | { | |
5428 | struct drm_i915_private *dev_priv; | |
5429 | bool ret = true; | |
5430 | ||
9270388e | 5431 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5432 | if (!i915_mch_dev) { |
5433 | ret = false; | |
5434 | goto out_unlock; | |
5435 | } | |
5436 | dev_priv = i915_mch_dev; | |
5437 | ||
20e4d407 | 5438 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5439 | |
20e4d407 | 5440 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5441 | ret = false; |
5442 | ||
5443 | out_unlock: | |
9270388e | 5444 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5445 | |
5446 | return ret; | |
5447 | } | |
5448 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5449 | ||
5450 | /** | |
5451 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5452 | * IPS got loaded first. | |
5453 | * | |
5454 | * This awkward dance is so that neither module has to depend on the | |
5455 | * other in order for IPS to do the appropriate communication of | |
5456 | * GPU turbo limits to i915. | |
5457 | */ | |
5458 | static void | |
5459 | ips_ping_for_i915_load(void) | |
5460 | { | |
5461 | void (*link)(void); | |
5462 | ||
5463 | link = symbol_get(ips_link_to_i915_driver); | |
5464 | if (link) { | |
5465 | link(); | |
5466 | symbol_put(ips_link_to_i915_driver); | |
5467 | } | |
5468 | } | |
5469 | ||
5470 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5471 | { | |
02d71956 DV |
5472 | /* We only register the i915 ips part with intel-ips once everything is |
5473 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5474 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5475 | i915_mch_dev = dev_priv; |
9270388e | 5476 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5477 | |
5478 | ips_ping_for_i915_load(); | |
5479 | } | |
5480 | ||
5481 | void intel_gpu_ips_teardown(void) | |
5482 | { | |
9270388e | 5483 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5484 | i915_mch_dev = NULL; |
9270388e | 5485 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5486 | } |
76c3552f | 5487 | |
8090c6b9 | 5488 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5489 | { |
5490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5491 | u32 lcfuse; | |
5492 | u8 pxw[16]; | |
5493 | int i; | |
5494 | ||
5495 | /* Disable to program */ | |
5496 | I915_WRITE(ECR, 0); | |
5497 | POSTING_READ(ECR); | |
5498 | ||
5499 | /* Program energy weights for various events */ | |
5500 | I915_WRITE(SDEW, 0x15040d00); | |
5501 | I915_WRITE(CSIEW0, 0x007f0000); | |
5502 | I915_WRITE(CSIEW1, 0x1e220004); | |
5503 | I915_WRITE(CSIEW2, 0x04000004); | |
5504 | ||
5505 | for (i = 0; i < 5; i++) | |
5506 | I915_WRITE(PEW + (i * 4), 0); | |
5507 | for (i = 0; i < 3; i++) | |
5508 | I915_WRITE(DEW + (i * 4), 0); | |
5509 | ||
5510 | /* Program P-state weights to account for frequency power adjustment */ | |
5511 | for (i = 0; i < 16; i++) { | |
5512 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5513 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5514 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5515 | PXVFREQ_PX_SHIFT; | |
5516 | unsigned long val; | |
5517 | ||
5518 | val = vid * vid; | |
5519 | val *= (freq / 1000); | |
5520 | val *= 255; | |
5521 | val /= (127*127*900); | |
5522 | if (val > 0xff) | |
5523 | DRM_ERROR("bad pxval: %ld\n", val); | |
5524 | pxw[i] = val; | |
5525 | } | |
5526 | /* Render standby states get 0 weight */ | |
5527 | pxw[14] = 0; | |
5528 | pxw[15] = 0; | |
5529 | ||
5530 | for (i = 0; i < 4; i++) { | |
5531 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5532 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5533 | I915_WRITE(PXW + (i * 4), val); | |
5534 | } | |
5535 | ||
5536 | /* Adjust magic regs to magic values (more experimental results) */ | |
5537 | I915_WRITE(OGW0, 0); | |
5538 | I915_WRITE(OGW1, 0); | |
5539 | I915_WRITE(EG0, 0x00007f00); | |
5540 | I915_WRITE(EG1, 0x0000000e); | |
5541 | I915_WRITE(EG2, 0x000e0000); | |
5542 | I915_WRITE(EG3, 0x68000300); | |
5543 | I915_WRITE(EG4, 0x42000000); | |
5544 | I915_WRITE(EG5, 0x00140031); | |
5545 | I915_WRITE(EG6, 0); | |
5546 | I915_WRITE(EG7, 0); | |
5547 | ||
5548 | for (i = 0; i < 8; i++) | |
5549 | I915_WRITE(PXWL + (i * 4), 0); | |
5550 | ||
5551 | /* Enable PMON + select events */ | |
5552 | I915_WRITE(ECR, 0x80000019); | |
5553 | ||
5554 | lcfuse = I915_READ(LCFUSE02); | |
5555 | ||
20e4d407 | 5556 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5557 | } |
5558 | ||
ae48434c ID |
5559 | void intel_init_gt_powersave(struct drm_device *dev) |
5560 | { | |
e6069ca8 ID |
5561 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5562 | ||
38807746 D |
5563 | if (IS_CHERRYVIEW(dev)) |
5564 | cherryview_init_gt_powersave(dev); | |
5565 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5566 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
5567 | } |
5568 | ||
5569 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5570 | { | |
38807746 D |
5571 | if (IS_CHERRYVIEW(dev)) |
5572 | return; | |
5573 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5574 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
5575 | } |
5576 | ||
dbea3cea ID |
5577 | static void gen6_suspend_rps(struct drm_device *dev) |
5578 | { | |
5579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5580 | ||
5581 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
5582 | ||
5583 | /* | |
5584 | * TODO: disable RPS interrupts on GEN9+ too once RPS support | |
5585 | * is added for it. | |
5586 | */ | |
5587 | if (INTEL_INFO(dev)->gen < 9) | |
5588 | gen6_disable_rps_interrupts(dev); | |
5589 | } | |
5590 | ||
156c7ca0 JB |
5591 | /** |
5592 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
5593 | * @dev: drm device | |
5594 | * | |
5595 | * We don't want to disable RC6 or other features here, we just want | |
5596 | * to make sure any work we've queued has finished and won't bother | |
5597 | * us while we're suspended. | |
5598 | */ | |
5599 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
5600 | { | |
5601 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5602 | ||
d4d70aa5 ID |
5603 | if (INTEL_INFO(dev)->gen < 6) |
5604 | return; | |
5605 | ||
dbea3cea | 5606 | gen6_suspend_rps(dev); |
b47adc17 D |
5607 | |
5608 | /* Force GPU to min freq during suspend */ | |
5609 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
5610 | } |
5611 | ||
8090c6b9 DV |
5612 | void intel_disable_gt_powersave(struct drm_device *dev) |
5613 | { | |
1a01ab3b JB |
5614 | struct drm_i915_private *dev_priv = dev->dev_private; |
5615 | ||
930ebb46 | 5616 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 5617 | ironlake_disable_drps(dev); |
930ebb46 | 5618 | ironlake_disable_rc6(dev); |
38807746 | 5619 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 5620 | intel_suspend_gt_powersave(dev); |
e494837a | 5621 | |
4fc688ce | 5622 | mutex_lock(&dev_priv->rps.hw_lock); |
20e49366 ZW |
5623 | if (INTEL_INFO(dev)->gen >= 9) |
5624 | gen9_disable_rps(dev); | |
5625 | else if (IS_CHERRYVIEW(dev)) | |
38807746 D |
5626 | cherryview_disable_rps(dev); |
5627 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
5628 | valleyview_disable_rps(dev); |
5629 | else | |
5630 | gen6_disable_rps(dev); | |
e534770a | 5631 | |
c0951f0c | 5632 | dev_priv->rps.enabled = false; |
4fc688ce | 5633 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 5634 | } |
8090c6b9 DV |
5635 | } |
5636 | ||
1a01ab3b JB |
5637 | static void intel_gen6_powersave_work(struct work_struct *work) |
5638 | { | |
5639 | struct drm_i915_private *dev_priv = | |
5640 | container_of(work, struct drm_i915_private, | |
5641 | rps.delayed_resume_work.work); | |
5642 | struct drm_device *dev = dev_priv->dev; | |
5643 | ||
4fc688ce | 5644 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 5645 | |
3cc134e3 ID |
5646 | /* |
5647 | * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is | |
5648 | * added for it. | |
5649 | */ | |
5650 | if (INTEL_INFO(dev)->gen < 9) | |
5651 | gen6_reset_rps_interrupts(dev); | |
5652 | ||
38807746 D |
5653 | if (IS_CHERRYVIEW(dev)) { |
5654 | cherryview_enable_rps(dev); | |
5655 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 5656 | valleyview_enable_rps(dev); |
20e49366 | 5657 | } else if (INTEL_INFO(dev)->gen >= 9) { |
b6fef0ef | 5658 | gen9_enable_rc6(dev); |
20e49366 | 5659 | gen9_enable_rps(dev); |
b6fef0ef | 5660 | __gen6_update_ring_freq(dev); |
6edee7f3 BW |
5661 | } else if (IS_BROADWELL(dev)) { |
5662 | gen8_enable_rps(dev); | |
c2bc2fc5 | 5663 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
5664 | } else { |
5665 | gen6_enable_rps(dev); | |
c2bc2fc5 | 5666 | __gen6_update_ring_freq(dev); |
0a073b84 | 5667 | } |
c0951f0c | 5668 | dev_priv->rps.enabled = true; |
3cc134e3 ID |
5669 | |
5670 | if (INTEL_INFO(dev)->gen < 9) | |
5671 | gen6_enable_rps_interrupts(dev); | |
5672 | ||
4fc688ce | 5673 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
5674 | |
5675 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
5676 | } |
5677 | ||
8090c6b9 DV |
5678 | void intel_enable_gt_powersave(struct drm_device *dev) |
5679 | { | |
1a01ab3b JB |
5680 | struct drm_i915_private *dev_priv = dev->dev_private; |
5681 | ||
f61018b1 YZ |
5682 | /* Powersaving is controlled by the host when inside a VM */ |
5683 | if (intel_vgpu_active(dev)) | |
5684 | return; | |
5685 | ||
8090c6b9 | 5686 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 5687 | mutex_lock(&dev->struct_mutex); |
8090c6b9 DV |
5688 | ironlake_enable_drps(dev); |
5689 | ironlake_enable_rc6(dev); | |
5690 | intel_init_emon(dev); | |
dc1d0136 | 5691 | mutex_unlock(&dev->struct_mutex); |
38807746 | 5692 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
5693 | /* |
5694 | * PCU communication is slow and this doesn't need to be | |
5695 | * done at any specific time, so do this out of our fast path | |
5696 | * to make resume and init faster. | |
c6df39b5 ID |
5697 | * |
5698 | * We depend on the HW RC6 power context save/restore | |
5699 | * mechanism when entering D3 through runtime PM suspend. So | |
5700 | * disable RPM until RPS/RC6 is properly setup. We can only | |
5701 | * get here via the driver load/system resume/runtime resume | |
5702 | * paths, so the _noresume version is enough (and in case of | |
5703 | * runtime resume it's necessary). | |
1a01ab3b | 5704 | */ |
c6df39b5 ID |
5705 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
5706 | round_jiffies_up_relative(HZ))) | |
5707 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
5708 | } |
5709 | } | |
5710 | ||
c6df39b5 ID |
5711 | void intel_reset_gt_powersave(struct drm_device *dev) |
5712 | { | |
5713 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5714 | ||
dbea3cea ID |
5715 | if (INTEL_INFO(dev)->gen < 6) |
5716 | return; | |
5717 | ||
5718 | gen6_suspend_rps(dev); | |
c6df39b5 | 5719 | dev_priv->rps.enabled = false; |
c6df39b5 ID |
5720 | } |
5721 | ||
3107bd48 DV |
5722 | static void ibx_init_clock_gating(struct drm_device *dev) |
5723 | { | |
5724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5725 | ||
5726 | /* | |
5727 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5728 | * gating for the panel power sequencer or it will fail to | |
5729 | * start up when no ports are active. | |
5730 | */ | |
5731 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5732 | } | |
5733 | ||
0e088b8f VS |
5734 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
5735 | { | |
5736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5737 | int pipe; | |
5738 | ||
055e393f | 5739 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
5740 | I915_WRITE(DSPCNTR(pipe), |
5741 | I915_READ(DSPCNTR(pipe)) | | |
5742 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 5743 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
5744 | } |
5745 | } | |
5746 | ||
017636cc VS |
5747 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
5748 | { | |
5749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5750 | ||
5751 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5752 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5753 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5754 | ||
5755 | /* | |
5756 | * Don't touch WM1S_LP_EN here. | |
5757 | * Doing so could cause underruns. | |
5758 | */ | |
5759 | } | |
5760 | ||
1fa61106 | 5761 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5762 | { |
5763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5764 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5765 | |
f1e8fa56 DL |
5766 | /* |
5767 | * Required for FBC | |
5768 | * WaFbcDisableDpfcClockGating:ilk | |
5769 | */ | |
4d47e4f5 DL |
5770 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
5771 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5772 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
5773 | |
5774 | I915_WRITE(PCH_3DCGDIS0, | |
5775 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5776 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5777 | I915_WRITE(PCH_3DCGDIS1, | |
5778 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5779 | ||
6f1d69b0 ED |
5780 | /* |
5781 | * According to the spec the following bits should be set in | |
5782 | * order to enable memory self-refresh | |
5783 | * The bit 22/21 of 0x42004 | |
5784 | * The bit 5 of 0x42020 | |
5785 | * The bit 15 of 0x45000 | |
5786 | */ | |
5787 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5788 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5789 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 5790 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
5791 | I915_WRITE(DISP_ARB_CTL, |
5792 | (I915_READ(DISP_ARB_CTL) | | |
5793 | DISP_FBC_WM_DIS)); | |
017636cc VS |
5794 | |
5795 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
5796 | |
5797 | /* | |
5798 | * Based on the document from hardware guys the following bits | |
5799 | * should be set unconditionally in order to enable FBC. | |
5800 | * The bit 22 of 0x42000 | |
5801 | * The bit 22 of 0x42004 | |
5802 | * The bit 7,8,9 of 0x42020. | |
5803 | */ | |
5804 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 5805 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
5806 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
5807 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5808 | ILK_FBCQ_DIS); | |
5809 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5810 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5811 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
5812 | } |
5813 | ||
4d47e4f5 DL |
5814 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
5815 | ||
6f1d69b0 ED |
5816 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5817 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5818 | ILK_ELPIN_409_SELECT); | |
5819 | I915_WRITE(_3D_CHICKEN2, | |
5820 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5821 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 5822 | |
ecdb4eb7 | 5823 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
5824 | I915_WRITE(CACHE_MODE_0, |
5825 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 5826 | |
4e04632e AG |
5827 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
5828 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5829 | ||
0e088b8f | 5830 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 5831 | |
3107bd48 DV |
5832 | ibx_init_clock_gating(dev); |
5833 | } | |
5834 | ||
5835 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5836 | { | |
5837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5838 | int pipe; | |
3f704fa2 | 5839 | uint32_t val; |
3107bd48 DV |
5840 | |
5841 | /* | |
5842 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5843 | * gating for the panel power sequencer or it will fail to | |
5844 | * start up when no ports are active. | |
5845 | */ | |
cd664078 JB |
5846 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
5847 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
5848 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
5849 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
5850 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
5851 | /* The below fixes the weird display corruption, a few pixels shifted |
5852 | * downward, on (only) LVDS of some HP laptops with IVY. | |
5853 | */ | |
055e393f | 5854 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
5855 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
5856 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
5857 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 5858 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 5859 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
5860 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
5861 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
5862 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
5863 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
5864 | } | |
3107bd48 | 5865 | /* WADP0ClockGatingDisable */ |
055e393f | 5866 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
5867 | I915_WRITE(TRANS_CHICKEN1(pipe), |
5868 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5869 | } | |
6f1d69b0 ED |
5870 | } |
5871 | ||
1d7aaa0c DV |
5872 | static void gen6_check_mch_setup(struct drm_device *dev) |
5873 | { | |
5874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5875 | uint32_t tmp; | |
5876 | ||
5877 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
5878 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
5879 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
5880 | tmp); | |
1d7aaa0c DV |
5881 | } |
5882 | ||
1fa61106 | 5883 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5884 | { |
5885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5886 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5887 | |
231e54f6 | 5888 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
5889 | |
5890 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5891 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5892 | ILK_ELPIN_409_SELECT); | |
5893 | ||
ecdb4eb7 | 5894 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
5895 | I915_WRITE(_3D_CHICKEN, |
5896 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
5897 | ||
4e04632e AG |
5898 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
5899 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5900 | ||
8d85d272 VS |
5901 | /* |
5902 | * BSpec recoomends 8x4 when MSAA is used, | |
5903 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5904 | * |
5905 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5906 | * disable bit, which we don't touch here, but it's good | |
5907 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
5908 | */ |
5909 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 5910 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 5911 | |
017636cc | 5912 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5913 | |
6f1d69b0 | 5914 | I915_WRITE(CACHE_MODE_0, |
50743298 | 5915 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
5916 | |
5917 | I915_WRITE(GEN6_UCGCTL1, | |
5918 | I915_READ(GEN6_UCGCTL1) | | |
5919 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
5920 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
5921 | ||
5922 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
5923 | * gating disable must be set. Failure to set it results in | |
5924 | * flickering pixels due to Z write ordering failures after | |
5925 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
5926 | * Sanctuary and Tropics, and apparently anything else with | |
5927 | * alpha test or pixel discard. | |
5928 | * | |
5929 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
5930 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 5931 | * |
ef59318c VS |
5932 | * WaDisableRCCUnitClockGating:snb |
5933 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
5934 | */ |
5935 | I915_WRITE(GEN6_UCGCTL2, | |
5936 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
5937 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
5938 | ||
5eb146dd | 5939 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
5940 | I915_WRITE(_3D_CHICKEN3, |
5941 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 5942 | |
e927ecde VS |
5943 | /* |
5944 | * Bspec says: | |
5945 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
5946 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
5947 | */ | |
5948 | I915_WRITE(_3D_CHICKEN3, | |
5949 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
5950 | ||
6f1d69b0 ED |
5951 | /* |
5952 | * According to the spec the following bits should be | |
5953 | * set in order to enable memory self-refresh and fbc: | |
5954 | * The bit21 and bit22 of 0x42000 | |
5955 | * The bit21 and bit22 of 0x42004 | |
5956 | * The bit5 and bit7 of 0x42020 | |
5957 | * The bit14 of 0x70180 | |
5958 | * The bit14 of 0x71180 | |
4bb35334 DL |
5959 | * |
5960 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
5961 | */ |
5962 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5963 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5964 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
5965 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5966 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5967 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
5968 | I915_WRITE(ILK_DSPCLK_GATE_D, |
5969 | I915_READ(ILK_DSPCLK_GATE_D) | | |
5970 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
5971 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 5972 | |
0e088b8f | 5973 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 5974 | |
3107bd48 | 5975 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
5976 | |
5977 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5978 | } |
5979 | ||
5980 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
5981 | { | |
5982 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
5983 | ||
3aad9059 | 5984 | /* |
46680e0a | 5985 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
5986 | * |
5987 | * This actually overrides the dispatch | |
5988 | * mode for all thread types. | |
5989 | */ | |
6f1d69b0 ED |
5990 | reg &= ~GEN7_FF_SCHED_MASK; |
5991 | reg |= GEN7_FF_TS_SCHED_HW; | |
5992 | reg |= GEN7_FF_VS_SCHED_HW; | |
5993 | reg |= GEN7_FF_DS_SCHED_HW; | |
5994 | ||
5995 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
5996 | } | |
5997 | ||
17a303ec PZ |
5998 | static void lpt_init_clock_gating(struct drm_device *dev) |
5999 | { | |
6000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6001 | ||
6002 | /* | |
6003 | * TODO: this bit should only be enabled when really needed, then | |
6004 | * disabled when not needed anymore in order to save power. | |
6005 | */ | |
6006 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
6007 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
6008 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6009 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6010 | |
6011 | /* WADPOClockGatingDisable:hsw */ | |
6012 | I915_WRITE(_TRANSA_CHICKEN1, | |
6013 | I915_READ(_TRANSA_CHICKEN1) | | |
6014 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
6015 | } |
6016 | ||
7d708ee4 ID |
6017 | static void lpt_suspend_hw(struct drm_device *dev) |
6018 | { | |
6019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6020 | ||
6021 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6022 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6023 | ||
6024 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6025 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6026 | } | |
6027 | } | |
6028 | ||
47c2bd97 | 6029 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6030 | { |
6031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6032 | enum pipe pipe; |
1020a5c2 BW |
6033 | |
6034 | I915_WRITE(WM3_LP_ILK, 0); | |
6035 | I915_WRITE(WM2_LP_ILK, 0); | |
6036 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd | 6037 | |
ab57fff1 | 6038 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6039 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6040 | |
ab57fff1 | 6041 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6042 | I915_WRITE(CHICKEN_PAR1_1, |
6043 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6044 | ||
ab57fff1 | 6045 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6046 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6047 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6048 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6049 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6050 | } |
63801f21 | 6051 | |
ab57fff1 BW |
6052 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6053 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6054 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6055 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6056 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6057 | |
295e8bb7 VS |
6058 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6059 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6060 | |
6061 | /* WaDisableSDEUnitClockGating:bdw */ | |
6062 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6063 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6064 | |
89d6b2b8 | 6065 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6066 | } |
6067 | ||
cad2a2d7 ED |
6068 | static void haswell_init_clock_gating(struct drm_device *dev) |
6069 | { | |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6071 | |
017636cc | 6072 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6073 | |
f3fc4884 FJ |
6074 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6075 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6076 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6077 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6078 | ||
ecdb4eb7 | 6079 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6080 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6081 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6082 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6083 | ||
e36ea7ff VS |
6084 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6085 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6086 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6087 | |
4e04632e AG |
6088 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6089 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6090 | ||
fe27c606 CW |
6091 | /* enable HiZ Raw Stall Optimization */ |
6092 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6093 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6094 | ||
ecdb4eb7 | 6095 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6096 | I915_WRITE(CACHE_MODE_1, |
6097 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6098 | |
a12c4967 VS |
6099 | /* |
6100 | * BSpec recommends 8x4 when MSAA is used, | |
6101 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6102 | * |
6103 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6104 | * disable bit, which we don't touch here, but it's good | |
6105 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6106 | */ |
6107 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6108 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 6109 | |
94411593 KG |
6110 | /* WaSampleCChickenBitEnable:hsw */ |
6111 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6112 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6113 | ||
ecdb4eb7 | 6114 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6115 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6116 | ||
90a88643 PZ |
6117 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6118 | I915_WRITE(CHICKEN_PAR1_1, | |
6119 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6120 | |
17a303ec | 6121 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6122 | } |
6123 | ||
1fa61106 | 6124 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6125 | { |
6126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6127 | uint32_t snpcr; |
6f1d69b0 | 6128 | |
017636cc | 6129 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6130 | |
231e54f6 | 6131 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6132 | |
ecdb4eb7 | 6133 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6134 | I915_WRITE(_3D_CHICKEN3, |
6135 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6136 | ||
ecdb4eb7 | 6137 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6138 | I915_WRITE(IVB_CHICKEN3, |
6139 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6140 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6141 | ||
ecdb4eb7 | 6142 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6143 | if (IS_IVB_GT1(dev)) |
6144 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6145 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6146 | |
4e04632e AG |
6147 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6148 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6149 | ||
ecdb4eb7 | 6150 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6151 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6152 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6153 | ||
ecdb4eb7 | 6154 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6155 | I915_WRITE(GEN7_L3CNTLREG1, |
6156 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6157 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6158 | GEN7_WA_L3_CHICKEN_MODE); |
6159 | if (IS_IVB_GT1(dev)) | |
6160 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6161 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6162 | else { |
6163 | /* must write both registers */ | |
6164 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6165 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6166 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6167 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6168 | } |
6f1d69b0 | 6169 | |
ecdb4eb7 | 6170 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6171 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6172 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6173 | ||
1b80a19a | 6174 | /* |
0f846f81 | 6175 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6176 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6177 | */ |
6178 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6179 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6180 | |
ecdb4eb7 | 6181 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6182 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6183 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6184 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6185 | ||
0e088b8f | 6186 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6187 | |
6188 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6189 | |
22721343 CW |
6190 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6191 | /* enable HiZ Raw Stall Optimization */ | |
6192 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6193 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6194 | } | |
116f2b6d | 6195 | |
ecdb4eb7 | 6196 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6197 | I915_WRITE(CACHE_MODE_1, |
6198 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6199 | |
a607c1a4 VS |
6200 | /* |
6201 | * BSpec recommends 8x4 when MSAA is used, | |
6202 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6203 | * |
6204 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6205 | * disable bit, which we don't touch here, but it's good | |
6206 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6207 | */ |
6208 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6209 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 6210 | |
20848223 BW |
6211 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6212 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6213 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6214 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6215 | |
ab5c608b BW |
6216 | if (!HAS_PCH_NOP(dev)) |
6217 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6218 | |
6219 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6220 | } |
6221 | ||
1fa61106 | 6222 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6223 | { |
6224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6225 | |
d7fe0cc0 | 6226 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6227 | |
ecdb4eb7 | 6228 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6229 | I915_WRITE(_3D_CHICKEN3, |
6230 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6231 | ||
ecdb4eb7 | 6232 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6233 | I915_WRITE(IVB_CHICKEN3, |
6234 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6235 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6236 | ||
fad7d36e | 6237 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6238 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6239 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6240 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6241 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6242 | |
4e04632e AG |
6243 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6244 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6245 | ||
ecdb4eb7 | 6246 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6247 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6248 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6249 | ||
ecdb4eb7 | 6250 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6251 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6252 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6253 | ||
ecdb4eb7 | 6254 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6255 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6256 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6257 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6258 | ||
46680e0a VS |
6259 | gen7_setup_fixed_func_scheduler(dev_priv); |
6260 | ||
3c0edaeb | 6261 | /* |
0f846f81 | 6262 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6263 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6264 | */ |
6265 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6266 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6267 | |
c98f5062 AG |
6268 | /* WaDisableL3Bank2xClockGate:vlv |
6269 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6270 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6271 | I915_WRITE(GEN7_UCGCTL4, | |
6272 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6273 | |
e0d8d59b | 6274 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6f1d69b0 | 6275 | |
afd58e79 VS |
6276 | /* |
6277 | * BSpec says this must be set, even though | |
6278 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6279 | */ | |
6b26c86d DV |
6280 | I915_WRITE(CACHE_MODE_1, |
6281 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6282 | |
da2518f9 VS |
6283 | /* |
6284 | * BSpec recommends 8x4 when MSAA is used, | |
6285 | * however in practice 16x4 seems fastest. | |
6286 | * | |
6287 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6288 | * disable bit, which we don't touch here, but it's good | |
6289 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6290 | */ | |
6291 | I915_WRITE(GEN7_GT_MODE, | |
6292 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6293 | ||
031994ee VS |
6294 | /* |
6295 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6296 | * This is the hardware default actually. | |
6297 | */ | |
6298 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6299 | ||
2d809570 | 6300 | /* |
ecdb4eb7 | 6301 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6302 | * Disable clock gating on th GCFG unit to prevent a delay |
6303 | * in the reporting of vblank events. | |
6304 | */ | |
7a0d1eed | 6305 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6306 | } |
6307 | ||
a4565da8 VS |
6308 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6309 | { | |
6310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6311 | ||
6312 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6313 | ||
6314 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
dd811e70 | 6315 | |
232ce337 VS |
6316 | /* WaVSRefCountFullforceMissDisable:chv */ |
6317 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6318 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6319 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6320 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6321 | |
6322 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6323 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6324 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6325 | |
6326 | /* WaDisableCSUnitClockGating:chv */ | |
6327 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6328 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6329 | |
6330 | /* WaDisableSDEUnitClockGating:chv */ | |
6331 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6332 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
a4565da8 VS |
6333 | } |
6334 | ||
1fa61106 | 6335 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6336 | { |
6337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6338 | uint32_t dspclk_gate; | |
6339 | ||
6340 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6341 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6342 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6343 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6344 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6345 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6346 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6347 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6348 | if (IS_GM45(dev)) | |
6349 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6350 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6351 | |
6352 | /* WaDisableRenderCachePipelinedFlush */ | |
6353 | I915_WRITE(CACHE_MODE_0, | |
6354 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6355 | |
4e04632e AG |
6356 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6357 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6358 | ||
0e088b8f | 6359 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6360 | } |
6361 | ||
1fa61106 | 6362 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6363 | { |
6364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6365 | ||
6366 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6367 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6368 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6369 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6370 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6371 | I915_WRITE(MI_ARB_STATE, |
6372 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6373 | |
6374 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6375 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6376 | } |
6377 | ||
1fa61106 | 6378 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6379 | { |
6380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6381 | ||
6382 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6383 | I965_RCC_CLOCK_GATE_DISABLE | | |
6384 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6385 | I965_ISC_CLOCK_GATE_DISABLE | | |
6386 | I965_FBC_CLOCK_GATE_DISABLE); | |
6387 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6388 | I915_WRITE(MI_ARB_STATE, |
6389 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6390 | |
6391 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6392 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6393 | } |
6394 | ||
1fa61106 | 6395 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6396 | { |
6397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6398 | u32 dstate = I915_READ(D_STATE); | |
6399 | ||
6400 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6401 | DSTATE_DOT_CLOCK_GATING; | |
6402 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6403 | |
6404 | if (IS_PINEVIEW(dev)) | |
6405 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6406 | |
6407 | /* IIR "flip pending" means done if this bit is set */ | |
6408 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6409 | |
6410 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6411 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6412 | |
6413 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6414 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6415 | |
6416 | I915_WRITE(MI_ARB_STATE, | |
6417 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6418 | } |
6419 | ||
1fa61106 | 6420 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6421 | { |
6422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6423 | ||
6424 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6425 | |
6426 | /* interrupts should cause a wake up from C3 */ | |
6427 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6428 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6429 | |
6430 | I915_WRITE(MEM_MODE, | |
6431 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6432 | } |
6433 | ||
1fa61106 | 6434 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6435 | { |
6436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6437 | ||
6438 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6439 | |
6440 | I915_WRITE(MEM_MODE, | |
6441 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6442 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6443 | } |
6444 | ||
6f1d69b0 ED |
6445 | void intel_init_clock_gating(struct drm_device *dev) |
6446 | { | |
6447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6448 | ||
c57e3551 DL |
6449 | if (dev_priv->display.init_clock_gating) |
6450 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6451 | } |
6452 | ||
7d708ee4 ID |
6453 | void intel_suspend_hw(struct drm_device *dev) |
6454 | { | |
6455 | if (HAS_PCH_LPT(dev)) | |
6456 | lpt_suspend_hw(dev); | |
6457 | } | |
6458 | ||
1fa61106 ED |
6459 | /* Set up chip specific power management-related functions */ |
6460 | void intel_init_pm(struct drm_device *dev) | |
6461 | { | |
6462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6463 | ||
7ff0ebcc | 6464 | intel_fbc_init(dev_priv); |
1fa61106 | 6465 | |
c921aba8 DV |
6466 | /* For cxsr */ |
6467 | if (IS_PINEVIEW(dev)) | |
6468 | i915_pineview_get_mem_freq(dev); | |
6469 | else if (IS_GEN5(dev)) | |
6470 | i915_ironlake_get_mem_freq(dev); | |
6471 | ||
1fa61106 | 6472 | /* For FIFO watermark updates */ |
f5ed50cb | 6473 | if (INTEL_INFO(dev)->gen >= 9) { |
2af30a5c PB |
6474 | skl_setup_wm_latency(dev); |
6475 | ||
45db2194 | 6476 | dev_priv->display.init_clock_gating = skl_init_clock_gating; |
2d41c0b5 PB |
6477 | dev_priv->display.update_wm = skl_update_wm; |
6478 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; | |
c83155a6 | 6479 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 6480 | ilk_setup_wm_latency(dev); |
53615a5e | 6481 | |
bd602544 VS |
6482 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6483 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6484 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6485 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6486 | dev_priv->display.update_wm = ilk_update_wm; | |
6487 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6488 | } else { | |
6489 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6490 | "Disable CxSR\n"); | |
6491 | } | |
6492 | ||
6493 | if (IS_GEN5(dev)) | |
1fa61106 | 6494 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6495 | else if (IS_GEN6(dev)) |
1fa61106 | 6496 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6497 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6498 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6499 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6500 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6501 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 6502 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 6503 | } else if (IS_CHERRYVIEW(dev)) { |
3c2777fd | 6504 | dev_priv->display.update_wm = cherryview_update_wm; |
01e184cc | 6505 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
a4565da8 VS |
6506 | dev_priv->display.init_clock_gating = |
6507 | cherryview_init_clock_gating; | |
1fa61106 ED |
6508 | } else if (IS_VALLEYVIEW(dev)) { |
6509 | dev_priv->display.update_wm = valleyview_update_wm; | |
01e184cc | 6510 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
1fa61106 ED |
6511 | dev_priv->display.init_clock_gating = |
6512 | valleyview_init_clock_gating; | |
1fa61106 ED |
6513 | } else if (IS_PINEVIEW(dev)) { |
6514 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6515 | dev_priv->is_ddr3, | |
6516 | dev_priv->fsb_freq, | |
6517 | dev_priv->mem_freq)) { | |
6518 | DRM_INFO("failed to find known CxSR latency " | |
6519 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6520 | "disabling CxSR\n", | |
6521 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6522 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6523 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6524 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6525 | dev_priv->display.update_wm = NULL; |
6526 | } else | |
6527 | dev_priv->display.update_wm = pineview_update_wm; | |
6528 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6529 | } else if (IS_G4X(dev)) { | |
6530 | dev_priv->display.update_wm = g4x_update_wm; | |
6531 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6532 | } else if (IS_GEN4(dev)) { | |
6533 | dev_priv->display.update_wm = i965_update_wm; | |
6534 | if (IS_CRESTLINE(dev)) | |
6535 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6536 | else if (IS_BROADWATER(dev)) | |
6537 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6538 | } else if (IS_GEN3(dev)) { | |
6539 | dev_priv->display.update_wm = i9xx_update_wm; | |
6540 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6541 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6542 | } else if (IS_GEN2(dev)) { |
6543 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6544 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6545 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6546 | } else { |
6547 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6548 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6549 | } |
6550 | ||
6551 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6552 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6553 | else | |
6554 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6555 | } else { | |
6556 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6557 | } |
6558 | } | |
6559 | ||
151a49d0 | 6560 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 6561 | { |
4fc688ce | 6562 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6563 | |
6564 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6565 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6566 | return -EAGAIN; | |
6567 | } | |
6568 | ||
6569 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
dddab346 | 6570 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
42c0526c BW |
6571 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
6572 | ||
6573 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6574 | 500)) { | |
6575 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6576 | return -ETIMEDOUT; | |
6577 | } | |
6578 | ||
6579 | *val = I915_READ(GEN6_PCODE_DATA); | |
6580 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6581 | ||
6582 | return 0; | |
6583 | } | |
6584 | ||
151a49d0 | 6585 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
42c0526c | 6586 | { |
4fc688ce | 6587 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6588 | |
6589 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6590 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6591 | return -EAGAIN; | |
6592 | } | |
6593 | ||
6594 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6595 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6596 | ||
6597 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6598 | 500)) { | |
6599 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6600 | return -ETIMEDOUT; | |
6601 | } | |
6602 | ||
6603 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6604 | ||
6605 | return 0; | |
6606 | } | |
a0e4e199 | 6607 | |
dd06f88c | 6608 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
855ba3be | 6609 | { |
dd06f88c VS |
6610 | switch (czclk_freq) { |
6611 | case 200: | |
6612 | return 10; | |
6613 | case 267: | |
6614 | return 12; | |
6615 | case 320: | |
6616 | case 333: | |
dd06f88c | 6617 | return 16; |
ab3fb157 VS |
6618 | case 400: |
6619 | return 20; | |
855ba3be JB |
6620 | default: |
6621 | return -1; | |
6622 | } | |
dd06f88c | 6623 | } |
855ba3be | 6624 | |
dd06f88c VS |
6625 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
6626 | { | |
6627 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); | |
6628 | ||
6629 | div = vlv_gpu_freq_div(czclk_freq); | |
6630 | if (div < 0) | |
6631 | return div; | |
6632 | ||
6633 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
855ba3be JB |
6634 | } |
6635 | ||
b55dd647 | 6636 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6637 | { |
dd06f88c | 6638 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); |
855ba3be | 6639 | |
dd06f88c VS |
6640 | mul = vlv_gpu_freq_div(czclk_freq); |
6641 | if (mul < 0) | |
6642 | return mul; | |
855ba3be | 6643 | |
dd06f88c | 6644 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
855ba3be JB |
6645 | } |
6646 | ||
b55dd647 | 6647 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6648 | { |
dd06f88c | 6649 | int div, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6650 | |
dd06f88c VS |
6651 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
6652 | if (div < 0) | |
6653 | return div; | |
22b1b2f8 | 6654 | |
dd06f88c | 6655 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
22b1b2f8 D |
6656 | } |
6657 | ||
b55dd647 | 6658 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6659 | { |
dd06f88c | 6660 | int mul, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6661 | |
dd06f88c VS |
6662 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
6663 | if (mul < 0) | |
6664 | return mul; | |
22b1b2f8 | 6665 | |
1c14762d | 6666 | /* CHV needs even values */ |
dd06f88c | 6667 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
22b1b2f8 D |
6668 | } |
6669 | ||
616bc820 | 6670 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6671 | { |
22b1b2f8 | 6672 | if (IS_CHERRYVIEW(dev_priv->dev)) |
616bc820 | 6673 | return chv_gpu_freq(dev_priv, val); |
22b1b2f8 | 6674 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6675 | return byt_gpu_freq(dev_priv, val); |
6676 | else | |
6677 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
6678 | } |
6679 | ||
616bc820 VS |
6680 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
6681 | { | |
22b1b2f8 | 6682 | if (IS_CHERRYVIEW(dev_priv->dev)) |
616bc820 | 6683 | return chv_freq_opcode(dev_priv, val); |
22b1b2f8 | 6684 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6685 | return byt_freq_opcode(dev_priv, val); |
6686 | else | |
6687 | return val / GT_FREQUENCY_MULTIPLIER; | |
6688 | } | |
22b1b2f8 | 6689 | |
f742a552 | 6690 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
6691 | { |
6692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6693 | ||
f742a552 DV |
6694 | mutex_init(&dev_priv->rps.hw_lock); |
6695 | ||
907b28c5 CW |
6696 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6697 | intel_gen6_powersave_work); | |
5d584b2e | 6698 | |
33688d95 | 6699 | dev_priv->pm.suspended = false; |
907b28c5 | 6700 | } |