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drm/i915: Use adjusted_mode in HDMI 12bpc clock check
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
f85da868 461 unsigned int max_hdisplay, max_vdisplay;
85208be0 462
29ebf90f
CW		 463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 465 return;
29ebf90f 466 }
85208be0 467
29ebf90f
CW		 468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 471 return;
29ebf90f 472 }
85208be0
ED		 473
474 /*
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
482 */
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 486 if (crtc) {
29ebf90f
CW		 487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 489 goto out_disable;
490 }
491 crtc = tmp_crtc;
492 }
493 }
494
495 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 498 goto out_disable;
499 }
500
501 intel_crtc = to_intel_crtc(crtc);
502 fb = crtc->fb;
503 intel_fb = to_intel_framebuffer(fb);
504 obj = intel_fb->obj;
505
8a5729a3
DL		 506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 510 goto out_disable;
85208be0 511 }
8a5729a3 512 if (!i915_enable_fbc) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 515 goto out_disable;
516 }
85208be0
ED		 517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
521 "disabling\n");
85208be0
ED		 522 goto out_disable;
523 }
f85da868
PZ		 524
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 max_hdisplay = 4096;
527 max_vdisplay = 2048;
528 } else {
529 max_hdisplay = 2048;
530 max_vdisplay = 1536;
531 }
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
891348b2
RV		 538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 542 goto out_disable;
543 }
544
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
547 */
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 552 goto out_disable;
553 }
554
555 /* If the kernel debugger is active, always disable compression */
556 if (in_dbg_master())
557 goto out_disable;
558
11be49eb 559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 562 goto out_disable;
563 }
564
85208be0
ED		 565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
569 */
5c3fe8b0
BW		 570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
85208be0
ED		 573 return;
574
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
581 *
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
590 * callback.
591 *
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
598 */
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
601 }
602
603 intel_enable_fbc(crtc, 500);
29ebf90f 604 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 605 return;
606
607out_disable:
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
612 }
11be49eb 613 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 614}
615
c921aba8
DV		 616static void i915_pineview_get_mem_freq(struct drm_device *dev)
617{
618 drm_i915_private_t *dev_priv = dev->dev_private;
619 u32 tmp;
620
621 tmp = I915_READ(CLKCFG);
622
623 switch (tmp & CLKCFG_FSB_MASK) {
624 case CLKCFG_FSB_533:
625 dev_priv->fsb_freq = 533; /* 133*4 */
626 break;
627 case CLKCFG_FSB_800:
628 dev_priv->fsb_freq = 800; /* 200*4 */
629 break;
630 case CLKCFG_FSB_667:
631 dev_priv->fsb_freq = 667; /* 167*4 */
632 break;
633 case CLKCFG_FSB_400:
634 dev_priv->fsb_freq = 400; /* 100*4 */
635 break;
636 }
637
638 switch (tmp & CLKCFG_MEM_MASK) {
639 case CLKCFG_MEM_533:
640 dev_priv->mem_freq = 533;
641 break;
642 case CLKCFG_MEM_667:
643 dev_priv->mem_freq = 667;
644 break;
645 case CLKCFG_MEM_800:
646 dev_priv->mem_freq = 800;
647 break;
648 }
649
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
653}
654
655static void i915_ironlake_get_mem_freq(struct drm_device *dev)
656{
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 u16 ddrpll, csipll;
659
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
662
663 switch (ddrpll & 0xff) {
664 case 0xc:
665 dev_priv->mem_freq = 800;
666 break;
667 case 0x10:
668 dev_priv->mem_freq = 1066;
669 break;
670 case 0x14:
671 dev_priv->mem_freq = 1333;
672 break;
673 case 0x18:
674 dev_priv->mem_freq = 1600;
675 break;
676 default:
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
678 ddrpll & 0xff);
679 dev_priv->mem_freq = 0;
680 break;
681 }
682
20e4d407 683 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 684
685 switch (csipll & 0x3ff) {
686 case 0x00c:
687 dev_priv->fsb_freq = 3200;
688 break;
689 case 0x00e:
690 dev_priv->fsb_freq = 3733;
691 break;
692 case 0x010:
693 dev_priv->fsb_freq = 4266;
694 break;
695 case 0x012:
696 dev_priv->fsb_freq = 4800;
697 break;
698 case 0x014:
699 dev_priv->fsb_freq = 5333;
700 break;
701 case 0x016:
702 dev_priv->fsb_freq = 5866;
703 break;
704 case 0x018:
705 dev_priv->fsb_freq = 6400;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
709 csipll & 0x3ff);
710 dev_priv->fsb_freq = 0;
711 break;
712 }
713
714 if (dev_priv->fsb_freq == 3200) {
20e4d407 715 dev_priv->ips.c_m = 0;
c921aba8 716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 717 dev_priv->ips.c_m = 1;
c921aba8 718 } else {
20e4d407 719 dev_priv->ips.c_m = 2;
c921aba8
DV		 720 }
721}
722
b445e3b0
ED		 723static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
729
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
735
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
741
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
747
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
753
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
759};
760
63c62275 761static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 762 int is_ddr3,
763 int fsb,
764 int mem)
765{
766 const struct cxsr_latency *latency;
767 int i;
768
769 if (fsb == 0 || mem == 0)
770 return NULL;
771
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
777 return latency;
778 }
779
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
781
782 return NULL;
783}
784
1fa61106 785static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
791}
792
793/*
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
796 * - chipset
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
803 *
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
806 */
807static const int latency_ns = 5000;
808
1fa61106 809static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
813 int size;
814
815 size = dsparb & 0x7f;
816 if (plane)
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x1ff;
832 if (plane)
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
838
839 return size;
840}
841
1fa61106 842static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 843{
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
846 int size;
847
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
850
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 plane ? "B" : "A",
853 size);
854
855 return size;
856}
857
1fa61106 858static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
866
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
869
870 return size;
871}
872
873/* Pineview has different values for various configs */
874static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
883 PINEVIEW_MAX_WM,
884 PINEVIEW_DFT_HPLLOFF_WM,
885 PINEVIEW_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
894};
895static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params g4x_wm_info = {
903 G4X_FIFO_SIZE,
904 G4X_MAX_WM,
905 G4X_MAX_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params g4x_cursor_wm_info = {
910 I965_CURSOR_FIFO,
911 I965_CURSOR_MAX_WM,
912 I965_CURSOR_DFT_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
918 VALLEYVIEW_MAX_WM,
919 VALLEYVIEW_MAX_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params valleyview_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 VALLEYVIEW_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 G4X_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i965_cursor_wm_info = {
931 I965_CURSOR_FIFO,
932 I965_CURSOR_MAX_WM,
933 I965_CURSOR_DFT_WM,
934 2,
935 I915_FIFO_LINE_SIZE,
936};
937static const struct intel_watermark_params i945_wm_info = {
938 I945_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
944static const struct intel_watermark_params i915_wm_info = {
945 I915_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I915_FIFO_LINE_SIZE
950};
951static const struct intel_watermark_params i855_wm_info = {
952 I855GM_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params i830_wm_info = {
959 I830_FIFO_SIZE,
960 I915_MAX_WM,
961 1,
962 2,
963 I830_FIFO_LINE_SIZE
964};
965
966static const struct intel_watermark_params ironlake_display_wm_info = {
967 ILK_DISPLAY_FIFO,
968 ILK_DISPLAY_MAXWM,
969 ILK_DISPLAY_DFTWM,
970 2,
971 ILK_FIFO_LINE_SIZE
972};
973static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 ILK_CURSOR_FIFO,
975 ILK_CURSOR_MAXWM,
976 ILK_CURSOR_DFTWM,
977 2,
978 ILK_FIFO_LINE_SIZE
979};
980static const struct intel_watermark_params ironlake_display_srwm_info = {
981 ILK_DISPLAY_SR_FIFO,
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
984 2,
985 ILK_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params ironlake_cursor_srwm_info = {
988 ILK_CURSOR_SR_FIFO,
989 ILK_CURSOR_MAX_SRWM,
990 ILK_CURSOR_DFT_SRWM,
991 2,
992 ILK_FIFO_LINE_SIZE
993};
994
995static const struct intel_watermark_params sandybridge_display_wm_info = {
996 SNB_DISPLAY_FIFO,
997 SNB_DISPLAY_MAXWM,
998 SNB_DISPLAY_DFTWM,
999 2,
1000 SNB_FIFO_LINE_SIZE
1001};
1002static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 SNB_CURSOR_FIFO,
1004 SNB_CURSOR_MAXWM,
1005 SNB_CURSOR_DFTWM,
1006 2,
1007 SNB_FIFO_LINE_SIZE
1008};
1009static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1013 2,
1014 SNB_FIFO_LINE_SIZE
1015};
1016static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017 SNB_CURSOR_SR_FIFO,
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1020 2,
1021 SNB_FIFO_LINE_SIZE
1022};
1023
1024
1025/**
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1031 *
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1036 *
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1042 */
1043static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1045 int fifo_size,
1046 int pixel_size,
1047 unsigned long latency_ns)
1048{
1049 long entries_required, wm_size;
1050
1051 /*
1052 * Note: we need to make sure we don't overflow for various clock &
1053 * latency values.
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1056 */
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058 1000;
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1070 if (wm_size <= 0)
1071 wm_size = wm->default_wm;
1072 return wm_size;
1073}
1074
1075static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076{
1077 struct drm_crtc *crtc, *enabled = NULL;
1078
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1080 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1081 if (enabled)
1082 return NULL;
1083 enabled = crtc;
1084 }
1085 }
1086
1087 return enabled;
1088}
1089
46ba614c 1090static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1091{
46ba614c 1092 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 struct drm_crtc *crtc;
1095 const struct cxsr_latency *latency;
1096 u32 reg;
1097 unsigned long wm;
1098
1099 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1100 dev_priv->fsb_freq, dev_priv->mem_freq);
1101 if (!latency) {
1102 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1103 pineview_disable_cxsr(dev);
1104 return;
1105 }
1106
1107 crtc = single_enabled_crtc(dev);
1108 if (crtc) {
1109 int clock = crtc->mode.clock;
1110 int pixel_size = crtc->fb->bits_per_pixel / 8;
1111
1112 /* Display SR */
1113 wm = intel_calculate_wm(clock, &pineview_display_wm,
1114 pineview_display_wm.fifo_size,
1115 pixel_size, latency->display_sr);
1116 reg = I915_READ(DSPFW1);
1117 reg &= ~DSPFW_SR_MASK;
1118 reg |= wm << DSPFW_SR_SHIFT;
1119 I915_WRITE(DSPFW1, reg);
1120 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1121
1122 /* cursor SR */
1123 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1124 pineview_display_wm.fifo_size,
1125 pixel_size, latency->cursor_sr);
1126 reg = I915_READ(DSPFW3);
1127 reg &= ~DSPFW_CURSOR_SR_MASK;
1128 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1129 I915_WRITE(DSPFW3, reg);
1130
1131 /* Display HPLL off SR */
1132 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1133 pineview_display_hplloff_wm.fifo_size,
1134 pixel_size, latency->display_hpll_disable);
1135 reg = I915_READ(DSPFW3);
1136 reg &= ~DSPFW_HPLL_SR_MASK;
1137 reg |= wm & DSPFW_HPLL_SR_MASK;
1138 I915_WRITE(DSPFW3, reg);
1139
1140 /* cursor HPLL off SR */
1141 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1142 pineview_display_hplloff_wm.fifo_size,
1143 pixel_size, latency->cursor_hpll_disable);
1144 reg = I915_READ(DSPFW3);
1145 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1146 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1147 I915_WRITE(DSPFW3, reg);
1148 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1149
1150 /* activate cxsr */
1151 I915_WRITE(DSPFW3,
1152 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1153 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1154 } else {
1155 pineview_disable_cxsr(dev);
1156 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1157 }
1158}
1159
1160static bool g4x_compute_wm0(struct drm_device *dev,
1161 int plane,
1162 const struct intel_watermark_params *display,
1163 int display_latency_ns,
1164 const struct intel_watermark_params *cursor,
1165 int cursor_latency_ns,
1166 int *plane_wm,
1167 int *cursor_wm)
1168{
1169 struct drm_crtc *crtc;
1170 int htotal, hdisplay, clock, pixel_size;
1171 int line_time_us, line_count;
1172 int entries, tlb_miss;
1173
1174 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1175 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1176 *cursor_wm = cursor->guard_size;
1177 *plane_wm = display->guard_size;
1178 return false;
1179 }
1180
1181 htotal = crtc->mode.htotal;
1182 hdisplay = crtc->mode.hdisplay;
1183 clock = crtc->mode.clock;
1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189 if (tlb_miss > 0)
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1195
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201 if (tlb_miss > 0)
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1207
1208 return true;
1209}
1210
1211/*
1212 * Check the wm result.
1213 *
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1216 * must be disabled.
1217 */
1218static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1222{
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1225
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1229 return false;
1230 }
1231
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1235 return false;
1236 }
1237
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240 return false;
1241 }
1242
1243 return true;
1244}
1245
1246static bool g4x_compute_srwm(struct drm_device *dev,
1247 int plane,
1248 int latency_ns,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1252{
1253 struct drm_crtc *crtc;
1254 int hdisplay, htotal, pixel_size, clock;
1255 unsigned long line_time_us;
1256 int line_count, line_size;
1257 int small, large;
1258 int entries;
1259
1260 if (!latency_ns) {
1261 *display_wm = *cursor_wm = 0;
1262 return false;
1263 }
1264
1265 crtc = intel_get_crtc_for_plane(dev, plane);
1266 hdisplay = crtc->mode.hdisplay;
1267 htotal = crtc->mode.htotal;
1268 clock = crtc->mode.clock;
1269 pixel_size = crtc->fb->bits_per_pixel / 8;
1270
1271 line_time_us = (htotal * 1000) / clock;
1272 line_count = (latency_ns / line_time_us + 1000) / 1000;
1273 line_size = hdisplay * pixel_size;
1274
1275 /* Use the minimum of the small and large buffer method for primary */
1276 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1277 large = line_count * line_size;
1278
1279 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1280 *display_wm = entries + display->guard_size;
1281
1282 /* calculate the self-refresh watermark for display cursor */
1283 entries = line_count * pixel_size * 64;
1284 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1285 *cursor_wm = entries + cursor->guard_size;
1286
1287 return g4x_check_srwm(dev,
1288 *display_wm, *cursor_wm,
1289 display, cursor);
1290}
1291
1292static bool vlv_compute_drain_latency(struct drm_device *dev,
1293 int plane,
1294 int *plane_prec_mult,
1295 int *plane_dl,
1296 int *cursor_prec_mult,
1297 int *cursor_dl)
1298{
1299 struct drm_crtc *crtc;
1300 int clock, pixel_size;
1301 int entries;
1302
1303 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1304 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1305 return false;
1306
1307 clock = crtc->mode.clock; /* VESA DOT Clock */
1308 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1309
1310 entries = (clock / 1000) * pixel_size;
1311 *plane_prec_mult = (entries > 256) ?
1312 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1313 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1314 pixel_size);
1315
1316 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1317 *cursor_prec_mult = (entries > 256) ?
1318 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1319 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1320
1321 return true;
1322}
1323
1324/*
1325 * Update drain latency registers of memory arbiter
1326 *
1327 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1328 * to be programmed. Each plane has a drain latency multiplier and a drain
1329 * latency value.
1330 */
1331
1332static void vlv_update_drain_latency(struct drm_device *dev)
1333{
1334 struct drm_i915_private *dev_priv = dev->dev_private;
1335 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1336 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1337 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1338 either 16 or 32 */
1339
1340 /* For plane A, Cursor A */
1341 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1342 &cursor_prec_mult, &cursora_dl)) {
1343 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1344 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1345 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1347
1348 I915_WRITE(VLV_DDL1, cursora_prec |
1349 (cursora_dl << DDL_CURSORA_SHIFT) |
1350 planea_prec | planea_dl);
1351 }
1352
1353 /* For plane B, Cursor B */
1354 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1355 &cursor_prec_mult, &cursorb_dl)) {
1356 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1357 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1358 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1360
1361 I915_WRITE(VLV_DDL2, cursorb_prec |
1362 (cursorb_dl << DDL_CURSORB_SHIFT) |
1363 planeb_prec | planeb_dl);
1364 }
1365}
1366
1367#define single_plane_enabled(mask) is_power_of_2(mask)
1368
46ba614c 1369static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1370{
46ba614c 1371 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1372 static const int sr_latency_ns = 12000;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1375 int plane_sr, cursor_sr;
af6c4575 1376 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1377 unsigned int enabled = 0;
1378
1379 vlv_update_drain_latency(dev);
1380
51cea1f4 1381 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1382 &valleyview_wm_info, latency_ns,
1383 &valleyview_cursor_wm_info, latency_ns,
1384 &planea_wm, &cursora_wm))
51cea1f4 1385 enabled |= 1 << PIPE_A;
b445e3b0 1386
51cea1f4 1387 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1388 &valleyview_wm_info, latency_ns,
1389 &valleyview_cursor_wm_info, latency_ns,
1390 &planeb_wm, &cursorb_wm))
51cea1f4 1391 enabled |= 1 << PIPE_B;
b445e3b0 1392
b445e3b0
ED		 1393 if (single_plane_enabled(enabled) &&
1394 g4x_compute_srwm(dev, ffs(enabled) - 1,
1395 sr_latency_ns,
1396 &valleyview_wm_info,
1397 &valleyview_cursor_wm_info,
af6c4575
CW		 1398 &plane_sr, &ignore_cursor_sr) &&
1399 g4x_compute_srwm(dev, ffs(enabled) - 1,
1400 2*sr_latency_ns,
1401 &valleyview_wm_info,
1402 &valleyview_cursor_wm_info,
52bd02d8 1403 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1404 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1405 } else {
b445e3b0
ED		 1406 I915_WRITE(FW_BLC_SELF_VLV,
1407 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1408 plane_sr = cursor_sr = 0;
1409 }
b445e3b0
ED		 1410
1411 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1412 planea_wm, cursora_wm,
1413 planeb_wm, cursorb_wm,
1414 plane_sr, cursor_sr);
1415
1416 I915_WRITE(DSPFW1,
1417 (plane_sr << DSPFW_SR_SHIFT) |
1418 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1419 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1420 planea_wm);
1421 I915_WRITE(DSPFW2,
8c919b28 1422 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1423 (cursora_wm << DSPFW_CURSORA_SHIFT));
1424 I915_WRITE(DSPFW3,
8c919b28
CW		 1425 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1426 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1427}
1428
46ba614c 1429static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1430{
46ba614c 1431 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1432 static const int sr_latency_ns = 12000;
1433 struct drm_i915_private *dev_priv = dev->dev_private;
1434 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1435 int plane_sr, cursor_sr;
1436 unsigned int enabled = 0;
1437
51cea1f4 1438 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1439 &g4x_wm_info, latency_ns,
1440 &g4x_cursor_wm_info, latency_ns,
1441 &planea_wm, &cursora_wm))
51cea1f4 1442 enabled |= 1 << PIPE_A;
b445e3b0 1443
51cea1f4 1444 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1445 &g4x_wm_info, latency_ns,
1446 &g4x_cursor_wm_info, latency_ns,
1447 &planeb_wm, &cursorb_wm))
51cea1f4 1448 enabled |= 1 << PIPE_B;
b445e3b0 1449
b445e3b0
ED		 1450 if (single_plane_enabled(enabled) &&
1451 g4x_compute_srwm(dev, ffs(enabled) - 1,
1452 sr_latency_ns,
1453 &g4x_wm_info,
1454 &g4x_cursor_wm_info,
52bd02d8 1455 &plane_sr, &cursor_sr)) {
b445e3b0 1456 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1457 } else {
b445e3b0
ED		 1458 I915_WRITE(FW_BLC_SELF,
1459 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1460 plane_sr = cursor_sr = 0;
1461 }
b445e3b0
ED		 1462
1463 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1464 planea_wm, cursora_wm,
1465 planeb_wm, cursorb_wm,
1466 plane_sr, cursor_sr);
1467
1468 I915_WRITE(DSPFW1,
1469 (plane_sr << DSPFW_SR_SHIFT) |
1470 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1471 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1472 planea_wm);
1473 I915_WRITE(DSPFW2,
8c919b28 1474 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1475 (cursora_wm << DSPFW_CURSORA_SHIFT));
1476 /* HPLL off in SR has some issues on G4x... disable it */
1477 I915_WRITE(DSPFW3,
8c919b28 1478 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1479 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1480}
1481
46ba614c 1482static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1483{
46ba614c 1484 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1485 struct drm_i915_private *dev_priv = dev->dev_private;
1486 struct drm_crtc *crtc;
1487 int srwm = 1;
1488 int cursor_sr = 16;
1489
1490 /* Calc sr entries for one plane configs */
1491 crtc = single_enabled_crtc(dev);
1492 if (crtc) {
1493 /* self-refresh has much higher latency */
1494 static const int sr_latency_ns = 12000;
1495 int clock = crtc->mode.clock;
1496 int htotal = crtc->mode.htotal;
1497 int hdisplay = crtc->mode.hdisplay;
1498 int pixel_size = crtc->fb->bits_per_pixel / 8;
1499 unsigned long line_time_us;
1500 int entries;
1501
1502 line_time_us = ((htotal * 1000) / clock);
1503
1504 /* Use ns/us then divide to preserve precision */
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1506 pixel_size * hdisplay;
1507 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1508 srwm = I965_FIFO_SIZE - entries;
1509 if (srwm < 0)
1510 srwm = 1;
1511 srwm &= 0x1ff;
1512 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1513 entries, srwm);
1514
1515 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1516 pixel_size * 64;
1517 entries = DIV_ROUND_UP(entries,
1518 i965_cursor_wm_info.cacheline_size);
1519 cursor_sr = i965_cursor_wm_info.fifo_size -
1520 (entries + i965_cursor_wm_info.guard_size);
1521
1522 if (cursor_sr > i965_cursor_wm_info.max_wm)
1523 cursor_sr = i965_cursor_wm_info.max_wm;
1524
1525 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1526 "cursor %d\n", srwm, cursor_sr);
1527
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1530 } else {
1531 /* Turn off self refresh if both pipes are enabled */
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1534 & ~FW_BLC_SELF_EN);
1535 }
1536
1537 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1538 srwm);
1539
1540 /* 965 has limitations... */
1541 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1542 (8 << 16) | (8 << 8) | (8 << 0));
1543 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1544 /* update cursor SR watermark */
1545 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1546}
1547
46ba614c 1548static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1549{
46ba614c 1550 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 const struct intel_watermark_params *wm_info;
1553 uint32_t fwater_lo;
1554 uint32_t fwater_hi;
1555 int cwm, srwm = 1;
1556 int fifo_size;
1557 int planea_wm, planeb_wm;
1558 struct drm_crtc *crtc, *enabled = NULL;
1559
1560 if (IS_I945GM(dev))
1561 wm_info = &i945_wm_info;
1562 else if (!IS_GEN2(dev))
1563 wm_info = &i915_wm_info;
1564 else
1565 wm_info = &i855_wm_info;
1566
1567 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1568 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1569 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1570 int cpp = crtc->fb->bits_per_pixel / 8;
1571 if (IS_GEN2(dev))
1572 cpp = 4;
1573
b445e3b0 1574 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1575 wm_info, fifo_size, cpp,
b445e3b0
ED		 1576 latency_ns);
1577 enabled = crtc;
1578 } else
1579 planea_wm = fifo_size - wm_info->guard_size;
1580
1581 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1582 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1583 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1584 int cpp = crtc->fb->bits_per_pixel / 8;
1585 if (IS_GEN2(dev))
1586 cpp = 4;
1587
b445e3b0 1588 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1589 wm_info, fifo_size, cpp,
b445e3b0
ED		 1590 latency_ns);
1591 if (enabled == NULL)
1592 enabled = crtc;
1593 else
1594 enabled = NULL;
1595 } else
1596 planeb_wm = fifo_size - wm_info->guard_size;
1597
1598 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1599
1600 /*
1601 * Overlay gets an aggressive default since video jitter is bad.
1602 */
1603 cwm = 2;
1604
1605 /* Play safe and disable self-refresh before adjusting watermarks. */
1606 if (IS_I945G(dev) || IS_I945GM(dev))
1607 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1608 else if (IS_I915GM(dev))
1609 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1610
1611 /* Calc sr entries for one plane configs */
1612 if (HAS_FW_BLC(dev) && enabled) {
1613 /* self-refresh has much higher latency */
1614 static const int sr_latency_ns = 6000;
1615 int clock = enabled->mode.clock;
1616 int htotal = enabled->mode.htotal;
1617 int hdisplay = enabled->mode.hdisplay;
1618 int pixel_size = enabled->fb->bits_per_pixel / 8;
1619 unsigned long line_time_us;
1620 int entries;
1621
1622 line_time_us = (htotal * 1000) / clock;
1623
1624 /* Use ns/us then divide to preserve precision */
1625 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1626 pixel_size * hdisplay;
1627 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1628 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1629 srwm = wm_info->fifo_size - entries;
1630 if (srwm < 0)
1631 srwm = 1;
1632
1633 if (IS_I945G(dev) || IS_I945GM(dev))
1634 I915_WRITE(FW_BLC_SELF,
1635 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1636 else if (IS_I915GM(dev))
1637 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1638 }
1639
1640 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1641 planea_wm, planeb_wm, cwm, srwm);
1642
1643 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1644 fwater_hi = (cwm & 0x1f);
1645
1646 /* Set request length to 8 cachelines per fetch */
1647 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1648 fwater_hi = fwater_hi | (1 << 8);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651 I915_WRITE(FW_BLC2, fwater_hi);
1652
1653 if (HAS_FW_BLC(dev)) {
1654 if (enabled) {
1655 if (IS_I945G(dev) || IS_I945GM(dev))
1656 I915_WRITE(FW_BLC_SELF,
1657 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1658 else if (IS_I915GM(dev))
1659 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1660 DRM_DEBUG_KMS("memory self refresh enabled\n");
1661 } else
1662 DRM_DEBUG_KMS("memory self refresh disabled\n");
1663 }
1664}
1665
46ba614c 1666static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1667{
46ba614c 1668 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 struct drm_crtc *crtc;
1671 uint32_t fwater_lo;
1672 int planea_wm;
1673
1674 crtc = single_enabled_crtc(dev);
1675 if (crtc == NULL)
1676 return;
1677
1678 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1679 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1680 4, latency_ns);
b445e3b0
ED		 1681 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1682 fwater_lo |= (3<<8) | planea_wm;
1683
1684 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1685
1686 I915_WRITE(FW_BLC, fwater_lo);
1687}
1688
b445e3b0
ED		 1689/*
1690 * Check the wm result.
1691 *
1692 * If any calculated watermark values is larger than the maximum value that
1693 * can be programmed into the associated watermark register, that watermark
1694 * must be disabled.
1695 */
1696static bool ironlake_check_srwm(struct drm_device *dev, int level,
1697 int fbc_wm, int display_wm, int cursor_wm,
1698 const struct intel_watermark_params *display,
1699 const struct intel_watermark_params *cursor)
1700{
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702
1703 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1704 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1705
1706 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1707 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1708 fbc_wm, SNB_FBC_MAX_SRWM, level);
1709
1710 /* fbc has it's own way to disable FBC WM */
1711 I915_WRITE(DISP_ARB_CTL,
1712 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1713 return false;
615aaa5f
VS		 1714 } else if (INTEL_INFO(dev)->gen >= 6) {
1715 /* enable FBC WM (except on ILK, where it must remain off) */
1716 I915_WRITE(DISP_ARB_CTL,
1717 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1718 }
1719
1720 if (display_wm > display->max_wm) {
1721 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1722 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1723 return false;
1724 }
1725
1726 if (cursor_wm > cursor->max_wm) {
1727 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1728 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1729 return false;
1730 }
1731
1732 if (!(fbc_wm || display_wm || cursor_wm)) {
1733 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1734 return false;
1735 }
1736
1737 return true;
1738}
1739
1740/*
1741 * Compute watermark values of WM[1-3],
1742 */
1743static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1744 int latency_ns,
1745 const struct intel_watermark_params *display,
1746 const struct intel_watermark_params *cursor,
1747 int *fbc_wm, int *display_wm, int *cursor_wm)
1748{
1749 struct drm_crtc *crtc;
1750 unsigned long line_time_us;
1751 int hdisplay, htotal, pixel_size, clock;
1752 int line_count, line_size;
1753 int small, large;
1754 int entries;
1755
1756 if (!latency_ns) {
1757 *fbc_wm = *display_wm = *cursor_wm = 0;
1758 return false;
1759 }
1760
1761 crtc = intel_get_crtc_for_plane(dev, plane);
1762 hdisplay = crtc->mode.hdisplay;
1763 htotal = crtc->mode.htotal;
1764 clock = crtc->mode.clock;
1765 pixel_size = crtc->fb->bits_per_pixel / 8;
1766
1767 line_time_us = (htotal * 1000) / clock;
1768 line_count = (latency_ns / line_time_us + 1000) / 1000;
1769 line_size = hdisplay * pixel_size;
1770
1771 /* Use the minimum of the small and large buffer method for primary */
1772 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1773 large = line_count * line_size;
1774
1775 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1776 *display_wm = entries + display->guard_size;
1777
1778 /*
1779 * Spec says:
1780 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1781 */
1782 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1783
1784 /* calculate the self-refresh watermark for display cursor */
1785 entries = line_count * pixel_size * 64;
1786 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1787 *cursor_wm = entries + cursor->guard_size;
1788
1789 return ironlake_check_srwm(dev, level,
1790 *fbc_wm, *display_wm, *cursor_wm,
1791 display, cursor);
1792}
1793
46ba614c 1794static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1795{
46ba614c 1796 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 int fbc_wm, plane_wm, cursor_wm;
1799 unsigned int enabled;
1800
1801 enabled = 0;
51cea1f4 1802 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1803 &ironlake_display_wm_info,
b0aea5dc 1804 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1805 &ironlake_cursor_wm_info,
b0aea5dc 1806 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1807 &plane_wm, &cursor_wm)) {
1808 I915_WRITE(WM0_PIPEA_ILK,
1809 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1810 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1811 " plane %d, " "cursor: %d\n",
1812 plane_wm, cursor_wm);
51cea1f4 1813 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1814 }
1815
51cea1f4 1816 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1817 &ironlake_display_wm_info,
b0aea5dc 1818 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1819 &ironlake_cursor_wm_info,
b0aea5dc 1820 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1821 &plane_wm, &cursor_wm)) {
1822 I915_WRITE(WM0_PIPEB_ILK,
1823 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1824 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1825 " plane %d, cursor: %d\n",
1826 plane_wm, cursor_wm);
51cea1f4 1827 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1828 }
1829
1830 /*
1831 * Calculate and update the self-refresh watermark only when one
1832 * display plane is used.
1833 */
1834 I915_WRITE(WM3_LP_ILK, 0);
1835 I915_WRITE(WM2_LP_ILK, 0);
1836 I915_WRITE(WM1_LP_ILK, 0);
1837
1838 if (!single_plane_enabled(enabled))
1839 return;
1840 enabled = ffs(enabled) - 1;
1841
1842 /* WM1 */
1843 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1844 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1845 &ironlake_display_srwm_info,
1846 &ironlake_cursor_srwm_info,
1847 &fbc_wm, &plane_wm, &cursor_wm))
1848 return;
1849
1850 I915_WRITE(WM1_LP_ILK,
1851 WM1_LP_SR_EN |
b0aea5dc 1852 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1853 (fbc_wm << WM1_LP_FBC_SHIFT) |
1854 (plane_wm << WM1_LP_SR_SHIFT) |
1855 cursor_wm);
1856
1857 /* WM2 */
1858 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1859 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM2_LP_ILK,
1866 WM2_LP_EN |
b0aea5dc 1867 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /*
1873 * WM3 is unsupported on ILK, probably because we don't have latency
1874 * data for that power state
1875 */
1876}
1877
46ba614c 1878static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1879{
46ba614c 1880 struct drm_device *dev = crtc->dev;
b445e3b0 1881 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1882 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1883 u32 val;
1884 int fbc_wm, plane_wm, cursor_wm;
1885 unsigned int enabled;
1886
1887 enabled = 0;
51cea1f4 1888 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1889 &sandybridge_display_wm_info, latency,
1890 &sandybridge_cursor_wm_info, latency,
1891 &plane_wm, &cursor_wm)) {
1892 val = I915_READ(WM0_PIPEA_ILK);
1893 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1894 I915_WRITE(WM0_PIPEA_ILK, val |
1895 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1896 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1897 " plane %d, " "cursor: %d\n",
1898 plane_wm, cursor_wm);
51cea1f4 1899 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1900 }
1901
51cea1f4 1902 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1903 &sandybridge_display_wm_info, latency,
1904 &sandybridge_cursor_wm_info, latency,
1905 &plane_wm, &cursor_wm)) {
1906 val = I915_READ(WM0_PIPEB_ILK);
1907 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1908 I915_WRITE(WM0_PIPEB_ILK, val |
1909 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1910 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1911 " plane %d, cursor: %d\n",
1912 plane_wm, cursor_wm);
51cea1f4 1913 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1914 }
1915
c43d0188
CW		 1916 /*
1917 * Calculate and update the self-refresh watermark only when one
1918 * display plane is used.
1919 *
1920 * SNB support 3 levels of watermark.
1921 *
1922 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1923 * and disabled in the descending order
1924 *
1925 */
1926 I915_WRITE(WM3_LP_ILK, 0);
1927 I915_WRITE(WM2_LP_ILK, 0);
1928 I915_WRITE(WM1_LP_ILK, 0);
1929
1930 if (!single_plane_enabled(enabled) ||
1931 dev_priv->sprite_scaling_enabled)
1932 return;
1933 enabled = ffs(enabled) - 1;
1934
1935 /* WM1 */
1936 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1937 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1938 &sandybridge_display_srwm_info,
1939 &sandybridge_cursor_srwm_info,
1940 &fbc_wm, &plane_wm, &cursor_wm))
1941 return;
1942
1943 I915_WRITE(WM1_LP_ILK,
1944 WM1_LP_SR_EN |
b0aea5dc 1945 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1946 (fbc_wm << WM1_LP_FBC_SHIFT) |
1947 (plane_wm << WM1_LP_SR_SHIFT) |
1948 cursor_wm);
1949
1950 /* WM2 */
1951 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1952 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1956 return;
1957
1958 I915_WRITE(WM2_LP_ILK,
1959 WM2_LP_EN |
b0aea5dc 1960 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1963 cursor_wm);
1964
1965 /* WM3 */
1966 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1967 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1971 return;
1972
1973 I915_WRITE(WM3_LP_ILK,
1974 WM3_LP_EN |
b0aea5dc 1975 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1978 cursor_wm);
1979}
1980
46ba614c 1981static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1982{
46ba614c 1983 struct drm_device *dev = crtc->dev;
c43d0188 1984 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1985 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 1986 u32 val;
1987 int fbc_wm, plane_wm, cursor_wm;
1988 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1989 unsigned int enabled;
1990
1991 enabled = 0;
51cea1f4 1992 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1993 &sandybridge_display_wm_info, latency,
1994 &sandybridge_cursor_wm_info, latency,
1995 &plane_wm, &cursor_wm)) {
1996 val = I915_READ(WM0_PIPEA_ILK);
1997 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1998 I915_WRITE(WM0_PIPEA_ILK, val |
1999 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2000 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2001 " plane %d, " "cursor: %d\n",
2002 plane_wm, cursor_wm);
51cea1f4 2003 enabled |= 1 << PIPE_A;
c43d0188
CW		 2004 }
2005
51cea1f4 2006 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2007 &sandybridge_display_wm_info, latency,
2008 &sandybridge_cursor_wm_info, latency,
2009 &plane_wm, &cursor_wm)) {
2010 val = I915_READ(WM0_PIPEB_ILK);
2011 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2012 I915_WRITE(WM0_PIPEB_ILK, val |
2013 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2014 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2015 " plane %d, cursor: %d\n",
2016 plane_wm, cursor_wm);
51cea1f4 2017 enabled |= 1 << PIPE_B;
c43d0188
CW		 2018 }
2019
51cea1f4 2020 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2021 &sandybridge_display_wm_info, latency,
2022 &sandybridge_cursor_wm_info, latency,
2023 &plane_wm, &cursor_wm)) {
2024 val = I915_READ(WM0_PIPEC_IVB);
2025 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2026 I915_WRITE(WM0_PIPEC_IVB, val |
2027 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2028 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2029 " plane %d, cursor: %d\n",
2030 plane_wm, cursor_wm);
51cea1f4 2031 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2032 }
2033
2034 /*
2035 * Calculate and update the self-refresh watermark only when one
2036 * display plane is used.
2037 *
2038 * SNB support 3 levels of watermark.
2039 *
2040 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2041 * and disabled in the descending order
2042 *
2043 */
2044 I915_WRITE(WM3_LP_ILK, 0);
2045 I915_WRITE(WM2_LP_ILK, 0);
2046 I915_WRITE(WM1_LP_ILK, 0);
2047
2048 if (!single_plane_enabled(enabled) ||
2049 dev_priv->sprite_scaling_enabled)
2050 return;
2051 enabled = ffs(enabled) - 1;
2052
2053 /* WM1 */
2054 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2055 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2056 &sandybridge_display_srwm_info,
2057 &sandybridge_cursor_srwm_info,
2058 &fbc_wm, &plane_wm, &cursor_wm))
2059 return;
2060
2061 I915_WRITE(WM1_LP_ILK,
2062 WM1_LP_SR_EN |
b0aea5dc 2063 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2064 (fbc_wm << WM1_LP_FBC_SHIFT) |
2065 (plane_wm << WM1_LP_SR_SHIFT) |
2066 cursor_wm);
2067
2068 /* WM2 */
2069 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2070 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2074 return;
2075
2076 I915_WRITE(WM2_LP_ILK,
2077 WM2_LP_EN |
b0aea5dc 2078 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2081 cursor_wm);
2082
c43d0188 2083 /* WM3, note we have to correct the cursor latency */
b445e3b0 2084 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2085 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2088 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2089 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2090 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2091 &sandybridge_display_srwm_info,
2092 &sandybridge_cursor_srwm_info,
2093 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2094 return;
2095
2096 I915_WRITE(WM3_LP_ILK,
2097 WM3_LP_EN |
b0aea5dc 2098 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2099 (fbc_wm << WM1_LP_FBC_SHIFT) |
2100 (plane_wm << WM1_LP_SR_SHIFT) |
2101 cursor_wm);
2102}
2103
3658729a
VS		 2104static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2105 struct drm_crtc *crtc)
801bcfff
PZ		 2106{
2107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2108 uint32_t pixel_rate, pfit_size;
2109
ff9a6750 2110 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2111
2112 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2113 * adjust the pixel_rate here. */
2114
2115 pfit_size = intel_crtc->config.pch_pfit.size;
2116 if (pfit_size) {
2117 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2118
2119 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2120 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2121 pfit_w = (pfit_size >> 16) & 0xFFFF;
2122 pfit_h = pfit_size & 0xFFFF;
2123 if (pipe_w < pfit_w)
2124 pipe_w = pfit_w;
2125 if (pipe_h < pfit_h)
2126 pipe_h = pfit_h;
2127
2128 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2129 pfit_w * pfit_h);
2130 }
2131
2132 return pixel_rate;
2133}
2134
37126462 2135/* latency must be in 0.1us units. */
23297044 2136static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2137 uint32_t latency)
2138{
2139 uint64_t ret;
2140
3312ba65
VS		 2141 if (WARN(latency == 0, "Latency value missing\n"))
2142 return UINT_MAX;
2143
801bcfff
PZ		 2144 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2145 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2146
2147 return ret;
2148}
2149
37126462 2150/* latency must be in 0.1us units. */
23297044 2151static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2152 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2153 uint32_t latency)
2154{
2155 uint32_t ret;
2156
3312ba65
VS		 2157 if (WARN(latency == 0, "Latency value missing\n"))
2158 return UINT_MAX;
2159
801bcfff
PZ		 2160 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2161 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2162 ret = DIV_ROUND_UP(ret, 64) + 2;
2163 return ret;
2164}
2165
23297044 2166static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2167 uint8_t bytes_per_pixel)
2168{
2169 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2170}
2171
801bcfff
PZ		 2172struct hsw_pipe_wm_parameters {
2173 bool active;
801bcfff
PZ		 2174 uint32_t pipe_htotal;
2175 uint32_t pixel_rate;
c35426d2
VS		 2176 struct intel_plane_wm_parameters pri;
2177 struct intel_plane_wm_parameters spr;
2178 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2179};
2180
cca32e9a
PZ		 2181struct hsw_wm_maximums {
2182 uint16_t pri;
2183 uint16_t spr;
2184 uint16_t cur;
2185 uint16_t fbc;
2186};
2187
801bcfff
PZ		 2188struct hsw_wm_values {
2189 uint32_t wm_pipe[3];
2190 uint32_t wm_lp[3];
2191 uint32_t wm_lp_spr[3];
2192 uint32_t wm_linetime[3];
cca32e9a 2193 bool enable_fbc_wm;
801bcfff
PZ		 2194};
2195
240264f4
VS		 2196/* used in computing the new watermarks state */
2197struct intel_wm_config {
2198 unsigned int num_pipes_active;
2199 bool sprites_enabled;
2200 bool sprites_scaled;
2201 bool fbc_wm_enabled;
2202};
2203
37126462
VS		 2204/*
2205 * For both WM_PIPE and WM_LP.
2206 * mem_value must be in 0.1us units.
2207 */
ac830fe1 2208static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2209 uint32_t mem_value,
2210 bool is_lp)
801bcfff 2211{
cca32e9a
PZ		 2212 uint32_t method1, method2;
2213
c35426d2 2214 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2215 return 0;
2216
23297044 2217 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2218 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2219 mem_value);
2220
2221 if (!is_lp)
2222 return method1;
2223
23297044 2224 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2225 params->pipe_htotal,
c35426d2
VS		 2226 params->pri.horiz_pixels,
2227 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2228 mem_value);
2229
2230 return min(method1, method2);
801bcfff
PZ		 2231}
2232
37126462
VS		 2233/*
2234 * For both WM_PIPE and WM_LP.
2235 * mem_value must be in 0.1us units.
2236 */
ac830fe1 2237static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2238 uint32_t mem_value)
2239{
2240 uint32_t method1, method2;
2241
c35426d2 2242 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2243 return 0;
2244
23297044 2245 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2246 params->spr.bytes_per_pixel,
801bcfff 2247 mem_value);
23297044 2248 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2249 params->pipe_htotal,
c35426d2
VS		 2250 params->spr.horiz_pixels,
2251 params->spr.bytes_per_pixel,
801bcfff
PZ		 2252 mem_value);
2253 return min(method1, method2);
2254}
2255
37126462
VS		 2256/*
2257 * For both WM_PIPE and WM_LP.
2258 * mem_value must be in 0.1us units.
2259 */
ac830fe1 2260static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2261 uint32_t mem_value)
2262{
c35426d2 2263 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2264 return 0;
2265
23297044 2266 return ilk_wm_method2(params->pixel_rate,
801bcfff 2267 params->pipe_htotal,
c35426d2
VS		 2268 params->cur.horiz_pixels,
2269 params->cur.bytes_per_pixel,
801bcfff
PZ		 2270 mem_value);
2271}
2272
cca32e9a 2273/* Only for WM_LP. */
ac830fe1 2274static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2275 uint32_t pri_val)
cca32e9a 2276{
c35426d2 2277 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2278 return 0;
2279
23297044 2280 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2281 params->pri.horiz_pixels,
2282 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2283}
2284
158ae64f
VS		 2285static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2286{
2287 if (INTEL_INFO(dev)->gen >= 7)
2288 return 768;
2289 else
2290 return 512;
2291}
2292
2293/* Calculate the maximum primary/sprite plane watermark */
2294static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2295 int level,
240264f4 2296 const struct intel_wm_config *config,
158ae64f
VS		 2297 enum intel_ddb_partitioning ddb_partitioning,
2298 bool is_sprite)
2299{
2300 unsigned int fifo_size = ilk_display_fifo_size(dev);
2301 unsigned int max;
2302
2303 /* if sprites aren't enabled, sprites get nothing */
240264f4 2304 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2305 return 0;
2306
2307 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2308 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2309 fifo_size /= INTEL_INFO(dev)->num_pipes;
2310
2311 /*
2312 * For some reason the non self refresh
2313 * FIFO size is only half of the self
2314 * refresh FIFO size on ILK/SNB.
2315 */
2316 if (INTEL_INFO(dev)->gen <= 6)
2317 fifo_size /= 2;
2318 }
2319
240264f4 2320 if (config->sprites_enabled) {
158ae64f
VS		 2321 /* level 0 is always calculated with 1:1 split */
2322 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2323 if (is_sprite)
2324 fifo_size *= 5;
2325 fifo_size /= 6;
2326 } else {
2327 fifo_size /= 2;
2328 }
2329 }
2330
2331 /* clamp to max that the registers can hold */
2332 if (INTEL_INFO(dev)->gen >= 7)
2333 /* IVB/HSW primary/sprite plane watermarks */
2334 max = level == 0 ? 127 : 1023;
2335 else if (!is_sprite)
2336 /* ILK/SNB primary plane watermarks */
2337 max = level == 0 ? 127 : 511;
2338 else
2339 /* ILK/SNB sprite plane watermarks */
2340 max = level == 0 ? 63 : 255;
2341
2342 return min(fifo_size, max);
2343}
2344
2345/* Calculate the maximum cursor plane watermark */
2346static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2347 int level,
2348 const struct intel_wm_config *config)
158ae64f
VS		 2349{
2350 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2351 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2352 return 64;
2353
2354 /* otherwise just report max that registers can hold */
2355 if (INTEL_INFO(dev)->gen >= 7)
2356 return level == 0 ? 63 : 255;
2357 else
2358 return level == 0 ? 31 : 63;
2359}
2360
2361/* Calculate the maximum FBC watermark */
2362static unsigned int ilk_fbc_wm_max(void)
2363{
2364 /* max that registers can hold */
2365 return 15;
2366}
2367
2368static void ilk_wm_max(struct drm_device *dev,
2369 int level,
240264f4 2370 const struct intel_wm_config *config,
158ae64f
VS		 2371 enum intel_ddb_partitioning ddb_partitioning,
2372 struct hsw_wm_maximums *max)
2373{
240264f4
VS		 2374 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2375 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2376 max->cur = ilk_cursor_wm_max(dev, level, config);
158ae64f
VS		 2377 max->fbc = ilk_fbc_wm_max();
2378}
2379
a9786a11
VS		 2380static bool ilk_check_wm(int level,
2381 const struct hsw_wm_maximums *max,
1fd527cc 2382 struct intel_wm_level *result)
a9786a11
VS		 2383{
2384 bool ret;
2385
2386 /* already determined to be invalid? */
2387 if (!result->enable)
2388 return false;
2389
2390 result->enable = result->pri_val <= max->pri &&
2391 result->spr_val <= max->spr &&
2392 result->cur_val <= max->cur;
2393
2394 ret = result->enable;
2395
2396 /*
2397 * HACK until we can pre-compute everything,
2398 * and thus fail gracefully if LP0 watermarks
2399 * are exceeded...
2400 */
2401 if (level == 0 && !result->enable) {
2402 if (result->pri_val > max->pri)
2403 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2404 level, result->pri_val, max->pri);
2405 if (result->spr_val > max->spr)
2406 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2407 level, result->spr_val, max->spr);
2408 if (result->cur_val > max->cur)
2409 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2410 level, result->cur_val, max->cur);
2411
2412 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2413 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2414 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2415 result->enable = true;
2416 }
2417
2418 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2419
2420 return ret;
2421}
2422
6f5ddd17
VS		 2423static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2424 int level,
ac830fe1 2425 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2426 struct intel_wm_level *result)
6f5ddd17
VS		 2427{
2428 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2429 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2430 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2431
2432 /* WM1+ latency values stored in 0.5us units */
2433 if (level > 0) {
2434 pri_latency *= 5;
2435 spr_latency *= 5;
2436 cur_latency *= 5;
2437 }
2438
2439 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2440 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2441 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2442 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2443 result->enable = true;
2444}
2445
5b77da33 2446static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
ac830fe1
VS		 2447 int level, const struct hsw_wm_maximums *max,
2448 const struct hsw_pipe_wm_parameters *params,
1fd527cc 2449 struct intel_wm_level *result)
cca32e9a
PZ		 2450{
2451 enum pipe pipe;
1fd527cc 2452 struct intel_wm_level res[3];
6f5ddd17
VS		 2453
2454 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2455 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
cca32e9a 2456
6f5ddd17
VS		 2457 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2458 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2459 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2460 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2461 result->enable = true;
cca32e9a 2462
a9786a11 2463 return ilk_check_wm(level, max, result);
cca32e9a
PZ		 2464}
2465
8de123a5
VS		 2466
2467static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
ac830fe1 2468 const struct hsw_pipe_wm_parameters *params)
801bcfff 2469{
8de123a5
VS		 2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_wm_config config = {
2472 .num_pipes_active = 1,
2473 .sprites_enabled = params->spr.enabled,
2474 .sprites_scaled = params->spr.scaled,
2475 };
2476 struct hsw_wm_maximums max;
2477 struct intel_wm_level res;
2478
2479 if (!params->active)
2480 return 0;
2481
2482 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
801bcfff 2483
8de123a5 2484 ilk_compute_wm_level(dev_priv, 0, params, &res);
801bcfff 2485
8de123a5 2486 ilk_check_wm(0, &max, &res);
801bcfff 2487
8de123a5
VS		 2488 return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
2489 (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
2490 res.cur_val;
801bcfff
PZ		 2491}
2492
2493static uint32_t
2494hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2495{
2496 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2498 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2499 u32 linetime, ips_linetime;
1f8eeabf 2500
801bcfff
PZ		 2501 if (!intel_crtc_active(crtc))
2502 return 0;
1011d8c4 2503
1f8eeabf
ED		 2504 /* The WM are computed with base on how long it takes to fill a single
2505 * row at the given clock rate, multiplied by 8.
2506 * */
85a02deb
PZ		 2507 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2508 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2509 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2510
801bcfff
PZ		 2511 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2512 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2513}
2514
12b134df
VS		 2515static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2516{
2517 struct drm_i915_private *dev_priv = dev->dev_private;
2518
2519 if (IS_HASWELL(dev)) {
2520 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2521
2522 wm[0] = (sskpd >> 56) & 0xFF;
2523 if (wm[0] == 0)
2524 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2525 wm[1] = (sskpd >> 4) & 0xFF;
2526 wm[2] = (sskpd >> 12) & 0xFF;
2527 wm[3] = (sskpd >> 20) & 0x1FF;
2528 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2529 } else if (INTEL_INFO(dev)->gen >= 6) {
2530 uint32_t sskpd = I915_READ(MCH_SSKPD);
2531
2532 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2533 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2534 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2535 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2536 } else if (INTEL_INFO(dev)->gen >= 5) {
2537 uint32_t mltr = I915_READ(MLTR_ILK);
2538
2539 /* ILK primary LP0 latency is 700 ns */
2540 wm[0] = 7;
2541 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2542 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2543 }
2544}
2545
53615a5e
VS		 2546static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2547{
2548 /* ILK sprite LP0 latency is 1300 ns */
2549 if (INTEL_INFO(dev)->gen == 5)
2550 wm[0] = 13;
2551}
2552
2553static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2554{
2555 /* ILK cursor LP0 latency is 1300 ns */
2556 if (INTEL_INFO(dev)->gen == 5)
2557 wm[0] = 13;
2558
2559 /* WaDoubleCursorLP3Latency:ivb */
2560 if (IS_IVYBRIDGE(dev))
2561 wm[3] *= 2;
2562}
2563
ad0d6dc4 2564static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2565{
26ec971e
VS		 2566 /* how many WM levels are we expecting */
2567 if (IS_HASWELL(dev))
ad0d6dc4 2568 return 4;
26ec971e 2569 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2570 return 3;
26ec971e 2571 else
ad0d6dc4
VS		 2572 return 2;
2573}
2574
2575static void intel_print_wm_latency(struct drm_device *dev,
2576 const char *name,
2577 const uint16_t wm[5])
2578{
2579 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2580
2581 for (level = 0; level <= max_level; level++) {
2582 unsigned int latency = wm[level];
2583
2584 if (latency == 0) {
2585 DRM_ERROR("%s WM%d latency not provided\n",
2586 name, level);
2587 continue;
2588 }
2589
2590 /* WM1+ latency values in 0.5us units */
2591 if (level > 0)
2592 latency *= 5;
2593
2594 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2595 name, level, wm[level],
2596 latency / 10, latency % 10);
2597 }
2598}
2599
53615a5e
VS		 2600static void intel_setup_wm_latency(struct drm_device *dev)
2601{
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603
2604 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2605
2606 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2607 sizeof(dev_priv->wm.pri_latency));
2608 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2609 sizeof(dev_priv->wm.pri_latency));
2610
2611 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2612 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2613
2614 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2615 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2616 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2617}
2618
801bcfff
PZ		 2619static void hsw_compute_wm_parameters(struct drm_device *dev,
2620 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2621 struct hsw_wm_maximums *lp_max_1_2,
2622 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2623{
1011d8c4 2624 struct drm_crtc *crtc;
801bcfff 2625 struct drm_plane *plane;
1011d8c4 2626 enum pipe pipe;
240264f4 2627 struct intel_wm_config config = {};
1011d8c4 2628
801bcfff
PZ		 2629 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631 struct hsw_pipe_wm_parameters *p;
2632
2633 pipe = intel_crtc->pipe;
2634 p = &params[pipe];
2635
2636 p->active = intel_crtc_active(crtc);
2637 if (!p->active)
2638 continue;
2639
240264f4 2640 config.num_pipes_active++;
cca32e9a 2641
801bcfff 2642 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2643 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2644 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2645 p->cur.bytes_per_pixel = 4;
2646 p->pri.horiz_pixels =
801bcfff 2647 intel_crtc->config.requested_mode.hdisplay;
c35426d2
VS		 2648 p->cur.horiz_pixels = 64;
2649 /* TODO: for now, assume primary and cursor planes are always enabled. */
2650 p->pri.enabled = true;
2651 p->cur.enabled = true;
801bcfff
PZ		 2652 }
2653
2654 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2655 struct intel_plane *intel_plane = to_intel_plane(plane);
2656 struct hsw_pipe_wm_parameters *p;
2657
2658 pipe = intel_plane->pipe;
2659 p = &params[pipe];
2660
c35426d2 2661 p->spr = intel_plane->wm;
cca32e9a 2662
c35426d2
VS		 2663 config.sprites_enabled |= p->spr.enabled;
2664 config.sprites_scaled |= p->spr.scaled;
cca32e9a
PZ		 2665 }
2666
240264f4 2667 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
158ae64f
VS		 2668
2669 /* 5/6 split only in single pipe config on IVB+ */
240264f4
VS		 2670 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2671 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
158ae64f
VS		 2672 else
2673 *lp_max_5_6 = *lp_max_1_2;
801bcfff
PZ		 2674}
2675
2676static void hsw_compute_wm_results(struct drm_device *dev,
ac830fe1
VS		 2677 const struct hsw_pipe_wm_parameters *params,
2678 const struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2679 struct hsw_wm_values *results)
2680{
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct drm_crtc *crtc;
1fd527cc 2683 struct intel_wm_level lp_results[4] = {};
801bcfff 2684 enum pipe pipe;
cca32e9a
PZ		 2685 int level, max_level, wm_lp;
2686
2687 for (level = 1; level <= 4; level++)
5b77da33
VS		 2688 if (!hsw_compute_lp_wm(dev_priv, level,
2689 lp_maximums, params,
cca32e9a
PZ		 2690 &lp_results[level - 1]))
2691 break;
2692 max_level = level - 1;
2693
5c536613
VS		 2694 memset(results, 0, sizeof(*results));
2695
cca32e9a
PZ		 2696 /* The spec says it is preferred to disable FBC WMs instead of disabling
2697 * a WM level. */
2698 results->enable_fbc_wm = true;
2699 for (level = 1; level <= max_level; level++) {
16e54061 2700 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
cca32e9a 2701 results->enable_fbc_wm = false;
71fff20f 2702 lp_results[level - 1].fbc_val = 0;
cca32e9a
PZ		 2703 }
2704 }
2705
cca32e9a 2706 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2707 const struct intel_wm_level *r;
801bcfff 2708
cca32e9a
PZ		 2709 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2710 if (level > max_level)
2711 break;
2712
2713 r = &lp_results[level - 1];
2714 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2715 r->fbc_val,
2716 r->pri_val,
2717 r->cur_val);
2718 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2719 }
801bcfff
PZ		 2720
2721 for_each_pipe(pipe)
8de123a5 2722 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
801bcfff 2723 &params[pipe]);
1011d8c4
PZ		 2724
2725 for_each_pipe(pipe) {
2726 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2727 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2728 }
2729}
2730
861f3389
PZ		 2731/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2732 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2733static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2734 struct hsw_wm_values *r2)
861f3389
PZ		 2735{
2736 int i, val_r1 = 0, val_r2 = 0;
2737
2738 for (i = 0; i < 3; i++) {
2739 if (r1->wm_lp[i] & WM3_LP_EN)
2740 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2741 if (r2->wm_lp[i] & WM3_LP_EN)
2742 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2743 }
2744
2745 if (val_r1 == val_r2) {
2746 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2747 return r2;
2748 else
2749 return r1;
2750 } else if (val_r1 > val_r2) {
2751 return r1;
2752 } else {
2753 return r2;
2754 }
2755}
2756
801bcfff
PZ		 2757/*
2758 * The spec says we shouldn't write when we don't need, because every write
2759 * causes WMs to be re-evaluated, expending some power.
2760 */
2761static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2762 struct hsw_wm_values *results,
77c122bc 2763 enum intel_ddb_partitioning partitioning)
801bcfff
PZ		 2764{
2765 struct hsw_wm_values previous;
2766 uint32_t val;
77c122bc 2767 enum intel_ddb_partitioning prev_partitioning;
cca32e9a 2768 bool prev_enable_fbc_wm;
801bcfff
PZ		 2769
2770 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2771 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2772 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2773 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2774 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2775 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2776 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2777 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2778 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2779 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2780 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2781 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2782
2783 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
77c122bc 2784 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
801bcfff 2785
cca32e9a
PZ		 2786 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2787
801bcfff
PZ		 2788 if (memcmp(results->wm_pipe, previous.wm_pipe,
2789 sizeof(results->wm_pipe)) == 0 &&
2790 memcmp(results->wm_lp, previous.wm_lp,
2791 sizeof(results->wm_lp)) == 0 &&
2792 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2793 sizeof(results->wm_lp_spr)) == 0 &&
2794 memcmp(results->wm_linetime, previous.wm_linetime,
2795 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2796 partitioning == prev_partitioning &&
2797 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2798 return;
2799
2800 if (previous.wm_lp[2] != 0)
2801 I915_WRITE(WM3_LP_ILK, 0);
2802 if (previous.wm_lp[1] != 0)
2803 I915_WRITE(WM2_LP_ILK, 0);
2804 if (previous.wm_lp[0] != 0)
2805 I915_WRITE(WM1_LP_ILK, 0);
2806
2807 if (previous.wm_pipe[0] != results->wm_pipe[0])
2808 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2809 if (previous.wm_pipe[1] != results->wm_pipe[1])
2810 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2811 if (previous.wm_pipe[2] != results->wm_pipe[2])
2812 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2813
2814 if (previous.wm_linetime[0] != results->wm_linetime[0])
2815 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2816 if (previous.wm_linetime[1] != results->wm_linetime[1])
2817 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2818 if (previous.wm_linetime[2] != results->wm_linetime[2])
2819 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2820
2821 if (prev_partitioning != partitioning) {
2822 val = I915_READ(WM_MISC);
77c122bc 2823 if (partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2824 val &= ~WM_MISC_DATA_PARTITION_5_6;
2825 else
2826 val |= WM_MISC_DATA_PARTITION_5_6;
2827 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2828 }
2829
cca32e9a
PZ		 2830 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
801bcfff
PZ		 2839 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2840 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2841 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2842 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2843 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2844 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2845
2846 if (results->wm_lp[0] != 0)
2847 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2848 if (results->wm_lp[1] != 0)
2849 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2850 if (results->wm_lp[2] != 0)
2851 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2852}
2853
46ba614c 2854static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2855{
46ba614c 2856 struct drm_device *dev = crtc->dev;
801bcfff 2857 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2858 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2859 struct hsw_pipe_wm_parameters params[3];
861f3389 2860 struct hsw_wm_values results_1_2, results_5_6, *best_results;
77c122bc 2861 enum intel_ddb_partitioning partitioning;
861f3389 2862
12b134df 2863 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2864
53615a5e 2865 hsw_compute_wm_results(dev, params,
53615a5e 2866 &lp_max_1_2, &results_1_2);
861f3389 2867 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2868 hsw_compute_wm_results(dev, params,
53615a5e 2869 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2870 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2871 } else {
2872 best_results = &results_1_2;
2873 }
2874
2875 partitioning = (best_results == &results_1_2) ?
77c122bc 2876 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2877
861f3389 2878 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2879}
2880
adf3d35e
VS		 2881static void haswell_update_sprite_wm(struct drm_plane *plane,
2882 struct drm_crtc *crtc,
526682e9 2883 uint32_t sprite_width, int pixel_size,
bdd57d03 2884 bool enabled, bool scaled)
526682e9 2885{
adf3d35e 2886 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2887
adf3d35e
VS		 2888 intel_plane->wm.enabled = enabled;
2889 intel_plane->wm.scaled = scaled;
2890 intel_plane->wm.horiz_pixels = sprite_width;
2891 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2892
46ba614c 2893 haswell_update_wm(crtc);
526682e9
PZ		 2894}
2895
b445e3b0
ED		 2896static bool
2897sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2898 uint32_t sprite_width, int pixel_size,
2899 const struct intel_watermark_params *display,
2900 int display_latency_ns, int *sprite_wm)
2901{
2902 struct drm_crtc *crtc;
2903 int clock;
2904 int entries, tlb_miss;
2905
2906 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2907 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2908 *sprite_wm = display->guard_size;
2909 return false;
2910 }
2911
2912 clock = crtc->mode.clock;
2913
2914 /* Use the small buffer method to calculate the sprite watermark */
2915 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2916 tlb_miss = display->fifo_size*display->cacheline_size -
2917 sprite_width * 8;
2918 if (tlb_miss > 0)
2919 entries += tlb_miss;
2920 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2921 *sprite_wm = entries + display->guard_size;
2922 if (*sprite_wm > (int)display->max_wm)
2923 *sprite_wm = display->max_wm;
2924
2925 return true;
2926}
2927
2928static bool
2929sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2930 uint32_t sprite_width, int pixel_size,
2931 const struct intel_watermark_params *display,
2932 int latency_ns, int *sprite_wm)
2933{
2934 struct drm_crtc *crtc;
2935 unsigned long line_time_us;
2936 int clock;
2937 int line_count, line_size;
2938 int small, large;
2939 int entries;
2940
2941 if (!latency_ns) {
2942 *sprite_wm = 0;
2943 return false;
2944 }
2945
2946 crtc = intel_get_crtc_for_plane(dev, plane);
2947 clock = crtc->mode.clock;
2948 if (!clock) {
2949 *sprite_wm = 0;
2950 return false;
2951 }
2952
2953 line_time_us = (sprite_width * 1000) / clock;
2954 if (!line_time_us) {
2955 *sprite_wm = 0;
2956 return false;
2957 }
2958
2959 line_count = (latency_ns / line_time_us + 1000) / 1000;
2960 line_size = sprite_width * pixel_size;
2961
2962 /* Use the minimum of the small and large buffer method for primary */
2963 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2964 large = line_count * line_size;
2965
2966 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2967 *sprite_wm = entries + display->guard_size;
2968
2969 return *sprite_wm > 0x3ff ? false : true;
2970}
2971
adf3d35e
VS		 2972static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2973 struct drm_crtc *crtc,
4c4ff43a 2974 uint32_t sprite_width, int pixel_size,
39db4a4d 2975 bool enabled, bool scaled)
b445e3b0 2976{
adf3d35e 2977 struct drm_device *dev = plane->dev;
b445e3b0 2978 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 2979 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 2980 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2981 u32 val;
2982 int sprite_wm, reg;
2983 int ret;
2984
39db4a4d 2985 if (!enabled)
4c4ff43a
PZ		 2986 return;
2987
b445e3b0
ED		 2988 switch (pipe) {
2989 case 0:
2990 reg = WM0_PIPEA_ILK;
2991 break;
2992 case 1:
2993 reg = WM0_PIPEB_ILK;
2994 break;
2995 case 2:
2996 reg = WM0_PIPEC_IVB;
2997 break;
2998 default:
2999 return; /* bad pipe */
3000 }
3001
3002 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3003 &sandybridge_display_wm_info,
3004 latency, &sprite_wm);
3005 if (!ret) {
84f44ce7
VS		 3006 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3007 pipe_name(pipe));
b445e3b0
ED		 3008 return;
3009 }
3010
3011 val = I915_READ(reg);
3012 val &= ~WM0_PIPE_SPRITE_MASK;
3013 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3014 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3015
3016
3017 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3018 pixel_size,
3019 &sandybridge_display_srwm_info,
b0aea5dc 3020 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3021 &sprite_wm);
3022 if (!ret) {
84f44ce7
VS		 3023 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3024 pipe_name(pipe));
b445e3b0
ED		 3025 return;
3026 }
3027 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3028
3029 /* Only IVB has two more LP watermarks for sprite */
3030 if (!IS_IVYBRIDGE(dev))
3031 return;
3032
3033 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3034 pixel_size,
3035 &sandybridge_display_srwm_info,
b0aea5dc 3036 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3037 &sprite_wm);
3038 if (!ret) {
84f44ce7
VS		 3039 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3040 pipe_name(pipe));
b445e3b0
ED		 3041 return;
3042 }
3043 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3044
3045 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3046 pixel_size,
3047 &sandybridge_display_srwm_info,
b0aea5dc 3048 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3049 &sprite_wm);
3050 if (!ret) {
84f44ce7
VS		 3051 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3052 pipe_name(pipe));
b445e3b0
ED		 3053 return;
3054 }
3055 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3056}
3057
3058/**
3059 * intel_update_watermarks - update FIFO watermark values based on current modes
3060 *
3061 * Calculate watermark values for the various WM regs based on current mode
3062 * and plane configuration.
3063 *
3064 * There are several cases to deal with here:
3065 * - normal (i.e. non-self-refresh)
3066 * - self-refresh (SR) mode
3067 * - lines are large relative to FIFO size (buffer can hold up to 2)
3068 * - lines are small relative to FIFO size (buffer can hold more than 2
3069 * lines), so need to account for TLB latency
3070 *
3071 * The normal calculation is:
3072 * watermark = dotclock * bytes per pixel * latency
3073 * where latency is platform & configuration dependent (we assume pessimal
3074 * values here).
3075 *
3076 * The SR calculation is:
3077 * watermark = (trunc(latency/line time)+1) * surface width *
3078 * bytes per pixel
3079 * where
3080 * line time = htotal / dotclock
3081 * surface width = hdisplay for normal plane and 64 for cursor
3082 * and latency is assumed to be high, as above.
3083 *
3084 * The final value programmed to the register should always be rounded up,
3085 * and include an extra 2 entries to account for clock crossings.
3086 *
3087 * We don't use the sprite, so we can ignore that. And on Crestline we have
3088 * to set the non-SR watermarks to 8.
3089 */
46ba614c 3090void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3091{
46ba614c 3092 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3093
3094 if (dev_priv->display.update_wm)
46ba614c 3095 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3096}
3097
adf3d35e
VS		 3098void intel_update_sprite_watermarks(struct drm_plane *plane,
3099 struct drm_crtc *crtc,
4c4ff43a 3100 uint32_t sprite_width, int pixel_size,
39db4a4d 3101 bool enabled, bool scaled)
b445e3b0 3102{
adf3d35e 3103 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3104
3105 if (dev_priv->display.update_sprite_wm)
adf3d35e 3106 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3107 pixel_size, enabled, scaled);
b445e3b0
ED		 3108}
3109
2b4e57bd
ED		 3110static struct drm_i915_gem_object *
3111intel_alloc_context_page(struct drm_device *dev)
3112{
3113 struct drm_i915_gem_object *ctx;
3114 int ret;
3115
3116 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3117
3118 ctx = i915_gem_alloc_object(dev, 4096);
3119 if (!ctx) {
3120 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3121 return NULL;
3122 }
3123
c37e2204 3124 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3125 if (ret) {
3126 DRM_ERROR("failed to pin power context: %d\n", ret);
3127 goto err_unref;
3128 }
3129
3130 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3131 if (ret) {
3132 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3133 goto err_unpin;
3134 }
3135
3136 return ctx;
3137
3138err_unpin:
3139 i915_gem_object_unpin(ctx);
3140err_unref:
3141 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3142 return NULL;
3143}
3144
9270388e
DV		 3145/**
3146 * Lock protecting IPS related data structures
9270388e
DV		 3147 */
3148DEFINE_SPINLOCK(mchdev_lock);
3149
3150/* Global for IPS driver to get at the current i915 device. Protected by
3151 * mchdev_lock. */
3152static struct drm_i915_private *i915_mch_dev;
3153
2b4e57bd
ED		 3154bool ironlake_set_drps(struct drm_device *dev, u8 val)
3155{
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 u16 rgvswctl;
3158
9270388e
DV		 3159 assert_spin_locked(&mchdev_lock);
3160
2b4e57bd
ED		 3161 rgvswctl = I915_READ16(MEMSWCTL);
3162 if (rgvswctl & MEMCTL_CMD_STS) {
3163 DRM_DEBUG("gpu busy, RCS change rejected\n");
3164 return false; /* still busy with another command */
3165 }
3166
3167 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3168 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3169 I915_WRITE16(MEMSWCTL, rgvswctl);
3170 POSTING_READ16(MEMSWCTL);
3171
3172 rgvswctl |= MEMCTL_CMD_STS;
3173 I915_WRITE16(MEMSWCTL, rgvswctl);
3174
3175 return true;
3176}
3177
8090c6b9 3178static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3179{
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 u32 rgvmodectl = I915_READ(MEMMODECTL);
3182 u8 fmax, fmin, fstart, vstart;
3183
9270388e
DV		 3184 spin_lock_irq(&mchdev_lock);
3185
2b4e57bd
ED		 3186 /* Enable temp reporting */
3187 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3188 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3189
3190 /* 100ms RC evaluation intervals */
3191 I915_WRITE(RCUPEI, 100000);
3192 I915_WRITE(RCDNEI, 100000);
3193
3194 /* Set max/min thresholds to 90ms and 80ms respectively */
3195 I915_WRITE(RCBMAXAVG, 90000);
3196 I915_WRITE(RCBMINAVG, 80000);
3197
3198 I915_WRITE(MEMIHYST, 1);
3199
3200 /* Set up min, max, and cur for interrupt handling */
3201 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3202 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3203 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3204 MEMMODE_FSTART_SHIFT;
3205
3206 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3207 PXVFREQ_PX_SHIFT;
3208
20e4d407
DV		 3209 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3210 dev_priv->ips.fstart = fstart;
2b4e57bd 3211
20e4d407
DV		 3212 dev_priv->ips.max_delay = fstart;
3213 dev_priv->ips.min_delay = fmin;
3214 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3215
3216 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3217 fmax, fmin, fstart);
3218
3219 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3220
3221 /*
3222 * Interrupts will be enabled in ironlake_irq_postinstall
3223 */
3224
3225 I915_WRITE(VIDSTART, vstart);
3226 POSTING_READ(VIDSTART);
3227
3228 rgvmodectl |= MEMMODE_SWMODE_EN;
3229 I915_WRITE(MEMMODECTL, rgvmodectl);
3230
9270388e 3231 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3232 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3233 mdelay(1);
2b4e57bd
ED		 3234
3235 ironlake_set_drps(dev, fstart);
3236
20e4d407 3237 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3238 I915_READ(0x112e0);
20e4d407
DV		 3239 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3240 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3241 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3242
3243 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3244}
3245
8090c6b9 3246static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3247{
3248 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3249 u16 rgvswctl;
3250
3251 spin_lock_irq(&mchdev_lock);
3252
3253 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3254
3255 /* Ack interrupts, disable EFC interrupt */
3256 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3257 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3258 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3259 I915_WRITE(DEIIR, DE_PCU_EVENT);
3260 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3261
3262 /* Go back to the starting frequency */
20e4d407 3263 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3264 mdelay(1);
2b4e57bd
ED		 3265 rgvswctl |= MEMCTL_CMD_STS;
3266 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3267 mdelay(1);
2b4e57bd 3268
9270388e 3269 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3270}
3271
acbe9475
DV		 3272/* There's a funny hw issue where the hw returns all 0 when reading from
3273 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3274 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3275 * all limits and the gpu stuck at whatever frequency it is at atm).
3276 */
65bccb5c 3277static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3278{
7b9e0ae6 3279 u32 limits;
2b4e57bd 3280
7b9e0ae6 3281 limits = 0;
c6a828d3
DV		 3282
3283 if (*val >= dev_priv->rps.max_delay)
3284 *val = dev_priv->rps.max_delay;
3285 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3286
3287 /* Only set the down limit when we've reached the lowest level to avoid
3288 * getting more interrupts, otherwise leave this clear. This prevents a
3289 * race in the hw when coming out of rc6: There's a tiny window where
3290 * the hw runs at the minimal clock before selecting the desired
3291 * frequency, if the down threshold expires in that window we will not
3292 * receive a down interrupt. */
c6a828d3
DV		 3293 if (*val <= dev_priv->rps.min_delay) {
3294 *val = dev_priv->rps.min_delay;
3295 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3296 }
3297
3298 return limits;
3299}
3300
3301void gen6_set_rps(struct drm_device *dev, u8 val)
3302{
3303 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3304 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3305
4fc688ce 3306 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3307 WARN_ON(val > dev_priv->rps.max_delay);
3308 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3309
c6a828d3 3310 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3311 return;
3312
92bd1bf0
RV		 3313 if (IS_HASWELL(dev))
3314 I915_WRITE(GEN6_RPNSWREQ,
3315 HSW_FREQUENCY(val));
3316 else
3317 I915_WRITE(GEN6_RPNSWREQ,
3318 GEN6_FREQUENCY(val) |
3319 GEN6_OFFSET(0) |
3320 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3321
3322 /* Make sure we continue to get interrupts
3323 * until we hit the minimum or maximum frequencies.
3324 */
3325 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3326
d5570a72
BW		 3327 POSTING_READ(GEN6_RPNSWREQ);
3328
c6a828d3 3329 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3330
3331 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3332}
3333
80814ae4
VS		 3334/*
3335 * Wait until the previous freq change has completed,
3336 * or the timeout elapsed, and then update our notion
3337 * of the current GPU frequency.
3338 */
3339static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3340{
80814ae4
VS		 3341 u32 pval;
3342
3343 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3344
e8474409
VS		 3345 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3346 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3347
3348 pval >>= 8;
3349
3350 if (pval != dev_priv->rps.cur_delay)
3351 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3352 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3353 dev_priv->rps.cur_delay,
3354 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3355
3356 dev_priv->rps.cur_delay = pval;
3357}
3358
0a073b84
JB		 3359void valleyview_set_rps(struct drm_device *dev, u8 val)
3360{
3361 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3362
3363 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3364
3365 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3366 WARN_ON(val > dev_priv->rps.max_delay);
3367 WARN_ON(val < dev_priv->rps.min_delay);
3368
80814ae4
VS		 3369 vlv_update_rps_cur_delay(dev_priv);
3370
73008b98 3371 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3372 vlv_gpu_freq(dev_priv->mem_freq,
3373 dev_priv->rps.cur_delay),
73008b98
VS		 3374 dev_priv->rps.cur_delay,
3375 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3376
3377 if (val == dev_priv->rps.cur_delay)
3378 return;
3379
ae99258f 3380 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3381
80814ae4 3382 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3383
3384 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3385}
3386
44fc7d5c 3387static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3388{
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390
2b4e57bd 3391 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3392 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3393 /* Complete PM interrupt masking here doesn't race with the rps work
3394 * item again unmasking PM interrupts because that is using a different
3395 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3396 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3397
59cdb63d 3398 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3399 dev_priv->rps.pm_iir = 0;
59cdb63d 3400 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3401
4848405c 3402 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3403}
3404
44fc7d5c 3405static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3406{
3407 struct drm_i915_private *dev_priv = dev->dev_private;
3408
3409 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3410 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3411
44fc7d5c
DV		 3412 gen6_disable_rps_interrupts(dev);
3413}
3414
3415static void valleyview_disable_rps(struct drm_device *dev)
3416{
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418
3419 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3420
44fc7d5c 3421 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3422
3423 if (dev_priv->vlv_pctx) {
3424 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3425 dev_priv->vlv_pctx = NULL;
3426 }
d20d4f0c
JB		 3427}
3428
2b4e57bd
ED		 3429int intel_enable_rc6(const struct drm_device *dev)
3430{
eb4926e4
DL		 3431 /* No RC6 before Ironlake */
3432 if (INTEL_INFO(dev)->gen < 5)
3433 return 0;
3434
456470eb 3435 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3436 if (i915_enable_rc6 >= 0)
3437 return i915_enable_rc6;
3438
6567d748
CW		 3439 /* Disable RC6 on Ironlake */
3440 if (INTEL_INFO(dev)->gen == 5)
3441 return 0;
2b4e57bd 3442
456470eb
DV		 3443 if (IS_HASWELL(dev)) {
3444 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3445 return INTEL_RC6_ENABLE;
456470eb 3446 }
2b4e57bd 3447
456470eb 3448 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3449 if (INTEL_INFO(dev)->gen == 6) {
3450 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3451 return INTEL_RC6_ENABLE;
3452 }
456470eb 3453
2b4e57bd
ED		 3454 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3455 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3456}
3457
44fc7d5c
DV		 3458static void gen6_enable_rps_interrupts(struct drm_device *dev)
3459{
3460 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3461 u32 enabled_intrs;
44fc7d5c
DV		 3462
3463 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3464 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3465 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3466 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3467 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3468
fd547d25 3469 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3470 enabled_intrs = GEN6_PM_RPS_EVENTS;
3471
3472 /* IVB and SNB hard hangs on looping batchbuffer
3473 * if GEN6_PM_UP_EI_EXPIRED is masked.
3474 */
3475 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3476 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3477
3478 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3479}
3480
79f5b2c7 3481static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3482{
79f5b2c7 3483 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3484 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3485 u32 rp_state_cap;
3486 u32 gt_perf_status;
31643d54 3487 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3488 u32 gtfifodbg;
2b4e57bd 3489 int rc6_mode;
42c0526c 3490 int i, ret;
2b4e57bd 3491
4fc688ce 3492 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3493
2b4e57bd
ED		 3494 /* Here begins a magic sequence of register writes to enable
3495 * auto-downclocking.
3496 *
3497 * Perhaps there might be some value in exposing these to
3498 * userspace...
3499 */
3500 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3501
3502 /* Clear the DBG now so we don't confuse earlier errors */
3503 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3504 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3505 I915_WRITE(GTFIFODBG, gtfifodbg);
3506 }
3507
3508 gen6_gt_force_wake_get(dev_priv);
3509
7b9e0ae6
CW		 3510 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3511 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3512
31c77388
BW		 3513 /* In units of 50MHz */
3514 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3515 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3516 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3517
2b4e57bd
ED		 3518 /* disable the counters and set deterministic thresholds */
3519 I915_WRITE(GEN6_RC_CONTROL, 0);
3520
3521 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3522 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3523 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3524 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3525 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3526
b4519513
CW		 3527 for_each_ring(ring, dev_priv, i)
3528 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3529
3530 I915_WRITE(GEN6_RC_SLEEP, 0);
3531 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3532 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3533 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3534 else
3535 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3536 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3537 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3538
5a7dc92a 3539 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3540 rc6_mode = intel_enable_rc6(dev_priv->dev);
3541 if (rc6_mode & INTEL_RC6_ENABLE)
3542 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3543
5a7dc92a
ED		 3544 /* We don't use those on Haswell */
3545 if (!IS_HASWELL(dev)) {
3546 if (rc6_mode & INTEL_RC6p_ENABLE)
3547 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3548
5a7dc92a
ED		 3549 if (rc6_mode & INTEL_RC6pp_ENABLE)
3550 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3551 }
2b4e57bd
ED		 3552
3553 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3554 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3555 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3556 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3557
3558 I915_WRITE(GEN6_RC_CONTROL,
3559 rc6_mask |
3560 GEN6_RC_CTL_EI_MODE(1) |
3561 GEN6_RC_CTL_HW_ENABLE);
3562
92bd1bf0
RV		 3563 if (IS_HASWELL(dev)) {
3564 I915_WRITE(GEN6_RPNSWREQ,
3565 HSW_FREQUENCY(10));
3566 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3567 HSW_FREQUENCY(12));
3568 } else {
3569 I915_WRITE(GEN6_RPNSWREQ,
3570 GEN6_FREQUENCY(10) |
3571 GEN6_OFFSET(0) |
3572 GEN6_AGGRESSIVE_TURBO);
3573 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3574 GEN6_FREQUENCY(12));
3575 }
2b4e57bd
ED		 3576
3577 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3578 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3579 dev_priv->rps.max_delay << 24 |
3580 dev_priv->rps.min_delay << 16);
5a7dc92a 3581
1ee9ae32
DV		 3582 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3583 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3584 I915_WRITE(GEN6_RP_UP_EI, 66000);
3585 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3586
2b4e57bd
ED		 3587 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3588 I915_WRITE(GEN6_RP_CONTROL,
3589 GEN6_RP_MEDIA_TURBO |
89ba829e 3590 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3591 GEN6_RP_MEDIA_IS_GFX |
3592 GEN6_RP_ENABLE |
3593 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3594 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3595
42c0526c 3596 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3597 if (!ret) {
42c0526c
BW		 3598 pcu_mbox = 0;
3599 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3600 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3601 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3602 (dev_priv->rps.max_delay & 0xff) * 50,
3603 (pcu_mbox & 0xff) * 50);
31c77388 3604 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3605 }
3606 } else {
3607 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3608 }
3609
7b9e0ae6 3610 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3611
44fc7d5c 3612 gen6_enable_rps_interrupts(dev);
2b4e57bd 3613
31643d54
BW		 3614 rc6vids = 0;
3615 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3616 if (IS_GEN6(dev) && ret) {
3617 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3618 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3619 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3620 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3621 rc6vids &= 0xffff00;
3622 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3623 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3624 if (ret)
3625 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3626 }
3627
2b4e57bd 3628 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3629}
3630
c67a470b 3631void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3632{
79f5b2c7 3633 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3634 int min_freq = 15;
3ebecd07
CW		 3635 unsigned int gpu_freq;
3636 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3637 int scaling_factor = 180;
3638
4fc688ce 3639 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3640
2b4e57bd
ED		 3641 max_ia_freq = cpufreq_quick_get_max(0);
3642 /*
3643 * Default to measured freq if none found, PCU will ensure we don't go
3644 * over
3645 */
3646 if (!max_ia_freq)
3647 max_ia_freq = tsc_khz;
3648
3649 /* Convert from kHz to MHz */
3650 max_ia_freq /= 1000;
3651
3ebecd07
CW		 3652 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3653 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3654 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3655
2b4e57bd
ED		 3656 /*
3657 * For each potential GPU frequency, load a ring frequency we'd like
3658 * to use for memory access. We do this by specifying the IA frequency
3659 * the PCU should use as a reference to determine the ring frequency.
3660 */
c6a828d3 3661 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3662 gpu_freq--) {
c6a828d3 3663 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3664 unsigned int ia_freq = 0, ring_freq = 0;
3665
3666 if (IS_HASWELL(dev)) {
3667 ring_freq = (gpu_freq * 5 + 3) / 4;
3668 ring_freq = max(min_ring_freq, ring_freq);
3669 /* leave ia_freq as the default, chosen by cpufreq */
3670 } else {
3671 /* On older processors, there is no separate ring
3672 * clock domain, so in order to boost the bandwidth
3673 * of the ring, we need to upclock the CPU (ia_freq).
3674 *
3675 * For GPU frequencies less than 750MHz,
3676 * just use the lowest ring freq.
3677 */
3678 if (gpu_freq < min_freq)
3679 ia_freq = 800;
3680 else
3681 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3682 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3683 }
2b4e57bd 3684
42c0526c
BW		 3685 sandybridge_pcode_write(dev_priv,
3686 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3687 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3688 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3689 gpu_freq);
2b4e57bd 3690 }
2b4e57bd
ED		 3691}
3692
0a073b84
JB		 3693int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3694{
3695 u32 val, rp0;
3696
64936258 3697 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3698
3699 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3700 /* Clamp to max */
3701 rp0 = min_t(u32, rp0, 0xea);
3702
3703 return rp0;
3704}
3705
3706static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3707{
3708 u32 val, rpe;
3709
64936258 3710 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3711 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3712 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3713 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3714
3715 return rpe;
3716}
3717
3718int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3719{
64936258 3720 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3721}
3722
52ceb908
JB		 3723static void vlv_rps_timer_work(struct work_struct *work)
3724{
3725 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3726 rps.vlv_work.work);
3727
3728 /*
3729 * Timer fired, we must be idle. Drop to min voltage state.
3730 * Note: we use RPe here since it should match the
3731 * Vmin we were shooting for. That should give us better
3732 * perf when we come back out of RC6 than if we used the
3733 * min freq available.
3734 */
3735 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3736 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3737 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3738 mutex_unlock(&dev_priv->rps.hw_lock);
3739}
3740
c9cddffc
JB		 3741static void valleyview_setup_pctx(struct drm_device *dev)
3742{
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct drm_i915_gem_object *pctx;
3745 unsigned long pctx_paddr;
3746 u32 pcbr;
3747 int pctx_size = 24*1024;
3748
3749 pcbr = I915_READ(VLV_PCBR);
3750 if (pcbr) {
3751 /* BIOS set it up already, grab the pre-alloc'd space */
3752 int pcbr_offset;
3753
3754 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3755 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3756 pcbr_offset,
190d6cd5 3757 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3758 pctx_size);
3759 goto out;
3760 }
3761
3762 /*
3763 * From the Gunit register HAS:
3764 * The Gfx driver is expected to program this register and ensure
3765 * proper allocation within Gfx stolen memory. For example, this
3766 * register should be programmed such than the PCBR range does not
3767 * overlap with other ranges, such as the frame buffer, protected
3768 * memory, or any other relevant ranges.
3769 */
3770 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3771 if (!pctx) {
3772 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3773 return;
3774 }
3775
3776 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3777 I915_WRITE(VLV_PCBR, pctx_paddr);
3778
3779out:
3780 dev_priv->vlv_pctx = pctx;
3781}
3782
0a073b84
JB		 3783static void valleyview_enable_rps(struct drm_device *dev)
3784{
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_ring_buffer *ring;
73008b98 3787 u32 gtfifodbg, val;
0a073b84
JB		 3788 int i;
3789
3790 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3791
3792 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3793 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3794 I915_WRITE(GTFIFODBG, gtfifodbg);
3795 }
3796
c9cddffc
JB		 3797 valleyview_setup_pctx(dev);
3798
0a073b84
JB		 3799 gen6_gt_force_wake_get(dev_priv);
3800
3801 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3802 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3803 I915_WRITE(GEN6_RP_UP_EI, 66000);
3804 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3805
3806 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3807
3808 I915_WRITE(GEN6_RP_CONTROL,
3809 GEN6_RP_MEDIA_TURBO |
3810 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3811 GEN6_RP_MEDIA_IS_GFX |
3812 GEN6_RP_ENABLE |
3813 GEN6_RP_UP_BUSY_AVG |
3814 GEN6_RP_DOWN_IDLE_CONT);
3815
3816 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3817 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3818 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3819
3820 for_each_ring(ring, dev_priv, i)
3821 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3822
3823 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3824
3825 /* allows RC6 residency counter to work */
3826 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3827 I915_WRITE(GEN6_RC_CONTROL,
3828 GEN7_RC_CTL_TO_MODE);
3829
64936258 3830 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3831 switch ((val >> 6) & 3) {
3832 case 0:
3833 case 1:
3834 dev_priv->mem_freq = 800;
3835 break;
3836 case 2:
3837 dev_priv->mem_freq = 1066;
3838 break;
3839 case 3:
3840 dev_priv->mem_freq = 1333;
3841 break;
3842 }
0a073b84
JB		 3843 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3844
3845 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3846 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3847
0a073b84 3848 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3849 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3850 vlv_gpu_freq(dev_priv->mem_freq,
3851 dev_priv->rps.cur_delay),
3852 dev_priv->rps.cur_delay);
0a073b84
JB		 3853
3854 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3855 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3856 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3857 vlv_gpu_freq(dev_priv->mem_freq,
3858 dev_priv->rps.max_delay),
3859 dev_priv->rps.max_delay);
0a073b84 3860
73008b98
VS		 3861 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3862 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3863 vlv_gpu_freq(dev_priv->mem_freq,
3864 dev_priv->rps.rpe_delay),
3865 dev_priv->rps.rpe_delay);
0a073b84 3866
73008b98
VS		 3867 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3868 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3869 vlv_gpu_freq(dev_priv->mem_freq,
3870 dev_priv->rps.min_delay),
3871 dev_priv->rps.min_delay);
0a073b84 3872
73008b98
VS		 3873 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3874 vlv_gpu_freq(dev_priv->mem_freq,
3875 dev_priv->rps.rpe_delay),
3876 dev_priv->rps.rpe_delay);
0a073b84 3877
52ceb908
JB		 3878 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3879
73008b98 3880 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3881
44fc7d5c 3882 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3883
3884 gen6_gt_force_wake_put(dev_priv);
3885}
3886
930ebb46 3887void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3888{
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890
3e373948
DV		 3891 if (dev_priv->ips.renderctx) {
3892 i915_gem_object_unpin(dev_priv->ips.renderctx);
3893 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3894 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3895 }
3896
3e373948
DV		 3897 if (dev_priv->ips.pwrctx) {
3898 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3899 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3900 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3901 }
3902}
3903
930ebb46 3904static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3905{
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907
3908 if (I915_READ(PWRCTXA)) {
3909 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3910 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3911 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3912 50);
3913
3914 I915_WRITE(PWRCTXA, 0);
3915 POSTING_READ(PWRCTXA);
3916
3917 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3918 POSTING_READ(RSTDBYCTL);
3919 }
2b4e57bd
ED		 3920}
3921
3922static int ironlake_setup_rc6(struct drm_device *dev)
3923{
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925
3e373948
DV		 3926 if (dev_priv->ips.renderctx == NULL)
3927 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3928 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3929 return -ENOMEM;
3930
3e373948
DV		 3931 if (dev_priv->ips.pwrctx == NULL)
3932 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3933 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3934 ironlake_teardown_rc6(dev);
3935 return -ENOMEM;
3936 }
3937
3938 return 0;
3939}
3940
930ebb46 3941static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3942{
3943 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3944 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3945 bool was_interruptible;
2b4e57bd
ED		 3946 int ret;
3947
3948 /* rc6 disabled by default due to repeated reports of hanging during
3949 * boot and resume.
3950 */
3951 if (!intel_enable_rc6(dev))
3952 return;
3953
79f5b2c7
DV		 3954 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3955
2b4e57bd 3956 ret = ironlake_setup_rc6(dev);
79f5b2c7 3957 if (ret)
2b4e57bd 3958 return;
2b4e57bd 3959
3e960501
CW		 3960 was_interruptible = dev_priv->mm.interruptible;
3961 dev_priv->mm.interruptible = false;
3962
2b4e57bd
ED		 3963 /*
3964 * GPU can automatically power down the render unit if given a page
3965 * to save state.
3966 */
6d90c952 3967 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3968 if (ret) {
3969 ironlake_teardown_rc6(dev);
3e960501 3970 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3971 return;
3972 }
3973
6d90c952
DV		 3974 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3975 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3976 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3977 MI_MM_SPACE_GTT |
3978 MI_SAVE_EXT_STATE_EN |
3979 MI_RESTORE_EXT_STATE_EN |
3980 MI_RESTORE_INHIBIT);
3981 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3982 intel_ring_emit(ring, MI_NOOP);
3983 intel_ring_emit(ring, MI_FLUSH);
3984 intel_ring_advance(ring);
2b4e57bd
ED		 3985
3986 /*
3987 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3988 * does an implicit flush, combined with MI_FLUSH above, it should be
3989 * safe to assume that renderctx is valid
3990 */
3e960501
CW		 3991 ret = intel_ring_idle(ring);
3992 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3993 if (ret) {
def27a58 3994 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3995 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3996 return;
3997 }
3998
f343c5f6 3999 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4000 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 4001}
4002
dde18883
ED		 4003static unsigned long intel_pxfreq(u32 vidfreq)
4004{
4005 unsigned long freq;
4006 int div = (vidfreq & 0x3f0000) >> 16;
4007 int post = (vidfreq & 0x3000) >> 12;
4008 int pre = (vidfreq & 0x7);
4009
4010 if (!pre)
4011 return 0;
4012
4013 freq = ((div * 133333) / ((1<<post) * pre));
4014
4015 return freq;
4016}
4017
eb48eb00
DV		 4018static const struct cparams {
4019 u16 i;
4020 u16 t;
4021 u16 m;
4022 u16 c;
4023} cparams[] = {
4024 { 1, 1333, 301, 28664 },
4025 { 1, 1066, 294, 24460 },
4026 { 1, 800, 294, 25192 },
4027 { 0, 1333, 276, 27605 },
4028 { 0, 1066, 276, 27605 },
4029 { 0, 800, 231, 23784 },
4030};
4031
f531dcb2 4032static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4033{
4034 u64 total_count, diff, ret;
4035 u32 count1, count2, count3, m = 0, c = 0;
4036 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4037 int i;
4038
02d71956
DV		 4039 assert_spin_locked(&mchdev_lock);
4040
20e4d407 4041 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4042
4043 /* Prevent division-by-zero if we are asking too fast.
4044 * Also, we don't get interesting results if we are polling
4045 * faster than once in 10ms, so just return the saved value
4046 * in such cases.
4047 */
4048 if (diff1 <= 10)
20e4d407 4049 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4050
4051 count1 = I915_READ(DMIEC);
4052 count2 = I915_READ(DDREC);
4053 count3 = I915_READ(CSIEC);
4054
4055 total_count = count1 + count2 + count3;
4056
4057 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4058 if (total_count < dev_priv->ips.last_count1) {
4059 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4060 diff += total_count;
4061 } else {
20e4d407 4062 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4063 }
4064
4065 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4066 if (cparams[i].i == dev_priv->ips.c_m &&
4067 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4068 m = cparams[i].m;
4069 c = cparams[i].c;
4070 break;
4071 }
4072 }
4073
4074 diff = div_u64(diff, diff1);
4075 ret = ((m * diff) + c);
4076 ret = div_u64(ret, 10);
4077
20e4d407
DV		 4078 dev_priv->ips.last_count1 = total_count;
4079 dev_priv->ips.last_time1 = now;
eb48eb00 4080
20e4d407 4081 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4082
4083 return ret;
4084}
4085
f531dcb2
CW		 4086unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4087{
4088 unsigned long val;
4089
4090 if (dev_priv->info->gen != 5)
4091 return 0;
4092
4093 spin_lock_irq(&mchdev_lock);
4094
4095 val = __i915_chipset_val(dev_priv);
4096
4097 spin_unlock_irq(&mchdev_lock);
4098
4099 return val;
4100}
4101
eb48eb00
DV		 4102unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4103{
4104 unsigned long m, x, b;
4105 u32 tsfs;
4106
4107 tsfs = I915_READ(TSFS);
4108
4109 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4110 x = I915_READ8(TR1);
4111
4112 b = tsfs & TSFS_INTR_MASK;
4113
4114 return ((m * x) / 127) - b;
4115}
4116
4117static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4118{
4119 static const struct v_table {
4120 u16 vd; /* in .1 mil */
4121 u16 vm; /* in .1 mil */
4122 } v_table[] = {
4123 { 0, 0, },
4124 { 375, 0, },
4125 { 500, 0, },
4126 { 625, 0, },
4127 { 750, 0, },
4128 { 875, 0, },
4129 { 1000, 0, },
4130 { 1125, 0, },
4131 { 4125, 3000, },
4132 { 4125, 3000, },
4133 { 4125, 3000, },
4134 { 4125, 3000, },
4135 { 4125, 3000, },
4136 { 4125, 3000, },
4137 { 4125, 3000, },
4138 { 4125, 3000, },
4139 { 4125, 3000, },
4140 { 4125, 3000, },
4141 { 4125, 3000, },
4142 { 4125, 3000, },
4143 { 4125, 3000, },
4144 { 4125, 3000, },
4145 { 4125, 3000, },
4146 { 4125, 3000, },
4147 { 4125, 3000, },
4148 { 4125, 3000, },
4149 { 4125, 3000, },
4150 { 4125, 3000, },
4151 { 4125, 3000, },
4152 { 4125, 3000, },
4153 { 4125, 3000, },
4154 { 4125, 3000, },
4155 { 4250, 3125, },
4156 { 4375, 3250, },
4157 { 4500, 3375, },
4158 { 4625, 3500, },
4159 { 4750, 3625, },
4160 { 4875, 3750, },
4161 { 5000, 3875, },
4162 { 5125, 4000, },
4163 { 5250, 4125, },
4164 { 5375, 4250, },
4165 { 5500, 4375, },
4166 { 5625, 4500, },
4167 { 5750, 4625, },
4168 { 5875, 4750, },
4169 { 6000, 4875, },
4170 { 6125, 5000, },
4171 { 6250, 5125, },
4172 { 6375, 5250, },
4173 { 6500, 5375, },
4174 { 6625, 5500, },
4175 { 6750, 5625, },
4176 { 6875, 5750, },
4177 { 7000, 5875, },
4178 { 7125, 6000, },
4179 { 7250, 6125, },
4180 { 7375, 6250, },
4181 { 7500, 6375, },
4182 { 7625, 6500, },
4183 { 7750, 6625, },
4184 { 7875, 6750, },
4185 { 8000, 6875, },
4186 { 8125, 7000, },
4187 { 8250, 7125, },
4188 { 8375, 7250, },
4189 { 8500, 7375, },
4190 { 8625, 7500, },
4191 { 8750, 7625, },
4192 { 8875, 7750, },
4193 { 9000, 7875, },
4194 { 9125, 8000, },
4195 { 9250, 8125, },
4196 { 9375, 8250, },
4197 { 9500, 8375, },
4198 { 9625, 8500, },
4199 { 9750, 8625, },
4200 { 9875, 8750, },
4201 { 10000, 8875, },
4202 { 10125, 9000, },
4203 { 10250, 9125, },
4204 { 10375, 9250, },
4205 { 10500, 9375, },
4206 { 10625, 9500, },
4207 { 10750, 9625, },
4208 { 10875, 9750, },
4209 { 11000, 9875, },
4210 { 11125, 10000, },
4211 { 11250, 10125, },
4212 { 11375, 10250, },
4213 { 11500, 10375, },
4214 { 11625, 10500, },
4215 { 11750, 10625, },
4216 { 11875, 10750, },
4217 { 12000, 10875, },
4218 { 12125, 11000, },
4219 { 12250, 11125, },
4220 { 12375, 11250, },
4221 { 12500, 11375, },
4222 { 12625, 11500, },
4223 { 12750, 11625, },
4224 { 12875, 11750, },
4225 { 13000, 11875, },
4226 { 13125, 12000, },
4227 { 13250, 12125, },
4228 { 13375, 12250, },
4229 { 13500, 12375, },
4230 { 13625, 12500, },
4231 { 13750, 12625, },
4232 { 13875, 12750, },
4233 { 14000, 12875, },
4234 { 14125, 13000, },
4235 { 14250, 13125, },
4236 { 14375, 13250, },
4237 { 14500, 13375, },
4238 { 14625, 13500, },
4239 { 14750, 13625, },
4240 { 14875, 13750, },
4241 { 15000, 13875, },
4242 { 15125, 14000, },
4243 { 15250, 14125, },
4244 { 15375, 14250, },
4245 { 15500, 14375, },
4246 { 15625, 14500, },
4247 { 15750, 14625, },
4248 { 15875, 14750, },
4249 { 16000, 14875, },
4250 { 16125, 15000, },
4251 };
4252 if (dev_priv->info->is_mobile)
4253 return v_table[pxvid].vm;
4254 else
4255 return v_table[pxvid].vd;
4256}
4257
02d71956 4258static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4259{
4260 struct timespec now, diff1;
4261 u64 diff;
4262 unsigned long diffms;
4263 u32 count;
4264
02d71956 4265 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4266
4267 getrawmonotonic(&now);
20e4d407 4268 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4269
4270 /* Don't divide by 0 */
4271 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4272 if (!diffms)
4273 return;
4274
4275 count = I915_READ(GFXEC);
4276
20e4d407
DV		 4277 if (count < dev_priv->ips.last_count2) {
4278 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4279 diff += count;
4280 } else {
20e4d407 4281 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4282 }
4283
20e4d407
DV		 4284 dev_priv->ips.last_count2 = count;
4285 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4286
4287 /* More magic constants... */
4288 diff = diff * 1181;
4289 diff = div_u64(diff, diffms * 10);
20e4d407 4290 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4291}
4292
02d71956
DV		 4293void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4294{
4295 if (dev_priv->info->gen != 5)
4296 return;
4297
9270388e 4298 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4299
4300 __i915_update_gfx_val(dev_priv);
4301
9270388e 4302 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4303}
4304
f531dcb2 4305static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4306{
4307 unsigned long t, corr, state1, corr2, state2;
4308 u32 pxvid, ext_v;
4309
02d71956
DV		 4310 assert_spin_locked(&mchdev_lock);
4311
c6a828d3 4312 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4313 pxvid = (pxvid >> 24) & 0x7f;
4314 ext_v = pvid_to_extvid(dev_priv, pxvid);
4315
4316 state1 = ext_v;
4317
4318 t = i915_mch_val(dev_priv);
4319
4320 /* Revel in the empirically derived constants */
4321
4322 /* Correction factor in 1/100000 units */
4323 if (t > 80)
4324 corr = ((t * 2349) + 135940);
4325 else if (t >= 50)
4326 corr = ((t * 964) + 29317);
4327 else /* < 50 */
4328 corr = ((t * 301) + 1004);
4329
4330 corr = corr * ((150142 * state1) / 10000 - 78642);
4331 corr /= 100000;
20e4d407 4332 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4333
4334 state2 = (corr2 * state1) / 10000;
4335 state2 /= 100; /* convert to mW */
4336
02d71956 4337 __i915_update_gfx_val(dev_priv);
eb48eb00 4338
20e4d407 4339 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4340}
4341
f531dcb2
CW		 4342unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4343{
4344 unsigned long val;
4345
4346 if (dev_priv->info->gen != 5)
4347 return 0;
4348
4349 spin_lock_irq(&mchdev_lock);
4350
4351 val = __i915_gfx_val(dev_priv);
4352
4353 spin_unlock_irq(&mchdev_lock);
4354
4355 return val;
4356}
4357
eb48eb00
DV		 4358/**
4359 * i915_read_mch_val - return value for IPS use
4360 *
4361 * Calculate and return a value for the IPS driver to use when deciding whether
4362 * we have thermal and power headroom to increase CPU or GPU power budget.
4363 */
4364unsigned long i915_read_mch_val(void)
4365{
4366 struct drm_i915_private *dev_priv;
4367 unsigned long chipset_val, graphics_val, ret = 0;
4368
9270388e 4369 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4370 if (!i915_mch_dev)
4371 goto out_unlock;
4372 dev_priv = i915_mch_dev;
4373
f531dcb2
CW		 4374 chipset_val = __i915_chipset_val(dev_priv);
4375 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4376
4377 ret = chipset_val + graphics_val;
4378
4379out_unlock:
9270388e 4380 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4381
4382 return ret;
4383}
4384EXPORT_SYMBOL_GPL(i915_read_mch_val);
4385
4386/**
4387 * i915_gpu_raise - raise GPU frequency limit
4388 *
4389 * Raise the limit; IPS indicates we have thermal headroom.
4390 */
4391bool i915_gpu_raise(void)
4392{
4393 struct drm_i915_private *dev_priv;
4394 bool ret = true;
4395
9270388e 4396 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4397 if (!i915_mch_dev) {
4398 ret = false;
4399 goto out_unlock;
4400 }
4401 dev_priv = i915_mch_dev;
4402
20e4d407
DV		 4403 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4404 dev_priv->ips.max_delay--;
eb48eb00
DV		 4405
4406out_unlock:
9270388e 4407 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4408
4409 return ret;
4410}
4411EXPORT_SYMBOL_GPL(i915_gpu_raise);
4412
4413/**
4414 * i915_gpu_lower - lower GPU frequency limit
4415 *
4416 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4417 * frequency maximum.
4418 */
4419bool i915_gpu_lower(void)
4420{
4421 struct drm_i915_private *dev_priv;
4422 bool ret = true;
4423
9270388e 4424 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4425 if (!i915_mch_dev) {
4426 ret = false;
4427 goto out_unlock;
4428 }
4429 dev_priv = i915_mch_dev;
4430
20e4d407
DV		 4431 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4432 dev_priv->ips.max_delay++;
eb48eb00
DV		 4433
4434out_unlock:
9270388e 4435 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4436
4437 return ret;
4438}
4439EXPORT_SYMBOL_GPL(i915_gpu_lower);
4440
4441/**
4442 * i915_gpu_busy - indicate GPU business to IPS
4443 *
4444 * Tell the IPS driver whether or not the GPU is busy.
4445 */
4446bool i915_gpu_busy(void)
4447{
4448 struct drm_i915_private *dev_priv;
f047e395 4449 struct intel_ring_buffer *ring;
eb48eb00 4450 bool ret = false;
f047e395 4451 int i;
eb48eb00 4452
9270388e 4453 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4454 if (!i915_mch_dev)
4455 goto out_unlock;
4456 dev_priv = i915_mch_dev;
4457
f047e395
CW		 4458 for_each_ring(ring, dev_priv, i)
4459 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4460
4461out_unlock:
9270388e 4462 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4463
4464 return ret;
4465}
4466EXPORT_SYMBOL_GPL(i915_gpu_busy);
4467
4468/**
4469 * i915_gpu_turbo_disable - disable graphics turbo
4470 *
4471 * Disable graphics turbo by resetting the max frequency and setting the
4472 * current frequency to the default.
4473 */
4474bool i915_gpu_turbo_disable(void)
4475{
4476 struct drm_i915_private *dev_priv;
4477 bool ret = true;
4478
9270388e 4479 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4480 if (!i915_mch_dev) {
4481 ret = false;
4482 goto out_unlock;
4483 }
4484 dev_priv = i915_mch_dev;
4485
20e4d407 4486 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4487
20e4d407 4488 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4489 ret = false;
4490
4491out_unlock:
9270388e 4492 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4493
4494 return ret;
4495}
4496EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4497
4498/**
4499 * Tells the intel_ips driver that the i915 driver is now loaded, if
4500 * IPS got loaded first.
4501 *
4502 * This awkward dance is so that neither module has to depend on the
4503 * other in order for IPS to do the appropriate communication of
4504 * GPU turbo limits to i915.
4505 */
4506static void
4507ips_ping_for_i915_load(void)
4508{
4509 void (*link)(void);
4510
4511 link = symbol_get(ips_link_to_i915_driver);
4512 if (link) {
4513 link();
4514 symbol_put(ips_link_to_i915_driver);
4515 }
4516}
4517
4518void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4519{
02d71956
DV		 4520 /* We only register the i915 ips part with intel-ips once everything is
4521 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4522 spin_lock_irq(&mchdev_lock);
eb48eb00 4523 i915_mch_dev = dev_priv;
9270388e 4524 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4525
4526 ips_ping_for_i915_load();
4527}
4528
4529void intel_gpu_ips_teardown(void)
4530{
9270388e 4531 spin_lock_irq(&mchdev_lock);
eb48eb00 4532 i915_mch_dev = NULL;
9270388e 4533 spin_unlock_irq(&mchdev_lock);
eb48eb00 4534}
8090c6b9 4535static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4536{
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538 u32 lcfuse;
4539 u8 pxw[16];
4540 int i;
4541
4542 /* Disable to program */
4543 I915_WRITE(ECR, 0);
4544 POSTING_READ(ECR);
4545
4546 /* Program energy weights for various events */
4547 I915_WRITE(SDEW, 0x15040d00);
4548 I915_WRITE(CSIEW0, 0x007f0000);
4549 I915_WRITE(CSIEW1, 0x1e220004);
4550 I915_WRITE(CSIEW2, 0x04000004);
4551
4552 for (i = 0; i < 5; i++)
4553 I915_WRITE(PEW + (i * 4), 0);
4554 for (i = 0; i < 3; i++)
4555 I915_WRITE(DEW + (i * 4), 0);
4556
4557 /* Program P-state weights to account for frequency power adjustment */
4558 for (i = 0; i < 16; i++) {
4559 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4560 unsigned long freq = intel_pxfreq(pxvidfreq);
4561 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4562 PXVFREQ_PX_SHIFT;
4563 unsigned long val;
4564
4565 val = vid * vid;
4566 val *= (freq / 1000);
4567 val *= 255;
4568 val /= (127*127*900);
4569 if (val > 0xff)
4570 DRM_ERROR("bad pxval: %ld\n", val);
4571 pxw[i] = val;
4572 }
4573 /* Render standby states get 0 weight */
4574 pxw[14] = 0;
4575 pxw[15] = 0;
4576
4577 for (i = 0; i < 4; i++) {
4578 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4579 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4580 I915_WRITE(PXW + (i * 4), val);
4581 }
4582
4583 /* Adjust magic regs to magic values (more experimental results) */
4584 I915_WRITE(OGW0, 0);
4585 I915_WRITE(OGW1, 0);
4586 I915_WRITE(EG0, 0x00007f00);
4587 I915_WRITE(EG1, 0x0000000e);
4588 I915_WRITE(EG2, 0x000e0000);
4589 I915_WRITE(EG3, 0x68000300);
4590 I915_WRITE(EG4, 0x42000000);
4591 I915_WRITE(EG5, 0x00140031);
4592 I915_WRITE(EG6, 0);
4593 I915_WRITE(EG7, 0);
4594
4595 for (i = 0; i < 8; i++)
4596 I915_WRITE(PXWL + (i * 4), 0);
4597
4598 /* Enable PMON + select events */
4599 I915_WRITE(ECR, 0x80000019);
4600
4601 lcfuse = I915_READ(LCFUSE02);
4602
20e4d407 4603 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4604}
4605
8090c6b9
DV		 4606void intel_disable_gt_powersave(struct drm_device *dev)
4607{
1a01ab3b
JB		 4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609
fd0c0642
DV		 4610 /* Interrupts should be disabled already to avoid re-arming. */
4611 WARN_ON(dev->irq_enabled);
4612
930ebb46 4613 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4614 ironlake_disable_drps(dev);
930ebb46 4615 ironlake_disable_rc6(dev);
0a073b84 4616 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4617 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4618 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4619 if (IS_VALLEYVIEW(dev))
4620 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4621 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4622 if (IS_VALLEYVIEW(dev))
4623 valleyview_disable_rps(dev);
4624 else
4625 gen6_disable_rps(dev);
4fc688ce 4626 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4627 }
8090c6b9
DV		 4628}
4629
1a01ab3b
JB		 4630static void intel_gen6_powersave_work(struct work_struct *work)
4631{
4632 struct drm_i915_private *dev_priv =
4633 container_of(work, struct drm_i915_private,
4634 rps.delayed_resume_work.work);
4635 struct drm_device *dev = dev_priv->dev;
4636
4fc688ce 4637 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4638
4639 if (IS_VALLEYVIEW(dev)) {
4640 valleyview_enable_rps(dev);
4641 } else {
4642 gen6_enable_rps(dev);
4643 gen6_update_ring_freq(dev);
4644 }
4fc688ce 4645 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4646}
4647
8090c6b9
DV		 4648void intel_enable_gt_powersave(struct drm_device *dev)
4649{
1a01ab3b
JB		 4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
8090c6b9
DV		 4652 if (IS_IRONLAKE_M(dev)) {
4653 ironlake_enable_drps(dev);
4654 ironlake_enable_rc6(dev);
4655 intel_init_emon(dev);
0a073b84 4656 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4657 /*
4658 * PCU communication is slow and this doesn't need to be
4659 * done at any specific time, so do this out of our fast path
4660 * to make resume and init faster.
4661 */
4662 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4663 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4664 }
4665}
4666
3107bd48
DV		 4667static void ibx_init_clock_gating(struct drm_device *dev)
4668{
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 /*
4672 * On Ibex Peak and Cougar Point, we need to disable clock
4673 * gating for the panel power sequencer or it will fail to
4674 * start up when no ports are active.
4675 */
4676 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4677}
4678
0e088b8f
VS		 4679static void g4x_disable_trickle_feed(struct drm_device *dev)
4680{
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682 int pipe;
4683
4684 for_each_pipe(pipe) {
4685 I915_WRITE(DSPCNTR(pipe),
4686 I915_READ(DSPCNTR(pipe)) |
4687 DISPPLANE_TRICKLE_FEED_DISABLE);
4688 intel_flush_display_plane(dev_priv, pipe);
4689 }
4690}
4691
1fa61106 4692static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4693{
4694 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4695 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4696
f1e8fa56
DL		 4697 /*
4698 * Required for FBC
4699 * WaFbcDisableDpfcClockGating:ilk
4700 */
4d47e4f5
DL		 4701 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4702 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4703 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4704
4705 I915_WRITE(PCH_3DCGDIS0,
4706 MARIUNIT_CLOCK_GATE_DISABLE |
4707 SVSMUNIT_CLOCK_GATE_DISABLE);
4708 I915_WRITE(PCH_3DCGDIS1,
4709 VFMUNIT_CLOCK_GATE_DISABLE);
4710
6f1d69b0
ED		 4711 /*
4712 * According to the spec the following bits should be set in
4713 * order to enable memory self-refresh
4714 * The bit 22/21 of 0x42004
4715 * The bit 5 of 0x42020
4716 * The bit 15 of 0x45000
4717 */
4718 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4719 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4720 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4721 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4722 I915_WRITE(DISP_ARB_CTL,
4723 (I915_READ(DISP_ARB_CTL) |
4724 DISP_FBC_WM_DIS));
4725 I915_WRITE(WM3_LP_ILK, 0);
4726 I915_WRITE(WM2_LP_ILK, 0);
4727 I915_WRITE(WM1_LP_ILK, 0);
4728
4729 /*
4730 * Based on the document from hardware guys the following bits
4731 * should be set unconditionally in order to enable FBC.
4732 * The bit 22 of 0x42000
4733 * The bit 22 of 0x42004
4734 * The bit 7,8,9 of 0x42020.
4735 */
4736 if (IS_IRONLAKE_M(dev)) {
4bb35334 4737 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4738 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4739 I915_READ(ILK_DISPLAY_CHICKEN1) |
4740 ILK_FBCQ_DIS);
4741 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4742 I915_READ(ILK_DISPLAY_CHICKEN2) |
4743 ILK_DPARB_GATE);
6f1d69b0
ED		 4744 }
4745
4d47e4f5
DL		 4746 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4747
6f1d69b0
ED		 4748 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4749 I915_READ(ILK_DISPLAY_CHICKEN2) |
4750 ILK_ELPIN_409_SELECT);
4751 I915_WRITE(_3D_CHICKEN2,
4752 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4753 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4754
ecdb4eb7 4755 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4756 I915_WRITE(CACHE_MODE_0,
4757 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4758
0e088b8f 4759 g4x_disable_trickle_feed(dev);
bdad2b2f 4760
3107bd48
DV		 4761 ibx_init_clock_gating(dev);
4762}
4763
4764static void cpt_init_clock_gating(struct drm_device *dev)
4765{
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 int pipe;
3f704fa2 4768 uint32_t val;
3107bd48
DV		 4769
4770 /*
4771 * On Ibex Peak and Cougar Point, we need to disable clock
4772 * gating for the panel power sequencer or it will fail to
4773 * start up when no ports are active.
4774 */
4775 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4776 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4777 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4778 /* The below fixes the weird display corruption, a few pixels shifted
4779 * downward, on (only) LVDS of some HP laptops with IVY.
4780 */
3f704fa2 4781 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4782 val = I915_READ(TRANS_CHICKEN2(pipe));
4783 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4784 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4785 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4786 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4787 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4788 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4789 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4790 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4791 }
3107bd48
DV		 4792 /* WADP0ClockGatingDisable */
4793 for_each_pipe(pipe) {
4794 I915_WRITE(TRANS_CHICKEN1(pipe),
4795 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4796 }
6f1d69b0
ED		 4797}
4798
1d7aaa0c
DV		 4799static void gen6_check_mch_setup(struct drm_device *dev)
4800{
4801 struct drm_i915_private *dev_priv = dev->dev_private;
4802 uint32_t tmp;
4803
4804 tmp = I915_READ(MCH_SSKPD);
4805 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4806 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4807 DRM_INFO("This can cause pipe underruns and display issues.\n");
4808 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4809 }
4810}
4811
1fa61106 4812static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4813{
4814 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4815 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4816
231e54f6 4817 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4818
4819 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4820 I915_READ(ILK_DISPLAY_CHICKEN2) |
4821 ILK_ELPIN_409_SELECT);
4822
ecdb4eb7 4823 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4824 I915_WRITE(_3D_CHICKEN,
4825 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4826
ecdb4eb7 4827 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4828 if (IS_SNB_GT1(dev))
4829 I915_WRITE(GEN6_GT_MODE,
4830 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4831
6f1d69b0
ED		 4832 I915_WRITE(WM3_LP_ILK, 0);
4833 I915_WRITE(WM2_LP_ILK, 0);
4834 I915_WRITE(WM1_LP_ILK, 0);
4835
6f1d69b0 4836 I915_WRITE(CACHE_MODE_0,
50743298 4837 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4838
4839 I915_WRITE(GEN6_UCGCTL1,
4840 I915_READ(GEN6_UCGCTL1) |
4841 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4842 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4843
4844 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4845 * gating disable must be set. Failure to set it results in
4846 * flickering pixels due to Z write ordering failures after
4847 * some amount of runtime in the Mesa "fire" demo, and Unigine
4848 * Sanctuary and Tropics, and apparently anything else with
4849 * alpha test or pixel discard.
4850 *
4851 * According to the spec, bit 11 (RCCUNIT) must also be set,
4852 * but we didn't debug actual testcases to find it out.
0f846f81 4853 *
ecdb4eb7
DL		 4854 * Also apply WaDisableVDSUnitClockGating:snb and
4855 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4856 */
4857 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4858 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4859 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4860 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4861
4862 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4863 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4864 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4865
4866 /*
4867 * According to the spec the following bits should be
4868 * set in order to enable memory self-refresh and fbc:
4869 * The bit21 and bit22 of 0x42000
4870 * The bit21 and bit22 of 0x42004
4871 * The bit5 and bit7 of 0x42020
4872 * The bit14 of 0x70180
4873 * The bit14 of 0x71180
4bb35334
DL		 4874 *
4875 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4876 */
4877 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4878 I915_READ(ILK_DISPLAY_CHICKEN1) |
4879 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4880 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4881 I915_READ(ILK_DISPLAY_CHICKEN2) |
4882 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4883 I915_WRITE(ILK_DSPCLK_GATE_D,
4884 I915_READ(ILK_DSPCLK_GATE_D) |
4885 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4886 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4887
0e088b8f 4888 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4889
4890 /* The default value should be 0x200 according to docs, but the two
4891 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4892 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4893 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4894
4895 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4896
4897 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4898}
4899
4900static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4901{
4902 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4903
4904 reg &= ~GEN7_FF_SCHED_MASK;
4905 reg |= GEN7_FF_TS_SCHED_HW;
4906 reg |= GEN7_FF_VS_SCHED_HW;
4907 reg |= GEN7_FF_DS_SCHED_HW;
4908
41c0b3a8
BW		 4909 if (IS_HASWELL(dev_priv->dev))
4910 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4911
6f1d69b0
ED		 4912 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4913}
4914
17a303ec
PZ		 4915static void lpt_init_clock_gating(struct drm_device *dev)
4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918
4919 /*
4920 * TODO: this bit should only be enabled when really needed, then
4921 * disabled when not needed anymore in order to save power.
4922 */
4923 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4924 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4925 I915_READ(SOUTH_DSPCLK_GATE_D) |
4926 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4927
4928 /* WADPOClockGatingDisable:hsw */
4929 I915_WRITE(_TRANSA_CHICKEN1,
4930 I915_READ(_TRANSA_CHICKEN1) |
4931 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4932}
4933
7d708ee4
ID		 4934static void lpt_suspend_hw(struct drm_device *dev)
4935{
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937
4938 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4939 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4940
4941 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4942 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4943 }
4944}
4945
cad2a2d7
ED		 4946static void haswell_init_clock_gating(struct drm_device *dev)
4947{
4948 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4949
4950 I915_WRITE(WM3_LP_ILK, 0);
4951 I915_WRITE(WM2_LP_ILK, 0);
4952 I915_WRITE(WM1_LP_ILK, 0);
4953
4954 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4955 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4956 */
4957 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4958
ecdb4eb7 4959 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4960 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4961 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4962
ecdb4eb7 4963 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4964 I915_WRITE(GEN7_L3CNTLREG1,
4965 GEN7_WA_FOR_GEN7_L3_CONTROL);
4966 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4967 GEN7_WA_L3_CHICKEN_MODE);
4968
ecdb4eb7 4969 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4970 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4971 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4972 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4973
ecdb4eb7 4974 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4975 gen7_setup_fixed_func_scheduler(dev_priv);
4976
ecdb4eb7 4977 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4978 I915_WRITE(CACHE_MODE_1,
4979 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4980
ecdb4eb7 4981 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4982 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4983
90a88643
PZ		 4984 /* WaRsPkgCStateDisplayPMReq:hsw */
4985 I915_WRITE(CHICKEN_PAR1_1,
4986 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4987
17a303ec 4988 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4989}
4990
1fa61106 4991static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4992{
4993 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4994 uint32_t snpcr;
6f1d69b0 4995
6f1d69b0
ED		 4996 I915_WRITE(WM3_LP_ILK, 0);
4997 I915_WRITE(WM2_LP_ILK, 0);
4998 I915_WRITE(WM1_LP_ILK, 0);
4999
231e54f6 5000 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5001
ecdb4eb7 5002 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5003 I915_WRITE(_3D_CHICKEN3,
5004 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5005
ecdb4eb7 5006 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5007 I915_WRITE(IVB_CHICKEN3,
5008 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5009 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5010
ecdb4eb7 5011 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5012 if (IS_IVB_GT1(dev))
5013 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5014 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5015 else
5016 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5017 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5018
ecdb4eb7 5019 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5020 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5021 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5022
ecdb4eb7 5023 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5024 I915_WRITE(GEN7_L3CNTLREG1,
5025 GEN7_WA_FOR_GEN7_L3_CONTROL);
5026 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5027 GEN7_WA_L3_CHICKEN_MODE);
5028 if (IS_IVB_GT1(dev))
5029 I915_WRITE(GEN7_ROW_CHICKEN2,
5030 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5031 else
5032 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5033 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5034
6f1d69b0 5035
ecdb4eb7 5036 /* WaForceL3Serialization:ivb */
61939d97
JB		 5037 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5038 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5039
0f846f81
JB		 5040 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5041 * gating disable must be set. Failure to set it results in
5042 * flickering pixels due to Z write ordering failures after
5043 * some amount of runtime in the Mesa "fire" demo, and Unigine
5044 * Sanctuary and Tropics, and apparently anything else with
5045 * alpha test or pixel discard.
5046 *
5047 * According to the spec, bit 11 (RCCUNIT) must also be set,
5048 * but we didn't debug actual testcases to find it out.
5049 *
5050 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5051 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5052 */
5053 I915_WRITE(GEN6_UCGCTL2,
5054 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5055 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5056
ecdb4eb7 5057 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5058 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5059 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5060 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5061
0e088b8f 5062 g4x_disable_trickle_feed(dev);
6f1d69b0 5063
ecdb4eb7 5064 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5065 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5066
ecdb4eb7 5067 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5068 I915_WRITE(CACHE_MODE_1,
5069 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5070
5071 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5072 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5073 snpcr |= GEN6_MBC_SNPCR_MED;
5074 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5075
ab5c608b
BW		 5076 if (!HAS_PCH_NOP(dev))
5077 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5078
5079 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5080}
5081
1fa61106 5082static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5083{
5084 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5085
d7fe0cc0 5086 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5087
ecdb4eb7 5088 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5089 I915_WRITE(_3D_CHICKEN3,
5090 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5091
ecdb4eb7 5092 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5093 I915_WRITE(IVB_CHICKEN3,
5094 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5095 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5096
ecdb4eb7 5097 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5098 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5099 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5100 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5101
ecdb4eb7 5102 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5103 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5104 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5105
ecdb4eb7 5106 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5107 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5108 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5109
ecdb4eb7 5110 /* WaForceL3Serialization:vlv */
61939d97
JB		 5111 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5112 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5113
ecdb4eb7 5114 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5115 I915_WRITE(GEN7_ROW_CHICKEN2,
5116 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5117
ecdb4eb7 5118 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5119 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5120 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5121 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5122
0f846f81
JB		 5123 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5124 * gating disable must be set. Failure to set it results in
5125 * flickering pixels due to Z write ordering failures after
5126 * some amount of runtime in the Mesa "fire" demo, and Unigine
5127 * Sanctuary and Tropics, and apparently anything else with
5128 * alpha test or pixel discard.
5129 *
5130 * According to the spec, bit 11 (RCCUNIT) must also be set,
5131 * but we didn't debug actual testcases to find it out.
5132 *
5133 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5134 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5135 *
ecdb4eb7
DL		 5136 * Also apply WaDisableVDSUnitClockGating:vlv and
5137 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5138 */
5139 I915_WRITE(GEN6_UCGCTL2,
5140 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5141 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5142 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5143 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5144 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5145
e3f33d46
JB		 5146 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5147
e0d8d59b 5148 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5149
6b26c86d
DV		 5150 I915_WRITE(CACHE_MODE_1,
5151 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5152
2d809570 5153 /*
ecdb4eb7 5154 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5155 * Disable clock gating on th GCFG unit to prevent a delay
5156 * in the reporting of vblank events.
5157 */
4e8c84a5
JB		 5158 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5159
5160 /* Conservative clock gating settings for now */
5161 I915_WRITE(0x9400, 0xffffffff);
5162 I915_WRITE(0x9404, 0xffffffff);
5163 I915_WRITE(0x9408, 0xffffffff);
5164 I915_WRITE(0x940c, 0xffffffff);
5165 I915_WRITE(0x9410, 0xffffffff);
5166 I915_WRITE(0x9414, 0xffffffff);
5167 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5168}
5169
1fa61106 5170static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5171{
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 uint32_t dspclk_gate;
5174
5175 I915_WRITE(RENCLK_GATE_D1, 0);
5176 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5177 GS_UNIT_CLOCK_GATE_DISABLE |
5178 CL_UNIT_CLOCK_GATE_DISABLE);
5179 I915_WRITE(RAMCLK_GATE_D, 0);
5180 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5181 OVRUNIT_CLOCK_GATE_DISABLE |
5182 OVCUNIT_CLOCK_GATE_DISABLE;
5183 if (IS_GM45(dev))
5184 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5185 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5186
5187 /* WaDisableRenderCachePipelinedFlush */
5188 I915_WRITE(CACHE_MODE_0,
5189 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5190
0e088b8f 5191 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5192}
5193
1fa61106 5194static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5195{
5196 struct drm_i915_private *dev_priv = dev->dev_private;
5197
5198 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5199 I915_WRITE(RENCLK_GATE_D2, 0);
5200 I915_WRITE(DSPCLK_GATE_D, 0);
5201 I915_WRITE(RAMCLK_GATE_D, 0);
5202 I915_WRITE16(DEUC, 0);
20f94967
VS		 5203 I915_WRITE(MI_ARB_STATE,
5204 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5205}
5206
1fa61106 5207static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5208{
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210
5211 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5212 I965_RCC_CLOCK_GATE_DISABLE |
5213 I965_RCPB_CLOCK_GATE_DISABLE |
5214 I965_ISC_CLOCK_GATE_DISABLE |
5215 I965_FBC_CLOCK_GATE_DISABLE);
5216 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5217 I915_WRITE(MI_ARB_STATE,
5218 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5219}
5220
1fa61106 5221static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5222{
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 u32 dstate = I915_READ(D_STATE);
5225
5226 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5227 DSTATE_DOT_CLOCK_GATING;
5228 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5229
5230 if (IS_PINEVIEW(dev))
5231 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5232
5233 /* IIR "flip pending" means done if this bit is set */
5234 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5235}
5236
1fa61106 5237static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5238{
5239 struct drm_i915_private *dev_priv = dev->dev_private;
5240
5241 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5242}
5243
1fa61106 5244static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5245{
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5249}
5250
6f1d69b0
ED		 5251void intel_init_clock_gating(struct drm_device *dev)
5252{
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254
5255 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5256}
5257
7d708ee4
ID		 5258void intel_suspend_hw(struct drm_device *dev)
5259{
5260 if (HAS_PCH_LPT(dev))
5261 lpt_suspend_hw(dev);
5262}
5263
15d199ea
PZ		 5264/**
5265 * We should only use the power well if we explicitly asked the hardware to
5266 * enable it, so check if it's enabled and also check if we've requested it to
5267 * be enabled.
5268 */
b97186f0
PZ		 5269bool intel_display_power_enabled(struct drm_device *dev,
5270 enum intel_display_power_domain domain)
15d199ea
PZ		 5271{
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273
b97186f0
PZ		 5274 if (!HAS_POWER_WELL(dev))
5275 return true;
5276
5277 switch (domain) {
5278 case POWER_DOMAIN_PIPE_A:
5279 case POWER_DOMAIN_TRANSCODER_EDP:
5280 return true;
5281 case POWER_DOMAIN_PIPE_B:
5282 case POWER_DOMAIN_PIPE_C:
5283 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5284 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5285 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5286 case POWER_DOMAIN_TRANSCODER_A:
5287 case POWER_DOMAIN_TRANSCODER_B:
5288 case POWER_DOMAIN_TRANSCODER_C:
15d199ea 5289 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5290 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
b97186f0
PZ		 5291 default:
5292 BUG();
5293 }
15d199ea
PZ		 5294}
5295
a38911a3 5296static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5297{
5298 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5299 bool is_enabled, enable_requested;
5300 uint32_t tmp;
d0d3e513 5301
fa42e23c 5302 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5303 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5304 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5305
fa42e23c
PZ		 5306 if (enable) {
5307 if (!enable_requested)
6aedd1f5
PZ		 5308 I915_WRITE(HSW_PWR_WELL_DRIVER,
5309 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5310
fa42e23c
PZ		 5311 if (!is_enabled) {
5312 DRM_DEBUG_KMS("Enabling power well\n");
5313 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5314 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5315 DRM_ERROR("Timeout enabling power well\n");
5316 }
5317 } else {
5318 if (enable_requested) {
9dbd8feb
PZ		 5319 unsigned long irqflags;
5320 enum pipe p;
5321
fa42e23c 5322 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5323 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5324 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5325
5326 /*
5327 * After this, the registers on the pipes that are part
5328 * of the power well will become zero, so we have to
5329 * adjust our counters according to that.
5330 *
5331 * FIXME: Should we do this in general in
5332 * drm_vblank_post_modeset?
5333 */
5334 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5335 for_each_pipe(p)
5336 if (p != PIPE_A)
5337 dev->last_vblank[p] = 0;
5338 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5339 }
5340 }
fa42e23c 5341}
d0d3e513 5342
a38911a3
WX		 5343static struct i915_power_well *hsw_pwr;
5344
5345/* Display audio driver power well request */
5346void i915_request_power_well(void)
5347{
5348 if (WARN_ON(!hsw_pwr))
5349 return;
5350
5351 spin_lock_irq(&hsw_pwr->lock);
5352 if (!hsw_pwr->count++ &&
5353 !hsw_pwr->i915_request)
5354 __intel_set_power_well(hsw_pwr->device, true);
5355 spin_unlock_irq(&hsw_pwr->lock);
5356}
5357EXPORT_SYMBOL_GPL(i915_request_power_well);
5358
5359/* Display audio driver power well release */
5360void i915_release_power_well(void)
5361{
5362 if (WARN_ON(!hsw_pwr))
5363 return;
5364
5365 spin_lock_irq(&hsw_pwr->lock);
5366 WARN_ON(!hsw_pwr->count);
5367 if (!--hsw_pwr->count &&
5368 !hsw_pwr->i915_request)
5369 __intel_set_power_well(hsw_pwr->device, false);
5370 spin_unlock_irq(&hsw_pwr->lock);
5371}
5372EXPORT_SYMBOL_GPL(i915_release_power_well);
5373
5374int i915_init_power_well(struct drm_device *dev)
5375{
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377
5378 hsw_pwr = &dev_priv->power_well;
5379
5380 hsw_pwr->device = dev;
5381 spin_lock_init(&hsw_pwr->lock);
5382 hsw_pwr->count = 0;
5383
5384 return 0;
5385}
5386
5387void i915_remove_power_well(struct drm_device *dev)
5388{
5389 hsw_pwr = NULL;
5390}
5391
5392void intel_set_power_well(struct drm_device *dev, bool enable)
5393{
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395 struct i915_power_well *power_well = &dev_priv->power_well;
5396
5397 if (!HAS_POWER_WELL(dev))
5398 return;
5399
5400 if (!i915_disable_power_well && !enable)
5401 return;
5402
5403 spin_lock_irq(&power_well->lock);
5404 power_well->i915_request = enable;
5405
5406 /* only reject "disable" power well request */
5407 if (power_well->count && !enable) {
5408 spin_unlock_irq(&power_well->lock);
5409 return;
5410 }
5411
5412 __intel_set_power_well(dev, enable);
5413 spin_unlock_irq(&power_well->lock);
5414}
5415
fa42e23c
PZ		 5416/*
5417 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5418 * when not needed anymore. We have 4 registers that can request the power well
5419 * to be enabled, and it will only be disabled if none of the registers is
5420 * requesting it to be enabled.
d0d3e513 5421 */
fa42e23c 5422void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5423{
5424 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5425
86d52df6 5426 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5427 return;
5428
fa42e23c
PZ		 5429 /* For now, we need the power well to be always enabled. */
5430 intel_set_power_well(dev, true);
d0d3e513 5431
fa42e23c
PZ		 5432 /* We're taking over the BIOS, so clear any requests made by it since
5433 * the driver is in charge now. */
6aedd1f5 5434 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5435 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5436}
5437
c67a470b
PZ		 5438/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5439void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5440{
5441 hsw_disable_package_c8(dev_priv);
5442}
5443
5444void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5445{
5446 hsw_enable_package_c8(dev_priv);
5447}
5448
1fa61106
ED		 5449/* Set up chip specific power management-related functions */
5450void intel_init_pm(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453
5454 if (I915_HAS_FBC(dev)) {
5455 if (HAS_PCH_SPLIT(dev)) {
5456 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5457 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5458 dev_priv->display.enable_fbc =
5459 gen7_enable_fbc;
5460 else
5461 dev_priv->display.enable_fbc =
5462 ironlake_enable_fbc;
1fa61106
ED		 5463 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5464 } else if (IS_GM45(dev)) {
5465 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5466 dev_priv->display.enable_fbc = g4x_enable_fbc;
5467 dev_priv->display.disable_fbc = g4x_disable_fbc;
5468 } else if (IS_CRESTLINE(dev)) {
5469 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5470 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5471 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5472 }
5473 /* 855GM needs testing */
5474 }
5475
c921aba8
DV		 5476 /* For cxsr */
5477 if (IS_PINEVIEW(dev))
5478 i915_pineview_get_mem_freq(dev);
5479 else if (IS_GEN5(dev))
5480 i915_ironlake_get_mem_freq(dev);
5481
1fa61106
ED		 5482 /* For FIFO watermark updates */
5483 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5484 intel_setup_wm_latency(dev);
5485
1fa61106 5486 if (IS_GEN5(dev)) {
53615a5e
VS		 5487 if (dev_priv->wm.pri_latency[1] &&
5488 dev_priv->wm.spr_latency[1] &&
5489 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5490 dev_priv->display.update_wm = ironlake_update_wm;
5491 else {
5492 DRM_DEBUG_KMS("Failed to get proper latency. "
5493 "Disable CxSR\n");
5494 dev_priv->display.update_wm = NULL;
5495 }
5496 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5497 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5498 if (dev_priv->wm.pri_latency[0] &&
5499 dev_priv->wm.spr_latency[0] &&
5500 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5501 dev_priv->display.update_wm = sandybridge_update_wm;
5502 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5503 } else {
5504 DRM_DEBUG_KMS("Failed to read display plane latency. "
5505 "Disable CxSR\n");
5506 dev_priv->display.update_wm = NULL;
5507 }
5508 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5509 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5510 if (dev_priv->wm.pri_latency[0] &&
5511 dev_priv->wm.spr_latency[0] &&
5512 dev_priv->wm.cur_latency[0]) {
c43d0188 5513 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5514 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5515 } else {
5516 DRM_DEBUG_KMS("Failed to read display plane latency. "
5517 "Disable CxSR\n");
5518 dev_priv->display.update_wm = NULL;
5519 }
5520 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5521 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5522 if (dev_priv->wm.pri_latency[0] &&
5523 dev_priv->wm.spr_latency[0] &&
5524 dev_priv->wm.cur_latency[0]) {
1011d8c4 5525 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5526 dev_priv->display.update_sprite_wm =
5527 haswell_update_sprite_wm;
6b8a5eeb
ED		 5528 } else {
5529 DRM_DEBUG_KMS("Failed to read display plane latency. "
5530 "Disable CxSR\n");
5531 dev_priv->display.update_wm = NULL;
5532 }
cad2a2d7 5533 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5534 } else
5535 dev_priv->display.update_wm = NULL;
5536 } else if (IS_VALLEYVIEW(dev)) {
5537 dev_priv->display.update_wm = valleyview_update_wm;
5538 dev_priv->display.init_clock_gating =
5539 valleyview_init_clock_gating;
1fa61106
ED		 5540 } else if (IS_PINEVIEW(dev)) {
5541 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5542 dev_priv->is_ddr3,
5543 dev_priv->fsb_freq,
5544 dev_priv->mem_freq)) {
5545 DRM_INFO("failed to find known CxSR latency "
5546 "(found ddr%s fsb freq %d, mem freq %d), "
5547 "disabling CxSR\n",
5548 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5549 dev_priv->fsb_freq, dev_priv->mem_freq);
5550 /* Disable CxSR and never update its watermark again */
5551 pineview_disable_cxsr(dev);
5552 dev_priv->display.update_wm = NULL;
5553 } else
5554 dev_priv->display.update_wm = pineview_update_wm;
5555 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5556 } else if (IS_G4X(dev)) {
5557 dev_priv->display.update_wm = g4x_update_wm;
5558 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5559 } else if (IS_GEN4(dev)) {
5560 dev_priv->display.update_wm = i965_update_wm;
5561 if (IS_CRESTLINE(dev))
5562 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5563 else if (IS_BROADWATER(dev))
5564 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5565 } else if (IS_GEN3(dev)) {
5566 dev_priv->display.update_wm = i9xx_update_wm;
5567 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5568 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5569 } else if (IS_I865G(dev)) {
5570 dev_priv->display.update_wm = i830_update_wm;
5571 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5572 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5573 } else if (IS_I85X(dev)) {
5574 dev_priv->display.update_wm = i9xx_update_wm;
5575 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5576 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5577 } else {
5578 dev_priv->display.update_wm = i830_update_wm;
5579 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5580 if (IS_845G(dev))
5581 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5582 else
5583 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5584 }
5585}
5586
42c0526c
BW		 5587int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5588{
4fc688ce 5589 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5590
5591 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5592 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5593 return -EAGAIN;
5594 }
5595
5596 I915_WRITE(GEN6_PCODE_DATA, *val);
5597 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5598
5599 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5600 500)) {
5601 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5602 return -ETIMEDOUT;
5603 }
5604
5605 *val = I915_READ(GEN6_PCODE_DATA);
5606 I915_WRITE(GEN6_PCODE_DATA, 0);
5607
5608 return 0;
5609}
5610
5611int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5612{
4fc688ce 5613 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5614
5615 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5616 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5617 return -EAGAIN;
5618 }
5619
5620 I915_WRITE(GEN6_PCODE_DATA, val);
5621 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5622
5623 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5624 500)) {
5625 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5626 return -ETIMEDOUT;
5627 }
5628
5629 I915_WRITE(GEN6_PCODE_DATA, 0);
5630
5631 return 0;
5632}
a0e4e199 5633
855ba3be
JB		 5634int vlv_gpu_freq(int ddr_freq, int val)
5635{
5636 int mult, base;
5637
5638 switch (ddr_freq) {
5639 case 800:
5640 mult = 20;
5641 base = 120;
5642 break;
5643 case 1066:
5644 mult = 22;
5645 base = 133;
5646 break;
5647 case 1333:
5648 mult = 21;
5649 base = 125;
5650 break;
5651 default:
5652 return -1;
5653 }
5654
5655 return ((val - 0xbd) * mult) + base;
5656}
5657
5658int vlv_freq_opcode(int ddr_freq, int val)
5659{
5660 int mult, base;
5661
5662 switch (ddr_freq) {
5663 case 800:
5664 mult = 20;
5665 base = 120;
5666 break;
5667 case 1066:
5668 mult = 22;
5669 base = 133;
5670 break;
5671 case 1333:
5672 mult = 21;
5673 base = 125;
5674 break;
5675 default:
5676 return -1;
5677 }
5678
5679 val /= mult;
5680 val -= base / mult;
5681 val += 0xbd;
5682
5683 if (val > 0xea)
5684 val = 0xea;
5685
5686 return val;
5687}
5688
907b28c5
CW		 5689void intel_pm_init(struct drm_device *dev)
5690{
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692
5693 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5694 intel_gen6_powersave_work);
5695}
5696
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