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drm/i915: Allow preservation of watermarks, v2.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 489};
b445e3b0 490static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 510};
9d539105 511static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 517};
9d539105
VS		 518static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524};
feb56b93 525static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532
b445e3b0
ED		 533/**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
ac484963 537 * @cpp: bytes per pixel
b445e3b0
ED		 538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
ac484963 553 int fifo_size, int cpp,
b445e3b0
ED		 554 unsigned long latency_ns)
555{
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
ac484963 564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
d6feb196
VS		 579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
b445e3b0
ED		 590 return wm_size;
591}
592
593static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594{
595 struct drm_crtc *crtc, *enabled = NULL;
596
70e1e0ec 597 for_each_crtc(dev, crtc) {
3490ea5d 598 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606}
607
46ba614c 608static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 609{
46ba614c 610 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 621 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
7c5f93b0 627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 629 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
ac484963 634 cpp, latency->display_sr);
b445e3b0
ED		 635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
f4998963 637 reg |= FW_WM(wm, SR);
b445e3b0
ED		 638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
ac484963 644 cpp, latency->cursor_sr);
b445e3b0
ED		 645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 647 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
ac484963 653 cpp, latency->display_hpll_disable);
b445e3b0
ED		 654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 656 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
ac484963 662 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 665 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
5209b1f4 669 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 670 } else {
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 }
673}
674
675static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
ac484963 686 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 691 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
6e3c9717 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 698 clock = adjusted_mode->crtc_clock;
fec8cba3 699 htotal = adjusted_mode->crtc_htotal;
6e3c9717 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 702
703 /* Use the small buffer method to calculate plane watermark */
ac484963 704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
922044c9 714 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726}
727
728/*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739{
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761}
762
763static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769{
770 struct drm_crtc *crtc;
4fe8590a 771 const struct drm_display_mode *adjusted_mode;
ac484963 772 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 785 clock = adjusted_mode->crtc_clock;
fec8cba3 786 htotal = adjusted_mode->crtc_htotal;
6e3c9717 787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 789
922044c9 790 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 791 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 792 line_size = hdisplay * cpp;
b445e3b0
ED		 793
794 /* Use the minimum of the small and large buffer method for primary */
ac484963 795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
ac484963 802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809}
810
15665979
VS		 811#define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
0018fda1
VS		 814static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816{
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
ae80152d 826 I915_WRITE(DSPFW1,
15665979
VS		 827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 831 I915_WRITE(DSPFW2,
15665979
VS		 832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 835 I915_WRITE(DSPFW3,
15665979 836 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
15665979
VS		 840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 842 I915_WRITE(DSPFW8_CHV,
15665979
VS		 843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 845 I915_WRITE(DSPFW9_CHV,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 848 I915_WRITE(DSPHOWM,
15665979
VS		 849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 859 } else {
860 I915_WRITE(DSPFW7,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 863 I915_WRITE(DSPHOWM,
15665979
VS		 864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 871 }
872
2cb389b7
VS		 873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
ae80152d 879 POSTING_READ(DSPFW1);
0018fda1
VS		 880}
881
15665979
VS		 882#undef FW_WM_VLV
883
6eb1a681
VS		 884enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 888};
889
262cd2e1
VS		 890/* latency must be in 0.1us units. */
891static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
ac484963 894 unsigned int cpp,
262cd2e1
VS		 895 unsigned int latency)
896{
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 900 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904}
905
906static void vlv_setup_wm_latency(struct drm_device *dev)
907{
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
58590c14
VS		 913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
262cd2e1
VS		 915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 920 }
921}
922
923static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927{
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 929 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
ac484963 937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
ac484963 953 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958}
959
54f1b6e1
VS		 960static void vlv_compute_fifo(struct intel_crtc *crtc)
961{
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025}
1026
262cd2e1
VS		 1027static void vlv_invert_wms(struct intel_crtc *crtc)
1028{
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059}
1060
26e1fe4f 1061static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1062{
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
852eb00d 1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1073
1074 wm_state->num_active_planes = 0;
262cd2e1 1075
54f1b6e1 1076 vlv_compute_fifo(crtc);
262cd2e1
VS		 1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
5a37ed0a 1133 wm_state->wm[level].cursor;
262cd2e1
VS		 1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
58590c14 1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158}
1159
54f1b6e1
VS		 1160#define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164{
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246}
1247
1248#undef VLV_FIFO
1249
262cd2e1
VS		 1250static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252{
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
58590c14 1256 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
6f9c784b
VS		 1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
262cd2e1
VS		 1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294}
1295
1296static void vlv_update_wm(struct drm_crtc *crtc)
1297{
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
26e1fe4f 1304 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1305 vlv_merge_wm(dev, &wm);
1306
54f1b6e1
VS		 1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1310 return;
54f1b6e1 1311 }
262cd2e1
VS		 1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
852eb00d 1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1322 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1323
54f1b6e1
VS		 1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
262cd2e1
VS		 1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
852eb00d 1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1347}
1348
ae80152d
VS		 1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
46ba614c 1351static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1352{
46ba614c 1353 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
9858425c 1359 bool cxsr_enabled;
b445e3b0 1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
52bd02d8 1378 &plane_sr, &cursor_sr)) {
9858425c 1379 cxsr_enabled = true;
52bd02d8 1380 } else {
9858425c 1381 cxsr_enabled = false;
5209b1f4 1382 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0 1385
a5043453
VS		 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
f4998963
VS		 1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
b445e3b0 1397 I915_WRITE(DSPFW2,
8c919b28 1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1399 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
8c919b28 1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1403 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1407}
1408
46ba614c 1409static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1410{
46ba614c 1411 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
9858425c 1416 bool cxsr_enabled;
b445e3b0
ED		 1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
124abe07 1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1424 int clock = adjusted_mode->crtc_clock;
fec8cba3 1425 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1428 unsigned long line_time_us;
1429 int entries;
1430
922044c9 1431 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1435 cpp * hdisplay;
b445e3b0
ED		 1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1445 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
9858425c 1457 cxsr_enabled = true;
b445e3b0 1458 } else {
9858425c 1459 cxsr_enabled = false;
b445e3b0 1460 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
f4998963
VS		 1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
b445e3b0 1474 /* update cursor SR watermark */
f4998963 1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1479}
1480
f4998963
VS		 1481#undef FW_WM
1482
46ba614c 1483static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
9d539105 1500 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1504 if (intel_crtc_active(crtc)) {
241bfc38 1505 const struct drm_display_mode *adjusted_mode;
ac484963 1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
6e3c9717 1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1512 wm_info, fifo_size, cpp,
5aef6003 1513 pessimal_latency_ns);
b445e3b0 1514 enabled = crtc;
9d539105 1515 } else {
b445e3b0 1516 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
ac484963 1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
6e3c9717 1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
5aef6003 1535 pessimal_latency_ns);
b445e3b0
ED		 1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
9d539105 1540 } else {
b445e3b0 1541 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
b445e3b0
ED		 1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d 1548 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1549 struct drm_i915_gem_object *obj;
2ab1bc9d 1550
59bea882 1551 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1552
1553 /* self-refresh seems busted with untiled */
2ff8fde1 1554 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1564 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
124abe07 1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1571 int clock = adjusted_mode->crtc_clock;
fec8cba3 1572 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1575 unsigned long line_time_us;
1576 int entries;
1577
922044c9 1578 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1582 cpp * hdisplay;
b445e3b0
ED		 1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
5209b1f4
ID		 1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
6e3c9717 1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1630 4, pessimal_latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
8cfb3407 1639uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1640{
fd4daa9c 1641 uint32_t pixel_rate;
801bcfff 1642
8cfb3407 1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
8cfb3407 1648 if (pipe_config->pch_pfit.enabled) {
801bcfff 1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
801bcfff 1654
801bcfff
PZ		 1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
15126882
MR		 1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
801bcfff
PZ		 1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670}
1671
37126462 1672/* latency must be in 0.1us units. */
ac484963 1673static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1674{
1675 uint64_t ret;
1676
3312ba65
VS		 1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
ac484963 1680 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1688 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1689 uint32_t latency)
1690{
1691 uint32_t ret;
1692
3312ba65
VS		 1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
15126882
MR		 1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
3312ba65 1697
801bcfff 1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1699 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702}
1703
23297044 1704static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1705 uint8_t cpp)
cca32e9a 1706{
15126882
MR		 1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
ac484963 1713 if (WARN_ON(!cpp))
15126882
MR		 1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
ac484963 1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1719}
1720
820c1980 1721struct ilk_wm_maximums {
cca32e9a
PZ		 1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726};
1727
37126462
VS		 1728/*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
7221fc33 1732static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1733 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1734 uint32_t mem_value,
1735 bool is_lp)
801bcfff 1736{
ac484963
VS		 1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1739 uint32_t method1, method2;
1740
7221fc33 1741 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1742 return 0;
1743
ac484963 1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1745
1746 if (!is_lp)
1747 return method1;
1748
7221fc33
MR		 1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1751 drm_rect_width(&pstate->dst),
ac484963 1752 cpp, mem_value);
cca32e9a
PZ		 1753
1754 return min(method1, method2);
801bcfff
PZ		 1755}
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
801bcfff
PZ		 1763 uint32_t mem_value)
1764{
ac484963
VS		 1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1767 uint32_t method1, method2;
1768
7221fc33 1769 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1770 return 0;
1771
ac484963 1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1775 drm_rect_width(&pstate->dst),
ac484963 1776 cpp, mem_value);
801bcfff
PZ		 1777 return min(method1, method2);
1778}
1779
37126462
VS		 1780/*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
7221fc33 1784static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1785 const struct intel_plane_state *pstate,
801bcfff
PZ		 1786 uint32_t mem_value)
1787{
b2435692
MR		 1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1795
b2435692 1796 if (!cstate->base.active)
801bcfff
PZ		 1797 return 0;
1798
7221fc33
MR		 1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1801 width, cpp, mem_value);
801bcfff
PZ		 1802}
1803
cca32e9a 1804/* Only for WM_LP. */
7221fc33 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1806 const struct intel_plane_state *pstate,
1fda9882 1807 uint32_t pri_val)
cca32e9a 1808{
ac484963
VS		 1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1811
7221fc33 1812 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1813 return 0;
1814
ac484963 1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1816}
1817
158ae64f
VS		 1818static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819{
416f4727
VS		 1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1823 return 768;
1824 else
1825 return 512;
1826}
1827
4e975081
VS		 1828static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830{
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843}
1844
1845static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847{
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852}
1853
1854static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855{
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860}
1861
158ae64f
VS		 1862/* Calculate the maximum primary/sprite plane watermark */
1863static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
240264f4 1865 const struct intel_wm_config *config,
158ae64f
VS		 1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868{
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1870
1871 /* if sprites aren't enabled, sprites get nothing */
240264f4 1872 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1876 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
240264f4 1888 if (config->sprites_enabled) {
158ae64f
VS		 1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
4e975081 1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1901}
1902
1903/* Calculate the maximum cursor plane watermark */
1904static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1905 int level,
1906 const struct intel_wm_config *config)
158ae64f
VS		 1907{
1908 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1909 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
4e975081 1913 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1914}
1915
d34ff9c6 1916static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1920 struct ilk_wm_maximums *max)
158ae64f 1921{
240264f4
VS		 1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1925 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1926}
1927
a3cb4048
VS		 1928static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931{
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936}
1937
d9395655 1938static bool ilk_validate_wm_level(int level,
820c1980 1939 const struct ilk_wm_maximums *max,
d9395655 1940 struct intel_wm_level *result)
a9786a11
VS		 1941{
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
a9786a11
VS		 1976 return ret;
1977}
1978
d34ff9c6 1979static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1980 const struct intel_crtc *intel_crtc,
6f5ddd17 1981 int level,
7221fc33 1982 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1fd527cc 1986 struct intel_wm_level *result)
6f5ddd17
VS		 1987{
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
86c8bbbe
MR		 1999 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2000 pri_latency, level);
2001 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2002 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2003 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2004 result->enable = true;
2005}
2006
801bcfff 2007static uint32_t
ee91a159
MR		 2008hsw_compute_linetime_wm(struct drm_device *dev,
2009 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2012 const struct drm_display_mode *adjusted_mode =
2013 &cstate->base.adjusted_mode;
85a02deb 2014 u32 linetime, ips_linetime;
1f8eeabf 2015
ee91a159
MR		 2016 if (!cstate->base.active)
2017 return 0;
2018 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2019 return 0;
2020 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2021 return 0;
1011d8c4 2022
1f8eeabf
ED		 2023 /* The WM are computed with base on how long it takes to fill a single
2024 * row at the given clock rate, multiplied by 8.
2025 * */
124abe07
VS		 2026 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2027 adjusted_mode->crtc_clock);
2028 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2029 dev_priv->cdclk_freq);
1f8eeabf 2030
801bcfff
PZ		 2031 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2032 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2033}
2034
2af30a5c 2035static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2036{
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038
2af30a5c
PB		 2039 if (IS_GEN9(dev)) {
2040 uint32_t val;
4f947386 2041 int ret, i;
367294be 2042 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2043
2044 /* read the first set of memory latencies[0:3] */
2045 val = 0; /* data0 to be programmed to 0 for first set */
2046 mutex_lock(&dev_priv->rps.hw_lock);
2047 ret = sandybridge_pcode_read(dev_priv,
2048 GEN9_PCODE_READ_MEM_LATENCY,
2049 &val);
2050 mutex_unlock(&dev_priv->rps.hw_lock);
2051
2052 if (ret) {
2053 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2054 return;
2055 }
2056
2057 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2058 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2059 GEN9_MEM_LATENCY_LEVEL_MASK;
2060 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2061 GEN9_MEM_LATENCY_LEVEL_MASK;
2062 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2063 GEN9_MEM_LATENCY_LEVEL_MASK;
2064
2065 /* read the second set of memory latencies[4:7] */
2066 val = 1; /* data0 to be programmed to 1 for second set */
2067 mutex_lock(&dev_priv->rps.hw_lock);
2068 ret = sandybridge_pcode_read(dev_priv,
2069 GEN9_PCODE_READ_MEM_LATENCY,
2070 &val);
2071 mutex_unlock(&dev_priv->rps.hw_lock);
2072 if (ret) {
2073 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2074 return;
2075 }
2076
2077 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2078 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2079 GEN9_MEM_LATENCY_LEVEL_MASK;
2080 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2081 GEN9_MEM_LATENCY_LEVEL_MASK;
2082 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2083 GEN9_MEM_LATENCY_LEVEL_MASK;
2084
367294be 2085 /*
6f97235b
DL		 2086 * WaWmMemoryReadLatency:skl
2087 *
367294be
VK		 2088 * punit doesn't take into account the read latency so we need
2089 * to add 2us to the various latency levels we retrieve from
2090 * the punit.
2091 * - W0 is a bit special in that it's the only level that
2092 * can't be disabled if we want to have display working, so
2093 * we always add 2us there.
2094 * - For levels >=1, punit returns 0us latency when they are
2095 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2096 *
2097 * Additionally, if a level n (n > 1) has a 0us latency, all
2098 * levels m (m >= n) need to be disabled. We make sure to
2099 * sanitize the values out of the punit to satisfy this
2100 * requirement.
367294be
VK		 2101 */
2102 wm[0] += 2;
2103 for (level = 1; level <= max_level; level++)
2104 if (wm[level] != 0)
2105 wm[level] += 2;
4f947386
VK		 2106 else {
2107 for (i = level + 1; i <= max_level; i++)
2108 wm[i] = 0;
367294be 2109
4f947386
VK		 2110 break;
2111 }
2af30a5c 2112 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2113 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2114
2115 wm[0] = (sskpd >> 56) & 0xFF;
2116 if (wm[0] == 0)
2117 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2118 wm[1] = (sskpd >> 4) & 0xFF;
2119 wm[2] = (sskpd >> 12) & 0xFF;
2120 wm[3] = (sskpd >> 20) & 0x1FF;
2121 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2122 } else if (INTEL_INFO(dev)->gen >= 6) {
2123 uint32_t sskpd = I915_READ(MCH_SSKPD);
2124
2125 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2126 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2127 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2128 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2129 } else if (INTEL_INFO(dev)->gen >= 5) {
2130 uint32_t mltr = I915_READ(MLTR_ILK);
2131
2132 /* ILK primary LP0 latency is 700 ns */
2133 wm[0] = 7;
2134 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2135 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2136 }
2137}
2138
53615a5e
VS		 2139static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2140{
2141 /* ILK sprite LP0 latency is 1300 ns */
2142 if (INTEL_INFO(dev)->gen == 5)
2143 wm[0] = 13;
2144}
2145
2146static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147{
2148 /* ILK cursor LP0 latency is 1300 ns */
2149 if (INTEL_INFO(dev)->gen == 5)
2150 wm[0] = 13;
2151
2152 /* WaDoubleCursorLP3Latency:ivb */
2153 if (IS_IVYBRIDGE(dev))
2154 wm[3] *= 2;
2155}
2156
546c81fd 2157int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2158{
26ec971e 2159 /* how many WM levels are we expecting */
b6e742f6 2160 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2161 return 7;
2162 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2163 return 4;
26ec971e 2164 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2165 return 3;
26ec971e 2166 else
ad0d6dc4
VS		 2167 return 2;
2168}
7526ed79 2169
ad0d6dc4
VS		 2170static void intel_print_wm_latency(struct drm_device *dev,
2171 const char *name,
2af30a5c 2172 const uint16_t wm[8])
ad0d6dc4
VS		 2173{
2174 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2175
2176 for (level = 0; level <= max_level; level++) {
2177 unsigned int latency = wm[level];
2178
2179 if (latency == 0) {
2180 DRM_ERROR("%s WM%d latency not provided\n",
2181 name, level);
2182 continue;
2183 }
2184
2af30a5c
PB		 2185 /*
2186 * - latencies are in us on gen9.
2187 * - before then, WM1+ latency values are in 0.5us units
2188 */
2189 if (IS_GEN9(dev))
2190 latency *= 10;
2191 else if (level > 0)
26ec971e
VS		 2192 latency *= 5;
2193
2194 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2195 name, level, wm[level],
2196 latency / 10, latency % 10);
2197 }
2198}
2199
e95a2f75
VS		 2200static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2201 uint16_t wm[5], uint16_t min)
2202{
2203 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2204
2205 if (wm[0] >= min)
2206 return false;
2207
2208 wm[0] = max(wm[0], min);
2209 for (level = 1; level <= max_level; level++)
2210 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2211
2212 return true;
2213}
2214
2215static void snb_wm_latency_quirk(struct drm_device *dev)
2216{
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218 bool changed;
2219
2220 /*
2221 * The BIOS provided WM memory latency values are often
2222 * inadequate for high resolution displays. Adjust them.
2223 */
2224 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2225 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2226 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2227
2228 if (!changed)
2229 return;
2230
2231 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2232 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2233 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2234 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2235}
2236
fa50ad61 2237static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2238{
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240
2241 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2242
2243 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2244 sizeof(dev_priv->wm.pri_latency));
2245 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2246 sizeof(dev_priv->wm.pri_latency));
2247
2248 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2249 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2250
2251 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2252 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2253 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2254
2255 if (IS_GEN6(dev))
2256 snb_wm_latency_quirk(dev);
53615a5e
VS		 2257}
2258
2af30a5c
PB		 2259static void skl_setup_wm_latency(struct drm_device *dev)
2260{
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262
2263 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2264 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2265}
2266
ed4a6a7c
MR		 2267static bool ilk_validate_pipe_wm(struct drm_device *dev,
2268 struct intel_pipe_wm *pipe_wm)
2269{
2270 /* LP0 watermark maximums depend on this pipe alone */
2271 const struct intel_wm_config config = {
2272 .num_pipes_active = 1,
2273 .sprites_enabled = pipe_wm->sprites_enabled,
2274 .sprites_scaled = pipe_wm->sprites_scaled,
2275 };
2276 struct ilk_wm_maximums max;
2277
2278 /* LP0 watermarks always use 1/2 DDB partitioning */
2279 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2280
2281 /* At least LP0 must be valid */
2282 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2283 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2284 return false;
2285 }
2286
2287 return true;
2288}
2289
0b2ae6d7 2290/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2291static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2292 struct drm_atomic_state *state)
0b2ae6d7 2293{
86c8bbbe
MR		 2294 struct intel_pipe_wm *pipe_wm;
2295 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2296 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2297 struct intel_crtc_state *cstate = NULL;
43d59eda 2298 struct intel_plane *intel_plane;
86c8bbbe
MR		 2299 struct drm_plane_state *ps;
2300 struct intel_plane_state *pristate = NULL;
43d59eda 2301 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2302 struct intel_plane_state *curstate = NULL;
d81f04c5 2303 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2304 struct ilk_wm_maximums max;
0b2ae6d7 2305
86c8bbbe
MR		 2306 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2307 if (IS_ERR(cstate))
2308 return PTR_ERR(cstate);
2309
2310 pipe_wm = &cstate->wm.optimal.ilk;
2311
43d59eda 2312 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2313 ps = drm_atomic_get_plane_state(state,
2314 &intel_plane->base);
2315 if (IS_ERR(ps))
2316 return PTR_ERR(ps);
2317
2318 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2319 pristate = to_intel_plane_state(ps);
2320 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2321 sprstate = to_intel_plane_state(ps);
2322 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2323 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2324 }
2325
ed4a6a7c
MR		 2326 pipe_wm->pipe_enabled = cstate->base.active;
2327 pipe_wm->sprites_enabled = sprstate->visible;
2328 pipe_wm->sprites_scaled = sprstate->visible &&
43d59eda
MR		 2329 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2330 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2331
d81f04c5
ML		 2332 usable_level = max_level;
2333
7b39a0b7 2334 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2335 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
d81f04c5 2336 usable_level = 1;
7b39a0b7
VS		 2337
2338 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2339 if (pipe_wm->sprites_scaled)
d81f04c5 2340 usable_level = 0;
7b39a0b7 2341
86c8bbbe
MR		 2342 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2343 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2344
a42a5719 2345 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2346 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2347
ed4a6a7c 2348 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2349 return -EINVAL;
a3cb4048
VS		 2350
2351 ilk_compute_wm_reg_maximums(dev, 1, &max);
2352
2353 for (level = 1; level <= max_level; level++) {
d81f04c5 2354 struct intel_wm_level *wm = &pipe_wm->wm[level];
a3cb4048 2355
86c8bbbe 2356 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2357 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2358
2359 /*
2360 * Disable any watermark level that exceeds the
2361 * register maximums since such watermarks are
2362 * always invalid.
2363 */
d81f04c5
ML		 2364 if (level > usable_level) {
2365 wm->enable = false;
2366 } else if (!ilk_validate_wm_level(level, &max, wm)) {
2367 wm->enable = false;
2368 usable_level = level;
2369 }
a3cb4048
VS		 2370 }
2371
86c8bbbe 2372 return 0;
0b2ae6d7
VS		 2373}
2374
ed4a6a7c
MR		 2375/*
2376 * Build a set of 'intermediate' watermark values that satisfy both the old
2377 * state and the new state. These can be programmed to the hardware
2378 * immediately.
2379 */
2380static int ilk_compute_intermediate_wm(struct drm_device *dev,
2381 struct intel_crtc *intel_crtc,
2382 struct intel_crtc_state *newstate)
2383{
2384 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2385 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2386 int level, max_level = ilk_wm_max_level(dev);
2387
2388 /*
2389 * Start with the final, target watermarks, then combine with the
2390 * currently active watermarks to get values that are safe both before
2391 * and after the vblank.
2392 */
2393 *a = newstate->wm.optimal.ilk;
2394 a->pipe_enabled |= b->pipe_enabled;
2395 a->sprites_enabled |= b->sprites_enabled;
2396 a->sprites_scaled |= b->sprites_scaled;
2397
2398 for (level = 0; level <= max_level; level++) {
2399 struct intel_wm_level *a_wm = &a->wm[level];
2400 const struct intel_wm_level *b_wm = &b->wm[level];
2401
2402 a_wm->enable &= b_wm->enable;
2403 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2404 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2405 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2406 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2407 }
2408
2409 /*
2410 * We need to make sure that these merged watermark values are
2411 * actually a valid configuration themselves. If they're not,
2412 * there's no safe way to transition from the old state to
2413 * the new state, so we need to fail the atomic transaction.
2414 */
2415 if (!ilk_validate_pipe_wm(dev, a))
2416 return -EINVAL;
2417
2418 /*
2419 * If our intermediate WM are identical to the final WM, then we can
2420 * omit the post-vblank programming; only update if it's different.
2421 */
2422 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2423 newstate->wm.need_postvbl_update = false;
2424
2425 return 0;
2426}
2427
0b2ae6d7
VS		 2428/*
2429 * Merge the watermarks from all active pipes for a specific level.
2430 */
2431static void ilk_merge_wm_level(struct drm_device *dev,
2432 int level,
2433 struct intel_wm_level *ret_wm)
2434{
2435 const struct intel_crtc *intel_crtc;
2436
d52fea5b
VS		 2437 ret_wm->enable = true;
2438
d3fcc808 2439 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2440 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2441 const struct intel_wm_level *wm = &active->wm[level];
2442
2443 if (!active->pipe_enabled)
2444 continue;
0b2ae6d7 2445
d52fea5b
VS		 2446 /*
2447 * The watermark values may have been used in the past,
2448 * so we must maintain them in the registers for some
2449 * time even if the level is now disabled.
2450 */
0b2ae6d7 2451 if (!wm->enable)
d52fea5b 2452 ret_wm->enable = false;
0b2ae6d7
VS		 2453
2454 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2455 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2456 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2457 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2458 }
0b2ae6d7
VS		 2459}
2460
2461/*
2462 * Merge all low power watermarks for all active pipes.
2463 */
2464static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2465 const struct intel_wm_config *config,
820c1980 2466 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2467 struct intel_pipe_wm *merged)
2468{
7733b49b 2469 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2470 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2471 int last_enabled_level = max_level;
0b2ae6d7 2472
0ba22e26
VS		 2473 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2474 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2475 config->num_pipes_active > 1)
2476 return;
2477
6c8b6c28
VS		 2478 /* ILK: FBC WM must be disabled always */
2479 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2480
2481 /* merge each WM1+ level */
2482 for (level = 1; level <= max_level; level++) {
2483 struct intel_wm_level *wm = &merged->wm[level];
2484
2485 ilk_merge_wm_level(dev, level, wm);
2486
d52fea5b
VS		 2487 if (level > last_enabled_level)
2488 wm->enable = false;
2489 else if (!ilk_validate_wm_level(level, max, wm))
2490 /* make sure all following levels get disabled */
2491 last_enabled_level = level - 1;
0b2ae6d7
VS		 2492
2493 /*
2494 * The spec says it is preferred to disable
2495 * FBC WMs instead of disabling a WM level.
2496 */
2497 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2498 if (wm->enable)
2499 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2500 wm->fbc_val = 0;
2501 }
2502 }
6c8b6c28
VS		 2503
2504 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2505 /*
2506 * FIXME this is racy. FBC might get enabled later.
2507 * What we should check here is whether FBC can be
2508 * enabled sometime later.
2509 */
7733b49b 2510 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2511 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2512 for (level = 2; level <= max_level; level++) {
2513 struct intel_wm_level *wm = &merged->wm[level];
2514
2515 wm->enable = false;
2516 }
2517 }
0b2ae6d7
VS		 2518}
2519
b380ca3c
VS		 2520static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2521{
2522 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2523 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2524}
2525
a68d68ee
VS		 2526/* The value we need to program into the WM_LPx latency field */
2527static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2528{
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530
a42a5719 2531 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2532 return 2 * level;
2533 else
2534 return dev_priv->wm.pri_latency[level];
2535}
2536
820c1980 2537static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2538 const struct intel_pipe_wm *merged,
609cedef 2539 enum intel_ddb_partitioning partitioning,
820c1980 2540 struct ilk_wm_values *results)
801bcfff 2541{
0b2ae6d7
VS		 2542 struct intel_crtc *intel_crtc;
2543 int level, wm_lp;
cca32e9a 2544
0362c781 2545 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2546 results->partitioning = partitioning;
cca32e9a 2547
0b2ae6d7 2548 /* LP1+ register values */
cca32e9a 2549 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2550 const struct intel_wm_level *r;
801bcfff 2551
b380ca3c 2552 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2553
0362c781 2554 r = &merged->wm[level];
cca32e9a 2555
d52fea5b
VS		 2556 /*
2557 * Maintain the watermark values even if the level is
2558 * disabled. Doing otherwise could cause underruns.
2559 */
2560 results->wm_lp[wm_lp - 1] =
a68d68ee 2561 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2562 (r->pri_val << WM1_LP_SR_SHIFT) |
2563 r->cur_val;
2564
d52fea5b
VS		 2565 if (r->enable)
2566 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2567
416f4727
VS		 2568 if (INTEL_INFO(dev)->gen >= 8)
2569 results->wm_lp[wm_lp - 1] |=
2570 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2571 else
2572 results->wm_lp[wm_lp - 1] |=
2573 r->fbc_val << WM1_LP_FBC_SHIFT;
2574
d52fea5b
VS		 2575 /*
2576 * Always set WM1S_LP_EN when spr_val != 0, even if the
2577 * level is disabled. Doing otherwise could cause underruns.
2578 */
6cef2b8a
VS		 2579 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2580 WARN_ON(wm_lp != 1);
2581 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2582 } else
2583 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2584 }
801bcfff 2585
0b2ae6d7 2586 /* LP0 register values */
d3fcc808 2587 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2588 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2589 const struct intel_wm_level *r =
2590 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2591
2592 if (WARN_ON(!r->enable))
2593 continue;
2594
ed4a6a7c 2595 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2596
0b2ae6d7
VS		 2597 results->wm_pipe[pipe] =
2598 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2599 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2600 r->cur_val;
801bcfff
PZ		 2601 }
2602}
2603
861f3389
PZ		 2604/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2605 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2606static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2607 struct intel_pipe_wm *r1,
2608 struct intel_pipe_wm *r2)
861f3389 2609{
198a1e9b
VS		 2610 int level, max_level = ilk_wm_max_level(dev);
2611 int level1 = 0, level2 = 0;
861f3389 2612
198a1e9b
VS		 2613 for (level = 1; level <= max_level; level++) {
2614 if (r1->wm[level].enable)
2615 level1 = level;
2616 if (r2->wm[level].enable)
2617 level2 = level;
861f3389
PZ		 2618 }
2619
198a1e9b
VS		 2620 if (level1 == level2) {
2621 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2622 return r2;
2623 else
2624 return r1;
198a1e9b 2625 } else if (level1 > level2) {
861f3389
PZ		 2626 return r1;
2627 } else {
2628 return r2;
2629 }
2630}
2631
49a687c4
VS		 2632/* dirty bits used to track which watermarks need changes */
2633#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2634#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2635#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2636#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2637#define WM_DIRTY_FBC (1 << 24)
2638#define WM_DIRTY_DDB (1 << 25)
2639
055e393f 2640static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2641 const struct ilk_wm_values *old,
2642 const struct ilk_wm_values *new)
49a687c4
VS		 2643{
2644 unsigned int dirty = 0;
2645 enum pipe pipe;
2646 int wm_lp;
2647
055e393f 2648 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2649 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2650 dirty |= WM_DIRTY_LINETIME(pipe);
2651 /* Must disable LP1+ watermarks too */
2652 dirty |= WM_DIRTY_LP_ALL;
2653 }
2654
2655 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2656 dirty |= WM_DIRTY_PIPE(pipe);
2657 /* Must disable LP1+ watermarks too */
2658 dirty |= WM_DIRTY_LP_ALL;
2659 }
2660 }
2661
2662 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2663 dirty |= WM_DIRTY_FBC;
2664 /* Must disable LP1+ watermarks too */
2665 dirty |= WM_DIRTY_LP_ALL;
2666 }
2667
2668 if (old->partitioning != new->partitioning) {
2669 dirty |= WM_DIRTY_DDB;
2670 /* Must disable LP1+ watermarks too */
2671 dirty |= WM_DIRTY_LP_ALL;
2672 }
2673
2674 /* LP1+ watermarks already deemed dirty, no need to continue */
2675 if (dirty & WM_DIRTY_LP_ALL)
2676 return dirty;
2677
2678 /* Find the lowest numbered LP1+ watermark in need of an update... */
2679 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2680 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2681 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2682 break;
2683 }
2684
2685 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2686 for (; wm_lp <= 3; wm_lp++)
2687 dirty |= WM_DIRTY_LP(wm_lp);
2688
2689 return dirty;
2690}
2691
8553c18e
VS		 2692static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2693 unsigned int dirty)
801bcfff 2694{
820c1980 2695 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2696 bool changed = false;
801bcfff 2697
facd619b
VS		 2698 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2699 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2700 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2701 changed = true;
facd619b
VS		 2702 }
2703 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2704 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2705 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2706 changed = true;
facd619b
VS		 2707 }
2708 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2709 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2711 changed = true;
facd619b 2712 }
801bcfff 2713
facd619b
VS		 2714 /*
2715 * Don't touch WM1S_LP_EN here.
2716 * Doing so could cause underruns.
2717 */
6cef2b8a 2718
8553c18e
VS		 2719 return changed;
2720}
2721
2722/*
2723 * The spec says we shouldn't write when we don't need, because every write
2724 * causes WMs to be re-evaluated, expending some power.
2725 */
820c1980
ID		 2726static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2727 struct ilk_wm_values *results)
8553c18e
VS		 2728{
2729 struct drm_device *dev = dev_priv->dev;
820c1980 2730 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2731 unsigned int dirty;
2732 uint32_t val;
2733
055e393f 2734 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2735 if (!dirty)
2736 return;
2737
2738 _ilk_disable_lp_wm(dev_priv, dirty);
2739
49a687c4 2740 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2741 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2742 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2743 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2744 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2745 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2746
49a687c4 2747 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2748 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2749 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2750 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2751 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2752 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2753
49a687c4 2754 if (dirty & WM_DIRTY_DDB) {
a42a5719 2755 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2756 val = I915_READ(WM_MISC);
2757 if (results->partitioning == INTEL_DDB_PART_1_2)
2758 val &= ~WM_MISC_DATA_PARTITION_5_6;
2759 else
2760 val |= WM_MISC_DATA_PARTITION_5_6;
2761 I915_WRITE(WM_MISC, val);
2762 } else {
2763 val = I915_READ(DISP_ARB_CTL2);
2764 if (results->partitioning == INTEL_DDB_PART_1_2)
2765 val &= ~DISP_DATA_PARTITION_5_6;
2766 else
2767 val |= DISP_DATA_PARTITION_5_6;
2768 I915_WRITE(DISP_ARB_CTL2, val);
2769 }
1011d8c4
PZ		 2770 }
2771
49a687c4 2772 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2773 val = I915_READ(DISP_ARB_CTL);
2774 if (results->enable_fbc_wm)
2775 val &= ~DISP_FBC_WM_DIS;
2776 else
2777 val |= DISP_FBC_WM_DIS;
2778 I915_WRITE(DISP_ARB_CTL, val);
2779 }
2780
954911eb
ID		 2781 if (dirty & WM_DIRTY_LP(1) &&
2782 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2783 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2784
2785 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2786 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2787 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2788 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2789 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2790 }
801bcfff 2791
facd619b 2792 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2793 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2794 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2795 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2796 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2797 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2798
2799 dev_priv->wm.hw = *results;
801bcfff
PZ		 2800}
2801
ed4a6a7c 2802bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2803{
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805
2806 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2807}
2808
b9cec075
DL		 2809/*
2810 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2811 * different active planes.
2812 */
2813
2814#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2815#define BXT_DDB_SIZE 512
b9cec075 2816
024c9045
MR		 2817/*
2818 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2819 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2820 * other universal planes are in indices 1..n. Note that this may leave unused
2821 * indices between the top "sprite" plane and the cursor.
2822 */
2823static int
2824skl_wm_plane_id(const struct intel_plane *plane)
2825{
2826 switch (plane->base.type) {
2827 case DRM_PLANE_TYPE_PRIMARY:
2828 return 0;
2829 case DRM_PLANE_TYPE_CURSOR:
2830 return PLANE_CURSOR;
2831 case DRM_PLANE_TYPE_OVERLAY:
2832 return plane->plane + 1;
2833 default:
2834 MISSING_CASE(plane->base.type);
2835 return plane->plane;
2836 }
2837}
2838
b9cec075
DL		 2839static void
2840skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2841 const struct intel_crtc_state *cstate,
b9cec075 2842 const struct intel_wm_config *config,
b9cec075
DL		 2843 struct skl_ddb_entry *alloc /* out */)
2844{
024c9045 2845 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2846 struct drm_crtc *crtc;
2847 unsigned int pipe_size, ddb_size;
2848 int nth_active_pipe;
2849
024c9045 2850 if (!cstate->base.active) {
b9cec075
DL		 2851 alloc->start = 0;
2852 alloc->end = 0;
2853 return;
2854 }
2855
43d735a6
DL		 2856 if (IS_BROXTON(dev))
2857 ddb_size = BXT_DDB_SIZE;
2858 else
2859 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2860
2861 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2862
2863 nth_active_pipe = 0;
2864 for_each_crtc(dev, crtc) {
3ef00284 2865 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2866 continue;
2867
2868 if (crtc == for_crtc)
2869 break;
2870
2871 nth_active_pipe++;
2872 }
2873
2874 pipe_size = ddb_size / config->num_pipes_active;
2875 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2876 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2877}
2878
2879static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2880{
2881 if (config->num_pipes_active == 1)
2882 return 32;
2883
2884 return 8;
2885}
2886
a269c583
DL		 2887static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2888{
2889 entry->start = reg & 0x3ff;
2890 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2891 if (entry->end)
2892 entry->end += 1;
a269c583
DL		 2893}
2894
08db6652
DL		 2895void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2896 struct skl_ddb_allocation *ddb /* out */)
a269c583 2897{
a269c583
DL		 2898 enum pipe pipe;
2899 int plane;
2900 u32 val;
2901
b10f1b20
ML		 2902 memset(ddb, 0, sizeof(*ddb));
2903
a269c583 2904 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2905 enum intel_display_power_domain power_domain;
2906
2907 power_domain = POWER_DOMAIN_PIPE(pipe);
2908 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2909 continue;
2910
dd740780 2911 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2912 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2913 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2914 val);
2915 }
2916
2917 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2918 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2919 val);
4d800030
ID		 2920
2921 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2922 }
2923}
2924
b9cec075 2925static unsigned int
024c9045
MR		 2926skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2927 const struct drm_plane_state *pstate,
2928 int y)
b9cec075 2929{
024c9045
MR		 2930 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2931 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2932
2933 /* for planar format */
024c9045 2934 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2935 if (y) /* y-plane data rate */
024c9045
MR		 2936 return intel_crtc->config->pipe_src_w *
2937 intel_crtc->config->pipe_src_h *
2938 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2939 else /* uv-plane data rate */
024c9045
MR		 2940 return (intel_crtc->config->pipe_src_w/2) *
2941 (intel_crtc->config->pipe_src_h/2) *
2942 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2943 }
2944
2945 /* for packed formats */
024c9045
MR		 2946 return intel_crtc->config->pipe_src_w *
2947 intel_crtc->config->pipe_src_h *
2948 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2949}
2950
2951/*
2952 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2953 * a 8192x4096@32bpp framebuffer:
2954 * 3 * 4096 * 8192 * 4 < 2^32
2955 */
2956static unsigned int
024c9045 2957skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2958{
024c9045
MR		 2959 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2960 struct drm_device *dev = intel_crtc->base.dev;
2961 const struct intel_plane *intel_plane;
b9cec075 2962 unsigned int total_data_rate = 0;
b9cec075 2963
024c9045
MR		 2964 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2965 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2966
024c9045 2967 if (pstate->fb == NULL)
b9cec075
DL		 2968 continue;
2969
024c9045
MR		 2970 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2971 continue;
2972
2973 /* packed/uv */
2974 total_data_rate += skl_plane_relative_data_rate(cstate,
2975 pstate,
2976 0);
2977
2978 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2979 /* y-plane */
2980 total_data_rate += skl_plane_relative_data_rate(cstate,
2981 pstate,
2982 1);
b9cec075
DL		 2983 }
2984
2985 return total_data_rate;
2986}
2987
2988static void
024c9045 2989skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2990 struct skl_ddb_allocation *ddb /* out */)
2991{
024c9045 2992 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2993 struct drm_device *dev = crtc->dev;
aa363136
MR		 2994 struct drm_i915_private *dev_priv = to_i915(dev);
2995 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2997 struct intel_plane *intel_plane;
b9cec075 2998 enum pipe pipe = intel_crtc->pipe;
34bb56af 2999 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3000 uint16_t alloc_size, start, cursor_blocks;
80958155 3001 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 3002 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 3003 unsigned int total_data_rate;
b9cec075 3004
024c9045 3005 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 3006 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3007 if (alloc_size == 0) {
3008 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 3009 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3010 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 3011 return;
3012 }
3013
3014 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 3015 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3016 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3017
3018 alloc_size -= cursor_blocks;
34bb56af 3019 alloc->end -= cursor_blocks;
b9cec075 3020
80958155 3021 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 3022 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3023 struct drm_plane *plane = &intel_plane->base;
3024 struct drm_framebuffer *fb = plane->state->fb;
3025 int id = skl_wm_plane_id(intel_plane);
80958155 3026
024c9045
MR		 3027 if (fb == NULL)
3028 continue;
3029 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 3030 continue;
3031
024c9045
MR		 3032 minimum[id] = 8;
3033 alloc_size -= minimum[id];
3034 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3035 alloc_size -= y_minimum[id];
80958155
DL		 3036 }
3037
b9cec075 3038 /*
80958155
DL		 3039 * 2. Distribute the remaining space in proportion to the amount of
3040 * data each plane needs to fetch from memory.
b9cec075
DL		 3041 *
3042 * FIXME: we may not allocate every single block here.
3043 */
024c9045 3044 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3045
34bb56af 3046 start = alloc->start;
024c9045
MR		 3047 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3048 struct drm_plane *plane = &intel_plane->base;
3049 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3050 unsigned int data_rate, y_data_rate;
3051 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3052 int id = skl_wm_plane_id(intel_plane);
b9cec075 3053
024c9045
MR		 3054 if (pstate->fb == NULL)
3055 continue;
3056 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3057 continue;
3058
024c9045 3059 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3060
3061 /*
2cd601c6 3062 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3063 * promote the expression to 64 bits to avoid overflowing, the
3064 * result is < available as data_rate / total_data_rate < 1
3065 */
024c9045 3066 plane_blocks = minimum[id];
80958155
DL		 3067 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3068 total_data_rate);
b9cec075 3069
024c9045
MR		 3070 ddb->plane[pipe][id].start = start;
3071 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3072
3073 start += plane_blocks;
2cd601c6
CK		 3074
3075 /*
3076 * allocation for y_plane part of planar format:
3077 */
024c9045
MR		 3078 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3079 y_data_rate = skl_plane_relative_data_rate(cstate,
3080 pstate,
3081 1);
3082 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3083 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3084 total_data_rate);
3085
024c9045
MR		 3086 ddb->y_plane[pipe][id].start = start;
3087 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3088
3089 start += y_plane_blocks;
3090 }
3091
b9cec075
DL		 3092 }
3093
3094}
3095
5cec258b 3096static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3097{
3098 /* TODO: Take into account the scalers once we support them */
2d112de7 3099 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3100}
3101
3102/*
3103 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3104 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3105 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3106 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3107*/
ac484963 3108static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3109{
3110 uint32_t wm_intermediate_val, ret;
3111
3112 if (latency == 0)
3113 return UINT_MAX;
3114
ac484963 3115 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3116 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3117
3118 return ret;
3119}
3120
3121static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3122 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3123 uint64_t tiling, uint32_t latency)
2d41c0b5 3124{
d4c2aa60
TU		 3125 uint32_t ret;
3126 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3127 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3128
3129 if (latency == 0)
3130 return UINT_MAX;
3131
ac484963 3132 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3133
3134 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3135 tiling == I915_FORMAT_MOD_Yf_TILED) {
3136 plane_bytes_per_line *= 4;
3137 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3138 plane_blocks_per_line /= 4;
3139 } else {
3140 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3141 }
3142
2d41c0b5
PB		 3143 wm_intermediate_val = latency * pixel_rate;
3144 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3145 plane_blocks_per_line;
2d41c0b5
PB		 3146
3147 return ret;
3148}
3149
2d41c0b5
PB		 3150static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3151 const struct intel_crtc *intel_crtc)
3152{
3153 struct drm_device *dev = intel_crtc->base.dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3156
e6d90023
KM		 3157 /*
3158 * If ddb allocation of pipes changed, it may require recalculation of
3159 * watermarks
3160 */
3161 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3162 return true;
3163
3164 return false;
3165}
3166
d4c2aa60 3167static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3168 struct intel_crtc_state *cstate,
3169 struct intel_plane *intel_plane,
afb024aa 3170 uint16_t ddb_allocation,
d4c2aa60 3171 int level,
afb024aa
DL		 3172 uint16_t *out_blocks, /* out */
3173 uint8_t *out_lines /* out */)
2d41c0b5 3174{
024c9045
MR		 3175 struct drm_plane *plane = &intel_plane->base;
3176 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3177 uint32_t latency = dev_priv->wm.skl_latency[level];
3178 uint32_t method1, method2;
3179 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3180 uint32_t res_blocks, res_lines;
3181 uint32_t selected_result;
ac484963 3182 uint8_t cpp;
2d41c0b5 3183
024c9045 3184 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3185 return false;
3186
ac484963 3187 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3188 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3189 cpp, latency);
024c9045
MR		 3190 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3191 cstate->base.adjusted_mode.crtc_htotal,
3192 cstate->pipe_src_w,
ac484963 3193 cpp, fb->modifier[0],
d4c2aa60 3194 latency);
2d41c0b5 3195
ac484963 3196 plane_bytes_per_line = cstate->pipe_src_w * cpp;
d4c2aa60 3197 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3198
024c9045
MR		 3199 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3200 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3201 uint32_t min_scanlines = 4;
3202 uint32_t y_tile_minimum;
024c9045 3203 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3204 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3205 drm_format_plane_cpp(fb->pixel_format, 1) :
3206 drm_format_plane_cpp(fb->pixel_format, 0);
3207
ac484963 3208 switch (cpp) {
1fc0a8f7
TU		 3209 case 1:
3210 min_scanlines = 16;
3211 break;
3212 case 2:
3213 min_scanlines = 8;
3214 break;
3215 case 8:
3216 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3217 }
1fc0a8f7
TU		 3218 }
3219 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3220 selected_result = max(method2, y_tile_minimum);
3221 } else {
3222 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3223 selected_result = min(method1, method2);
3224 else
3225 selected_result = method1;
3226 }
2d41c0b5 3227
d4c2aa60
TU		 3228 res_blocks = selected_result + 1;
3229 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3230
0fda6568 3231 if (level >= 1 && level <= 7) {
024c9045
MR		 3232 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3233 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3234 res_lines += 4;
3235 else
3236 res_blocks++;
3237 }
e6d66171 3238
d4c2aa60 3239 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3240 return false;
3241
3242 *out_blocks = res_blocks;
3243 *out_lines = res_lines;
2d41c0b5
PB		 3244
3245 return true;
3246}
3247
3248static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3249 struct skl_ddb_allocation *ddb,
024c9045 3250 struct intel_crtc_state *cstate,
2d41c0b5 3251 int level,
2d41c0b5
PB		 3252 struct skl_wm_level *result)
3253{
024c9045
MR		 3254 struct drm_device *dev = dev_priv->dev;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3256 struct intel_plane *intel_plane;
2d41c0b5 3257 uint16_t ddb_blocks;
024c9045
MR		 3258 enum pipe pipe = intel_crtc->pipe;
3259
3260 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3261 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3262
2d41c0b5
PB		 3263 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3264
d4c2aa60 3265 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3266 cstate,
3267 intel_plane,
2d41c0b5 3268 ddb_blocks,
d4c2aa60 3269 level,
2d41c0b5
PB		 3270 &result->plane_res_b[i],
3271 &result->plane_res_l[i]);
3272 }
2d41c0b5
PB		 3273}
3274
407b50f3 3275static uint32_t
024c9045 3276skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3277{
024c9045 3278 if (!cstate->base.active)
407b50f3
DL		 3279 return 0;
3280
024c9045 3281 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3282 return 0;
407b50f3 3283
024c9045
MR		 3284 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3285 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3286}
3287
024c9045 3288static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3289 struct skl_wm_level *trans_wm /* out */)
407b50f3 3290{
024c9045 3291 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3293 struct intel_plane *intel_plane;
9414f563 3294
024c9045 3295 if (!cstate->base.active)
407b50f3 3296 return;
9414f563
DL		 3297
3298 /* Until we know more, just disable transition WMs */
024c9045
MR		 3299 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3300 int i = skl_wm_plane_id(intel_plane);
3301
9414f563 3302 trans_wm->plane_en[i] = false;
024c9045 3303 }
407b50f3
DL		 3304}
3305
024c9045 3306static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3307 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3308 struct skl_pipe_wm *pipe_wm)
3309{
024c9045 3310 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3311 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3312 int level, max_level = ilk_wm_max_level(dev);
3313
3314 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3315 skl_compute_wm_level(dev_priv, ddb, cstate,
3316 level, &pipe_wm->wm[level]);
2d41c0b5 3317 }
024c9045 3318 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3319
024c9045 3320 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3321}
3322
3323static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3324 struct skl_pipe_wm *p_wm,
3325 struct skl_wm_values *r,
3326 struct intel_crtc *intel_crtc)
3327{
3328 int level, max_level = ilk_wm_max_level(dev);
3329 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3330 uint32_t temp;
3331 int i;
2d41c0b5
PB		 3332
3333 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3334 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3335 temp = 0;
2d41c0b5
PB		 3336
3337 temp |= p_wm->wm[level].plane_res_l[i] <<
3338 PLANE_WM_LINES_SHIFT;
3339 temp |= p_wm->wm[level].plane_res_b[i];
3340 if (p_wm->wm[level].plane_en[i])
3341 temp |= PLANE_WM_EN;
3342
3343 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3344 }
3345
3346 temp = 0;
2d41c0b5 3347
4969d33e
MR		 3348 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3349 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3350
4969d33e 3351 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3352 temp |= PLANE_WM_EN;
3353
4969d33e 3354 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3355
3356 }
3357
9414f563
DL		 3358 /* transition WMs */
3359 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3360 temp = 0;
3361 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3362 temp |= p_wm->trans_wm.plane_res_b[i];
3363 if (p_wm->trans_wm.plane_en[i])
3364 temp |= PLANE_WM_EN;
3365
3366 r->plane_trans[pipe][i] = temp;
3367 }
3368
3369 temp = 0;
4969d33e
MR		 3370 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3371 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3372 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3373 temp |= PLANE_WM_EN;
3374
4969d33e 3375 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3376
2d41c0b5
PB		 3377 r->wm_linetime[pipe] = p_wm->linetime;
3378}
3379
f0f59a00
VS		 3380static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3381 i915_reg_t reg,
16160e3d
DL		 3382 const struct skl_ddb_entry *entry)
3383{
3384 if (entry->end)
3385 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3386 else
3387 I915_WRITE(reg, 0);
3388}
3389
2d41c0b5
PB		 3390static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3391 const struct skl_wm_values *new)
3392{
3393 struct drm_device *dev = dev_priv->dev;
3394 struct intel_crtc *crtc;
3395
19c8054c 3396 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3397 int i, level, max_level = ilk_wm_max_level(dev);
3398 enum pipe pipe = crtc->pipe;
3399
5d374d96
DL		 3400 if (!new->dirty[pipe])
3401 continue;
8211bd5b 3402
5d374d96 3403 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3404
5d374d96
DL		 3405 for (level = 0; level <= max_level; level++) {
3406 for (i = 0; i < intel_num_planes(crtc); i++)
3407 I915_WRITE(PLANE_WM(pipe, i, level),
3408 new->plane[pipe][i][level]);
3409 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3410 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3411 }
5d374d96
DL		 3412 for (i = 0; i < intel_num_planes(crtc); i++)
3413 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3414 new->plane_trans[pipe][i]);
4969d33e
MR		 3415 I915_WRITE(CUR_WM_TRANS(pipe),
3416 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3417
2cd601c6 3418 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3419 skl_ddb_entry_write(dev_priv,
3420 PLANE_BUF_CFG(pipe, i),
3421 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3422 skl_ddb_entry_write(dev_priv,
3423 PLANE_NV12_BUF_CFG(pipe, i),
3424 &new->ddb.y_plane[pipe][i]);
3425 }
5d374d96
DL		 3426
3427 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3428 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3429 }
2d41c0b5
PB		 3430}
3431
0e8fb7ba
DL		 3432/*
3433 * When setting up a new DDB allocation arrangement, we need to correctly
3434 * sequence the times at which the new allocations for the pipes are taken into
3435 * account or we'll have pipes fetching from space previously allocated to
3436 * another pipe.
3437 *
3438 * Roughly the sequence looks like:
3439 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3440 * overlapping with a previous light-up pipe (another way to put it is:
3441 * pipes with their new allocation strickly included into their old ones).
3442 * 2. re-allocate the other pipes that get their allocation reduced
3443 * 3. allocate the pipes having their allocation increased
3444 *
3445 * Steps 1. and 2. are here to take care of the following case:
3446 * - Initially DDB looks like this:
3447 * | B | C |
3448 * - enable pipe A.
3449 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3450 * allocation
3451 * | A | B | C |
3452 *
3453 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3454 */
3455
d21b795c
DL		 3456static void
3457skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3458{
0e8fb7ba
DL		 3459 int plane;
3460
d21b795c
DL		 3461 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3462
dd740780 3463 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3464 I915_WRITE(PLANE_SURF(pipe, plane),
3465 I915_READ(PLANE_SURF(pipe, plane)));
3466 }
3467 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3468}
3469
3470static bool
3471skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3472 const struct skl_ddb_allocation *new,
3473 enum pipe pipe)
3474{
3475 uint16_t old_size, new_size;
3476
3477 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3478 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3479
3480 return old_size != new_size &&
3481 new->pipe[pipe].start >= old->pipe[pipe].start &&
3482 new->pipe[pipe].end <= old->pipe[pipe].end;
3483}
3484
3485static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3486 struct skl_wm_values *new_values)
3487{
3488 struct drm_device *dev = dev_priv->dev;
3489 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3490 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3491 struct intel_crtc *crtc;
3492 enum pipe pipe;
3493
3494 new_ddb = &new_values->ddb;
3495 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3496
3497 /*
3498 * First pass: flush the pipes with the new allocation contained into
3499 * the old space.
3500 *
3501 * We'll wait for the vblank on those pipes to ensure we can safely
3502 * re-allocate the freed space without this pipe fetching from it.
3503 */
3504 for_each_intel_crtc(dev, crtc) {
3505 if (!crtc->active)
3506 continue;
3507
3508 pipe = crtc->pipe;
3509
3510 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3511 continue;
3512
d21b795c 3513 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3514 intel_wait_for_vblank(dev, pipe);
3515
3516 reallocated[pipe] = true;
3517 }
3518
3519
3520 /*
3521 * Second pass: flush the pipes that are having their allocation
3522 * reduced, but overlapping with a previous allocation.
3523 *
3524 * Here as well we need to wait for the vblank to make sure the freed
3525 * space is not used anymore.
3526 */
3527 for_each_intel_crtc(dev, crtc) {
3528 if (!crtc->active)
3529 continue;
3530
3531 pipe = crtc->pipe;
3532
3533 if (reallocated[pipe])
3534 continue;
3535
3536 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3537 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3538 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3539 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3540 reallocated[pipe] = true;
0e8fb7ba 3541 }
0e8fb7ba
DL		 3542 }
3543
3544 /*
3545 * Third pass: flush the pipes that got more space allocated.
3546 *
3547 * We don't need to actively wait for the update here, next vblank
3548 * will just get more DDB space with the correct WM values.
3549 */
3550 for_each_intel_crtc(dev, crtc) {
3551 if (!crtc->active)
3552 continue;
3553
3554 pipe = crtc->pipe;
3555
3556 /*
3557 * At this point, only the pipes more space than before are
3558 * left to re-allocate.
3559 */
3560 if (reallocated[pipe])
3561 continue;
3562
d21b795c 3563 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3564 }
3565}
3566
2d41c0b5 3567static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3568 struct skl_ddb_allocation *ddb, /* out */
3569 struct skl_pipe_wm *pipe_wm /* out */)
3570{
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3572 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3573
aa363136 3574 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3575 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3576
4e0963c7 3577 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3578 return false;
3579
4e0963c7 3580 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3581
2d41c0b5
PB		 3582 return true;
3583}
3584
3585static void skl_update_other_pipe_wm(struct drm_device *dev,
3586 struct drm_crtc *crtc,
2d41c0b5
PB		 3587 struct skl_wm_values *r)
3588{
3589 struct intel_crtc *intel_crtc;
3590 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3591
3592 /*
3593 * If the WM update hasn't changed the allocation for this_crtc (the
3594 * crtc we are currently computing the new WM values for), other
3595 * enabled crtcs will keep the same allocation and we don't need to
3596 * recompute anything for them.
3597 */
3598 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3599 return;
3600
3601 /*
3602 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3603 * other active pipes need new DDB allocation and WM values.
3604 */
19c8054c 3605 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3606 struct skl_pipe_wm pipe_wm = {};
3607 bool wm_changed;
3608
3609 if (this_crtc->pipe == intel_crtc->pipe)
3610 continue;
3611
3612 if (!intel_crtc->active)
3613 continue;
3614
aa363136 3615 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3616 &r->ddb, &pipe_wm);
3617
3618 /*
3619 * If we end up re-computing the other pipe WM values, it's
3620 * because it was really needed, so we expect the WM values to
3621 * be different.
3622 */
3623 WARN_ON(!wm_changed);
3624
024c9045 3625 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3626 r->dirty[intel_crtc->pipe] = true;
3627 }
3628}
3629
adda50b8
BP		 3630static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3631{
3632 watermarks->wm_linetime[pipe] = 0;
3633 memset(watermarks->plane[pipe], 0,
3634 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3635 memset(watermarks->plane_trans[pipe],
3636 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3637 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3638
3639 /* Clear ddb entries for pipe */
3640 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3641 memset(&watermarks->ddb.plane[pipe], 0,
3642 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3643 memset(&watermarks->ddb.y_plane[pipe], 0,
3644 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3645 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3646 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3647
3648}
3649
2d41c0b5
PB		 3650static void skl_update_wm(struct drm_crtc *crtc)
3651{
3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3655 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3656 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3657 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3658
adda50b8
BP		 3659
3660 /* Clear all dirty flags */
3661 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3662
3663 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3664
aa363136 3665 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3666 return;
3667
4e0963c7 3668 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3669 results->dirty[intel_crtc->pipe] = true;
3670
aa363136 3671 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3672 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3673 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3674
3675 /* store the new configuration */
3676 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3677}
3678
d890565c
VS		 3679static void ilk_compute_wm_config(struct drm_device *dev,
3680 struct intel_wm_config *config)
3681{
3682 struct intel_crtc *crtc;
3683
3684 /* Compute the currently _active_ config */
3685 for_each_intel_crtc(dev, crtc) {
3686 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3687
3688 if (!wm->pipe_enabled)
3689 continue;
3690
3691 config->sprites_enabled |= wm->sprites_enabled;
3692 config->sprites_scaled |= wm->sprites_scaled;
3693 config->num_pipes_active++;
3694 }
3695}
3696
ed4a6a7c 3697static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3698{
ed4a6a7c 3699 struct drm_device *dev = dev_priv->dev;
b9d5c839 3700 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3701 struct ilk_wm_maximums max;
d890565c 3702 struct intel_wm_config config = {};
820c1980 3703 struct ilk_wm_values results = {};
77c122bc 3704 enum intel_ddb_partitioning partitioning;
261a27d1 3705
d890565c
VS		 3706 ilk_compute_wm_config(dev, &config);
3707
3708 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3709 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3710
3711 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3712 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3713 config.num_pipes_active == 1 && config.sprites_enabled) {
3714 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3715 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3716
820c1980 3717 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3718 } else {
198a1e9b 3719 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3720 }
3721
198a1e9b 3722 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3723 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3724
820c1980 3725 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3726
820c1980 3727 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3728}
3729
ed4a6a7c 3730static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3731{
ed4a6a7c
MR		 3732 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3733 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3734
ed4a6a7c
MR		 3735 mutex_lock(&dev_priv->wm.wm_mutex);
3736 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3737 ilk_program_watermarks(dev_priv);
3738 mutex_unlock(&dev_priv->wm.wm_mutex);
3739}
bf220452 3740
ed4a6a7c
MR		 3741static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3742{
3743 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3744 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3745
ed4a6a7c
MR		 3746 mutex_lock(&dev_priv->wm.wm_mutex);
3747 if (cstate->wm.need_postvbl_update) {
3748 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3749 ilk_program_watermarks(dev_priv);
3750 }
3751 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3752}
3753
3078999f
PB		 3754static void skl_pipe_wm_active_state(uint32_t val,
3755 struct skl_pipe_wm *active,
3756 bool is_transwm,
3757 bool is_cursor,
3758 int i,
3759 int level)
3760{
3761 bool is_enabled = (val & PLANE_WM_EN) != 0;
3762
3763 if (!is_transwm) {
3764 if (!is_cursor) {
3765 active->wm[level].plane_en[i] = is_enabled;
3766 active->wm[level].plane_res_b[i] =
3767 val & PLANE_WM_BLOCKS_MASK;
3768 active->wm[level].plane_res_l[i] =
3769 (val >> PLANE_WM_LINES_SHIFT) &
3770 PLANE_WM_LINES_MASK;
3771 } else {
4969d33e
MR		 3772 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3773 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3774 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3775 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3776 (val >> PLANE_WM_LINES_SHIFT) &
3777 PLANE_WM_LINES_MASK;
3778 }
3779 } else {
3780 if (!is_cursor) {
3781 active->trans_wm.plane_en[i] = is_enabled;
3782 active->trans_wm.plane_res_b[i] =
3783 val & PLANE_WM_BLOCKS_MASK;
3784 active->trans_wm.plane_res_l[i] =
3785 (val >> PLANE_WM_LINES_SHIFT) &
3786 PLANE_WM_LINES_MASK;
3787 } else {
4969d33e
MR		 3788 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3789 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3790 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3791 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3792 (val >> PLANE_WM_LINES_SHIFT) &
3793 PLANE_WM_LINES_MASK;
3794 }
3795 }
3796}
3797
3798static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3799{
3800 struct drm_device *dev = crtc->dev;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3804 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3805 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3806 enum pipe pipe = intel_crtc->pipe;
3807 int level, i, max_level;
3808 uint32_t temp;
3809
3810 max_level = ilk_wm_max_level(dev);
3811
3812 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3813
3814 for (level = 0; level <= max_level; level++) {
3815 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3816 hw->plane[pipe][i][level] =
3817 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3818 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3819 }
3820
3821 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3822 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3823 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3824
3ef00284 3825 if (!intel_crtc->active)
3078999f
PB		 3826 return;
3827
3828 hw->dirty[pipe] = true;
3829
3830 active->linetime = hw->wm_linetime[pipe];
3831
3832 for (level = 0; level <= max_level; level++) {
3833 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3834 temp = hw->plane[pipe][i][level];
3835 skl_pipe_wm_active_state(temp, active, false,
3836 false, i, level);
3837 }
4969d33e 3838 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3839 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3840 }
3841
3842 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3843 temp = hw->plane_trans[pipe][i];
3844 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3845 }
3846
4969d33e 3847 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3848 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3849
3850 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3851}
3852
3853void skl_wm_get_hw_state(struct drm_device *dev)
3854{
a269c583
DL		 3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3857 struct drm_crtc *crtc;
3858
a269c583 3859 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3861 skl_pipe_wm_get_hw_state(crtc);
3862}
3863
243e6a44
VS		 3864static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3865{
3866 struct drm_device *dev = crtc->dev;
3867 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3868 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3870 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3871 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3872 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3873 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3874 [PIPE_A] = WM0_PIPEA_ILK,
3875 [PIPE_B] = WM0_PIPEB_ILK,
3876 [PIPE_C] = WM0_PIPEC_IVB,
3877 };
3878
3879 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3880 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3881 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3882
3ef00284 3883 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3884
3885 if (active->pipe_enabled) {
243e6a44
VS		 3886 u32 tmp = hw->wm_pipe[pipe];
3887
3888 /*
3889 * For active pipes LP0 watermark is marked as
3890 * enabled, and LP1+ watermaks as disabled since
3891 * we can't really reverse compute them in case
3892 * multiple pipes are active.
3893 */
3894 active->wm[0].enable = true;
3895 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3896 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3897 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3898 active->linetime = hw->wm_linetime[pipe];
3899 } else {
3900 int level, max_level = ilk_wm_max_level(dev);
3901
3902 /*
3903 * For inactive pipes, all watermark levels
3904 * should be marked as enabled but zeroed,
3905 * which is what we'd compute them to.
3906 */
3907 for (level = 0; level <= max_level; level++)
3908 active->wm[level].enable = true;
3909 }
4e0963c7
MR		 3910
3911 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3912}
3913
6eb1a681
VS		 3914#define _FW_WM(value, plane) \
3915 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3916#define _FW_WM_VLV(value, plane) \
3917 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3918
3919static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3920 struct vlv_wm_values *wm)
3921{
3922 enum pipe pipe;
3923 uint32_t tmp;
3924
3925 for_each_pipe(dev_priv, pipe) {
3926 tmp = I915_READ(VLV_DDL(pipe));
3927
3928 wm->ddl[pipe].primary =
3929 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3930 wm->ddl[pipe].cursor =
3931 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3932 wm->ddl[pipe].sprite[0] =
3933 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3934 wm->ddl[pipe].sprite[1] =
3935 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3936 }
3937
3938 tmp = I915_READ(DSPFW1);
3939 wm->sr.plane = _FW_WM(tmp, SR);
3940 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3941 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3943
3944 tmp = I915_READ(DSPFW2);
3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3948
3949 tmp = I915_READ(DSPFW3);
3950 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3951
3952 if (IS_CHERRYVIEW(dev_priv)) {
3953 tmp = I915_READ(DSPFW7_CHV);
3954 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3955 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3956
3957 tmp = I915_READ(DSPFW8_CHV);
3958 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3959 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3960
3961 tmp = I915_READ(DSPFW9_CHV);
3962 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3963 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3964
3965 tmp = I915_READ(DSPHOWM);
3966 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3967 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3968 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3969 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3970 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3971 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3972 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3976 } else {
3977 tmp = I915_READ(DSPFW7);
3978 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3979 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3980
3981 tmp = I915_READ(DSPHOWM);
3982 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3983 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3984 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3985 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3989 }
3990}
3991
3992#undef _FW_WM
3993#undef _FW_WM_VLV
3994
3995void vlv_wm_get_hw_state(struct drm_device *dev)
3996{
3997 struct drm_i915_private *dev_priv = to_i915(dev);
3998 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3999 struct intel_plane *plane;
4000 enum pipe pipe;
4001 u32 val;
4002
4003 vlv_read_wm_values(dev_priv, wm);
4004
4005 for_each_intel_plane(dev, plane) {
4006 switch (plane->base.type) {
4007 int sprite;
4008 case DRM_PLANE_TYPE_CURSOR:
4009 plane->wm.fifo_size = 63;
4010 break;
4011 case DRM_PLANE_TYPE_PRIMARY:
4012 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4013 break;
4014 case DRM_PLANE_TYPE_OVERLAY:
4015 sprite = plane->plane;
4016 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4017 break;
4018 }
4019 }
4020
4021 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4022 wm->level = VLV_WM_LEVEL_PM2;
4023
4024 if (IS_CHERRYVIEW(dev_priv)) {
4025 mutex_lock(&dev_priv->rps.hw_lock);
4026
4027 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4028 if (val & DSP_MAXFIFO_PM5_ENABLE)
4029 wm->level = VLV_WM_LEVEL_PM5;
4030
58590c14
VS		 4031 /*
4032 * If DDR DVFS is disabled in the BIOS, Punit
4033 * will never ack the request. So if that happens
4034 * assume we don't have to enable/disable DDR DVFS
4035 * dynamically. To test that just set the REQ_ACK
4036 * bit to poke the Punit, but don't change the
4037 * HIGH/LOW bits so that we don't actually change
4038 * the current state.
4039 */
6eb1a681 4040 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4041 val |= FORCE_DDR_FREQ_REQ_ACK;
4042 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4043
4044 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4045 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4046 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4047 "assuming DDR DVFS is disabled\n");
4048 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4049 } else {
4050 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4051 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4052 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4053 }
6eb1a681
VS		 4054
4055 mutex_unlock(&dev_priv->rps.hw_lock);
4056 }
4057
4058 for_each_pipe(dev_priv, pipe)
4059 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4060 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4061 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4062
4063 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4064 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4065}
4066
243e6a44
VS		 4067void ilk_wm_get_hw_state(struct drm_device *dev)
4068{
4069 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4070 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4071 struct drm_crtc *crtc;
4072
70e1e0ec 4073 for_each_crtc(dev, crtc)
243e6a44
VS		 4074 ilk_pipe_wm_get_hw_state(crtc);
4075
4076 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4077 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4078 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4079
4080 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4081 if (INTEL_INFO(dev)->gen >= 7) {
4082 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4083 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4084 }
243e6a44 4085
a42a5719 4086 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4087 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4088 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4089 else if (IS_IVYBRIDGE(dev))
4090 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4091 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4092
4093 hw->enable_fbc_wm =
4094 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4095}
4096
b445e3b0
ED		 4097/**
4098 * intel_update_watermarks - update FIFO watermark values based on current modes
4099 *
4100 * Calculate watermark values for the various WM regs based on current mode
4101 * and plane configuration.
4102 *
4103 * There are several cases to deal with here:
4104 * - normal (i.e. non-self-refresh)
4105 * - self-refresh (SR) mode
4106 * - lines are large relative to FIFO size (buffer can hold up to 2)
4107 * - lines are small relative to FIFO size (buffer can hold more than 2
4108 * lines), so need to account for TLB latency
4109 *
4110 * The normal calculation is:
4111 * watermark = dotclock * bytes per pixel * latency
4112 * where latency is platform & configuration dependent (we assume pessimal
4113 * values here).
4114 *
4115 * The SR calculation is:
4116 * watermark = (trunc(latency/line time)+1) * surface width *
4117 * bytes per pixel
4118 * where
4119 * line time = htotal / dotclock
4120 * surface width = hdisplay for normal plane and 64 for cursor
4121 * and latency is assumed to be high, as above.
4122 *
4123 * The final value programmed to the register should always be rounded up,
4124 * and include an extra 2 entries to account for clock crossings.
4125 *
4126 * We don't use the sprite, so we can ignore that. And on Crestline we have
4127 * to set the non-SR watermarks to 8.
4128 */
46ba614c 4129void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4130{
46ba614c 4131 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4132
4133 if (dev_priv->display.update_wm)
46ba614c 4134 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4135}
4136
e2828914 4137/*
9270388e 4138 * Lock protecting IPS related data structures
9270388e
DV		 4139 */
4140DEFINE_SPINLOCK(mchdev_lock);
4141
4142/* Global for IPS driver to get at the current i915 device. Protected by
4143 * mchdev_lock. */
4144static struct drm_i915_private *i915_mch_dev;
4145
2b4e57bd
ED		 4146bool ironlake_set_drps(struct drm_device *dev, u8 val)
4147{
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 u16 rgvswctl;
4150
9270388e
DV		 4151 assert_spin_locked(&mchdev_lock);
4152
2b4e57bd
ED		 4153 rgvswctl = I915_READ16(MEMSWCTL);
4154 if (rgvswctl & MEMCTL_CMD_STS) {
4155 DRM_DEBUG("gpu busy, RCS change rejected\n");
4156 return false; /* still busy with another command */
4157 }
4158
4159 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4160 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4161 I915_WRITE16(MEMSWCTL, rgvswctl);
4162 POSTING_READ16(MEMSWCTL);
4163
4164 rgvswctl |= MEMCTL_CMD_STS;
4165 I915_WRITE16(MEMSWCTL, rgvswctl);
4166
4167 return true;
4168}
4169
8090c6b9 4170static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4171{
4172 struct drm_i915_private *dev_priv = dev->dev_private;
84f1b20f 4173 u32 rgvmodectl;
2b4e57bd
ED		 4174 u8 fmax, fmin, fstart, vstart;
4175
9270388e
DV		 4176 spin_lock_irq(&mchdev_lock);
4177
84f1b20f
TU		 4178 rgvmodectl = I915_READ(MEMMODECTL);
4179
2b4e57bd
ED		 4180 /* Enable temp reporting */
4181 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4182 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4183
4184 /* 100ms RC evaluation intervals */
4185 I915_WRITE(RCUPEI, 100000);
4186 I915_WRITE(RCDNEI, 100000);
4187
4188 /* Set max/min thresholds to 90ms and 80ms respectively */
4189 I915_WRITE(RCBMAXAVG, 90000);
4190 I915_WRITE(RCBMINAVG, 80000);
4191
4192 I915_WRITE(MEMIHYST, 1);
4193
4194 /* Set up min, max, and cur for interrupt handling */
4195 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4196 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4197 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4198 MEMMODE_FSTART_SHIFT;
4199
616847e7 4200 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4201 PXVFREQ_PX_SHIFT;
4202
20e4d407
DV		 4203 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4204 dev_priv->ips.fstart = fstart;
2b4e57bd 4205
20e4d407
DV		 4206 dev_priv->ips.max_delay = fstart;
4207 dev_priv->ips.min_delay = fmin;
4208 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4209
4210 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4211 fmax, fmin, fstart);
4212
4213 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4214
4215 /*
4216 * Interrupts will be enabled in ironlake_irq_postinstall
4217 */
4218
4219 I915_WRITE(VIDSTART, vstart);
4220 POSTING_READ(VIDSTART);
4221
4222 rgvmodectl |= MEMMODE_SWMODE_EN;
4223 I915_WRITE(MEMMODECTL, rgvmodectl);
4224
9270388e 4225 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4226 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4227 mdelay(1);
2b4e57bd
ED		 4228
4229 ironlake_set_drps(dev, fstart);
4230
7d81c3e0
VS		 4231 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4232 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4233 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4234 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4235 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4236
4237 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4238}
4239
8090c6b9 4240static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4241{
4242 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4243 u16 rgvswctl;
4244
4245 spin_lock_irq(&mchdev_lock);
4246
4247 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4248
4249 /* Ack interrupts, disable EFC interrupt */
4250 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4251 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4252 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4253 I915_WRITE(DEIIR, DE_PCU_EVENT);
4254 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4255
4256 /* Go back to the starting frequency */
20e4d407 4257 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4258 mdelay(1);
2b4e57bd
ED		 4259 rgvswctl |= MEMCTL_CMD_STS;
4260 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4261 mdelay(1);
2b4e57bd 4262
9270388e 4263 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4264}
4265
acbe9475
DV		 4266/* There's a funny hw issue where the hw returns all 0 when reading from
4267 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4268 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4269 * all limits and the gpu stuck at whatever frequency it is at atm).
4270 */
74ef1173 4271static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4272{
7b9e0ae6 4273 u32 limits;
2b4e57bd 4274
20b46e59
DV		 4275 /* Only set the down limit when we've reached the lowest level to avoid
4276 * getting more interrupts, otherwise leave this clear. This prevents a
4277 * race in the hw when coming out of rc6: There's a tiny window where
4278 * the hw runs at the minimal clock before selecting the desired
4279 * frequency, if the down threshold expires in that window we will not
4280 * receive a down interrupt. */
74ef1173
AG		 4281 if (IS_GEN9(dev_priv->dev)) {
4282 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4283 if (val <= dev_priv->rps.min_freq_softlimit)
4284 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4285 } else {
4286 limits = dev_priv->rps.max_freq_softlimit << 24;
4287 if (val <= dev_priv->rps.min_freq_softlimit)
4288 limits |= dev_priv->rps.min_freq_softlimit << 16;
4289 }
20b46e59
DV		 4290
4291 return limits;
4292}
4293
dd75fdc8
CW		 4294static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4295{
4296 int new_power;
8a586437
AG		 4297 u32 threshold_up = 0, threshold_down = 0; /* in % */
4298 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4299
4300 new_power = dev_priv->rps.power;
4301 switch (dev_priv->rps.power) {
4302 case LOW_POWER:
b39fb297 4303 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4304 new_power = BETWEEN;
4305 break;
4306
4307 case BETWEEN:
b39fb297 4308 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4309 new_power = LOW_POWER;
b39fb297 4310 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4311 new_power = HIGH_POWER;
4312 break;
4313
4314 case HIGH_POWER:
b39fb297 4315 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4316 new_power = BETWEEN;
4317 break;
4318 }
4319 /* Max/min bins are special */
aed242ff 4320 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4321 new_power = LOW_POWER;
aed242ff 4322 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4323 new_power = HIGH_POWER;
4324 if (new_power == dev_priv->rps.power)
4325 return;
4326
4327 /* Note the units here are not exactly 1us, but 1280ns. */
4328 switch (new_power) {
4329 case LOW_POWER:
4330 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4331 ei_up = 16000;
4332 threshold_up = 95;
dd75fdc8
CW		 4333
4334 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4335 ei_down = 32000;
4336 threshold_down = 85;
dd75fdc8
CW		 4337 break;
4338
4339 case BETWEEN:
4340 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4341 ei_up = 13000;
4342 threshold_up = 90;
dd75fdc8
CW		 4343
4344 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4345 ei_down = 32000;
4346 threshold_down = 75;
dd75fdc8
CW		 4347 break;
4348
4349 case HIGH_POWER:
4350 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4351 ei_up = 10000;
4352 threshold_up = 85;
dd75fdc8
CW		 4353
4354 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4355 ei_down = 32000;
4356 threshold_down = 60;
dd75fdc8
CW		 4357 break;
4358 }
4359
8a586437
AG		 4360 I915_WRITE(GEN6_RP_UP_EI,
4361 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4362 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4363 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4364
4365 I915_WRITE(GEN6_RP_DOWN_EI,
4366 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4367 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4368 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4369
4370 I915_WRITE(GEN6_RP_CONTROL,
4371 GEN6_RP_MEDIA_TURBO |
4372 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4373 GEN6_RP_MEDIA_IS_GFX |
4374 GEN6_RP_ENABLE |
4375 GEN6_RP_UP_BUSY_AVG |
4376 GEN6_RP_DOWN_IDLE_AVG);
4377
dd75fdc8 4378 dev_priv->rps.power = new_power;
8fb55197
CW		 4379 dev_priv->rps.up_threshold = threshold_up;
4380 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4381 dev_priv->rps.last_adj = 0;
4382}
4383
2876ce73
CW		 4384static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4385{
4386 u32 mask = 0;
4387
4388 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4389 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4390 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4391 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4392
7b3c29f6
CW		 4393 mask &= dev_priv->pm_rps_events;
4394
59d02a1f 4395 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4396}
4397
b8a5ff8d
JM		 4398/* gen6_set_rps is called to update the frequency request, but should also be
4399 * called when the range (min_delay and max_delay) is modified so that we can
4400 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4401static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4402{
4403 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4404
23eafea6 4405 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4406 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4407 return;
4408
4fc688ce 4409 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4410 WARN_ON(val > dev_priv->rps.max_freq);
4411 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4412
eb64cad1
CW		 4413 /* min/max delay may still have been modified so be sure to
4414 * write the limits value.
4415 */
4416 if (val != dev_priv->rps.cur_freq) {
4417 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4418
5704195c
AG		 4419 if (IS_GEN9(dev))
4420 I915_WRITE(GEN6_RPNSWREQ,
4421 GEN9_FREQUENCY(val));
4422 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4423 I915_WRITE(GEN6_RPNSWREQ,
4424 HSW_FREQUENCY(val));
4425 else
4426 I915_WRITE(GEN6_RPNSWREQ,
4427 GEN6_FREQUENCY(val) |
4428 GEN6_OFFSET(0) |
4429 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4430 }
7b9e0ae6 4431
7b9e0ae6
CW		 4432 /* Make sure we continue to get interrupts
4433 * until we hit the minimum or maximum frequencies.
4434 */
74ef1173 4435 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4436 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4437
d5570a72
BW		 4438 POSTING_READ(GEN6_RPNSWREQ);
4439
b39fb297 4440 dev_priv->rps.cur_freq = val;
0f94592e 4441 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4442}
4443
ffe02b40
VS		 4444static void valleyview_set_rps(struct drm_device *dev, u8 val)
4445{
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447
4448 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4449 WARN_ON(val > dev_priv->rps.max_freq);
4450 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4451
4452 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4453 "Odd GPU freq value\n"))
4454 val &= ~1;
4455
cd25dd5b
D		 4456 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4457
8fb55197 4458 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4459 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4460 if (!IS_CHERRYVIEW(dev_priv))
4461 gen6_set_rps_thresholds(dev_priv, val);
4462 }
ffe02b40 4463
ffe02b40
VS		 4464 dev_priv->rps.cur_freq = val;
4465 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4466}
4467
a7f6e231 4468/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4469 *
4470 * * If Gfx is Idle, then
a7f6e231
D		 4471 * 1. Forcewake Media well.
4472 * 2. Request idle freq.
4473 * 3. Release Forcewake of Media well.
76c3552f
D		 4474*/
4475static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4476{
aed242ff 4477 u32 val = dev_priv->rps.idle_freq;
5549d25f 4478
aed242ff 4479 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4480 return;
4481
a7f6e231
D		 4482 /* Wake up the media well, as that takes a lot less
4483 * power than the Render well. */
4484 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4485 valleyview_set_rps(dev_priv->dev, val);
4486 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4487}
4488
43cf3bf0
CW		 4489void gen6_rps_busy(struct drm_i915_private *dev_priv)
4490{
4491 mutex_lock(&dev_priv->rps.hw_lock);
4492 if (dev_priv->rps.enabled) {
4493 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4494 gen6_rps_reset_ei(dev_priv);
4495 I915_WRITE(GEN6_PMINTRMSK,
4496 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4497 }
4498 mutex_unlock(&dev_priv->rps.hw_lock);
4499}
4500
b29c19b6
CW		 4501void gen6_rps_idle(struct drm_i915_private *dev_priv)
4502{
691bb717
DL		 4503 struct drm_device *dev = dev_priv->dev;
4504
b29c19b6 4505 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4506 if (dev_priv->rps.enabled) {
666a4537 4507 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4508 vlv_set_rps_idle(dev_priv);
7526ed79 4509 else
aed242ff 4510 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4511 dev_priv->rps.last_adj = 0;
43cf3bf0 4512 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4513 }
8d3afd7d 4514 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4515
8d3afd7d 4516 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4517 while (!list_empty(&dev_priv->rps.clients))
4518 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4519 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4520}
4521
1854d5ca 4522void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4523 struct intel_rps_client *rps,
4524 unsigned long submitted)
b29c19b6 4525{
8d3afd7d
CW		 4526 /* This is intentionally racy! We peek at the state here, then
4527 * validate inside the RPS worker.
4528 */
4529 if (!(dev_priv->mm.busy &&
4530 dev_priv->rps.enabled &&
4531 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4532 return;
43cf3bf0 4533
e61b9958
CW		 4534 /* Force a RPS boost (and don't count it against the client) if
4535 * the GPU is severely congested.
4536 */
d0bc54f2 4537 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4538 rps = NULL;
4539
8d3afd7d
CW		 4540 spin_lock(&dev_priv->rps.client_lock);
4541 if (rps == NULL || list_empty(&rps->link)) {
4542 spin_lock_irq(&dev_priv->irq_lock);
4543 if (dev_priv->rps.interrupts_enabled) {
4544 dev_priv->rps.client_boost = true;
4545 queue_work(dev_priv->wq, &dev_priv->rps.work);
4546 }
4547 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4548
2e1b8730
CW		 4549 if (rps != NULL) {
4550 list_add(&rps->link, &dev_priv->rps.clients);
4551 rps->boosts++;
1854d5ca
CW		 4552 } else
4553 dev_priv->rps.boosts++;
c0951f0c 4554 }
8d3afd7d 4555 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4556}
4557
ffe02b40 4558void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4559{
666a4537 4560 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4561 valleyview_set_rps(dev, val);
4562 else
4563 gen6_set_rps(dev, val);
0a073b84
JB		 4564}
4565
20e49366
ZW		 4566static void gen9_disable_rps(struct drm_device *dev)
4567{
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569
4570 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4571 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4572}
4573
44fc7d5c 4574static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4575{
4576 struct drm_i915_private *dev_priv = dev->dev_private;
4577
4578 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4579 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4580}
4581
38807746
D		 4582static void cherryview_disable_rps(struct drm_device *dev)
4583{
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585
4586 I915_WRITE(GEN6_RC_CONTROL, 0);
4587}
4588
44fc7d5c
DV		 4589static void valleyview_disable_rps(struct drm_device *dev)
4590{
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592
98a2e5f9
D		 4593 /* we're doing forcewake before Disabling RC6,
4594 * This what the BIOS expects when going into suspend */
59bad947 4595 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4596
44fc7d5c 4597 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4598
59bad947 4599 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4600}
4601
dc39fff7
BW		 4602static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4603{
666a4537 4604 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4605 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4606 mode = GEN6_RC_CTL_RC6_ENABLE;
4607 else
4608 mode = 0;
4609 }
58abf1da
RV		 4610 if (HAS_RC6p(dev))
4611 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4612 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4613 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4614 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4615
4616 else
4617 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4618 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4619}
4620
274008e8
SAK		 4621static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4622{
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4624 bool enable_rc6 = true;
4625 unsigned long rc6_ctx_base;
4626
4627 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4628 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4629 enable_rc6 = false;
4630 }
4631
4632 /*
4633 * The exact context size is not known for BXT, so assume a page size
4634 * for this check.
4635 */
4636 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4637 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4638 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4639 dev_priv->gtt.stolen_reserved_size))) {
4640 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4641 enable_rc6 = false;
4642 }
4643
4644 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4645 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4646 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4647 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4648 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4649 enable_rc6 = false;
4650 }
4651
4652 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4653 GEN6_RC_CTL_HW_ENABLE)) &&
4654 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4655 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4656 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4657 enable_rc6 = false;
4658 }
4659
4660 return enable_rc6;
4661}
4662
4663int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4664{
e7d66d89
DV		 4665 /* No RC6 before Ironlake and code is gone for ilk. */
4666 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4667 return 0;
4668
274008e8
SAK		 4669 if (!enable_rc6)
4670 return 0;
4671
4672 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4673 DRM_INFO("RC6 disabled by BIOS\n");
4674 return 0;
4675 }
4676
456470eb 4677 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4678 if (enable_rc6 >= 0) {
4679 int mask;
4680
58abf1da 4681 if (HAS_RC6p(dev))
e6069ca8
ID		 4682 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4683 INTEL_RC6pp_ENABLE;
4684 else
4685 mask = INTEL_RC6_ENABLE;
4686
4687 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4688 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4689 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4690
4691 return enable_rc6 & mask;
4692 }
2b4e57bd 4693
8bade1ad 4694 if (IS_IVYBRIDGE(dev))
cca84a1f 4695 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4696
4697 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4698}
4699
e6069ca8
ID		 4700int intel_enable_rc6(const struct drm_device *dev)
4701{
4702 return i915.enable_rc6;
4703}
4704
93ee2920 4705static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4706{
93ee2920
TR		 4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 uint32_t rp_state_cap;
4709 u32 ddcc_status = 0;
4710 int ret;
4711
3280e8b0
BW		 4712 /* All of these values are in units of 50MHz */
4713 dev_priv->rps.cur_freq = 0;
93ee2920 4714 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4715 if (IS_BROXTON(dev)) {
4716 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4717 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4718 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4719 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4720 } else {
4721 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4722 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4723 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4724 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4725 }
4726
3280e8b0
BW		 4727 /* hw_max = RP0 until we check for overclocking */
4728 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4729
93ee2920 4730 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4731 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4732 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4733 ret = sandybridge_pcode_read(dev_priv,
4734 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4735 &ddcc_status);
4736 if (0 == ret)
4737 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4738 clamp_t(u8,
4739 ((ddcc_status >> 8) & 0xff),
4740 dev_priv->rps.min_freq,
4741 dev_priv->rps.max_freq);
93ee2920
TR		 4742 }
4743
ef11bdb3 4744 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4745 /* Store the frequency values in 16.66 MHZ units, which is
4746 the natural hardware unit for SKL */
4747 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4748 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4749 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4750 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4751 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4752 }
4753
aed242ff
CW		 4754 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4755
3280e8b0
BW		 4756 /* Preserve min/max settings in case of re-init */
4757 if (dev_priv->rps.max_freq_softlimit == 0)
4758 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4759
93ee2920
TR		 4760 if (dev_priv->rps.min_freq_softlimit == 0) {
4761 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4762 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4763 max_t(int, dev_priv->rps.efficient_freq,
4764 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4765 else
4766 dev_priv->rps.min_freq_softlimit =
4767 dev_priv->rps.min_freq;
4768 }
3280e8b0
BW		 4769}
4770
b6fef0ef 4771/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4772static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4773{
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775
4776 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4777
ba1c554c
DL		 4778 gen6_init_rps_frequencies(dev);
4779
23eafea6 4780 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4781 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4782 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4783 return;
4784 }
4785
0beb059a
AG		 4786 /* Program defaults and thresholds for RPS*/
4787 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4788 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4789
4790 /* 1 second timeout*/
4791 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4792 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4793
b6fef0ef 4794 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4795
0beb059a
AG		 4796 /* Leaning on the below call to gen6_set_rps to program/setup the
4797 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4798 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4799 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4800 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4801
4802 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4803}
4804
4805static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4806{
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_engine_cs *ring;
4809 uint32_t rc6_mask = 0;
4810 int unused;
4811
4812 /* 1a: Software RC state - RC0 */
4813 I915_WRITE(GEN6_RC_STATE, 0);
4814
4815 /* 1b: Get forcewake during program sequence. Although the driver
4816 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4817 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4818
4819 /* 2a: Disable RC states. */
4820 I915_WRITE(GEN6_RC_CONTROL, 0);
4821
4822 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4823
4824 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4825 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4826 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4827 else
4828 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4829 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4830 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4831 for_each_ring(ring, dev_priv, unused)
4832 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4833
4834 if (HAS_GUC_UCODE(dev))
4835 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4836
20e49366 4837 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4838
38c23527
ZW		 4839 /* 2c: Program Coarse Power Gating Policies. */
4840 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4841 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4842
20e49366
ZW		 4843 /* 3a: Enable RC6 */
4844 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4845 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4846 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4847 /* WaRsUseTimeoutMode */
e87a005d 4848 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4849 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4850 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4851 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4852 GEN7_RC_CTL_TO_MODE |
4853 rc6_mask);
3e7732a0
SAK		 4854 } else {
4855 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4856 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4857 GEN6_RC_CTL_EI_MODE(1) |
4858 rc6_mask);
3e7732a0 4859 }
20e49366 4860
cb07bae0
SK		 4861 /*
4862 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4863 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4864 */
06e668ac 4865 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4866 I915_WRITE(GEN9_PG_ENABLE, 0);
4867 else
4868 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4869 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4870
59bad947 4871 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4872
4873}
4874
6edee7f3
BW		 4875static void gen8_enable_rps(struct drm_device *dev)
4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4878 struct intel_engine_cs *ring;
93ee2920 4879 uint32_t rc6_mask = 0;
6edee7f3
BW		 4880 int unused;
4881
4882 /* 1a: Software RC state - RC0 */
4883 I915_WRITE(GEN6_RC_STATE, 0);
4884
4885 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4886 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4887 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4888
4889 /* 2a: Disable RC states. */
4890 I915_WRITE(GEN6_RC_CONTROL, 0);
4891
93ee2920
TR		 4892 /* Initialize rps frequencies */
4893 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4894
4895 /* 2b: Program RC6 thresholds.*/
4896 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4897 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4898 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4899 for_each_ring(ring, dev_priv, unused)
4900 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4901 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4902 if (IS_BROADWELL(dev))
4903 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4904 else
4905 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4906
4907 /* 3: Enable RC6 */
4908 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4909 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4910 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4911 if (IS_BROADWELL(dev))
4912 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4913 GEN7_RC_CTL_TO_MODE |
4914 rc6_mask);
4915 else
4916 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4917 GEN6_RC_CTL_EI_MODE(1) |
4918 rc6_mask);
6edee7f3
BW		 4919
4920 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4921 I915_WRITE(GEN6_RPNSWREQ,
4922 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4923 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4924 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4925 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4926 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4927
4928 /* Docs recommend 900MHz, and 300 MHz respectively */
4929 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4930 dev_priv->rps.max_freq_softlimit << 24 |
4931 dev_priv->rps.min_freq_softlimit << 16);
4932
4933 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4934 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4935 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4936 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4937
4938 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4939
4940 /* 5: Enable RPS */
7526ed79
DV		 4941 I915_WRITE(GEN6_RP_CONTROL,
4942 GEN6_RP_MEDIA_TURBO |
4943 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4944 GEN6_RP_MEDIA_IS_GFX |
4945 GEN6_RP_ENABLE |
4946 GEN6_RP_UP_BUSY_AVG |
4947 GEN6_RP_DOWN_IDLE_AVG);
4948
4949 /* 6: Ring frequency + overclocking (our driver does this later */
4950
c7f3153a 4951 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4952 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4953
59bad947 4954 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4955}
4956
79f5b2c7 4957static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4958{
79f5b2c7 4959 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4960 struct intel_engine_cs *ring;
d060c169 4961 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4962 u32 gtfifodbg;
2b4e57bd 4963 int rc6_mode;
42c0526c 4964 int i, ret;
2b4e57bd 4965
4fc688ce 4966 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4967
2b4e57bd
ED		 4968 /* Here begins a magic sequence of register writes to enable
4969 * auto-downclocking.
4970 *
4971 * Perhaps there might be some value in exposing these to
4972 * userspace...
4973 */
4974 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4975
4976 /* Clear the DBG now so we don't confuse earlier errors */
4977 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4978 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4979 I915_WRITE(GTFIFODBG, gtfifodbg);
4980 }
4981
59bad947 4982 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4983
93ee2920
TR		 4984 /* Initialize rps frequencies */
4985 gen6_init_rps_frequencies(dev);
dd0a1aa1 4986
2b4e57bd
ED		 4987 /* disable the counters and set deterministic thresholds */
4988 I915_WRITE(GEN6_RC_CONTROL, 0);
4989
4990 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4991 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4992 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4993 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4994 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4995
b4519513
CW		 4996 for_each_ring(ring, dev_priv, i)
4997 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4998
4999 I915_WRITE(GEN6_RC_SLEEP, 0);
5000 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5001 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5002 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5003 else
5004 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5005 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5006 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5007
5a7dc92a 5008 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5009 rc6_mode = intel_enable_rc6(dev_priv->dev);
5010 if (rc6_mode & INTEL_RC6_ENABLE)
5011 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5012
5a7dc92a
ED		 5013 /* We don't use those on Haswell */
5014 if (!IS_HASWELL(dev)) {
5015 if (rc6_mode & INTEL_RC6p_ENABLE)
5016 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5017
5a7dc92a
ED		 5018 if (rc6_mode & INTEL_RC6pp_ENABLE)
5019 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5020 }
2b4e57bd 5021
dc39fff7 5022 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5023
5024 I915_WRITE(GEN6_RC_CONTROL,
5025 rc6_mask |
5026 GEN6_RC_CTL_EI_MODE(1) |
5027 GEN6_RC_CTL_HW_ENABLE);
5028
dd75fdc8
CW		 5029 /* Power down if completely idle for over 50ms */
5030 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5031 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5032
42c0526c 5033 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5034 if (ret)
42c0526c 5035 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5036
5037 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5038 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5039 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5040 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5041 (pcu_mbox & 0xff) * 50);
b39fb297 5042 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5043 }
5044
dd75fdc8 5045 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5046 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5047
31643d54
BW		 5048 rc6vids = 0;
5049 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5050 if (IS_GEN6(dev) && ret) {
5051 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5052 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5053 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5054 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5055 rc6vids &= 0xffff00;
5056 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5057 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5058 if (ret)
5059 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5060 }
5061
59bad947 5062 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5063}
5064
c2bc2fc5 5065static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5066{
79f5b2c7 5067 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5068 int min_freq = 15;
3ebecd07
CW		 5069 unsigned int gpu_freq;
5070 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5071 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5072 int scaling_factor = 180;
eda79642 5073 struct cpufreq_policy *policy;
2b4e57bd 5074
4fc688ce 5075 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5076
eda79642
BW		 5077 policy = cpufreq_cpu_get(0);
5078 if (policy) {
5079 max_ia_freq = policy->cpuinfo.max_freq;
5080 cpufreq_cpu_put(policy);
5081 } else {
5082 /*
5083 * Default to measured freq if none found, PCU will ensure we
5084 * don't go over
5085 */
2b4e57bd 5086 max_ia_freq = tsc_khz;
eda79642 5087 }
2b4e57bd
ED		 5088
5089 /* Convert from kHz to MHz */
5090 max_ia_freq /= 1000;
5091
153b4b95 5092 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5093 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5094 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5095
ef11bdb3 5096 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5097 /* Convert GT frequency to 50 HZ units */
5098 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5099 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5100 } else {
5101 min_gpu_freq = dev_priv->rps.min_freq;
5102 max_gpu_freq = dev_priv->rps.max_freq;
5103 }
5104
2b4e57bd
ED		 5105 /*
5106 * For each potential GPU frequency, load a ring frequency we'd like
5107 * to use for memory access. We do this by specifying the IA frequency
5108 * the PCU should use as a reference to determine the ring frequency.
5109 */
4c8c7743
AG		 5110 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5111 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5112 unsigned int ia_freq = 0, ring_freq = 0;
5113
ef11bdb3 5114 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5115 /*
5116 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5117 * No floor required for ring frequency on SKL.
5118 */
5119 ring_freq = gpu_freq;
5120 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5121 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5122 ring_freq = max(min_ring_freq, gpu_freq);
5123 } else if (IS_HASWELL(dev)) {
f6aca45c 5124 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5125 ring_freq = max(min_ring_freq, ring_freq);
5126 /* leave ia_freq as the default, chosen by cpufreq */
5127 } else {
5128 /* On older processors, there is no separate ring
5129 * clock domain, so in order to boost the bandwidth
5130 * of the ring, we need to upclock the CPU (ia_freq).
5131 *
5132 * For GPU frequencies less than 750MHz,
5133 * just use the lowest ring freq.
5134 */
5135 if (gpu_freq < min_freq)
5136 ia_freq = 800;
5137 else
5138 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5139 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5140 }
2b4e57bd 5141
42c0526c
BW		 5142 sandybridge_pcode_write(dev_priv,
5143 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5144 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5145 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5146 gpu_freq);
2b4e57bd 5147 }
2b4e57bd
ED		 5148}
5149
c2bc2fc5
ID		 5150void gen6_update_ring_freq(struct drm_device *dev)
5151{
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153
97d3308a 5154 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5155 return;
5156
5157 mutex_lock(&dev_priv->rps.hw_lock);
5158 __gen6_update_ring_freq(dev);
5159 mutex_unlock(&dev_priv->rps.hw_lock);
5160}
5161
03af2045 5162static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5163{
095acd5f 5164 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5165 u32 val, rp0;
5166
5b5929cb 5167 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5168
5b5929cb
JN		 5169 switch (INTEL_INFO(dev)->eu_total) {
5170 case 8:
5171 /* (2 * 4) config */
5172 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5173 break;
5174 case 12:
5175 /* (2 * 6) config */
5176 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5177 break;
5178 case 16:
5179 /* (2 * 8) config */
5180 default:
5181 /* Setting (2 * 8) Min RP0 for any other combination */
5182 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5183 break;
095acd5f 5184 }
5b5929cb
JN		 5185
5186 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5187
2b6b3a09
D		 5188 return rp0;
5189}
5190
5191static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5192{
5193 u32 val, rpe;
5194
5195 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5196 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5197
5198 return rpe;
5199}
5200
7707df4a
D		 5201static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5202{
5203 u32 val, rp1;
5204
5b5929cb
JN		 5205 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5206 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5207
7707df4a
D		 5208 return rp1;
5209}
5210
f8f2b001
D		 5211static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5212{
5213 u32 val, rp1;
5214
5215 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5216
5217 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5218
5219 return rp1;
5220}
5221
03af2045 5222static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5223{
5224 u32 val, rp0;
5225
64936258 5226 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5227
5228 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5229 /* Clamp to max */
5230 rp0 = min_t(u32, rp0, 0xea);
5231
5232 return rp0;
5233}
5234
5235static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5236{
5237 u32 val, rpe;
5238
64936258 5239 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5240 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5241 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5242 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5243
5244 return rpe;
5245}
5246
03af2045 5247static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5248{
36146035
ID		 5249 u32 val;
5250
5251 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5252 /*
5253 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5254 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5255 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5256 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5257 * to make sure it matches what Punit accepts.
5258 */
5259 return max_t(u32, val, 0xc0);
0a073b84
JB		 5260}
5261
ae48434c
ID		 5262/* Check that the pctx buffer wasn't move under us. */
5263static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5264{
5265 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5266
5267 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5268 dev_priv->vlv_pctx->stolen->start);
5269}
5270
38807746
D		 5271
5272/* Check that the pcbr address is not empty. */
5273static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5274{
5275 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5276
5277 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5278}
5279
5280static void cherryview_setup_pctx(struct drm_device *dev)
5281{
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 unsigned long pctx_paddr, paddr;
5284 struct i915_gtt *gtt = &dev_priv->gtt;
5285 u32 pcbr;
5286 int pctx_size = 32*1024;
5287
38807746
D		 5288 pcbr = I915_READ(VLV_PCBR);
5289 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5290 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5291 paddr = (dev_priv->mm.stolen_base +
5292 (gtt->stolen_size - pctx_size));
5293
5294 pctx_paddr = (paddr & (~4095));
5295 I915_WRITE(VLV_PCBR, pctx_paddr);
5296 }
ce611ef8
VS		 5297
5298 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5299}
5300
c9cddffc
JB		 5301static void valleyview_setup_pctx(struct drm_device *dev)
5302{
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 struct drm_i915_gem_object *pctx;
5305 unsigned long pctx_paddr;
5306 u32 pcbr;
5307 int pctx_size = 24*1024;
5308
ee504898 5309 mutex_lock(&dev->struct_mutex);
17b0c1f7 5310
c9cddffc
JB		 5311 pcbr = I915_READ(VLV_PCBR);
5312 if (pcbr) {
5313 /* BIOS set it up already, grab the pre-alloc'd space */
5314 int pcbr_offset;
5315
5316 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5317 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5318 pcbr_offset,
190d6cd5 5319 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5320 pctx_size);
5321 goto out;
5322 }
5323
ce611ef8
VS		 5324 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5325
c9cddffc
JB		 5326 /*
5327 * From the Gunit register HAS:
5328 * The Gfx driver is expected to program this register and ensure
5329 * proper allocation within Gfx stolen memory. For example, this
5330 * register should be programmed such than the PCBR range does not
5331 * overlap with other ranges, such as the frame buffer, protected
5332 * memory, or any other relevant ranges.
5333 */
5334 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5335 if (!pctx) {
5336 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5337 goto out;
c9cddffc
JB		 5338 }
5339
5340 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5341 I915_WRITE(VLV_PCBR, pctx_paddr);
5342
5343out:
ce611ef8 5344 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5345 dev_priv->vlv_pctx = pctx;
ee504898 5346 mutex_unlock(&dev->struct_mutex);
c9cddffc
JB		 5347}
5348
ae48434c
ID		 5349static void valleyview_cleanup_pctx(struct drm_device *dev)
5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352
5353 if (WARN_ON(!dev_priv->vlv_pctx))
5354 return;
5355
ee504898 5356 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5357 dev_priv->vlv_pctx = NULL;
5358}
5359
4e80519e
ID		 5360static void valleyview_init_gt_powersave(struct drm_device *dev)
5361{
5362 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5363 u32 val;
4e80519e
ID		 5364
5365 valleyview_setup_pctx(dev);
5366
5367 mutex_lock(&dev_priv->rps.hw_lock);
5368
2bb25c17
VS		 5369 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5370 switch ((val >> 6) & 3) {
5371 case 0:
5372 case 1:
5373 dev_priv->mem_freq = 800;
5374 break;
5375 case 2:
5376 dev_priv->mem_freq = 1066;
5377 break;
5378 case 3:
5379 dev_priv->mem_freq = 1333;
5380 break;
5381 }
80b83b62 5382 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5383
4e80519e
ID		 5384 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5385 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5386 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5387 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5388 dev_priv->rps.max_freq);
5389
5390 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5391 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5392 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5393 dev_priv->rps.efficient_freq);
5394
f8f2b001
D		 5395 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5396 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5397 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5398 dev_priv->rps.rp1_freq);
5399
4e80519e
ID		 5400 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5401 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5402 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5403 dev_priv->rps.min_freq);
5404
aed242ff
CW		 5405 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5406
4e80519e
ID		 5407 /* Preserve min/max settings in case of re-init */
5408 if (dev_priv->rps.max_freq_softlimit == 0)
5409 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5410
5411 if (dev_priv->rps.min_freq_softlimit == 0)
5412 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5413
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415}
5416
38807746
D		 5417static void cherryview_init_gt_powersave(struct drm_device *dev)
5418{
2b6b3a09 5419 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5420 u32 val;
2b6b3a09 5421
38807746 5422 cherryview_setup_pctx(dev);
2b6b3a09
D		 5423
5424 mutex_lock(&dev_priv->rps.hw_lock);
5425
a580516d 5426 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5427 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5428 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5429
2bb25c17 5430 switch ((val >> 2) & 0x7) {
2bb25c17 5431 case 3:
2bb25c17
VS		 5432 dev_priv->mem_freq = 2000;
5433 break;
bfa7df01 5434 default:
2bb25c17
VS		 5435 dev_priv->mem_freq = 1600;
5436 break;
5437 }
80b83b62 5438 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5439
2b6b3a09
D		 5440 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5441 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5442 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5443 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5444 dev_priv->rps.max_freq);
5445
5446 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5447 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5448 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5449 dev_priv->rps.efficient_freq);
5450
7707df4a
D		 5451 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5452 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5453 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5454 dev_priv->rps.rp1_freq);
5455
5b7c91b7
D		 5456 /* PUnit validated range is only [RPe, RP0] */
5457 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5458 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5459 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5460 dev_priv->rps.min_freq);
5461
1c14762d
VS		 5462 WARN_ONCE((dev_priv->rps.max_freq |
5463 dev_priv->rps.efficient_freq |
5464 dev_priv->rps.rp1_freq |
5465 dev_priv->rps.min_freq) & 1,
5466 "Odd GPU freq values\n");
5467
aed242ff
CW		 5468 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5469
2b6b3a09
D		 5470 /* Preserve min/max settings in case of re-init */
5471 if (dev_priv->rps.max_freq_softlimit == 0)
5472 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5473
5474 if (dev_priv->rps.min_freq_softlimit == 0)
5475 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5476
5477 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5478}
5479
4e80519e
ID		 5480static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5481{
5482 valleyview_cleanup_pctx(dev);
5483}
5484
38807746
D		 5485static void cherryview_enable_rps(struct drm_device *dev)
5486{
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 struct intel_engine_cs *ring;
2b6b3a09 5489 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5490 int i;
5491
5492 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5493
5494 gtfifodbg = I915_READ(GTFIFODBG);
5495 if (gtfifodbg) {
5496 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5497 gtfifodbg);
5498 I915_WRITE(GTFIFODBG, gtfifodbg);
5499 }
5500
5501 cherryview_check_pctx(dev_priv);
5502
5503 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5504 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5505 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5506
160614a2
VS		 5507 /* Disable RC states. */
5508 I915_WRITE(GEN6_RC_CONTROL, 0);
5509
38807746
D		 5510 /* 2a: Program RC6 thresholds.*/
5511 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5512 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5513 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5514
5515 for_each_ring(ring, dev_priv, i)
5516 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5517 I915_WRITE(GEN6_RC_SLEEP, 0);
5518
f4f71c7d
D		 5519 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5520 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5521
5522 /* allows RC6 residency counter to work */
5523 I915_WRITE(VLV_COUNTER_CONTROL,
5524 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5525 VLV_MEDIA_RC6_COUNT_EN |
5526 VLV_RENDER_RC6_COUNT_EN));
5527
5528 /* For now we assume BIOS is allocating and populating the PCBR */
5529 pcbr = I915_READ(VLV_PCBR);
5530
38807746
D		 5531 /* 3: Enable RC6 */
5532 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5533 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5534 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5535
5536 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5537
2b6b3a09 5538 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5539 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5540 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5541 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5542 I915_WRITE(GEN6_RP_UP_EI, 66000);
5543 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5544
5545 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5546
5547 /* 5: Enable RPS */
5548 I915_WRITE(GEN6_RP_CONTROL,
5549 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5550 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5551 GEN6_RP_ENABLE |
5552 GEN6_RP_UP_BUSY_AVG |
5553 GEN6_RP_DOWN_IDLE_AVG);
5554
3ef62342
D		 5555 /* Setting Fixed Bias */
5556 val = VLV_OVERRIDE_EN |
5557 VLV_SOC_TDP_EN |
5558 CHV_BIAS_CPU_50_SOC_50;
5559 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5560
2b6b3a09
D		 5561 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5562
8d40c3ae
VS		 5563 /* RPS code assumes GPLL is used */
5564 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5565
742f491d 5566 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5567 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5568
5569 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5570 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5571 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5572 dev_priv->rps.cur_freq);
5573
5574 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5575 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5576 dev_priv->rps.efficient_freq);
5577
5578 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5579
59bad947 5580 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5581}
5582
0a073b84
JB		 5583static void valleyview_enable_rps(struct drm_device *dev)
5584{
5585 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5586 struct intel_engine_cs *ring;
2a5913a8 5587 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5588 int i;
5589
5590 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5591
ae48434c
ID		 5592 valleyview_check_pctx(dev_priv);
5593
0a073b84 5594 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5595 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5596 gtfifodbg);
0a073b84
JB		 5597 I915_WRITE(GTFIFODBG, gtfifodbg);
5598 }
5599
c8d9a590 5600 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5601 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5602
160614a2
VS		 5603 /* Disable RC states. */
5604 I915_WRITE(GEN6_RC_CONTROL, 0);
5605
cad725fe 5606 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5607 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5608 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5609 I915_WRITE(GEN6_RP_UP_EI, 66000);
5610 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5611
5612 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5613
5614 I915_WRITE(GEN6_RP_CONTROL,
5615 GEN6_RP_MEDIA_TURBO |
5616 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5617 GEN6_RP_MEDIA_IS_GFX |
5618 GEN6_RP_ENABLE |
5619 GEN6_RP_UP_BUSY_AVG |
5620 GEN6_RP_DOWN_IDLE_CONT);
5621
5622 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5623 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5624 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5625
5626 for_each_ring(ring, dev_priv, i)
5627 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5628
2f0aa304 5629 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5630
5631 /* allows RC6 residency counter to work */
49798eb2 5632 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5633 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5634 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5635 VLV_MEDIA_RC6_COUNT_EN |
5636 VLV_RENDER_RC6_COUNT_EN));
31685c25 5637
a2b23fe0 5638 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5639 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5640
5641 intel_print_rc6_info(dev, rc6_mode);
5642
a2b23fe0 5643 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5644
3ef62342
D		 5645 /* Setting Fixed Bias */
5646 val = VLV_OVERRIDE_EN |
5647 VLV_SOC_TDP_EN |
5648 VLV_BIAS_CPU_125_SOC_875;
5649 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5650
64936258 5651 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5652
8d40c3ae
VS		 5653 /* RPS code assumes GPLL is used */
5654 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5655
742f491d 5656 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5657 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5658
b39fb297 5659 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5660 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5661 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5662 dev_priv->rps.cur_freq);
0a073b84 5663
73008b98 5664 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5665 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5666 dev_priv->rps.efficient_freq);
0a073b84 5667
b39fb297 5668 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5669
59bad947 5670 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5671}
5672
dde18883
ED		 5673static unsigned long intel_pxfreq(u32 vidfreq)
5674{
5675 unsigned long freq;
5676 int div = (vidfreq & 0x3f0000) >> 16;
5677 int post = (vidfreq & 0x3000) >> 12;
5678 int pre = (vidfreq & 0x7);
5679
5680 if (!pre)
5681 return 0;
5682
5683 freq = ((div * 133333) / ((1<<post) * pre));
5684
5685 return freq;
5686}
5687
eb48eb00
DV		 5688static const struct cparams {
5689 u16 i;
5690 u16 t;
5691 u16 m;
5692 u16 c;
5693} cparams[] = {
5694 { 1, 1333, 301, 28664 },
5695 { 1, 1066, 294, 24460 },
5696 { 1, 800, 294, 25192 },
5697 { 0, 1333, 276, 27605 },
5698 { 0, 1066, 276, 27605 },
5699 { 0, 800, 231, 23784 },
5700};
5701
f531dcb2 5702static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5703{
5704 u64 total_count, diff, ret;
5705 u32 count1, count2, count3, m = 0, c = 0;
5706 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5707 int i;
5708
02d71956
DV		 5709 assert_spin_locked(&mchdev_lock);
5710
20e4d407 5711 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5712
5713 /* Prevent division-by-zero if we are asking too fast.
5714 * Also, we don't get interesting results if we are polling
5715 * faster than once in 10ms, so just return the saved value
5716 * in such cases.
5717 */
5718 if (diff1 <= 10)
20e4d407 5719 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5720
5721 count1 = I915_READ(DMIEC);
5722 count2 = I915_READ(DDREC);
5723 count3 = I915_READ(CSIEC);
5724
5725 total_count = count1 + count2 + count3;
5726
5727 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5728 if (total_count < dev_priv->ips.last_count1) {
5729 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5730 diff += total_count;
5731 } else {
20e4d407 5732 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5733 }
5734
5735 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5736 if (cparams[i].i == dev_priv->ips.c_m &&
5737 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5738 m = cparams[i].m;
5739 c = cparams[i].c;
5740 break;
5741 }
5742 }
5743
5744 diff = div_u64(diff, diff1);
5745 ret = ((m * diff) + c);
5746 ret = div_u64(ret, 10);
5747
20e4d407
DV		 5748 dev_priv->ips.last_count1 = total_count;
5749 dev_priv->ips.last_time1 = now;
eb48eb00 5750
20e4d407 5751 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5752
5753 return ret;
5754}
5755
f531dcb2
CW		 5756unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5757{
3d13ef2e 5758 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5759 unsigned long val;
5760
3d13ef2e 5761 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5762 return 0;
5763
5764 spin_lock_irq(&mchdev_lock);
5765
5766 val = __i915_chipset_val(dev_priv);
5767
5768 spin_unlock_irq(&mchdev_lock);
5769
5770 return val;
5771}
5772
eb48eb00
DV		 5773unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5774{
5775 unsigned long m, x, b;
5776 u32 tsfs;
5777
5778 tsfs = I915_READ(TSFS);
5779
5780 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5781 x = I915_READ8(TR1);
5782
5783 b = tsfs & TSFS_INTR_MASK;
5784
5785 return ((m * x) / 127) - b;
5786}
5787
d972d6ee
MK		 5788static int _pxvid_to_vd(u8 pxvid)
5789{
5790 if (pxvid == 0)
5791 return 0;
5792
5793 if (pxvid >= 8 && pxvid < 31)
5794 pxvid = 31;
5795
5796 return (pxvid + 2) * 125;
5797}
5798
5799static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5800{
3d13ef2e 5801 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5802 const int vd = _pxvid_to_vd(pxvid);
5803 const int vm = vd - 1125;
5804
3d13ef2e 5805 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5806 return vm > 0 ? vm : 0;
5807
5808 return vd;
eb48eb00
DV		 5809}
5810
02d71956 5811static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5812{
5ed0bdf2 5813 u64 now, diff, diffms;
eb48eb00
DV		 5814 u32 count;
5815
02d71956 5816 assert_spin_locked(&mchdev_lock);
eb48eb00 5817
5ed0bdf2
TG		 5818 now = ktime_get_raw_ns();
5819 diffms = now - dev_priv->ips.last_time2;
5820 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5821
5822 /* Don't divide by 0 */
eb48eb00
DV		 5823 if (!diffms)
5824 return;
5825
5826 count = I915_READ(GFXEC);
5827
20e4d407
DV		 5828 if (count < dev_priv->ips.last_count2) {
5829 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5830 diff += count;
5831 } else {
20e4d407 5832 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5833 }
5834
20e4d407
DV		 5835 dev_priv->ips.last_count2 = count;
5836 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5837
5838 /* More magic constants... */
5839 diff = diff * 1181;
5840 diff = div_u64(diff, diffms * 10);
20e4d407 5841 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5842}
5843
02d71956
DV		 5844void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5845{
3d13ef2e
DL		 5846 struct drm_device *dev = dev_priv->dev;
5847
5848 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5849 return;
5850
9270388e 5851 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5852
5853 __i915_update_gfx_val(dev_priv);
5854
9270388e 5855 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5856}
5857
f531dcb2 5858static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5859{
5860 unsigned long t, corr, state1, corr2, state2;
5861 u32 pxvid, ext_v;
5862
02d71956
DV		 5863 assert_spin_locked(&mchdev_lock);
5864
616847e7 5865 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5866 pxvid = (pxvid >> 24) & 0x7f;
5867 ext_v = pvid_to_extvid(dev_priv, pxvid);
5868
5869 state1 = ext_v;
5870
5871 t = i915_mch_val(dev_priv);
5872
5873 /* Revel in the empirically derived constants */
5874
5875 /* Correction factor in 1/100000 units */
5876 if (t > 80)
5877 corr = ((t * 2349) + 135940);
5878 else if (t >= 50)
5879 corr = ((t * 964) + 29317);
5880 else /* < 50 */
5881 corr = ((t * 301) + 1004);
5882
5883 corr = corr * ((150142 * state1) / 10000 - 78642);
5884 corr /= 100000;
20e4d407 5885 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5886
5887 state2 = (corr2 * state1) / 10000;
5888 state2 /= 100; /* convert to mW */
5889
02d71956 5890 __i915_update_gfx_val(dev_priv);
eb48eb00 5891
20e4d407 5892 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5893}
5894
f531dcb2
CW		 5895unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5896{
3d13ef2e 5897 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5898 unsigned long val;
5899
3d13ef2e 5900 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5901 return 0;
5902
5903 spin_lock_irq(&mchdev_lock);
5904
5905 val = __i915_gfx_val(dev_priv);
5906
5907 spin_unlock_irq(&mchdev_lock);
5908
5909 return val;
5910}
5911
eb48eb00
DV		 5912/**
5913 * i915_read_mch_val - return value for IPS use
5914 *
5915 * Calculate and return a value for the IPS driver to use when deciding whether
5916 * we have thermal and power headroom to increase CPU or GPU power budget.
5917 */
5918unsigned long i915_read_mch_val(void)
5919{
5920 struct drm_i915_private *dev_priv;
5921 unsigned long chipset_val, graphics_val, ret = 0;
5922
9270388e 5923 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5924 if (!i915_mch_dev)
5925 goto out_unlock;
5926 dev_priv = i915_mch_dev;
5927
f531dcb2
CW		 5928 chipset_val = __i915_chipset_val(dev_priv);
5929 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5930
5931 ret = chipset_val + graphics_val;
5932
5933out_unlock:
9270388e 5934 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5935
5936 return ret;
5937}
5938EXPORT_SYMBOL_GPL(i915_read_mch_val);
5939
5940/**
5941 * i915_gpu_raise - raise GPU frequency limit
5942 *
5943 * Raise the limit; IPS indicates we have thermal headroom.
5944 */
5945bool i915_gpu_raise(void)
5946{
5947 struct drm_i915_private *dev_priv;
5948 bool ret = true;
5949
9270388e 5950 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5951 if (!i915_mch_dev) {
5952 ret = false;
5953 goto out_unlock;
5954 }
5955 dev_priv = i915_mch_dev;
5956
20e4d407
DV		 5957 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5958 dev_priv->ips.max_delay--;
eb48eb00
DV		 5959
5960out_unlock:
9270388e 5961 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5962
5963 return ret;
5964}
5965EXPORT_SYMBOL_GPL(i915_gpu_raise);
5966
5967/**
5968 * i915_gpu_lower - lower GPU frequency limit
5969 *
5970 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5971 * frequency maximum.
5972 */
5973bool i915_gpu_lower(void)
5974{
5975 struct drm_i915_private *dev_priv;
5976 bool ret = true;
5977
9270388e 5978 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5979 if (!i915_mch_dev) {
5980 ret = false;
5981 goto out_unlock;
5982 }
5983 dev_priv = i915_mch_dev;
5984
20e4d407
DV		 5985 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5986 dev_priv->ips.max_delay++;
eb48eb00
DV		 5987
5988out_unlock:
9270388e 5989 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5990
5991 return ret;
5992}
5993EXPORT_SYMBOL_GPL(i915_gpu_lower);
5994
5995/**
5996 * i915_gpu_busy - indicate GPU business to IPS
5997 *
5998 * Tell the IPS driver whether or not the GPU is busy.
5999 */
6000bool i915_gpu_busy(void)
6001{
6002 struct drm_i915_private *dev_priv;
a4872ba6 6003 struct intel_engine_cs *ring;
eb48eb00 6004 bool ret = false;
f047e395 6005 int i;
eb48eb00 6006
9270388e 6007 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6008 if (!i915_mch_dev)
6009 goto out_unlock;
6010 dev_priv = i915_mch_dev;
6011
f047e395
CW		 6012 for_each_ring(ring, dev_priv, i)
6013 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 6014
6015out_unlock:
9270388e 6016 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6017
6018 return ret;
6019}
6020EXPORT_SYMBOL_GPL(i915_gpu_busy);
6021
6022/**
6023 * i915_gpu_turbo_disable - disable graphics turbo
6024 *
6025 * Disable graphics turbo by resetting the max frequency and setting the
6026 * current frequency to the default.
6027 */
6028bool i915_gpu_turbo_disable(void)
6029{
6030 struct drm_i915_private *dev_priv;
6031 bool ret = true;
6032
9270388e 6033 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6034 if (!i915_mch_dev) {
6035 ret = false;
6036 goto out_unlock;
6037 }
6038 dev_priv = i915_mch_dev;
6039
20e4d407 6040 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6041
20e4d407 6042 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6043 ret = false;
6044
6045out_unlock:
9270388e 6046 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6047
6048 return ret;
6049}
6050EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6051
6052/**
6053 * Tells the intel_ips driver that the i915 driver is now loaded, if
6054 * IPS got loaded first.
6055 *
6056 * This awkward dance is so that neither module has to depend on the
6057 * other in order for IPS to do the appropriate communication of
6058 * GPU turbo limits to i915.
6059 */
6060static void
6061ips_ping_for_i915_load(void)
6062{
6063 void (*link)(void);
6064
6065 link = symbol_get(ips_link_to_i915_driver);
6066 if (link) {
6067 link();
6068 symbol_put(ips_link_to_i915_driver);
6069 }
6070}
6071
6072void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6073{
02d71956
DV		 6074 /* We only register the i915 ips part with intel-ips once everything is
6075 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6076 spin_lock_irq(&mchdev_lock);
eb48eb00 6077 i915_mch_dev = dev_priv;
9270388e 6078 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6079
6080 ips_ping_for_i915_load();
6081}
6082
6083void intel_gpu_ips_teardown(void)
6084{
9270388e 6085 spin_lock_irq(&mchdev_lock);
eb48eb00 6086 i915_mch_dev = NULL;
9270388e 6087 spin_unlock_irq(&mchdev_lock);
eb48eb00 6088}
76c3552f 6089
8090c6b9 6090static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6091{
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 u32 lcfuse;
6094 u8 pxw[16];
6095 int i;
6096
6097 /* Disable to program */
6098 I915_WRITE(ECR, 0);
6099 POSTING_READ(ECR);
6100
6101 /* Program energy weights for various events */
6102 I915_WRITE(SDEW, 0x15040d00);
6103 I915_WRITE(CSIEW0, 0x007f0000);
6104 I915_WRITE(CSIEW1, 0x1e220004);
6105 I915_WRITE(CSIEW2, 0x04000004);
6106
6107 for (i = 0; i < 5; i++)
616847e7 6108 I915_WRITE(PEW(i), 0);
dde18883 6109 for (i = 0; i < 3; i++)
616847e7 6110 I915_WRITE(DEW(i), 0);
dde18883
ED		 6111
6112 /* Program P-state weights to account for frequency power adjustment */
6113 for (i = 0; i < 16; i++) {
616847e7 6114 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6115 unsigned long freq = intel_pxfreq(pxvidfreq);
6116 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6117 PXVFREQ_PX_SHIFT;
6118 unsigned long val;
6119
6120 val = vid * vid;
6121 val *= (freq / 1000);
6122 val *= 255;
6123 val /= (127*127*900);
6124 if (val > 0xff)
6125 DRM_ERROR("bad pxval: %ld\n", val);
6126 pxw[i] = val;
6127 }
6128 /* Render standby states get 0 weight */
6129 pxw[14] = 0;
6130 pxw[15] = 0;
6131
6132 for (i = 0; i < 4; i++) {
6133 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6134 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6135 I915_WRITE(PXW(i), val);
dde18883
ED		 6136 }
6137
6138 /* Adjust magic regs to magic values (more experimental results) */
6139 I915_WRITE(OGW0, 0);
6140 I915_WRITE(OGW1, 0);
6141 I915_WRITE(EG0, 0x00007f00);
6142 I915_WRITE(EG1, 0x0000000e);
6143 I915_WRITE(EG2, 0x000e0000);
6144 I915_WRITE(EG3, 0x68000300);
6145 I915_WRITE(EG4, 0x42000000);
6146 I915_WRITE(EG5, 0x00140031);
6147 I915_WRITE(EG6, 0);
6148 I915_WRITE(EG7, 0);
6149
6150 for (i = 0; i < 8; i++)
616847e7 6151 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6152
6153 /* Enable PMON + select events */
6154 I915_WRITE(ECR, 0x80000019);
6155
6156 lcfuse = I915_READ(LCFUSE02);
6157
20e4d407 6158 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6159}
6160
ae48434c
ID		 6161void intel_init_gt_powersave(struct drm_device *dev)
6162{
b268c699
ID		 6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164
b268c699
ID		 6165 /*
6166 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6167 * requirement.
6168 */
6169 if (!i915.enable_rc6) {
6170 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6171 intel_runtime_pm_get(dev_priv);
6172 }
e6069ca8 6173
38807746
D		 6174 if (IS_CHERRYVIEW(dev))
6175 cherryview_init_gt_powersave(dev);
6176 else if (IS_VALLEYVIEW(dev))
4e80519e 6177 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6178}
6179
6180void intel_cleanup_gt_powersave(struct drm_device *dev)
6181{
b268c699
ID		 6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183
38807746
D		 6184 if (IS_CHERRYVIEW(dev))
6185 return;
6186 else if (IS_VALLEYVIEW(dev))
4e80519e 6187 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6188
6189 if (!i915.enable_rc6)
6190 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6191}
6192
dbea3cea
ID		 6193static void gen6_suspend_rps(struct drm_device *dev)
6194{
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196
6197 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6198
4c2a8897 6199 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6200}
6201
156c7ca0
JB		 6202/**
6203 * intel_suspend_gt_powersave - suspend PM work and helper threads
6204 * @dev: drm device
6205 *
6206 * We don't want to disable RC6 or other features here, we just want
6207 * to make sure any work we've queued has finished and won't bother
6208 * us while we're suspended.
6209 */
6210void intel_suspend_gt_powersave(struct drm_device *dev)
6211{
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213
d4d70aa5
ID		 6214 if (INTEL_INFO(dev)->gen < 6)
6215 return;
6216
dbea3cea 6217 gen6_suspend_rps(dev);
b47adc17
D		 6218
6219 /* Force GPU to min freq during suspend */
6220 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6221}
6222
8090c6b9
DV		 6223void intel_disable_gt_powersave(struct drm_device *dev)
6224{
1a01ab3b
JB		 6225 struct drm_i915_private *dev_priv = dev->dev_private;
6226
930ebb46 6227 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6228 ironlake_disable_drps(dev);
38807746 6229 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6230 intel_suspend_gt_powersave(dev);
e494837a 6231
4fc688ce 6232 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6233 if (INTEL_INFO(dev)->gen >= 9)
6234 gen9_disable_rps(dev);
6235 else if (IS_CHERRYVIEW(dev))
38807746
D		 6236 cherryview_disable_rps(dev);
6237 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6238 valleyview_disable_rps(dev);
6239 else
6240 gen6_disable_rps(dev);
e534770a 6241
c0951f0c 6242 dev_priv->rps.enabled = false;
4fc688ce 6243 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6244 }
8090c6b9
DV		 6245}
6246
1a01ab3b
JB		 6247static void intel_gen6_powersave_work(struct work_struct *work)
6248{
6249 struct drm_i915_private *dev_priv =
6250 container_of(work, struct drm_i915_private,
6251 rps.delayed_resume_work.work);
6252 struct drm_device *dev = dev_priv->dev;
6253
4fc688ce 6254 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6255
4c2a8897 6256 gen6_reset_rps_interrupts(dev);
3cc134e3 6257
38807746
D		 6258 if (IS_CHERRYVIEW(dev)) {
6259 cherryview_enable_rps(dev);
6260 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6261 valleyview_enable_rps(dev);
20e49366 6262 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6263 gen9_enable_rc6(dev);
20e49366 6264 gen9_enable_rps(dev);
ef11bdb3 6265 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6266 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6267 } else if (IS_BROADWELL(dev)) {
6268 gen8_enable_rps(dev);
c2bc2fc5 6269 __gen6_update_ring_freq(dev);
0a073b84
JB		 6270 } else {
6271 gen6_enable_rps(dev);
c2bc2fc5 6272 __gen6_update_ring_freq(dev);
0a073b84 6273 }
aed242ff
CW		 6274
6275 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6276 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6277
6278 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6279 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6280
c0951f0c 6281 dev_priv->rps.enabled = true;
3cc134e3 6282
4c2a8897 6283 gen6_enable_rps_interrupts(dev);
3cc134e3 6284
4fc688ce 6285 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6286
6287 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6288}
6289
8090c6b9
DV		 6290void intel_enable_gt_powersave(struct drm_device *dev)
6291{
1a01ab3b
JB		 6292 struct drm_i915_private *dev_priv = dev->dev_private;
6293
f61018b1
YZ		 6294 /* Powersaving is controlled by the host when inside a VM */
6295 if (intel_vgpu_active(dev))
6296 return;
6297
8090c6b9
DV		 6298 if (IS_IRONLAKE_M(dev)) {
6299 ironlake_enable_drps(dev);
84f1b20f 6300 mutex_lock(&dev->struct_mutex);
8090c6b9 6301 intel_init_emon(dev);
dc1d0136 6302 mutex_unlock(&dev->struct_mutex);
38807746 6303 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6304 /*
6305 * PCU communication is slow and this doesn't need to be
6306 * done at any specific time, so do this out of our fast path
6307 * to make resume and init faster.
c6df39b5
ID		 6308 *
6309 * We depend on the HW RC6 power context save/restore
6310 * mechanism when entering D3 through runtime PM suspend. So
6311 * disable RPM until RPS/RC6 is properly setup. We can only
6312 * get here via the driver load/system resume/runtime resume
6313 * paths, so the _noresume version is enough (and in case of
6314 * runtime resume it's necessary).
1a01ab3b 6315 */
c6df39b5
ID		 6316 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6317 round_jiffies_up_relative(HZ)))
6318 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6319 }
6320}
6321
c6df39b5
ID		 6322void intel_reset_gt_powersave(struct drm_device *dev)
6323{
6324 struct drm_i915_private *dev_priv = dev->dev_private;
6325
dbea3cea
ID		 6326 if (INTEL_INFO(dev)->gen < 6)
6327 return;
6328
6329 gen6_suspend_rps(dev);
c6df39b5 6330 dev_priv->rps.enabled = false;
c6df39b5
ID		 6331}
6332
3107bd48
DV		 6333static void ibx_init_clock_gating(struct drm_device *dev)
6334{
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336
6337 /*
6338 * On Ibex Peak and Cougar Point, we need to disable clock
6339 * gating for the panel power sequencer or it will fail to
6340 * start up when no ports are active.
6341 */
6342 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6343}
6344
0e088b8f
VS		 6345static void g4x_disable_trickle_feed(struct drm_device *dev)
6346{
6347 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6348 enum pipe pipe;
0e088b8f 6349
055e393f 6350 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6351 I915_WRITE(DSPCNTR(pipe),
6352 I915_READ(DSPCNTR(pipe)) |
6353 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6354
6355 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6356 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6357 }
6358}
6359
017636cc
VS		 6360static void ilk_init_lp_watermarks(struct drm_device *dev)
6361{
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363
6364 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6365 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6366 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6367
6368 /*
6369 * Don't touch WM1S_LP_EN here.
6370 * Doing so could cause underruns.
6371 */
6372}
6373
1fa61106 6374static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6375{
6376 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6377 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6378
f1e8fa56
DL		 6379 /*
6380 * Required for FBC
6381 * WaFbcDisableDpfcClockGating:ilk
6382 */
4d47e4f5
DL		 6383 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6384 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6385 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6386
6387 I915_WRITE(PCH_3DCGDIS0,
6388 MARIUNIT_CLOCK_GATE_DISABLE |
6389 SVSMUNIT_CLOCK_GATE_DISABLE);
6390 I915_WRITE(PCH_3DCGDIS1,
6391 VFMUNIT_CLOCK_GATE_DISABLE);
6392
6f1d69b0
ED		 6393 /*
6394 * According to the spec the following bits should be set in
6395 * order to enable memory self-refresh
6396 * The bit 22/21 of 0x42004
6397 * The bit 5 of 0x42020
6398 * The bit 15 of 0x45000
6399 */
6400 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6401 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6402 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6403 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6404 I915_WRITE(DISP_ARB_CTL,
6405 (I915_READ(DISP_ARB_CTL) |
6406 DISP_FBC_WM_DIS));
017636cc
VS		 6407
6408 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6409
6410 /*
6411 * Based on the document from hardware guys the following bits
6412 * should be set unconditionally in order to enable FBC.
6413 * The bit 22 of 0x42000
6414 * The bit 22 of 0x42004
6415 * The bit 7,8,9 of 0x42020.
6416 */
6417 if (IS_IRONLAKE_M(dev)) {
4bb35334 6418 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6419 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6420 I915_READ(ILK_DISPLAY_CHICKEN1) |
6421 ILK_FBCQ_DIS);
6422 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6423 I915_READ(ILK_DISPLAY_CHICKEN2) |
6424 ILK_DPARB_GATE);
6f1d69b0
ED		 6425 }
6426
4d47e4f5
DL		 6427 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6428
6f1d69b0
ED		 6429 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6430 I915_READ(ILK_DISPLAY_CHICKEN2) |
6431 ILK_ELPIN_409_SELECT);
6432 I915_WRITE(_3D_CHICKEN2,
6433 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6434 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6435
ecdb4eb7 6436 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6437 I915_WRITE(CACHE_MODE_0,
6438 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6439
4e04632e
AG		 6440 /* WaDisable_RenderCache_OperationalFlush:ilk */
6441 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6442
0e088b8f 6443 g4x_disable_trickle_feed(dev);
bdad2b2f 6444
3107bd48
DV		 6445 ibx_init_clock_gating(dev);
6446}
6447
6448static void cpt_init_clock_gating(struct drm_device *dev)
6449{
6450 struct drm_i915_private *dev_priv = dev->dev_private;
6451 int pipe;
3f704fa2 6452 uint32_t val;
3107bd48
DV		 6453
6454 /*
6455 * On Ibex Peak and Cougar Point, we need to disable clock
6456 * gating for the panel power sequencer or it will fail to
6457 * start up when no ports are active.
6458 */
cd664078
JB		 6459 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6460 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6461 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6462 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6463 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6464 /* The below fixes the weird display corruption, a few pixels shifted
6465 * downward, on (only) LVDS of some HP laptops with IVY.
6466 */
055e393f 6467 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6468 val = I915_READ(TRANS_CHICKEN2(pipe));
6469 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6470 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6471 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6472 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6473 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6474 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6475 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6476 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6477 }
3107bd48 6478 /* WADP0ClockGatingDisable */
055e393f 6479 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6480 I915_WRITE(TRANS_CHICKEN1(pipe),
6481 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6482 }
6f1d69b0
ED		 6483}
6484
1d7aaa0c
DV		 6485static void gen6_check_mch_setup(struct drm_device *dev)
6486{
6487 struct drm_i915_private *dev_priv = dev->dev_private;
6488 uint32_t tmp;
6489
6490 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6491 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6492 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6493 tmp);
1d7aaa0c
DV		 6494}
6495
1fa61106 6496static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6497{
6498 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6499 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6500
231e54f6 6501 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6502
6503 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6504 I915_READ(ILK_DISPLAY_CHICKEN2) |
6505 ILK_ELPIN_409_SELECT);
6506
ecdb4eb7 6507 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6508 I915_WRITE(_3D_CHICKEN,
6509 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6510
4e04632e
AG		 6511 /* WaDisable_RenderCache_OperationalFlush:snb */
6512 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6513
8d85d272
VS		 6514 /*
6515 * BSpec recoomends 8x4 when MSAA is used,
6516 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6517 *
6518 * Note that PS/WM thread counts depend on the WIZ hashing
6519 * disable bit, which we don't touch here, but it's good
6520 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6521 */
6522 I915_WRITE(GEN6_GT_MODE,
98533251 6523 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6524
017636cc 6525 ilk_init_lp_watermarks(dev);
6f1d69b0 6526
6f1d69b0 6527 I915_WRITE(CACHE_MODE_0,
50743298 6528 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6529
6530 I915_WRITE(GEN6_UCGCTL1,
6531 I915_READ(GEN6_UCGCTL1) |
6532 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6533 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6534
6535 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6536 * gating disable must be set. Failure to set it results in
6537 * flickering pixels due to Z write ordering failures after
6538 * some amount of runtime in the Mesa "fire" demo, and Unigine
6539 * Sanctuary and Tropics, and apparently anything else with
6540 * alpha test or pixel discard.
6541 *
6542 * According to the spec, bit 11 (RCCUNIT) must also be set,
6543 * but we didn't debug actual testcases to find it out.
0f846f81 6544 *
ef59318c
VS		 6545 * WaDisableRCCUnitClockGating:snb
6546 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6547 */
6548 I915_WRITE(GEN6_UCGCTL2,
6549 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6550 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6551
5eb146dd 6552 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6553 I915_WRITE(_3D_CHICKEN3,
6554 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6555
e927ecde
VS		 6556 /*
6557 * Bspec says:
6558 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6559 * 3DSTATE_SF number of SF output attributes is more than 16."
6560 */
6561 I915_WRITE(_3D_CHICKEN3,
6562 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6563
6f1d69b0
ED		 6564 /*
6565 * According to the spec the following bits should be
6566 * set in order to enable memory self-refresh and fbc:
6567 * The bit21 and bit22 of 0x42000
6568 * The bit21 and bit22 of 0x42004
6569 * The bit5 and bit7 of 0x42020
6570 * The bit14 of 0x70180
6571 * The bit14 of 0x71180
4bb35334
DL		 6572 *
6573 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6574 */
6575 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6576 I915_READ(ILK_DISPLAY_CHICKEN1) |
6577 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6578 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6579 I915_READ(ILK_DISPLAY_CHICKEN2) |
6580 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6581 I915_WRITE(ILK_DSPCLK_GATE_D,
6582 I915_READ(ILK_DSPCLK_GATE_D) |
6583 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6584 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6585
0e088b8f 6586 g4x_disable_trickle_feed(dev);
f8f2ac9a 6587
3107bd48 6588 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6589
6590 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6591}
6592
6593static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6594{
6595 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6596
3aad9059 6597 /*
46680e0a 6598 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6599 *
6600 * This actually overrides the dispatch
6601 * mode for all thread types.
6602 */
6f1d69b0
ED		 6603 reg &= ~GEN7_FF_SCHED_MASK;
6604 reg |= GEN7_FF_TS_SCHED_HW;
6605 reg |= GEN7_FF_VS_SCHED_HW;
6606 reg |= GEN7_FF_DS_SCHED_HW;
6607
6608 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6609}
6610
17a303ec
PZ		 6611static void lpt_init_clock_gating(struct drm_device *dev)
6612{
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614
6615 /*
6616 * TODO: this bit should only be enabled when really needed, then
6617 * disabled when not needed anymore in order to save power.
6618 */
c2699524 6619 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6620 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6621 I915_READ(SOUTH_DSPCLK_GATE_D) |
6622 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6623
6624 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6625 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6626 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6627 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6628}
6629
7d708ee4
ID		 6630static void lpt_suspend_hw(struct drm_device *dev)
6631{
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633
c2699524 6634 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6635 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6636
6637 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6638 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6639 }
6640}
6641
47c2bd97 6642static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6643{
6644 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6645 enum pipe pipe;
4d487cff 6646 uint32_t misccpctl;
1020a5c2 6647
7ad0dbab 6648 ilk_init_lp_watermarks(dev);
50ed5fbd 6649
ab57fff1 6650 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6651 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6652
ab57fff1 6653 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6654 I915_WRITE(CHICKEN_PAR1_1,
6655 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6656
ab57fff1 6657 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6658 for_each_pipe(dev_priv, pipe) {
07d27e20 6659 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6660 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6661 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6662 }
63801f21 6663
ab57fff1
BW		 6664 /* WaVSRefCountFullforceMissDisable:bdw */
6665 /* WaDSRefCountFullforceMissDisable:bdw */
6666 I915_WRITE(GEN7_FF_THREAD_MODE,
6667 I915_READ(GEN7_FF_THREAD_MODE) &
6668 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6669
295e8bb7
VS		 6670 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6671 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6672
6673 /* WaDisableSDEUnitClockGating:bdw */
6674 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6675 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6676
4d487cff
VS		 6677 /*
6678 * WaProgramL3SqcReg1Default:bdw
6679 * WaTempDisableDOPClkGating:bdw
6680 */
6681 misccpctl = I915_READ(GEN7_MISCCPCTL);
6682 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6683 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6684 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6685
6d50b065
VS		 6686 /*
6687 * WaGttCachingOffByDefault:bdw
6688 * GTT cache may not work with big pages, so if those
6689 * are ever enabled GTT cache may need to be disabled.
6690 */
6691 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6692
89d6b2b8 6693 lpt_init_clock_gating(dev);
1020a5c2
BW		 6694}
6695
cad2a2d7
ED		 6696static void haswell_init_clock_gating(struct drm_device *dev)
6697{
6698 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6699
017636cc 6700 ilk_init_lp_watermarks(dev);
cad2a2d7 6701
f3fc4884
FJ		 6702 /* L3 caching of data atomics doesn't work -- disable it. */
6703 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6704 I915_WRITE(HSW_ROW_CHICKEN3,
6705 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6706
ecdb4eb7 6707 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6708 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6709 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6710 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6711
e36ea7ff
VS		 6712 /* WaVSRefCountFullforceMissDisable:hsw */
6713 I915_WRITE(GEN7_FF_THREAD_MODE,
6714 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6715
4e04632e
AG		 6716 /* WaDisable_RenderCache_OperationalFlush:hsw */
6717 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6718
fe27c606
CW		 6719 /* enable HiZ Raw Stall Optimization */
6720 I915_WRITE(CACHE_MODE_0_GEN7,
6721 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6722
ecdb4eb7 6723 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6724 I915_WRITE(CACHE_MODE_1,
6725 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6726
a12c4967
VS		 6727 /*
6728 * BSpec recommends 8x4 when MSAA is used,
6729 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6730 *
6731 * Note that PS/WM thread counts depend on the WIZ hashing
6732 * disable bit, which we don't touch here, but it's good
6733 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6734 */
6735 I915_WRITE(GEN7_GT_MODE,
98533251 6736 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6737
94411593
KG		 6738 /* WaSampleCChickenBitEnable:hsw */
6739 I915_WRITE(HALF_SLICE_CHICKEN3,
6740 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6741
ecdb4eb7 6742 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6743 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6744
90a88643
PZ		 6745 /* WaRsPkgCStateDisplayPMReq:hsw */
6746 I915_WRITE(CHICKEN_PAR1_1,
6747 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6748
17a303ec 6749 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6750}
6751
1fa61106 6752static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6753{
6754 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6755 uint32_t snpcr;
6f1d69b0 6756
017636cc 6757 ilk_init_lp_watermarks(dev);
6f1d69b0 6758
231e54f6 6759 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6760
ecdb4eb7 6761 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6762 I915_WRITE(_3D_CHICKEN3,
6763 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6764
ecdb4eb7 6765 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6766 I915_WRITE(IVB_CHICKEN3,
6767 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6768 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6769
ecdb4eb7 6770 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6771 if (IS_IVB_GT1(dev))
6772 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6773 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6774
4e04632e
AG		 6775 /* WaDisable_RenderCache_OperationalFlush:ivb */
6776 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6777
ecdb4eb7 6778 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6779 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6780 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6781
ecdb4eb7 6782 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6783 I915_WRITE(GEN7_L3CNTLREG1,
6784 GEN7_WA_FOR_GEN7_L3_CONTROL);
6785 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6786 GEN7_WA_L3_CHICKEN_MODE);
6787 if (IS_IVB_GT1(dev))
6788 I915_WRITE(GEN7_ROW_CHICKEN2,
6789 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6790 else {
6791 /* must write both registers */
6792 I915_WRITE(GEN7_ROW_CHICKEN2,
6793 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6794 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6795 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6796 }
6f1d69b0 6797
ecdb4eb7 6798 /* WaForceL3Serialization:ivb */
61939d97
JB		 6799 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6800 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6801
1b80a19a 6802 /*
0f846f81 6803 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6804 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6805 */
6806 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6807 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6808
ecdb4eb7 6809 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6810 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6811 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6812 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6813
0e088b8f 6814 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6815
6816 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6817
22721343
CW		 6818 if (0) { /* causes HiZ corruption on ivb:gt1 */
6819 /* enable HiZ Raw Stall Optimization */
6820 I915_WRITE(CACHE_MODE_0_GEN7,
6821 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6822 }
116f2b6d 6823
ecdb4eb7 6824 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6825 I915_WRITE(CACHE_MODE_1,
6826 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6827
a607c1a4
VS		 6828 /*
6829 * BSpec recommends 8x4 when MSAA is used,
6830 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6831 *
6832 * Note that PS/WM thread counts depend on the WIZ hashing
6833 * disable bit, which we don't touch here, but it's good
6834 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6835 */
6836 I915_WRITE(GEN7_GT_MODE,
98533251 6837 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6838
20848223
BW		 6839 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6840 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6841 snpcr |= GEN6_MBC_SNPCR_MED;
6842 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6843
ab5c608b
BW		 6844 if (!HAS_PCH_NOP(dev))
6845 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6846
6847 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6848}
6849
c6beb13e
VS		 6850static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6851{
6852 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6853
6854 /*
6855 * Disable trickle feed and enable pnd deadline calculation
6856 */
6857 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6858 I915_WRITE(CBR1_VLV, 0);
6859}
6860
1fa61106 6861static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6862{
6863 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6864
c6beb13e 6865 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6866
ecdb4eb7 6867 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6868 I915_WRITE(_3D_CHICKEN3,
6869 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6870
ecdb4eb7 6871 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6872 I915_WRITE(IVB_CHICKEN3,
6873 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6874 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6875
fad7d36e 6876 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6877 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6878 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6879 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6880 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6881
4e04632e
AG		 6882 /* WaDisable_RenderCache_OperationalFlush:vlv */
6883 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6884
ecdb4eb7 6885 /* WaForceL3Serialization:vlv */
61939d97
JB		 6886 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6887 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6888
ecdb4eb7 6889 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6890 I915_WRITE(GEN7_ROW_CHICKEN2,
6891 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6892
ecdb4eb7 6893 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6894 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6895 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6896 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6897
46680e0a
VS		 6898 gen7_setup_fixed_func_scheduler(dev_priv);
6899
3c0edaeb 6900 /*
0f846f81 6901 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6902 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6903 */
6904 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6905 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6906
c98f5062
AG		 6907 /* WaDisableL3Bank2xClockGate:vlv
6908 * Disabling L3 clock gating- MMIO 940c[25] = 1
6909 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6910 I915_WRITE(GEN7_UCGCTL4,
6911 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6912
afd58e79
VS		 6913 /*
6914 * BSpec says this must be set, even though
6915 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6916 */
6b26c86d
DV		 6917 I915_WRITE(CACHE_MODE_1,
6918 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6919
da2518f9
VS		 6920 /*
6921 * BSpec recommends 8x4 when MSAA is used,
6922 * however in practice 16x4 seems fastest.
6923 *
6924 * Note that PS/WM thread counts depend on the WIZ hashing
6925 * disable bit, which we don't touch here, but it's good
6926 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6927 */
6928 I915_WRITE(GEN7_GT_MODE,
6929 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6930
031994ee
VS		 6931 /*
6932 * WaIncreaseL3CreditsForVLVB0:vlv
6933 * This is the hardware default actually.
6934 */
6935 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6936
2d809570 6937 /*
ecdb4eb7 6938 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6939 * Disable clock gating on th GCFG unit to prevent a delay
6940 * in the reporting of vblank events.
6941 */
7a0d1eed 6942 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6943}
6944
a4565da8
VS		 6945static void cherryview_init_clock_gating(struct drm_device *dev)
6946{
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948
c6beb13e 6949 vlv_init_display_clock_gating(dev_priv);
dd811e70 6950
232ce337
VS		 6951 /* WaVSRefCountFullforceMissDisable:chv */
6952 /* WaDSRefCountFullforceMissDisable:chv */
6953 I915_WRITE(GEN7_FF_THREAD_MODE,
6954 I915_READ(GEN7_FF_THREAD_MODE) &
6955 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6956
6957 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6958 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6959 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6960
6961 /* WaDisableCSUnitClockGating:chv */
6962 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6963 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6964
6965 /* WaDisableSDEUnitClockGating:chv */
6966 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6967 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6968
6969 /*
6970 * GTT cache may not work with big pages, so if those
6971 * are ever enabled GTT cache may need to be disabled.
6972 */
6973 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6974}
6975
1fa61106 6976static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6977{
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979 uint32_t dspclk_gate;
6980
6981 I915_WRITE(RENCLK_GATE_D1, 0);
6982 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6983 GS_UNIT_CLOCK_GATE_DISABLE |
6984 CL_UNIT_CLOCK_GATE_DISABLE);
6985 I915_WRITE(RAMCLK_GATE_D, 0);
6986 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6987 OVRUNIT_CLOCK_GATE_DISABLE |
6988 OVCUNIT_CLOCK_GATE_DISABLE;
6989 if (IS_GM45(dev))
6990 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6991 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6992
6993 /* WaDisableRenderCachePipelinedFlush */
6994 I915_WRITE(CACHE_MODE_0,
6995 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6996
4e04632e
AG		 6997 /* WaDisable_RenderCache_OperationalFlush:g4x */
6998 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6999
0e088b8f 7000 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7001}
7002
1fa61106 7003static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7004{
7005 struct drm_i915_private *dev_priv = dev->dev_private;
7006
7007 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7008 I915_WRITE(RENCLK_GATE_D2, 0);
7009 I915_WRITE(DSPCLK_GATE_D, 0);
7010 I915_WRITE(RAMCLK_GATE_D, 0);
7011 I915_WRITE16(DEUC, 0);
20f94967
VS		 7012 I915_WRITE(MI_ARB_STATE,
7013 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7014
7015 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7016 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7017}
7018
1fa61106 7019static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7020{
7021 struct drm_i915_private *dev_priv = dev->dev_private;
7022
7023 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7024 I965_RCC_CLOCK_GATE_DISABLE |
7025 I965_RCPB_CLOCK_GATE_DISABLE |
7026 I965_ISC_CLOCK_GATE_DISABLE |
7027 I965_FBC_CLOCK_GATE_DISABLE);
7028 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7029 I915_WRITE(MI_ARB_STATE,
7030 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7031
7032 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7033 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7034}
7035
1fa61106 7036static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7037{
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039 u32 dstate = I915_READ(D_STATE);
7040
7041 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7042 DSTATE_DOT_CLOCK_GATING;
7043 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7044
7045 if (IS_PINEVIEW(dev))
7046 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7047
7048 /* IIR "flip pending" means done if this bit is set */
7049 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7050
7051 /* interrupts should cause a wake up from C3 */
3299254f 7052 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7053
7054 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7055 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7056
7057 I915_WRITE(MI_ARB_STATE,
7058 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7059}
7060
1fa61106 7061static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7062{
7063 struct drm_i915_private *dev_priv = dev->dev_private;
7064
7065 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7066
7067 /* interrupts should cause a wake up from C3 */
7068 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7069 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7070
7071 I915_WRITE(MEM_MODE,
7072 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7073}
7074
1fa61106 7075static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7076{
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078
7079 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7080
7081 I915_WRITE(MEM_MODE,
7082 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7083 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7084}
7085
6f1d69b0
ED		 7086void intel_init_clock_gating(struct drm_device *dev)
7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089
c57e3551
DL		 7090 if (dev_priv->display.init_clock_gating)
7091 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7092}
7093
7d708ee4
ID		 7094void intel_suspend_hw(struct drm_device *dev)
7095{
7096 if (HAS_PCH_LPT(dev))
7097 lpt_suspend_hw(dev);
7098}
7099
1fa61106
ED		 7100/* Set up chip specific power management-related functions */
7101void intel_init_pm(struct drm_device *dev)
7102{
7103 struct drm_i915_private *dev_priv = dev->dev_private;
7104
7ff0ebcc 7105 intel_fbc_init(dev_priv);
1fa61106 7106
c921aba8
DV		 7107 /* For cxsr */
7108 if (IS_PINEVIEW(dev))
7109 i915_pineview_get_mem_freq(dev);
7110 else if (IS_GEN5(dev))
7111 i915_ironlake_get_mem_freq(dev);
7112
1fa61106 7113 /* For FIFO watermark updates */
f5ed50cb 7114 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7115 skl_setup_wm_latency(dev);
7116
a82abe43
ID		 7117 if (IS_BROXTON(dev))
7118 dev_priv->display.init_clock_gating =
7119 bxt_init_clock_gating;
2d41c0b5 7120 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7121 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7122 ilk_setup_wm_latency(dev);
53615a5e 7123
bd602544
VS		 7124 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7125 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7126 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7127 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7128 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7129 dev_priv->display.compute_intermediate_wm =
7130 ilk_compute_intermediate_wm;
7131 dev_priv->display.initial_watermarks =
7132 ilk_initial_watermarks;
7133 dev_priv->display.optimize_watermarks =
7134 ilk_optimize_watermarks;
bd602544
VS		 7135 } else {
7136 DRM_DEBUG_KMS("Failed to read display plane latency. "
7137 "Disable CxSR\n");
7138 }
7139
7140 if (IS_GEN5(dev))
1fa61106 7141 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7142 else if (IS_GEN6(dev))
1fa61106 7143 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7144 else if (IS_IVYBRIDGE(dev))
1fa61106 7145 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7146 else if (IS_HASWELL(dev))
cad2a2d7 7147 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7148 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7149 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7150 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7151 vlv_setup_wm_latency(dev);
7152
7153 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7154 dev_priv->display.init_clock_gating =
7155 cherryview_init_clock_gating;
1fa61106 7156 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7157 vlv_setup_wm_latency(dev);
7158
7159 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7160 dev_priv->display.init_clock_gating =
7161 valleyview_init_clock_gating;
1fa61106
ED		 7162 } else if (IS_PINEVIEW(dev)) {
7163 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7164 dev_priv->is_ddr3,
7165 dev_priv->fsb_freq,
7166 dev_priv->mem_freq)) {
7167 DRM_INFO("failed to find known CxSR latency "
7168 "(found ddr%s fsb freq %d, mem freq %d), "
7169 "disabling CxSR\n",
7170 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7171 dev_priv->fsb_freq, dev_priv->mem_freq);
7172 /* Disable CxSR and never update its watermark again */
5209b1f4 7173 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7174 dev_priv->display.update_wm = NULL;
7175 } else
7176 dev_priv->display.update_wm = pineview_update_wm;
7177 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7178 } else if (IS_G4X(dev)) {
7179 dev_priv->display.update_wm = g4x_update_wm;
7180 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7181 } else if (IS_GEN4(dev)) {
7182 dev_priv->display.update_wm = i965_update_wm;
7183 if (IS_CRESTLINE(dev))
7184 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7185 else if (IS_BROADWATER(dev))
7186 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7187 } else if (IS_GEN3(dev)) {
7188 dev_priv->display.update_wm = i9xx_update_wm;
7189 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7190 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7191 } else if (IS_GEN2(dev)) {
7192 if (INTEL_INFO(dev)->num_pipes == 1) {
7193 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7194 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7195 } else {
7196 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7197 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7198 }
7199
7200 if (IS_I85X(dev) || IS_I865G(dev))
7201 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7202 else
7203 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7204 } else {
7205 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7206 }
7207}
7208
151a49d0 7209int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7210{
4fc688ce 7211 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7212
7213 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7214 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7215 return -EAGAIN;
7216 }
7217
7218 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7219 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7220 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7221
7222 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7223 500)) {
7224 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7225 return -ETIMEDOUT;
7226 }
7227
7228 *val = I915_READ(GEN6_PCODE_DATA);
7229 I915_WRITE(GEN6_PCODE_DATA, 0);
7230
7231 return 0;
7232}
7233
151a49d0 7234int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7235{
4fc688ce 7236 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7237
7238 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7239 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7240 return -EAGAIN;
7241 }
7242
7243 I915_WRITE(GEN6_PCODE_DATA, val);
7244 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7245
7246 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7247 500)) {
7248 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7249 return -ETIMEDOUT;
7250 }
7251
7252 I915_WRITE(GEN6_PCODE_DATA, 0);
7253
7254 return 0;
7255}
a0e4e199 7256
dd06f88c 7257static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7258{
dd06f88c
VS		 7259 switch (czclk_freq) {
7260 case 200:
7261 return 10;
7262 case 267:
7263 return 12;
7264 case 320:
7265 case 333:
dd06f88c 7266 return 16;
ab3fb157
VS		 7267 case 400:
7268 return 20;
855ba3be
JB		 7269 default:
7270 return -1;
7271 }
dd06f88c 7272}
855ba3be 7273
dd06f88c
VS		 7274static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7275{
bfa7df01 7276 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7277
7278 div = vlv_gpu_freq_div(czclk_freq);
7279 if (div < 0)
7280 return div;
7281
7282 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7283}
7284
b55dd647 7285static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7286{
bfa7df01 7287 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7288
dd06f88c
VS		 7289 mul = vlv_gpu_freq_div(czclk_freq);
7290 if (mul < 0)
7291 return mul;
855ba3be 7292
dd06f88c 7293 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7294}
7295
b55dd647 7296static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7297{
bfa7df01 7298 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7299
9c06f674 7300 div = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7301 if (div < 0)
7302 return div;
9c06f674 7303 div /= 2;
22b1b2f8 7304
dd06f88c 7305 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7306}
7307
b55dd647 7308static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7309{
bfa7df01 7310 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7311
9c06f674 7312 mul = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7313 if (mul < 0)
7314 return mul;
9c06f674 7315 mul /= 2;
22b1b2f8 7316
1c14762d 7317 /* CHV needs even values */
dd06f88c 7318 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7319}
7320
616bc820 7321int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7322{
80b6dda4 7323 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7324 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7325 GEN9_FREQ_SCALER);
80b6dda4 7326 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7327 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7328 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7329 return byt_gpu_freq(dev_priv, val);
7330 else
7331 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7332}
7333
616bc820
VS		 7334int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7335{
80b6dda4 7336 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7337 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7338 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7339 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7340 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7341 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7342 return byt_freq_opcode(dev_priv, val);
7343 else
500a3d2e 7344 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7345}
22b1b2f8 7346
6ad790c0
CW		 7347struct request_boost {
7348 struct work_struct work;
eed29a5b 7349 struct drm_i915_gem_request *req;
6ad790c0
CW		 7350};
7351
7352static void __intel_rps_boost_work(struct work_struct *work)
7353{
7354 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7355 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7356
e61b9958
CW		 7357 if (!i915_gem_request_completed(req, true))
7358 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7359 req->emitted_jiffies);
6ad790c0 7360
e61b9958 7361 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7362 kfree(boost);
7363}
7364
7365void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7366 struct drm_i915_gem_request *req)
6ad790c0
CW		 7367{
7368 struct request_boost *boost;
7369
eed29a5b 7370 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7371 return;
7372
e61b9958
CW		 7373 if (i915_gem_request_completed(req, true))
7374 return;
7375
6ad790c0
CW		 7376 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7377 if (boost == NULL)
7378 return;
7379
eed29a5b
DV		 7380 i915_gem_request_reference(req);
7381 boost->req = req;
6ad790c0
CW		 7382
7383 INIT_WORK(&boost->work, __intel_rps_boost_work);
7384 queue_work(to_i915(dev)->wq, &boost->work);
7385}
7386
f742a552 7387void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7388{
7389 struct drm_i915_private *dev_priv = dev->dev_private;
7390
f742a552 7391 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7392 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7393
907b28c5
CW		 7394 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7395 intel_gen6_powersave_work);
1854d5ca 7396 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7397 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7398 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7399
33688d95 7400 dev_priv->pm.suspended = false;
1f814dac 7401 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7402 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7403}
Ubuntu Jammy Linux kernel mirror