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drm/i915: Add crtc->plane_ids_mask
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
46f16e63 59static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
a82abe43 60{
b033bb6d 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
b033bb6d
MK		 65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 81}
82
46f16e63 83static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
b033bb6d 84{
46f16e63 85 gen9_init_clock_gating(dev_priv);
b033bb6d 86
a7546159
NH		 87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
32608ca2
ID		 91 /*
92 * FIXME:
868434c5 93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 94 */
32608ca2 95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 105}
106
148ac1f3 107static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 108{
c921aba8
DV		 109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143}
144
148ac1f3 145static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 146{
c921aba8
DV		 147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
20e4d407 172 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
20e4d407 204 dev_priv->ips.c_m = 0;
c921aba8 205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 206 dev_priv->ips.c_m = 1;
c921aba8 207 } else {
20e4d407 208 dev_priv->ips.c_m = 2;
c921aba8
DV		 209 }
210}
211
b445e3b0
ED		 212static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248};
249
44a655ca
TU		 250static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
b445e3b0
ED		 252 int fsb,
253 int mem)
254{
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272}
273
fc1ac8de
VS		 274static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275{
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294}
295
cfb41411
VS		 296static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297{
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310}
311
f4998963
VS		 312#define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
5209b1f4 315void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 316{
5209b1f4 317 u32 val;
b445e3b0 318
920a14b2 319 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 320 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 321 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 322 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 323 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 324 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 325 POSTING_READ(FW_BLC_SELF);
9b1e14f4 326 } else if (IS_PINEVIEW(dev_priv)) {
5209b1f4
ID		 327 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
328 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
329 I915_WRITE(DSPFW3, val);
a7a6c498 330 POSTING_READ(DSPFW3);
50a0bc90 331 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 332 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
333 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
334 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 335 POSTING_READ(FW_BLC_SELF);
50a0bc90 336 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 337 /*
338 * FIXME can't find a bit like this for 915G, and
339 * and yet it does have the related watermark in
340 * FW_BLC_SELF. What's going on?
341 */
5209b1f4
ID		 342 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
343 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
344 I915_WRITE(INSTPM, val);
a7a6c498 345 POSTING_READ(INSTPM);
5209b1f4
ID		 346 } else {
347 return;
348 }
b445e3b0 349
08c4d7fc 350 DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable));
b445e3b0
ED		 351}
352
fc1ac8de 353
b445e3b0
ED		 354/*
355 * Latency for FIFO fetches is dependent on several factors:
356 * - memory configuration (speed, channels)
357 * - chipset
358 * - current MCH state
359 * It can be fairly high in some situations, so here we assume a fairly
360 * pessimal value. It's a tradeoff between extra memory fetches (if we
361 * set this value too high, the FIFO will fetch frequently to stay full)
362 * and power consumption (set it too low to save power and we might see
363 * FIFO underruns and display "flicker").
364 *
365 * A value of 5us seems to be a good balance; safe for very low end
366 * platforms but not overly aggressive on lower latency configs.
367 */
5aef6003 368static const int pessimal_latency_ns = 5000;
b445e3b0 369
b5004720
VS		 370#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
371 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
372
ef0f5e93 373static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
b5004720
VS		 374 enum pipe pipe, int plane)
375{
b5004720
VS		 376 int sprite0_start, sprite1_start, size;
377
378 switch (pipe) {
379 uint32_t dsparb, dsparb2, dsparb3;
380 case PIPE_A:
381 dsparb = I915_READ(DSPARB);
382 dsparb2 = I915_READ(DSPARB2);
383 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
384 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
385 break;
386 case PIPE_B:
387 dsparb = I915_READ(DSPARB);
388 dsparb2 = I915_READ(DSPARB2);
389 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
390 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
391 break;
392 case PIPE_C:
393 dsparb2 = I915_READ(DSPARB2);
394 dsparb3 = I915_READ(DSPARB3);
395 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
396 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
397 break;
398 default:
399 return 0;
400 }
401
402 switch (plane) {
403 case 0:
404 size = sprite0_start;
405 break;
406 case 1:
407 size = sprite1_start - sprite0_start;
408 break;
409 case 2:
410 size = 512 - 1 - sprite1_start;
411 break;
412 default:
413 return 0;
414 }
415
416 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
417 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
418 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
419 size);
420
421 return size;
422}
423
ef0f5e93 424static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 425{
b445e3b0
ED		 426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x7f;
430 if (plane)
431 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
432
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
434 plane ? "B" : "A", size);
435
436 return size;
437}
438
ef0f5e93 439static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 440{
b445e3b0
ED		 441 uint32_t dsparb = I915_READ(DSPARB);
442 int size;
443
444 size = dsparb & 0x1ff;
445 if (plane)
446 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
447 size >>= 1; /* Convert to cachelines */
448
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
450 plane ? "B" : "A", size);
451
452 return size;
453}
454
ef0f5e93 455static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 456{
b445e3b0
ED		 457 uint32_t dsparb = I915_READ(DSPARB);
458 int size;
459
460 size = dsparb & 0x7f;
461 size >>= 2; /* Convert to cachelines */
462
463 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
464 plane ? "B" : "A",
465 size);
466
467 return size;
468}
469
b445e3b0
ED		 470/* Pineview has different values for various configs */
471static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 477};
478static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 479 .fifo_size = PINEVIEW_DISPLAY_FIFO,
480 .max_wm = PINEVIEW_MAX_WM,
481 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
482 .guard_size = PINEVIEW_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 484};
485static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 491};
492static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 493 .fifo_size = PINEVIEW_CURSOR_FIFO,
494 .max_wm = PINEVIEW_CURSOR_MAX_WM,
495 .default_wm = PINEVIEW_CURSOR_DFT_WM,
496 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
497 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 498};
499static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 500 .fifo_size = G4X_FIFO_SIZE,
501 .max_wm = G4X_MAX_WM,
502 .default_wm = G4X_MAX_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 505};
506static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 507 .fifo_size = I965_CURSOR_FIFO,
508 .max_wm = I965_CURSOR_MAX_WM,
509 .default_wm = I965_CURSOR_DFT_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 512};
b445e3b0 513static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 521 .fifo_size = I945_FIFO_SIZE,
522 .max_wm = I915_MAX_WM,
523 .default_wm = 1,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 528 .fifo_size = I915_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 533};
9d539105 534static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 535 .fifo_size = I855GM_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 540};
9d539105
VS		 541static const struct intel_watermark_params i830_bc_wm_info = {
542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM/2,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
547};
feb56b93 548static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 549 .fifo_size = I830_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 554};
555
b445e3b0
ED		 556/**
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
ac484963 560 * @cpp: bytes per pixel
b445e3b0
ED		 561 * @latency_ns: memory latency for the platform
562 *
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
567 *
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
573 */
574static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
575 const struct intel_watermark_params *wm,
ac484963 576 int fifo_size, int cpp,
b445e3b0
ED		 577 unsigned long latency_ns)
578{
579 long entries_required, wm_size;
580
581 /*
582 * Note: we need to make sure we don't overflow for various clock &
583 * latency values.
584 * clocks go from a few thousand to several hundred thousand.
585 * latency is usually a few thousand
586 */
ac484963 587 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 588 1000;
589 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
590
591 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
592
593 wm_size = fifo_size - (entries_required + wm->guard_size);
594
595 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
596
597 /* Don't promote wm_size to unsigned... */
598 if (wm_size > (long)wm->max_wm)
599 wm_size = wm->max_wm;
600 if (wm_size <= 0)
601 wm_size = wm->default_wm;
d6feb196
VS		 602
603 /*
604 * Bspec seems to indicate that the value shouldn't be lower than
605 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
606 * Lets go for 8 which is the burst size since certain platforms
607 * already use a hardcoded 8 (which is what the spec says should be
608 * done).
609 */
610 if (wm_size <= 8)
611 wm_size = 8;
612
b445e3b0
ED		 613 return wm_size;
614}
615
ffc7a76b 616static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
b445e3b0 617{
efc2611e 618 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 619
ffc7a76b 620 for_each_intel_crtc(&dev_priv->drm, crtc) {
efc2611e 621 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 622 if (enabled)
623 return NULL;
624 enabled = crtc;
625 }
626 }
627
628 return enabled;
629}
630
432081bc 631static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 632{
ffc7a76b 633 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 634 struct intel_crtc *crtc;
b445e3b0
ED		 635 const struct cxsr_latency *latency;
636 u32 reg;
637 unsigned long wm;
638
50a0bc90
TU		 639 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
640 dev_priv->is_ddr3,
641 dev_priv->fsb_freq,
642 dev_priv->mem_freq);
b445e3b0
ED		 643 if (!latency) {
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 645 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 646 return;
647 }
648
ffc7a76b 649 crtc = single_enabled_crtc(dev_priv);
b445e3b0 650 if (crtc) {
efc2611e
VS		 651 const struct drm_display_mode *adjusted_mode =
652 &crtc->config->base.adjusted_mode;
653 const struct drm_framebuffer *fb =
654 crtc->base.primary->state->fb;
655 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
7c5f93b0 656 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 657
658 /* Display SR */
659 wm = intel_calculate_wm(clock, &pineview_display_wm,
660 pineview_display_wm.fifo_size,
ac484963 661 cpp, latency->display_sr);
b445e3b0
ED		 662 reg = I915_READ(DSPFW1);
663 reg &= ~DSPFW_SR_MASK;
f4998963 664 reg |= FW_WM(wm, SR);
b445e3b0
ED		 665 I915_WRITE(DSPFW1, reg);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
667
668 /* cursor SR */
669 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
670 pineview_display_wm.fifo_size,
ac484963 671 cpp, latency->cursor_sr);
b445e3b0
ED		 672 reg = I915_READ(DSPFW3);
673 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 674 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 675 I915_WRITE(DSPFW3, reg);
676
677 /* Display HPLL off SR */
678 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
679 pineview_display_hplloff_wm.fifo_size,
ac484963 680 cpp, latency->display_hpll_disable);
b445e3b0
ED		 681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 683 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 684 I915_WRITE(DSPFW3, reg);
685
686 /* cursor HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
ac484963 689 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 692 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 693 I915_WRITE(DSPFW3, reg);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
695
5209b1f4 696 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 697 } else {
5209b1f4 698 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 699 }
700}
701
f0ce2310 702static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 703 int plane,
704 const struct intel_watermark_params *display,
705 int display_latency_ns,
706 const struct intel_watermark_params *cursor,
707 int cursor_latency_ns,
708 int *plane_wm,
709 int *cursor_wm)
710{
efc2611e 711 struct intel_crtc *crtc;
4fe8590a 712 const struct drm_display_mode *adjusted_mode;
efc2611e 713 const struct drm_framebuffer *fb;
ac484963 714 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 715 int line_time_us, line_count;
716 int entries, tlb_miss;
717
b91eb5cc 718 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 719 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 720 *cursor_wm = cursor->guard_size;
721 *plane_wm = display->guard_size;
722 return false;
723 }
724
efc2611e
VS		 725 adjusted_mode = &crtc->config->base.adjusted_mode;
726 fb = crtc->base.primary->state->fb;
241bfc38 727 clock = adjusted_mode->crtc_clock;
fec8cba3 728 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 729 hdisplay = crtc->config->pipe_src_w;
730 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 731
732 /* Use the small buffer method to calculate plane watermark */
ac484963 733 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 734 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
735 if (tlb_miss > 0)
736 entries += tlb_miss;
737 entries = DIV_ROUND_UP(entries, display->cacheline_size);
738 *plane_wm = entries + display->guard_size;
739 if (*plane_wm > (int)display->max_wm)
740 *plane_wm = display->max_wm;
741
742 /* Use the large buffer method to calculate cursor watermark */
922044c9 743 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 744 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 745 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 746 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
750 *cursor_wm = entries + cursor->guard_size;
751 if (*cursor_wm > (int)cursor->max_wm)
752 *cursor_wm = (int)cursor->max_wm;
753
754 return true;
755}
756
757/*
758 * Check the wm result.
759 *
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
762 * must be disabled.
763 */
f0ce2310 764static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 765 int display_wm, int cursor_wm,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor)
768{
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm, cursor_wm);
771
772 if (display_wm > display->max_wm) {
ae9400ca 773 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 774 display_wm, display->max_wm);
775 return false;
776 }
777
778 if (cursor_wm > cursor->max_wm) {
ae9400ca 779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 780 cursor_wm, cursor->max_wm);
781 return false;
782 }
783
784 if (!(display_wm || cursor_wm)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
786 return false;
787 }
788
789 return true;
790}
791
f0ce2310 792static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 793 int plane,
794 int latency_ns,
795 const struct intel_watermark_params *display,
796 const struct intel_watermark_params *cursor,
797 int *display_wm, int *cursor_wm)
798{
efc2611e 799 struct intel_crtc *crtc;
4fe8590a 800 const struct drm_display_mode *adjusted_mode;
efc2611e 801 const struct drm_framebuffer *fb;
ac484963 802 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 803 unsigned long line_time_us;
804 int line_count, line_size;
805 int small, large;
806 int entries;
807
808 if (!latency_ns) {
809 *display_wm = *cursor_wm = 0;
810 return false;
811 }
812
b91eb5cc 813 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 814 adjusted_mode = &crtc->config->base.adjusted_mode;
815 fb = crtc->base.primary->state->fb;
241bfc38 816 clock = adjusted_mode->crtc_clock;
fec8cba3 817 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 818 hdisplay = crtc->config->pipe_src_w;
819 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0 820
922044c9 821 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 822 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 823 line_size = hdisplay * cpp;
b445e3b0
ED		 824
825 /* Use the minimum of the small and large buffer method for primary */
ac484963 826 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 827 large = line_count * line_size;
828
829 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
830 *display_wm = entries + display->guard_size;
831
832 /* calculate the self-refresh watermark for display cursor */
efc2611e 833 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 834 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
835 *cursor_wm = entries + cursor->guard_size;
836
f0ce2310 837 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 838 *display_wm, *cursor_wm,
839 display, cursor);
840}
841
15665979
VS		 842#define FW_WM_VLV(value, plane) \
843 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
844
0018fda1
VS		 845static void vlv_write_wm_values(struct intel_crtc *crtc,
846 const struct vlv_wm_values *wm)
847{
848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
849 enum pipe pipe = crtc->pipe;
850
851 I915_WRITE(VLV_DDL(pipe),
852 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
853 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
854 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
855 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
856
ae80152d 857 I915_WRITE(DSPFW1,
15665979
VS		 858 FW_WM(wm->sr.plane, SR) |
859 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
860 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
861 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 862 I915_WRITE(DSPFW2,
15665979
VS		 863 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
864 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
865 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 866 I915_WRITE(DSPFW3,
15665979 867 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 868
869 if (IS_CHERRYVIEW(dev_priv)) {
870 I915_WRITE(DSPFW7_CHV,
15665979
VS		 871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
872 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 873 I915_WRITE(DSPFW8_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
875 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 876 I915_WRITE(DSPFW9_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
878 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 879 I915_WRITE(DSPHOWM,
15665979
VS		 880 FW_WM(wm->sr.plane >> 9, SR_HI) |
881 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
882 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
883 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
885 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
886 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
888 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
889 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 890 } else {
891 I915_WRITE(DSPFW7,
15665979
VS		 892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 894 I915_WRITE(DSPHOWM,
15665979
VS		 895 FW_WM(wm->sr.plane >> 9, SR_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
898 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
901 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 902 }
903
2cb389b7
VS		 904 /* zero (unused) WM1 watermarks */
905 I915_WRITE(DSPFW4, 0);
906 I915_WRITE(DSPFW5, 0);
907 I915_WRITE(DSPFW6, 0);
908 I915_WRITE(DSPHOWM1, 0);
909
ae80152d 910 POSTING_READ(DSPFW1);
0018fda1
VS		 911}
912
15665979
VS		 913#undef FW_WM_VLV
914
6eb1a681
VS		 915enum vlv_wm_level {
916 VLV_WM_LEVEL_PM2,
917 VLV_WM_LEVEL_PM5,
918 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 919};
920
262cd2e1
VS		 921/* latency must be in 0.1us units. */
922static unsigned int vlv_wm_method2(unsigned int pixel_rate,
923 unsigned int pipe_htotal,
924 unsigned int horiz_pixels,
ac484963 925 unsigned int cpp,
262cd2e1
VS		 926 unsigned int latency)
927{
928 unsigned int ret;
929
930 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 931 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 932 ret = DIV_ROUND_UP(ret, 64);
933
934 return ret;
935}
936
bb726519 937static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
262cd2e1 938{
262cd2e1
VS		 939 /* all latencies in usec */
940 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
941
58590c14
VS		 942 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
943
262cd2e1
VS		 944 if (IS_CHERRYVIEW(dev_priv)) {
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
946 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 947
948 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 949 }
950}
951
952static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
953 struct intel_crtc *crtc,
954 const struct intel_plane_state *state,
955 int level)
956{
957 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 958 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 959
960 if (dev_priv->wm.pri_latency[level] == 0)
961 return USHRT_MAX;
962
936e71e3 963 if (!state->base.visible)
262cd2e1
VS		 964 return 0;
965
ac484963 966 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 967 clock = crtc->config->base.adjusted_mode.crtc_clock;
968 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
969 width = crtc->config->pipe_src_w;
970 if (WARN_ON(htotal == 0))
971 htotal = 1;
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
974 /*
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
979 */
980 wm = 63;
981 } else {
ac484963 982 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 983 dev_priv->wm.pri_latency[level] * 10);
984 }
985
986 return min_t(int, wm, USHRT_MAX);
987}
988
54f1b6e1
VS		 989static void vlv_compute_fifo(struct intel_crtc *crtc)
990{
991 struct drm_device *dev = crtc->base.dev;
992 struct vlv_wm_state *wm_state = &crtc->wm_state;
993 struct intel_plane *plane;
994 unsigned int total_rate = 0;
995 const int fifo_size = 512 - 1;
996 int fifo_extra, fifo_left = fifo_size;
997
998 for_each_intel_plane_on_crtc(dev, crtc, plane) {
999 struct intel_plane_state *state =
1000 to_intel_plane_state(plane->base.state);
1001
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
1004
936e71e3 1005 if (state->base.visible) {
54f1b6e1
VS		 1006 wm_state->num_active_planes++;
1007 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1008 }
1009 }
1010
1011 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012 struct intel_plane_state *state =
1013 to_intel_plane_state(plane->base.state);
1014 unsigned int rate;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 plane->wm.fifo_size = 63;
1018 continue;
1019 }
1020
936e71e3 1021 if (!state->base.visible) {
54f1b6e1
VS		 1022 plane->wm.fifo_size = 0;
1023 continue;
1024 }
1025
1026 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1027 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028 fifo_left -= plane->wm.fifo_size;
1029 }
1030
1031 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035 int plane_extra;
1036
1037 if (fifo_left == 0)
1038 break;
1039
1040 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041 continue;
1042
1043 /* give it all to the first plane if none are active */
1044 if (plane->wm.fifo_size == 0 &&
1045 wm_state->num_active_planes)
1046 continue;
1047
1048 plane_extra = min(fifo_extra, fifo_left);
1049 plane->wm.fifo_size += plane_extra;
1050 fifo_left -= plane_extra;
1051 }
1052
1053 WARN_ON(fifo_left != 0);
1054}
1055
262cd2e1
VS		 1056static void vlv_invert_wms(struct intel_crtc *crtc)
1057{
1058 struct vlv_wm_state *wm_state = &crtc->wm_state;
1059 int level;
1060
1061 for (level = 0; level < wm_state->num_levels; level++) {
1062 struct drm_device *dev = crtc->base.dev;
b7f05d4a
TU		 1063 const int sr_fifo_size =
1064 INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
262cd2e1
VS		 1065 struct intel_plane *plane;
1066
1067 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1068 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1069
1070 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1071 switch (plane->base.type) {
1072 int sprite;
1073 case DRM_PLANE_TYPE_CURSOR:
1074 wm_state->wm[level].cursor = plane->wm.fifo_size -
1075 wm_state->wm[level].cursor;
1076 break;
1077 case DRM_PLANE_TYPE_PRIMARY:
1078 wm_state->wm[level].primary = plane->wm.fifo_size -
1079 wm_state->wm[level].primary;
1080 break;
1081 case DRM_PLANE_TYPE_OVERLAY:
1082 sprite = plane->plane;
1083 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1084 wm_state->wm[level].sprite[sprite];
1085 break;
1086 }
1087 }
1088 }
1089}
1090
26e1fe4f 1091static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1092{
1093 struct drm_device *dev = crtc->base.dev;
b7f05d4a 1094 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1095 struct vlv_wm_state *wm_state = &crtc->wm_state;
1096 struct intel_plane *plane;
b7f05d4a 1097 int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
262cd2e1
VS		 1098 int level;
1099
1100 memset(wm_state, 0, sizeof(*wm_state));
1101
852eb00d 1102 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
b7f05d4a 1103 wm_state->num_levels = dev_priv->wm.max_level + 1;
262cd2e1
VS		 1104
1105 wm_state->num_active_planes = 0;
262cd2e1 1106
54f1b6e1 1107 vlv_compute_fifo(crtc);
262cd2e1
VS		 1108
1109 if (wm_state->num_active_planes != 1)
1110 wm_state->cxsr = false;
1111
1112 if (wm_state->cxsr) {
1113 for (level = 0; level < wm_state->num_levels; level++) {
1114 wm_state->sr[level].plane = sr_fifo_size;
1115 wm_state->sr[level].cursor = 63;
1116 }
1117 }
1118
1119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1120 struct intel_plane_state *state =
1121 to_intel_plane_state(plane->base.state);
1122
936e71e3 1123 if (!state->base.visible)
262cd2e1
VS		 1124 continue;
1125
1126 /* normal watermarks */
1127 for (level = 0; level < wm_state->num_levels; level++) {
1128 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1129 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1130
1131 /* hack */
1132 if (WARN_ON(level == 0 && wm > max_wm))
1133 wm = max_wm;
1134
1135 if (wm > plane->wm.fifo_size)
1136 break;
1137
1138 switch (plane->base.type) {
1139 int sprite;
1140 case DRM_PLANE_TYPE_CURSOR:
1141 wm_state->wm[level].cursor = wm;
1142 break;
1143 case DRM_PLANE_TYPE_PRIMARY:
1144 wm_state->wm[level].primary = wm;
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 wm_state->wm[level].sprite[sprite] = wm;
1149 break;
1150 }
1151 }
1152
1153 wm_state->num_levels = level;
1154
1155 if (!wm_state->cxsr)
1156 continue;
1157
1158 /* maxfifo watermarks */
1159 switch (plane->base.type) {
1160 int sprite, level;
1161 case DRM_PLANE_TYPE_CURSOR:
1162 for (level = 0; level < wm_state->num_levels; level++)
1163 wm_state->sr[level].cursor =
5a37ed0a 1164 wm_state->wm[level].cursor;
262cd2e1
VS		 1165 break;
1166 case DRM_PLANE_TYPE_PRIMARY:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].plane =
1169 min(wm_state->sr[level].plane,
1170 wm_state->wm[level].primary);
1171 break;
1172 case DRM_PLANE_TYPE_OVERLAY:
1173 sprite = plane->plane;
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
1176 min(wm_state->sr[level].plane,
1177 wm_state->wm[level].sprite[sprite]);
1178 break;
1179 }
1180 }
1181
1182 /* clear any (partially) filled invalid levels */
b7f05d4a 1183 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
262cd2e1
VS		 1184 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1185 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1186 }
1187
1188 vlv_invert_wms(crtc);
1189}
1190
54f1b6e1
VS		 1191#define VLV_FIFO(plane, value) \
1192 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1193
1194static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1195{
1196 struct drm_device *dev = crtc->base.dev;
1197 struct drm_i915_private *dev_priv = to_i915(dev);
1198 struct intel_plane *plane;
1199 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1200
1201 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1202 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1203 WARN_ON(plane->wm.fifo_size != 63);
1204 continue;
1205 }
1206
1207 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1208 sprite0_start = plane->wm.fifo_size;
1209 else if (plane->plane == 0)
1210 sprite1_start = sprite0_start + plane->wm.fifo_size;
1211 else
1212 fifo_size = sprite1_start + plane->wm.fifo_size;
1213 }
1214
1215 WARN_ON(fifo_size != 512 - 1);
1216
1217 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1218 pipe_name(crtc->pipe), sprite0_start,
1219 sprite1_start, fifo_size);
1220
1221 switch (crtc->pipe) {
1222 uint32_t dsparb, dsparb2, dsparb3;
1223 case PIPE_A:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1228 VLV_FIFO(SPRITEB, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1230 VLV_FIFO(SPRITEB, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1233 VLV_FIFO(SPRITEB_HI, 0x1));
1234 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_B:
1241 dsparb = I915_READ(DSPARB);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1245 VLV_FIFO(SPRITED, 0xff));
1246 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1247 VLV_FIFO(SPRITED, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1250 VLV_FIFO(SPRITED_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB, dsparb);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 case PIPE_C:
1258 dsparb3 = I915_READ(DSPARB3);
1259 dsparb2 = I915_READ(DSPARB2);
1260
1261 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1262 VLV_FIFO(SPRITEF, 0xff));
1263 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1264 VLV_FIFO(SPRITEF, sprite1_start));
1265
1266 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1267 VLV_FIFO(SPRITEF_HI, 0xff));
1268 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1269 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1270
1271 I915_WRITE(DSPARB3, dsparb3);
1272 I915_WRITE(DSPARB2, dsparb2);
1273 break;
1274 default:
1275 break;
1276 }
1277}
1278
1279#undef VLV_FIFO
1280
262cd2e1
VS		 1281static void vlv_merge_wm(struct drm_device *dev,
1282 struct vlv_wm_values *wm)
1283{
1284 struct intel_crtc *crtc;
1285 int num_active_crtcs = 0;
1286
58590c14 1287 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1288 wm->cxsr = true;
1289
1290 for_each_intel_crtc(dev, crtc) {
1291 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1292
1293 if (!crtc->active)
1294 continue;
1295
1296 if (!wm_state->cxsr)
1297 wm->cxsr = false;
1298
1299 num_active_crtcs++;
1300 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1301 }
1302
1303 if (num_active_crtcs != 1)
1304 wm->cxsr = false;
1305
6f9c784b
VS		 1306 if (num_active_crtcs > 1)
1307 wm->level = VLV_WM_LEVEL_PM2;
1308
262cd2e1
VS		 1309 for_each_intel_crtc(dev, crtc) {
1310 struct vlv_wm_state *wm_state = &crtc->wm_state;
1311 enum pipe pipe = crtc->pipe;
1312
1313 if (!crtc->active)
1314 continue;
1315
1316 wm->pipe[pipe] = wm_state->wm[wm->level];
1317 if (wm->cxsr)
1318 wm->sr = wm_state->sr[wm->level];
1319
1320 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1321 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1322 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1323 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1324 }
1325}
1326
432081bc 1327static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1328{
432081bc 1329 struct drm_device *dev = crtc->base.dev;
fac5e23e 1330 struct drm_i915_private *dev_priv = to_i915(dev);
432081bc 1331 enum pipe pipe = crtc->pipe;
262cd2e1
VS		 1332 struct vlv_wm_values wm = {};
1333
432081bc 1334 vlv_compute_wm(crtc);
262cd2e1
VS		 1335 vlv_merge_wm(dev, &wm);
1336
54f1b6e1
VS		 1337 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1338 /* FIXME should be part of crtc atomic commit */
432081bc 1339 vlv_pipe_set_fifo_size(crtc);
262cd2e1 1340 return;
54f1b6e1 1341 }
262cd2e1
VS		 1342
1343 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1344 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1345 chv_set_memory_dvfs(dev_priv, false);
1346
1347 if (wm.level < VLV_WM_LEVEL_PM5 &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1349 chv_set_memory_pm5(dev_priv, false);
1350
852eb00d 1351 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1352 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1353
54f1b6e1 1354 /* FIXME should be part of crtc atomic commit */
432081bc 1355 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1356
432081bc 1357 vlv_write_wm_values(crtc, &wm);
262cd2e1
VS		 1358
1359 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1360 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1361 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1362 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1363 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1364
852eb00d 1365 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1366 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1367
1368 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1369 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1370 chv_set_memory_pm5(dev_priv, true);
1371
1372 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1374 chv_set_memory_dvfs(dev_priv, true);
1375
1376 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1377}
1378
ae80152d
VS		 1379#define single_plane_enabled(mask) is_power_of_2(mask)
1380
432081bc 1381static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1382{
b91eb5cc 1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1384 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
9858425c 1388 bool cxsr_enabled;
b445e3b0 1389
f0ce2310 1390 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1391 &g4x_wm_info, pessimal_latency_ns,
1392 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1393 &planea_wm, &cursora_wm))
51cea1f4 1394 enabled |= 1 << PIPE_A;
b445e3b0 1395
f0ce2310 1396 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1397 &g4x_wm_info, pessimal_latency_ns,
1398 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1399 &planeb_wm, &cursorb_wm))
51cea1f4 1400 enabled |= 1 << PIPE_B;
b445e3b0 1401
b445e3b0 1402 if (single_plane_enabled(enabled) &&
f0ce2310 1403 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1404 sr_latency_ns,
1405 &g4x_wm_info,
1406 &g4x_cursor_wm_info,
52bd02d8 1407 &plane_sr, &cursor_sr)) {
9858425c 1408 cxsr_enabled = true;
52bd02d8 1409 } else {
9858425c 1410 cxsr_enabled = false;
5209b1f4 1411 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1412 plane_sr = cursor_sr = 0;
1413 }
b445e3b0 1414
a5043453
VS		 1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1417 planea_wm, cursora_wm,
1418 planeb_wm, cursorb_wm,
1419 plane_sr, cursor_sr);
1420
1421 I915_WRITE(DSPFW1,
f4998963
VS		 1422 FW_WM(plane_sr, SR) |
1423 FW_WM(cursorb_wm, CURSORB) |
1424 FW_WM(planeb_wm, PLANEB) |
1425 FW_WM(planea_wm, PLANEA));
b445e3b0 1426 I915_WRITE(DSPFW2,
8c919b28 1427 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1428 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1429 /* HPLL off in SR has some issues on G4x... disable it */
1430 I915_WRITE(DSPFW3,
8c919b28 1431 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1432 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1433
1434 if (cxsr_enabled)
1435 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1436}
1437
432081bc 1438static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1439{
ffc7a76b 1440 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1441 struct intel_crtc *crtc;
b445e3b0
ED		 1442 int srwm = 1;
1443 int cursor_sr = 16;
9858425c 1444 bool cxsr_enabled;
b445e3b0
ED		 1445
1446 /* Calc sr entries for one plane configs */
ffc7a76b 1447 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1448 if (crtc) {
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns = 12000;
efc2611e
VS		 1451 const struct drm_display_mode *adjusted_mode =
1452 &crtc->config->base.adjusted_mode;
1453 const struct drm_framebuffer *fb =
1454 crtc->base.primary->state->fb;
241bfc38 1455 int clock = adjusted_mode->crtc_clock;
fec8cba3 1456 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1457 int hdisplay = crtc->config->pipe_src_w;
1458 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 1459 unsigned long line_time_us;
1460 int entries;
1461
922044c9 1462 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1463
1464 /* Use ns/us then divide to preserve precision */
1465 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1466 cpp * hdisplay;
b445e3b0
ED		 1467 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1468 srwm = I965_FIFO_SIZE - entries;
1469 if (srwm < 0)
1470 srwm = 1;
1471 srwm &= 0x1ff;
1472 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1473 entries, srwm);
1474
1475 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1476 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1477 entries = DIV_ROUND_UP(entries,
1478 i965_cursor_wm_info.cacheline_size);
1479 cursor_sr = i965_cursor_wm_info.fifo_size -
1480 (entries + i965_cursor_wm_info.guard_size);
1481
1482 if (cursor_sr > i965_cursor_wm_info.max_wm)
1483 cursor_sr = i965_cursor_wm_info.max_wm;
1484
1485 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1486 "cursor %d\n", srwm, cursor_sr);
1487
9858425c 1488 cxsr_enabled = true;
b445e3b0 1489 } else {
9858425c 1490 cxsr_enabled = false;
b445e3b0 1491 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1492 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1493 }
1494
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1496 srwm);
1497
1498 /* 965 has limitations... */
f4998963
VS		 1499 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1500 FW_WM(8, CURSORB) |
1501 FW_WM(8, PLANEB) |
1502 FW_WM(8, PLANEA));
1503 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1504 FW_WM(8, PLANEC_OLD));
b445e3b0 1505 /* update cursor SR watermark */
f4998963 1506 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1507
1508 if (cxsr_enabled)
1509 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1510}
1511
f4998963
VS		 1512#undef FW_WM
1513
432081bc 1514static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1515{
ffc7a76b 1516 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
b445e3b0
ED		 1517 const struct intel_watermark_params *wm_info;
1518 uint32_t fwater_lo;
1519 uint32_t fwater_hi;
1520 int cwm, srwm = 1;
1521 int fifo_size;
1522 int planea_wm, planeb_wm;
efc2611e 1523 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 1524
a9097be4 1525 if (IS_I945GM(dev_priv))
b445e3b0 1526 wm_info = &i945_wm_info;
5db94019 1527 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1528 wm_info = &i915_wm_info;
1529 else
9d539105 1530 wm_info = &i830_a_wm_info;
b445e3b0 1531
ef0f5e93 1532 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
b91eb5cc 1533 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1534 if (intel_crtc_active(crtc)) {
1535 const struct drm_display_mode *adjusted_mode =
1536 &crtc->config->base.adjusted_mode;
1537 const struct drm_framebuffer *fb =
1538 crtc->base.primary->state->fb;
1539 int cpp;
1540
5db94019 1541 if (IS_GEN2(dev_priv))
b9e0bda3 1542 cpp = 4;
efc2611e
VS		 1543 else
1544 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1545
241bfc38 1546 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0 1549 enabled = crtc;
9d539105 1550 } else {
b445e3b0 1551 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1552 if (planea_wm > (long)wm_info->max_wm)
1553 planea_wm = wm_info->max_wm;
1554 }
1555
5db94019 1556 if (IS_GEN2(dev_priv))
9d539105 1557 wm_info = &i830_bc_wm_info;
b445e3b0 1558
ef0f5e93 1559 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
b91eb5cc 1560 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1561 if (intel_crtc_active(crtc)) {
1562 const struct drm_display_mode *adjusted_mode =
1563 &crtc->config->base.adjusted_mode;
1564 const struct drm_framebuffer *fb =
1565 crtc->base.primary->state->fb;
1566 int cpp;
1567
5db94019 1568 if (IS_GEN2(dev_priv))
b9e0bda3 1569 cpp = 4;
efc2611e
VS		 1570 else
1571 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1572
241bfc38 1573 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0
ED		 1576 if (enabled == NULL)
1577 enabled = crtc;
1578 else
1579 enabled = NULL;
9d539105 1580 } else {
b445e3b0 1581 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1582 if (planeb_wm > (long)wm_info->max_wm)
1583 planeb_wm = wm_info->max_wm;
1584 }
b445e3b0
ED		 1585
1586 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1587
50a0bc90 1588 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1589 struct drm_i915_gem_object *obj;
2ab1bc9d 1590
efc2611e 1591 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1592
1593 /* self-refresh seems busted with untiled */
3e510a8e 1594 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1595 enabled = NULL;
1596 }
1597
b445e3b0
ED		 1598 /*
1599 * Overlay gets an aggressive default since video jitter is bad.
1600 */
1601 cwm = 2;
1602
1603 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1604 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1605
1606 /* Calc sr entries for one plane configs */
03427fcb 1607 if (HAS_FW_BLC(dev_priv) && enabled) {
b445e3b0
ED		 1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
efc2611e
VS		 1610 const struct drm_display_mode *adjusted_mode =
1611 &enabled->config->base.adjusted_mode;
1612 const struct drm_framebuffer *fb =
1613 enabled->base.primary->state->fb;
241bfc38 1614 int clock = adjusted_mode->crtc_clock;
fec8cba3 1615 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1616 int hdisplay = enabled->config->pipe_src_w;
1617 int cpp;
b445e3b0
ED		 1618 unsigned long line_time_us;
1619 int entries;
1620
50a0bc90 1621 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1622 cpp = 4;
efc2611e
VS		 1623 else
1624 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2d1b5056 1625
922044c9 1626 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1627
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1630 cpp * hdisplay;
b445e3b0
ED		 1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1634 if (srwm < 0)
1635 srwm = 1;
1636
50a0bc90 1637 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1640 else
b445e3b0
ED		 1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1642 }
1643
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1646
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1649
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1653
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1656
5209b1f4
ID		 1657 if (enabled)
1658 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1659}
1660
432081bc 1661static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1662{
ffc7a76b 1663 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1664 struct intel_crtc *crtc;
241bfc38 1665 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1666 uint32_t fwater_lo;
1667 int planea_wm;
1668
ffc7a76b 1669 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1670 if (crtc == NULL)
1671 return;
1672
efc2611e 1673 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1674 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1675 &i845_wm_info,
ef0f5e93 1676 dev_priv->display.get_fifo_size(dev_priv, 0),
5aef6003 1677 4, pessimal_latency_ns);
b445e3b0
ED		 1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1679 fwater_lo |= (3<<8) | planea_wm;
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1682
1683 I915_WRITE(FW_BLC, fwater_lo);
1684}
1685
8cfb3407 1686uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1687{
fd4daa9c 1688 uint32_t pixel_rate;
801bcfff 1689
8cfb3407 1690 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1691
1692 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1693 * adjust the pixel_rate here. */
1694
8cfb3407 1695 if (pipe_config->pch_pfit.enabled) {
801bcfff 1696 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1697 uint32_t pfit_size = pipe_config->pch_pfit.size;
1698
1699 pipe_w = pipe_config->pipe_src_w;
1700 pipe_h = pipe_config->pipe_src_h;
801bcfff 1701
801bcfff
PZ		 1702 pfit_w = (pfit_size >> 16) & 0xFFFF;
1703 pfit_h = pfit_size & 0xFFFF;
1704 if (pipe_w < pfit_w)
1705 pipe_w = pfit_w;
1706 if (pipe_h < pfit_h)
1707 pipe_h = pfit_h;
1708
15126882
MR		 1709 if (WARN_ON(!pfit_w || !pfit_h))
1710 return pixel_rate;
1711
801bcfff
PZ		 1712 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1713 pfit_w * pfit_h);
1714 }
1715
1716 return pixel_rate;
1717}
1718
37126462 1719/* latency must be in 0.1us units. */
ac484963 1720static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1721{
1722 uint64_t ret;
1723
3312ba65
VS		 1724 if (WARN(latency == 0, "Latency value missing\n"))
1725 return UINT_MAX;
1726
ac484963 1727 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1729
1730 return ret;
1731}
1732
37126462 1733/* latency must be in 0.1us units. */
23297044 1734static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1735 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1736 uint32_t latency)
1737{
1738 uint32_t ret;
1739
3312ba65
VS		 1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
15126882
MR		 1742 if (WARN_ON(!pipe_htotal))
1743 return UINT_MAX;
3312ba65 1744
801bcfff 1745 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1746 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1747 ret = DIV_ROUND_UP(ret, 64) + 2;
1748 return ret;
1749}
1750
23297044 1751static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1752 uint8_t cpp)
cca32e9a 1753{
15126882
MR		 1754 /*
1755 * Neither of these should be possible since this function shouldn't be
1756 * called if the CRTC is off or the plane is invisible. But let's be
1757 * extra paranoid to avoid a potential divide-by-zero if we screw up
1758 * elsewhere in the driver.
1759 */
ac484963 1760 if (WARN_ON(!cpp))
15126882
MR		 1761 return 0;
1762 if (WARN_ON(!horiz_pixels))
1763 return 0;
1764
ac484963 1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1766}
1767
820c1980 1768struct ilk_wm_maximums {
cca32e9a
PZ		 1769 uint16_t pri;
1770 uint16_t spr;
1771 uint16_t cur;
1772 uint16_t fbc;
1773};
1774
37126462
VS		 1775/*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
7221fc33 1779static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1780 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1781 uint32_t mem_value,
1782 bool is_lp)
801bcfff 1783{
ac484963
VS		 1784 int cpp = pstate->base.fb ?
1785 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1786 uint32_t method1, method2;
1787
936e71e3 1788 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1789 return 0;
1790
ac484963 1791 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1792
1793 if (!is_lp)
1794 return method1;
1795
7221fc33
MR		 1796 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1797 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1798 drm_rect_width(&pstate->base.dst),
ac484963 1799 cpp, mem_value);
cca32e9a
PZ		 1800
1801 return min(method1, method2);
801bcfff
PZ		 1802}
1803
37126462
VS		 1804/*
1805 * For both WM_PIPE and WM_LP.
1806 * mem_value must be in 0.1us units.
1807 */
7221fc33 1808static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1809 const struct intel_plane_state *pstate,
801bcfff
PZ		 1810 uint32_t mem_value)
1811{
ac484963
VS		 1812 int cpp = pstate->base.fb ?
1813 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1814 uint32_t method1, method2;
1815
936e71e3 1816 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1817 return 0;
1818
ac484963 1819 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1820 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1821 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1822 drm_rect_width(&pstate->base.dst),
ac484963 1823 cpp, mem_value);
801bcfff
PZ		 1824 return min(method1, method2);
1825}
1826
37126462
VS		 1827/*
1828 * For both WM_PIPE and WM_LP.
1829 * mem_value must be in 0.1us units.
1830 */
7221fc33 1831static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1832 const struct intel_plane_state *pstate,
801bcfff
PZ		 1833 uint32_t mem_value)
1834{
b2435692
MR		 1835 /*
1836 * We treat the cursor plane as always-on for the purposes of watermark
1837 * calculation. Until we have two-stage watermark programming merged,
1838 * this is necessary to avoid flickering.
1839 */
1840 int cpp = 4;
936e71e3 1841 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1842
b2435692 1843 if (!cstate->base.active)
801bcfff
PZ		 1844 return 0;
1845
7221fc33
MR		 1846 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1847 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1848 width, cpp, mem_value);
801bcfff
PZ		 1849}
1850
cca32e9a 1851/* Only for WM_LP. */
7221fc33 1852static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1853 const struct intel_plane_state *pstate,
1fda9882 1854 uint32_t pri_val)
cca32e9a 1855{
ac484963
VS		 1856 int cpp = pstate->base.fb ?
1857 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1858
936e71e3 1859 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1860 return 0;
1861
936e71e3 1862 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1863}
1864
175fded1
TU		 1865static unsigned int
1866ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
158ae64f 1867{
175fded1 1868 if (INTEL_GEN(dev_priv) >= 8)
416f4727 1869 return 3072;
175fded1 1870 else if (INTEL_GEN(dev_priv) >= 7)
158ae64f
VS		 1871 return 768;
1872 else
1873 return 512;
1874}
1875
175fded1
TU		 1876static unsigned int
1877ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1878 int level, bool is_sprite)
4e975081 1879{
175fded1 1880 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1881 /* BDW primary/sprite plane watermarks */
1882 return level == 0 ? 255 : 2047;
175fded1 1883 else if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1884 /* IVB/HSW primary/sprite plane watermarks */
1885 return level == 0 ? 127 : 1023;
1886 else if (!is_sprite)
1887 /* ILK/SNB primary plane watermarks */
1888 return level == 0 ? 127 : 511;
1889 else
1890 /* ILK/SNB sprite plane watermarks */
1891 return level == 0 ? 63 : 255;
1892}
1893
175fded1
TU		 1894static unsigned int
1895ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
4e975081 1896{
175fded1 1897 if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901}
1902
175fded1 1903static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
4e975081 1904{
175fded1 1905 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1906 return 31;
1907 else
1908 return 15;
1909}
1910
158ae64f
VS		 1911/* Calculate the maximum primary/sprite plane watermark */
1912static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1913 int level,
240264f4 1914 const struct intel_wm_config *config,
158ae64f
VS		 1915 enum intel_ddb_partitioning ddb_partitioning,
1916 bool is_sprite)
1917{
175fded1
TU		 1918 struct drm_i915_private *dev_priv = to_i915(dev);
1919 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
158ae64f
VS		 1920
1921 /* if sprites aren't enabled, sprites get nothing */
240264f4 1922 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1923 return 0;
1924
1925 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1926 if (level == 0 || config->num_pipes_active > 1) {
175fded1 1927 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
158ae64f
VS		 1928
1929 /*
1930 * For some reason the non self refresh
1931 * FIFO size is only half of the self
1932 * refresh FIFO size on ILK/SNB.
1933 */
175fded1 1934 if (INTEL_GEN(dev_priv) <= 6)
158ae64f
VS		 1935 fifo_size /= 2;
1936 }
1937
240264f4 1938 if (config->sprites_enabled) {
158ae64f
VS		 1939 /* level 0 is always calculated with 1:1 split */
1940 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1941 if (is_sprite)
1942 fifo_size *= 5;
1943 fifo_size /= 6;
1944 } else {
1945 fifo_size /= 2;
1946 }
1947 }
1948
1949 /* clamp to max that the registers can hold */
175fded1 1950 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
158ae64f
VS		 1951}
1952
1953/* Calculate the maximum cursor plane watermark */
1954static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1955 int level,
1956 const struct intel_wm_config *config)
158ae64f
VS		 1957{
1958 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1959 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1960 return 64;
1961
1962 /* otherwise just report max that registers can hold */
175fded1 1963 return ilk_cursor_wm_reg_max(to_i915(dev), level);
158ae64f
VS		 1964}
1965
d34ff9c6 1966static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1967 int level,
1968 const struct intel_wm_config *config,
1969 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1970 struct ilk_wm_maximums *max)
158ae64f 1971{
240264f4
VS		 1972 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1973 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1974 max->cur = ilk_cursor_wm_max(dev, level, config);
175fded1 1975 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
158ae64f
VS		 1976}
1977
175fded1 1978static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
a3cb4048
VS		 1979 int level,
1980 struct ilk_wm_maximums *max)
1981{
175fded1
TU		 1982 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1983 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1984 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1985 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
a3cb4048
VS		 1986}
1987
d9395655 1988static bool ilk_validate_wm_level(int level,
820c1980 1989 const struct ilk_wm_maximums *max,
d9395655 1990 struct intel_wm_level *result)
a9786a11
VS		 1991{
1992 bool ret;
1993
1994 /* already determined to be invalid? */
1995 if (!result->enable)
1996 return false;
1997
1998 result->enable = result->pri_val <= max->pri &&
1999 result->spr_val <= max->spr &&
2000 result->cur_val <= max->cur;
2001
2002 ret = result->enable;
2003
2004 /*
2005 * HACK until we can pre-compute everything,
2006 * and thus fail gracefully if LP0 watermarks
2007 * are exceeded...
2008 */
2009 if (level == 0 && !result->enable) {
2010 if (result->pri_val > max->pri)
2011 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2012 level, result->pri_val, max->pri);
2013 if (result->spr_val > max->spr)
2014 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2015 level, result->spr_val, max->spr);
2016 if (result->cur_val > max->cur)
2017 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2018 level, result->cur_val, max->cur);
2019
2020 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2021 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2022 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2023 result->enable = true;
2024 }
2025
a9786a11
VS		 2026 return ret;
2027}
2028
d34ff9c6 2029static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2030 const struct intel_crtc *intel_crtc,
6f5ddd17 2031 int level,
7221fc33 2032 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2033 struct intel_plane_state *pristate,
2034 struct intel_plane_state *sprstate,
2035 struct intel_plane_state *curstate,
1fd527cc 2036 struct intel_wm_level *result)
6f5ddd17
VS		 2037{
2038 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2039 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2040 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2041
2042 /* WM1+ latency values stored in 0.5us units */
2043 if (level > 0) {
2044 pri_latency *= 5;
2045 spr_latency *= 5;
2046 cur_latency *= 5;
2047 }
2048
e3bddded
ML		 2049 if (pristate) {
2050 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2051 pri_latency, level);
2052 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2053 }
2054
2055 if (sprstate)
2056 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2057
2058 if (curstate)
2059 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2060
6f5ddd17
VS		 2061 result->enable = true;
2062}
2063
801bcfff 2064static uint32_t
532f7a7f 2065hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2066{
532f7a7f
VS		 2067 const struct intel_atomic_state *intel_state =
2068 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2069 const struct drm_display_mode *adjusted_mode =
2070 &cstate->base.adjusted_mode;
85a02deb 2071 u32 linetime, ips_linetime;
1f8eeabf 2072
ee91a159
MR		 2073 if (!cstate->base.active)
2074 return 0;
2075 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2076 return 0;
532f7a7f 2077 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2078 return 0;
1011d8c4 2079
1f8eeabf
ED		 2080 /* The WM are computed with base on how long it takes to fill a single
2081 * row at the given clock rate, multiplied by 8.
2082 * */
124abe07
VS		 2083 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2084 adjusted_mode->crtc_clock);
2085 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2086 intel_state->cdclk);
1f8eeabf 2087
801bcfff
PZ		 2088 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2089 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2090}
2091
bb726519
VS		 2092static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2093 uint16_t wm[8])
12b134df 2094{
5db94019 2095 if (IS_GEN9(dev_priv)) {
2af30a5c 2096 uint32_t val;
4f947386 2097 int ret, i;
5db94019 2098 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2099
2100 /* read the first set of memory latencies[0:3] */
2101 val = 0; /* data0 to be programmed to 0 for first set */
2102 mutex_lock(&dev_priv->rps.hw_lock);
2103 ret = sandybridge_pcode_read(dev_priv,
2104 GEN9_PCODE_READ_MEM_LATENCY,
2105 &val);
2106 mutex_unlock(&dev_priv->rps.hw_lock);
2107
2108 if (ret) {
2109 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2110 return;
2111 }
2112
2113 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2117 GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120
2121 /* read the second set of memory latencies[4:7] */
2122 val = 1; /* data0 to be programmed to 1 for second set */
2123 mutex_lock(&dev_priv->rps.hw_lock);
2124 ret = sandybridge_pcode_read(dev_priv,
2125 GEN9_PCODE_READ_MEM_LATENCY,
2126 &val);
2127 mutex_unlock(&dev_priv->rps.hw_lock);
2128 if (ret) {
2129 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2130 return;
2131 }
2132
2133 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2137 GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140
0727e40a
PZ		 2141 /*
2142 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2143 * need to be disabled. We make sure to sanitize the values out
2144 * of the punit to satisfy this requirement.
2145 */
2146 for (level = 1; level <= max_level; level++) {
2147 if (wm[level] == 0) {
2148 for (i = level + 1; i <= max_level; i++)
2149 wm[i] = 0;
2150 break;
2151 }
2152 }
2153
367294be 2154 /*
6f97235b
DL		 2155 * WaWmMemoryReadLatency:skl
2156 *
367294be 2157 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2158 * to add 2us to the various latency levels we retrieve from the
2159 * punit when level 0 response data us 0us.
367294be 2160 */
0727e40a
PZ		 2161 if (wm[0] == 0) {
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++) {
2164 if (wm[level] == 0)
2165 break;
367294be 2166 wm[level] += 2;
4f947386 2167 }
0727e40a
PZ		 2168 }
2169
8652744b 2170 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2171 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> 56) & 0xFF;
2174 if (wm[0] == 0)
2175 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2176 wm[1] = (sskpd >> 4) & 0xFF;
2177 wm[2] = (sskpd >> 12) & 0xFF;
2178 wm[3] = (sskpd >> 20) & 0x1FF;
2179 wm[4] = (sskpd >> 32) & 0x1FF;
bb726519 2180 } else if (INTEL_GEN(dev_priv) >= 6) {
63cf9a13
VS		 2181 uint32_t sskpd = I915_READ(MCH_SSKPD);
2182
2183 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2184 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2185 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2186 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
bb726519 2187 } else if (INTEL_GEN(dev_priv) >= 5) {
3a88d0ac
VS		 2188 uint32_t mltr = I915_READ(MLTR_ILK);
2189
2190 /* ILK primary LP0 latency is 700 ns */
2191 wm[0] = 7;
2192 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2193 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2194 }
2195}
2196
5db94019
TU		 2197static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2198 uint16_t wm[5])
53615a5e
VS		 2199{
2200 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2201 if (IS_GEN5(dev_priv))
53615a5e
VS		 2202 wm[0] = 13;
2203}
2204
fd6b8f43
TU		 2205static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2206 uint16_t wm[5])
53615a5e
VS		 2207{
2208 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2209 if (IS_GEN5(dev_priv))
53615a5e
VS		 2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2213 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2214 wm[3] *= 2;
2215}
2216
5db94019 2217int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2218{
26ec971e 2219 /* how many WM levels are we expecting */
8652744b 2220 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2221 return 7;
8652744b 2222 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2223 return 4;
8652744b 2224 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2225 return 3;
26ec971e 2226 else
ad0d6dc4
VS		 2227 return 2;
2228}
7526ed79 2229
5db94019 2230static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2231 const char *name,
2af30a5c 2232 const uint16_t wm[8])
ad0d6dc4 2233{
5db94019 2234 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2af30a5c
PB		 2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
5db94019 2249 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2250 latency *= 10;
2251 else if (level > 0)
26ec971e
VS		 2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258}
2259
e95a2f75
VS		 2260static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262{
5db94019 2263 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273}
2274
bb726519 2275static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
e95a2f75 2276{
e95a2f75
VS		 2277 bool changed;
2278
2279 /*
2280 * The BIOS provided WM memory latency values are often
2281 * inadequate for high resolution displays. Adjust them.
2282 */
2283 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2284 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2286
2287 if (!changed)
2288 return;
2289
2290 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2291 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2292 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2293 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2294}
2295
bb726519 2296static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
53615a5e 2297{
bb726519 2298 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
53615a5e
VS		 2299
2300 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2301 sizeof(dev_priv->wm.pri_latency));
2302 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2303 sizeof(dev_priv->wm.pri_latency));
2304
5db94019 2305 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2306 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2307
5db94019
TU		 2308 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2309 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2310 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2311
5db94019 2312 if (IS_GEN6(dev_priv))
bb726519 2313 snb_wm_latency_quirk(dev_priv);
53615a5e
VS		 2314}
2315
bb726519 2316static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2af30a5c 2317{
bb726519 2318 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
5db94019 2319 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2320}
2321
ed4a6a7c
MR		 2322static bool ilk_validate_pipe_wm(struct drm_device *dev,
2323 struct intel_pipe_wm *pipe_wm)
2324{
2325 /* LP0 watermark maximums depend on this pipe alone */
2326 const struct intel_wm_config config = {
2327 .num_pipes_active = 1,
2328 .sprites_enabled = pipe_wm->sprites_enabled,
2329 .sprites_scaled = pipe_wm->sprites_scaled,
2330 };
2331 struct ilk_wm_maximums max;
2332
2333 /* LP0 watermarks always use 1/2 DDB partitioning */
2334 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2335
2336 /* At least LP0 must be valid */
2337 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2338 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2339 return false;
2340 }
2341
2342 return true;
2343}
2344
0b2ae6d7 2345/* Compute new watermarks for the pipe */
e3bddded 2346static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2347{
e3bddded
ML		 2348 struct drm_atomic_state *state = cstate->base.state;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2350 struct intel_pipe_wm *pipe_wm;
e3bddded 2351 struct drm_device *dev = state->dev;
fac5e23e 2352 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2353 struct intel_plane *intel_plane;
86c8bbbe 2354 struct intel_plane_state *pristate = NULL;
43d59eda 2355 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2356 struct intel_plane_state *curstate = NULL;
5db94019 2357 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2358 struct ilk_wm_maximums max;
0b2ae6d7 2359
e8f1f02e 2360 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2361
43d59eda 2362 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2363 struct intel_plane_state *ps;
2364
2365 ps = intel_atomic_get_existing_plane_state(state,
2366 intel_plane);
2367 if (!ps)
2368 continue;
86c8bbbe
MR		 2369
2370 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2371 pristate = ps;
86c8bbbe 2372 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2373 sprstate = ps;
86c8bbbe 2374 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2375 curstate = ps;
43d59eda
MR		 2376 }
2377
ed4a6a7c 2378 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2379 if (sprstate) {
936e71e3
VS		 2380 pipe_wm->sprites_enabled = sprstate->base.visible;
2381 pipe_wm->sprites_scaled = sprstate->base.visible &&
2382 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2383 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2384 }
2385
d81f04c5
ML		 2386 usable_level = max_level;
2387
7b39a0b7 2388 /* ILK/SNB: LP2+ watermarks only w/o sprites */
175fded1 2389 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2390 usable_level = 1;
7b39a0b7
VS		 2391
2392 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2393 if (pipe_wm->sprites_scaled)
d81f04c5 2394 usable_level = 0;
7b39a0b7 2395
86c8bbbe 2396 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2397 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2398
2399 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2400 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2401
8652744b 2402 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2403 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2404
ed4a6a7c 2405 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2406 return -EINVAL;
a3cb4048 2407
175fded1 2408 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
a3cb4048
VS		 2409
2410 for (level = 1; level <= max_level; level++) {
71f0a626 2411 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2412
86c8bbbe 2413 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2414 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2415
2416 /*
2417 * Disable any watermark level that exceeds the
2418 * register maximums since such watermarks are
2419 * always invalid.
2420 */
71f0a626
ML		 2421 if (level > usable_level)
2422 continue;
2423
2424 if (ilk_validate_wm_level(level, &max, wm))
2425 pipe_wm->wm[level] = *wm;
2426 else
d81f04c5 2427 usable_level = level;
a3cb4048
VS		 2428 }
2429
86c8bbbe 2430 return 0;
0b2ae6d7
VS		 2431}
2432
ed4a6a7c
MR		 2433/*
2434 * Build a set of 'intermediate' watermark values that satisfy both the old
2435 * state and the new state. These can be programmed to the hardware
2436 * immediately.
2437 */
2438static int ilk_compute_intermediate_wm(struct drm_device *dev,
2439 struct intel_crtc *intel_crtc,
2440 struct intel_crtc_state *newstate)
2441{
e8f1f02e 2442 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2443 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2444 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2445
2446 /*
2447 * Start with the final, target watermarks, then combine with the
2448 * currently active watermarks to get values that are safe both before
2449 * and after the vblank.
2450 */
e8f1f02e 2451 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2452 a->pipe_enabled |= b->pipe_enabled;
2453 a->sprites_enabled |= b->sprites_enabled;
2454 a->sprites_scaled |= b->sprites_scaled;
2455
2456 for (level = 0; level <= max_level; level++) {
2457 struct intel_wm_level *a_wm = &a->wm[level];
2458 const struct intel_wm_level *b_wm = &b->wm[level];
2459
2460 a_wm->enable &= b_wm->enable;
2461 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2462 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2463 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2464 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2465 }
2466
2467 /*
2468 * We need to make sure that these merged watermark values are
2469 * actually a valid configuration themselves. If they're not,
2470 * there's no safe way to transition from the old state to
2471 * the new state, so we need to fail the atomic transaction.
2472 */
2473 if (!ilk_validate_pipe_wm(dev, a))
2474 return -EINVAL;
2475
2476 /*
2477 * If our intermediate WM are identical to the final WM, then we can
2478 * omit the post-vblank programming; only update if it's different.
2479 */
e8f1f02e 2480 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2481 newstate->wm.need_postvbl_update = false;
2482
2483 return 0;
2484}
2485
0b2ae6d7
VS		 2486/*
2487 * Merge the watermarks from all active pipes for a specific level.
2488 */
2489static void ilk_merge_wm_level(struct drm_device *dev,
2490 int level,
2491 struct intel_wm_level *ret_wm)
2492{
2493 const struct intel_crtc *intel_crtc;
2494
d52fea5b
VS		 2495 ret_wm->enable = true;
2496
d3fcc808 2497 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2498 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2499 const struct intel_wm_level *wm = &active->wm[level];
2500
2501 if (!active->pipe_enabled)
2502 continue;
0b2ae6d7 2503
d52fea5b
VS		 2504 /*
2505 * The watermark values may have been used in the past,
2506 * so we must maintain them in the registers for some
2507 * time even if the level is now disabled.
2508 */
0b2ae6d7 2509 if (!wm->enable)
d52fea5b 2510 ret_wm->enable = false;
0b2ae6d7
VS		 2511
2512 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2513 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2514 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2515 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2516 }
0b2ae6d7
VS		 2517}
2518
2519/*
2520 * Merge all low power watermarks for all active pipes.
2521 */
2522static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2523 const struct intel_wm_config *config,
820c1980 2524 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2525 struct intel_pipe_wm *merged)
2526{
fac5e23e 2527 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2528 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2529 int last_enabled_level = max_level;
0b2ae6d7 2530
0ba22e26 2531 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2532 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2533 config->num_pipes_active > 1)
1204d5ba 2534 last_enabled_level = 0;
0ba22e26 2535
6c8b6c28 2536 /* ILK: FBC WM must be disabled always */
175fded1 2537 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
0b2ae6d7
VS		 2538
2539 /* merge each WM1+ level */
2540 for (level = 1; level <= max_level; level++) {
2541 struct intel_wm_level *wm = &merged->wm[level];
2542
2543 ilk_merge_wm_level(dev, level, wm);
2544
d52fea5b
VS		 2545 if (level > last_enabled_level)
2546 wm->enable = false;
2547 else if (!ilk_validate_wm_level(level, max, wm))
2548 /* make sure all following levels get disabled */
2549 last_enabled_level = level - 1;
0b2ae6d7
VS		 2550
2551 /*
2552 * The spec says it is preferred to disable
2553 * FBC WMs instead of disabling a WM level.
2554 */
2555 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2556 if (wm->enable)
2557 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2558 wm->fbc_val = 0;
2559 }
2560 }
6c8b6c28
VS		 2561
2562 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2563 /*
2564 * FIXME this is racy. FBC might get enabled later.
2565 * What we should check here is whether FBC can be
2566 * enabled sometime later.
2567 */
5db94019 2568 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2569 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2570 for (level = 2; level <= max_level; level++) {
2571 struct intel_wm_level *wm = &merged->wm[level];
2572
2573 wm->enable = false;
2574 }
2575 }
0b2ae6d7
VS		 2576}
2577
b380ca3c
VS		 2578static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2579{
2580 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2581 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2582}
2583
a68d68ee
VS		 2584/* The value we need to program into the WM_LPx latency field */
2585static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2586{
fac5e23e 2587 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2588
8652744b 2589 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2590 return 2 * level;
2591 else
2592 return dev_priv->wm.pri_latency[level];
2593}
2594
820c1980 2595static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2596 const struct intel_pipe_wm *merged,
609cedef 2597 enum intel_ddb_partitioning partitioning,
820c1980 2598 struct ilk_wm_values *results)
801bcfff 2599{
175fded1 2600 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7
VS		 2601 struct intel_crtc *intel_crtc;
2602 int level, wm_lp;
cca32e9a 2603
0362c781 2604 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2605 results->partitioning = partitioning;
cca32e9a 2606
0b2ae6d7 2607 /* LP1+ register values */
cca32e9a 2608 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2609 const struct intel_wm_level *r;
801bcfff 2610
b380ca3c 2611 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2612
0362c781 2613 r = &merged->wm[level];
cca32e9a 2614
d52fea5b
VS		 2615 /*
2616 * Maintain the watermark values even if the level is
2617 * disabled. Doing otherwise could cause underruns.
2618 */
2619 results->wm_lp[wm_lp - 1] =
a68d68ee 2620 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2621 (r->pri_val << WM1_LP_SR_SHIFT) |
2622 r->cur_val;
2623
d52fea5b
VS		 2624 if (r->enable)
2625 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2626
175fded1 2627 if (INTEL_GEN(dev_priv) >= 8)
416f4727
VS		 2628 results->wm_lp[wm_lp - 1] |=
2629 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2630 else
2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT;
2633
d52fea5b
VS		 2634 /*
2635 * Always set WM1S_LP_EN when spr_val != 0, even if the
2636 * level is disabled. Doing otherwise could cause underruns.
2637 */
175fded1 2638 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
6cef2b8a
VS		 2639 WARN_ON(wm_lp != 1);
2640 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2641 } else
2642 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2643 }
801bcfff 2644
0b2ae6d7 2645 /* LP0 register values */
d3fcc808 2646 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2647 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2648 const struct intel_wm_level *r =
2649 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2650
2651 if (WARN_ON(!r->enable))
2652 continue;
2653
ed4a6a7c 2654 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2655
0b2ae6d7
VS		 2656 results->wm_pipe[pipe] =
2657 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2658 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2659 r->cur_val;
801bcfff
PZ		 2660 }
2661}
2662
861f3389
PZ		 2663/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2664 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2665static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2666 struct intel_pipe_wm *r1,
2667 struct intel_pipe_wm *r2)
861f3389 2668{
5db94019 2669 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2670 int level1 = 0, level2 = 0;
861f3389 2671
198a1e9b
VS		 2672 for (level = 1; level <= max_level; level++) {
2673 if (r1->wm[level].enable)
2674 level1 = level;
2675 if (r2->wm[level].enable)
2676 level2 = level;
861f3389
PZ		 2677 }
2678
198a1e9b
VS		 2679 if (level1 == level2) {
2680 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2681 return r2;
2682 else
2683 return r1;
198a1e9b 2684 } else if (level1 > level2) {
861f3389
PZ		 2685 return r1;
2686 } else {
2687 return r2;
2688 }
2689}
2690
49a687c4
VS		 2691/* dirty bits used to track which watermarks need changes */
2692#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2693#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2694#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2695#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2696#define WM_DIRTY_FBC (1 << 24)
2697#define WM_DIRTY_DDB (1 << 25)
2698
055e393f 2699static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2700 const struct ilk_wm_values *old,
2701 const struct ilk_wm_values *new)
49a687c4
VS		 2702{
2703 unsigned int dirty = 0;
2704 enum pipe pipe;
2705 int wm_lp;
2706
055e393f 2707 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2708 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2709 dirty |= WM_DIRTY_LINETIME(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713
2714 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2715 dirty |= WM_DIRTY_PIPE(pipe);
2716 /* Must disable LP1+ watermarks too */
2717 dirty |= WM_DIRTY_LP_ALL;
2718 }
2719 }
2720
2721 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2722 dirty |= WM_DIRTY_FBC;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 if (old->partitioning != new->partitioning) {
2728 dirty |= WM_DIRTY_DDB;
2729 /* Must disable LP1+ watermarks too */
2730 dirty |= WM_DIRTY_LP_ALL;
2731 }
2732
2733 /* LP1+ watermarks already deemed dirty, no need to continue */
2734 if (dirty & WM_DIRTY_LP_ALL)
2735 return dirty;
2736
2737 /* Find the lowest numbered LP1+ watermark in need of an update... */
2738 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2739 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2740 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2741 break;
2742 }
2743
2744 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2745 for (; wm_lp <= 3; wm_lp++)
2746 dirty |= WM_DIRTY_LP(wm_lp);
2747
2748 return dirty;
2749}
2750
8553c18e
VS		 2751static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2752 unsigned int dirty)
801bcfff 2753{
820c1980 2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2755 bool changed = false;
801bcfff 2756
facd619b
VS		 2757 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2758 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2760 changed = true;
facd619b
VS		 2761 }
2762 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2763 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2765 changed = true;
facd619b
VS		 2766 }
2767 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2768 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2769 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2770 changed = true;
facd619b 2771 }
801bcfff 2772
facd619b
VS		 2773 /*
2774 * Don't touch WM1S_LP_EN here.
2775 * Doing so could cause underruns.
2776 */
6cef2b8a 2777
8553c18e
VS		 2778 return changed;
2779}
2780
2781/*
2782 * The spec says we shouldn't write when we don't need, because every write
2783 * causes WMs to be re-evaluated, expending some power.
2784 */
820c1980
ID		 2785static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2786 struct ilk_wm_values *results)
8553c18e 2787{
820c1980 2788 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2789 unsigned int dirty;
2790 uint32_t val;
2791
055e393f 2792 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2793 if (!dirty)
2794 return;
2795
2796 _ilk_disable_lp_wm(dev_priv, dirty);
2797
49a687c4 2798 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2799 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2800 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2801 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2802 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2803 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2804
49a687c4 2805 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2807 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2808 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2809 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2810 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2811
49a687c4 2812 if (dirty & WM_DIRTY_DDB) {
8652744b 2813 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2814 val = I915_READ(WM_MISC);
2815 if (results->partitioning == INTEL_DDB_PART_1_2)
2816 val &= ~WM_MISC_DATA_PARTITION_5_6;
2817 else
2818 val |= WM_MISC_DATA_PARTITION_5_6;
2819 I915_WRITE(WM_MISC, val);
2820 } else {
2821 val = I915_READ(DISP_ARB_CTL2);
2822 if (results->partitioning == INTEL_DDB_PART_1_2)
2823 val &= ~DISP_DATA_PARTITION_5_6;
2824 else
2825 val |= DISP_DATA_PARTITION_5_6;
2826 I915_WRITE(DISP_ARB_CTL2, val);
2827 }
1011d8c4
PZ		 2828 }
2829
49a687c4 2830 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2831 val = I915_READ(DISP_ARB_CTL);
2832 if (results->enable_fbc_wm)
2833 val &= ~DISP_FBC_WM_DIS;
2834 else
2835 val |= DISP_FBC_WM_DIS;
2836 I915_WRITE(DISP_ARB_CTL, val);
2837 }
2838
954911eb
ID		 2839 if (dirty & WM_DIRTY_LP(1) &&
2840 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2841 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2842
175fded1 2843 if (INTEL_GEN(dev_priv) >= 7) {
6cef2b8a
VS		 2844 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2845 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2846 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2847 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2848 }
801bcfff 2849
facd619b 2850 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2852 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2854 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2856
2857 dev_priv->wm.hw = *results;
801bcfff
PZ		 2858}
2859
ed4a6a7c 2860bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2861{
fac5e23e 2862 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2863
2864 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2865}
2866
656d1b89 2867#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2868
024c9045
MR		 2869/*
2870 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2871 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2872 * other universal planes are in indices 1..n. Note that this may leave unused
2873 * indices between the top "sprite" plane and the cursor.
2874 */
2875static int
2876skl_wm_plane_id(const struct intel_plane *plane)
2877{
2878 switch (plane->base.type) {
2879 case DRM_PLANE_TYPE_PRIMARY:
2880 return 0;
2881 case DRM_PLANE_TYPE_CURSOR:
2882 return PLANE_CURSOR;
2883 case DRM_PLANE_TYPE_OVERLAY:
2884 return plane->plane + 1;
2885 default:
2886 MISSING_CASE(plane->base.type);
2887 return plane->plane;
2888 }
2889}
2890
ee3d532f
PZ		 2891/*
2892 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2893 * so assume we'll always need it in order to avoid underruns.
2894 */
2895static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2896{
2897 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2898
2899 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2900 IS_KABYLAKE(dev_priv))
2901 return true;
2902
2903 return false;
2904}
2905
56feca91
PZ		 2906static bool
2907intel_has_sagv(struct drm_i915_private *dev_priv)
2908{
6e3100ec
PZ		 2909 if (IS_KABYLAKE(dev_priv))
2910 return true;
2911
2912 if (IS_SKYLAKE(dev_priv) &&
2913 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2914 return true;
2915
2916 return false;
56feca91
PZ		 2917}
2918
656d1b89
L		 2919/*
2920 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2921 * depending on power and performance requirements. The display engine access
2922 * to system memory is blocked during the adjustment time. Because of the
2923 * blocking time, having this enabled can cause full system hangs and/or pipe
2924 * underruns if we don't meet all of the following requirements:
2925 *
2926 * - <= 1 pipe enabled
2927 * - All planes can enable watermarks for latencies >= SAGV engine block time
2928 * - We're not using an interlaced display configuration
2929 */
2930int
16dcdc4e 2931intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2932{
2933 int ret;
2934
56feca91
PZ		 2935 if (!intel_has_sagv(dev_priv))
2936 return 0;
2937
2938 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2939 return 0;
2940
2941 DRM_DEBUG_KMS("Enabling the SAGV\n");
2942 mutex_lock(&dev_priv->rps.hw_lock);
2943
2944 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2945 GEN9_SAGV_ENABLE);
2946
2947 /* We don't need to wait for the SAGV when enabling */
2948 mutex_unlock(&dev_priv->rps.hw_lock);
2949
2950 /*
2951 * Some skl systems, pre-release machines in particular,
2952 * don't actually have an SAGV.
2953 */
6e3100ec 2954 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2955 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2956 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2957 return 0;
2958 } else if (ret < 0) {
2959 DRM_ERROR("Failed to enable the SAGV\n");
2960 return ret;
2961 }
2962
16dcdc4e 2963 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2964 return 0;
2965}
2966
2967static int
16dcdc4e 2968intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2969{
2970 int ret;
2971 uint32_t temp = GEN9_SAGV_DISABLE;
2972
2973 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2974 &temp);
2975 if (ret)
2976 return ret;
2977 else
2978 return temp & GEN9_SAGV_IS_DISABLED;
2979}
2980
2981int
16dcdc4e 2982intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2983{
2984 int ret, result;
2985
56feca91
PZ		 2986 if (!intel_has_sagv(dev_priv))
2987 return 0;
2988
2989 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2990 return 0;
2991
2992 DRM_DEBUG_KMS("Disabling the SAGV\n");
2993 mutex_lock(&dev_priv->rps.hw_lock);
2994
2995 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2996 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2997 mutex_unlock(&dev_priv->rps.hw_lock);
2998
2999 if (ret == -ETIMEDOUT) {
3000 DRM_ERROR("Request to disable SAGV timed out\n");
3001 return -ETIMEDOUT;
3002 }
3003
3004 /*
3005 * Some skl systems, pre-release machines in particular,
3006 * don't actually have an SAGV.
3007 */
6e3100ec 3008 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3009 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3010 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3011 return 0;
3012 } else if (result < 0) {
3013 DRM_ERROR("Failed to disable the SAGV\n");
3014 return result;
3015 }
3016
16dcdc4e 3017 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3018 return 0;
3019}
3020
16dcdc4e 3021bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3022{
3023 struct drm_device *dev = state->dev;
3024 struct drm_i915_private *dev_priv = to_i915(dev);
3025 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3026 struct intel_crtc *crtc;
3027 struct intel_plane *plane;
d8c0fafc 3028 struct intel_crtc_state *cstate;
3029 struct skl_plane_wm *wm;
656d1b89 3030 enum pipe pipe;
d8c0fafc 3031 int level, latency;
656d1b89 3032
56feca91
PZ		 3033 if (!intel_has_sagv(dev_priv))
3034 return false;
3035
656d1b89
L		 3036 /*
3037 * SKL workaround: bspec recommends we disable the SAGV when we have
3038 * more then one pipe enabled
3039 *
3040 * If there are no active CRTCs, no additional checks need be performed
3041 */
3042 if (hweight32(intel_state->active_crtcs) == 0)
3043 return true;
3044 else if (hweight32(intel_state->active_crtcs) > 1)
3045 return false;
3046
3047 /* Since we're now guaranteed to only have one active CRTC... */
3048 pipe = ffs(intel_state->active_crtcs) - 1;
98187836 3049 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
d8c0fafc 3050 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3051
c89cadd5 3052 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3053 return false;
3054
ee3d532f 3055 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3056 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3057
656d1b89 3058 /* Skip this plane if it's not enabled */
d8c0fafc 3059 if (!wm->wm[0].plane_en)
656d1b89
L		 3060 continue;
3061
3062 /* Find the highest enabled wm level for this plane */
5db94019 3063 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3064 !wm->wm[level].plane_en; --level)
656d1b89
L		 3065 { }
3066
ee3d532f
PZ		 3067 latency = dev_priv->wm.skl_latency[level];
3068
3069 if (skl_needs_memory_bw_wa(intel_state) &&
3070 plane->base.state->fb->modifier[0] ==
3071 I915_FORMAT_MOD_X_TILED)
3072 latency += 15;
3073
656d1b89
L		 3074 /*
3075 * If any of the planes on this pipe don't enable wm levels
3076 * that incur memory latencies higher then 30µs we can't enable
3077 * the SAGV
3078 */
ee3d532f 3079 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3080 return false;
3081 }
3082
3083 return true;
3084}
3085
b9cec075
DL		 3086static void
3087skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3088 const struct intel_crtc_state *cstate,
c107acfe
MR		 3089 struct skl_ddb_entry *alloc, /* out */
3090 int *num_active /* out */)
b9cec075 3091{
c107acfe
MR		 3092 struct drm_atomic_state *state = cstate->base.state;
3093 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3094 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3095 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3096 unsigned int pipe_size, ddb_size;
3097 int nth_active_pipe;
c107acfe 3098
a6d3460e 3099 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3100 alloc->start = 0;
3101 alloc->end = 0;
a6d3460e 3102 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3103 return;
3104 }
3105
a6d3460e
MR		 3106 if (intel_state->active_pipe_changes)
3107 *num_active = hweight32(intel_state->active_crtcs);
3108 else
3109 *num_active = hweight32(dev_priv->active_crtcs);
3110
6f3fff60
D		 3111 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3112 WARN_ON(ddb_size == 0);
b9cec075
DL		 3113
3114 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3115
c107acfe 3116 /*
a6d3460e
MR		 3117 * If the state doesn't change the active CRTC's, then there's
3118 * no need to recalculate; the existing pipe allocation limits
3119 * should remain unchanged. Note that we're safe from racing
3120 * commits since any racing commit that changes the active CRTC
3121 * list would need to grab _all_ crtc locks, including the one
3122 * we currently hold.
c107acfe 3123 */
a6d3460e 3124 if (!intel_state->active_pipe_changes) {
512b5527
ML		 3125 /*
3126 * alloc may be cleared by clear_intel_crtc_state,
3127 * copy from old state to be sure
3128 */
3129 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
a6d3460e 3130 return;
c107acfe 3131 }
a6d3460e
MR		 3132
3133 nth_active_pipe = hweight32(intel_state->active_crtcs &
3134 (drm_crtc_mask(for_crtc) - 1));
3135 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3136 alloc->start = nth_active_pipe * ddb_size / *num_active;
3137 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3138}
3139
c107acfe 3140static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3141{
c107acfe 3142 if (num_active == 1)
b9cec075
DL		 3143 return 32;
3144
3145 return 8;
3146}
3147
a269c583
DL		 3148static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3149{
3150 entry->start = reg & 0x3ff;
3151 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3152 if (entry->end)
3153 entry->end += 1;
a269c583
DL		 3154}
3155
08db6652
DL		 3156void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3157 struct skl_ddb_allocation *ddb /* out */)
a269c583 3158{
a269c583
DL		 3159 enum pipe pipe;
3160 int plane;
3161 u32 val;
3162
b10f1b20
ML		 3163 memset(ddb, 0, sizeof(*ddb));
3164
a269c583 3165 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3166 enum intel_display_power_domain power_domain;
3167
3168 power_domain = POWER_DOMAIN_PIPE(pipe);
3169 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3170 continue;
3171
8b364b41 3172 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3173 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3174 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3175 val);
3176 }
3177
3178 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3179 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3180 val);
4d800030
ID		 3181
3182 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3183 }
3184}
3185
9c2f7a9d
KM		 3186/*
3187 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3188 * The bspec defines downscale amount as:
3189 *
3190 * """
3191 * Horizontal down scale amount = maximum[1, Horizontal source size /
3192 * Horizontal destination size]
3193 * Vertical down scale amount = maximum[1, Vertical source size /
3194 * Vertical destination size]
3195 * Total down scale amount = Horizontal down scale amount *
3196 * Vertical down scale amount
3197 * """
3198 *
3199 * Return value is provided in 16.16 fixed point form to retain fractional part.
3200 * Caller should take care of dividing & rounding off the value.
3201 */
3202static uint32_t
3203skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3204{
3205 uint32_t downscale_h, downscale_w;
3206 uint32_t src_w, src_h, dst_w, dst_h;
3207
936e71e3 3208 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3209 return DRM_PLANE_HELPER_NO_SCALING;
3210
3211 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3212 src_w = drm_rect_width(&pstate->base.src);
3213 src_h = drm_rect_height(&pstate->base.src);
3214 dst_w = drm_rect_width(&pstate->base.dst);
3215 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3216 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3217 swap(dst_w, dst_h);
3218
3219 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3220 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3221
3222 /* Provide result in 16.16 fixed point */
3223 return (uint64_t)downscale_w * downscale_h >> 16;
3224}
3225
b9cec075 3226static unsigned int
024c9045
MR		 3227skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3228 const struct drm_plane_state *pstate,
3229 int y)
b9cec075 3230{
a280f7dd 3231 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3232 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3233 uint32_t down_scale_amount, data_rate;
a280f7dd 3234 uint32_t width = 0, height = 0;
a1de91e5
MR		 3235 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3236
936e71e3 3237 if (!intel_pstate->base.visible)
a1de91e5
MR		 3238 return 0;
3239 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3240 return 0;
3241 if (y && format != DRM_FORMAT_NV12)
3242 return 0;
a280f7dd 3243
936e71e3
VS		 3244 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3245 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3246
bd2ef25d 3247 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3248 swap(width, height);
2cd601c6
CK		 3249
3250 /* for planar format */
a1de91e5 3251 if (format == DRM_FORMAT_NV12) {
2cd601c6 3252 if (y) /* y-plane data rate */
8d19d7d9 3253 data_rate = width * height *
a1de91e5 3254 drm_format_plane_cpp(format, 0);
2cd601c6 3255 else /* uv-plane data rate */
8d19d7d9 3256 data_rate = (width / 2) * (height / 2) *
a1de91e5 3257 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3258 } else {
3259 /* for packed formats */
3260 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3261 }
3262
8d19d7d9
KM		 3263 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3264
3265 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3266}
3267
3268/*
3269 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3270 * a 8192x4096@32bpp framebuffer:
3271 * 3 * 4096 * 8192 * 4 < 2^32
3272 */
3273static unsigned int
1e6ee542
ML		 3274skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3275 unsigned *plane_data_rate,
3276 unsigned *plane_y_data_rate)
b9cec075 3277{
9c74d826
MR		 3278 struct drm_crtc_state *cstate = &intel_cstate->base;
3279 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3280 struct drm_plane *plane;
024c9045 3281 const struct intel_plane *intel_plane;
c8fe32c1 3282 const struct drm_plane_state *pstate;
a1de91e5 3283 unsigned int rate, total_data_rate = 0;
9c74d826 3284 int id;
a6d3460e
MR		 3285
3286 if (WARN_ON(!state))
3287 return 0;
b9cec075 3288
a1de91e5 3289 /* Calculate and cache data rate for each plane */
c8fe32c1 3290 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3291 id = skl_wm_plane_id(to_intel_plane(plane));
3292 intel_plane = to_intel_plane(plane);
3293
a6d3460e
MR		 3294 /* packed/uv */
3295 rate = skl_plane_relative_data_rate(intel_cstate,
3296 pstate, 0);
1e6ee542
ML		 3297 plane_data_rate[id] = rate;
3298
3299 total_data_rate += rate;
a6d3460e
MR		 3300
3301 /* y-plane */
3302 rate = skl_plane_relative_data_rate(intel_cstate,
3303 pstate, 1);
1e6ee542 3304 plane_y_data_rate[id] = rate;
024c9045 3305
1e6ee542 3306 total_data_rate += rate;
b9cec075
DL		 3307 }
3308
3309 return total_data_rate;
3310}
3311
cbcfd14b
KM		 3312static uint16_t
3313skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3314 const int y)
3315{
3316 struct drm_framebuffer *fb = pstate->fb;
3317 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3318 uint32_t src_w, src_h;
3319 uint32_t min_scanlines = 8;
3320 uint8_t plane_bpp;
3321
3322 if (WARN_ON(!fb))
3323 return 0;
3324
3325 /* For packed formats, no y-plane, return 0 */
3326 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3327 return 0;
3328
3329 /* For Non Y-tile return 8-blocks */
3330 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3331 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3332 return 8;
3333
936e71e3
VS		 3334 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3335 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3336
bd2ef25d 3337 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3338 swap(src_w, src_h);
3339
3340 /* Halve UV plane width and height for NV12 */
3341 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3342 src_w /= 2;
3343 src_h /= 2;
3344 }
3345
3346 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3347 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3348 else
3349 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3350
bd2ef25d 3351 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3352 switch (plane_bpp) {
3353 case 1:
3354 min_scanlines = 32;
3355 break;
3356 case 2:
3357 min_scanlines = 16;
3358 break;
3359 case 4:
3360 min_scanlines = 8;
3361 break;
3362 case 8:
3363 min_scanlines = 4;
3364 break;
3365 default:
3366 WARN(1, "Unsupported pixel depth %u for rotation",
3367 plane_bpp);
3368 min_scanlines = 32;
3369 }
3370 }
3371
3372 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3373}
3374
49845a7a
ML		 3375static void
3376skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3377 uint16_t *minimum, uint16_t *y_minimum)
3378{
3379 const struct drm_plane_state *pstate;
3380 struct drm_plane *plane;
3381
3382 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3383 struct intel_plane *intel_plane = to_intel_plane(plane);
3384 int id = skl_wm_plane_id(intel_plane);
3385
3386 if (id == PLANE_CURSOR)
3387 continue;
3388
3389 if (!pstate->visible)
3390 continue;
3391
3392 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3393 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3394 }
3395
3396 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3397}
3398
c107acfe 3399static int
024c9045 3400skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3401 struct skl_ddb_allocation *ddb /* out */)
3402{
c107acfe 3403 struct drm_atomic_state *state = cstate->base.state;
024c9045 3404 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3405 struct drm_device *dev = crtc->dev;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3408 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3409 uint16_t alloc_size, start;
fefdd810
ML		 3410 uint16_t minimum[I915_MAX_PLANES] = {};
3411 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3412 unsigned int total_data_rate;
c107acfe
MR		 3413 int num_active;
3414 int id, i;
1e6ee542
ML		 3415 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3416 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3417
5a920b85
PZ		 3418 /* Clear the partitioning for disabled planes. */
3419 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3420 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3421
a6d3460e
MR		 3422 if (WARN_ON(!state))
3423 return 0;
3424
c107acfe 3425 if (!cstate->base.active) {
ce0ba283 3426 alloc->start = alloc->end = 0;
c107acfe
MR		 3427 return 0;
3428 }
3429
a6d3460e 3430 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3431 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3432 if (alloc_size == 0) {
3433 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3434 return 0;
b9cec075
DL		 3435 }
3436
49845a7a 3437 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3438
49845a7a
ML		 3439 /*
3440 * 1. Allocate the mininum required blocks for each active plane
3441 * and allocate the cursor, it doesn't require extra allocation
3442 * proportional to the data rate.
3443 */
80958155 3444
49845a7a 3445 for (i = 0; i < I915_MAX_PLANES; i++) {
c107acfe
MR		 3446 alloc_size -= minimum[i];
3447 alloc_size -= y_minimum[i];
80958155
DL		 3448 }
3449
49845a7a
ML		 3450 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3451 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3452
b9cec075 3453 /*
80958155
DL		 3454 * 2. Distribute the remaining space in proportion to the amount of
3455 * data each plane needs to fetch from memory.
b9cec075
DL		 3456 *
3457 * FIXME: we may not allocate every single block here.
3458 */
1e6ee542
ML		 3459 total_data_rate = skl_get_total_relative_data_rate(cstate,
3460 plane_data_rate,
3461 plane_y_data_rate);
a1de91e5 3462 if (total_data_rate == 0)
c107acfe 3463 return 0;
b9cec075 3464
34bb56af 3465 start = alloc->start;
1e6ee542 3466 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3467 unsigned int data_rate, y_data_rate;
3468 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3469
49845a7a
ML		 3470 if (id == PLANE_CURSOR)
3471 continue;
3472
1e6ee542 3473 data_rate = plane_data_rate[id];
b9cec075
DL		 3474
3475 /*
2cd601c6 3476 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3477 * promote the expression to 64 bits to avoid overflowing, the
3478 * result is < available as data_rate / total_data_rate < 1
3479 */
024c9045 3480 plane_blocks = minimum[id];
80958155
DL		 3481 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3482 total_data_rate);
b9cec075 3483
c107acfe
MR		 3484 /* Leave disabled planes at (0,0) */
3485 if (data_rate) {
3486 ddb->plane[pipe][id].start = start;
3487 ddb->plane[pipe][id].end = start + plane_blocks;
3488 }
b9cec075
DL		 3489
3490 start += plane_blocks;
2cd601c6
CK		 3491
3492 /*
3493 * allocation for y_plane part of planar format:
3494 */
1e6ee542 3495 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3496
3497 y_plane_blocks = y_minimum[id];
3498 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3499 total_data_rate);
2cd601c6 3500
c107acfe
MR		 3501 if (y_data_rate) {
3502 ddb->y_plane[pipe][id].start = start;
3503 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3504 }
a1de91e5
MR		 3505
3506 start += y_plane_blocks;
b9cec075
DL		 3507 }
3508
c107acfe 3509 return 0;
b9cec075
DL		 3510}
3511
2d41c0b5
PB		 3512/*
3513 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3514 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3515 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3516 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3517*/
ac484963 3518static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3519{
3520 uint32_t wm_intermediate_val, ret;
3521
3522 if (latency == 0)
3523 return UINT_MAX;
3524
ac484963 3525 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3526 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3527
3528 return ret;
3529}
3530
3531static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3532 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3533{
d4c2aa60 3534 uint32_t ret;
d4c2aa60 3535 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3536
3537 if (latency == 0)
3538 return UINT_MAX;
3539
2d41c0b5
PB		 3540 wm_intermediate_val = latency * pixel_rate;
3541 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3542 plane_blocks_per_line;
2d41c0b5
PB		 3543
3544 return ret;
3545}
3546
9c2f7a9d
KM		 3547static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3548 struct intel_plane_state *pstate)
3549{
3550 uint64_t adjusted_pixel_rate;
3551 uint64_t downscale_amount;
3552 uint64_t pixel_rate;
3553
3554 /* Shouldn't reach here on disabled planes... */
936e71e3 3555 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3556 return 0;
3557
3558 /*
3559 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3560 * with additional adjustments for plane-specific scaling.
3561 */
cfd7e3a2 3562 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3563 downscale_amount = skl_plane_downscale_amount(pstate);
3564
3565 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3566 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3567
3568 return pixel_rate;
3569}
3570
55994c2c
MR		 3571static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3572 struct intel_crtc_state *cstate,
3573 struct intel_plane_state *intel_pstate,
3574 uint16_t ddb_allocation,
3575 int level,
3576 uint16_t *out_blocks, /* out */
3577 uint8_t *out_lines, /* out */
3578 bool *enabled /* out */)
2d41c0b5 3579{
33815fa5
MR		 3580 struct drm_plane_state *pstate = &intel_pstate->base;
3581 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3582 uint32_t latency = dev_priv->wm.skl_latency[level];
3583 uint32_t method1, method2;
3584 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3585 uint32_t res_blocks, res_lines;
3586 uint32_t selected_result;
ac484963 3587 uint8_t cpp;
a280f7dd 3588 uint32_t width = 0, height = 0;
9c2f7a9d 3589 uint32_t plane_pixel_rate;
75676ed4 3590 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3591 struct intel_atomic_state *state =
3592 to_intel_atomic_state(cstate->base.state);
3593 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3594
936e71e3 3595 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3596 *enabled = false;
3597 return 0;
3598 }
2d41c0b5 3599
ee3d532f
PZ		 3600 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3601 latency += 15;
3602
936e71e3
VS		 3603 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3604 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3605
bd2ef25d 3606 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3607 swap(width, height);
3608
ac484963 3609 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3610 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3611
61d0a04d 3612 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3613 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3614 drm_format_plane_cpp(fb->pixel_format, 1) :
3615 drm_format_plane_cpp(fb->pixel_format, 0);
3616
3617 switch (cpp) {
3618 case 1:
3619 y_min_scanlines = 16;
3620 break;
3621 case 2:
3622 y_min_scanlines = 8;
3623 break;
1186fa85
PZ		 3624 case 4:
3625 y_min_scanlines = 4;
3626 break;
86a462bc
PZ		 3627 default:
3628 MISSING_CASE(cpp);
3629 return -EINVAL;
1186fa85
PZ		 3630 }
3631 } else {
3632 y_min_scanlines = 4;
3633 }
3634
2ef32dee
PZ		 3635 if (apply_memory_bw_wa)
3636 y_min_scanlines *= 2;
3637
7a1a8aed
PZ		 3638 plane_bytes_per_line = width * cpp;
3639 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3640 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3641 plane_blocks_per_line =
3642 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3643 plane_blocks_per_line /= y_min_scanlines;
3644 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3645 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3646 + 1;
3647 } else {
3648 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3649 }
3650
9c2f7a9d
KM		 3651 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3652 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3653 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3654 latency,
7a1a8aed 3655 plane_blocks_per_line);
2d41c0b5 3656
75676ed4
PZ		 3657 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3658
024c9045
MR		 3659 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3660 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3661 selected_result = max(method2, y_tile_minimum);
3662 } else {
f1db3eaf
PZ		 3663 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3664 (plane_bytes_per_line / 512 < 1))
3665 selected_result = method2;
3666 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3667 selected_result = min(method1, method2);
3668 else
3669 selected_result = method1;
3670 }
2d41c0b5 3671
d4c2aa60
TU		 3672 res_blocks = selected_result + 1;
3673 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3674
0fda6568 3675 if (level >= 1 && level <= 7) {
024c9045 3676 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3677 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3678 res_blocks += y_tile_minimum;
1186fa85 3679 res_lines += y_min_scanlines;
75676ed4 3680 } else {
0fda6568 3681 res_blocks++;
75676ed4 3682 }
0fda6568 3683 }
e6d66171 3684
55994c2c
MR		 3685 if (res_blocks >= ddb_allocation || res_lines > 31) {
3686 *enabled = false;
6b6bada7
MR		 3687
3688 /*
3689 * If there are no valid level 0 watermarks, then we can't
3690 * support this display configuration.
3691 */
3692 if (level) {
3693 return 0;
3694 } else {
3695 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3696 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3697 to_intel_crtc(cstate->base.crtc)->pipe,
3698 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3699 res_blocks, ddb_allocation, res_lines);
3700
3701 return -EINVAL;
3702 }
55994c2c 3703 }
e6d66171
DL		 3704
3705 *out_blocks = res_blocks;
3706 *out_lines = res_lines;
55994c2c 3707 *enabled = true;
2d41c0b5 3708
55994c2c 3709 return 0;
2d41c0b5
PB		 3710}
3711
f4a96752
MR		 3712static int
3713skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3714 struct skl_ddb_allocation *ddb,
3715 struct intel_crtc_state *cstate,
a62163e9 3716 struct intel_plane *intel_plane,
f4a96752
MR		 3717 int level,
3718 struct skl_wm_level *result)
2d41c0b5 3719{
f4a96752 3720 struct drm_atomic_state *state = cstate->base.state;
024c9045 3721 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3722 struct drm_plane *plane = &intel_plane->base;
3723 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3724 uint16_t ddb_blocks;
024c9045 3725 enum pipe pipe = intel_crtc->pipe;
55994c2c 3726 int ret;
a62163e9
L		 3727 int i = skl_wm_plane_id(intel_plane);
3728
3729 if (state)
3730 intel_pstate =
3731 intel_atomic_get_existing_plane_state(state,
3732 intel_plane);
024c9045 3733
f4a96752 3734 /*
a62163e9
L		 3735 * Note: If we start supporting multiple pending atomic commits against
3736 * the same planes/CRTC's in the future, plane->state will no longer be
3737 * the correct pre-state to use for the calculations here and we'll
3738 * need to change where we get the 'unchanged' plane data from.
3739 *
3740 * For now this is fine because we only allow one queued commit against
3741 * a CRTC. Even if the plane isn't modified by this transaction and we
3742 * don't have a plane lock, we still have the CRTC's lock, so we know
3743 * that no other transactions are racing with us to update it.
f4a96752 3744 */
a62163e9
L		 3745 if (!intel_pstate)
3746 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3747
a62163e9 3748 WARN_ON(!intel_pstate->base.fb);
f4a96752 3749
a62163e9 3750 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3751
a62163e9
L		 3752 ret = skl_compute_plane_wm(dev_priv,
3753 cstate,
3754 intel_pstate,
3755 ddb_blocks,
3756 level,
3757 &result->plane_res_b,
3758 &result->plane_res_l,
3759 &result->plane_en);
3760 if (ret)
3761 return ret;
f4a96752
MR		 3762
3763 return 0;
2d41c0b5
PB		 3764}
3765
407b50f3 3766static uint32_t
024c9045 3767skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3768{
30d1b5fe
PZ		 3769 uint32_t pixel_rate;
3770
024c9045 3771 if (!cstate->base.active)
407b50f3
DL		 3772 return 0;
3773
30d1b5fe
PZ		 3774 pixel_rate = ilk_pipe_pixel_rate(cstate);
3775
3776 if (WARN_ON(pixel_rate == 0))
661abfc0 3777 return 0;
407b50f3 3778
024c9045 3779 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3780 pixel_rate);
407b50f3
DL		 3781}
3782
024c9045 3783static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3784 struct skl_wm_level *trans_wm /* out */)
407b50f3 3785{
024c9045 3786 if (!cstate->base.active)
407b50f3 3787 return;
9414f563
DL		 3788
3789 /* Until we know more, just disable transition WMs */
a62163e9 3790 trans_wm->plane_en = false;
407b50f3
DL		 3791}
3792
55994c2c
MR		 3793static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3794 struct skl_ddb_allocation *ddb,
3795 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3796{
024c9045 3797 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3798 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3799 struct intel_plane *intel_plane;
3800 struct skl_plane_wm *wm;
5db94019 3801 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3802 int ret;
2d41c0b5 3803
a62163e9
L		 3804 /*
3805 * We'll only calculate watermarks for planes that are actually
3806 * enabled, so make sure all other planes are set as disabled.
3807 */
3808 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3809
3810 for_each_intel_plane_mask(&dev_priv->drm,
3811 intel_plane,
3812 cstate->base.plane_mask) {
3813 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3814
3815 for (level = 0; level <= max_level; level++) {
3816 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3817 intel_plane, level,
3818 &wm->wm[level]);
3819 if (ret)
3820 return ret;
3821 }
3822 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3823 }
024c9045 3824 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3825
55994c2c 3826 return 0;
2d41c0b5
PB		 3827}
3828
f0f59a00
VS		 3829static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3830 i915_reg_t reg,
16160e3d
DL		 3831 const struct skl_ddb_entry *entry)
3832{
3833 if (entry->end)
3834 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3835 else
3836 I915_WRITE(reg, 0);
3837}
3838
d8c0fafc 3839static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3840 i915_reg_t reg,
3841 const struct skl_wm_level *level)
3842{
3843 uint32_t val = 0;
3844
3845 if (level->plane_en) {
3846 val |= PLANE_WM_EN;
3847 val |= level->plane_res_b;
3848 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3849 }
3850
3851 I915_WRITE(reg, val);
3852}
3853
d9348dec
VS		 3854static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3855 const struct skl_plane_wm *wm,
3856 const struct skl_ddb_allocation *ddb,
3857 int plane)
62e0fb88
L		 3858{
3859 struct drm_crtc *crtc = &intel_crtc->base;
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3862 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3863 enum pipe pipe = intel_crtc->pipe;
3864
3865 for (level = 0; level <= max_level; level++) {
d8c0fafc 3866 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3867 &wm->wm[level]);
62e0fb88 3868 }
d8c0fafc 3869 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3870 &wm->trans_wm);
27082493
L		 3871
3872 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3873 &ddb->plane[pipe][plane]);
27082493 3874 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3875 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3876}
3877
d9348dec
VS		 3878static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3879 const struct skl_plane_wm *wm,
3880 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3881{
3882 struct drm_crtc *crtc = &intel_crtc->base;
3883 struct drm_device *dev = crtc->dev;
3884 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3885 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3886 enum pipe pipe = intel_crtc->pipe;
3887
3888 for (level = 0; level <= max_level; level++) {
d8c0fafc 3889 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3890 &wm->wm[level]);
62e0fb88 3891 }
d8c0fafc 3892 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3893
27082493 3894 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3895 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3896}
3897
45ece230 3898bool skl_wm_level_equals(const struct skl_wm_level *l1,
3899 const struct skl_wm_level *l2)
3900{
3901 if (l1->plane_en != l2->plane_en)
3902 return false;
3903
3904 /* If both planes aren't enabled, the rest shouldn't matter */
3905 if (!l1->plane_en)
3906 return true;
3907
3908 return (l1->plane_res_l == l2->plane_res_l &&
3909 l1->plane_res_b == l2->plane_res_b);
3910}
3911
27082493
L		 3912static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3913 const struct skl_ddb_entry *b)
0e8fb7ba 3914{
27082493 3915 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3916}
3917
5eff503b
ML		 3918bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3919 const struct skl_ddb_entry *ddb,
3920 int ignore)
0e8fb7ba 3921{
ce0ba283 3922 int i;
0e8fb7ba 3923
5eff503b
ML		 3924 for (i = 0; i < I915_MAX_PIPES; i++)
3925 if (i != ignore && entries[i] &&
3926 skl_ddb_entries_overlap(ddb, entries[i]))
27082493 3927 return true;
0e8fb7ba 3928
27082493 3929 return false;
0e8fb7ba
DL		 3930}
3931
55994c2c 3932static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3933 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3934 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3935 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3936 bool *changed /* out */)
2d41c0b5 3937{
f4a96752 3938 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3939 int ret;
2d41c0b5 3940
55994c2c
MR		 3941 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3942 if (ret)
3943 return ret;
2d41c0b5 3944
03af79e0 3945 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3946 *changed = false;
3947 else
3948 *changed = true;
2d41c0b5 3949
55994c2c 3950 return 0;
2d41c0b5
PB		 3951}
3952
9b613022
MR		 3953static uint32_t
3954pipes_modified(struct drm_atomic_state *state)
3955{
3956 struct drm_crtc *crtc;
3957 struct drm_crtc_state *cstate;
3958 uint32_t i, ret = 0;
3959
3960 for_each_crtc_in_state(state, crtc, cstate, i)
3961 ret |= drm_crtc_mask(crtc);
3962
3963 return ret;
3964}
3965
bb7791bd 3966static int
7f60e200
PZ		 3967skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3968{
3969 struct drm_atomic_state *state = cstate->base.state;
3970 struct drm_device *dev = state->dev;
3971 struct drm_crtc *crtc = cstate->base.crtc;
3972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3973 struct drm_i915_private *dev_priv = to_i915(dev);
3974 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3975 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3976 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3977 struct drm_plane_state *plane_state;
3978 struct drm_plane *plane;
3979 enum pipe pipe = intel_crtc->pipe;
3980 int id;
3981
3982 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3983
220b0965 3984 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 3985 id = skl_wm_plane_id(to_intel_plane(plane));
3986
3987 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3988 &new_ddb->plane[pipe][id]) &&
3989 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3990 &new_ddb->y_plane[pipe][id]))
3991 continue;
3992
3993 plane_state = drm_atomic_get_plane_state(state, plane);
3994 if (IS_ERR(plane_state))
3995 return PTR_ERR(plane_state);
3996 }
3997
3998 return 0;
3999}
4000
98d39494
MR		 4001static int
4002skl_compute_ddb(struct drm_atomic_state *state)
4003{
4004 struct drm_device *dev = state->dev;
4005 struct drm_i915_private *dev_priv = to_i915(dev);
4006 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4007 struct intel_crtc *intel_crtc;
734fa01f 4008 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4009 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4010 int ret;
4011
4012 /*
4013 * If this is our first atomic update following hardware readout,
4014 * we can't trust the DDB that the BIOS programmed for us. Let's
4015 * pretend that all pipes switched active status so that we'll
4016 * ensure a full DDB recompute.
4017 */
1b54a880
MR		 4018 if (dev_priv->wm.distrust_bios_wm) {
4019 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4020 state->acquire_ctx);
4021 if (ret)
4022 return ret;
4023
98d39494
MR		 4024 intel_state->active_pipe_changes = ~0;
4025
1b54a880
MR		 4026 /*
4027 * We usually only initialize intel_state->active_crtcs if we
4028 * we're doing a modeset; make sure this field is always
4029 * initialized during the sanitization process that happens
4030 * on the first commit too.
4031 */
4032 if (!intel_state->modeset)
4033 intel_state->active_crtcs = dev_priv->active_crtcs;
4034 }
4035
98d39494
MR		 4036 /*
4037 * If the modeset changes which CRTC's are active, we need to
4038 * recompute the DDB allocation for *all* active pipes, even
4039 * those that weren't otherwise being modified in any way by this
4040 * atomic commit. Due to the shrinking of the per-pipe allocations
4041 * when new active CRTC's are added, it's possible for a pipe that
4042 * we were already using and aren't changing at all here to suddenly
4043 * become invalid if its DDB needs exceeds its new allocation.
4044 *
4045 * Note that if we wind up doing a full DDB recompute, we can't let
4046 * any other display updates race with this transaction, so we need
4047 * to grab the lock on *all* CRTC's.
4048 */
734fa01f 4049 if (intel_state->active_pipe_changes) {
98d39494 4050 realloc_pipes = ~0;
734fa01f
MR		 4051 intel_state->wm_results.dirty_pipes = ~0;
4052 }
98d39494 4053
5a920b85
PZ		 4054 /*
4055 * We're not recomputing for the pipes not included in the commit, so
4056 * make sure we start with the current state.
4057 */
4058 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4059
98d39494
MR		 4060 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4061 struct intel_crtc_state *cstate;
4062
4063 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4064 if (IS_ERR(cstate))
4065 return PTR_ERR(cstate);
4066
734fa01f 4067 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4068 if (ret)
4069 return ret;
05a76d3d 4070
7f60e200 4071 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4072 if (ret)
4073 return ret;
98d39494
MR		 4074 }
4075
4076 return 0;
4077}
4078
2722efb9
MR		 4079static void
4080skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4081 struct skl_wm_values *src,
4082 enum pipe pipe)
4083{
2722efb9
MR		 4084 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4085 sizeof(dst->ddb.y_plane[pipe]));
4086 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4087 sizeof(dst->ddb.plane[pipe]));
4088}
4089
413fc530 4090static void
4091skl_print_wm_changes(const struct drm_atomic_state *state)
4092{
4093 const struct drm_device *dev = state->dev;
4094 const struct drm_i915_private *dev_priv = to_i915(dev);
4095 const struct intel_atomic_state *intel_state =
4096 to_intel_atomic_state(state);
4097 const struct drm_crtc *crtc;
4098 const struct drm_crtc_state *cstate;
413fc530 4099 const struct intel_plane *intel_plane;
413fc530 4100 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4101 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4102 int id;
7570498e 4103 int i;
413fc530 4104
4105 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4106 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107 enum pipe pipe = intel_crtc->pipe;
413fc530 4108
7570498e 4109 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4110 const struct skl_ddb_entry *old, *new;
4111
413fc530 4112 id = skl_wm_plane_id(intel_plane);
4113 old = &old_ddb->plane[pipe][id];
4114 new = &new_ddb->plane[pipe][id];
4115
413fc530 4116 if (skl_ddb_entry_equal(old, new))
4117 continue;
4118
7570498e
ML		 4119 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4120 intel_plane->base.base.id,
4121 intel_plane->base.name,
4122 old->start, old->end,
4123 new->start, new->end);
413fc530 4124 }
4125 }
4126}
4127
98d39494
MR		 4128static int
4129skl_compute_wm(struct drm_atomic_state *state)
4130{
4131 struct drm_crtc *crtc;
4132 struct drm_crtc_state *cstate;
734fa01f
MR		 4133 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4134 struct skl_wm_values *results = &intel_state->wm_results;
4135 struct skl_pipe_wm *pipe_wm;
98d39494 4136 bool changed = false;
734fa01f 4137 int ret, i;
98d39494
MR		 4138
4139 /*
4140 * If this transaction isn't actually touching any CRTC's, don't
4141 * bother with watermark calculation. Note that if we pass this
4142 * test, we're guaranteed to hold at least one CRTC state mutex,
4143 * which means we can safely use values like dev_priv->active_crtcs
4144 * since any racing commits that want to update them would need to
4145 * hold _all_ CRTC state mutexes.
4146 */
4147 for_each_crtc_in_state(state, crtc, cstate, i)
4148 changed = true;
4149 if (!changed)
4150 return 0;
4151
734fa01f
MR		 4152 /* Clear all dirty flags */
4153 results->dirty_pipes = 0;
4154
98d39494
MR		 4155 ret = skl_compute_ddb(state);
4156 if (ret)
4157 return ret;
4158
734fa01f
MR		 4159 /*
4160 * Calculate WM's for all pipes that are part of this transaction.
4161 * Note that the DDB allocation above may have added more CRTC's that
4162 * weren't otherwise being modified (and set bits in dirty_pipes) if
4163 * pipe allocations had to change.
4164 *
4165 * FIXME: Now that we're doing this in the atomic check phase, we
4166 * should allow skl_update_pipe_wm() to return failure in cases where
4167 * no suitable watermark values can be found.
4168 */
4169 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4170 struct intel_crtc_state *intel_cstate =
4171 to_intel_crtc_state(cstate);
03af79e0
ML		 4172 const struct skl_pipe_wm *old_pipe_wm =
4173 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4174
4175 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4176 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4177 &results->ddb, &changed);
734fa01f
MR		 4178 if (ret)
4179 return ret;
4180
4181 if (changed)
4182 results->dirty_pipes |= drm_crtc_mask(crtc);
4183
4184 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4185 /* This pipe's WM's did not change */
4186 continue;
4187
4188 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4189 }
4190
413fc530 4191 skl_print_wm_changes(state);
4192
98d39494
MR		 4193 return 0;
4194}
4195
ccf010fb
ML		 4196static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4197 struct intel_crtc_state *cstate)
4198{
4199 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4200 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4201 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
e62929b3 4202 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
ccf010fb 4203 enum pipe pipe = crtc->pipe;
e62929b3
ML		 4204 int plane;
4205
4206 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4207 return;
ccf010fb
ML		 4208
4209 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
e62929b3
ML		 4210
4211 for_each_universal_plane(dev_priv, pipe, plane)
4212 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4213
4214 skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
ccf010fb
ML		 4215}
4216
e62929b3
ML		 4217static void skl_initial_wm(struct intel_atomic_state *state,
4218 struct intel_crtc_state *cstate)
2d41c0b5 4219{
e62929b3 4220 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
432081bc 4221 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4222 struct drm_i915_private *dev_priv = to_i915(dev);
e62929b3 4223 struct skl_wm_values *results = &state->wm_results;
2722efb9 4224 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
27082493 4225 enum pipe pipe = intel_crtc->pipe;
adda50b8 4226
432081bc 4227 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4228 return;
4229
734fa01f 4230 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4231
e62929b3
ML		 4232 if (cstate->base.active_changed)
4233 skl_atomic_update_crtc_wm(state, cstate);
27082493
L		 4234
4235 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4236
4237 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4238}
4239
d890565c
VS		 4240static void ilk_compute_wm_config(struct drm_device *dev,
4241 struct intel_wm_config *config)
4242{
4243 struct intel_crtc *crtc;
4244
4245 /* Compute the currently _active_ config */
4246 for_each_intel_crtc(dev, crtc) {
4247 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4248
4249 if (!wm->pipe_enabled)
4250 continue;
4251
4252 config->sprites_enabled |= wm->sprites_enabled;
4253 config->sprites_scaled |= wm->sprites_scaled;
4254 config->num_pipes_active++;
4255 }
4256}
4257
ed4a6a7c 4258static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4259{
91c8a326 4260 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4261 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4262 struct ilk_wm_maximums max;
d890565c 4263 struct intel_wm_config config = {};
820c1980 4264 struct ilk_wm_values results = {};
77c122bc 4265 enum intel_ddb_partitioning partitioning;
261a27d1 4266
d890565c
VS		 4267 ilk_compute_wm_config(dev, &config);
4268
4269 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4270 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4271
4272 /* 5/6 split only in single pipe config on IVB+ */
175fded1 4273 if (INTEL_GEN(dev_priv) >= 7 &&
d890565c
VS		 4274 config.num_pipes_active == 1 && config.sprites_enabled) {
4275 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4276 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4277
820c1980 4278 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4279 } else {
198a1e9b 4280 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4281 }
4282
198a1e9b 4283 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4284 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4285
820c1980 4286 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4287
820c1980 4288 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4289}
4290
ccf010fb
ML		 4291static void ilk_initial_watermarks(struct intel_atomic_state *state,
4292 struct intel_crtc_state *cstate)
b9d5c839 4293{
ed4a6a7c
MR		 4294 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4295 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4296
ed4a6a7c 4297 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4298 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4299 ilk_program_watermarks(dev_priv);
4300 mutex_unlock(&dev_priv->wm.wm_mutex);
4301}
bf220452 4302
ccf010fb
ML		 4303static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4304 struct intel_crtc_state *cstate)
ed4a6a7c
MR		 4305{
4306 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4307 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4308
ed4a6a7c
MR		 4309 mutex_lock(&dev_priv->wm.wm_mutex);
4310 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4311 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4312 ilk_program_watermarks(dev_priv);
4313 }
4314 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4315}
4316
d8c0fafc 4317static inline void skl_wm_level_from_reg_val(uint32_t val,
4318 struct skl_wm_level *level)
3078999f 4319{
d8c0fafc 4320 level->plane_en = val & PLANE_WM_EN;
4321 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4322 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4323 PLANE_WM_LINES_MASK;
3078999f
PB		 4324}
4325
bf9d99ad 4326void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4327 struct skl_pipe_wm *out)
3078999f
PB		 4328{
4329 struct drm_device *dev = crtc->dev;
fac5e23e 4330 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4332 struct intel_plane *intel_plane;
d8c0fafc 4333 struct skl_plane_wm *wm;
3078999f 4334 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4335 int level, id, max_level;
4336 uint32_t val;
3078999f 4337
5db94019 4338 max_level = ilk_wm_max_level(dev_priv);
3078999f 4339
d8c0fafc 4340 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4341 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4342 wm = &out->planes[id];
3078999f 4343
d8c0fafc 4344 for (level = 0; level <= max_level; level++) {
4345 if (id != PLANE_CURSOR)
4346 val = I915_READ(PLANE_WM(pipe, id, level));
4347 else
4348 val = I915_READ(CUR_WM(pipe, level));
3078999f 4349
d8c0fafc 4350 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4351 }
3078999f 4352
d8c0fafc 4353 if (id != PLANE_CURSOR)
4354 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4355 else
4356 val = I915_READ(CUR_WM_TRANS(pipe));
4357
4358 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4359 }
4360
d8c0fafc 4361 if (!intel_crtc->active)
4362 return;
4e0963c7 4363
bf9d99ad 4364 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4365}
4366
4367void skl_wm_get_hw_state(struct drm_device *dev)
4368{
fac5e23e 4369 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4370 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4371 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4372 struct drm_crtc *crtc;
bf9d99ad 4373 struct intel_crtc *intel_crtc;
4374 struct intel_crtc_state *cstate;
3078999f 4375
a269c583 4376 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4377 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4378 intel_crtc = to_intel_crtc(crtc);
4379 cstate = to_intel_crtc_state(crtc->state);
4380
4381 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4382
03af79e0 4383 if (intel_crtc->active)
bf9d99ad 4384 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4385 }
a1de91e5 4386
279e99d7
MR		 4387 if (dev_priv->active_crtcs) {
4388 /* Fully recompute DDB on first atomic commit */
4389 dev_priv->wm.distrust_bios_wm = true;
4390 } else {
4391 /* Easy/common case; just sanitize DDB now if everything off */
4392 memset(ddb, 0, sizeof(*ddb));
4393 }
3078999f
PB		 4394}
4395
243e6a44
VS		 4396static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4397{
4398 struct drm_device *dev = crtc->dev;
fac5e23e 4399 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4400 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4402 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4403 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4404 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4405 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4406 [PIPE_A] = WM0_PIPEA_ILK,
4407 [PIPE_B] = WM0_PIPEB_ILK,
4408 [PIPE_C] = WM0_PIPEC_IVB,
4409 };
4410
4411 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4412 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4413 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4414
15606534
VS		 4415 memset(active, 0, sizeof(*active));
4416
3ef00284 4417 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4418
4419 if (active->pipe_enabled) {
243e6a44
VS		 4420 u32 tmp = hw->wm_pipe[pipe];
4421
4422 /*
4423 * For active pipes LP0 watermark is marked as
4424 * enabled, and LP1+ watermaks as disabled since
4425 * we can't really reverse compute them in case
4426 * multiple pipes are active.
4427 */
4428 active->wm[0].enable = true;
4429 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4430 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4431 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4432 active->linetime = hw->wm_linetime[pipe];
4433 } else {
5db94019 4434 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4435
4436 /*
4437 * For inactive pipes, all watermark levels
4438 * should be marked as enabled but zeroed,
4439 * which is what we'd compute them to.
4440 */
4441 for (level = 0; level <= max_level; level++)
4442 active->wm[level].enable = true;
4443 }
4e0963c7
MR		 4444
4445 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4446}
4447
6eb1a681
VS		 4448#define _FW_WM(value, plane) \
4449 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4450#define _FW_WM_VLV(value, plane) \
4451 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4452
4453static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4454 struct vlv_wm_values *wm)
4455{
4456 enum pipe pipe;
4457 uint32_t tmp;
4458
4459 for_each_pipe(dev_priv, pipe) {
4460 tmp = I915_READ(VLV_DDL(pipe));
4461
4462 wm->ddl[pipe].primary =
4463 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4464 wm->ddl[pipe].cursor =
4465 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4466 wm->ddl[pipe].sprite[0] =
4467 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4468 wm->ddl[pipe].sprite[1] =
4469 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4470 }
4471
4472 tmp = I915_READ(DSPFW1);
4473 wm->sr.plane = _FW_WM(tmp, SR);
4474 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4475 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4476 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4477
4478 tmp = I915_READ(DSPFW2);
4479 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4480 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4481 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4482
4483 tmp = I915_READ(DSPFW3);
4484 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4485
4486 if (IS_CHERRYVIEW(dev_priv)) {
4487 tmp = I915_READ(DSPFW7_CHV);
4488 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4489 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4490
4491 tmp = I915_READ(DSPFW8_CHV);
4492 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4493 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4494
4495 tmp = I915_READ(DSPFW9_CHV);
4496 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4497 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4498
4499 tmp = I915_READ(DSPHOWM);
4500 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4501 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4502 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4503 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4504 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4505 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4506 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4507 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4508 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4509 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4510 } else {
4511 tmp = I915_READ(DSPFW7);
4512 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4513 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4514
4515 tmp = I915_READ(DSPHOWM);
4516 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4517 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4518 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4519 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4520 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4521 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4522 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4523 }
4524}
4525
4526#undef _FW_WM
4527#undef _FW_WM_VLV
4528
4529void vlv_wm_get_hw_state(struct drm_device *dev)
4530{
4531 struct drm_i915_private *dev_priv = to_i915(dev);
4532 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4533 struct intel_plane *plane;
4534 enum pipe pipe;
4535 u32 val;
4536
4537 vlv_read_wm_values(dev_priv, wm);
4538
4539 for_each_intel_plane(dev, plane) {
4540 switch (plane->base.type) {
4541 int sprite;
4542 case DRM_PLANE_TYPE_CURSOR:
4543 plane->wm.fifo_size = 63;
4544 break;
4545 case DRM_PLANE_TYPE_PRIMARY:
ef0f5e93 4546 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
6eb1a681
VS		 4547 break;
4548 case DRM_PLANE_TYPE_OVERLAY:
4549 sprite = plane->plane;
ef0f5e93 4550 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
6eb1a681
VS		 4551 break;
4552 }
4553 }
4554
4555 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4556 wm->level = VLV_WM_LEVEL_PM2;
4557
4558 if (IS_CHERRYVIEW(dev_priv)) {
4559 mutex_lock(&dev_priv->rps.hw_lock);
4560
4561 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4562 if (val & DSP_MAXFIFO_PM5_ENABLE)
4563 wm->level = VLV_WM_LEVEL_PM5;
4564
58590c14
VS		 4565 /*
4566 * If DDR DVFS is disabled in the BIOS, Punit
4567 * will never ack the request. So if that happens
4568 * assume we don't have to enable/disable DDR DVFS
4569 * dynamically. To test that just set the REQ_ACK
4570 * bit to poke the Punit, but don't change the
4571 * HIGH/LOW bits so that we don't actually change
4572 * the current state.
4573 */
6eb1a681 4574 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4575 val |= FORCE_DDR_FREQ_REQ_ACK;
4576 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4577
4578 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4579 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4580 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4581 "assuming DDR DVFS is disabled\n");
4582 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4583 } else {
4584 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4585 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4586 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4587 }
6eb1a681
VS		 4588
4589 mutex_unlock(&dev_priv->rps.hw_lock);
4590 }
4591
4592 for_each_pipe(dev_priv, pipe)
4593 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4594 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4595 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4596
4597 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4598 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4599}
4600
243e6a44
VS		 4601void ilk_wm_get_hw_state(struct drm_device *dev)
4602{
fac5e23e 4603 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4604 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4605 struct drm_crtc *crtc;
4606
70e1e0ec 4607 for_each_crtc(dev, crtc)
243e6a44
VS		 4608 ilk_pipe_wm_get_hw_state(crtc);
4609
4610 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4611 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4612 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4613
4614 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
175fded1 4615 if (INTEL_GEN(dev_priv) >= 7) {
cfa7698b
VS		 4616 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4617 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4618 }
243e6a44 4619
8652744b 4620 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4621 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4622 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4623 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4624 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4625 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4626
4627 hw->enable_fbc_wm =
4628 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4629}
4630
b445e3b0
ED		 4631/**
4632 * intel_update_watermarks - update FIFO watermark values based on current modes
4633 *
4634 * Calculate watermark values for the various WM regs based on current mode
4635 * and plane configuration.
4636 *
4637 * There are several cases to deal with here:
4638 * - normal (i.e. non-self-refresh)
4639 * - self-refresh (SR) mode
4640 * - lines are large relative to FIFO size (buffer can hold up to 2)
4641 * - lines are small relative to FIFO size (buffer can hold more than 2
4642 * lines), so need to account for TLB latency
4643 *
4644 * The normal calculation is:
4645 * watermark = dotclock * bytes per pixel * latency
4646 * where latency is platform & configuration dependent (we assume pessimal
4647 * values here).
4648 *
4649 * The SR calculation is:
4650 * watermark = (trunc(latency/line time)+1) * surface width *
4651 * bytes per pixel
4652 * where
4653 * line time = htotal / dotclock
4654 * surface width = hdisplay for normal plane and 64 for cursor
4655 * and latency is assumed to be high, as above.
4656 *
4657 * The final value programmed to the register should always be rounded up,
4658 * and include an extra 2 entries to account for clock crossings.
4659 *
4660 * We don't use the sprite, so we can ignore that. And on Crestline we have
4661 * to set the non-SR watermarks to 8.
4662 */
432081bc 4663void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4664{
432081bc 4665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4666
4667 if (dev_priv->display.update_wm)
46ba614c 4668 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4669}
4670
e2828914 4671/*
9270388e 4672 * Lock protecting IPS related data structures
9270388e
DV		 4673 */
4674DEFINE_SPINLOCK(mchdev_lock);
4675
4676/* Global for IPS driver to get at the current i915 device. Protected by
4677 * mchdev_lock. */
4678static struct drm_i915_private *i915_mch_dev;
4679
91d14251 4680bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4681{
2b4e57bd
ED		 4682 u16 rgvswctl;
4683
9270388e
DV		 4684 assert_spin_locked(&mchdev_lock);
4685
2b4e57bd
ED		 4686 rgvswctl = I915_READ16(MEMSWCTL);
4687 if (rgvswctl & MEMCTL_CMD_STS) {
4688 DRM_DEBUG("gpu busy, RCS change rejected\n");
4689 return false; /* still busy with another command */
4690 }
4691
4692 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4693 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4694 I915_WRITE16(MEMSWCTL, rgvswctl);
4695 POSTING_READ16(MEMSWCTL);
4696
4697 rgvswctl |= MEMCTL_CMD_STS;
4698 I915_WRITE16(MEMSWCTL, rgvswctl);
4699
4700 return true;
4701}
4702
91d14251 4703static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4704{
84f1b20f 4705 u32 rgvmodectl;
2b4e57bd
ED		 4706 u8 fmax, fmin, fstart, vstart;
4707
9270388e
DV		 4708 spin_lock_irq(&mchdev_lock);
4709
84f1b20f
TU		 4710 rgvmodectl = I915_READ(MEMMODECTL);
4711
2b4e57bd
ED		 4712 /* Enable temp reporting */
4713 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4714 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4715
4716 /* 100ms RC evaluation intervals */
4717 I915_WRITE(RCUPEI, 100000);
4718 I915_WRITE(RCDNEI, 100000);
4719
4720 /* Set max/min thresholds to 90ms and 80ms respectively */
4721 I915_WRITE(RCBMAXAVG, 90000);
4722 I915_WRITE(RCBMINAVG, 80000);
4723
4724 I915_WRITE(MEMIHYST, 1);
4725
4726 /* Set up min, max, and cur for interrupt handling */
4727 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4728 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4729 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4730 MEMMODE_FSTART_SHIFT;
4731
616847e7 4732 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4733 PXVFREQ_PX_SHIFT;
4734
20e4d407
DV		 4735 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4736 dev_priv->ips.fstart = fstart;
2b4e57bd 4737
20e4d407
DV		 4738 dev_priv->ips.max_delay = fstart;
4739 dev_priv->ips.min_delay = fmin;
4740 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4741
4742 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4743 fmax, fmin, fstart);
4744
4745 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4746
4747 /*
4748 * Interrupts will be enabled in ironlake_irq_postinstall
4749 */
4750
4751 I915_WRITE(VIDSTART, vstart);
4752 POSTING_READ(VIDSTART);
4753
4754 rgvmodectl |= MEMMODE_SWMODE_EN;
4755 I915_WRITE(MEMMODECTL, rgvmodectl);
4756
9270388e 4757 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4758 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4759 mdelay(1);
2b4e57bd 4760
91d14251 4761 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4762
7d81c3e0
VS		 4763 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4764 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4765 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4766 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4767 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4768
4769 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4770}
4771
91d14251 4772static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4773{
9270388e
DV		 4774 u16 rgvswctl;
4775
4776 spin_lock_irq(&mchdev_lock);
4777
4778 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4779
4780 /* Ack interrupts, disable EFC interrupt */
4781 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4782 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4783 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4784 I915_WRITE(DEIIR, DE_PCU_EVENT);
4785 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4786
4787 /* Go back to the starting frequency */
91d14251 4788 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4789 mdelay(1);
2b4e57bd
ED		 4790 rgvswctl |= MEMCTL_CMD_STS;
4791 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4792 mdelay(1);
2b4e57bd 4793
9270388e 4794 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4795}
4796
acbe9475
DV		 4797/* There's a funny hw issue where the hw returns all 0 when reading from
4798 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4799 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4800 * all limits and the gpu stuck at whatever frequency it is at atm).
4801 */
74ef1173 4802static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4803{
7b9e0ae6 4804 u32 limits;
2b4e57bd 4805
20b46e59
DV		 4806 /* Only set the down limit when we've reached the lowest level to avoid
4807 * getting more interrupts, otherwise leave this clear. This prevents a
4808 * race in the hw when coming out of rc6: There's a tiny window where
4809 * the hw runs at the minimal clock before selecting the desired
4810 * frequency, if the down threshold expires in that window we will not
4811 * receive a down interrupt. */
2d1fe073 4812 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4813 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4814 if (val <= dev_priv->rps.min_freq_softlimit)
4815 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4816 } else {
4817 limits = dev_priv->rps.max_freq_softlimit << 24;
4818 if (val <= dev_priv->rps.min_freq_softlimit)
4819 limits |= dev_priv->rps.min_freq_softlimit << 16;
4820 }
20b46e59
DV		 4821
4822 return limits;
4823}
4824
dd75fdc8
CW		 4825static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4826{
4827 int new_power;
8a586437
AG		 4828 u32 threshold_up = 0, threshold_down = 0; /* in % */
4829 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4830
4831 new_power = dev_priv->rps.power;
4832 switch (dev_priv->rps.power) {
4833 case LOW_POWER:
a72b5623
CW		 4834 if (val > dev_priv->rps.efficient_freq + 1 &&
4835 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4836 new_power = BETWEEN;
4837 break;
4838
4839 case BETWEEN:
a72b5623
CW		 4840 if (val <= dev_priv->rps.efficient_freq &&
4841 val < dev_priv->rps.cur_freq)
dd75fdc8 4842 new_power = LOW_POWER;
a72b5623
CW		 4843 else if (val >= dev_priv->rps.rp0_freq &&
4844 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4845 new_power = HIGH_POWER;
4846 break;
4847
4848 case HIGH_POWER:
a72b5623
CW		 4849 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4850 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4851 new_power = BETWEEN;
4852 break;
4853 }
4854 /* Max/min bins are special */
aed242ff 4855 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4856 new_power = LOW_POWER;
aed242ff 4857 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4858 new_power = HIGH_POWER;
4859 if (new_power == dev_priv->rps.power)
4860 return;
4861
4862 /* Note the units here are not exactly 1us, but 1280ns. */
4863 switch (new_power) {
4864 case LOW_POWER:
4865 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4866 ei_up = 16000;
4867 threshold_up = 95;
dd75fdc8
CW		 4868
4869 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4870 ei_down = 32000;
4871 threshold_down = 85;
dd75fdc8
CW		 4872 break;
4873
4874 case BETWEEN:
4875 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4876 ei_up = 13000;
4877 threshold_up = 90;
dd75fdc8
CW		 4878
4879 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4880 ei_down = 32000;
4881 threshold_down = 75;
dd75fdc8
CW		 4882 break;
4883
4884 case HIGH_POWER:
4885 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4886 ei_up = 10000;
4887 threshold_up = 85;
dd75fdc8
CW		 4888
4889 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4890 ei_down = 32000;
4891 threshold_down = 60;
dd75fdc8
CW		 4892 break;
4893 }
4894
8a586437 4895 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4896 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4897 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4898 GT_INTERVAL_FROM_US(dev_priv,
4899 ei_up * threshold_up / 100));
8a586437
AG		 4900
4901 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4902 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4903 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4904 GT_INTERVAL_FROM_US(dev_priv,
4905 ei_down * threshold_down / 100));
4906
4907 I915_WRITE(GEN6_RP_CONTROL,
4908 GEN6_RP_MEDIA_TURBO |
4909 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4910 GEN6_RP_MEDIA_IS_GFX |
4911 GEN6_RP_ENABLE |
4912 GEN6_RP_UP_BUSY_AVG |
4913 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4914
dd75fdc8 4915 dev_priv->rps.power = new_power;
8fb55197
CW		 4916 dev_priv->rps.up_threshold = threshold_up;
4917 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4918 dev_priv->rps.last_adj = 0;
4919}
4920
2876ce73
CW		 4921static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4922{
4923 u32 mask = 0;
4924
4925 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4926 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4927 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4928 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4929
7b3c29f6
CW		 4930 mask &= dev_priv->pm_rps_events;
4931
59d02a1f 4932 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4933}
4934
b8a5ff8d
JM		 4935/* gen6_set_rps is called to update the frequency request, but should also be
4936 * called when the range (min_delay and max_delay) is modified so that we can
4937 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4938static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4939{
23eafea6 4940 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4941 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4942 return;
4943
4fc688ce 4944 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4945 WARN_ON(val > dev_priv->rps.max_freq);
4946 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4947
eb64cad1
CW		 4948 /* min/max delay may still have been modified so be sure to
4949 * write the limits value.
4950 */
4951 if (val != dev_priv->rps.cur_freq) {
4952 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4953
dc97997a 4954 if (IS_GEN9(dev_priv))
5704195c
AG		 4955 I915_WRITE(GEN6_RPNSWREQ,
4956 GEN9_FREQUENCY(val));
dc97997a 4957 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4958 I915_WRITE(GEN6_RPNSWREQ,
4959 HSW_FREQUENCY(val));
4960 else
4961 I915_WRITE(GEN6_RPNSWREQ,
4962 GEN6_FREQUENCY(val) |
4963 GEN6_OFFSET(0) |
4964 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4965 }
7b9e0ae6 4966
7b9e0ae6
CW		 4967 /* Make sure we continue to get interrupts
4968 * until we hit the minimum or maximum frequencies.
4969 */
74ef1173 4970 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4971 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4972
d5570a72
BW		 4973 POSTING_READ(GEN6_RPNSWREQ);
4974
b39fb297 4975 dev_priv->rps.cur_freq = val;
0f94592e 4976 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4977}
4978
dc97997a 4979static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4980{
ffe02b40 4981 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4982 WARN_ON(val > dev_priv->rps.max_freq);
4983 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4984
dc97997a 4985 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4986 "Odd GPU freq value\n"))
4987 val &= ~1;
4988
cd25dd5b
D		 4989 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4990
8fb55197 4991 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4992 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4993 if (!IS_CHERRYVIEW(dev_priv))
4994 gen6_set_rps_thresholds(dev_priv, val);
4995 }
ffe02b40 4996
ffe02b40
VS		 4997 dev_priv->rps.cur_freq = val;
4998 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4999}
5000
a7f6e231 5001/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5002 *
5003 * * If Gfx is Idle, then
a7f6e231
D		 5004 * 1. Forcewake Media well.
5005 * 2. Request idle freq.
5006 * 3. Release Forcewake of Media well.
76c3552f
D		 5007*/
5008static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5009{
aed242ff 5010 u32 val = dev_priv->rps.idle_freq;
5549d25f 5011
aed242ff 5012 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5013 return;
5014
a7f6e231
D		 5015 /* Wake up the media well, as that takes a lot less
5016 * power than the Render well. */
5017 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5018 valleyview_set_rps(dev_priv, val);
a7f6e231 5019 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5020}
5021
43cf3bf0
CW		 5022void gen6_rps_busy(struct drm_i915_private *dev_priv)
5023{
5024 mutex_lock(&dev_priv->rps.hw_lock);
5025 if (dev_priv->rps.enabled) {
5026 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5027 gen6_rps_reset_ei(dev_priv);
5028 I915_WRITE(GEN6_PMINTRMSK,
5029 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5030
c33d247d
CW		 5031 gen6_enable_rps_interrupts(dev_priv);
5032
2b83c4c4
MW		 5033 /* Ensure we start at the user's desired frequency */
5034 intel_set_rps(dev_priv,
5035 clamp(dev_priv->rps.cur_freq,
5036 dev_priv->rps.min_freq_softlimit,
5037 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5038 }
5039 mutex_unlock(&dev_priv->rps.hw_lock);
5040}
5041
b29c19b6
CW		 5042void gen6_rps_idle(struct drm_i915_private *dev_priv)
5043{
c33d247d
CW		 5044 /* Flush our bottom-half so that it does not race with us
5045 * setting the idle frequency and so that it is bounded by
5046 * our rpm wakeref. And then disable the interrupts to stop any
5047 * futher RPS reclocking whilst we are asleep.
5048 */
5049 gen6_disable_rps_interrupts(dev_priv);
5050
b29c19b6 5051 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5052 if (dev_priv->rps.enabled) {
dc97997a 5053 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5054 vlv_set_rps_idle(dev_priv);
7526ed79 5055 else
dc97997a 5056 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5057 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5058 I915_WRITE(GEN6_PMINTRMSK,
5059 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5060 }
8d3afd7d 5061 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5062
8d3afd7d 5063 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5064 while (!list_empty(&dev_priv->rps.clients))
5065 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5066 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5067}
5068
1854d5ca 5069void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5070 struct intel_rps_client *rps,
5071 unsigned long submitted)
b29c19b6 5072{
8d3afd7d
CW		 5073 /* This is intentionally racy! We peek at the state here, then
5074 * validate inside the RPS worker.
5075 */
67d97da3 5076 if (!(dev_priv->gt.awake &&
8d3afd7d 5077 dev_priv->rps.enabled &&
29ecd78d 5078 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5079 return;
43cf3bf0 5080
e61b9958
CW		 5081 /* Force a RPS boost (and don't count it against the client) if
5082 * the GPU is severely congested.
5083 */
d0bc54f2 5084 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5085 rps = NULL;
5086
8d3afd7d
CW		 5087 spin_lock(&dev_priv->rps.client_lock);
5088 if (rps == NULL || list_empty(&rps->link)) {
5089 spin_lock_irq(&dev_priv->irq_lock);
5090 if (dev_priv->rps.interrupts_enabled) {
5091 dev_priv->rps.client_boost = true;
c33d247d 5092 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5093 }
5094 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5095
2e1b8730
CW		 5096 if (rps != NULL) {
5097 list_add(&rps->link, &dev_priv->rps.clients);
5098 rps->boosts++;
1854d5ca
CW		 5099 } else
5100 dev_priv->rps.boosts++;
c0951f0c 5101 }
8d3afd7d 5102 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5103}
5104
dc97997a 5105void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5106{
dc97997a
CW		 5107 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5108 valleyview_set_rps(dev_priv, val);
ffe02b40 5109 else
dc97997a 5110 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5111}
5112
dc97997a 5113static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5114{
20e49366 5115 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5116 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5117}
5118
dc97997a 5119static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5120{
2030d684
AG		 5121 I915_WRITE(GEN6_RP_CONTROL, 0);
5122}
5123
dc97997a 5124static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5125{
d20d4f0c 5126 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5127 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5128 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5129}
5130
dc97997a 5131static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5132{
38807746
D		 5133 I915_WRITE(GEN6_RC_CONTROL, 0);
5134}
5135
dc97997a 5136static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5137{
98a2e5f9
D		 5138 /* we're doing forcewake before Disabling RC6,
5139 * This what the BIOS expects when going into suspend */
59bad947 5140 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5141
44fc7d5c 5142 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5143
59bad947 5144 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5145}
5146
dc97997a 5147static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5148{
dc97997a 5149 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5150 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5151 mode = GEN6_RC_CTL_RC6_ENABLE;
5152 else
5153 mode = 0;
5154 }
dc97997a 5155 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5156 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5157 "RC6 %s RC6p %s RC6pp %s\n",
5158 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5159 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5160 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5161
5162 else
b99d49cc
ID		 5163 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5164 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5165}
5166
dc97997a 5167static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5168{
72e96d64 5169 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5170 bool enable_rc6 = true;
5171 unsigned long rc6_ctx_base;
fc619841
ID		 5172 u32 rc_ctl;
5173 int rc_sw_target;
5174
5175 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5176 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5177 RC_SW_TARGET_STATE_SHIFT;
5178 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5179 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5180 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5181 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5182 rc_sw_target);
274008e8
SAK		 5183
5184 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5185 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5186 enable_rc6 = false;
5187 }
5188
5189 /*
5190 * The exact context size is not known for BXT, so assume a page size
5191 * for this check.
5192 */
5193 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5194 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5195 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5196 ggtt->stolen_reserved_size))) {
b99d49cc 5197 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5198 enable_rc6 = false;
5199 }
5200
5201 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5202 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5203 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5204 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5205 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5206 enable_rc6 = false;
5207 }
5208
fc619841
ID		 5209 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5210 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5211 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5212 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5213 enable_rc6 = false;
5214 }
5215
5216 if (!I915_READ(GEN6_GFXPAUSE)) {
5217 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5218 enable_rc6 = false;
5219 }
5220
5221 if (!I915_READ(GEN8_MISC_CTRL0)) {
5222 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5223 enable_rc6 = false;
5224 }
5225
5226 return enable_rc6;
5227}
5228
dc97997a 5229int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5230{
e7d66d89 5231 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5232 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5233 return 0;
5234
274008e8
SAK		 5235 if (!enable_rc6)
5236 return 0;
5237
dc97997a 5238 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5239 DRM_INFO("RC6 disabled by BIOS\n");
5240 return 0;
5241 }
5242
456470eb 5243 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5244 if (enable_rc6 >= 0) {
5245 int mask;
5246
dc97997a 5247 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5248 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5249 INTEL_RC6pp_ENABLE;
5250 else
5251 mask = INTEL_RC6_ENABLE;
5252
5253 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5254 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5255 "(requested %d, valid %d)\n",
5256 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5257
5258 return enable_rc6 & mask;
5259 }
2b4e57bd 5260
dc97997a 5261 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5262 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5263
5264 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5265}
5266
dc97997a 5267static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5268{
5269 /* All of these values are in units of 50MHz */
773ea9a8 5270
93ee2920 5271 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5272 if (IS_BROXTON(dev_priv)) {
773ea9a8 5273 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5274 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5275 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5276 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5277 } else {
773ea9a8 5278 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5279 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5280 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5281 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5282 }
3280e8b0 5283 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5284 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5285
93ee2920 5286 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5287 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5288 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5289 u32 ddcc_status = 0;
5290
5291 if (sandybridge_pcode_read(dev_priv,
5292 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5293 &ddcc_status) == 0)
93ee2920 5294 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5295 clamp_t(u8,
5296 ((ddcc_status >> 8) & 0xff),
5297 dev_priv->rps.min_freq,
5298 dev_priv->rps.max_freq);
93ee2920
TR		 5299 }
5300
dc97997a 5301 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5302 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5303 * the natural hardware unit for SKL
5304 */
c5e0688c
AG		 5305 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5306 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5307 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5308 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5309 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5310 }
3280e8b0
BW		 5311}
5312
3a45b05c
CW		 5313static void reset_rps(struct drm_i915_private *dev_priv,
5314 void (*set)(struct drm_i915_private *, u8))
5315{
5316 u8 freq = dev_priv->rps.cur_freq;
5317
5318 /* force a reset */
5319 dev_priv->rps.power = -1;
5320 dev_priv->rps.cur_freq = -1;
5321
5322 set(dev_priv, freq);
5323}
5324
b6fef0ef 5325/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5326static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5327{
b6fef0ef
JB		 5328 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5329
23eafea6 5330 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5331 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5332 /*
5333 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5334 * clear out the Control register just to avoid inconsitency
5335 * with debugfs interface, which will show Turbo as enabled
5336 * only and that is not expected by the User after adding the
5337 * WaGsvDisableTurbo. Apart from this there is no problem even
5338 * if the Turbo is left enabled in the Control register, as the
5339 * Up/Down interrupts would remain masked.
5340 */
dc97997a 5341 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5342 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5343 return;
5344 }
5345
0beb059a
AG		 5346 /* Program defaults and thresholds for RPS*/
5347 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5348 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5349
5350 /* 1 second timeout*/
5351 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5352 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5353
b6fef0ef 5354 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5355
0beb059a
AG		 5356 /* Leaning on the below call to gen6_set_rps to program/setup the
5357 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5358 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5359 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5360
5361 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5362}
5363
dc97997a 5364static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5365{
e2f80391 5366 struct intel_engine_cs *engine;
3b3f1650 5367 enum intel_engine_id id;
20e49366 5368 uint32_t rc6_mask = 0;
20e49366
ZW		 5369
5370 /* 1a: Software RC state - RC0 */
5371 I915_WRITE(GEN6_RC_STATE, 0);
5372
5373 /* 1b: Get forcewake during program sequence. Although the driver
5374 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5375 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5376
5377 /* 2a: Disable RC states. */
5378 I915_WRITE(GEN6_RC_CONTROL, 0);
5379
5380 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5381
5382 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5383 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5384 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5385 else
5386 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5387 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5388 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5389 for_each_engine(engine, dev_priv, id)
e2f80391 5390 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5391
1a3d1898 5392 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5393 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5394
20e49366 5395 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5396
38c23527
ZW		 5397 /* 2c: Program Coarse Power Gating Policies. */
5398 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5399 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5400
20e49366 5401 /* 3a: Enable RC6 */
dc97997a 5402 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5403 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5404 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5405 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5406 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5407 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5408 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5409 GEN7_RC_CTL_TO_MODE |
5410 rc6_mask);
3e7732a0
SAK		 5411 } else {
5412 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5413 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5414 GEN6_RC_CTL_EI_MODE(1) |
5415 rc6_mask);
3e7732a0 5416 }
20e49366 5417
cb07bae0
SK		 5418 /*
5419 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5420 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5421 */
dc97997a 5422 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5423 I915_WRITE(GEN9_PG_ENABLE, 0);
5424 else
5425 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5426 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5427
59bad947 5428 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5429}
5430
dc97997a 5431static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5432{
e2f80391 5433 struct intel_engine_cs *engine;
3b3f1650 5434 enum intel_engine_id id;
93ee2920 5435 uint32_t rc6_mask = 0;
6edee7f3
BW		 5436
5437 /* 1a: Software RC state - RC0 */
5438 I915_WRITE(GEN6_RC_STATE, 0);
5439
5440 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5441 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5442 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5443
5444 /* 2a: Disable RC states. */
5445 I915_WRITE(GEN6_RC_CONTROL, 0);
5446
6edee7f3
BW		 5447 /* 2b: Program RC6 thresholds.*/
5448 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5449 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5450 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5451 for_each_engine(engine, dev_priv, id)
e2f80391 5452 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5453 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5454 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5455 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5456 else
5457 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5458
5459 /* 3: Enable RC6 */
dc97997a 5460 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5461 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5462 intel_print_rc6_info(dev_priv, rc6_mask);
5463 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5464 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5465 GEN7_RC_CTL_TO_MODE |
5466 rc6_mask);
5467 else
5468 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5469 GEN6_RC_CTL_EI_MODE(1) |
5470 rc6_mask);
6edee7f3
BW		 5471
5472 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5473 I915_WRITE(GEN6_RPNSWREQ,
5474 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5475 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5476 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5477 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5478 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5479
5480 /* Docs recommend 900MHz, and 300 MHz respectively */
5481 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5482 dev_priv->rps.max_freq_softlimit << 24 |
5483 dev_priv->rps.min_freq_softlimit << 16);
5484
5485 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5486 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5487 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5488 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5489
5490 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5491
5492 /* 5: Enable RPS */
7526ed79
DV		 5493 I915_WRITE(GEN6_RP_CONTROL,
5494 GEN6_RP_MEDIA_TURBO |
5495 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5496 GEN6_RP_MEDIA_IS_GFX |
5497 GEN6_RP_ENABLE |
5498 GEN6_RP_UP_BUSY_AVG |
5499 GEN6_RP_DOWN_IDLE_AVG);
5500
5501 /* 6: Ring frequency + overclocking (our driver does this later */
5502
3a45b05c 5503 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5504
59bad947 5505 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5506}
5507
dc97997a 5508static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5509{
e2f80391 5510 struct intel_engine_cs *engine;
3b3f1650 5511 enum intel_engine_id id;
99ac9612 5512 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5513 u32 gtfifodbg;
2b4e57bd 5514 int rc6_mode;
b4ac5afc 5515 int ret;
2b4e57bd 5516
4fc688ce 5517 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5518
2b4e57bd
ED		 5519 /* Here begins a magic sequence of register writes to enable
5520 * auto-downclocking.
5521 *
5522 * Perhaps there might be some value in exposing these to
5523 * userspace...
5524 */
5525 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5526
5527 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5528 gtfifodbg = I915_READ(GTFIFODBG);
5529 if (gtfifodbg) {
2b4e57bd
ED		 5530 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5531 I915_WRITE(GTFIFODBG, gtfifodbg);
5532 }
5533
59bad947 5534 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5535
5536 /* disable the counters and set deterministic thresholds */
5537 I915_WRITE(GEN6_RC_CONTROL, 0);
5538
5539 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5540 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5541 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5542 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5543 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5544
3b3f1650 5545 for_each_engine(engine, dev_priv, id)
e2f80391 5546 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5547
5548 I915_WRITE(GEN6_RC_SLEEP, 0);
5549 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5550 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5551 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5552 else
5553 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5554 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5555 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5556
5a7dc92a 5557 /* Check if we are enabling RC6 */
dc97997a 5558 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5559 if (rc6_mode & INTEL_RC6_ENABLE)
5560 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5561
5a7dc92a 5562 /* We don't use those on Haswell */
dc97997a 5563 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5564 if (rc6_mode & INTEL_RC6p_ENABLE)
5565 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5566
5a7dc92a
ED		 5567 if (rc6_mode & INTEL_RC6pp_ENABLE)
5568 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5569 }
2b4e57bd 5570
dc97997a 5571 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5572
5573 I915_WRITE(GEN6_RC_CONTROL,
5574 rc6_mask |
5575 GEN6_RC_CTL_EI_MODE(1) |
5576 GEN6_RC_CTL_HW_ENABLE);
5577
dd75fdc8
CW		 5578 /* Power down if completely idle for over 50ms */
5579 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5580 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5581
3a45b05c 5582 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5583
31643d54
BW		 5584 rc6vids = 0;
5585 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5586 if (IS_GEN6(dev_priv) && ret) {
31643d54 5587 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5588 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5589 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5590 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5591 rc6vids &= 0xffff00;
5592 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5593 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5594 if (ret)
5595 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5596 }
5597
59bad947 5598 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5599}
5600
fb7404e8 5601static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5602{
5603 int min_freq = 15;
3ebecd07
CW		 5604 unsigned int gpu_freq;
5605 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5606 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5607 int scaling_factor = 180;
eda79642 5608 struct cpufreq_policy *policy;
2b4e57bd 5609
4fc688ce 5610 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5611
eda79642
BW		 5612 policy = cpufreq_cpu_get(0);
5613 if (policy) {
5614 max_ia_freq = policy->cpuinfo.max_freq;
5615 cpufreq_cpu_put(policy);
5616 } else {
5617 /*
5618 * Default to measured freq if none found, PCU will ensure we
5619 * don't go over
5620 */
2b4e57bd 5621 max_ia_freq = tsc_khz;
eda79642 5622 }
2b4e57bd
ED		 5623
5624 /* Convert from kHz to MHz */
5625 max_ia_freq /= 1000;
5626
153b4b95 5627 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5628 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5629 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5630
dc97997a 5631 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5632 /* Convert GT frequency to 50 HZ units */
5633 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5634 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5635 } else {
5636 min_gpu_freq = dev_priv->rps.min_freq;
5637 max_gpu_freq = dev_priv->rps.max_freq;
5638 }
5639
2b4e57bd
ED		 5640 /*
5641 * For each potential GPU frequency, load a ring frequency we'd like
5642 * to use for memory access. We do this by specifying the IA frequency
5643 * the PCU should use as a reference to determine the ring frequency.
5644 */
4c8c7743
AG		 5645 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5646 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5647 unsigned int ia_freq = 0, ring_freq = 0;
5648
dc97997a 5649 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5650 /*
5651 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5652 * No floor required for ring frequency on SKL.
5653 */
5654 ring_freq = gpu_freq;
dc97997a 5655 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5656 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5657 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5658 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5659 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5660 ring_freq = max(min_ring_freq, ring_freq);
5661 /* leave ia_freq as the default, chosen by cpufreq */
5662 } else {
5663 /* On older processors, there is no separate ring
5664 * clock domain, so in order to boost the bandwidth
5665 * of the ring, we need to upclock the CPU (ia_freq).
5666 *
5667 * For GPU frequencies less than 750MHz,
5668 * just use the lowest ring freq.
5669 */
5670 if (gpu_freq < min_freq)
5671 ia_freq = 800;
5672 else
5673 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5674 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5675 }
2b4e57bd 5676
42c0526c
BW		 5677 sandybridge_pcode_write(dev_priv,
5678 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5679 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5680 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5681 gpu_freq);
2b4e57bd 5682 }
2b4e57bd
ED		 5683}
5684
03af2045 5685static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5686{
5687 u32 val, rp0;
5688
5b5929cb 5689 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5690
43b67998 5691 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5692 case 8:
5693 /* (2 * 4) config */
5694 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5695 break;
5696 case 12:
5697 /* (2 * 6) config */
5698 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5699 break;
5700 case 16:
5701 /* (2 * 8) config */
5702 default:
5703 /* Setting (2 * 8) Min RP0 for any other combination */
5704 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5705 break;
095acd5f 5706 }
5b5929cb
JN		 5707
5708 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5709
2b6b3a09
D		 5710 return rp0;
5711}
5712
5713static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5714{
5715 u32 val, rpe;
5716
5717 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5718 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5719
5720 return rpe;
5721}
5722
7707df4a
D		 5723static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5724{
5725 u32 val, rp1;
5726
5b5929cb
JN		 5727 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5728 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5729
7707df4a
D		 5730 return rp1;
5731}
5732
f8f2b001
D		 5733static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5734{
5735 u32 val, rp1;
5736
5737 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5738
5739 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5740
5741 return rp1;
5742}
5743
03af2045 5744static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5745{
5746 u32 val, rp0;
5747
64936258 5748 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5749
5750 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5751 /* Clamp to max */
5752 rp0 = min_t(u32, rp0, 0xea);
5753
5754 return rp0;
5755}
5756
5757static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5758{
5759 u32 val, rpe;
5760
64936258 5761 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5762 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5763 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5764 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5765
5766 return rpe;
5767}
5768
03af2045 5769static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5770{
36146035
ID		 5771 u32 val;
5772
5773 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5774 /*
5775 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5776 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5777 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5778 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5779 * to make sure it matches what Punit accepts.
5780 */
5781 return max_t(u32, val, 0xc0);
0a073b84
JB		 5782}
5783
ae48434c
ID		 5784/* Check that the pctx buffer wasn't move under us. */
5785static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5786{
5787 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5788
5789 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5790 dev_priv->vlv_pctx->stolen->start);
5791}
5792
38807746
D		 5793
5794/* Check that the pcbr address is not empty. */
5795static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5796{
5797 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5798
5799 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5800}
5801
dc97997a 5802static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5803{
62106b4f 5804 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5805 unsigned long pctx_paddr, paddr;
38807746
D		 5806 u32 pcbr;
5807 int pctx_size = 32*1024;
5808
38807746
D		 5809 pcbr = I915_READ(VLV_PCBR);
5810 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5811 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5812 paddr = (dev_priv->mm.stolen_base +
62106b4f 5813 (ggtt->stolen_size - pctx_size));
38807746
D		 5814
5815 pctx_paddr = (paddr & (~4095));
5816 I915_WRITE(VLV_PCBR, pctx_paddr);
5817 }
ce611ef8
VS		 5818
5819 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5820}
5821
dc97997a 5822static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5823{
c9cddffc
JB		 5824 struct drm_i915_gem_object *pctx;
5825 unsigned long pctx_paddr;
5826 u32 pcbr;
5827 int pctx_size = 24*1024;
5828
5829 pcbr = I915_READ(VLV_PCBR);
5830 if (pcbr) {
5831 /* BIOS set it up already, grab the pre-alloc'd space */
5832 int pcbr_offset;
5833
5834 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5835 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5836 pcbr_offset,
190d6cd5 5837 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5838 pctx_size);
5839 goto out;
5840 }
5841
ce611ef8
VS		 5842 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5843
c9cddffc
JB		 5844 /*
5845 * From the Gunit register HAS:
5846 * The Gfx driver is expected to program this register and ensure
5847 * proper allocation within Gfx stolen memory. For example, this
5848 * register should be programmed such than the PCBR range does not
5849 * overlap with other ranges, such as the frame buffer, protected
5850 * memory, or any other relevant ranges.
5851 */
91c8a326 5852 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5853 if (!pctx) {
5854 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5855 goto out;
c9cddffc
JB		 5856 }
5857
5858 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5859 I915_WRITE(VLV_PCBR, pctx_paddr);
5860
5861out:
ce611ef8 5862 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5863 dev_priv->vlv_pctx = pctx;
5864}
5865
dc97997a 5866static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5867{
ae48434c
ID		 5868 if (WARN_ON(!dev_priv->vlv_pctx))
5869 return;
5870
f0cd5182 5871 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5872 dev_priv->vlv_pctx = NULL;
5873}
5874
c30fec65
VS		 5875static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5876{
5877 dev_priv->rps.gpll_ref_freq =
5878 vlv_get_cck_clock(dev_priv, "GPLL ref",
5879 CCK_GPLL_CLOCK_CONTROL,
5880 dev_priv->czclk_freq);
5881
5882 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5883 dev_priv->rps.gpll_ref_freq);
5884}
5885
dc97997a 5886static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5887{
2bb25c17 5888 u32 val;
4e80519e 5889
dc97997a 5890 valleyview_setup_pctx(dev_priv);
4e80519e 5891
c30fec65
VS		 5892 vlv_init_gpll_ref_freq(dev_priv);
5893
2bb25c17
VS		 5894 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5895 switch ((val >> 6) & 3) {
5896 case 0:
5897 case 1:
5898 dev_priv->mem_freq = 800;
5899 break;
5900 case 2:
5901 dev_priv->mem_freq = 1066;
5902 break;
5903 case 3:
5904 dev_priv->mem_freq = 1333;
5905 break;
5906 }
80b83b62 5907 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5908
4e80519e
ID		 5909 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5910 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5911 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5912 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5913 dev_priv->rps.max_freq);
5914
5915 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5916 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5917 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5918 dev_priv->rps.efficient_freq);
5919
f8f2b001
D		 5920 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5921 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5922 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5923 dev_priv->rps.rp1_freq);
5924
4e80519e
ID		 5925 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5926 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5927 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5928 dev_priv->rps.min_freq);
4e80519e
ID		 5929}
5930
dc97997a 5931static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5932{
2bb25c17 5933 u32 val;
2b6b3a09 5934
dc97997a 5935 cherryview_setup_pctx(dev_priv);
2b6b3a09 5936
c30fec65
VS		 5937 vlv_init_gpll_ref_freq(dev_priv);
5938
a580516d 5939 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5940 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5941 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5942
2bb25c17 5943 switch ((val >> 2) & 0x7) {
2bb25c17 5944 case 3:
2bb25c17
VS		 5945 dev_priv->mem_freq = 2000;
5946 break;
bfa7df01 5947 default:
2bb25c17
VS		 5948 dev_priv->mem_freq = 1600;
5949 break;
5950 }
80b83b62 5951 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5952
2b6b3a09
D		 5953 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5954 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5955 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5956 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5957 dev_priv->rps.max_freq);
5958
5959 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5960 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5961 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5962 dev_priv->rps.efficient_freq);
5963
7707df4a
D		 5964 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5965 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5966 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5967 dev_priv->rps.rp1_freq);
5968
5b7c91b7
D		 5969 /* PUnit validated range is only [RPe, RP0] */
5970 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5971 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5972 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5973 dev_priv->rps.min_freq);
5974
1c14762d
VS		 5975 WARN_ONCE((dev_priv->rps.max_freq |
5976 dev_priv->rps.efficient_freq |
5977 dev_priv->rps.rp1_freq |
5978 dev_priv->rps.min_freq) & 1,
5979 "Odd GPU freq values\n");
38807746
D		 5980}
5981
dc97997a 5982static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5983{
dc97997a 5984 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5985}
5986
dc97997a 5987static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5988{
e2f80391 5989 struct intel_engine_cs *engine;
3b3f1650 5990 enum intel_engine_id id;
2b6b3a09 5991 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5992
5993 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5994
297b32ec
VS		 5995 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5996 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5997 if (gtfifodbg) {
5998 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5999 gtfifodbg);
6000 I915_WRITE(GTFIFODBG, gtfifodbg);
6001 }
6002
6003 cherryview_check_pctx(dev_priv);
6004
6005 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6006 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6007 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6008
160614a2
VS		 6009 /* Disable RC states. */
6010 I915_WRITE(GEN6_RC_CONTROL, 0);
6011
38807746
D		 6012 /* 2a: Program RC6 thresholds.*/
6013 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6014 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6015 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6016
3b3f1650 6017 for_each_engine(engine, dev_priv, id)
e2f80391 6018 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6019 I915_WRITE(GEN6_RC_SLEEP, 0);
6020
f4f71c7d
D		 6021 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6022 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6023
6024 /* allows RC6 residency counter to work */
6025 I915_WRITE(VLV_COUNTER_CONTROL,
6026 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6027 VLV_MEDIA_RC6_COUNT_EN |
6028 VLV_RENDER_RC6_COUNT_EN));
6029
6030 /* For now we assume BIOS is allocating and populating the PCBR */
6031 pcbr = I915_READ(VLV_PCBR);
6032
38807746 6033 /* 3: Enable RC6 */
dc97997a
CW		 6034 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6035 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6036 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6037
6038 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6039
2b6b3a09 6040 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6041 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6042 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6043 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6044 I915_WRITE(GEN6_RP_UP_EI, 66000);
6045 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6046
6047 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6048
6049 /* 5: Enable RPS */
6050 I915_WRITE(GEN6_RP_CONTROL,
6051 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6052 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6053 GEN6_RP_ENABLE |
6054 GEN6_RP_UP_BUSY_AVG |
6055 GEN6_RP_DOWN_IDLE_AVG);
6056
3ef62342
D		 6057 /* Setting Fixed Bias */
6058 val = VLV_OVERRIDE_EN |
6059 VLV_SOC_TDP_EN |
6060 CHV_BIAS_CPU_50_SOC_50;
6061 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6062
2b6b3a09
D		 6063 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6064
8d40c3ae
VS		 6065 /* RPS code assumes GPLL is used */
6066 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6067
742f491d 6068 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6069 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6070
3a45b05c 6071 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6072
59bad947 6073 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6074}
6075
dc97997a 6076static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6077{
e2f80391 6078 struct intel_engine_cs *engine;
3b3f1650 6079 enum intel_engine_id id;
2a5913a8 6080 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6081
6082 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6083
ae48434c
ID		 6084 valleyview_check_pctx(dev_priv);
6085
297b32ec
VS		 6086 gtfifodbg = I915_READ(GTFIFODBG);
6087 if (gtfifodbg) {
f7d85c1e
JB		 6088 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6089 gtfifodbg);
0a073b84
JB		 6090 I915_WRITE(GTFIFODBG, gtfifodbg);
6091 }
6092
c8d9a590 6093 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6094 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6095
160614a2
VS		 6096 /* Disable RC states. */
6097 I915_WRITE(GEN6_RC_CONTROL, 0);
6098
cad725fe 6099 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6100 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6101 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6102 I915_WRITE(GEN6_RP_UP_EI, 66000);
6103 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6104
6105 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6106
6107 I915_WRITE(GEN6_RP_CONTROL,
6108 GEN6_RP_MEDIA_TURBO |
6109 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6110 GEN6_RP_MEDIA_IS_GFX |
6111 GEN6_RP_ENABLE |
6112 GEN6_RP_UP_BUSY_AVG |
6113 GEN6_RP_DOWN_IDLE_CONT);
6114
6115 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6116 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6117 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6118
3b3f1650 6119 for_each_engine(engine, dev_priv, id)
e2f80391 6120 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6121
2f0aa304 6122 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6123
6124 /* allows RC6 residency counter to work */
49798eb2 6125 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6126 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6127 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6128 VLV_MEDIA_RC6_COUNT_EN |
6129 VLV_RENDER_RC6_COUNT_EN));
31685c25 6130
dc97997a 6131 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6132 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6133
dc97997a 6134 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6135
a2b23fe0 6136 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6137
3ef62342
D		 6138 /* Setting Fixed Bias */
6139 val = VLV_OVERRIDE_EN |
6140 VLV_SOC_TDP_EN |
6141 VLV_BIAS_CPU_125_SOC_875;
6142 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6143
64936258 6144 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6145
8d40c3ae
VS		 6146 /* RPS code assumes GPLL is used */
6147 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6148
742f491d 6149 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6150 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6151
3a45b05c 6152 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6153
59bad947 6154 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6155}
6156
dde18883
ED		 6157static unsigned long intel_pxfreq(u32 vidfreq)
6158{
6159 unsigned long freq;
6160 int div = (vidfreq & 0x3f0000) >> 16;
6161 int post = (vidfreq & 0x3000) >> 12;
6162 int pre = (vidfreq & 0x7);
6163
6164 if (!pre)
6165 return 0;
6166
6167 freq = ((div * 133333) / ((1<<post) * pre));
6168
6169 return freq;
6170}
6171
eb48eb00
DV		 6172static const struct cparams {
6173 u16 i;
6174 u16 t;
6175 u16 m;
6176 u16 c;
6177} cparams[] = {
6178 { 1, 1333, 301, 28664 },
6179 { 1, 1066, 294, 24460 },
6180 { 1, 800, 294, 25192 },
6181 { 0, 1333, 276, 27605 },
6182 { 0, 1066, 276, 27605 },
6183 { 0, 800, 231, 23784 },
6184};
6185
f531dcb2 6186static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6187{
6188 u64 total_count, diff, ret;
6189 u32 count1, count2, count3, m = 0, c = 0;
6190 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6191 int i;
6192
02d71956
DV		 6193 assert_spin_locked(&mchdev_lock);
6194
20e4d407 6195 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6196
6197 /* Prevent division-by-zero if we are asking too fast.
6198 * Also, we don't get interesting results if we are polling
6199 * faster than once in 10ms, so just return the saved value
6200 * in such cases.
6201 */
6202 if (diff1 <= 10)
20e4d407 6203 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6204
6205 count1 = I915_READ(DMIEC);
6206 count2 = I915_READ(DDREC);
6207 count3 = I915_READ(CSIEC);
6208
6209 total_count = count1 + count2 + count3;
6210
6211 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6212 if (total_count < dev_priv->ips.last_count1) {
6213 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6214 diff += total_count;
6215 } else {
20e4d407 6216 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6217 }
6218
6219 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6220 if (cparams[i].i == dev_priv->ips.c_m &&
6221 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6222 m = cparams[i].m;
6223 c = cparams[i].c;
6224 break;
6225 }
6226 }
6227
6228 diff = div_u64(diff, diff1);
6229 ret = ((m * diff) + c);
6230 ret = div_u64(ret, 10);
6231
20e4d407
DV		 6232 dev_priv->ips.last_count1 = total_count;
6233 dev_priv->ips.last_time1 = now;
eb48eb00 6234
20e4d407 6235 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6236
6237 return ret;
6238}
6239
f531dcb2
CW		 6240unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6241{
6242 unsigned long val;
6243
dc97997a 6244 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6245 return 0;
6246
6247 spin_lock_irq(&mchdev_lock);
6248
6249 val = __i915_chipset_val(dev_priv);
6250
6251 spin_unlock_irq(&mchdev_lock);
6252
6253 return val;
6254}
6255
eb48eb00
DV		 6256unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6257{
6258 unsigned long m, x, b;
6259 u32 tsfs;
6260
6261 tsfs = I915_READ(TSFS);
6262
6263 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6264 x = I915_READ8(TR1);
6265
6266 b = tsfs & TSFS_INTR_MASK;
6267
6268 return ((m * x) / 127) - b;
6269}
6270
d972d6ee
MK		 6271static int _pxvid_to_vd(u8 pxvid)
6272{
6273 if (pxvid == 0)
6274 return 0;
6275
6276 if (pxvid >= 8 && pxvid < 31)
6277 pxvid = 31;
6278
6279 return (pxvid + 2) * 125;
6280}
6281
6282static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6283{
d972d6ee
MK		 6284 const int vd = _pxvid_to_vd(pxvid);
6285 const int vm = vd - 1125;
6286
dc97997a 6287 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6288 return vm > 0 ? vm : 0;
6289
6290 return vd;
eb48eb00
DV		 6291}
6292
02d71956 6293static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6294{
5ed0bdf2 6295 u64 now, diff, diffms;
eb48eb00
DV		 6296 u32 count;
6297
02d71956 6298 assert_spin_locked(&mchdev_lock);
eb48eb00 6299
5ed0bdf2
TG		 6300 now = ktime_get_raw_ns();
6301 diffms = now - dev_priv->ips.last_time2;
6302 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6303
6304 /* Don't divide by 0 */
eb48eb00
DV		 6305 if (!diffms)
6306 return;
6307
6308 count = I915_READ(GFXEC);
6309
20e4d407
DV		 6310 if (count < dev_priv->ips.last_count2) {
6311 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6312 diff += count;
6313 } else {
20e4d407 6314 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6315 }
6316
20e4d407
DV		 6317 dev_priv->ips.last_count2 = count;
6318 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6319
6320 /* More magic constants... */
6321 diff = diff * 1181;
6322 diff = div_u64(diff, diffms * 10);
20e4d407 6323 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6324}
6325
02d71956
DV		 6326void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6327{
dc97997a 6328 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6329 return;
6330
9270388e 6331 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6332
6333 __i915_update_gfx_val(dev_priv);
6334
9270388e 6335 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6336}
6337
f531dcb2 6338static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6339{
6340 unsigned long t, corr, state1, corr2, state2;
6341 u32 pxvid, ext_v;
6342
02d71956
DV		 6343 assert_spin_locked(&mchdev_lock);
6344
616847e7 6345 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6346 pxvid = (pxvid >> 24) & 0x7f;
6347 ext_v = pvid_to_extvid(dev_priv, pxvid);
6348
6349 state1 = ext_v;
6350
6351 t = i915_mch_val(dev_priv);
6352
6353 /* Revel in the empirically derived constants */
6354
6355 /* Correction factor in 1/100000 units */
6356 if (t > 80)
6357 corr = ((t * 2349) + 135940);
6358 else if (t >= 50)
6359 corr = ((t * 964) + 29317);
6360 else /* < 50 */
6361 corr = ((t * 301) + 1004);
6362
6363 corr = corr * ((150142 * state1) / 10000 - 78642);
6364 corr /= 100000;
20e4d407 6365 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6366
6367 state2 = (corr2 * state1) / 10000;
6368 state2 /= 100; /* convert to mW */
6369
02d71956 6370 __i915_update_gfx_val(dev_priv);
eb48eb00 6371
20e4d407 6372 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6373}
6374
f531dcb2
CW		 6375unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6376{
6377 unsigned long val;
6378
dc97997a 6379 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6380 return 0;
6381
6382 spin_lock_irq(&mchdev_lock);
6383
6384 val = __i915_gfx_val(dev_priv);
6385
6386 spin_unlock_irq(&mchdev_lock);
6387
6388 return val;
6389}
6390
eb48eb00
DV		 6391/**
6392 * i915_read_mch_val - return value for IPS use
6393 *
6394 * Calculate and return a value for the IPS driver to use when deciding whether
6395 * we have thermal and power headroom to increase CPU or GPU power budget.
6396 */
6397unsigned long i915_read_mch_val(void)
6398{
6399 struct drm_i915_private *dev_priv;
6400 unsigned long chipset_val, graphics_val, ret = 0;
6401
9270388e 6402 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6403 if (!i915_mch_dev)
6404 goto out_unlock;
6405 dev_priv = i915_mch_dev;
6406
f531dcb2
CW		 6407 chipset_val = __i915_chipset_val(dev_priv);
6408 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6409
6410 ret = chipset_val + graphics_val;
6411
6412out_unlock:
9270388e 6413 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6414
6415 return ret;
6416}
6417EXPORT_SYMBOL_GPL(i915_read_mch_val);
6418
6419/**
6420 * i915_gpu_raise - raise GPU frequency limit
6421 *
6422 * Raise the limit; IPS indicates we have thermal headroom.
6423 */
6424bool i915_gpu_raise(void)
6425{
6426 struct drm_i915_private *dev_priv;
6427 bool ret = true;
6428
9270388e 6429 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6430 if (!i915_mch_dev) {
6431 ret = false;
6432 goto out_unlock;
6433 }
6434 dev_priv = i915_mch_dev;
6435
20e4d407
DV		 6436 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6437 dev_priv->ips.max_delay--;
eb48eb00
DV		 6438
6439out_unlock:
9270388e 6440 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6441
6442 return ret;
6443}
6444EXPORT_SYMBOL_GPL(i915_gpu_raise);
6445
6446/**
6447 * i915_gpu_lower - lower GPU frequency limit
6448 *
6449 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6450 * frequency maximum.
6451 */
6452bool i915_gpu_lower(void)
6453{
6454 struct drm_i915_private *dev_priv;
6455 bool ret = true;
6456
9270388e 6457 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6458 if (!i915_mch_dev) {
6459 ret = false;
6460 goto out_unlock;
6461 }
6462 dev_priv = i915_mch_dev;
6463
20e4d407
DV		 6464 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6465 dev_priv->ips.max_delay++;
eb48eb00
DV		 6466
6467out_unlock:
9270388e 6468 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6469
6470 return ret;
6471}
6472EXPORT_SYMBOL_GPL(i915_gpu_lower);
6473
6474/**
6475 * i915_gpu_busy - indicate GPU business to IPS
6476 *
6477 * Tell the IPS driver whether or not the GPU is busy.
6478 */
6479bool i915_gpu_busy(void)
6480{
eb48eb00
DV		 6481 bool ret = false;
6482
9270388e 6483 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6484 if (i915_mch_dev)
6485 ret = i915_mch_dev->gt.awake;
9270388e 6486 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6487
6488 return ret;
6489}
6490EXPORT_SYMBOL_GPL(i915_gpu_busy);
6491
6492/**
6493 * i915_gpu_turbo_disable - disable graphics turbo
6494 *
6495 * Disable graphics turbo by resetting the max frequency and setting the
6496 * current frequency to the default.
6497 */
6498bool i915_gpu_turbo_disable(void)
6499{
6500 struct drm_i915_private *dev_priv;
6501 bool ret = true;
6502
9270388e 6503 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6504 if (!i915_mch_dev) {
6505 ret = false;
6506 goto out_unlock;
6507 }
6508 dev_priv = i915_mch_dev;
6509
20e4d407 6510 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6511
91d14251 6512 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6513 ret = false;
6514
6515out_unlock:
9270388e 6516 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6517
6518 return ret;
6519}
6520EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6521
6522/**
6523 * Tells the intel_ips driver that the i915 driver is now loaded, if
6524 * IPS got loaded first.
6525 *
6526 * This awkward dance is so that neither module has to depend on the
6527 * other in order for IPS to do the appropriate communication of
6528 * GPU turbo limits to i915.
6529 */
6530static void
6531ips_ping_for_i915_load(void)
6532{
6533 void (*link)(void);
6534
6535 link = symbol_get(ips_link_to_i915_driver);
6536 if (link) {
6537 link();
6538 symbol_put(ips_link_to_i915_driver);
6539 }
6540}
6541
6542void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6543{
02d71956
DV		 6544 /* We only register the i915 ips part with intel-ips once everything is
6545 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6546 spin_lock_irq(&mchdev_lock);
eb48eb00 6547 i915_mch_dev = dev_priv;
9270388e 6548 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6549
6550 ips_ping_for_i915_load();
6551}
6552
6553void intel_gpu_ips_teardown(void)
6554{
9270388e 6555 spin_lock_irq(&mchdev_lock);
eb48eb00 6556 i915_mch_dev = NULL;
9270388e 6557 spin_unlock_irq(&mchdev_lock);
eb48eb00 6558}
76c3552f 6559
dc97997a 6560static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6561{
dde18883
ED		 6562 u32 lcfuse;
6563 u8 pxw[16];
6564 int i;
6565
6566 /* Disable to program */
6567 I915_WRITE(ECR, 0);
6568 POSTING_READ(ECR);
6569
6570 /* Program energy weights for various events */
6571 I915_WRITE(SDEW, 0x15040d00);
6572 I915_WRITE(CSIEW0, 0x007f0000);
6573 I915_WRITE(CSIEW1, 0x1e220004);
6574 I915_WRITE(CSIEW2, 0x04000004);
6575
6576 for (i = 0; i < 5; i++)
616847e7 6577 I915_WRITE(PEW(i), 0);
dde18883 6578 for (i = 0; i < 3; i++)
616847e7 6579 I915_WRITE(DEW(i), 0);
dde18883
ED		 6580
6581 /* Program P-state weights to account for frequency power adjustment */
6582 for (i = 0; i < 16; i++) {
616847e7 6583 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6584 unsigned long freq = intel_pxfreq(pxvidfreq);
6585 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6586 PXVFREQ_PX_SHIFT;
6587 unsigned long val;
6588
6589 val = vid * vid;
6590 val *= (freq / 1000);
6591 val *= 255;
6592 val /= (127*127*900);
6593 if (val > 0xff)
6594 DRM_ERROR("bad pxval: %ld\n", val);
6595 pxw[i] = val;
6596 }
6597 /* Render standby states get 0 weight */
6598 pxw[14] = 0;
6599 pxw[15] = 0;
6600
6601 for (i = 0; i < 4; i++) {
6602 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6603 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6604 I915_WRITE(PXW(i), val);
dde18883
ED		 6605 }
6606
6607 /* Adjust magic regs to magic values (more experimental results) */
6608 I915_WRITE(OGW0, 0);
6609 I915_WRITE(OGW1, 0);
6610 I915_WRITE(EG0, 0x00007f00);
6611 I915_WRITE(EG1, 0x0000000e);
6612 I915_WRITE(EG2, 0x000e0000);
6613 I915_WRITE(EG3, 0x68000300);
6614 I915_WRITE(EG4, 0x42000000);
6615 I915_WRITE(EG5, 0x00140031);
6616 I915_WRITE(EG6, 0);
6617 I915_WRITE(EG7, 0);
6618
6619 for (i = 0; i < 8; i++)
616847e7 6620 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6621
6622 /* Enable PMON + select events */
6623 I915_WRITE(ECR, 0x80000019);
6624
6625 lcfuse = I915_READ(LCFUSE02);
6626
20e4d407 6627 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6628}
6629
dc97997a 6630void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6631{
b268c699
ID		 6632 /*
6633 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6634 * requirement.
6635 */
6636 if (!i915.enable_rc6) {
6637 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6638 intel_runtime_pm_get(dev_priv);
6639 }
e6069ca8 6640
b5163dbb 6641 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6642 mutex_lock(&dev_priv->rps.hw_lock);
6643
6644 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6645 if (IS_CHERRYVIEW(dev_priv))
6646 cherryview_init_gt_powersave(dev_priv);
6647 else if (IS_VALLEYVIEW(dev_priv))
6648 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6649 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6650 gen6_init_rps_frequencies(dev_priv);
6651
6652 /* Derive initial user preferences/limits from the hardware limits */
6653 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6654 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6655
6656 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6657 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6658
6659 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6660 dev_priv->rps.min_freq_softlimit =
6661 max_t(int,
6662 dev_priv->rps.efficient_freq,
6663 intel_freq_opcode(dev_priv, 450));
6664
99ac9612
CW		 6665 /* After setting max-softlimit, find the overclock max freq */
6666 if (IS_GEN6(dev_priv) ||
6667 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6668 u32 params = 0;
6669
6670 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6671 if (params & BIT(31)) { /* OC supported */
6672 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6673 (dev_priv->rps.max_freq & 0xff) * 50,
6674 (params & 0xff) * 50);
6675 dev_priv->rps.max_freq = params & 0xff;
6676 }
6677 }
6678
29ecd78d
CW		 6679 /* Finally allow us to boost to max by default */
6680 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6681
773ea9a8 6682 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6683 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6684
6685 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6686}
6687
dc97997a 6688void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6689{
8dac1e1f 6690 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6691 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6692
6693 if (!i915.enable_rc6)
6694 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6695}
6696
54b4f68f
CW		 6697/**
6698 * intel_suspend_gt_powersave - suspend PM work and helper threads
6699 * @dev_priv: i915 device
6700 *
6701 * We don't want to disable RC6 or other features here, we just want
6702 * to make sure any work we've queued has finished and won't bother
6703 * us while we're suspended.
6704 */
6705void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6706{
6707 if (INTEL_GEN(dev_priv) < 6)
6708 return;
6709
6710 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6711 intel_runtime_pm_put(dev_priv);
6712
6713 /* gen6_rps_idle() will be called later to disable interrupts */
6714}
6715
b7137e0c
CW		 6716void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6717{
6718 dev_priv->rps.enabled = true; /* force disabling */
6719 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6720
6721 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6722}
6723
dc97997a 6724void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6725{
b7137e0c
CW		 6726 if (!READ_ONCE(dev_priv->rps.enabled))
6727 return;
e494837a 6728
b7137e0c 6729 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6730
b7137e0c
CW		 6731 if (INTEL_GEN(dev_priv) >= 9) {
6732 gen9_disable_rc6(dev_priv);
6733 gen9_disable_rps(dev_priv);
6734 } else if (IS_CHERRYVIEW(dev_priv)) {
6735 cherryview_disable_rps(dev_priv);
6736 } else if (IS_VALLEYVIEW(dev_priv)) {
6737 valleyview_disable_rps(dev_priv);
6738 } else if (INTEL_GEN(dev_priv) >= 6) {
6739 gen6_disable_rps(dev_priv);
6740 } else if (IS_IRONLAKE_M(dev_priv)) {
6741 ironlake_disable_drps(dev_priv);
930ebb46 6742 }
b7137e0c
CW		 6743
6744 dev_priv->rps.enabled = false;
6745 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6746}
6747
b7137e0c 6748void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6749{
54b4f68f
CW		 6750 /* We shouldn't be disabling as we submit, so this should be less
6751 * racy than it appears!
6752 */
b7137e0c
CW		 6753 if (READ_ONCE(dev_priv->rps.enabled))
6754 return;
1a01ab3b 6755
b7137e0c
CW		 6756 /* Powersaving is controlled by the host when inside a VM */
6757 if (intel_vgpu_active(dev_priv))
6758 return;
0a073b84 6759
b7137e0c 6760 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6761
6762 if (IS_CHERRYVIEW(dev_priv)) {
6763 cherryview_enable_rps(dev_priv);
6764 } else if (IS_VALLEYVIEW(dev_priv)) {
6765 valleyview_enable_rps(dev_priv);
b7137e0c 6766 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6767 gen9_enable_rc6(dev_priv);
6768 gen9_enable_rps(dev_priv);
6769 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6770 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6771 } else if (IS_BROADWELL(dev_priv)) {
6772 gen8_enable_rps(dev_priv);
fb7404e8 6773 gen6_update_ring_freq(dev_priv);
b7137e0c 6774 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6775 gen6_enable_rps(dev_priv);
fb7404e8 6776 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6777 } else if (IS_IRONLAKE_M(dev_priv)) {
6778 ironlake_enable_drps(dev_priv);
6779 intel_init_emon(dev_priv);
0a073b84 6780 }
aed242ff
CW		 6781
6782 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6783 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6784
6785 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6786 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6787
54b4f68f 6788 dev_priv->rps.enabled = true;
b7137e0c
CW		 6789 mutex_unlock(&dev_priv->rps.hw_lock);
6790}
3cc134e3 6791
54b4f68f
CW		 6792static void __intel_autoenable_gt_powersave(struct work_struct *work)
6793{
6794 struct drm_i915_private *dev_priv =
6795 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6796 struct intel_engine_cs *rcs;
6797 struct drm_i915_gem_request *req;
6798
6799 if (READ_ONCE(dev_priv->rps.enabled))
6800 goto out;
6801
3b3f1650 6802 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6803 if (rcs->last_context)
6804 goto out;
6805
6806 if (!rcs->init_context)
6807 goto out;
6808
6809 mutex_lock(&dev_priv->drm.struct_mutex);
6810
6811 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6812 if (IS_ERR(req))
6813 goto unlock;
6814
6815 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6816 rcs->init_context(req);
6817
6818 /* Mark the device busy, calling intel_enable_gt_powersave() */
6819 i915_add_request_no_flush(req);
6820
6821unlock:
6822 mutex_unlock(&dev_priv->drm.struct_mutex);
6823out:
6824 intel_runtime_pm_put(dev_priv);
6825}
6826
6827void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6828{
6829 if (READ_ONCE(dev_priv->rps.enabled))
6830 return;
6831
6832 if (IS_IRONLAKE_M(dev_priv)) {
6833 ironlake_enable_drps(dev_priv);
54b4f68f 6834 intel_init_emon(dev_priv);
54b4f68f
CW		 6835 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6836 /*
6837 * PCU communication is slow and this doesn't need to be
6838 * done at any specific time, so do this out of our fast path
6839 * to make resume and init faster.
6840 *
6841 * We depend on the HW RC6 power context save/restore
6842 * mechanism when entering D3 through runtime PM suspend. So
6843 * disable RPM until RPS/RC6 is properly setup. We can only
6844 * get here via the driver load/system resume/runtime resume
6845 * paths, so the _noresume version is enough (and in case of
6846 * runtime resume it's necessary).
6847 */
6848 if (queue_delayed_work(dev_priv->wq,
6849 &dev_priv->rps.autoenable_work,
6850 round_jiffies_up_relative(HZ)))
6851 intel_runtime_pm_get_noresume(dev_priv);
6852 }
6853}
6854
46f16e63 6855static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6856{
3107bd48
DV		 6857 /*
6858 * On Ibex Peak and Cougar Point, we need to disable clock
6859 * gating for the panel power sequencer or it will fail to
6860 * start up when no ports are active.
6861 */
6862 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6863}
6864
46f16e63 6865static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
0e088b8f 6866{
b12ce1d8 6867 enum pipe pipe;
0e088b8f 6868
055e393f 6869 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6870 I915_WRITE(DSPCNTR(pipe),
6871 I915_READ(DSPCNTR(pipe)) |
6872 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6873
6874 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6875 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6876 }
6877}
6878
46f16e63 6879static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
017636cc 6880{
017636cc
VS		 6881 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6882 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6883 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6884
6885 /*
6886 * Don't touch WM1S_LP_EN here.
6887 * Doing so could cause underruns.
6888 */
6889}
6890
46f16e63 6891static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 6892{
231e54f6 6893 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6894
f1e8fa56
DL		 6895 /*
6896 * Required for FBC
6897 * WaFbcDisableDpfcClockGating:ilk
6898 */
4d47e4f5
DL		 6899 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6900 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6901 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6902
6903 I915_WRITE(PCH_3DCGDIS0,
6904 MARIUNIT_CLOCK_GATE_DISABLE |
6905 SVSMUNIT_CLOCK_GATE_DISABLE);
6906 I915_WRITE(PCH_3DCGDIS1,
6907 VFMUNIT_CLOCK_GATE_DISABLE);
6908
6f1d69b0
ED		 6909 /*
6910 * According to the spec the following bits should be set in
6911 * order to enable memory self-refresh
6912 * The bit 22/21 of 0x42004
6913 * The bit 5 of 0x42020
6914 * The bit 15 of 0x45000
6915 */
6916 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6917 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6918 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6919 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6920 I915_WRITE(DISP_ARB_CTL,
6921 (I915_READ(DISP_ARB_CTL) |
6922 DISP_FBC_WM_DIS));
017636cc 6923
46f16e63 6924 ilk_init_lp_watermarks(dev_priv);
6f1d69b0
ED		 6925
6926 /*
6927 * Based on the document from hardware guys the following bits
6928 * should be set unconditionally in order to enable FBC.
6929 * The bit 22 of 0x42000
6930 * The bit 22 of 0x42004
6931 * The bit 7,8,9 of 0x42020.
6932 */
50a0bc90 6933 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6934 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6935 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6936 I915_READ(ILK_DISPLAY_CHICKEN1) |
6937 ILK_FBCQ_DIS);
6938 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6939 I915_READ(ILK_DISPLAY_CHICKEN2) |
6940 ILK_DPARB_GATE);
6f1d69b0
ED		 6941 }
6942
4d47e4f5
DL		 6943 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6944
6f1d69b0
ED		 6945 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6946 I915_READ(ILK_DISPLAY_CHICKEN2) |
6947 ILK_ELPIN_409_SELECT);
6948 I915_WRITE(_3D_CHICKEN2,
6949 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6950 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6951
ecdb4eb7 6952 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6953 I915_WRITE(CACHE_MODE_0,
6954 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6955
4e04632e
AG		 6956 /* WaDisable_RenderCache_OperationalFlush:ilk */
6957 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6958
46f16e63 6959 g4x_disable_trickle_feed(dev_priv);
bdad2b2f 6960
46f16e63 6961 ibx_init_clock_gating(dev_priv);
3107bd48
DV		 6962}
6963
46f16e63 6964static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6965{
3107bd48 6966 int pipe;
3f704fa2 6967 uint32_t val;
3107bd48
DV		 6968
6969 /*
6970 * On Ibex Peak and Cougar Point, we need to disable clock
6971 * gating for the panel power sequencer or it will fail to
6972 * start up when no ports are active.
6973 */
cd664078
JB		 6974 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6975 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6976 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6977 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6978 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6979 /* The below fixes the weird display corruption, a few pixels shifted
6980 * downward, on (only) LVDS of some HP laptops with IVY.
6981 */
055e393f 6982 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6983 val = I915_READ(TRANS_CHICKEN2(pipe));
6984 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6985 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6986 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6987 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6988 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6989 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6990 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6991 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6992 }
3107bd48 6993 /* WADP0ClockGatingDisable */
055e393f 6994 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6995 I915_WRITE(TRANS_CHICKEN1(pipe),
6996 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6997 }
6f1d69b0
ED		 6998}
6999
46f16e63 7000static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
1d7aaa0c 7001{
1d7aaa0c
DV		 7002 uint32_t tmp;
7003
7004 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7005 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7006 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7007 tmp);
1d7aaa0c
DV		 7008}
7009
46f16e63 7010static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7011{
231e54f6 7012 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7013
231e54f6 7014 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7015
7016 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7017 I915_READ(ILK_DISPLAY_CHICKEN2) |
7018 ILK_ELPIN_409_SELECT);
7019
ecdb4eb7 7020 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7021 I915_WRITE(_3D_CHICKEN,
7022 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7023
4e04632e
AG		 7024 /* WaDisable_RenderCache_OperationalFlush:snb */
7025 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7026
8d85d272
VS		 7027 /*
7028 * BSpec recoomends 8x4 when MSAA is used,
7029 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7030 *
7031 * Note that PS/WM thread counts depend on the WIZ hashing
7032 * disable bit, which we don't touch here, but it's good
7033 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7034 */
7035 I915_WRITE(GEN6_GT_MODE,
98533251 7036 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7037
46f16e63 7038 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7039
6f1d69b0 7040 I915_WRITE(CACHE_MODE_0,
50743298 7041 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7042
7043 I915_WRITE(GEN6_UCGCTL1,
7044 I915_READ(GEN6_UCGCTL1) |
7045 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7046 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7047
7048 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7049 * gating disable must be set. Failure to set it results in
7050 * flickering pixels due to Z write ordering failures after
7051 * some amount of runtime in the Mesa "fire" demo, and Unigine
7052 * Sanctuary and Tropics, and apparently anything else with
7053 * alpha test or pixel discard.
7054 *
7055 * According to the spec, bit 11 (RCCUNIT) must also be set,
7056 * but we didn't debug actual testcases to find it out.
0f846f81 7057 *
ef59318c
VS		 7058 * WaDisableRCCUnitClockGating:snb
7059 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7060 */
7061 I915_WRITE(GEN6_UCGCTL2,
7062 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7063 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7064
5eb146dd 7065 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7066 I915_WRITE(_3D_CHICKEN3,
7067 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7068
e927ecde
VS		 7069 /*
7070 * Bspec says:
7071 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7072 * 3DSTATE_SF number of SF output attributes is more than 16."
7073 */
7074 I915_WRITE(_3D_CHICKEN3,
7075 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7076
6f1d69b0
ED		 7077 /*
7078 * According to the spec the following bits should be
7079 * set in order to enable memory self-refresh and fbc:
7080 * The bit21 and bit22 of 0x42000
7081 * The bit21 and bit22 of 0x42004
7082 * The bit5 and bit7 of 0x42020
7083 * The bit14 of 0x70180
7084 * The bit14 of 0x71180
4bb35334
DL		 7085 *
7086 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7087 */
7088 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7089 I915_READ(ILK_DISPLAY_CHICKEN1) |
7090 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7091 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7092 I915_READ(ILK_DISPLAY_CHICKEN2) |
7093 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7094 I915_WRITE(ILK_DSPCLK_GATE_D,
7095 I915_READ(ILK_DSPCLK_GATE_D) |
7096 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7097 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7098
46f16e63 7099 g4x_disable_trickle_feed(dev_priv);
f8f2ac9a 7100
46f16e63 7101 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7102
46f16e63 7103 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7104}
7105
7106static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7107{
7108 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7109
3aad9059 7110 /*
46680e0a 7111 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7112 *
7113 * This actually overrides the dispatch
7114 * mode for all thread types.
7115 */
6f1d69b0
ED		 7116 reg &= ~GEN7_FF_SCHED_MASK;
7117 reg |= GEN7_FF_TS_SCHED_HW;
7118 reg |= GEN7_FF_VS_SCHED_HW;
7119 reg |= GEN7_FF_DS_SCHED_HW;
7120
7121 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7122}
7123
46f16e63 7124static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
17a303ec 7125{
17a303ec
PZ		 7126 /*
7127 * TODO: this bit should only be enabled when really needed, then
7128 * disabled when not needed anymore in order to save power.
7129 */
4f8036a2 7130 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7131 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7132 I915_READ(SOUTH_DSPCLK_GATE_D) |
7133 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7134
7135 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7136 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7137 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7138 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7139}
7140
712bf364 7141static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7142{
4f8036a2 7143 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7144 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7145
7146 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7147 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7148 }
7149}
7150
450174fe
ID		 7151static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7152 int general_prio_credits,
7153 int high_prio_credits)
7154{
7155 u32 misccpctl;
7156
7157 /* WaTempDisableDOPClkGating:bdw */
7158 misccpctl = I915_READ(GEN7_MISCCPCTL);
7159 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7160
7161 I915_WRITE(GEN8_L3SQCREG1,
7162 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7163 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7164
7165 /*
7166 * Wait at least 100 clocks before re-enabling clock gating.
7167 * See the definition of L3SQCREG1 in BSpec.
7168 */
7169 POSTING_READ(GEN8_L3SQCREG1);
7170 udelay(1);
7171 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7172}
7173
46f16e63 7174static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
9498dba7 7175{
46f16e63 7176 gen9_init_clock_gating(dev_priv);
9498dba7
MK		 7177
7178 /* WaDisableSDEUnitClockGating:kbl */
7179 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7180 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7181 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7182
7183 /* WaDisableGamClockGating:kbl */
7184 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7185 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7186 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7187
7188 /* WaFbcNukeOnHostModify:kbl */
7189 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7190 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7191}
7192
46f16e63 7193static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
dc00b6a0 7194{
46f16e63 7195 gen9_init_clock_gating(dev_priv);
44fff99f
MK		 7196
7197 /* WAC6entrylatency:skl */
7198 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7199 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7200
7201 /* WaFbcNukeOnHostModify:skl */
7202 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7203 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7204}
7205
46f16e63 7206static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
1020a5c2 7207{
07d27e20 7208 enum pipe pipe;
1020a5c2 7209
46f16e63 7210 ilk_init_lp_watermarks(dev_priv);
50ed5fbd 7211
ab57fff1 7212 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7213 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7214
ab57fff1 7215 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7216 I915_WRITE(CHICKEN_PAR1_1,
7217 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7218
ab57fff1 7219 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7220 for_each_pipe(dev_priv, pipe) {
07d27e20 7221 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7222 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7223 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7224 }
63801f21 7225
ab57fff1
BW		 7226 /* WaVSRefCountFullforceMissDisable:bdw */
7227 /* WaDSRefCountFullforceMissDisable:bdw */
7228 I915_WRITE(GEN7_FF_THREAD_MODE,
7229 I915_READ(GEN7_FF_THREAD_MODE) &
7230 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7231
295e8bb7
VS		 7232 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7233 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7234
7235 /* WaDisableSDEUnitClockGating:bdw */
7236 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7237 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7238
450174fe
ID		 7239 /* WaProgramL3SqcReg1Default:bdw */
7240 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7241
6d50b065
VS		 7242 /*
7243 * WaGttCachingOffByDefault:bdw
7244 * GTT cache may not work with big pages, so if those
7245 * are ever enabled GTT cache may need to be disabled.
7246 */
7247 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7248
17e0adf0
MK		 7249 /* WaKVMNotificationOnConfigChange:bdw */
7250 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7251 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7252
46f16e63 7253 lpt_init_clock_gating(dev_priv);
1020a5c2
BW		 7254}
7255
46f16e63 7256static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
cad2a2d7 7257{
46f16e63 7258 ilk_init_lp_watermarks(dev_priv);
cad2a2d7 7259
f3fc4884
FJ		 7260 /* L3 caching of data atomics doesn't work -- disable it. */
7261 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7262 I915_WRITE(HSW_ROW_CHICKEN3,
7263 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7264
ecdb4eb7 7265 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7266 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7267 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7268 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7269
e36ea7ff
VS		 7270 /* WaVSRefCountFullforceMissDisable:hsw */
7271 I915_WRITE(GEN7_FF_THREAD_MODE,
7272 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7273
4e04632e
AG		 7274 /* WaDisable_RenderCache_OperationalFlush:hsw */
7275 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7276
fe27c606
CW		 7277 /* enable HiZ Raw Stall Optimization */
7278 I915_WRITE(CACHE_MODE_0_GEN7,
7279 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7280
ecdb4eb7 7281 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7282 I915_WRITE(CACHE_MODE_1,
7283 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7284
a12c4967
VS		 7285 /*
7286 * BSpec recommends 8x4 when MSAA is used,
7287 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7288 *
7289 * Note that PS/WM thread counts depend on the WIZ hashing
7290 * disable bit, which we don't touch here, but it's good
7291 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7292 */
7293 I915_WRITE(GEN7_GT_MODE,
98533251 7294 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7295
94411593
KG		 7296 /* WaSampleCChickenBitEnable:hsw */
7297 I915_WRITE(HALF_SLICE_CHICKEN3,
7298 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7299
ecdb4eb7 7300 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7301 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7302
90a88643
PZ		 7303 /* WaRsPkgCStateDisplayPMReq:hsw */
7304 I915_WRITE(CHICKEN_PAR1_1,
7305 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7306
46f16e63 7307 lpt_init_clock_gating(dev_priv);
cad2a2d7
ED		 7308}
7309
46f16e63 7310static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7311{
20848223 7312 uint32_t snpcr;
6f1d69b0 7313
46f16e63 7314 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7315
231e54f6 7316 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7317
ecdb4eb7 7318 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7319 I915_WRITE(_3D_CHICKEN3,
7320 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7321
ecdb4eb7 7322 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7323 I915_WRITE(IVB_CHICKEN3,
7324 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7325 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7326
ecdb4eb7 7327 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7328 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7329 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7330 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7331
4e04632e
AG		 7332 /* WaDisable_RenderCache_OperationalFlush:ivb */
7333 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7334
ecdb4eb7 7335 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7336 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7337 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7338
ecdb4eb7 7339 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7340 I915_WRITE(GEN7_L3CNTLREG1,
7341 GEN7_WA_FOR_GEN7_L3_CONTROL);
7342 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7343 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7344 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7345 I915_WRITE(GEN7_ROW_CHICKEN2,
7346 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7347 else {
7348 /* must write both registers */
7349 I915_WRITE(GEN7_ROW_CHICKEN2,
7350 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7351 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7352 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7353 }
6f1d69b0 7354
ecdb4eb7 7355 /* WaForceL3Serialization:ivb */
61939d97
JB		 7356 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7357 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7358
1b80a19a 7359 /*
0f846f81 7360 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7361 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7362 */
7363 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7364 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7365
ecdb4eb7 7366 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7367 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7368 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7369 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7370
46f16e63 7371 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7372
7373 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7374
22721343
CW		 7375 if (0) { /* causes HiZ corruption on ivb:gt1 */
7376 /* enable HiZ Raw Stall Optimization */
7377 I915_WRITE(CACHE_MODE_0_GEN7,
7378 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7379 }
116f2b6d 7380
ecdb4eb7 7381 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7382 I915_WRITE(CACHE_MODE_1,
7383 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7384
a607c1a4
VS		 7385 /*
7386 * BSpec recommends 8x4 when MSAA is used,
7387 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7388 *
7389 * Note that PS/WM thread counts depend on the WIZ hashing
7390 * disable bit, which we don't touch here, but it's good
7391 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7392 */
7393 I915_WRITE(GEN7_GT_MODE,
98533251 7394 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7395
20848223
BW		 7396 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7397 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7398 snpcr |= GEN6_MBC_SNPCR_MED;
7399 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7400
6e266956 7401 if (!HAS_PCH_NOP(dev_priv))
46f16e63 7402 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7403
46f16e63 7404 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7405}
7406
46f16e63 7407static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7408{
ecdb4eb7 7409 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7410 I915_WRITE(_3D_CHICKEN3,
7411 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7412
ecdb4eb7 7413 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7414 I915_WRITE(IVB_CHICKEN3,
7415 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7416 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7417
fad7d36e 7418 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7419 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7420 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7421 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7422 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7423
4e04632e
AG		 7424 /* WaDisable_RenderCache_OperationalFlush:vlv */
7425 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7426
ecdb4eb7 7427 /* WaForceL3Serialization:vlv */
61939d97
JB		 7428 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7429 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7430
ecdb4eb7 7431 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7432 I915_WRITE(GEN7_ROW_CHICKEN2,
7433 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7434
ecdb4eb7 7435 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7436 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7437 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7438 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7439
46680e0a
VS		 7440 gen7_setup_fixed_func_scheduler(dev_priv);
7441
3c0edaeb 7442 /*
0f846f81 7443 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7444 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7445 */
7446 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7447 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7448
c98f5062
AG		 7449 /* WaDisableL3Bank2xClockGate:vlv
7450 * Disabling L3 clock gating- MMIO 940c[25] = 1
7451 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7452 I915_WRITE(GEN7_UCGCTL4,
7453 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7454
afd58e79
VS		 7455 /*
7456 * BSpec says this must be set, even though
7457 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7458 */
6b26c86d
DV		 7459 I915_WRITE(CACHE_MODE_1,
7460 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7461
da2518f9
VS		 7462 /*
7463 * BSpec recommends 8x4 when MSAA is used,
7464 * however in practice 16x4 seems fastest.
7465 *
7466 * Note that PS/WM thread counts depend on the WIZ hashing
7467 * disable bit, which we don't touch here, but it's good
7468 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7469 */
7470 I915_WRITE(GEN7_GT_MODE,
7471 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7472
031994ee
VS		 7473 /*
7474 * WaIncreaseL3CreditsForVLVB0:vlv
7475 * This is the hardware default actually.
7476 */
7477 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7478
2d809570 7479 /*
ecdb4eb7 7480 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7481 * Disable clock gating on th GCFG unit to prevent a delay
7482 * in the reporting of vblank events.
7483 */
7a0d1eed 7484 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7485}
7486
46f16e63 7487static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
a4565da8 7488{
232ce337
VS		 7489 /* WaVSRefCountFullforceMissDisable:chv */
7490 /* WaDSRefCountFullforceMissDisable:chv */
7491 I915_WRITE(GEN7_FF_THREAD_MODE,
7492 I915_READ(GEN7_FF_THREAD_MODE) &
7493 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7494
7495 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7496 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7497 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7498
7499 /* WaDisableCSUnitClockGating:chv */
7500 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7501 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7502
7503 /* WaDisableSDEUnitClockGating:chv */
7504 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7505 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7506
450174fe
ID		 7507 /*
7508 * WaProgramL3SqcReg1Default:chv
7509 * See gfxspecs/Related Documents/Performance Guide/
7510 * LSQC Setting Recommendations.
7511 */
7512 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7513
6d50b065
VS		 7514 /*
7515 * GTT cache may not work with big pages, so if those
7516 * are ever enabled GTT cache may need to be disabled.
7517 */
7518 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7519}
7520
46f16e63 7521static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7522{
6f1d69b0
ED		 7523 uint32_t dspclk_gate;
7524
7525 I915_WRITE(RENCLK_GATE_D1, 0);
7526 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7527 GS_UNIT_CLOCK_GATE_DISABLE |
7528 CL_UNIT_CLOCK_GATE_DISABLE);
7529 I915_WRITE(RAMCLK_GATE_D, 0);
7530 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7531 OVRUNIT_CLOCK_GATE_DISABLE |
7532 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7533 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7534 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7535 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7536
7537 /* WaDisableRenderCachePipelinedFlush */
7538 I915_WRITE(CACHE_MODE_0,
7539 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7540
4e04632e
AG		 7541 /* WaDisable_RenderCache_OperationalFlush:g4x */
7542 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7543
46f16e63 7544 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7545}
7546
46f16e63 7547static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7548{
6f1d69b0
ED		 7549 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7550 I915_WRITE(RENCLK_GATE_D2, 0);
7551 I915_WRITE(DSPCLK_GATE_D, 0);
7552 I915_WRITE(RAMCLK_GATE_D, 0);
7553 I915_WRITE16(DEUC, 0);
20f94967
VS		 7554 I915_WRITE(MI_ARB_STATE,
7555 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7556
7557 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7558 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7559}
7560
46f16e63 7561static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7562{
6f1d69b0
ED		 7563 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7564 I965_RCC_CLOCK_GATE_DISABLE |
7565 I965_RCPB_CLOCK_GATE_DISABLE |
7566 I965_ISC_CLOCK_GATE_DISABLE |
7567 I965_FBC_CLOCK_GATE_DISABLE);
7568 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7569 I915_WRITE(MI_ARB_STATE,
7570 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7571
7572 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7573 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7574}
7575
46f16e63 7576static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7577{
6f1d69b0
ED		 7578 u32 dstate = I915_READ(D_STATE);
7579
7580 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7581 DSTATE_DOT_CLOCK_GATING;
7582 I915_WRITE(D_STATE, dstate);
13a86b85 7583
9b1e14f4 7584 if (IS_PINEVIEW(dev_priv))
13a86b85 7585 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7586
7587 /* IIR "flip pending" means done if this bit is set */
7588 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7589
7590 /* interrupts should cause a wake up from C3 */
3299254f 7591 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7592
7593 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7594 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7595
7596 I915_WRITE(MI_ARB_STATE,
7597 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7598}
7599
46f16e63 7600static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7601{
6f1d69b0 7602 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7603
7604 /* interrupts should cause a wake up from C3 */
7605 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7606 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7607
7608 I915_WRITE(MEM_MODE,
7609 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7610}
7611
46f16e63 7612static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7613{
6f1d69b0 7614 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7615
7616 I915_WRITE(MEM_MODE,
7617 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7618 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7619}
7620
46f16e63 7621void intel_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7622{
46f16e63 7623 dev_priv->display.init_clock_gating(dev_priv);
6f1d69b0
ED		 7624}
7625
712bf364 7626void intel_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7627{
712bf364
VS		 7628 if (HAS_PCH_LPT(dev_priv))
7629 lpt_suspend_hw(dev_priv);
7d708ee4
ID		 7630}
7631
46f16e63 7632static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
bb400da9
ID		 7633{
7634 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7635}
7636
7637/**
7638 * intel_init_clock_gating_hooks - setup the clock gating hooks
7639 * @dev_priv: device private
7640 *
7641 * Setup the hooks that configure which clocks of a given platform can be
7642 * gated and also apply various GT and display specific workarounds for these
7643 * platforms. Note that some GT specific workarounds are applied separately
7644 * when GPU contexts or batchbuffers start their execution.
7645 */
7646void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7647{
7648 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7649 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7650 else if (IS_KABYLAKE(dev_priv))
9498dba7 7651 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7652 else if (IS_BROXTON(dev_priv))
7653 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7654 else if (IS_BROADWELL(dev_priv))
7655 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7656 else if (IS_CHERRYVIEW(dev_priv))
7657 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7658 else if (IS_HASWELL(dev_priv))
7659 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7660 else if (IS_IVYBRIDGE(dev_priv))
7661 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7662 else if (IS_VALLEYVIEW(dev_priv))
7663 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7664 else if (IS_GEN6(dev_priv))
7665 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7666 else if (IS_GEN5(dev_priv))
7667 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7668 else if (IS_G4X(dev_priv))
7669 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7670 else if (IS_CRESTLINE(dev_priv))
7671 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7672 else if (IS_BROADWATER(dev_priv))
7673 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7674 else if (IS_GEN3(dev_priv))
7675 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7676 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7677 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7678 else if (IS_GEN2(dev_priv))
7679 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7680 else {
7681 MISSING_CASE(INTEL_DEVID(dev_priv));
7682 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7683 }
7684}
7685
1fa61106 7686/* Set up chip specific power management-related functions */
62d75df7 7687void intel_init_pm(struct drm_i915_private *dev_priv)
1fa61106 7688{
7ff0ebcc 7689 intel_fbc_init(dev_priv);
1fa61106 7690
c921aba8 7691 /* For cxsr */
9b1e14f4 7692 if (IS_PINEVIEW(dev_priv))
148ac1f3 7693 i915_pineview_get_mem_freq(dev_priv);
5db94019 7694 else if (IS_GEN5(dev_priv))
148ac1f3 7695 i915_ironlake_get_mem_freq(dev_priv);
c921aba8 7696
1fa61106 7697 /* For FIFO watermark updates */
62d75df7 7698 if (INTEL_GEN(dev_priv) >= 9) {
bb726519 7699 skl_setup_wm_latency(dev_priv);
e62929b3 7700 dev_priv->display.initial_watermarks = skl_initial_wm;
ccf010fb 7701 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
98d39494 7702 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7703 } else if (HAS_PCH_SPLIT(dev_priv)) {
bb726519 7704 ilk_setup_wm_latency(dev_priv);
53615a5e 7705
5db94019 7706 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7707 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7708 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7709 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7710 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7711 dev_priv->display.compute_intermediate_wm =
7712 ilk_compute_intermediate_wm;
7713 dev_priv->display.initial_watermarks =
7714 ilk_initial_watermarks;
7715 dev_priv->display.optimize_watermarks =
7716 ilk_optimize_watermarks;
bd602544
VS		 7717 } else {
7718 DRM_DEBUG_KMS("Failed to read display plane latency. "
7719 "Disable CxSR\n");
7720 }
920a14b2 7721 } else if (IS_CHERRYVIEW(dev_priv)) {
bb726519 7722 vlv_setup_wm_latency(dev_priv);
262cd2e1 7723 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7724 } else if (IS_VALLEYVIEW(dev_priv)) {
bb726519 7725 vlv_setup_wm_latency(dev_priv);
26e1fe4f 7726 dev_priv->display.update_wm = vlv_update_wm;
9b1e14f4 7727 } else if (IS_PINEVIEW(dev_priv)) {
50a0bc90 7728 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7729 dev_priv->is_ddr3,
7730 dev_priv->fsb_freq,
7731 dev_priv->mem_freq)) {
7732 DRM_INFO("failed to find known CxSR latency "
7733 "(found ddr%s fsb freq %d, mem freq %d), "
7734 "disabling CxSR\n",
7735 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7736 dev_priv->fsb_freq, dev_priv->mem_freq);
7737 /* Disable CxSR and never update its watermark again */
5209b1f4 7738 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7739 dev_priv->display.update_wm = NULL;
7740 } else
7741 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7742 } else if (IS_G4X(dev_priv)) {
1fa61106 7743 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7744 } else if (IS_GEN4(dev_priv)) {
1fa61106 7745 dev_priv->display.update_wm = i965_update_wm;
5db94019 7746 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7747 dev_priv->display.update_wm = i9xx_update_wm;
7748 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7749 } else if (IS_GEN2(dev_priv)) {
62d75df7 7750 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
feb56b93 7751 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7752 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7753 } else {
7754 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7755 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7756 }
feb56b93
DV		 7757 } else {
7758 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7759 }
7760}
7761
87660502
L		 7762static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7763{
7764 uint32_t flags =
7765 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7766
7767 switch (flags) {
7768 case GEN6_PCODE_SUCCESS:
7769 return 0;
7770 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7771 case GEN6_PCODE_ILLEGAL_CMD:
7772 return -ENXIO;
7773 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7774 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7775 return -EOVERFLOW;
7776 case GEN6_PCODE_TIMEOUT:
7777 return -ETIMEDOUT;
7778 default:
7779 MISSING_CASE(flags)
7780 return 0;
7781 }
7782}
7783
7784static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7785{
7786 uint32_t flags =
7787 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7788
7789 switch (flags) {
7790 case GEN6_PCODE_SUCCESS:
7791 return 0;
7792 case GEN6_PCODE_ILLEGAL_CMD:
7793 return -ENXIO;
7794 case GEN7_PCODE_TIMEOUT:
7795 return -ETIMEDOUT;
7796 case GEN7_PCODE_ILLEGAL_DATA:
7797 return -EINVAL;
7798 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7799 return -EOVERFLOW;
7800 default:
7801 MISSING_CASE(flags);
7802 return 0;
7803 }
7804}
7805
151a49d0 7806int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7807{
87660502
L		 7808 int status;
7809
4fc688ce 7810 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7811
3f5582dd
CW		 7812 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7813 * use te fw I915_READ variants to reduce the amount of work
7814 * required when reading/writing.
7815 */
7816
7817 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7818 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7819 return -EAGAIN;
7820 }
7821
3f5582dd
CW		 7822 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7823 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7824 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7825
3f5582dd
CW		 7826 if (intel_wait_for_register_fw(dev_priv,
7827 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7828 500)) {
42c0526c
BW		 7829 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7830 return -ETIMEDOUT;
7831 }
7832
3f5582dd
CW		 7833 *val = I915_READ_FW(GEN6_PCODE_DATA);
7834 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7835
87660502
L		 7836 if (INTEL_GEN(dev_priv) > 6)
7837 status = gen7_check_mailbox_status(dev_priv);
7838 else
7839 status = gen6_check_mailbox_status(dev_priv);
7840
7841 if (status) {
7842 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7843 status);
7844 return status;
7845 }
7846
42c0526c
BW		 7847 return 0;
7848}
7849
3f5582dd 7850int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7851 u32 mbox, u32 val)
42c0526c 7852{
87660502
L		 7853 int status;
7854
4fc688ce 7855 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7856
3f5582dd
CW		 7857 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7858 * use te fw I915_READ variants to reduce the amount of work
7859 * required when reading/writing.
7860 */
7861
7862 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7863 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7864 return -EAGAIN;
7865 }
7866
3f5582dd
CW		 7867 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7868 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7869
3f5582dd
CW		 7870 if (intel_wait_for_register_fw(dev_priv,
7871 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7872 500)) {
42c0526c
BW		 7873 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7874 return -ETIMEDOUT;
7875 }
7876
3f5582dd 7877 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7878
87660502
L		 7879 if (INTEL_GEN(dev_priv) > 6)
7880 status = gen7_check_mailbox_status(dev_priv);
7881 else
7882 status = gen6_check_mailbox_status(dev_priv);
7883
7884 if (status) {
7885 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7886 status);
7887 return status;
7888 }
7889
42c0526c
BW		 7890 return 0;
7891}
a0e4e199 7892
dd06f88c
VS		 7893static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7894{
c30fec65
VS		 7895 /*
7896 * N = val - 0xb7
7897 * Slow = Fast = GPLL ref * N
7898 */
7899 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7900}
7901
b55dd647 7902static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7903{
c30fec65 7904 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7905}
7906
b55dd647 7907static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7908{
c30fec65
VS		 7909 /*
7910 * N = val / 2
7911 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7912 */
7913 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7914}
7915
b55dd647 7916static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7917{
1c14762d 7918 /* CHV needs even values */
c30fec65 7919 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7920}
7921
616bc820 7922int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7923{
2d1fe073 7924 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7925 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7926 GEN9_FREQ_SCALER);
2d1fe073 7927 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7928 return chv_gpu_freq(dev_priv, val);
2d1fe073 7929 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7930 return byt_gpu_freq(dev_priv, val);
7931 else
7932 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7933}
7934
616bc820
VS		 7935int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7936{
2d1fe073 7937 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7938 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7939 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7940 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7941 return chv_freq_opcode(dev_priv, val);
2d1fe073 7942 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7943 return byt_freq_opcode(dev_priv, val);
7944 else
500a3d2e 7945 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7946}
22b1b2f8 7947
6ad790c0
CW		 7948struct request_boost {
7949 struct work_struct work;
eed29a5b 7950 struct drm_i915_gem_request *req;
6ad790c0
CW		 7951};
7952
7953static void __intel_rps_boost_work(struct work_struct *work)
7954{
7955 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7956 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7957
f69a02c9 7958 if (!i915_gem_request_completed(req))
c033666a 7959 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7960
e8a261ea 7961 i915_gem_request_put(req);
6ad790c0
CW		 7962 kfree(boost);
7963}
7964
91d14251 7965void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7966{
7967 struct request_boost *boost;
7968
91d14251 7969 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7970 return;
7971
f69a02c9 7972 if (i915_gem_request_completed(req))
e61b9958
CW		 7973 return;
7974
6ad790c0
CW		 7975 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7976 if (boost == NULL)
7977 return;
7978
e8a261ea 7979 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7980
7981 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7982 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7983}
7984
f742a552 7985void intel_pm_setup(struct drm_device *dev)
907b28c5 7986{
fac5e23e 7987 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7988
f742a552 7989 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7990 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7991
54b4f68f
CW		 7992 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7993 __intel_autoenable_gt_powersave);
1854d5ca 7994 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7995
33688d95 7996 dev_priv->pm.suspended = false;
1f814dac 7997 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 7998}
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