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drm/i915: Restore rps/rc6 on reset
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 struct drm_framebuffer *fb = crtc->fb;
153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
224 struct drm_framebuffer *fb = crtc->fb;
225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 struct drm_framebuffer *fb = crtc->fb;
281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 297 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 298 } else {
7dd23ba0 299 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 300 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
301 HSW_BYPASS_FBC_QUEUE);
891348b2 302 }
b74ea102 303
abe959c7
RV		 304 I915_WRITE(SNB_DPFC_CTL_SA,
305 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
306 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
307
308 sandybridge_blit_fbc_update(dev);
309
b19870ee 310 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 311}
312
85208be0
ED		 313bool intel_fbc_enabled(struct drm_device *dev)
314{
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 if (!dev_priv->display.fbc_enabled)
318 return false;
319
320 return dev_priv->display.fbc_enabled(dev);
321}
322
323static void intel_fbc_work_fn(struct work_struct *__work)
324{
325 struct intel_fbc_work *work =
326 container_of(to_delayed_work(__work),
327 struct intel_fbc_work, work);
328 struct drm_device *dev = work->crtc->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330
331 mutex_lock(&dev->struct_mutex);
5c3fe8b0 332 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 333 /* Double check that we haven't switched fb without cancelling
334 * the prior work.
335 */
336 if (work->crtc->fb == work->fb) {
993495ae 337 dev_priv->display.enable_fbc(work->crtc);
85208be0 338
5c3fe8b0
BW		 339 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
340 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
341 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 342 }
343
5c3fe8b0 344 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 345 }
346 mutex_unlock(&dev->struct_mutex);
347
348 kfree(work);
349}
350
351static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
352{
5c3fe8b0 353 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 354 return;
355
356 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
357
358 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 359 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 360 * entirely asynchronously.
361 */
5c3fe8b0 362 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 363 /* tasklet was killed before being run, clean up */
5c3fe8b0 364 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 365
366 /* Mark the work as no longer wanted so that if it does
367 * wake-up (because the work was already running and waiting
368 * for our mutex), it will discover that is no longer
369 * necessary to run.
370 */
5c3fe8b0 371 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 372}
373
993495ae 374static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 375{
376 struct intel_fbc_work *work;
377 struct drm_device *dev = crtc->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379
380 if (!dev_priv->display.enable_fbc)
381 return;
382
383 intel_cancel_fbc_work(dev_priv);
384
b14c5679 385 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 386 if (work == NULL) {
6cdcb5e7 387 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 388 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 389 return;
390 }
391
392 work->crtc = crtc;
393 work->fb = crtc->fb;
85208be0
ED		 394 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
395
5c3fe8b0 396 dev_priv->fbc.fbc_work = work;
85208be0 397
85208be0
ED		 398 /* Delay the actual enabling to let pageflipping cease and the
399 * display to settle before starting the compression. Note that
400 * this delay also serves a second purpose: it allows for a
401 * vblank to pass after disabling the FBC before we attempt
402 * to modify the control registers.
403 *
404 * A more complicated solution would involve tracking vblanks
405 * following the termination of the page-flipping sequence
406 * and indeed performing the enable as a co-routine and not
407 * waiting synchronously upon the vblank.
7457d617
DL		 408 *
409 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 410 */
411 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
412}
413
414void intel_disable_fbc(struct drm_device *dev)
415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417
418 intel_cancel_fbc_work(dev_priv);
419
420 if (!dev_priv->display.disable_fbc)
421 return;
422
423 dev_priv->display.disable_fbc(dev);
5c3fe8b0 424 dev_priv->fbc.plane = -1;
85208be0
ED		 425}
426
29ebf90f
CW		 427static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
428 enum no_fbc_reason reason)
429{
430 if (dev_priv->fbc.no_fbc_reason == reason)
431 return false;
432
433 dev_priv->fbc.no_fbc_reason = reason;
434 return true;
435}
436
85208be0
ED		 437/**
438 * intel_update_fbc - enable/disable FBC as needed
439 * @dev: the drm_device
440 *
441 * Set up the framebuffer compression hardware at mode set time. We
442 * enable it if possible:
443 * - plane A only (on pre-965)
444 * - no pixel mulitply/line duplication
445 * - no alpha buffer discard
446 * - no dual wide
f85da868 447 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 448 *
449 * We can't assume that any compression will take place (worst case),
450 * so the compressed buffer has to be the same size as the uncompressed
451 * one. It also must reside (along with the line length buffer) in
452 * stolen memory.
453 *
454 * We need to enable/disable FBC on a global basis.
455 */
456void intel_update_fbc(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 struct drm_crtc *crtc = NULL, *tmp_crtc;
460 struct intel_crtc *intel_crtc;
461 struct drm_framebuffer *fb;
462 struct intel_framebuffer *intel_fb;
463 struct drm_i915_gem_object *obj;
ef644fda 464 const struct drm_display_mode *adjusted_mode;
37327abd 465 unsigned int max_width, max_height;
85208be0 466
3a77c4c4 467 if (!HAS_FBC(dev)) {
29ebf90f 468 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 469 return;
29ebf90f 470 }
85208be0 471
d330a953 472 if (!i915.powersave) {
29ebf90f
CW		 473 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
474 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 475 return;
29ebf90f 476 }
85208be0
ED		 477
478 /*
479 * If FBC is already on, we just have to verify that we can
480 * keep it that way...
481 * Need to disable if:
482 * - more than one pipe is active
483 * - changing FBC params (stride, fence, mode)
484 * - new fb is too large to fit in compressed buffer
485 * - going to an unsupported config (interlace, pixel multiply, etc.)
486 */
487 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 488 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 489 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 490 if (crtc) {
29ebf90f
CW		 491 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
492 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 493 goto out_disable;
494 }
495 crtc = tmp_crtc;
496 }
497 }
498
499 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 500 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
501 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 502 goto out_disable;
503 }
504
505 intel_crtc = to_intel_crtc(crtc);
506 fb = crtc->fb;
507 intel_fb = to_intel_framebuffer(fb);
508 obj = intel_fb->obj;
ef644fda 509 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 510
d330a953 511 if (i915.enable_fbc < 0 &&
8a5729a3 512 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
514 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 515 goto out_disable;
85208be0 516 }
d330a953 517 if (!i915.enable_fbc) {
29ebf90f
CW		 518 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
519 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 520 goto out_disable;
521 }
ef644fda
VS		 522 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
523 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 524 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
525 DRM_DEBUG_KMS("mode incompatible with compression, "
526 "disabling\n");
85208be0
ED		 527 goto out_disable;
528 }
f85da868
PZ		 529
530 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 531 max_width = 4096;
532 max_height = 2048;
f85da868 533 } else {
37327abd
VS		 534 max_width = 2048;
535 max_height = 1536;
f85da868 536 }
37327abd
VS		 537 if (intel_crtc->config.pipe_src_w > max_width ||
538 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 539 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
540 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 541 goto out_disable;
542 }
c5a44aa0
VS		 543 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
544 intel_crtc->plane != PLANE_A) {
29ebf90f 545 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 546 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 547 goto out_disable;
548 }
549
550 /* The use of a CPU fence is mandatory in order to detect writes
551 * by the CPU to the scanout and trigger updates to the FBC.
552 */
553 if (obj->tiling_mode != I915_TILING_X ||
554 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 555 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
556 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 557 goto out_disable;
558 }
559
560 /* If the kernel debugger is active, always disable compression */
561 if (in_dbg_master())
562 goto out_disable;
563
11be49eb 564 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 565 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
566 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 567 goto out_disable;
568 }
569
85208be0
ED		 570 /* If the scanout has not changed, don't modify the FBC settings.
571 * Note that we make the fundamental assumption that the fb->obj
572 * cannot be unpinned (and have its GTT offset and fence revoked)
573 * without first being decoupled from the scanout and FBC disabled.
574 */
5c3fe8b0
BW		 575 if (dev_priv->fbc.plane == intel_crtc->plane &&
576 dev_priv->fbc.fb_id == fb->base.id &&
577 dev_priv->fbc.y == crtc->y)
85208be0
ED		 578 return;
579
580 if (intel_fbc_enabled(dev)) {
581 /* We update FBC along two paths, after changing fb/crtc
582 * configuration (modeswitching) and after page-flipping
583 * finishes. For the latter, we know that not only did
584 * we disable the FBC at the start of the page-flip
585 * sequence, but also more than one vblank has passed.
586 *
587 * For the former case of modeswitching, it is possible
588 * to switch between two FBC valid configurations
589 * instantaneously so we do need to disable the FBC
590 * before we can modify its control registers. We also
591 * have to wait for the next vblank for that to take
592 * effect. However, since we delay enabling FBC we can
593 * assume that a vblank has passed since disabling and
594 * that we can safely alter the registers in the deferred
595 * callback.
596 *
597 * In the scenario that we go from a valid to invalid
598 * and then back to valid FBC configuration we have
599 * no strict enforcement that a vblank occurred since
600 * disabling the FBC. However, along all current pipe
601 * disabling paths we do need to wait for a vblank at
602 * some point. And we wait before enabling FBC anyway.
603 */
604 DRM_DEBUG_KMS("disabling active FBC for update\n");
605 intel_disable_fbc(dev);
606 }
607
993495ae 608 intel_enable_fbc(crtc);
29ebf90f 609 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 610 return;
611
612out_disable:
613 /* Multiple disables should be harmless */
614 if (intel_fbc_enabled(dev)) {
615 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
616 intel_disable_fbc(dev);
617 }
11be49eb 618 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 619}
620
c921aba8
DV		 621static void i915_pineview_get_mem_freq(struct drm_device *dev)
622{
623 drm_i915_private_t *dev_priv = dev->dev_private;
624 u32 tmp;
625
626 tmp = I915_READ(CLKCFG);
627
628 switch (tmp & CLKCFG_FSB_MASK) {
629 case CLKCFG_FSB_533:
630 dev_priv->fsb_freq = 533; /* 133*4 */
631 break;
632 case CLKCFG_FSB_800:
633 dev_priv->fsb_freq = 800; /* 200*4 */
634 break;
635 case CLKCFG_FSB_667:
636 dev_priv->fsb_freq = 667; /* 167*4 */
637 break;
638 case CLKCFG_FSB_400:
639 dev_priv->fsb_freq = 400; /* 100*4 */
640 break;
641 }
642
643 switch (tmp & CLKCFG_MEM_MASK) {
644 case CLKCFG_MEM_533:
645 dev_priv->mem_freq = 533;
646 break;
647 case CLKCFG_MEM_667:
648 dev_priv->mem_freq = 667;
649 break;
650 case CLKCFG_MEM_800:
651 dev_priv->mem_freq = 800;
652 break;
653 }
654
655 /* detect pineview DDR3 setting */
656 tmp = I915_READ(CSHRDDR3CTL);
657 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
658}
659
660static void i915_ironlake_get_mem_freq(struct drm_device *dev)
661{
662 drm_i915_private_t *dev_priv = dev->dev_private;
663 u16 ddrpll, csipll;
664
665 ddrpll = I915_READ16(DDRMPLL1);
666 csipll = I915_READ16(CSIPLL0);
667
668 switch (ddrpll & 0xff) {
669 case 0xc:
670 dev_priv->mem_freq = 800;
671 break;
672 case 0x10:
673 dev_priv->mem_freq = 1066;
674 break;
675 case 0x14:
676 dev_priv->mem_freq = 1333;
677 break;
678 case 0x18:
679 dev_priv->mem_freq = 1600;
680 break;
681 default:
682 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
683 ddrpll & 0xff);
684 dev_priv->mem_freq = 0;
685 break;
686 }
687
20e4d407 688 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 689
690 switch (csipll & 0x3ff) {
691 case 0x00c:
692 dev_priv->fsb_freq = 3200;
693 break;
694 case 0x00e:
695 dev_priv->fsb_freq = 3733;
696 break;
697 case 0x010:
698 dev_priv->fsb_freq = 4266;
699 break;
700 case 0x012:
701 dev_priv->fsb_freq = 4800;
702 break;
703 case 0x014:
704 dev_priv->fsb_freq = 5333;
705 break;
706 case 0x016:
707 dev_priv->fsb_freq = 5866;
708 break;
709 case 0x018:
710 dev_priv->fsb_freq = 6400;
711 break;
712 default:
713 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
714 csipll & 0x3ff);
715 dev_priv->fsb_freq = 0;
716 break;
717 }
718
719 if (dev_priv->fsb_freq == 3200) {
20e4d407 720 dev_priv->ips.c_m = 0;
c921aba8 721 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 722 dev_priv->ips.c_m = 1;
c921aba8 723 } else {
20e4d407 724 dev_priv->ips.c_m = 2;
c921aba8
DV		 725 }
726}
727
b445e3b0
ED		 728static const struct cxsr_latency cxsr_latency_table[] = {
729 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
730 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
731 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
732 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
733 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
734
735 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
736 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
737 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
738 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
739 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
740
741 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
742 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
743 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
744 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
745 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
746
747 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
748 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
749 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
750 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
751 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
752
753 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
754 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
755 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
756 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
757 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
758
759 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
760 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
761 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
762 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
763 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
764};
765
63c62275 766static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 767 int is_ddr3,
768 int fsb,
769 int mem)
770{
771 const struct cxsr_latency *latency;
772 int i;
773
774 if (fsb == 0 || mem == 0)
775 return NULL;
776
777 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
778 latency = &cxsr_latency_table[i];
779 if (is_desktop == latency->is_desktop &&
780 is_ddr3 == latency->is_ddr3 &&
781 fsb == latency->fsb_freq && mem == latency->mem_freq)
782 return latency;
783 }
784
785 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
786
787 return NULL;
788}
789
1fa61106 790static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 791{
792 struct drm_i915_private *dev_priv = dev->dev_private;
793
794 /* deactivate cxsr */
795 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
796}
797
798/*
799 * Latency for FIFO fetches is dependent on several factors:
800 * - memory configuration (speed, channels)
801 * - chipset
802 * - current MCH state
803 * It can be fairly high in some situations, so here we assume a fairly
804 * pessimal value. It's a tradeoff between extra memory fetches (if we
805 * set this value too high, the FIFO will fetch frequently to stay full)
806 * and power consumption (set it too low to save power and we might see
807 * FIFO underruns and display "flicker").
808 *
809 * A value of 5us seems to be a good balance; safe for very low end
810 * platforms but not overly aggressive on lower latency configs.
811 */
812static const int latency_ns = 5000;
813
1fa61106 814static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 uint32_t dsparb = I915_READ(DSPARB);
818 int size;
819
820 size = dsparb & 0x7f;
821 if (plane)
822 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
823
824 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
825 plane ? "B" : "A", size);
826
827 return size;
828}
829
feb56b93 830static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 uint32_t dsparb = I915_READ(DSPARB);
834 int size;
835
836 size = dsparb & 0x1ff;
837 if (plane)
838 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
839 size >>= 1; /* Convert to cachelines */
840
841 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
842 plane ? "B" : "A", size);
843
844 return size;
845}
846
1fa61106 847static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 848{
849 struct drm_i915_private *dev_priv = dev->dev_private;
850 uint32_t dsparb = I915_READ(DSPARB);
851 int size;
852
853 size = dsparb & 0x7f;
854 size >>= 2; /* Convert to cachelines */
855
856 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
857 plane ? "B" : "A",
858 size);
859
860 return size;
861}
862
b445e3b0
ED		 863/* Pineview has different values for various configs */
864static const struct intel_watermark_params pineview_display_wm = {
865 PINEVIEW_DISPLAY_FIFO,
866 PINEVIEW_MAX_WM,
867 PINEVIEW_DFT_WM,
868 PINEVIEW_GUARD_WM,
869 PINEVIEW_FIFO_LINE_SIZE
870};
871static const struct intel_watermark_params pineview_display_hplloff_wm = {
872 PINEVIEW_DISPLAY_FIFO,
873 PINEVIEW_MAX_WM,
874 PINEVIEW_DFT_HPLLOFF_WM,
875 PINEVIEW_GUARD_WM,
876 PINEVIEW_FIFO_LINE_SIZE
877};
878static const struct intel_watermark_params pineview_cursor_wm = {
879 PINEVIEW_CURSOR_FIFO,
880 PINEVIEW_CURSOR_MAX_WM,
881 PINEVIEW_CURSOR_DFT_WM,
882 PINEVIEW_CURSOR_GUARD_WM,
883 PINEVIEW_FIFO_LINE_SIZE,
884};
885static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
886 PINEVIEW_CURSOR_FIFO,
887 PINEVIEW_CURSOR_MAX_WM,
888 PINEVIEW_CURSOR_DFT_WM,
889 PINEVIEW_CURSOR_GUARD_WM,
890 PINEVIEW_FIFO_LINE_SIZE
891};
892static const struct intel_watermark_params g4x_wm_info = {
893 G4X_FIFO_SIZE,
894 G4X_MAX_WM,
895 G4X_MAX_WM,
896 2,
897 G4X_FIFO_LINE_SIZE,
898};
899static const struct intel_watermark_params g4x_cursor_wm_info = {
900 I965_CURSOR_FIFO,
901 I965_CURSOR_MAX_WM,
902 I965_CURSOR_DFT_WM,
903 2,
904 G4X_FIFO_LINE_SIZE,
905};
906static const struct intel_watermark_params valleyview_wm_info = {
907 VALLEYVIEW_FIFO_SIZE,
908 VALLEYVIEW_MAX_WM,
909 VALLEYVIEW_MAX_WM,
910 2,
911 G4X_FIFO_LINE_SIZE,
912};
913static const struct intel_watermark_params valleyview_cursor_wm_info = {
914 I965_CURSOR_FIFO,
915 VALLEYVIEW_CURSOR_MAX_WM,
916 I965_CURSOR_DFT_WM,
917 2,
918 G4X_FIFO_LINE_SIZE,
919};
920static const struct intel_watermark_params i965_cursor_wm_info = {
921 I965_CURSOR_FIFO,
922 I965_CURSOR_MAX_WM,
923 I965_CURSOR_DFT_WM,
924 2,
925 I915_FIFO_LINE_SIZE,
926};
927static const struct intel_watermark_params i945_wm_info = {
928 I945_FIFO_SIZE,
929 I915_MAX_WM,
930 1,
931 2,
932 I915_FIFO_LINE_SIZE
933};
934static const struct intel_watermark_params i915_wm_info = {
935 I915_FIFO_SIZE,
936 I915_MAX_WM,
937 1,
938 2,
939 I915_FIFO_LINE_SIZE
940};
feb56b93 941static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 942 I855GM_FIFO_SIZE,
943 I915_MAX_WM,
944 1,
945 2,
946 I830_FIFO_LINE_SIZE
947};
feb56b93 948static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 949 I830_FIFO_SIZE,
950 I915_MAX_WM,
951 1,
952 2,
953 I830_FIFO_LINE_SIZE
954};
955
b445e3b0
ED		 956/**
957 * intel_calculate_wm - calculate watermark level
958 * @clock_in_khz: pixel clock
959 * @wm: chip FIFO params
960 * @pixel_size: display pixel size
961 * @latency_ns: memory latency for the platform
962 *
963 * Calculate the watermark level (the level at which the display plane will
964 * start fetching from memory again). Each chip has a different display
965 * FIFO size and allocation, so the caller needs to figure that out and pass
966 * in the correct intel_watermark_params structure.
967 *
968 * As the pixel clock runs, the FIFO will be drained at a rate that depends
969 * on the pixel size. When it reaches the watermark level, it'll start
970 * fetching FIFO line sized based chunks from memory until the FIFO fills
971 * past the watermark point. If the FIFO drains completely, a FIFO underrun
972 * will occur, and a display engine hang could result.
973 */
974static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
975 const struct intel_watermark_params *wm,
976 int fifo_size,
977 int pixel_size,
978 unsigned long latency_ns)
979{
980 long entries_required, wm_size;
981
982 /*
983 * Note: we need to make sure we don't overflow for various clock &
984 * latency values.
985 * clocks go from a few thousand to several hundred thousand.
986 * latency is usually a few thousand
987 */
988 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
989 1000;
990 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
991
992 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
993
994 wm_size = fifo_size - (entries_required + wm->guard_size);
995
996 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
997
998 /* Don't promote wm_size to unsigned... */
999 if (wm_size > (long)wm->max_wm)
1000 wm_size = wm->max_wm;
1001 if (wm_size <= 0)
1002 wm_size = wm->default_wm;
1003 return wm_size;
1004}
1005
1006static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1007{
1008 struct drm_crtc *crtc, *enabled = NULL;
1009
1010 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1011 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1012 if (enabled)
1013 return NULL;
1014 enabled = crtc;
1015 }
1016 }
1017
1018 return enabled;
1019}
1020
46ba614c 1021static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1022{
46ba614c 1023 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 struct drm_crtc *crtc;
1026 const struct cxsr_latency *latency;
1027 u32 reg;
1028 unsigned long wm;
1029
1030 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1031 dev_priv->fsb_freq, dev_priv->mem_freq);
1032 if (!latency) {
1033 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1034 pineview_disable_cxsr(dev);
1035 return;
1036 }
1037
1038 crtc = single_enabled_crtc(dev);
1039 if (crtc) {
241bfc38 1040 const struct drm_display_mode *adjusted_mode;
b445e3b0 1041 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1042 int clock;
1043
1044 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1045 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1046
1047 /* Display SR */
1048 wm = intel_calculate_wm(clock, &pineview_display_wm,
1049 pineview_display_wm.fifo_size,
1050 pixel_size, latency->display_sr);
1051 reg = I915_READ(DSPFW1);
1052 reg &= ~DSPFW_SR_MASK;
1053 reg |= wm << DSPFW_SR_SHIFT;
1054 I915_WRITE(DSPFW1, reg);
1055 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1056
1057 /* cursor SR */
1058 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1059 pineview_display_wm.fifo_size,
1060 pixel_size, latency->cursor_sr);
1061 reg = I915_READ(DSPFW3);
1062 reg &= ~DSPFW_CURSOR_SR_MASK;
1063 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1064 I915_WRITE(DSPFW3, reg);
1065
1066 /* Display HPLL off SR */
1067 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1068 pineview_display_hplloff_wm.fifo_size,
1069 pixel_size, latency->display_hpll_disable);
1070 reg = I915_READ(DSPFW3);
1071 reg &= ~DSPFW_HPLL_SR_MASK;
1072 reg |= wm & DSPFW_HPLL_SR_MASK;
1073 I915_WRITE(DSPFW3, reg);
1074
1075 /* cursor HPLL off SR */
1076 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1077 pineview_display_hplloff_wm.fifo_size,
1078 pixel_size, latency->cursor_hpll_disable);
1079 reg = I915_READ(DSPFW3);
1080 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1081 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1082 I915_WRITE(DSPFW3, reg);
1083 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1084
1085 /* activate cxsr */
1086 I915_WRITE(DSPFW3,
1087 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1088 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1089 } else {
1090 pineview_disable_cxsr(dev);
1091 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1092 }
1093}
1094
1095static bool g4x_compute_wm0(struct drm_device *dev,
1096 int plane,
1097 const struct intel_watermark_params *display,
1098 int display_latency_ns,
1099 const struct intel_watermark_params *cursor,
1100 int cursor_latency_ns,
1101 int *plane_wm,
1102 int *cursor_wm)
1103{
1104 struct drm_crtc *crtc;
4fe8590a 1105 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1106 int htotal, hdisplay, clock, pixel_size;
1107 int line_time_us, line_count;
1108 int entries, tlb_miss;
1109
1110 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1111 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1112 *cursor_wm = cursor->guard_size;
1113 *plane_wm = display->guard_size;
1114 return false;
1115 }
1116
4fe8590a 1117 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1118 clock = adjusted_mode->crtc_clock;
fec8cba3 1119 htotal = adjusted_mode->crtc_htotal;
37327abd 1120 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1121 pixel_size = crtc->fb->bits_per_pixel / 8;
1122
1123 /* Use the small buffer method to calculate plane watermark */
1124 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1125 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1126 if (tlb_miss > 0)
1127 entries += tlb_miss;
1128 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1129 *plane_wm = entries + display->guard_size;
1130 if (*plane_wm > (int)display->max_wm)
1131 *plane_wm = display->max_wm;
1132
1133 /* Use the large buffer method to calculate cursor watermark */
1134 line_time_us = ((htotal * 1000) / clock);
1135 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1136 entries = line_count * 64 * pixel_size;
1137 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1138 if (tlb_miss > 0)
1139 entries += tlb_miss;
1140 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1141 *cursor_wm = entries + cursor->guard_size;
1142 if (*cursor_wm > (int)cursor->max_wm)
1143 *cursor_wm = (int)cursor->max_wm;
1144
1145 return true;
1146}
1147
1148/*
1149 * Check the wm result.
1150 *
1151 * If any calculated watermark values is larger than the maximum value that
1152 * can be programmed into the associated watermark register, that watermark
1153 * must be disabled.
1154 */
1155static bool g4x_check_srwm(struct drm_device *dev,
1156 int display_wm, int cursor_wm,
1157 const struct intel_watermark_params *display,
1158 const struct intel_watermark_params *cursor)
1159{
1160 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1161 display_wm, cursor_wm);
1162
1163 if (display_wm > display->max_wm) {
1164 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1165 display_wm, display->max_wm);
1166 return false;
1167 }
1168
1169 if (cursor_wm > cursor->max_wm) {
1170 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1171 cursor_wm, cursor->max_wm);
1172 return false;
1173 }
1174
1175 if (!(display_wm || cursor_wm)) {
1176 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1177 return false;
1178 }
1179
1180 return true;
1181}
1182
1183static bool g4x_compute_srwm(struct drm_device *dev,
1184 int plane,
1185 int latency_ns,
1186 const struct intel_watermark_params *display,
1187 const struct intel_watermark_params *cursor,
1188 int *display_wm, int *cursor_wm)
1189{
1190 struct drm_crtc *crtc;
4fe8590a 1191 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1192 int hdisplay, htotal, pixel_size, clock;
1193 unsigned long line_time_us;
1194 int line_count, line_size;
1195 int small, large;
1196 int entries;
1197
1198 if (!latency_ns) {
1199 *display_wm = *cursor_wm = 0;
1200 return false;
1201 }
1202
1203 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1204 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1205 clock = adjusted_mode->crtc_clock;
fec8cba3 1206 htotal = adjusted_mode->crtc_htotal;
37327abd 1207 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1208 pixel_size = crtc->fb->bits_per_pixel / 8;
1209
1210 line_time_us = (htotal * 1000) / clock;
1211 line_count = (latency_ns / line_time_us + 1000) / 1000;
1212 line_size = hdisplay * pixel_size;
1213
1214 /* Use the minimum of the small and large buffer method for primary */
1215 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1216 large = line_count * line_size;
1217
1218 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1219 *display_wm = entries + display->guard_size;
1220
1221 /* calculate the self-refresh watermark for display cursor */
1222 entries = line_count * pixel_size * 64;
1223 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1224 *cursor_wm = entries + cursor->guard_size;
1225
1226 return g4x_check_srwm(dev,
1227 *display_wm, *cursor_wm,
1228 display, cursor);
1229}
1230
1231static bool vlv_compute_drain_latency(struct drm_device *dev,
1232 int plane,
1233 int *plane_prec_mult,
1234 int *plane_dl,
1235 int *cursor_prec_mult,
1236 int *cursor_dl)
1237{
1238 struct drm_crtc *crtc;
1239 int clock, pixel_size;
1240 int entries;
1241
1242 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1243 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1244 return false;
1245
241bfc38 1246 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1247 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1248
1249 entries = (clock / 1000) * pixel_size;
1250 *plane_prec_mult = (entries > 256) ?
1251 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1252 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1253 pixel_size);
1254
1255 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1256 *cursor_prec_mult = (entries > 256) ?
1257 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1258 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1259
1260 return true;
1261}
1262
1263/*
1264 * Update drain latency registers of memory arbiter
1265 *
1266 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1267 * to be programmed. Each plane has a drain latency multiplier and a drain
1268 * latency value.
1269 */
1270
1271static void vlv_update_drain_latency(struct drm_device *dev)
1272{
1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1275 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1276 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1277 either 16 or 32 */
1278
1279 /* For plane A, Cursor A */
1280 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1281 &cursor_prec_mult, &cursora_dl)) {
1282 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1284 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1285 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1286
1287 I915_WRITE(VLV_DDL1, cursora_prec |
1288 (cursora_dl << DDL_CURSORA_SHIFT) |
1289 planea_prec | planea_dl);
1290 }
1291
1292 /* For plane B, Cursor B */
1293 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1294 &cursor_prec_mult, &cursorb_dl)) {
1295 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1296 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1297 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1298 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1299
1300 I915_WRITE(VLV_DDL2, cursorb_prec |
1301 (cursorb_dl << DDL_CURSORB_SHIFT) |
1302 planeb_prec | planeb_dl);
1303 }
1304}
1305
1306#define single_plane_enabled(mask) is_power_of_2(mask)
1307
46ba614c 1308static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1309{
46ba614c 1310 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1311 static const int sr_latency_ns = 12000;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1314 int plane_sr, cursor_sr;
af6c4575 1315 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1316 unsigned int enabled = 0;
1317
1318 vlv_update_drain_latency(dev);
1319
51cea1f4 1320 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1321 &valleyview_wm_info, latency_ns,
1322 &valleyview_cursor_wm_info, latency_ns,
1323 &planea_wm, &cursora_wm))
51cea1f4 1324 enabled |= 1 << PIPE_A;
b445e3b0 1325
51cea1f4 1326 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1327 &valleyview_wm_info, latency_ns,
1328 &valleyview_cursor_wm_info, latency_ns,
1329 &planeb_wm, &cursorb_wm))
51cea1f4 1330 enabled |= 1 << PIPE_B;
b445e3b0 1331
b445e3b0
ED		 1332 if (single_plane_enabled(enabled) &&
1333 g4x_compute_srwm(dev, ffs(enabled) - 1,
1334 sr_latency_ns,
1335 &valleyview_wm_info,
1336 &valleyview_cursor_wm_info,
af6c4575
CW		 1337 &plane_sr, &ignore_cursor_sr) &&
1338 g4x_compute_srwm(dev, ffs(enabled) - 1,
1339 2*sr_latency_ns,
1340 &valleyview_wm_info,
1341 &valleyview_cursor_wm_info,
52bd02d8 1342 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1343 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1344 } else {
b445e3b0
ED		 1345 I915_WRITE(FW_BLC_SELF_VLV,
1346 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1347 plane_sr = cursor_sr = 0;
1348 }
b445e3b0
ED		 1349
1350 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1351 planea_wm, cursora_wm,
1352 planeb_wm, cursorb_wm,
1353 plane_sr, cursor_sr);
1354
1355 I915_WRITE(DSPFW1,
1356 (plane_sr << DSPFW_SR_SHIFT) |
1357 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1358 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1359 planea_wm);
1360 I915_WRITE(DSPFW2,
8c919b28 1361 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1362 (cursora_wm << DSPFW_CURSORA_SHIFT));
1363 I915_WRITE(DSPFW3,
8c919b28
CW		 1364 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1365 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1366}
1367
46ba614c 1368static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1369{
46ba614c 1370 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1371 static const int sr_latency_ns = 12000;
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1374 int plane_sr, cursor_sr;
1375 unsigned int enabled = 0;
1376
51cea1f4 1377 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1378 &g4x_wm_info, latency_ns,
1379 &g4x_cursor_wm_info, latency_ns,
1380 &planea_wm, &cursora_wm))
51cea1f4 1381 enabled |= 1 << PIPE_A;
b445e3b0 1382
51cea1f4 1383 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1384 &g4x_wm_info, latency_ns,
1385 &g4x_cursor_wm_info, latency_ns,
1386 &planeb_wm, &cursorb_wm))
51cea1f4 1387 enabled |= 1 << PIPE_B;
b445e3b0 1388
b445e3b0
ED		 1389 if (single_plane_enabled(enabled) &&
1390 g4x_compute_srwm(dev, ffs(enabled) - 1,
1391 sr_latency_ns,
1392 &g4x_wm_info,
1393 &g4x_cursor_wm_info,
52bd02d8 1394 &plane_sr, &cursor_sr)) {
b445e3b0 1395 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1396 } else {
b445e3b0
ED		 1397 I915_WRITE(FW_BLC_SELF,
1398 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1399 plane_sr = cursor_sr = 0;
1400 }
b445e3b0
ED		 1401
1402 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403 planea_wm, cursora_wm,
1404 planeb_wm, cursorb_wm,
1405 plane_sr, cursor_sr);
1406
1407 I915_WRITE(DSPFW1,
1408 (plane_sr << DSPFW_SR_SHIFT) |
1409 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1410 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1411 planea_wm);
1412 I915_WRITE(DSPFW2,
8c919b28 1413 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1414 (cursora_wm << DSPFW_CURSORA_SHIFT));
1415 /* HPLL off in SR has some issues on G4x... disable it */
1416 I915_WRITE(DSPFW3,
8c919b28 1417 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1418 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1419}
1420
46ba614c 1421static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1422{
46ba614c 1423 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1424 struct drm_i915_private *dev_priv = dev->dev_private;
1425 struct drm_crtc *crtc;
1426 int srwm = 1;
1427 int cursor_sr = 16;
1428
1429 /* Calc sr entries for one plane configs */
1430 crtc = single_enabled_crtc(dev);
1431 if (crtc) {
1432 /* self-refresh has much higher latency */
1433 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1434 const struct drm_display_mode *adjusted_mode =
1435 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1436 int clock = adjusted_mode->crtc_clock;
fec8cba3 1437 int htotal = adjusted_mode->crtc_htotal;
37327abd 1438 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1439 int pixel_size = crtc->fb->bits_per_pixel / 8;
1440 unsigned long line_time_us;
1441 int entries;
1442
1443 line_time_us = ((htotal * 1000) / clock);
1444
1445 /* Use ns/us then divide to preserve precision */
1446 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1447 pixel_size * hdisplay;
1448 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1449 srwm = I965_FIFO_SIZE - entries;
1450 if (srwm < 0)
1451 srwm = 1;
1452 srwm &= 0x1ff;
1453 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1454 entries, srwm);
1455
1456 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1457 pixel_size * 64;
1458 entries = DIV_ROUND_UP(entries,
1459 i965_cursor_wm_info.cacheline_size);
1460 cursor_sr = i965_cursor_wm_info.fifo_size -
1461 (entries + i965_cursor_wm_info.guard_size);
1462
1463 if (cursor_sr > i965_cursor_wm_info.max_wm)
1464 cursor_sr = i965_cursor_wm_info.max_wm;
1465
1466 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1467 "cursor %d\n", srwm, cursor_sr);
1468
1469 if (IS_CRESTLINE(dev))
1470 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1471 } else {
1472 /* Turn off self refresh if both pipes are enabled */
1473 if (IS_CRESTLINE(dev))
1474 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1475 & ~FW_BLC_SELF_EN);
1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
1482 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1483 (8 << 16) | (8 << 8) | (8 << 0));
1484 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1485 /* update cursor SR watermark */
1486 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1487}
1488
46ba614c 1489static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1490{
46ba614c 1491 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 const struct intel_watermark_params *wm_info;
1494 uint32_t fwater_lo;
1495 uint32_t fwater_hi;
1496 int cwm, srwm = 1;
1497 int fifo_size;
1498 int planea_wm, planeb_wm;
1499 struct drm_crtc *crtc, *enabled = NULL;
1500
1501 if (IS_I945GM(dev))
1502 wm_info = &i945_wm_info;
1503 else if (!IS_GEN2(dev))
1504 wm_info = &i915_wm_info;
1505 else
feb56b93 1506 wm_info = &i830_wm_info;
b445e3b0
ED		 1507
1508 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1509 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1510 if (intel_crtc_active(crtc)) {
241bfc38 1511 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1512 int cpp = crtc->fb->bits_per_pixel / 8;
1513 if (IS_GEN2(dev))
1514 cpp = 4;
1515
241bfc38
DL		 1516 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1517 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1518 wm_info, fifo_size, cpp,
b445e3b0
ED		 1519 latency_ns);
1520 enabled = crtc;
1521 } else
1522 planea_wm = fifo_size - wm_info->guard_size;
1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1528 int cpp = crtc->fb->bits_per_pixel / 8;
1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
241bfc38
DL		 1532 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
b445e3b0
ED		 1535 latency_ns);
1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
1540 } else
1541 planeb_wm = fifo_size - wm_info->guard_size;
1542
1543 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1544
1545 /*
1546 * Overlay gets an aggressive default since video jitter is bad.
1547 */
1548 cwm = 2;
1549
1550 /* Play safe and disable self-refresh before adjusting watermarks. */
1551 if (IS_I945G(dev) || IS_I945GM(dev))
1552 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1553 else if (IS_I915GM(dev))
3f2dc5ac 1554 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1555
1556 /* Calc sr entries for one plane configs */
1557 if (HAS_FW_BLC(dev) && enabled) {
1558 /* self-refresh has much higher latency */
1559 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1560 const struct drm_display_mode *adjusted_mode =
1561 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1562 int clock = adjusted_mode->crtc_clock;
fec8cba3 1563 int htotal = adjusted_mode->crtc_htotal;
f727b490 1564 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
b445e3b0
ED		 1565 int pixel_size = enabled->fb->bits_per_pixel / 8;
1566 unsigned long line_time_us;
1567 int entries;
1568
1569 line_time_us = (htotal * 1000) / clock;
1570
1571 /* Use ns/us then divide to preserve precision */
1572 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1573 pixel_size * hdisplay;
1574 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1575 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1576 srwm = wm_info->fifo_size - entries;
1577 if (srwm < 0)
1578 srwm = 1;
1579
1580 if (IS_I945G(dev) || IS_I945GM(dev))
1581 I915_WRITE(FW_BLC_SELF,
1582 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1583 else if (IS_I915GM(dev))
1584 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1585 }
1586
1587 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1588 planea_wm, planeb_wm, cwm, srwm);
1589
1590 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1591 fwater_hi = (cwm & 0x1f);
1592
1593 /* Set request length to 8 cachelines per fetch */
1594 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1595 fwater_hi = fwater_hi | (1 << 8);
1596
1597 I915_WRITE(FW_BLC, fwater_lo);
1598 I915_WRITE(FW_BLC2, fwater_hi);
1599
1600 if (HAS_FW_BLC(dev)) {
1601 if (enabled) {
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1605 else if (IS_I915GM(dev))
3f2dc5ac 1606 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1607 DRM_DEBUG_KMS("memory self refresh enabled\n");
1608 } else
1609 DRM_DEBUG_KMS("memory self refresh disabled\n");
1610 }
1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
241bfc38
DL		 1626 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1630 4, latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
3658729a
VS		 1639static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1640 struct drm_crtc *crtc)
801bcfff
PZ		 1641{
1642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1643 uint32_t pixel_rate;
801bcfff 1644
241bfc38 1645 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1646
1647 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1648 * adjust the pixel_rate here. */
1649
fd4daa9c 1650 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1651 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1652 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1653
37327abd
VS		 1654 pipe_w = intel_crtc->config.pipe_src_w;
1655 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1656 pfit_w = (pfit_size >> 16) & 0xFFFF;
1657 pfit_h = pfit_size & 0xFFFF;
1658 if (pipe_w < pfit_w)
1659 pipe_w = pfit_w;
1660 if (pipe_h < pfit_h)
1661 pipe_h = pfit_h;
1662
1663 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1664 pfit_w * pfit_h);
1665 }
1666
1667 return pixel_rate;
1668}
1669
37126462 1670/* latency must be in 0.1us units. */
23297044 1671static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1672 uint32_t latency)
1673{
1674 uint64_t ret;
1675
3312ba65
VS		 1676 if (WARN(latency == 0, "Latency value missing\n"))
1677 return UINT_MAX;
1678
801bcfff
PZ		 1679 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1680 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1681
1682 return ret;
1683}
1684
37126462 1685/* latency must be in 0.1us units. */
23297044 1686static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1687 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1688 uint32_t latency)
1689{
1690 uint32_t ret;
1691
3312ba65
VS		 1692 if (WARN(latency == 0, "Latency value missing\n"))
1693 return UINT_MAX;
1694
801bcfff
PZ		 1695 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1696 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1697 ret = DIV_ROUND_UP(ret, 64) + 2;
1698 return ret;
1699}
1700
23297044 1701static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1702 uint8_t bytes_per_pixel)
1703{
1704 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1705}
1706
820c1980 1707struct ilk_pipe_wm_parameters {
801bcfff 1708 bool active;
801bcfff
PZ		 1709 uint32_t pipe_htotal;
1710 uint32_t pixel_rate;
c35426d2
VS		 1711 struct intel_plane_wm_parameters pri;
1712 struct intel_plane_wm_parameters spr;
1713 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1714};
1715
820c1980 1716struct ilk_wm_maximums {
cca32e9a
PZ		 1717 uint16_t pri;
1718 uint16_t spr;
1719 uint16_t cur;
1720 uint16_t fbc;
1721};
1722
240264f4
VS		 1723/* used in computing the new watermarks state */
1724struct intel_wm_config {
1725 unsigned int num_pipes_active;
1726 bool sprites_enabled;
1727 bool sprites_scaled;
240264f4
VS		 1728};
1729
37126462
VS		 1730/*
1731 * For both WM_PIPE and WM_LP.
1732 * mem_value must be in 0.1us units.
1733 */
820c1980 1734static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1735 uint32_t mem_value,
1736 bool is_lp)
801bcfff 1737{
cca32e9a
PZ		 1738 uint32_t method1, method2;
1739
c35426d2 1740 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1741 return 0;
1742
23297044 1743 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1744 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1745 mem_value);
1746
1747 if (!is_lp)
1748 return method1;
1749
23297044 1750 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1751 params->pipe_htotal,
c35426d2
VS		 1752 params->pri.horiz_pixels,
1753 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1754 mem_value);
1755
1756 return min(method1, method2);
801bcfff
PZ		 1757}
1758
37126462
VS		 1759/*
1760 * For both WM_PIPE and WM_LP.
1761 * mem_value must be in 0.1us units.
1762 */
820c1980 1763static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1764 uint32_t mem_value)
1765{
1766 uint32_t method1, method2;
1767
c35426d2 1768 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1769 return 0;
1770
23297044 1771 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1772 params->spr.bytes_per_pixel,
801bcfff 1773 mem_value);
23297044 1774 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1775 params->pipe_htotal,
c35426d2
VS		 1776 params->spr.horiz_pixels,
1777 params->spr.bytes_per_pixel,
801bcfff
PZ		 1778 mem_value);
1779 return min(method1, method2);
1780}
1781
37126462
VS		 1782/*
1783 * For both WM_PIPE and WM_LP.
1784 * mem_value must be in 0.1us units.
1785 */
820c1980 1786static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1787 uint32_t mem_value)
1788{
c35426d2 1789 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1790 return 0;
1791
23297044 1792 return ilk_wm_method2(params->pixel_rate,
801bcfff 1793 params->pipe_htotal,
c35426d2
VS		 1794 params->cur.horiz_pixels,
1795 params->cur.bytes_per_pixel,
801bcfff
PZ		 1796 mem_value);
1797}
1798
cca32e9a 1799/* Only for WM_LP. */
820c1980 1800static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1801 uint32_t pri_val)
cca32e9a 1802{
c35426d2 1803 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1804 return 0;
1805
23297044 1806 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1807 params->pri.horiz_pixels,
1808 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1809}
1810
158ae64f
VS		 1811static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1812{
416f4727
VS		 1813 if (INTEL_INFO(dev)->gen >= 8)
1814 return 3072;
1815 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1816 return 768;
1817 else
1818 return 512;
1819}
1820
1821/* Calculate the maximum primary/sprite plane watermark */
1822static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1823 int level,
240264f4 1824 const struct intel_wm_config *config,
158ae64f
VS		 1825 enum intel_ddb_partitioning ddb_partitioning,
1826 bool is_sprite)
1827{
1828 unsigned int fifo_size = ilk_display_fifo_size(dev);
1829 unsigned int max;
1830
1831 /* if sprites aren't enabled, sprites get nothing */
240264f4 1832 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1833 return 0;
1834
1835 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1836 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1837 fifo_size /= INTEL_INFO(dev)->num_pipes;
1838
1839 /*
1840 * For some reason the non self refresh
1841 * FIFO size is only half of the self
1842 * refresh FIFO size on ILK/SNB.
1843 */
1844 if (INTEL_INFO(dev)->gen <= 6)
1845 fifo_size /= 2;
1846 }
1847
240264f4 1848 if (config->sprites_enabled) {
158ae64f
VS		 1849 /* level 0 is always calculated with 1:1 split */
1850 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1851 if (is_sprite)
1852 fifo_size *= 5;
1853 fifo_size /= 6;
1854 } else {
1855 fifo_size /= 2;
1856 }
1857 }
1858
1859 /* clamp to max that the registers can hold */
416f4727
VS		 1860 if (INTEL_INFO(dev)->gen >= 8)
1861 max = level == 0 ? 255 : 2047;
1862 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1863 /* IVB/HSW primary/sprite plane watermarks */
1864 max = level == 0 ? 127 : 1023;
1865 else if (!is_sprite)
1866 /* ILK/SNB primary plane watermarks */
1867 max = level == 0 ? 127 : 511;
1868 else
1869 /* ILK/SNB sprite plane watermarks */
1870 max = level == 0 ? 63 : 255;
1871
1872 return min(fifo_size, max);
1873}
1874
1875/* Calculate the maximum cursor plane watermark */
1876static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1877 int level,
1878 const struct intel_wm_config *config)
158ae64f
VS		 1879{
1880 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1881 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1882 return 64;
1883
1884 /* otherwise just report max that registers can hold */
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891/* Calculate the maximum FBC watermark */
d34ff9c6 1892static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
158ae64f
VS		 1893{
1894 /* max that registers can hold */
416f4727
VS		 1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
158ae64f
VS		 1899}
1900
d34ff9c6 1901static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1902 int level,
1903 const struct intel_wm_config *config,
1904 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1905 struct ilk_wm_maximums *max)
158ae64f 1906{
240264f4
VS		 1907 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1908 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1909 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 1910 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 1911}
1912
d9395655 1913static bool ilk_validate_wm_level(int level,
820c1980 1914 const struct ilk_wm_maximums *max,
d9395655 1915 struct intel_wm_level *result)
a9786a11
VS		 1916{
1917 bool ret;
1918
1919 /* already determined to be invalid? */
1920 if (!result->enable)
1921 return false;
1922
1923 result->enable = result->pri_val <= max->pri &&
1924 result->spr_val <= max->spr &&
1925 result->cur_val <= max->cur;
1926
1927 ret = result->enable;
1928
1929 /*
1930 * HACK until we can pre-compute everything,
1931 * and thus fail gracefully if LP0 watermarks
1932 * are exceeded...
1933 */
1934 if (level == 0 && !result->enable) {
1935 if (result->pri_val > max->pri)
1936 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1937 level, result->pri_val, max->pri);
1938 if (result->spr_val > max->spr)
1939 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1940 level, result->spr_val, max->spr);
1941 if (result->cur_val > max->cur)
1942 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1943 level, result->cur_val, max->cur);
1944
1945 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1946 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1947 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1948 result->enable = true;
1949 }
1950
a9786a11
VS		 1951 return ret;
1952}
1953
d34ff9c6 1954static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1955 int level,
820c1980 1956 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1957 struct intel_wm_level *result)
6f5ddd17
VS		 1958{
1959 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1960 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1961 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1962
1963 /* WM1+ latency values stored in 0.5us units */
1964 if (level > 0) {
1965 pri_latency *= 5;
1966 spr_latency *= 5;
1967 cur_latency *= 5;
1968 }
1969
1970 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1971 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1972 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1973 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1974 result->enable = true;
1975}
1976
801bcfff
PZ		 1977static uint32_t
1978hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1979{
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 1982 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 1983 u32 linetime, ips_linetime;
1f8eeabf 1984
801bcfff
PZ		 1985 if (!intel_crtc_active(crtc))
1986 return 0;
1011d8c4 1987
1f8eeabf
ED		 1988 /* The WM are computed with base on how long it takes to fill a single
1989 * row at the given clock rate, multiplied by 8.
1990 * */
fec8cba3
JB		 1991 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1992 mode->crtc_clock);
1993 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1994 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1995
801bcfff
PZ		 1996 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1997 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1998}
1999
12b134df
VS		 2000static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2001{
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003
a42a5719 2004 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2005 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2006
2007 wm[0] = (sskpd >> 56) & 0xFF;
2008 if (wm[0] == 0)
2009 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2010 wm[1] = (sskpd >> 4) & 0xFF;
2011 wm[2] = (sskpd >> 12) & 0xFF;
2012 wm[3] = (sskpd >> 20) & 0x1FF;
2013 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2014 } else if (INTEL_INFO(dev)->gen >= 6) {
2015 uint32_t sskpd = I915_READ(MCH_SSKPD);
2016
2017 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2018 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2019 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2020 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2021 } else if (INTEL_INFO(dev)->gen >= 5) {
2022 uint32_t mltr = I915_READ(MLTR_ILK);
2023
2024 /* ILK primary LP0 latency is 700 ns */
2025 wm[0] = 7;
2026 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2027 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2028 }
2029}
2030
53615a5e
VS		 2031static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032{
2033 /* ILK sprite LP0 latency is 1300 ns */
2034 if (INTEL_INFO(dev)->gen == 5)
2035 wm[0] = 13;
2036}
2037
2038static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2039{
2040 /* ILK cursor LP0 latency is 1300 ns */
2041 if (INTEL_INFO(dev)->gen == 5)
2042 wm[0] = 13;
2043
2044 /* WaDoubleCursorLP3Latency:ivb */
2045 if (IS_IVYBRIDGE(dev))
2046 wm[3] *= 2;
2047}
2048
ad0d6dc4 2049static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2050{
26ec971e 2051 /* how many WM levels are we expecting */
a42a5719 2052 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2053 return 4;
26ec971e 2054 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2055 return 3;
26ec971e 2056 else
ad0d6dc4
VS		 2057 return 2;
2058}
2059
2060static void intel_print_wm_latency(struct drm_device *dev,
2061 const char *name,
2062 const uint16_t wm[5])
2063{
2064 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2065
2066 for (level = 0; level <= max_level; level++) {
2067 unsigned int latency = wm[level];
2068
2069 if (latency == 0) {
2070 DRM_ERROR("%s WM%d latency not provided\n",
2071 name, level);
2072 continue;
2073 }
2074
2075 /* WM1+ latency values in 0.5us units */
2076 if (level > 0)
2077 latency *= 5;
2078
2079 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2080 name, level, wm[level],
2081 latency / 10, latency % 10);
2082 }
2083}
2084
53615a5e
VS		 2085static void intel_setup_wm_latency(struct drm_device *dev)
2086{
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088
2089 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2090
2091 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2092 sizeof(dev_priv->wm.pri_latency));
2093 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2094 sizeof(dev_priv->wm.pri_latency));
2095
2096 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2097 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2098
2099 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2100 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2101 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2102}
2103
820c1980
ID		 2104static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2105 struct ilk_pipe_wm_parameters *p,
a485bfb8 2106 struct intel_wm_config *config)
1011d8c4 2107{
7c4a395f
VS		 2108 struct drm_device *dev = crtc->dev;
2109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2110 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2111 struct drm_plane *plane;
1011d8c4 2112
7c4a395f
VS		 2113 p->active = intel_crtc_active(crtc);
2114 if (p->active) {
576b259e 2115 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
3658729a 2116 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2117 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2118 p->cur.bytes_per_pixel = 4;
37327abd 2119 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2120 p->cur.horiz_pixels = 64;
2121 /* TODO: for now, assume primary and cursor planes are always enabled. */
2122 p->pri.enabled = true;
2123 p->cur.enabled = true;
801bcfff
PZ		 2124 }
2125
7c4a395f 2126 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2127 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2128
801bcfff
PZ		 2129 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2130 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2131
7c4a395f
VS		 2132 if (intel_plane->pipe == pipe)
2133 p->spr = intel_plane->wm;
cca32e9a 2134
a485bfb8
VS		 2135 config->sprites_enabled |= intel_plane->wm.enabled;
2136 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2137 }
801bcfff
PZ		 2138}
2139
0b2ae6d7
VS		 2140/* Compute new watermarks for the pipe */
2141static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2142 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2143 struct intel_pipe_wm *pipe_wm)
2144{
2145 struct drm_device *dev = crtc->dev;
d34ff9c6 2146 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2147 int level, max_level = ilk_wm_max_level(dev);
2148 /* LP0 watermark maximums depend on this pipe alone */
2149 struct intel_wm_config config = {
2150 .num_pipes_active = 1,
2151 .sprites_enabled = params->spr.enabled,
2152 .sprites_scaled = params->spr.scaled,
2153 };
820c1980 2154 struct ilk_wm_maximums max;
0b2ae6d7 2155
0b2ae6d7 2156 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2157 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2158
7b39a0b7
VS		 2159 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2160 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2161 max_level = 1;
2162
2163 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2164 if (params->spr.scaled)
2165 max_level = 0;
2166
0b2ae6d7
VS		 2167 for (level = 0; level <= max_level; level++)
2168 ilk_compute_wm_level(dev_priv, level, params,
2169 &pipe_wm->wm[level]);
2170
a42a5719 2171 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2172 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2173
2174 /* At least LP0 must be valid */
d9395655 2175 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2176}
2177
2178/*
2179 * Merge the watermarks from all active pipes for a specific level.
2180 */
2181static void ilk_merge_wm_level(struct drm_device *dev,
2182 int level,
2183 struct intel_wm_level *ret_wm)
2184{
2185 const struct intel_crtc *intel_crtc;
2186
2187 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2188 const struct intel_wm_level *wm =
2189 &intel_crtc->wm.active.wm[level];
2190
2191 if (!wm->enable)
2192 return;
2193
2194 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2195 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2196 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2197 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2198 }
2199
2200 ret_wm->enable = true;
2201}
2202
2203/*
2204 * Merge all low power watermarks for all active pipes.
2205 */
2206static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2207 const struct intel_wm_config *config,
820c1980 2208 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2209 struct intel_pipe_wm *merged)
2210{
2211 int level, max_level = ilk_wm_max_level(dev);
2212
0ba22e26
VS		 2213 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2214 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2215 config->num_pipes_active > 1)
2216 return;
2217
6c8b6c28
VS		 2218 /* ILK: FBC WM must be disabled always */
2219 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2220
2221 /* merge each WM1+ level */
2222 for (level = 1; level <= max_level; level++) {
2223 struct intel_wm_level *wm = &merged->wm[level];
2224
2225 ilk_merge_wm_level(dev, level, wm);
2226
d9395655 2227 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2228 break;
2229
2230 /*
2231 * The spec says it is preferred to disable
2232 * FBC WMs instead of disabling a WM level.
2233 */
2234 if (wm->fbc_val > max->fbc) {
2235 merged->fbc_wm_enabled = false;
2236 wm->fbc_val = 0;
2237 }
2238 }
6c8b6c28
VS		 2239
2240 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2241 /*
2242 * FIXME this is racy. FBC might get enabled later.
2243 * What we should check here is whether FBC can be
2244 * enabled sometime later.
2245 */
2246 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2247 for (level = 2; level <= max_level; level++) {
2248 struct intel_wm_level *wm = &merged->wm[level];
2249
2250 wm->enable = false;
2251 }
2252 }
0b2ae6d7
VS		 2253}
2254
b380ca3c
VS		 2255static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2256{
2257 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2258 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2259}
2260
a68d68ee
VS		 2261/* The value we need to program into the WM_LPx latency field */
2262static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2263{
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265
a42a5719 2266 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2267 return 2 * level;
2268 else
2269 return dev_priv->wm.pri_latency[level];
2270}
2271
820c1980 2272static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2273 const struct intel_pipe_wm *merged,
609cedef 2274 enum intel_ddb_partitioning partitioning,
820c1980 2275 struct ilk_wm_values *results)
801bcfff 2276{
0b2ae6d7
VS		 2277 struct intel_crtc *intel_crtc;
2278 int level, wm_lp;
cca32e9a 2279
0362c781 2280 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2281 results->partitioning = partitioning;
cca32e9a 2282
0b2ae6d7 2283 /* LP1+ register values */
cca32e9a 2284 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2285 const struct intel_wm_level *r;
801bcfff 2286
b380ca3c 2287 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2288
0362c781 2289 r = &merged->wm[level];
0b2ae6d7 2290 if (!r->enable)
cca32e9a
PZ		 2291 break;
2292
416f4727 2293 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2294 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2295 (r->pri_val << WM1_LP_SR_SHIFT) |
2296 r->cur_val;
2297
2298 if (INTEL_INFO(dev)->gen >= 8)
2299 results->wm_lp[wm_lp - 1] |=
2300 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2301 else
2302 results->wm_lp[wm_lp - 1] |=
2303 r->fbc_val << WM1_LP_FBC_SHIFT;
2304
6cef2b8a
VS		 2305 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2306 WARN_ON(wm_lp != 1);
2307 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2308 } else
2309 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2310 }
801bcfff 2311
0b2ae6d7
VS		 2312 /* LP0 register values */
2313 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2314 enum pipe pipe = intel_crtc->pipe;
2315 const struct intel_wm_level *r =
2316 &intel_crtc->wm.active.wm[0];
2317
2318 if (WARN_ON(!r->enable))
2319 continue;
2320
2321 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2322
0b2ae6d7
VS		 2323 results->wm_pipe[pipe] =
2324 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2325 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2326 r->cur_val;
801bcfff
PZ		 2327 }
2328}
2329
861f3389
PZ		 2330/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2331 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2332static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2333 struct intel_pipe_wm *r1,
2334 struct intel_pipe_wm *r2)
861f3389 2335{
198a1e9b
VS		 2336 int level, max_level = ilk_wm_max_level(dev);
2337 int level1 = 0, level2 = 0;
861f3389 2338
198a1e9b
VS		 2339 for (level = 1; level <= max_level; level++) {
2340 if (r1->wm[level].enable)
2341 level1 = level;
2342 if (r2->wm[level].enable)
2343 level2 = level;
861f3389
PZ		 2344 }
2345
198a1e9b
VS		 2346 if (level1 == level2) {
2347 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2348 return r2;
2349 else
2350 return r1;
198a1e9b 2351 } else if (level1 > level2) {
861f3389
PZ		 2352 return r1;
2353 } else {
2354 return r2;
2355 }
2356}
2357
49a687c4
VS		 2358/* dirty bits used to track which watermarks need changes */
2359#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2360#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2361#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2362#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2363#define WM_DIRTY_FBC (1 << 24)
2364#define WM_DIRTY_DDB (1 << 25)
2365
2366static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2367 const struct ilk_wm_values *old,
2368 const struct ilk_wm_values *new)
49a687c4
VS		 2369{
2370 unsigned int dirty = 0;
2371 enum pipe pipe;
2372 int wm_lp;
2373
2374 for_each_pipe(pipe) {
2375 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2376 dirty |= WM_DIRTY_LINETIME(pipe);
2377 /* Must disable LP1+ watermarks too */
2378 dirty |= WM_DIRTY_LP_ALL;
2379 }
2380
2381 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2382 dirty |= WM_DIRTY_PIPE(pipe);
2383 /* Must disable LP1+ watermarks too */
2384 dirty |= WM_DIRTY_LP_ALL;
2385 }
2386 }
2387
2388 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2389 dirty |= WM_DIRTY_FBC;
2390 /* Must disable LP1+ watermarks too */
2391 dirty |= WM_DIRTY_LP_ALL;
2392 }
2393
2394 if (old->partitioning != new->partitioning) {
2395 dirty |= WM_DIRTY_DDB;
2396 /* Must disable LP1+ watermarks too */
2397 dirty |= WM_DIRTY_LP_ALL;
2398 }
2399
2400 /* LP1+ watermarks already deemed dirty, no need to continue */
2401 if (dirty & WM_DIRTY_LP_ALL)
2402 return dirty;
2403
2404 /* Find the lowest numbered LP1+ watermark in need of an update... */
2405 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2406 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2407 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2408 break;
2409 }
2410
2411 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2412 for (; wm_lp <= 3; wm_lp++)
2413 dirty |= WM_DIRTY_LP(wm_lp);
2414
2415 return dirty;
2416}
2417
8553c18e
VS		 2418static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2419 unsigned int dirty)
801bcfff 2420{
820c1980 2421 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2422 bool changed = false;
801bcfff 2423
facd619b
VS		 2424 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2425 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2426 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2427 changed = true;
facd619b
VS		 2428 }
2429 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2430 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2431 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2432 changed = true;
facd619b
VS		 2433 }
2434 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2435 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2436 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2437 changed = true;
facd619b 2438 }
801bcfff 2439
facd619b
VS		 2440 /*
2441 * Don't touch WM1S_LP_EN here.
2442 * Doing so could cause underruns.
2443 */
6cef2b8a 2444
8553c18e
VS		 2445 return changed;
2446}
2447
2448/*
2449 * The spec says we shouldn't write when we don't need, because every write
2450 * causes WMs to be re-evaluated, expending some power.
2451 */
820c1980
ID		 2452static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2453 struct ilk_wm_values *results)
8553c18e
VS		 2454{
2455 struct drm_device *dev = dev_priv->dev;
820c1980 2456 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2457 unsigned int dirty;
2458 uint32_t val;
2459
2460 dirty = ilk_compute_wm_dirty(dev, previous, results);
2461 if (!dirty)
2462 return;
2463
2464 _ilk_disable_lp_wm(dev_priv, dirty);
2465
49a687c4 2466 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2467 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2468 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2469 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2470 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2471 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2472
49a687c4 2473 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2474 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2475 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2476 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2477 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2478 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2479
49a687c4 2480 if (dirty & WM_DIRTY_DDB) {
a42a5719 2481 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2482 val = I915_READ(WM_MISC);
2483 if (results->partitioning == INTEL_DDB_PART_1_2)
2484 val &= ~WM_MISC_DATA_PARTITION_5_6;
2485 else
2486 val |= WM_MISC_DATA_PARTITION_5_6;
2487 I915_WRITE(WM_MISC, val);
2488 } else {
2489 val = I915_READ(DISP_ARB_CTL2);
2490 if (results->partitioning == INTEL_DDB_PART_1_2)
2491 val &= ~DISP_DATA_PARTITION_5_6;
2492 else
2493 val |= DISP_DATA_PARTITION_5_6;
2494 I915_WRITE(DISP_ARB_CTL2, val);
2495 }
1011d8c4
PZ		 2496 }
2497
49a687c4 2498 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2499 val = I915_READ(DISP_ARB_CTL);
2500 if (results->enable_fbc_wm)
2501 val &= ~DISP_FBC_WM_DIS;
2502 else
2503 val |= DISP_FBC_WM_DIS;
2504 I915_WRITE(DISP_ARB_CTL, val);
2505 }
2506
954911eb
ID		 2507 if (dirty & WM_DIRTY_LP(1) &&
2508 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2509 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2510
2511 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2512 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2513 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2515 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2516 }
801bcfff 2517
facd619b 2518 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2519 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2520 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2521 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2522 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2523 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2524
2525 dev_priv->wm.hw = *results;
801bcfff
PZ		 2526}
2527
8553c18e
VS		 2528static bool ilk_disable_lp_wm(struct drm_device *dev)
2529{
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531
2532 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2533}
2534
820c1980 2535static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2536{
7c4a395f 2537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2538 struct drm_device *dev = crtc->dev;
801bcfff 2539 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2540 struct ilk_wm_maximums max;
2541 struct ilk_pipe_wm_parameters params = {};
2542 struct ilk_wm_values results = {};
77c122bc 2543 enum intel_ddb_partitioning partitioning;
7c4a395f 2544 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2545 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2546 struct intel_wm_config config = {};
7c4a395f 2547
820c1980 2548 ilk_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2549
2550 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2551
2552 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2553 return;
861f3389 2554
7c4a395f 2555 intel_crtc->wm.active = pipe_wm;
861f3389 2556
34982fe1 2557 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2558 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2559
2560 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2561 if (INTEL_INFO(dev)->gen >= 7 &&
2562 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2563 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2564 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2565
820c1980 2566 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2567 } else {
198a1e9b 2568 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2569 }
2570
198a1e9b 2571 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2572 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2573
820c1980 2574 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2575
820c1980 2576 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2577}
2578
820c1980 2579static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2580 struct drm_crtc *crtc,
526682e9 2581 uint32_t sprite_width, int pixel_size,
bdd57d03 2582 bool enabled, bool scaled)
526682e9 2583{
8553c18e 2584 struct drm_device *dev = plane->dev;
adf3d35e 2585 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2586
adf3d35e
VS		 2587 intel_plane->wm.enabled = enabled;
2588 intel_plane->wm.scaled = scaled;
2589 intel_plane->wm.horiz_pixels = sprite_width;
2590 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2591
8553c18e
VS		 2592 /*
2593 * IVB workaround: must disable low power watermarks for at least
2594 * one frame before enabling scaling. LP watermarks can be re-enabled
2595 * when scaling is disabled.
2596 *
2597 * WaCxSRDisabledForSpriteScaling:ivb
2598 */
2599 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2600 intel_wait_for_vblank(dev, intel_plane->pipe);
2601
820c1980 2602 ilk_update_wm(crtc);
526682e9
PZ		 2603}
2604
243e6a44
VS		 2605static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2606{
2607 struct drm_device *dev = crtc->dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2609 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2611 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2612 enum pipe pipe = intel_crtc->pipe;
2613 static const unsigned int wm0_pipe_reg[] = {
2614 [PIPE_A] = WM0_PIPEA_ILK,
2615 [PIPE_B] = WM0_PIPEB_ILK,
2616 [PIPE_C] = WM0_PIPEC_IVB,
2617 };
2618
2619 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2620 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2621 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44
VS		 2622
2623 if (intel_crtc_active(crtc)) {
2624 u32 tmp = hw->wm_pipe[pipe];
2625
2626 /*
2627 * For active pipes LP0 watermark is marked as
2628 * enabled, and LP1+ watermaks as disabled since
2629 * we can't really reverse compute them in case
2630 * multiple pipes are active.
2631 */
2632 active->wm[0].enable = true;
2633 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2634 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2635 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2636 active->linetime = hw->wm_linetime[pipe];
2637 } else {
2638 int level, max_level = ilk_wm_max_level(dev);
2639
2640 /*
2641 * For inactive pipes, all watermark levels
2642 * should be marked as enabled but zeroed,
2643 * which is what we'd compute them to.
2644 */
2645 for (level = 0; level <= max_level; level++)
2646 active->wm[level].enable = true;
2647 }
2648}
2649
2650void ilk_wm_get_hw_state(struct drm_device *dev)
2651{
2652 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2653 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2654 struct drm_crtc *crtc;
2655
2656 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2657 ilk_pipe_wm_get_hw_state(crtc);
2658
2659 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2660 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2661 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2662
2663 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2664 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2665 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2666
a42a5719 2667 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2668 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2669 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2670 else if (IS_IVYBRIDGE(dev))
2671 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2672 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2673
2674 hw->enable_fbc_wm =
2675 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2676}
2677
b445e3b0
ED		 2678/**
2679 * intel_update_watermarks - update FIFO watermark values based on current modes
2680 *
2681 * Calculate watermark values for the various WM regs based on current mode
2682 * and plane configuration.
2683 *
2684 * There are several cases to deal with here:
2685 * - normal (i.e. non-self-refresh)
2686 * - self-refresh (SR) mode
2687 * - lines are large relative to FIFO size (buffer can hold up to 2)
2688 * - lines are small relative to FIFO size (buffer can hold more than 2
2689 * lines), so need to account for TLB latency
2690 *
2691 * The normal calculation is:
2692 * watermark = dotclock * bytes per pixel * latency
2693 * where latency is platform & configuration dependent (we assume pessimal
2694 * values here).
2695 *
2696 * The SR calculation is:
2697 * watermark = (trunc(latency/line time)+1) * surface width *
2698 * bytes per pixel
2699 * where
2700 * line time = htotal / dotclock
2701 * surface width = hdisplay for normal plane and 64 for cursor
2702 * and latency is assumed to be high, as above.
2703 *
2704 * The final value programmed to the register should always be rounded up,
2705 * and include an extra 2 entries to account for clock crossings.
2706 *
2707 * We don't use the sprite, so we can ignore that. And on Crestline we have
2708 * to set the non-SR watermarks to 8.
2709 */
46ba614c 2710void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2711{
46ba614c 2712 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2713
2714 if (dev_priv->display.update_wm)
46ba614c 2715 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2716}
2717
adf3d35e
VS		 2718void intel_update_sprite_watermarks(struct drm_plane *plane,
2719 struct drm_crtc *crtc,
4c4ff43a 2720 uint32_t sprite_width, int pixel_size,
39db4a4d 2721 bool enabled, bool scaled)
b445e3b0 2722{
adf3d35e 2723 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2724
2725 if (dev_priv->display.update_sprite_wm)
adf3d35e 2726 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2727 pixel_size, enabled, scaled);
b445e3b0
ED		 2728}
2729
2b4e57bd
ED		 2730static struct drm_i915_gem_object *
2731intel_alloc_context_page(struct drm_device *dev)
2732{
2733 struct drm_i915_gem_object *ctx;
2734 int ret;
2735
2736 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2737
2738 ctx = i915_gem_alloc_object(dev, 4096);
2739 if (!ctx) {
2740 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2741 return NULL;
2742 }
2743
c37e2204 2744 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2745 if (ret) {
2746 DRM_ERROR("failed to pin power context: %d\n", ret);
2747 goto err_unref;
2748 }
2749
2750 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2751 if (ret) {
2752 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2753 goto err_unpin;
2754 }
2755
2756 return ctx;
2757
2758err_unpin:
d7f46fc4 2759 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2760err_unref:
2761 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2762 return NULL;
2763}
2764
9270388e
DV		 2765/**
2766 * Lock protecting IPS related data structures
9270388e
DV		 2767 */
2768DEFINE_SPINLOCK(mchdev_lock);
2769
2770/* Global for IPS driver to get at the current i915 device. Protected by
2771 * mchdev_lock. */
2772static struct drm_i915_private *i915_mch_dev;
2773
2b4e57bd
ED		 2774bool ironlake_set_drps(struct drm_device *dev, u8 val)
2775{
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 u16 rgvswctl;
2778
9270388e
DV		 2779 assert_spin_locked(&mchdev_lock);
2780
2b4e57bd
ED		 2781 rgvswctl = I915_READ16(MEMSWCTL);
2782 if (rgvswctl & MEMCTL_CMD_STS) {
2783 DRM_DEBUG("gpu busy, RCS change rejected\n");
2784 return false; /* still busy with another command */
2785 }
2786
2787 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2788 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2789 I915_WRITE16(MEMSWCTL, rgvswctl);
2790 POSTING_READ16(MEMSWCTL);
2791
2792 rgvswctl |= MEMCTL_CMD_STS;
2793 I915_WRITE16(MEMSWCTL, rgvswctl);
2794
2795 return true;
2796}
2797
8090c6b9 2798static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2799{
2800 struct drm_i915_private *dev_priv = dev->dev_private;
2801 u32 rgvmodectl = I915_READ(MEMMODECTL);
2802 u8 fmax, fmin, fstart, vstart;
2803
9270388e
DV		 2804 spin_lock_irq(&mchdev_lock);
2805
2b4e57bd
ED		 2806 /* Enable temp reporting */
2807 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2808 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2809
2810 /* 100ms RC evaluation intervals */
2811 I915_WRITE(RCUPEI, 100000);
2812 I915_WRITE(RCDNEI, 100000);
2813
2814 /* Set max/min thresholds to 90ms and 80ms respectively */
2815 I915_WRITE(RCBMAXAVG, 90000);
2816 I915_WRITE(RCBMINAVG, 80000);
2817
2818 I915_WRITE(MEMIHYST, 1);
2819
2820 /* Set up min, max, and cur for interrupt handling */
2821 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2822 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2823 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2824 MEMMODE_FSTART_SHIFT;
2825
2826 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2827 PXVFREQ_PX_SHIFT;
2828
20e4d407
DV		 2829 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2830 dev_priv->ips.fstart = fstart;
2b4e57bd 2831
20e4d407
DV		 2832 dev_priv->ips.max_delay = fstart;
2833 dev_priv->ips.min_delay = fmin;
2834 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2835
2836 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2837 fmax, fmin, fstart);
2838
2839 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2840
2841 /*
2842 * Interrupts will be enabled in ironlake_irq_postinstall
2843 */
2844
2845 I915_WRITE(VIDSTART, vstart);
2846 POSTING_READ(VIDSTART);
2847
2848 rgvmodectl |= MEMMODE_SWMODE_EN;
2849 I915_WRITE(MEMMODECTL, rgvmodectl);
2850
9270388e 2851 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2852 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2853 mdelay(1);
2b4e57bd
ED		 2854
2855 ironlake_set_drps(dev, fstart);
2856
20e4d407 2857 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2858 I915_READ(0x112e0);
20e4d407
DV		 2859 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2860 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2861 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2862
2863 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2864}
2865
8090c6b9 2866static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2867{
2868 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2869 u16 rgvswctl;
2870
2871 spin_lock_irq(&mchdev_lock);
2872
2873 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2874
2875 /* Ack interrupts, disable EFC interrupt */
2876 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2877 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2878 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2879 I915_WRITE(DEIIR, DE_PCU_EVENT);
2880 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2881
2882 /* Go back to the starting frequency */
20e4d407 2883 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2884 mdelay(1);
2b4e57bd
ED		 2885 rgvswctl |= MEMCTL_CMD_STS;
2886 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2887 mdelay(1);
2b4e57bd 2888
9270388e 2889 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2890}
2891
acbe9475
DV		 2892/* There's a funny hw issue where the hw returns all 0 when reading from
2893 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2894 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2895 * all limits and the gpu stuck at whatever frequency it is at atm).
2896 */
6917c7b9 2897static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2898{
7b9e0ae6 2899 u32 limits;
2b4e57bd 2900
20b46e59
DV		 2901 /* Only set the down limit when we've reached the lowest level to avoid
2902 * getting more interrupts, otherwise leave this clear. This prevents a
2903 * race in the hw when coming out of rc6: There's a tiny window where
2904 * the hw runs at the minimal clock before selecting the desired
2905 * frequency, if the down threshold expires in that window we will not
2906 * receive a down interrupt. */
6917c7b9
CW		 2907 limits = dev_priv->rps.max_delay << 24;
2908 if (val <= dev_priv->rps.min_delay)
c6a828d3 2909 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2910
2911 return limits;
2912}
2913
dd75fdc8
CW		 2914static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2915{
2916 int new_power;
2917
2918 new_power = dev_priv->rps.power;
2919 switch (dev_priv->rps.power) {
2920 case LOW_POWER:
2921 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2922 new_power = BETWEEN;
2923 break;
2924
2925 case BETWEEN:
2926 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2927 new_power = LOW_POWER;
2928 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2929 new_power = HIGH_POWER;
2930 break;
2931
2932 case HIGH_POWER:
2933 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2934 new_power = BETWEEN;
2935 break;
2936 }
2937 /* Max/min bins are special */
2938 if (val == dev_priv->rps.min_delay)
2939 new_power = LOW_POWER;
2940 if (val == dev_priv->rps.max_delay)
2941 new_power = HIGH_POWER;
2942 if (new_power == dev_priv->rps.power)
2943 return;
2944
2945 /* Note the units here are not exactly 1us, but 1280ns. */
2946 switch (new_power) {
2947 case LOW_POWER:
2948 /* Upclock if more than 95% busy over 16ms */
2949 I915_WRITE(GEN6_RP_UP_EI, 12500);
2950 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2951
2952 /* Downclock if less than 85% busy over 32ms */
2953 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2954 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2955
2956 I915_WRITE(GEN6_RP_CONTROL,
2957 GEN6_RP_MEDIA_TURBO |
2958 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2959 GEN6_RP_MEDIA_IS_GFX |
2960 GEN6_RP_ENABLE |
2961 GEN6_RP_UP_BUSY_AVG |
2962 GEN6_RP_DOWN_IDLE_AVG);
2963 break;
2964
2965 case BETWEEN:
2966 /* Upclock if more than 90% busy over 13ms */
2967 I915_WRITE(GEN6_RP_UP_EI, 10250);
2968 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2969
2970 /* Downclock if less than 75% busy over 32ms */
2971 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2972 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2973
2974 I915_WRITE(GEN6_RP_CONTROL,
2975 GEN6_RP_MEDIA_TURBO |
2976 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2977 GEN6_RP_MEDIA_IS_GFX |
2978 GEN6_RP_ENABLE |
2979 GEN6_RP_UP_BUSY_AVG |
2980 GEN6_RP_DOWN_IDLE_AVG);
2981 break;
2982
2983 case HIGH_POWER:
2984 /* Upclock if more than 85% busy over 10ms */
2985 I915_WRITE(GEN6_RP_UP_EI, 8000);
2986 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2987
2988 /* Downclock if less than 60% busy over 32ms */
2989 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2990 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
2991
2992 I915_WRITE(GEN6_RP_CONTROL,
2993 GEN6_RP_MEDIA_TURBO |
2994 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2995 GEN6_RP_MEDIA_IS_GFX |
2996 GEN6_RP_ENABLE |
2997 GEN6_RP_UP_BUSY_AVG |
2998 GEN6_RP_DOWN_IDLE_AVG);
2999 break;
3000 }
3001
3002 dev_priv->rps.power = new_power;
3003 dev_priv->rps.last_adj = 0;
3004}
3005
20b46e59
DV		 3006void gen6_set_rps(struct drm_device *dev, u8 val)
3007{
3008 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3009
4fc688ce 3010 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3011 WARN_ON(val > dev_priv->rps.max_delay);
3012 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3013
c6a828d3 3014 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3015 return;
3016
dd75fdc8
CW		 3017 gen6_set_rps_thresholds(dev_priv, val);
3018
92bd1bf0
RV		 3019 if (IS_HASWELL(dev))
3020 I915_WRITE(GEN6_RPNSWREQ,
3021 HSW_FREQUENCY(val));
3022 else
3023 I915_WRITE(GEN6_RPNSWREQ,
3024 GEN6_FREQUENCY(val) |
3025 GEN6_OFFSET(0) |
3026 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3027
3028 /* Make sure we continue to get interrupts
3029 * until we hit the minimum or maximum frequencies.
3030 */
6917c7b9
CW		 3031 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3032 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3033
d5570a72
BW		 3034 POSTING_READ(GEN6_RPNSWREQ);
3035
c6a828d3 3036 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3037
3038 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3039}
3040
76c3552f
D		 3041/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3042 *
3043 * * If Gfx is Idle, then
3044 * 1. Mask Turbo interrupts
3045 * 2. Bring up Gfx clock
3046 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3047 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3048 * 5. Unmask Turbo interrupts
3049*/
3050static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3051{
3052 /*
3053 * When we are idle. Drop to min voltage state.
3054 */
3055
3056 if (dev_priv->rps.cur_delay <= dev_priv->rps.min_delay)
3057 return;
3058
3059 /* Mask turbo interrupt so that they will not come in between */
3060 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3061
3062 /* Bring up the Gfx clock */
3063 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3064 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3065 VLV_GFX_CLK_FORCE_ON_BIT);
3066
3067 if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3068 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3069 DRM_ERROR("GFX_CLK_ON request timed out\n");
3070 return;
3071 }
3072
3073 dev_priv->rps.cur_delay = dev_priv->rps.min_delay;
3074
3075 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3076 dev_priv->rps.min_delay);
3077
3078 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3079 & GENFREQSTATUS) == 0, 5))
3080 DRM_ERROR("timed out waiting for Punit\n");
3081
3082 /* Release the Gfx clock */
3083 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3084 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3085 ~VLV_GFX_CLK_FORCE_ON_BIT);
3086
3087 /* Unmask Up interrupts */
3088 dev_priv->rps.rp_up_masked = true;
3089 gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD,
3090 dev_priv->rps.min_delay);
3091}
3092
b29c19b6
CW		 3093void gen6_rps_idle(struct drm_i915_private *dev_priv)
3094{
691bb717
DL		 3095 struct drm_device *dev = dev_priv->dev;
3096
b29c19b6 3097 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3098 if (dev_priv->rps.enabled) {
691bb717 3099 if (IS_VALLEYVIEW(dev))
76c3552f 3100 vlv_set_rps_idle(dev_priv);
c0951f0c
CW		 3101 else
3102 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3103 dev_priv->rps.last_adj = 0;
3104 }
b29c19b6
CW		 3105 mutex_unlock(&dev_priv->rps.hw_lock);
3106}
3107
3108void gen6_rps_boost(struct drm_i915_private *dev_priv)
3109{
691bb717
DL		 3110 struct drm_device *dev = dev_priv->dev;
3111
b29c19b6 3112 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3113 if (dev_priv->rps.enabled) {
691bb717 3114 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3115 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3116 else
3117 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3118 dev_priv->rps.last_adj = 0;
3119 }
b29c19b6
CW		 3120 mutex_unlock(&dev_priv->rps.hw_lock);
3121}
3122
0a073b84
JB		 3123void valleyview_set_rps(struct drm_device *dev, u8 val)
3124{
3125 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3126
0a073b84
JB		 3127 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3128 WARN_ON(val > dev_priv->rps.max_delay);
3129 WARN_ON(val < dev_priv->rps.min_delay);
3130
73008b98 3131 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3132 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3133 dev_priv->rps.cur_delay,
2ec3815f 3134 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3135
3136 if (val == dev_priv->rps.cur_delay)
3137 return;
3138
ae99258f 3139 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3140
80814ae4 3141 dev_priv->rps.cur_delay = val;
0a073b84 3142
2ec3815f 3143 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3144}
3145
44fc7d5c 3146static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3147{
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149
2b4e57bd 3150 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3151 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3152 /* Complete PM interrupt masking here doesn't race with the rps work
3153 * item again unmasking PM interrupts because that is using a different
3154 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3155 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3156
59cdb63d 3157 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3158 dev_priv->rps.pm_iir = 0;
59cdb63d 3159 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3160
4848405c 3161 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3162}
3163
44fc7d5c 3164static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3165{
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167
3168 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3169 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3170
44fc7d5c
DV		 3171 gen6_disable_rps_interrupts(dev);
3172}
3173
3174static void valleyview_disable_rps(struct drm_device *dev)
3175{
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177
3178 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3179
44fc7d5c 3180 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3181
3182 if (dev_priv->vlv_pctx) {
3183 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3184 dev_priv->vlv_pctx = NULL;
3185 }
d20d4f0c
JB		 3186}
3187
dc39fff7
BW		 3188static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3189{
3190 if (IS_GEN6(dev))
3191 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3192
3193 if (IS_HASWELL(dev))
3194 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3195
3196 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3197 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3198 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3199 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3200}
3201
2b4e57bd
ED		 3202int intel_enable_rc6(const struct drm_device *dev)
3203{
eb4926e4
DL		 3204 /* No RC6 before Ironlake */
3205 if (INTEL_INFO(dev)->gen < 5)
3206 return 0;
3207
456470eb 3208 /* Respect the kernel parameter if it is set */
d330a953
JN		 3209 if (i915.enable_rc6 >= 0)
3210 return i915.enable_rc6;
2b4e57bd 3211
6567d748
CW		 3212 /* Disable RC6 on Ironlake */
3213 if (INTEL_INFO(dev)->gen == 5)
3214 return 0;
2b4e57bd 3215
dc39fff7 3216 if (IS_HASWELL(dev))
4a637c2c 3217 return INTEL_RC6_ENABLE;
2b4e57bd 3218
456470eb 3219 /* snb/ivb have more than one rc6 state. */
dc39fff7 3220 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3221 return INTEL_RC6_ENABLE;
456470eb 3222
2b4e57bd
ED		 3223 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3224}
3225
44fc7d5c
DV		 3226static void gen6_enable_rps_interrupts(struct drm_device *dev)
3227{
3228 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3229 u32 enabled_intrs;
44fc7d5c
DV		 3230
3231 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3232 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3233 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3234 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3235 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3236
fd547d25 3237 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3238 enabled_intrs = GEN6_PM_RPS_EVENTS;
3239
3240 /* IVB and SNB hard hangs on looping batchbuffer
3241 * if GEN6_PM_UP_EI_EXPIRED is masked.
3242 */
3243 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3244 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3245
3246 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3247}
3248
6edee7f3
BW		 3249static void gen8_enable_rps(struct drm_device *dev)
3250{
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 struct intel_ring_buffer *ring;
3253 uint32_t rc6_mask = 0, rp_state_cap;
3254 int unused;
3255
3256 /* 1a: Software RC state - RC0 */
3257 I915_WRITE(GEN6_RC_STATE, 0);
3258
3259 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3260 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3261 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3262
3263 /* 2a: Disable RC states. */
3264 I915_WRITE(GEN6_RC_CONTROL, 0);
3265
3266 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3267
3268 /* 2b: Program RC6 thresholds.*/
3269 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3270 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3271 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3272 for_each_ring(ring, dev_priv, unused)
3273 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3274 I915_WRITE(GEN6_RC_SLEEP, 0);
3275 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3276
3277 /* 3: Enable RC6 */
3278 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3279 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3280 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3281 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3282 GEN6_RC_CTL_EI_MODE(1) |
3283 rc6_mask);
3284
3285 /* 4 Program defaults and thresholds for RPS*/
3286 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3287 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3288 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3289 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3290
3291 /* Docs recommend 900MHz, and 300 MHz respectively */
3292 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3293 dev_priv->rps.max_delay << 24 |
3294 dev_priv->rps.min_delay << 16);
3295
3296 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3297 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3298 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3299 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3300
3301 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3302
3303 /* 5: Enable RPS */
3304 I915_WRITE(GEN6_RP_CONTROL,
3305 GEN6_RP_MEDIA_TURBO |
3306 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3307 GEN6_RP_MEDIA_IS_GFX |
3308 GEN6_RP_ENABLE |
3309 GEN6_RP_UP_BUSY_AVG |
3310 GEN6_RP_DOWN_IDLE_AVG);
3311
3312 /* 6: Ring frequency + overclocking (our driver does this later */
3313
3314 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3315
3316 gen6_enable_rps_interrupts(dev);
3317
c8d9a590 3318 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3319}
3320
79f5b2c7 3321static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3322{
79f5b2c7 3323 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3324 struct intel_ring_buffer *ring;
dd0a1aa1 3325 u32 rp_state_cap, hw_max, hw_min;
7b9e0ae6 3326 u32 gt_perf_status;
31643d54 3327 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3328 u32 gtfifodbg;
2b4e57bd 3329 int rc6_mode;
42c0526c 3330 int i, ret;
2b4e57bd 3331
4fc688ce 3332 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3333
2b4e57bd
ED		 3334 /* Here begins a magic sequence of register writes to enable
3335 * auto-downclocking.
3336 *
3337 * Perhaps there might be some value in exposing these to
3338 * userspace...
3339 */
3340 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3341
3342 /* Clear the DBG now so we don't confuse earlier errors */
3343 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3344 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3345 I915_WRITE(GTFIFODBG, gtfifodbg);
3346 }
3347
c8d9a590 3348 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3349
7b9e0ae6
CW		 3350 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3351 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3352
31c77388 3353 /* In units of 50MHz */
dd0a1aa1
JM		 3354 dev_priv->rps.hw_max = hw_max = rp_state_cap & 0xff;
3355 hw_min = (rp_state_cap >> 16) & 0xff;
dd75fdc8
CW		 3356 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3357 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3358 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3359 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3360
dd0a1aa1
JM		 3361 /* Preserve min/max settings in case of re-init */
3362 if (dev_priv->rps.max_delay == 0)
3363 dev_priv->rps.max_delay = hw_max;
3364
3365 if (dev_priv->rps.min_delay == 0)
3366 dev_priv->rps.min_delay = hw_min;
3367
2b4e57bd
ED		 3368 /* disable the counters and set deterministic thresholds */
3369 I915_WRITE(GEN6_RC_CONTROL, 0);
3370
3371 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3372 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3373 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3374 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3375 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3376
b4519513
CW		 3377 for_each_ring(ring, dev_priv, i)
3378 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3379
3380 I915_WRITE(GEN6_RC_SLEEP, 0);
3381 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3382 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3383 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3384 else
3385 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3386 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3387 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3388
5a7dc92a 3389 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3390 rc6_mode = intel_enable_rc6(dev_priv->dev);
3391 if (rc6_mode & INTEL_RC6_ENABLE)
3392 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3393
5a7dc92a
ED		 3394 /* We don't use those on Haswell */
3395 if (!IS_HASWELL(dev)) {
3396 if (rc6_mode & INTEL_RC6p_ENABLE)
3397 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3398
5a7dc92a
ED		 3399 if (rc6_mode & INTEL_RC6pp_ENABLE)
3400 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3401 }
2b4e57bd 3402
dc39fff7 3403 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3404
3405 I915_WRITE(GEN6_RC_CONTROL,
3406 rc6_mask |
3407 GEN6_RC_CTL_EI_MODE(1) |
3408 GEN6_RC_CTL_HW_ENABLE);
3409
dd75fdc8
CW		 3410 /* Power down if completely idle for over 50ms */
3411 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3412 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3413
42c0526c 3414 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3415 if (!ret) {
42c0526c
BW		 3416 pcu_mbox = 0;
3417 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3418 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3419 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3420 (dev_priv->rps.max_delay & 0xff) * 50,
3421 (pcu_mbox & 0xff) * 50);
31c77388 3422 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3423 }
3424 } else {
3425 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3426 }
3427
dd75fdc8
CW		 3428 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3429 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3430
44fc7d5c 3431 gen6_enable_rps_interrupts(dev);
2b4e57bd 3432
31643d54
BW		 3433 rc6vids = 0;
3434 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3435 if (IS_GEN6(dev) && ret) {
3436 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3437 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3438 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3439 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3440 rc6vids &= 0xffff00;
3441 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3442 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3443 if (ret)
3444 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3445 }
3446
c8d9a590 3447 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3448}
3449
c67a470b 3450void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3451{
79f5b2c7 3452 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3453 int min_freq = 15;
3ebecd07
CW		 3454 unsigned int gpu_freq;
3455 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3456 int scaling_factor = 180;
eda79642 3457 struct cpufreq_policy *policy;
2b4e57bd 3458
4fc688ce 3459 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3460
eda79642
BW		 3461 policy = cpufreq_cpu_get(0);
3462 if (policy) {
3463 max_ia_freq = policy->cpuinfo.max_freq;
3464 cpufreq_cpu_put(policy);
3465 } else {
3466 /*
3467 * Default to measured freq if none found, PCU will ensure we
3468 * don't go over
3469 */
2b4e57bd 3470 max_ia_freq = tsc_khz;
eda79642 3471 }
2b4e57bd
ED		 3472
3473 /* Convert from kHz to MHz */
3474 max_ia_freq /= 1000;
3475
153b4b95 3476 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3477 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3478 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3479
2b4e57bd
ED		 3480 /*
3481 * For each potential GPU frequency, load a ring frequency we'd like
3482 * to use for memory access. We do this by specifying the IA frequency
3483 * the PCU should use as a reference to determine the ring frequency.
3484 */
c6a828d3 3485 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3486 gpu_freq--) {
c6a828d3 3487 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3488 unsigned int ia_freq = 0, ring_freq = 0;
3489
46c764d4
BW		 3490 if (INTEL_INFO(dev)->gen >= 8) {
3491 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3492 ring_freq = max(min_ring_freq, gpu_freq);
3493 } else if (IS_HASWELL(dev)) {
f6aca45c 3494 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3495 ring_freq = max(min_ring_freq, ring_freq);
3496 /* leave ia_freq as the default, chosen by cpufreq */
3497 } else {
3498 /* On older processors, there is no separate ring
3499 * clock domain, so in order to boost the bandwidth
3500 * of the ring, we need to upclock the CPU (ia_freq).
3501 *
3502 * For GPU frequencies less than 750MHz,
3503 * just use the lowest ring freq.
3504 */
3505 if (gpu_freq < min_freq)
3506 ia_freq = 800;
3507 else
3508 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3509 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3510 }
2b4e57bd 3511
42c0526c
BW		 3512 sandybridge_pcode_write(dev_priv,
3513 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3514 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3515 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3516 gpu_freq);
2b4e57bd 3517 }
2b4e57bd
ED		 3518}
3519
0a073b84
JB		 3520int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3521{
3522 u32 val, rp0;
3523
64936258 3524 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3525
3526 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3527 /* Clamp to max */
3528 rp0 = min_t(u32, rp0, 0xea);
3529
3530 return rp0;
3531}
3532
3533static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3534{
3535 u32 val, rpe;
3536
64936258 3537 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3538 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3539 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3540 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3541
3542 return rpe;
3543}
3544
3545int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3546{
64936258 3547 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3548}
3549
c9cddffc
JB		 3550static void valleyview_setup_pctx(struct drm_device *dev)
3551{
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 struct drm_i915_gem_object *pctx;
3554 unsigned long pctx_paddr;
3555 u32 pcbr;
3556 int pctx_size = 24*1024;
3557
3558 pcbr = I915_READ(VLV_PCBR);
3559 if (pcbr) {
3560 /* BIOS set it up already, grab the pre-alloc'd space */
3561 int pcbr_offset;
3562
3563 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3564 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3565 pcbr_offset,
190d6cd5 3566 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3567 pctx_size);
3568 goto out;
3569 }
3570
3571 /*
3572 * From the Gunit register HAS:
3573 * The Gfx driver is expected to program this register and ensure
3574 * proper allocation within Gfx stolen memory. For example, this
3575 * register should be programmed such than the PCBR range does not
3576 * overlap with other ranges, such as the frame buffer, protected
3577 * memory, or any other relevant ranges.
3578 */
3579 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3580 if (!pctx) {
3581 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3582 return;
3583 }
3584
3585 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3586 I915_WRITE(VLV_PCBR, pctx_paddr);
3587
3588out:
3589 dev_priv->vlv_pctx = pctx;
3590}
3591
0a073b84
JB		 3592static void valleyview_enable_rps(struct drm_device *dev)
3593{
3594 struct drm_i915_private *dev_priv = dev->dev_private;
3595 struct intel_ring_buffer *ring;
dd0a1aa1 3596 u32 gtfifodbg, val, hw_max, hw_min, rc6_mode = 0;
0a073b84
JB		 3597 int i;
3598
3599 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3600
3601 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3602 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3603 gtfifodbg);
0a073b84
JB		 3604 I915_WRITE(GTFIFODBG, gtfifodbg);
3605 }
3606
c9cddffc
JB		 3607 valleyview_setup_pctx(dev);
3608
c8d9a590
D		 3609 /* If VLV, Forcewake all wells, else re-direct to regular path */
3610 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3611
3612 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3613 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3614 I915_WRITE(GEN6_RP_UP_EI, 66000);
3615 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3616
3617 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3618
3619 I915_WRITE(GEN6_RP_CONTROL,
3620 GEN6_RP_MEDIA_TURBO |
3621 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3622 GEN6_RP_MEDIA_IS_GFX |
3623 GEN6_RP_ENABLE |
3624 GEN6_RP_UP_BUSY_AVG |
3625 GEN6_RP_DOWN_IDLE_CONT);
3626
3627 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3628 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3629 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3630
3631 for_each_ring(ring, dev_priv, i)
3632 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3633
2f0aa304 3634 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3635
3636 /* allows RC6 residency counter to work */
49798eb2
JB		 3637 I915_WRITE(VLV_COUNTER_CONTROL,
3638 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3639 VLV_MEDIA_RC6_COUNT_EN |
3640 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3641 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3642 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3643
3644 intel_print_rc6_info(dev, rc6_mode);
3645
a2b23fe0 3646 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3647
64936258 3648 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3649
3650 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3651 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3652
0a073b84 3653 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 3654 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 3655 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3656 dev_priv->rps.cur_delay);
0a073b84 3657
dd0a1aa1 3658 dev_priv->rps.hw_max = hw_max = valleyview_rps_max_freq(dev_priv);
73008b98 3659 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
dd0a1aa1
JM		 3660 vlv_gpu_freq(dev_priv, hw_max),
3661 hw_max);
0a073b84 3662
73008b98
VS		 3663 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3664 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 3665 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3666 dev_priv->rps.rpe_delay);
0a073b84 3667
dd0a1aa1 3668 hw_min = valleyview_rps_min_freq(dev_priv);
73008b98 3669 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
dd0a1aa1
JM		 3670 vlv_gpu_freq(dev_priv, hw_min),
3671 hw_min);
3672
3673 /* Preserve min/max settings in case of re-init */
3674 if (dev_priv->rps.max_delay == 0)
3675 dev_priv->rps.max_delay = hw_max;
3676
3677 if (dev_priv->rps.min_delay == 0)
3678 dev_priv->rps.min_delay = hw_min;
0a073b84 3679
73008b98 3680 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 3681 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3682 dev_priv->rps.rpe_delay);
0a073b84 3683
73008b98 3684 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3685
27544369
D		 3686 dev_priv->rps.rp_up_masked = false;
3687 dev_priv->rps.rp_down_masked = false;
3688
44fc7d5c 3689 gen6_enable_rps_interrupts(dev);
0a073b84 3690
c8d9a590 3691 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3692}
3693
930ebb46 3694void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3695{
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697
3e373948 3698 if (dev_priv->ips.renderctx) {
d7f46fc4 3699 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 3700 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3701 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3702 }
3703
3e373948 3704 if (dev_priv->ips.pwrctx) {
d7f46fc4 3705 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 3706 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3707 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3708 }
3709}
3710
930ebb46 3711static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3712{
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714
3715 if (I915_READ(PWRCTXA)) {
3716 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3717 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3718 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3719 50);
3720
3721 I915_WRITE(PWRCTXA, 0);
3722 POSTING_READ(PWRCTXA);
3723
3724 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3725 POSTING_READ(RSTDBYCTL);
3726 }
2b4e57bd
ED		 3727}
3728
3729static int ironlake_setup_rc6(struct drm_device *dev)
3730{
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732
3e373948
DV		 3733 if (dev_priv->ips.renderctx == NULL)
3734 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3735 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3736 return -ENOMEM;
3737
3e373948
DV		 3738 if (dev_priv->ips.pwrctx == NULL)
3739 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3740 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3741 ironlake_teardown_rc6(dev);
3742 return -ENOMEM;
3743 }
3744
3745 return 0;
3746}
3747
930ebb46 3748static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3749{
3750 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3751 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3752 bool was_interruptible;
2b4e57bd
ED		 3753 int ret;
3754
3755 /* rc6 disabled by default due to repeated reports of hanging during
3756 * boot and resume.
3757 */
3758 if (!intel_enable_rc6(dev))
3759 return;
3760
79f5b2c7
DV		 3761 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3762
2b4e57bd 3763 ret = ironlake_setup_rc6(dev);
79f5b2c7 3764 if (ret)
2b4e57bd 3765 return;
2b4e57bd 3766
3e960501
CW		 3767 was_interruptible = dev_priv->mm.interruptible;
3768 dev_priv->mm.interruptible = false;
3769
2b4e57bd
ED		 3770 /*
3771 * GPU can automatically power down the render unit if given a page
3772 * to save state.
3773 */
6d90c952 3774 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3775 if (ret) {
3776 ironlake_teardown_rc6(dev);
3e960501 3777 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3778 return;
3779 }
3780
6d90c952
DV		 3781 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3782 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3783 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3784 MI_MM_SPACE_GTT |
3785 MI_SAVE_EXT_STATE_EN |
3786 MI_RESTORE_EXT_STATE_EN |
3787 MI_RESTORE_INHIBIT);
3788 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3789 intel_ring_emit(ring, MI_NOOP);
3790 intel_ring_emit(ring, MI_FLUSH);
3791 intel_ring_advance(ring);
2b4e57bd
ED		 3792
3793 /*
3794 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3795 * does an implicit flush, combined with MI_FLUSH above, it should be
3796 * safe to assume that renderctx is valid
3797 */
3e960501
CW		 3798 ret = intel_ring_idle(ring);
3799 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3800 if (ret) {
def27a58 3801 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3802 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3803 return;
3804 }
3805
f343c5f6 3806 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3807 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 3808
3809 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 3810}
3811
dde18883
ED		 3812static unsigned long intel_pxfreq(u32 vidfreq)
3813{
3814 unsigned long freq;
3815 int div = (vidfreq & 0x3f0000) >> 16;
3816 int post = (vidfreq & 0x3000) >> 12;
3817 int pre = (vidfreq & 0x7);
3818
3819 if (!pre)
3820 return 0;
3821
3822 freq = ((div * 133333) / ((1<<post) * pre));
3823
3824 return freq;
3825}
3826
eb48eb00
DV		 3827static const struct cparams {
3828 u16 i;
3829 u16 t;
3830 u16 m;
3831 u16 c;
3832} cparams[] = {
3833 { 1, 1333, 301, 28664 },
3834 { 1, 1066, 294, 24460 },
3835 { 1, 800, 294, 25192 },
3836 { 0, 1333, 276, 27605 },
3837 { 0, 1066, 276, 27605 },
3838 { 0, 800, 231, 23784 },
3839};
3840
f531dcb2 3841static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3842{
3843 u64 total_count, diff, ret;
3844 u32 count1, count2, count3, m = 0, c = 0;
3845 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3846 int i;
3847
02d71956
DV		 3848 assert_spin_locked(&mchdev_lock);
3849
20e4d407 3850 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3851
3852 /* Prevent division-by-zero if we are asking too fast.
3853 * Also, we don't get interesting results if we are polling
3854 * faster than once in 10ms, so just return the saved value
3855 * in such cases.
3856 */
3857 if (diff1 <= 10)
20e4d407 3858 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3859
3860 count1 = I915_READ(DMIEC);
3861 count2 = I915_READ(DDREC);
3862 count3 = I915_READ(CSIEC);
3863
3864 total_count = count1 + count2 + count3;
3865
3866 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3867 if (total_count < dev_priv->ips.last_count1) {
3868 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3869 diff += total_count;
3870 } else {
20e4d407 3871 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3872 }
3873
3874 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3875 if (cparams[i].i == dev_priv->ips.c_m &&
3876 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3877 m = cparams[i].m;
3878 c = cparams[i].c;
3879 break;
3880 }
3881 }
3882
3883 diff = div_u64(diff, diff1);
3884 ret = ((m * diff) + c);
3885 ret = div_u64(ret, 10);
3886
20e4d407
DV		 3887 dev_priv->ips.last_count1 = total_count;
3888 dev_priv->ips.last_time1 = now;
eb48eb00 3889
20e4d407 3890 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3891
3892 return ret;
3893}
3894
f531dcb2
CW		 3895unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3896{
3897 unsigned long val;
3898
3899 if (dev_priv->info->gen != 5)
3900 return 0;
3901
3902 spin_lock_irq(&mchdev_lock);
3903
3904 val = __i915_chipset_val(dev_priv);
3905
3906 spin_unlock_irq(&mchdev_lock);
3907
3908 return val;
3909}
3910
eb48eb00
DV		 3911unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3912{
3913 unsigned long m, x, b;
3914 u32 tsfs;
3915
3916 tsfs = I915_READ(TSFS);
3917
3918 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3919 x = I915_READ8(TR1);
3920
3921 b = tsfs & TSFS_INTR_MASK;
3922
3923 return ((m * x) / 127) - b;
3924}
3925
3926static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3927{
3928 static const struct v_table {
3929 u16 vd; /* in .1 mil */
3930 u16 vm; /* in .1 mil */
3931 } v_table[] = {
3932 { 0, 0, },
3933 { 375, 0, },
3934 { 500, 0, },
3935 { 625, 0, },
3936 { 750, 0, },
3937 { 875, 0, },
3938 { 1000, 0, },
3939 { 1125, 0, },
3940 { 4125, 3000, },
3941 { 4125, 3000, },
3942 { 4125, 3000, },
3943 { 4125, 3000, },
3944 { 4125, 3000, },
3945 { 4125, 3000, },
3946 { 4125, 3000, },
3947 { 4125, 3000, },
3948 { 4125, 3000, },
3949 { 4125, 3000, },
3950 { 4125, 3000, },
3951 { 4125, 3000, },
3952 { 4125, 3000, },
3953 { 4125, 3000, },
3954 { 4125, 3000, },
3955 { 4125, 3000, },
3956 { 4125, 3000, },
3957 { 4125, 3000, },
3958 { 4125, 3000, },
3959 { 4125, 3000, },
3960 { 4125, 3000, },
3961 { 4125, 3000, },
3962 { 4125, 3000, },
3963 { 4125, 3000, },
3964 { 4250, 3125, },
3965 { 4375, 3250, },
3966 { 4500, 3375, },
3967 { 4625, 3500, },
3968 { 4750, 3625, },
3969 { 4875, 3750, },
3970 { 5000, 3875, },
3971 { 5125, 4000, },
3972 { 5250, 4125, },
3973 { 5375, 4250, },
3974 { 5500, 4375, },
3975 { 5625, 4500, },
3976 { 5750, 4625, },
3977 { 5875, 4750, },
3978 { 6000, 4875, },
3979 { 6125, 5000, },
3980 { 6250, 5125, },
3981 { 6375, 5250, },
3982 { 6500, 5375, },
3983 { 6625, 5500, },
3984 { 6750, 5625, },
3985 { 6875, 5750, },
3986 { 7000, 5875, },
3987 { 7125, 6000, },
3988 { 7250, 6125, },
3989 { 7375, 6250, },
3990 { 7500, 6375, },
3991 { 7625, 6500, },
3992 { 7750, 6625, },
3993 { 7875, 6750, },
3994 { 8000, 6875, },
3995 { 8125, 7000, },
3996 { 8250, 7125, },
3997 { 8375, 7250, },
3998 { 8500, 7375, },
3999 { 8625, 7500, },
4000 { 8750, 7625, },
4001 { 8875, 7750, },
4002 { 9000, 7875, },
4003 { 9125, 8000, },
4004 { 9250, 8125, },
4005 { 9375, 8250, },
4006 { 9500, 8375, },
4007 { 9625, 8500, },
4008 { 9750, 8625, },
4009 { 9875, 8750, },
4010 { 10000, 8875, },
4011 { 10125, 9000, },
4012 { 10250, 9125, },
4013 { 10375, 9250, },
4014 { 10500, 9375, },
4015 { 10625, 9500, },
4016 { 10750, 9625, },
4017 { 10875, 9750, },
4018 { 11000, 9875, },
4019 { 11125, 10000, },
4020 { 11250, 10125, },
4021 { 11375, 10250, },
4022 { 11500, 10375, },
4023 { 11625, 10500, },
4024 { 11750, 10625, },
4025 { 11875, 10750, },
4026 { 12000, 10875, },
4027 { 12125, 11000, },
4028 { 12250, 11125, },
4029 { 12375, 11250, },
4030 { 12500, 11375, },
4031 { 12625, 11500, },
4032 { 12750, 11625, },
4033 { 12875, 11750, },
4034 { 13000, 11875, },
4035 { 13125, 12000, },
4036 { 13250, 12125, },
4037 { 13375, 12250, },
4038 { 13500, 12375, },
4039 { 13625, 12500, },
4040 { 13750, 12625, },
4041 { 13875, 12750, },
4042 { 14000, 12875, },
4043 { 14125, 13000, },
4044 { 14250, 13125, },
4045 { 14375, 13250, },
4046 { 14500, 13375, },
4047 { 14625, 13500, },
4048 { 14750, 13625, },
4049 { 14875, 13750, },
4050 { 15000, 13875, },
4051 { 15125, 14000, },
4052 { 15250, 14125, },
4053 { 15375, 14250, },
4054 { 15500, 14375, },
4055 { 15625, 14500, },
4056 { 15750, 14625, },
4057 { 15875, 14750, },
4058 { 16000, 14875, },
4059 { 16125, 15000, },
4060 };
4061 if (dev_priv->info->is_mobile)
4062 return v_table[pxvid].vm;
4063 else
4064 return v_table[pxvid].vd;
4065}
4066
02d71956 4067static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4068{
4069 struct timespec now, diff1;
4070 u64 diff;
4071 unsigned long diffms;
4072 u32 count;
4073
02d71956 4074 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4075
4076 getrawmonotonic(&now);
20e4d407 4077 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4078
4079 /* Don't divide by 0 */
4080 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4081 if (!diffms)
4082 return;
4083
4084 count = I915_READ(GFXEC);
4085
20e4d407
DV		 4086 if (count < dev_priv->ips.last_count2) {
4087 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4088 diff += count;
4089 } else {
20e4d407 4090 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4091 }
4092
20e4d407
DV		 4093 dev_priv->ips.last_count2 = count;
4094 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4095
4096 /* More magic constants... */
4097 diff = diff * 1181;
4098 diff = div_u64(diff, diffms * 10);
20e4d407 4099 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4100}
4101
02d71956
DV		 4102void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4103{
4104 if (dev_priv->info->gen != 5)
4105 return;
4106
9270388e 4107 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4108
4109 __i915_update_gfx_val(dev_priv);
4110
9270388e 4111 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4112}
4113
f531dcb2 4114static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4115{
4116 unsigned long t, corr, state1, corr2, state2;
4117 u32 pxvid, ext_v;
4118
02d71956
DV		 4119 assert_spin_locked(&mchdev_lock);
4120
c6a828d3 4121 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4122 pxvid = (pxvid >> 24) & 0x7f;
4123 ext_v = pvid_to_extvid(dev_priv, pxvid);
4124
4125 state1 = ext_v;
4126
4127 t = i915_mch_val(dev_priv);
4128
4129 /* Revel in the empirically derived constants */
4130
4131 /* Correction factor in 1/100000 units */
4132 if (t > 80)
4133 corr = ((t * 2349) + 135940);
4134 else if (t >= 50)
4135 corr = ((t * 964) + 29317);
4136 else /* < 50 */
4137 corr = ((t * 301) + 1004);
4138
4139 corr = corr * ((150142 * state1) / 10000 - 78642);
4140 corr /= 100000;
20e4d407 4141 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4142
4143 state2 = (corr2 * state1) / 10000;
4144 state2 /= 100; /* convert to mW */
4145
02d71956 4146 __i915_update_gfx_val(dev_priv);
eb48eb00 4147
20e4d407 4148 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4149}
4150
f531dcb2
CW		 4151unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4152{
4153 unsigned long val;
4154
4155 if (dev_priv->info->gen != 5)
4156 return 0;
4157
4158 spin_lock_irq(&mchdev_lock);
4159
4160 val = __i915_gfx_val(dev_priv);
4161
4162 spin_unlock_irq(&mchdev_lock);
4163
4164 return val;
4165}
4166
eb48eb00
DV		 4167/**
4168 * i915_read_mch_val - return value for IPS use
4169 *
4170 * Calculate and return a value for the IPS driver to use when deciding whether
4171 * we have thermal and power headroom to increase CPU or GPU power budget.
4172 */
4173unsigned long i915_read_mch_val(void)
4174{
4175 struct drm_i915_private *dev_priv;
4176 unsigned long chipset_val, graphics_val, ret = 0;
4177
9270388e 4178 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4179 if (!i915_mch_dev)
4180 goto out_unlock;
4181 dev_priv = i915_mch_dev;
4182
f531dcb2
CW		 4183 chipset_val = __i915_chipset_val(dev_priv);
4184 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4185
4186 ret = chipset_val + graphics_val;
4187
4188out_unlock:
9270388e 4189 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4190
4191 return ret;
4192}
4193EXPORT_SYMBOL_GPL(i915_read_mch_val);
4194
4195/**
4196 * i915_gpu_raise - raise GPU frequency limit
4197 *
4198 * Raise the limit; IPS indicates we have thermal headroom.
4199 */
4200bool i915_gpu_raise(void)
4201{
4202 struct drm_i915_private *dev_priv;
4203 bool ret = true;
4204
9270388e 4205 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4206 if (!i915_mch_dev) {
4207 ret = false;
4208 goto out_unlock;
4209 }
4210 dev_priv = i915_mch_dev;
4211
20e4d407
DV		 4212 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4213 dev_priv->ips.max_delay--;
eb48eb00
DV		 4214
4215out_unlock:
9270388e 4216 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4217
4218 return ret;
4219}
4220EXPORT_SYMBOL_GPL(i915_gpu_raise);
4221
4222/**
4223 * i915_gpu_lower - lower GPU frequency limit
4224 *
4225 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4226 * frequency maximum.
4227 */
4228bool i915_gpu_lower(void)
4229{
4230 struct drm_i915_private *dev_priv;
4231 bool ret = true;
4232
9270388e 4233 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4234 if (!i915_mch_dev) {
4235 ret = false;
4236 goto out_unlock;
4237 }
4238 dev_priv = i915_mch_dev;
4239
20e4d407
DV		 4240 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4241 dev_priv->ips.max_delay++;
eb48eb00
DV		 4242
4243out_unlock:
9270388e 4244 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4245
4246 return ret;
4247}
4248EXPORT_SYMBOL_GPL(i915_gpu_lower);
4249
4250/**
4251 * i915_gpu_busy - indicate GPU business to IPS
4252 *
4253 * Tell the IPS driver whether or not the GPU is busy.
4254 */
4255bool i915_gpu_busy(void)
4256{
4257 struct drm_i915_private *dev_priv;
f047e395 4258 struct intel_ring_buffer *ring;
eb48eb00 4259 bool ret = false;
f047e395 4260 int i;
eb48eb00 4261
9270388e 4262 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4263 if (!i915_mch_dev)
4264 goto out_unlock;
4265 dev_priv = i915_mch_dev;
4266
f047e395
CW		 4267 for_each_ring(ring, dev_priv, i)
4268 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4269
4270out_unlock:
9270388e 4271 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4272
4273 return ret;
4274}
4275EXPORT_SYMBOL_GPL(i915_gpu_busy);
4276
4277/**
4278 * i915_gpu_turbo_disable - disable graphics turbo
4279 *
4280 * Disable graphics turbo by resetting the max frequency and setting the
4281 * current frequency to the default.
4282 */
4283bool i915_gpu_turbo_disable(void)
4284{
4285 struct drm_i915_private *dev_priv;
4286 bool ret = true;
4287
9270388e 4288 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4289 if (!i915_mch_dev) {
4290 ret = false;
4291 goto out_unlock;
4292 }
4293 dev_priv = i915_mch_dev;
4294
20e4d407 4295 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4296
20e4d407 4297 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4298 ret = false;
4299
4300out_unlock:
9270388e 4301 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4302
4303 return ret;
4304}
4305EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4306
4307/**
4308 * Tells the intel_ips driver that the i915 driver is now loaded, if
4309 * IPS got loaded first.
4310 *
4311 * This awkward dance is so that neither module has to depend on the
4312 * other in order for IPS to do the appropriate communication of
4313 * GPU turbo limits to i915.
4314 */
4315static void
4316ips_ping_for_i915_load(void)
4317{
4318 void (*link)(void);
4319
4320 link = symbol_get(ips_link_to_i915_driver);
4321 if (link) {
4322 link();
4323 symbol_put(ips_link_to_i915_driver);
4324 }
4325}
4326
4327void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4328{
02d71956
DV		 4329 /* We only register the i915 ips part with intel-ips once everything is
4330 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4331 spin_lock_irq(&mchdev_lock);
eb48eb00 4332 i915_mch_dev = dev_priv;
9270388e 4333 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4334
4335 ips_ping_for_i915_load();
4336}
4337
4338void intel_gpu_ips_teardown(void)
4339{
9270388e 4340 spin_lock_irq(&mchdev_lock);
eb48eb00 4341 i915_mch_dev = NULL;
9270388e 4342 spin_unlock_irq(&mchdev_lock);
eb48eb00 4343}
76c3552f 4344
8090c6b9 4345static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4346{
4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348 u32 lcfuse;
4349 u8 pxw[16];
4350 int i;
4351
4352 /* Disable to program */
4353 I915_WRITE(ECR, 0);
4354 POSTING_READ(ECR);
4355
4356 /* Program energy weights for various events */
4357 I915_WRITE(SDEW, 0x15040d00);
4358 I915_WRITE(CSIEW0, 0x007f0000);
4359 I915_WRITE(CSIEW1, 0x1e220004);
4360 I915_WRITE(CSIEW2, 0x04000004);
4361
4362 for (i = 0; i < 5; i++)
4363 I915_WRITE(PEW + (i * 4), 0);
4364 for (i = 0; i < 3; i++)
4365 I915_WRITE(DEW + (i * 4), 0);
4366
4367 /* Program P-state weights to account for frequency power adjustment */
4368 for (i = 0; i < 16; i++) {
4369 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4370 unsigned long freq = intel_pxfreq(pxvidfreq);
4371 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4372 PXVFREQ_PX_SHIFT;
4373 unsigned long val;
4374
4375 val = vid * vid;
4376 val *= (freq / 1000);
4377 val *= 255;
4378 val /= (127*127*900);
4379 if (val > 0xff)
4380 DRM_ERROR("bad pxval: %ld\n", val);
4381 pxw[i] = val;
4382 }
4383 /* Render standby states get 0 weight */
4384 pxw[14] = 0;
4385 pxw[15] = 0;
4386
4387 for (i = 0; i < 4; i++) {
4388 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4389 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4390 I915_WRITE(PXW + (i * 4), val);
4391 }
4392
4393 /* Adjust magic regs to magic values (more experimental results) */
4394 I915_WRITE(OGW0, 0);
4395 I915_WRITE(OGW1, 0);
4396 I915_WRITE(EG0, 0x00007f00);
4397 I915_WRITE(EG1, 0x0000000e);
4398 I915_WRITE(EG2, 0x000e0000);
4399 I915_WRITE(EG3, 0x68000300);
4400 I915_WRITE(EG4, 0x42000000);
4401 I915_WRITE(EG5, 0x00140031);
4402 I915_WRITE(EG6, 0);
4403 I915_WRITE(EG7, 0);
4404
4405 for (i = 0; i < 8; i++)
4406 I915_WRITE(PXWL + (i * 4), 0);
4407
4408 /* Enable PMON + select events */
4409 I915_WRITE(ECR, 0x80000019);
4410
4411 lcfuse = I915_READ(LCFUSE02);
4412
20e4d407 4413 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4414}
4415
8090c6b9
DV		 4416void intel_disable_gt_powersave(struct drm_device *dev)
4417{
1a01ab3b
JB		 4418 struct drm_i915_private *dev_priv = dev->dev_private;
4419
fd0c0642
DV		 4420 /* Interrupts should be disabled already to avoid re-arming. */
4421 WARN_ON(dev->irq_enabled);
4422
930ebb46 4423 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4424 ironlake_disable_drps(dev);
930ebb46 4425 ironlake_disable_rc6(dev);
0a073b84 4426 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4427 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4428 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4429 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4430 if (IS_VALLEYVIEW(dev))
4431 valleyview_disable_rps(dev);
4432 else
4433 gen6_disable_rps(dev);
c0951f0c 4434 dev_priv->rps.enabled = false;
4fc688ce 4435 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4436 }
8090c6b9
DV		 4437}
4438
1a01ab3b
JB		 4439static void intel_gen6_powersave_work(struct work_struct *work)
4440{
4441 struct drm_i915_private *dev_priv =
4442 container_of(work, struct drm_i915_private,
4443 rps.delayed_resume_work.work);
4444 struct drm_device *dev = dev_priv->dev;
4445
4fc688ce 4446 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4447
4448 if (IS_VALLEYVIEW(dev)) {
4449 valleyview_enable_rps(dev);
6edee7f3
BW		 4450 } else if (IS_BROADWELL(dev)) {
4451 gen8_enable_rps(dev);
4452 gen6_update_ring_freq(dev);
0a073b84
JB		 4453 } else {
4454 gen6_enable_rps(dev);
4455 gen6_update_ring_freq(dev);
4456 }
c0951f0c 4457 dev_priv->rps.enabled = true;
4fc688ce 4458 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4459}
4460
8090c6b9
DV		 4461void intel_enable_gt_powersave(struct drm_device *dev)
4462{
1a01ab3b
JB		 4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464
8090c6b9
DV		 4465 if (IS_IRONLAKE_M(dev)) {
4466 ironlake_enable_drps(dev);
4467 ironlake_enable_rc6(dev);
4468 intel_init_emon(dev);
0a073b84 4469 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4470 /*
4471 * PCU communication is slow and this doesn't need to be
4472 * done at any specific time, so do this out of our fast path
4473 * to make resume and init faster.
4474 */
4475 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4476 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4477 }
4478}
4479
3107bd48
DV		 4480static void ibx_init_clock_gating(struct drm_device *dev)
4481{
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483
4484 /*
4485 * On Ibex Peak and Cougar Point, we need to disable clock
4486 * gating for the panel power sequencer or it will fail to
4487 * start up when no ports are active.
4488 */
4489 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4490}
4491
0e088b8f
VS		 4492static void g4x_disable_trickle_feed(struct drm_device *dev)
4493{
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 int pipe;
4496
4497 for_each_pipe(pipe) {
4498 I915_WRITE(DSPCNTR(pipe),
4499 I915_READ(DSPCNTR(pipe)) |
4500 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4501 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4502 }
4503}
4504
017636cc
VS		 4505static void ilk_init_lp_watermarks(struct drm_device *dev)
4506{
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508
4509 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4510 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4511 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4512
4513 /*
4514 * Don't touch WM1S_LP_EN here.
4515 * Doing so could cause underruns.
4516 */
4517}
4518
1fa61106 4519static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4520{
4521 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4522 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4523
f1e8fa56
DL		 4524 /*
4525 * Required for FBC
4526 * WaFbcDisableDpfcClockGating:ilk
4527 */
4d47e4f5
DL		 4528 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4529 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4530 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4531
4532 I915_WRITE(PCH_3DCGDIS0,
4533 MARIUNIT_CLOCK_GATE_DISABLE |
4534 SVSMUNIT_CLOCK_GATE_DISABLE);
4535 I915_WRITE(PCH_3DCGDIS1,
4536 VFMUNIT_CLOCK_GATE_DISABLE);
4537
6f1d69b0
ED		 4538 /*
4539 * According to the spec the following bits should be set in
4540 * order to enable memory self-refresh
4541 * The bit 22/21 of 0x42004
4542 * The bit 5 of 0x42020
4543 * The bit 15 of 0x45000
4544 */
4545 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4546 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4547 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4548 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4549 I915_WRITE(DISP_ARB_CTL,
4550 (I915_READ(DISP_ARB_CTL) |
4551 DISP_FBC_WM_DIS));
017636cc
VS		 4552
4553 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4554
4555 /*
4556 * Based on the document from hardware guys the following bits
4557 * should be set unconditionally in order to enable FBC.
4558 * The bit 22 of 0x42000
4559 * The bit 22 of 0x42004
4560 * The bit 7,8,9 of 0x42020.
4561 */
4562 if (IS_IRONLAKE_M(dev)) {
4bb35334 4563 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4564 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4565 I915_READ(ILK_DISPLAY_CHICKEN1) |
4566 ILK_FBCQ_DIS);
4567 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4568 I915_READ(ILK_DISPLAY_CHICKEN2) |
4569 ILK_DPARB_GATE);
6f1d69b0
ED		 4570 }
4571
4d47e4f5
DL		 4572 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4573
6f1d69b0
ED		 4574 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4575 I915_READ(ILK_DISPLAY_CHICKEN2) |
4576 ILK_ELPIN_409_SELECT);
4577 I915_WRITE(_3D_CHICKEN2,
4578 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4579 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4580
ecdb4eb7 4581 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4582 I915_WRITE(CACHE_MODE_0,
4583 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4584
0e088b8f 4585 g4x_disable_trickle_feed(dev);
bdad2b2f 4586
3107bd48
DV		 4587 ibx_init_clock_gating(dev);
4588}
4589
4590static void cpt_init_clock_gating(struct drm_device *dev)
4591{
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 int pipe;
3f704fa2 4594 uint32_t val;
3107bd48
DV		 4595
4596 /*
4597 * On Ibex Peak and Cougar Point, we need to disable clock
4598 * gating for the panel power sequencer or it will fail to
4599 * start up when no ports are active.
4600 */
cd664078
JB		 4601 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4602 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4603 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4604 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4605 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4606 /* The below fixes the weird display corruption, a few pixels shifted
4607 * downward, on (only) LVDS of some HP laptops with IVY.
4608 */
3f704fa2 4609 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4610 val = I915_READ(TRANS_CHICKEN2(pipe));
4611 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4612 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4613 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4614 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4615 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4616 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4617 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4618 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4619 }
3107bd48
DV		 4620 /* WADP0ClockGatingDisable */
4621 for_each_pipe(pipe) {
4622 I915_WRITE(TRANS_CHICKEN1(pipe),
4623 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4624 }
6f1d69b0
ED		 4625}
4626
1d7aaa0c
DV		 4627static void gen6_check_mch_setup(struct drm_device *dev)
4628{
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 uint32_t tmp;
4631
4632 tmp = I915_READ(MCH_SSKPD);
4633 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4634 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4635 DRM_INFO("This can cause pipe underruns and display issues.\n");
4636 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4637 }
4638}
4639
1fa61106 4640static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4641{
4642 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4643 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4644
231e54f6 4645 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4646
4647 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4648 I915_READ(ILK_DISPLAY_CHICKEN2) |
4649 ILK_ELPIN_409_SELECT);
4650
ecdb4eb7 4651 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4652 I915_WRITE(_3D_CHICKEN,
4653 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4654
ecdb4eb7 4655 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4656 if (IS_SNB_GT1(dev))
4657 I915_WRITE(GEN6_GT_MODE,
4658 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4659
017636cc 4660 ilk_init_lp_watermarks(dev);
6f1d69b0 4661
6f1d69b0 4662 I915_WRITE(CACHE_MODE_0,
50743298 4663 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4664
4665 I915_WRITE(GEN6_UCGCTL1,
4666 I915_READ(GEN6_UCGCTL1) |
4667 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4668 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4669
4670 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4671 * gating disable must be set. Failure to set it results in
4672 * flickering pixels due to Z write ordering failures after
4673 * some amount of runtime in the Mesa "fire" demo, and Unigine
4674 * Sanctuary and Tropics, and apparently anything else with
4675 * alpha test or pixel discard.
4676 *
4677 * According to the spec, bit 11 (RCCUNIT) must also be set,
4678 * but we didn't debug actual testcases to find it out.
0f846f81 4679 *
ef59318c
VS		 4680 * WaDisableRCCUnitClockGating:snb
4681 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 4682 */
4683 I915_WRITE(GEN6_UCGCTL2,
4684 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4685 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4686
4687 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4688 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4689 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4690
4691 /*
4692 * According to the spec the following bits should be
4693 * set in order to enable memory self-refresh and fbc:
4694 * The bit21 and bit22 of 0x42000
4695 * The bit21 and bit22 of 0x42004
4696 * The bit5 and bit7 of 0x42020
4697 * The bit14 of 0x70180
4698 * The bit14 of 0x71180
4bb35334
DL		 4699 *
4700 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4701 */
4702 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4703 I915_READ(ILK_DISPLAY_CHICKEN1) |
4704 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4705 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4706 I915_READ(ILK_DISPLAY_CHICKEN2) |
4707 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4708 I915_WRITE(ILK_DSPCLK_GATE_D,
4709 I915_READ(ILK_DSPCLK_GATE_D) |
4710 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4711 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4712
0e088b8f 4713 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4714
4715 /* The default value should be 0x200 according to docs, but the two
4716 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4717 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4718 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4719
4720 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4721
4722 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4723}
4724
4725static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4726{
4727 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4728
3aad9059 4729 /*
46680e0a 4730 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 4731 *
4732 * This actually overrides the dispatch
4733 * mode for all thread types.
4734 */
6f1d69b0
ED		 4735 reg &= ~GEN7_FF_SCHED_MASK;
4736 reg |= GEN7_FF_TS_SCHED_HW;
4737 reg |= GEN7_FF_VS_SCHED_HW;
4738 reg |= GEN7_FF_DS_SCHED_HW;
4739
4740 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4741}
4742
17a303ec
PZ		 4743static void lpt_init_clock_gating(struct drm_device *dev)
4744{
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746
4747 /*
4748 * TODO: this bit should only be enabled when really needed, then
4749 * disabled when not needed anymore in order to save power.
4750 */
4751 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4752 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4753 I915_READ(SOUTH_DSPCLK_GATE_D) |
4754 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4755
4756 /* WADPOClockGatingDisable:hsw */
4757 I915_WRITE(_TRANSA_CHICKEN1,
4758 I915_READ(_TRANSA_CHICKEN1) |
4759 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4760}
4761
7d708ee4
ID		 4762static void lpt_suspend_hw(struct drm_device *dev)
4763{
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765
4766 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4767 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4768
4769 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4770 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4771 }
4772}
4773
1020a5c2
BW		 4774static void gen8_init_clock_gating(struct drm_device *dev)
4775{
4776 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 4777 enum pipe i;
1020a5c2
BW		 4778
4779 I915_WRITE(WM3_LP_ILK, 0);
4780 I915_WRITE(WM2_LP_ILK, 0);
4781 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 4782
4783 /* FIXME(BDW): Check all the w/a, some might only apply to
4784 * pre-production hw. */
4785
4167e32c
DL		 4786 /*
4787 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4788 * pre-production hardware
4789 */
fd392b60
BW		 4790 I915_WRITE(HALF_SLICE_CHICKEN3,
4791 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 4792 I915_WRITE(HALF_SLICE_CHICKEN3,
4793 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 4794 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4795
7f88da0c
BW		 4796 I915_WRITE(_3D_CHICKEN3,
4797 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4798
a75f3628
BW		 4799 I915_WRITE(COMMON_SLICE_CHICKEN2,
4800 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4801
4c2e7a5f
BW		 4802 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4803 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4804
ab57fff1 4805 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 4806 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 4807
ab57fff1 4808 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4809 I915_WRITE(CHICKEN_PAR1_1,
4810 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4811
ab57fff1 4812 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4813 for_each_pipe(i) {
4814 I915_WRITE(CHICKEN_PIPESL_1(i),
4815 I915_READ(CHICKEN_PIPESL_1(i) |
4816 DPRS_MASK_VBLANK_SRD));
4817 }
63801f21
BW		 4818
4819 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4820 * workaround for for a possible hang in the unlikely event a TLB
4821 * invalidation occurs during a PSD flush.
4822 */
4823 I915_WRITE(HDC_CHICKEN0,
4824 I915_READ(HDC_CHICKEN0) |
4825 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 4826
4827 /* WaVSRefCountFullforceMissDisable:bdw */
4828 /* WaDSRefCountFullforceMissDisable:bdw */
4829 I915_WRITE(GEN7_FF_THREAD_MODE,
4830 I915_READ(GEN7_FF_THREAD_MODE) &
4831 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
1020a5c2
BW		 4832}
4833
cad2a2d7
ED		 4834static void haswell_init_clock_gating(struct drm_device *dev)
4835{
4836 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 4837
017636cc 4838 ilk_init_lp_watermarks(dev);
cad2a2d7 4839
f3fc4884
FJ		 4840 /* L3 caching of data atomics doesn't work -- disable it. */
4841 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4842 I915_WRITE(HSW_ROW_CHICKEN3,
4843 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4844
ecdb4eb7 4845 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4846 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4847 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4848 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4849
e36ea7ff
VS		 4850 /* WaVSRefCountFullforceMissDisable:hsw */
4851 I915_WRITE(GEN7_FF_THREAD_MODE,
4852 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 4853
fe27c606
CW		 4854 /* enable HiZ Raw Stall Optimization */
4855 I915_WRITE(CACHE_MODE_0_GEN7,
4856 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4857
ecdb4eb7 4858 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4859 I915_WRITE(CACHE_MODE_1,
4860 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4861
ecdb4eb7 4862 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4863 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4864
90a88643
PZ		 4865 /* WaRsPkgCStateDisplayPMReq:hsw */
4866 I915_WRITE(CHICKEN_PAR1_1,
4867 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4868
17a303ec 4869 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4870}
4871
1fa61106 4872static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4873{
4874 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4875 uint32_t snpcr;
6f1d69b0 4876
017636cc 4877 ilk_init_lp_watermarks(dev);
6f1d69b0 4878
231e54f6 4879 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4880
ecdb4eb7 4881 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4882 I915_WRITE(_3D_CHICKEN3,
4883 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4884
ecdb4eb7 4885 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4886 I915_WRITE(IVB_CHICKEN3,
4887 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4888 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4889
ecdb4eb7 4890 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4891 if (IS_IVB_GT1(dev))
4892 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4893 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4894
ecdb4eb7 4895 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4896 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4897 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4898
ecdb4eb7 4899 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4900 I915_WRITE(GEN7_L3CNTLREG1,
4901 GEN7_WA_FOR_GEN7_L3_CONTROL);
4902 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4903 GEN7_WA_L3_CHICKEN_MODE);
4904 if (IS_IVB_GT1(dev))
4905 I915_WRITE(GEN7_ROW_CHICKEN2,
4906 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 4907 else {
4908 /* must write both registers */
4909 I915_WRITE(GEN7_ROW_CHICKEN2,
4910 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 4911 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4912 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 4913 }
6f1d69b0 4914
ecdb4eb7 4915 /* WaForceL3Serialization:ivb */
61939d97
JB		 4916 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4917 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4918
1b80a19a 4919 /*
0f846f81 4920 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4921 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4922 */
4923 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 4924 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 4925
ecdb4eb7 4926 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4927 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4928 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4929 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4930
0e088b8f 4931 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 4932
4933 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4934
116f2b6d
CW		 4935 /* enable HiZ Raw Stall Optimization */
4936 I915_WRITE(CACHE_MODE_0_GEN7,
4937 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4938
ecdb4eb7 4939 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4940 I915_WRITE(CACHE_MODE_1,
4941 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4942
4943 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4944 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4945 snpcr |= GEN6_MBC_SNPCR_MED;
4946 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4947
ab5c608b
BW		 4948 if (!HAS_PCH_NOP(dev))
4949 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4950
4951 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4952}
4953
1fa61106 4954static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4955{
4956 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 4957 u32 val;
4958
4959 mutex_lock(&dev_priv->rps.hw_lock);
4960 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4961 mutex_unlock(&dev_priv->rps.hw_lock);
4962 switch ((val >> 6) & 3) {
4963 case 0:
85b1d7b3
JB		 4964 dev_priv->mem_freq = 800;
4965 break;
f64a28a7 4966 case 1:
85b1d7b3
JB		 4967 dev_priv->mem_freq = 1066;
4968 break;
f64a28a7 4969 case 2:
85b1d7b3
JB		 4970 dev_priv->mem_freq = 1333;
4971 break;
f64a28a7 4972 case 3:
2325991e 4973 dev_priv->mem_freq = 1333;
f64a28a7 4974 break;
85b1d7b3
JB		 4975 }
4976 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 4977
d7fe0cc0 4978 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4979
ecdb4eb7 4980 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4981 I915_WRITE(_3D_CHICKEN3,
4982 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4983
ecdb4eb7 4984 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4985 I915_WRITE(IVB_CHICKEN3,
4986 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4987 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4988
fad7d36e 4989 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 4990 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4991 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4992 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4993 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4994
d50764a9 4995 /* WaDisableL3CacheAging:vlv */
d0cf5ead 4996 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0 4997
ecdb4eb7 4998 /* WaForceL3Serialization:vlv */
61939d97
JB		 4999 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5000 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5001
ecdb4eb7 5002 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5003 I915_WRITE(GEN7_ROW_CHICKEN2,
5004 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5005
ecdb4eb7 5006 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5007 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5008 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5009 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5010
46680e0a
VS		 5011 gen7_setup_fixed_func_scheduler(dev_priv);
5012
3c0edaeb 5013 /*
0f846f81 5014 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5015 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5016 */
5017 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5018 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5019
c5c32cda 5020 /* WaDisableL3Bank2xClockGate:vlv */
e3f33d46
JB		 5021 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5022
e0d8d59b 5023 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5024
afd58e79
VS		 5025 /*
5026 * BSpec says this must be set, even though
5027 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5028 */
6b26c86d
DV		 5029 I915_WRITE(CACHE_MODE_1,
5030 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5031
031994ee
VS		 5032 /*
5033 * WaIncreaseL3CreditsForVLVB0:vlv
5034 * This is the hardware default actually.
5035 */
5036 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5037
2d809570 5038 /*
ecdb4eb7 5039 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5040 * Disable clock gating on th GCFG unit to prevent a delay
5041 * in the reporting of vblank events.
5042 */
7a0d1eed 5043 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5044}
5045
1fa61106 5046static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5047{
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 uint32_t dspclk_gate;
5050
5051 I915_WRITE(RENCLK_GATE_D1, 0);
5052 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5053 GS_UNIT_CLOCK_GATE_DISABLE |
5054 CL_UNIT_CLOCK_GATE_DISABLE);
5055 I915_WRITE(RAMCLK_GATE_D, 0);
5056 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5057 OVRUNIT_CLOCK_GATE_DISABLE |
5058 OVCUNIT_CLOCK_GATE_DISABLE;
5059 if (IS_GM45(dev))
5060 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5061 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5062
5063 /* WaDisableRenderCachePipelinedFlush */
5064 I915_WRITE(CACHE_MODE_0,
5065 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5066
0e088b8f 5067 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5068}
5069
1fa61106 5070static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5071{
5072 struct drm_i915_private *dev_priv = dev->dev_private;
5073
5074 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5075 I915_WRITE(RENCLK_GATE_D2, 0);
5076 I915_WRITE(DSPCLK_GATE_D, 0);
5077 I915_WRITE(RAMCLK_GATE_D, 0);
5078 I915_WRITE16(DEUC, 0);
20f94967
VS		 5079 I915_WRITE(MI_ARB_STATE,
5080 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5081}
5082
1fa61106 5083static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5084{
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086
5087 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5088 I965_RCC_CLOCK_GATE_DISABLE |
5089 I965_RCPB_CLOCK_GATE_DISABLE |
5090 I965_ISC_CLOCK_GATE_DISABLE |
5091 I965_FBC_CLOCK_GATE_DISABLE);
5092 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5093 I915_WRITE(MI_ARB_STATE,
5094 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5095}
5096
1fa61106 5097static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5098{
5099 struct drm_i915_private *dev_priv = dev->dev_private;
5100 u32 dstate = I915_READ(D_STATE);
5101
5102 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5103 DSTATE_DOT_CLOCK_GATING;
5104 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5105
5106 if (IS_PINEVIEW(dev))
5107 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5108
5109 /* IIR "flip pending" means done if this bit is set */
5110 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5111}
5112
1fa61106 5113static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5114{
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116
5117 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5118}
5119
1fa61106 5120static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5121{
5122 struct drm_i915_private *dev_priv = dev->dev_private;
5123
5124 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5125}
5126
6f1d69b0
ED		 5127void intel_init_clock_gating(struct drm_device *dev)
5128{
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130
5131 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5132}
5133
7d708ee4
ID		 5134void intel_suspend_hw(struct drm_device *dev)
5135{
5136 if (HAS_PCH_LPT(dev))
5137 lpt_suspend_hw(dev);
5138}
5139
c1ca727f
ID		 5140#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5141 for (i = 0; \
5142 i < (power_domains)->power_well_count && \
5143 ((power_well) = &(power_domains)->power_wells[i]); \
5144 i++) \
5145 if ((power_well)->domains & (domain_mask))
5146
5147#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5148 for (i = (power_domains)->power_well_count - 1; \
5149 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5150 i--) \
5151 if ((power_well)->domains & (domain_mask))
5152
15d199ea
PZ		 5153/**
5154 * We should only use the power well if we explicitly asked the hardware to
5155 * enable it, so check if it's enabled and also check if we've requested it to
5156 * be enabled.
5157 */
c1ca727f
ID		 5158static bool hsw_power_well_enabled(struct drm_device *dev,
5159 struct i915_power_well *power_well)
5160{
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162
5163 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5164 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5165}
5166
ddf9c536
ID		 5167bool intel_display_power_enabled_sw(struct drm_device *dev,
5168 enum intel_display_power_domain domain)
5169{
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct i915_power_domains *power_domains;
5172
5173 power_domains = &dev_priv->power_domains;
5174
5175 return power_domains->domain_use_count[domain];
5176}
5177
b97186f0
PZ		 5178bool intel_display_power_enabled(struct drm_device *dev,
5179 enum intel_display_power_domain domain)
15d199ea
PZ		 5180{
5181 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5182 struct i915_power_domains *power_domains;
5183 struct i915_power_well *power_well;
5184 bool is_enabled;
5185 int i;
15d199ea 5186
c1ca727f
ID		 5187 power_domains = &dev_priv->power_domains;
5188
5189 is_enabled = true;
5190
5191 mutex_lock(&power_domains->lock);
5192 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5193 if (power_well->always_on)
5194 continue;
5195
c1ca727f
ID		 5196 if (!power_well->is_enabled(dev, power_well)) {
5197 is_enabled = false;
5198 break;
5199 }
5200 }
5201 mutex_unlock(&power_domains->lock);
5202
5203 return is_enabled;
15d199ea
PZ		 5204}
5205
d5e8fdc8
PZ		 5206static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5207{
5208 struct drm_device *dev = dev_priv->dev;
5209 unsigned long irqflags;
5210
f9dcb0df
PZ		 5211 /*
5212 * After we re-enable the power well, if we touch VGA register 0x3d5
5213 * we'll get unclaimed register interrupts. This stops after we write
5214 * anything to the VGA MSR register. The vgacon module uses this
5215 * register all the time, so if we unbind our driver and, as a
5216 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5217 * console_unlock(). So make here we touch the VGA MSR register, making
5218 * sure vgacon can keep working normally without triggering interrupts
5219 * and error messages.
5220 */
5221 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5222 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5223 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5224
d5e8fdc8
PZ		 5225 if (IS_BROADWELL(dev)) {
5226 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5227 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5228 dev_priv->de_irq_mask[PIPE_B]);
5229 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5230 ~dev_priv->de_irq_mask[PIPE_B] |
5231 GEN8_PIPE_VBLANK);
5232 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5233 dev_priv->de_irq_mask[PIPE_C]);
5234 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5235 ~dev_priv->de_irq_mask[PIPE_C] |
5236 GEN8_PIPE_VBLANK);
5237 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5238 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5239 }
5240}
5241
5242static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5243{
5244 struct drm_device *dev = dev_priv->dev;
5245 enum pipe p;
5246 unsigned long irqflags;
5247
5248 /*
5249 * After this, the registers on the pipes that are part of the power
5250 * well will become zero, so we have to adjust our counters according to
5251 * that.
5252 *
5253 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5254 */
5255 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5256 for_each_pipe(p)
5257 if (p != PIPE_A)
5258 dev->vblank[p].last = 0;
5259 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5260}
5261
c1ca727f
ID		 5262static void hsw_set_power_well(struct drm_device *dev,
5263 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5264{
5265 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5266 bool is_enabled, enable_requested;
5267 uint32_t tmp;
d0d3e513 5268
d62292c8
PZ		 5269 WARN_ON(dev_priv->pc8.enabled);
5270
fa42e23c 5271 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5272 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5273 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5274
fa42e23c
PZ		 5275 if (enable) {
5276 if (!enable_requested)
6aedd1f5
PZ		 5277 I915_WRITE(HSW_PWR_WELL_DRIVER,
5278 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5279
fa42e23c
PZ		 5280 if (!is_enabled) {
5281 DRM_DEBUG_KMS("Enabling power well\n");
5282 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5283 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5284 DRM_ERROR("Timeout enabling power well\n");
5285 }
596cc11e 5286
d5e8fdc8 5287 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5288 } else {
5289 if (enable_requested) {
5290 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5291 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5292 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5293
d5e8fdc8 5294 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5295 }
5296 }
fa42e23c 5297}
d0d3e513 5298
b4ed4484
ID		 5299static void __intel_power_well_get(struct drm_device *dev,
5300 struct i915_power_well *power_well)
2d66aef5 5301{
d62292c8
PZ		 5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303
5304 if (!power_well->count++ && power_well->set) {
5305 hsw_disable_package_c8(dev_priv);
c1ca727f 5306 power_well->set(dev, power_well, true);
d62292c8 5307 }
2d66aef5
VS		 5308}
5309
b4ed4484
ID		 5310static void __intel_power_well_put(struct drm_device *dev,
5311 struct i915_power_well *power_well)
2d66aef5 5312{
d62292c8
PZ		 5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314
2d66aef5 5315 WARN_ON(!power_well->count);
c1ca727f 5316
d62292c8 5317 if (!--power_well->count && power_well->set &&
d330a953 5318 i915.disable_power_well) {
c1ca727f 5319 power_well->set(dev, power_well, false);
d62292c8
PZ		 5320 hsw_enable_package_c8(dev_priv);
5321 }
2d66aef5
VS		 5322}
5323
6765625e
VS		 5324void intel_display_power_get(struct drm_device *dev,
5325 enum intel_display_power_domain domain)
5326{
5327 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5328 struct i915_power_domains *power_domains;
c1ca727f
ID		 5329 struct i915_power_well *power_well;
5330 int i;
6765625e 5331
83c00f55
ID		 5332 power_domains = &dev_priv->power_domains;
5333
5334 mutex_lock(&power_domains->lock);
1da51581 5335
c1ca727f
ID		 5336 for_each_power_well(i, power_well, BIT(domain), power_domains)
5337 __intel_power_well_get(dev, power_well);
1da51581 5338
ddf9c536
ID		 5339 power_domains->domain_use_count[domain]++;
5340
83c00f55 5341 mutex_unlock(&power_domains->lock);
6765625e
VS		 5342}
5343
5344void intel_display_power_put(struct drm_device *dev,
5345 enum intel_display_power_domain domain)
5346{
5347 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5348 struct i915_power_domains *power_domains;
c1ca727f
ID		 5349 struct i915_power_well *power_well;
5350 int i;
6765625e 5351
83c00f55
ID		 5352 power_domains = &dev_priv->power_domains;
5353
5354 mutex_lock(&power_domains->lock);
1da51581 5355
1da51581
ID		 5356 WARN_ON(!power_domains->domain_use_count[domain]);
5357 power_domains->domain_use_count[domain]--;
ddf9c536
ID		 5358
5359 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5360 __intel_power_well_put(dev, power_well);
1da51581 5361
83c00f55 5362 mutex_unlock(&power_domains->lock);
6765625e
VS		 5363}
5364
83c00f55 5365static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5366
5367/* Display audio driver power well request */
5368void i915_request_power_well(void)
5369{
b4ed4484
ID		 5370 struct drm_i915_private *dev_priv;
5371
a38911a3
WX		 5372 if (WARN_ON(!hsw_pwr))
5373 return;
5374
b4ed4484
ID		 5375 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5376 power_domains);
fbeeaa23 5377 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5378}
5379EXPORT_SYMBOL_GPL(i915_request_power_well);
5380
5381/* Display audio driver power well release */
5382void i915_release_power_well(void)
5383{
b4ed4484
ID		 5384 struct drm_i915_private *dev_priv;
5385
a38911a3
WX		 5386 if (WARN_ON(!hsw_pwr))
5387 return;
5388
b4ed4484
ID		 5389 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5390 power_domains);
fbeeaa23 5391 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5392}
5393EXPORT_SYMBOL_GPL(i915_release_power_well);
5394
1c2256df
ID		 5395static struct i915_power_well i9xx_always_on_power_well[] = {
5396 {
5397 .name = "always-on",
5398 .always_on = 1,
5399 .domains = POWER_DOMAIN_MASK,
5400 },
5401};
5402
c1ca727f 5403static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5404 {
5405 .name = "always-on",
5406 .always_on = 1,
5407 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5408 },
c1ca727f
ID		 5409 {
5410 .name = "display",
5411 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5412 .is_enabled = hsw_power_well_enabled,
5413 .set = hsw_set_power_well,
5414 },
5415};
5416
5417static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5418 {
5419 .name = "always-on",
5420 .always_on = 1,
5421 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5422 },
c1ca727f
ID		 5423 {
5424 .name = "display",
5425 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5426 .is_enabled = hsw_power_well_enabled,
5427 .set = hsw_set_power_well,
5428 },
5429};
5430
5431#define set_power_wells(power_domains, __power_wells) ({ \
5432 (power_domains)->power_wells = (__power_wells); \
5433 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5434})
5435
ddb642fb 5436int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5437{
5438 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5439 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5440
83c00f55 5441 mutex_init(&power_domains->lock);
a38911a3 5442
c1ca727f
ID		 5443 /*
5444 * The enabling order will be from lower to higher indexed wells,
5445 * the disabling order is reversed.
5446 */
5447 if (IS_HASWELL(dev)) {
5448 set_power_wells(power_domains, hsw_power_wells);
5449 hsw_pwr = power_domains;
5450 } else if (IS_BROADWELL(dev)) {
5451 set_power_wells(power_domains, bdw_power_wells);
5452 hsw_pwr = power_domains;
5453 } else {
1c2256df 5454 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5455 }
a38911a3
WX		 5456
5457 return 0;
5458}
5459
ddb642fb 5460void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5461{
5462 hsw_pwr = NULL;
5463}
5464
ddb642fb 5465static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5466{
5467 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5468 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5469 struct i915_power_well *power_well;
c1ca727f 5470 int i;
9cdb826c 5471
83c00f55 5472 mutex_lock(&power_domains->lock);
c1ca727f
ID		 5473 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5474 if (power_well->set)
5475 power_well->set(dev, power_well, power_well->count > 0);
5476 }
83c00f55 5477 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5478}
5479
fa42e23c
PZ		 5480/*
5481 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5482 * when not needed anymore. We have 4 registers that can request the power well
5483 * to be enabled, and it will only be disabled if none of the registers is
5484 * requesting it to be enabled.
d0d3e513 5485 */
ddb642fb 5486void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5489
fa42e23c 5490 /* For now, we need the power well to be always enabled. */
baa70707 5491 intel_display_set_init_power(dev, true);
ddb642fb 5492 intel_power_domains_resume(dev);
d0d3e513 5493
f7243ac9
ID		 5494 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5495 return;
5496
fa42e23c
PZ		 5497 /* We're taking over the BIOS, so clear any requests made by it since
5498 * the driver is in charge now. */
6aedd1f5 5499 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5500 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5501}
5502
c67a470b
PZ		 5503/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5504void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5505{
5506 hsw_disable_package_c8(dev_priv);
5507}
5508
5509void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5510{
5511 hsw_enable_package_c8(dev_priv);
5512}
5513
8a187455
PZ		 5514void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5515{
5516 struct drm_device *dev = dev_priv->dev;
5517 struct device *device = &dev->pdev->dev;
5518
5519 if (!HAS_RUNTIME_PM(dev))
5520 return;
5521
5522 pm_runtime_get_sync(device);
5523 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5524}
5525
5526void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5527{
5528 struct drm_device *dev = dev_priv->dev;
5529 struct device *device = &dev->pdev->dev;
5530
5531 if (!HAS_RUNTIME_PM(dev))
5532 return;
5533
5534 pm_runtime_mark_last_busy(device);
5535 pm_runtime_put_autosuspend(device);
5536}
5537
5538void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5539{
5540 struct drm_device *dev = dev_priv->dev;
5541 struct device *device = &dev->pdev->dev;
5542
5543 dev_priv->pm.suspended = false;
5544
5545 if (!HAS_RUNTIME_PM(dev))
5546 return;
5547
5548 pm_runtime_set_active(device);
5549
5550 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5551 pm_runtime_mark_last_busy(device);
5552 pm_runtime_use_autosuspend(device);
5553}
5554
5555void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5556{
5557 struct drm_device *dev = dev_priv->dev;
5558 struct device *device = &dev->pdev->dev;
5559
5560 if (!HAS_RUNTIME_PM(dev))
5561 return;
5562
5563 /* Make sure we're not suspended first. */
5564 pm_runtime_get_sync(device);
5565 pm_runtime_disable(device);
5566}
5567
1fa61106
ED		 5568/* Set up chip specific power management-related functions */
5569void intel_init_pm(struct drm_device *dev)
5570{
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5572
3a77c4c4 5573 if (HAS_FBC(dev)) {
40045465 5574 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 5575 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 5576 dev_priv->display.enable_fbc = gen7_enable_fbc;
5577 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5578 } else if (INTEL_INFO(dev)->gen >= 5) {
5579 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5580 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 5581 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5582 } else if (IS_GM45(dev)) {
5583 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5584 dev_priv->display.enable_fbc = g4x_enable_fbc;
5585 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 5586 } else {
1fa61106
ED		 5587 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5588 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5589 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 5590
5591 /* This value was pulled out of someone's hat */
5592 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 5593 }
1fa61106
ED		 5594 }
5595
c921aba8
DV		 5596 /* For cxsr */
5597 if (IS_PINEVIEW(dev))
5598 i915_pineview_get_mem_freq(dev);
5599 else if (IS_GEN5(dev))
5600 i915_ironlake_get_mem_freq(dev);
5601
1fa61106
ED		 5602 /* For FIFO watermark updates */
5603 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5604 intel_setup_wm_latency(dev);
5605
bd602544
VS		 5606 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5607 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5608 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
5609 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
5610 dev_priv->display.update_wm = ilk_update_wm;
5611 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
5612 } else {
5613 DRM_DEBUG_KMS("Failed to read display plane latency. "
5614 "Disable CxSR\n");
5615 }
5616
5617 if (IS_GEN5(dev))
1fa61106 5618 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 5619 else if (IS_GEN6(dev))
1fa61106 5620 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 5621 else if (IS_IVYBRIDGE(dev))
1fa61106 5622 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 5623 else if (IS_HASWELL(dev))
cad2a2d7 5624 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 5625 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 5626 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 5627 } else if (IS_VALLEYVIEW(dev)) {
5628 dev_priv->display.update_wm = valleyview_update_wm;
5629 dev_priv->display.init_clock_gating =
5630 valleyview_init_clock_gating;
1fa61106
ED		 5631 } else if (IS_PINEVIEW(dev)) {
5632 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5633 dev_priv->is_ddr3,
5634 dev_priv->fsb_freq,
5635 dev_priv->mem_freq)) {
5636 DRM_INFO("failed to find known CxSR latency "
5637 "(found ddr%s fsb freq %d, mem freq %d), "
5638 "disabling CxSR\n",
5639 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5640 dev_priv->fsb_freq, dev_priv->mem_freq);
5641 /* Disable CxSR and never update its watermark again */
5642 pineview_disable_cxsr(dev);
5643 dev_priv->display.update_wm = NULL;
5644 } else
5645 dev_priv->display.update_wm = pineview_update_wm;
5646 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5647 } else if (IS_G4X(dev)) {
5648 dev_priv->display.update_wm = g4x_update_wm;
5649 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5650 } else if (IS_GEN4(dev)) {
5651 dev_priv->display.update_wm = i965_update_wm;
5652 if (IS_CRESTLINE(dev))
5653 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5654 else if (IS_BROADWATER(dev))
5655 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5656 } else if (IS_GEN3(dev)) {
5657 dev_priv->display.update_wm = i9xx_update_wm;
5658 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5659 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 5660 } else if (IS_GEN2(dev)) {
5661 if (INTEL_INFO(dev)->num_pipes == 1) {
5662 dev_priv->display.update_wm = i845_update_wm;
1fa61106 5663 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 5664 } else {
5665 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 5666 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 5667 }
5668
5669 if (IS_I85X(dev) || IS_I865G(dev))
5670 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5671 else
5672 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5673 } else {
5674 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 5675 }
5676}
5677
42c0526c
BW		 5678int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5679{
4fc688ce 5680 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5681
5682 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5683 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5684 return -EAGAIN;
5685 }
5686
5687 I915_WRITE(GEN6_PCODE_DATA, *val);
5688 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5689
5690 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5691 500)) {
5692 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5693 return -ETIMEDOUT;
5694 }
5695
5696 *val = I915_READ(GEN6_PCODE_DATA);
5697 I915_WRITE(GEN6_PCODE_DATA, 0);
5698
5699 return 0;
5700}
5701
5702int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5703{
4fc688ce 5704 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5705
5706 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5707 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5708 return -EAGAIN;
5709 }
5710
5711 I915_WRITE(GEN6_PCODE_DATA, val);
5712 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5713
5714 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5715 500)) {
5716 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5717 return -ETIMEDOUT;
5718 }
5719
5720 I915_WRITE(GEN6_PCODE_DATA, 0);
5721
5722 return 0;
5723}
a0e4e199 5724
2ec3815f 5725int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 5726{
07ab118b 5727 int div;
855ba3be 5728
07ab118b 5729 /* 4 x czclk */
2ec3815f 5730 switch (dev_priv->mem_freq) {
855ba3be 5731 case 800:
07ab118b 5732 div = 10;
855ba3be
JB		 5733 break;
5734 case 1066:
07ab118b 5735 div = 12;
855ba3be
JB		 5736 break;
5737 case 1333:
07ab118b 5738 div = 16;
855ba3be
JB		 5739 break;
5740 default:
5741 return -1;
5742 }
5743
2ec3815f 5744 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 5745}
5746
2ec3815f 5747int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 5748{
07ab118b 5749 int mul;
855ba3be 5750
07ab118b 5751 /* 4 x czclk */
2ec3815f 5752 switch (dev_priv->mem_freq) {
855ba3be 5753 case 800:
07ab118b 5754 mul = 10;
855ba3be
JB		 5755 break;
5756 case 1066:
07ab118b 5757 mul = 12;
855ba3be
JB		 5758 break;
5759 case 1333:
07ab118b 5760 mul = 16;
855ba3be
JB		 5761 break;
5762 default:
5763 return -1;
5764 }
5765
2ec3815f 5766 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 5767}
5768
f742a552 5769void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 5770{
5771 struct drm_i915_private *dev_priv = dev->dev_private;
5772
f742a552
DV		 5773 mutex_init(&dev_priv->rps.hw_lock);
5774
5775 mutex_init(&dev_priv->pc8.lock);
5776 dev_priv->pc8.requirements_met = false;
5777 dev_priv->pc8.gpu_idle = false;
5778 dev_priv->pc8.irqs_disabled = false;
5779 dev_priv->pc8.enabled = false;
5780 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
5781 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
907b28c5
CW		 5782 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5783 intel_gen6_powersave_work);
5784}
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