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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
f9dcb0df | 33 | #include <linux/vgaarb.h> |
f4db9321 | 34 | #include <drm/i915_powerwell.h> |
8a187455 | 35 | #include <linux/pm_runtime.h> |
85208be0 | 36 | |
dc39fff7 BW |
37 | /** |
38 | * RC6 is a special power stage which allows the GPU to enter an very | |
39 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
40 | * stage is entered automatically when the GPU is idle when RC6 support is | |
41 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
42 | * | |
43 | * There are different RC6 modes available in Intel GPU, which differentiate | |
44 | * among each other with the latency required to enter and leave RC6 and | |
45 | * voltage consumed by the GPU in different states. | |
46 | * | |
47 | * The combination of the following flags define which states GPU is allowed | |
48 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
49 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
50 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
51 | * which brings the most power savings; deeper states save more power, but | |
52 | * require higher latency to switch to and wake up. | |
53 | */ | |
54 | #define INTEL_RC6_ENABLE (1<<0) | |
55 | #define INTEL_RC6p_ENABLE (1<<1) | |
56 | #define INTEL_RC6pp_ENABLE (1<<2) | |
57 | ||
f6750b3c ED |
58 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
59 | * framebuffer contents in-memory, aiming at reducing the required bandwidth | |
60 | * during in-memory transfers and, therefore, reduce the power packet. | |
85208be0 | 61 | * |
f6750b3c ED |
62 | * The benefits of FBC are mostly visible with solid backgrounds and |
63 | * variation-less patterns. | |
85208be0 | 64 | * |
f6750b3c ED |
65 | * FBC-related functionality can be enabled by the means of the |
66 | * i915.i915_enable_fbc parameter | |
85208be0 ED |
67 | */ |
68 | ||
da2078cd DL |
69 | static void gen9_init_clock_gating(struct drm_device *dev) |
70 | { | |
71 | } | |
72 | ||
1fa61106 | 73 | static void i8xx_disable_fbc(struct drm_device *dev) |
85208be0 ED |
74 | { |
75 | struct drm_i915_private *dev_priv = dev->dev_private; | |
76 | u32 fbc_ctl; | |
77 | ||
78 | /* Disable compression */ | |
79 | fbc_ctl = I915_READ(FBC_CONTROL); | |
80 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
81 | return; | |
82 | ||
83 | fbc_ctl &= ~FBC_CTL_EN; | |
84 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
85 | ||
86 | /* Wait for compressing bit to clear */ | |
87 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
88 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
89 | return; | |
90 | } | |
91 | ||
92 | DRM_DEBUG_KMS("disabled FBC\n"); | |
93 | } | |
94 | ||
993495ae | 95 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
96 | { |
97 | struct drm_device *dev = crtc->dev; | |
98 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 99 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 100 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 ED |
101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
102 | int cfb_pitch; | |
7f2cf220 | 103 | int i; |
159f9875 | 104 | u32 fbc_ctl; |
85208be0 | 105 | |
5c3fe8b0 | 106 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
85208be0 ED |
107 | if (fb->pitches[0] < cfb_pitch) |
108 | cfb_pitch = fb->pitches[0]; | |
109 | ||
42a430f5 VS |
110 | /* FBC_CTL wants 32B or 64B units */ |
111 | if (IS_GEN2(dev)) | |
112 | cfb_pitch = (cfb_pitch / 32) - 1; | |
113 | else | |
114 | cfb_pitch = (cfb_pitch / 64) - 1; | |
85208be0 ED |
115 | |
116 | /* Clear old tags */ | |
117 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
118 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
119 | ||
159f9875 VS |
120 | if (IS_GEN4(dev)) { |
121 | u32 fbc_ctl2; | |
122 | ||
123 | /* Set it up... */ | |
124 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
7f2cf220 | 125 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
159f9875 VS |
126 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
127 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
128 | } | |
85208be0 ED |
129 | |
130 | /* enable it... */ | |
993495ae VS |
131 | fbc_ctl = I915_READ(FBC_CONTROL); |
132 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
133 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
85208be0 ED |
134 | if (IS_I945GM(dev)) |
135 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
136 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
85208be0 ED |
137 | fbc_ctl |= obj->fence_reg; |
138 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
139 | ||
5cd5410e | 140 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
84f44ce7 | 141 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
85208be0 ED |
142 | } |
143 | ||
1fa61106 | 144 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
145 | { |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | ||
148 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
149 | } | |
150 | ||
993495ae | 151 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
152 | { |
153 | struct drm_device *dev = crtc->dev; | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 155 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 156 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 | 157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
85208be0 ED |
158 | u32 dpfc_ctl; |
159 | ||
3fa2e0ee VS |
160 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
161 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
162 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
163 | else | |
164 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
85208be0 | 165 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
85208be0 | 166 | |
85208be0 ED |
167 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
168 | ||
169 | /* enable it... */ | |
fe74c1a5 | 170 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
85208be0 | 171 | |
84f44ce7 | 172 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
173 | } |
174 | ||
1fa61106 | 175 | static void g4x_disable_fbc(struct drm_device *dev) |
85208be0 ED |
176 | { |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
178 | u32 dpfc_ctl; | |
179 | ||
180 | /* Disable compression */ | |
181 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
182 | if (dpfc_ctl & DPFC_CTL_EN) { | |
183 | dpfc_ctl &= ~DPFC_CTL_EN; | |
184 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
185 | ||
186 | DRM_DEBUG_KMS("disabled FBC\n"); | |
187 | } | |
188 | } | |
189 | ||
1fa61106 | 190 | static bool g4x_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
191 | { |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | ||
194 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
195 | } | |
196 | ||
197 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
198 | { | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | u32 blt_ecoskpd; | |
201 | ||
202 | /* Make sure blitter notifies FBC of writes */ | |
940aece4 D |
203 | |
204 | /* Blitter is part of Media powerwell on VLV. No impact of | |
205 | * his param in other platforms for now */ | |
206 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); | |
c8d9a590 | 207 | |
85208be0 ED |
208 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
209 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
210 | GEN6_BLITTER_LOCK_SHIFT; | |
211 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
212 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
213 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
214 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
215 | GEN6_BLITTER_LOCK_SHIFT); | |
216 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
217 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
c8d9a590 | 218 | |
940aece4 | 219 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
85208be0 ED |
220 | } |
221 | ||
993495ae | 222 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
223 | { |
224 | struct drm_device *dev = crtc->dev; | |
225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 226 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 227 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 | 228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
85208be0 ED |
229 | u32 dpfc_ctl; |
230 | ||
46f3dab9 | 231 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
3fa2e0ee | 232 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
5e59f717 BW |
233 | dev_priv->fbc.threshold++; |
234 | ||
235 | switch (dev_priv->fbc.threshold) { | |
236 | case 4: | |
237 | case 3: | |
238 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
239 | break; | |
240 | case 2: | |
3fa2e0ee | 241 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
242 | break; |
243 | case 1: | |
3fa2e0ee | 244 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
245 | break; |
246 | } | |
d629336b VS |
247 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
248 | if (IS_GEN5(dev)) | |
249 | dpfc_ctl |= obj->fence_reg; | |
85208be0 | 250 | |
85208be0 | 251 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
f343c5f6 | 252 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
85208be0 ED |
253 | /* enable it... */ |
254 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
255 | ||
256 | if (IS_GEN6(dev)) { | |
257 | I915_WRITE(SNB_DPFC_CTL_SA, | |
258 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
259 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
260 | sandybridge_blit_fbc_update(dev); | |
261 | } | |
262 | ||
84f44ce7 | 263 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
264 | } |
265 | ||
1fa61106 | 266 | static void ironlake_disable_fbc(struct drm_device *dev) |
85208be0 ED |
267 | { |
268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
269 | u32 dpfc_ctl; | |
270 | ||
271 | /* Disable compression */ | |
272 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
273 | if (dpfc_ctl & DPFC_CTL_EN) { | |
274 | dpfc_ctl &= ~DPFC_CTL_EN; | |
275 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
276 | ||
277 | DRM_DEBUG_KMS("disabled FBC\n"); | |
278 | } | |
279 | } | |
280 | ||
1fa61106 | 281 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
282 | { |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
284 | ||
285 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
286 | } | |
287 | ||
993495ae | 288 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
abe959c7 RV |
289 | { |
290 | struct drm_device *dev = crtc->dev; | |
291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 292 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 293 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
abe959c7 | 294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3fa2e0ee | 295 | u32 dpfc_ctl; |
abe959c7 | 296 | |
3fa2e0ee VS |
297 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
298 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
5e59f717 BW |
299 | dev_priv->fbc.threshold++; |
300 | ||
301 | switch (dev_priv->fbc.threshold) { | |
302 | case 4: | |
303 | case 3: | |
304 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
305 | break; | |
306 | case 2: | |
3fa2e0ee | 307 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
308 | break; |
309 | case 1: | |
3fa2e0ee | 310 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
311 | break; |
312 | } | |
313 | ||
3fa2e0ee VS |
314 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
315 | ||
da46f936 RV |
316 | if (dev_priv->fbc.false_color) |
317 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
318 | ||
3fa2e0ee | 319 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
abe959c7 | 320 | |
891348b2 | 321 | if (IS_IVYBRIDGE(dev)) { |
7dd23ba0 | 322 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
2adb6db8 VS |
323 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
324 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
325 | ILK_FBCQ_DIS); | |
28554164 | 326 | } else { |
2adb6db8 | 327 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
8f670bb1 VS |
328 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
329 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
330 | HSW_FBCQ_DIS); | |
891348b2 | 331 | } |
b74ea102 | 332 | |
abe959c7 RV |
333 | I915_WRITE(SNB_DPFC_CTL_SA, |
334 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
335 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
336 | ||
337 | sandybridge_blit_fbc_update(dev); | |
338 | ||
b19870ee | 339 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
abe959c7 RV |
340 | } |
341 | ||
85208be0 ED |
342 | bool intel_fbc_enabled(struct drm_device *dev) |
343 | { | |
344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
345 | ||
346 | if (!dev_priv->display.fbc_enabled) | |
347 | return false; | |
348 | ||
349 | return dev_priv->display.fbc_enabled(dev); | |
350 | } | |
351 | ||
c5ad011d RV |
352 | void gen8_fbc_sw_flush(struct drm_device *dev, u32 value) |
353 | { | |
354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
355 | ||
356 | if (!IS_GEN8(dev)) | |
357 | return; | |
358 | ||
359 | I915_WRITE(MSG_FBC_REND_STATE, value); | |
360 | } | |
361 | ||
85208be0 ED |
362 | static void intel_fbc_work_fn(struct work_struct *__work) |
363 | { | |
364 | struct intel_fbc_work *work = | |
365 | container_of(to_delayed_work(__work), | |
366 | struct intel_fbc_work, work); | |
367 | struct drm_device *dev = work->crtc->dev; | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369 | ||
370 | mutex_lock(&dev->struct_mutex); | |
5c3fe8b0 | 371 | if (work == dev_priv->fbc.fbc_work) { |
85208be0 ED |
372 | /* Double check that we haven't switched fb without cancelling |
373 | * the prior work. | |
374 | */ | |
f4510a27 | 375 | if (work->crtc->primary->fb == work->fb) { |
993495ae | 376 | dev_priv->display.enable_fbc(work->crtc); |
85208be0 | 377 | |
5c3fe8b0 | 378 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
f4510a27 | 379 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
5c3fe8b0 | 380 | dev_priv->fbc.y = work->crtc->y; |
85208be0 ED |
381 | } |
382 | ||
5c3fe8b0 | 383 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
384 | } |
385 | mutex_unlock(&dev->struct_mutex); | |
386 | ||
387 | kfree(work); | |
388 | } | |
389 | ||
390 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
391 | { | |
5c3fe8b0 | 392 | if (dev_priv->fbc.fbc_work == NULL) |
85208be0 ED |
393 | return; |
394 | ||
395 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
396 | ||
397 | /* Synchronisation is provided by struct_mutex and checking of | |
5c3fe8b0 | 398 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
85208be0 ED |
399 | * entirely asynchronously. |
400 | */ | |
5c3fe8b0 | 401 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
85208be0 | 402 | /* tasklet was killed before being run, clean up */ |
5c3fe8b0 | 403 | kfree(dev_priv->fbc.fbc_work); |
85208be0 ED |
404 | |
405 | /* Mark the work as no longer wanted so that if it does | |
406 | * wake-up (because the work was already running and waiting | |
407 | * for our mutex), it will discover that is no longer | |
408 | * necessary to run. | |
409 | */ | |
5c3fe8b0 | 410 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
411 | } |
412 | ||
993495ae | 413 | static void intel_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
414 | { |
415 | struct intel_fbc_work *work; | |
416 | struct drm_device *dev = crtc->dev; | |
417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
418 | ||
419 | if (!dev_priv->display.enable_fbc) | |
420 | return; | |
421 | ||
422 | intel_cancel_fbc_work(dev_priv); | |
423 | ||
b14c5679 | 424 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
85208be0 | 425 | if (work == NULL) { |
6cdcb5e7 | 426 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
993495ae | 427 | dev_priv->display.enable_fbc(crtc); |
85208be0 ED |
428 | return; |
429 | } | |
430 | ||
431 | work->crtc = crtc; | |
f4510a27 | 432 | work->fb = crtc->primary->fb; |
85208be0 ED |
433 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
434 | ||
5c3fe8b0 | 435 | dev_priv->fbc.fbc_work = work; |
85208be0 | 436 | |
85208be0 ED |
437 | /* Delay the actual enabling to let pageflipping cease and the |
438 | * display to settle before starting the compression. Note that | |
439 | * this delay also serves a second purpose: it allows for a | |
440 | * vblank to pass after disabling the FBC before we attempt | |
441 | * to modify the control registers. | |
442 | * | |
443 | * A more complicated solution would involve tracking vblanks | |
444 | * following the termination of the page-flipping sequence | |
445 | * and indeed performing the enable as a co-routine and not | |
446 | * waiting synchronously upon the vblank. | |
7457d617 DL |
447 | * |
448 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
85208be0 ED |
449 | */ |
450 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
451 | } | |
452 | ||
453 | void intel_disable_fbc(struct drm_device *dev) | |
454 | { | |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
456 | ||
457 | intel_cancel_fbc_work(dev_priv); | |
458 | ||
459 | if (!dev_priv->display.disable_fbc) | |
460 | return; | |
461 | ||
462 | dev_priv->display.disable_fbc(dev); | |
5c3fe8b0 | 463 | dev_priv->fbc.plane = -1; |
85208be0 ED |
464 | } |
465 | ||
29ebf90f CW |
466 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
467 | enum no_fbc_reason reason) | |
468 | { | |
469 | if (dev_priv->fbc.no_fbc_reason == reason) | |
470 | return false; | |
471 | ||
472 | dev_priv->fbc.no_fbc_reason = reason; | |
473 | return true; | |
474 | } | |
475 | ||
85208be0 ED |
476 | /** |
477 | * intel_update_fbc - enable/disable FBC as needed | |
478 | * @dev: the drm_device | |
479 | * | |
480 | * Set up the framebuffer compression hardware at mode set time. We | |
481 | * enable it if possible: | |
482 | * - plane A only (on pre-965) | |
483 | * - no pixel mulitply/line duplication | |
484 | * - no alpha buffer discard | |
485 | * - no dual wide | |
f85da868 | 486 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
85208be0 ED |
487 | * |
488 | * We can't assume that any compression will take place (worst case), | |
489 | * so the compressed buffer has to be the same size as the uncompressed | |
490 | * one. It also must reside (along with the line length buffer) in | |
491 | * stolen memory. | |
492 | * | |
493 | * We need to enable/disable FBC on a global basis. | |
494 | */ | |
495 | void intel_update_fbc(struct drm_device *dev) | |
496 | { | |
497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
499 | struct intel_crtc *intel_crtc; | |
500 | struct drm_framebuffer *fb; | |
85208be0 | 501 | struct drm_i915_gem_object *obj; |
ef644fda | 502 | const struct drm_display_mode *adjusted_mode; |
37327abd | 503 | unsigned int max_width, max_height; |
85208be0 | 504 | |
3a77c4c4 | 505 | if (!HAS_FBC(dev)) { |
29ebf90f | 506 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
85208be0 | 507 | return; |
29ebf90f | 508 | } |
85208be0 | 509 | |
d330a953 | 510 | if (!i915.powersave) { |
29ebf90f CW |
511 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
512 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 | 513 | return; |
29ebf90f | 514 | } |
85208be0 ED |
515 | |
516 | /* | |
517 | * If FBC is already on, we just have to verify that we can | |
518 | * keep it that way... | |
519 | * Need to disable if: | |
520 | * - more than one pipe is active | |
521 | * - changing FBC params (stride, fence, mode) | |
522 | * - new fb is too large to fit in compressed buffer | |
523 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
524 | */ | |
70e1e0ec | 525 | for_each_crtc(dev, tmp_crtc) { |
3490ea5d | 526 | if (intel_crtc_active(tmp_crtc) && |
4c445e0e | 527 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
85208be0 | 528 | if (crtc) { |
29ebf90f CW |
529 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
530 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
85208be0 ED |
531 | goto out_disable; |
532 | } | |
533 | crtc = tmp_crtc; | |
534 | } | |
535 | } | |
536 | ||
f4510a27 | 537 | if (!crtc || crtc->primary->fb == NULL) { |
29ebf90f CW |
538 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
539 | DRM_DEBUG_KMS("no output, disabling\n"); | |
85208be0 ED |
540 | goto out_disable; |
541 | } | |
542 | ||
543 | intel_crtc = to_intel_crtc(crtc); | |
f4510a27 | 544 | fb = crtc->primary->fb; |
2ff8fde1 | 545 | obj = intel_fb_obj(fb); |
ef644fda | 546 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
85208be0 | 547 | |
0368920e | 548 | if (i915.enable_fbc < 0) { |
29ebf90f CW |
549 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
550 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
8a5729a3 | 551 | goto out_disable; |
85208be0 | 552 | } |
d330a953 | 553 | if (!i915.enable_fbc) { |
29ebf90f CW |
554 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
555 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 ED |
556 | goto out_disable; |
557 | } | |
ef644fda VS |
558 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
559 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
29ebf90f CW |
560 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
561 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
562 | "disabling\n"); | |
85208be0 ED |
563 | goto out_disable; |
564 | } | |
f85da868 | 565 | |
032843a5 DS |
566 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { |
567 | max_width = 4096; | |
568 | max_height = 4096; | |
569 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
37327abd VS |
570 | max_width = 4096; |
571 | max_height = 2048; | |
f85da868 | 572 | } else { |
37327abd VS |
573 | max_width = 2048; |
574 | max_height = 1536; | |
f85da868 | 575 | } |
37327abd VS |
576 | if (intel_crtc->config.pipe_src_w > max_width || |
577 | intel_crtc->config.pipe_src_h > max_height) { | |
29ebf90f CW |
578 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
579 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
85208be0 ED |
580 | goto out_disable; |
581 | } | |
8f94d24b | 582 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
c5a44aa0 | 583 | intel_crtc->plane != PLANE_A) { |
29ebf90f | 584 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
c5a44aa0 | 585 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
85208be0 ED |
586 | goto out_disable; |
587 | } | |
588 | ||
589 | /* The use of a CPU fence is mandatory in order to detect writes | |
590 | * by the CPU to the scanout and trigger updates to the FBC. | |
591 | */ | |
592 | if (obj->tiling_mode != I915_TILING_X || | |
593 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
29ebf90f CW |
594 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
595 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
85208be0 ED |
596 | goto out_disable; |
597 | } | |
48404c1e SJ |
598 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
599 | to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) { | |
600 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) | |
601 | DRM_DEBUG_KMS("Rotation unsupported, disabling\n"); | |
602 | goto out_disable; | |
603 | } | |
85208be0 ED |
604 | |
605 | /* If the kernel debugger is active, always disable compression */ | |
606 | if (in_dbg_master()) | |
607 | goto out_disable; | |
608 | ||
2ff8fde1 | 609 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, |
5e59f717 | 610 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
29ebf90f CW |
611 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
612 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
11be49eb CW |
613 | goto out_disable; |
614 | } | |
615 | ||
85208be0 ED |
616 | /* If the scanout has not changed, don't modify the FBC settings. |
617 | * Note that we make the fundamental assumption that the fb->obj | |
618 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
619 | * without first being decoupled from the scanout and FBC disabled. | |
620 | */ | |
5c3fe8b0 BW |
621 | if (dev_priv->fbc.plane == intel_crtc->plane && |
622 | dev_priv->fbc.fb_id == fb->base.id && | |
623 | dev_priv->fbc.y == crtc->y) | |
85208be0 ED |
624 | return; |
625 | ||
626 | if (intel_fbc_enabled(dev)) { | |
627 | /* We update FBC along two paths, after changing fb/crtc | |
628 | * configuration (modeswitching) and after page-flipping | |
629 | * finishes. For the latter, we know that not only did | |
630 | * we disable the FBC at the start of the page-flip | |
631 | * sequence, but also more than one vblank has passed. | |
632 | * | |
633 | * For the former case of modeswitching, it is possible | |
634 | * to switch between two FBC valid configurations | |
635 | * instantaneously so we do need to disable the FBC | |
636 | * before we can modify its control registers. We also | |
637 | * have to wait for the next vblank for that to take | |
638 | * effect. However, since we delay enabling FBC we can | |
639 | * assume that a vblank has passed since disabling and | |
640 | * that we can safely alter the registers in the deferred | |
641 | * callback. | |
642 | * | |
643 | * In the scenario that we go from a valid to invalid | |
644 | * and then back to valid FBC configuration we have | |
645 | * no strict enforcement that a vblank occurred since | |
646 | * disabling the FBC. However, along all current pipe | |
647 | * disabling paths we do need to wait for a vblank at | |
648 | * some point. And we wait before enabling FBC anyway. | |
649 | */ | |
650 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
651 | intel_disable_fbc(dev); | |
652 | } | |
653 | ||
993495ae | 654 | intel_enable_fbc(crtc); |
29ebf90f | 655 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
85208be0 ED |
656 | return; |
657 | ||
658 | out_disable: | |
659 | /* Multiple disables should be harmless */ | |
660 | if (intel_fbc_enabled(dev)) { | |
661 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
662 | intel_disable_fbc(dev); | |
663 | } | |
11be49eb | 664 | i915_gem_stolen_cleanup_compression(dev); |
85208be0 ED |
665 | } |
666 | ||
c921aba8 DV |
667 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
668 | { | |
50227e1c | 669 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
670 | u32 tmp; |
671 | ||
672 | tmp = I915_READ(CLKCFG); | |
673 | ||
674 | switch (tmp & CLKCFG_FSB_MASK) { | |
675 | case CLKCFG_FSB_533: | |
676 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
677 | break; | |
678 | case CLKCFG_FSB_800: | |
679 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
680 | break; | |
681 | case CLKCFG_FSB_667: | |
682 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
683 | break; | |
684 | case CLKCFG_FSB_400: | |
685 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
686 | break; | |
687 | } | |
688 | ||
689 | switch (tmp & CLKCFG_MEM_MASK) { | |
690 | case CLKCFG_MEM_533: | |
691 | dev_priv->mem_freq = 533; | |
692 | break; | |
693 | case CLKCFG_MEM_667: | |
694 | dev_priv->mem_freq = 667; | |
695 | break; | |
696 | case CLKCFG_MEM_800: | |
697 | dev_priv->mem_freq = 800; | |
698 | break; | |
699 | } | |
700 | ||
701 | /* detect pineview DDR3 setting */ | |
702 | tmp = I915_READ(CSHRDDR3CTL); | |
703 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
704 | } | |
705 | ||
706 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
707 | { | |
50227e1c | 708 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
709 | u16 ddrpll, csipll; |
710 | ||
711 | ddrpll = I915_READ16(DDRMPLL1); | |
712 | csipll = I915_READ16(CSIPLL0); | |
713 | ||
714 | switch (ddrpll & 0xff) { | |
715 | case 0xc: | |
716 | dev_priv->mem_freq = 800; | |
717 | break; | |
718 | case 0x10: | |
719 | dev_priv->mem_freq = 1066; | |
720 | break; | |
721 | case 0x14: | |
722 | dev_priv->mem_freq = 1333; | |
723 | break; | |
724 | case 0x18: | |
725 | dev_priv->mem_freq = 1600; | |
726 | break; | |
727 | default: | |
728 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
729 | ddrpll & 0xff); | |
730 | dev_priv->mem_freq = 0; | |
731 | break; | |
732 | } | |
733 | ||
20e4d407 | 734 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
735 | |
736 | switch (csipll & 0x3ff) { | |
737 | case 0x00c: | |
738 | dev_priv->fsb_freq = 3200; | |
739 | break; | |
740 | case 0x00e: | |
741 | dev_priv->fsb_freq = 3733; | |
742 | break; | |
743 | case 0x010: | |
744 | dev_priv->fsb_freq = 4266; | |
745 | break; | |
746 | case 0x012: | |
747 | dev_priv->fsb_freq = 4800; | |
748 | break; | |
749 | case 0x014: | |
750 | dev_priv->fsb_freq = 5333; | |
751 | break; | |
752 | case 0x016: | |
753 | dev_priv->fsb_freq = 5866; | |
754 | break; | |
755 | case 0x018: | |
756 | dev_priv->fsb_freq = 6400; | |
757 | break; | |
758 | default: | |
759 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
760 | csipll & 0x3ff); | |
761 | dev_priv->fsb_freq = 0; | |
762 | break; | |
763 | } | |
764 | ||
765 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 766 | dev_priv->ips.c_m = 0; |
c921aba8 | 767 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 768 | dev_priv->ips.c_m = 1; |
c921aba8 | 769 | } else { |
20e4d407 | 770 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
771 | } |
772 | } | |
773 | ||
b445e3b0 ED |
774 | static const struct cxsr_latency cxsr_latency_table[] = { |
775 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
776 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
777 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
778 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
779 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
780 | ||
781 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
782 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
783 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
784 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
785 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
786 | ||
787 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
788 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
789 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
790 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
791 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
792 | ||
793 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
794 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
795 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
796 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
797 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
798 | ||
799 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
800 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
801 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
802 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
803 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
804 | ||
805 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
806 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
807 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
808 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
809 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
810 | }; | |
811 | ||
63c62275 | 812 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
813 | int is_ddr3, |
814 | int fsb, | |
815 | int mem) | |
816 | { | |
817 | const struct cxsr_latency *latency; | |
818 | int i; | |
819 | ||
820 | if (fsb == 0 || mem == 0) | |
821 | return NULL; | |
822 | ||
823 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
824 | latency = &cxsr_latency_table[i]; | |
825 | if (is_desktop == latency->is_desktop && | |
826 | is_ddr3 == latency->is_ddr3 && | |
827 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
828 | return latency; | |
829 | } | |
830 | ||
831 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
832 | ||
833 | return NULL; | |
834 | } | |
835 | ||
5209b1f4 | 836 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 837 | { |
5209b1f4 ID |
838 | struct drm_device *dev = dev_priv->dev; |
839 | u32 val; | |
b445e3b0 | 840 | |
5209b1f4 ID |
841 | if (IS_VALLEYVIEW(dev)) { |
842 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
843 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { | |
844 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
845 | } else if (IS_PINEVIEW(dev)) { | |
846 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
847 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
848 | I915_WRITE(DSPFW3, val); | |
849 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
850 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
851 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
852 | I915_WRITE(FW_BLC_SELF, val); | |
853 | } else if (IS_I915GM(dev)) { | |
854 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
855 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
856 | I915_WRITE(INSTPM, val); | |
857 | } else { | |
858 | return; | |
859 | } | |
b445e3b0 | 860 | |
5209b1f4 ID |
861 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
862 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
863 | } |
864 | ||
865 | /* | |
866 | * Latency for FIFO fetches is dependent on several factors: | |
867 | * - memory configuration (speed, channels) | |
868 | * - chipset | |
869 | * - current MCH state | |
870 | * It can be fairly high in some situations, so here we assume a fairly | |
871 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
872 | * set this value too high, the FIFO will fetch frequently to stay full) | |
873 | * and power consumption (set it too low to save power and we might see | |
874 | * FIFO underruns and display "flicker"). | |
875 | * | |
876 | * A value of 5us seems to be a good balance; safe for very low end | |
877 | * platforms but not overly aggressive on lower latency configs. | |
878 | */ | |
5aef6003 | 879 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 880 | |
1fa61106 | 881 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
882 | { |
883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
884 | uint32_t dsparb = I915_READ(DSPARB); | |
885 | int size; | |
886 | ||
887 | size = dsparb & 0x7f; | |
888 | if (plane) | |
889 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
890 | ||
891 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
892 | plane ? "B" : "A", size); | |
893 | ||
894 | return size; | |
895 | } | |
896 | ||
feb56b93 | 897 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
898 | { |
899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
900 | uint32_t dsparb = I915_READ(DSPARB); | |
901 | int size; | |
902 | ||
903 | size = dsparb & 0x1ff; | |
904 | if (plane) | |
905 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
906 | size >>= 1; /* Convert to cachelines */ | |
907 | ||
908 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
909 | plane ? "B" : "A", size); | |
910 | ||
911 | return size; | |
912 | } | |
913 | ||
1fa61106 | 914 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
915 | { |
916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
917 | uint32_t dsparb = I915_READ(DSPARB); | |
918 | int size; | |
919 | ||
920 | size = dsparb & 0x7f; | |
921 | size >>= 2; /* Convert to cachelines */ | |
922 | ||
923 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
924 | plane ? "B" : "A", | |
925 | size); | |
926 | ||
927 | return size; | |
928 | } | |
929 | ||
b445e3b0 ED |
930 | /* Pineview has different values for various configs */ |
931 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
932 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
933 | .max_wm = PINEVIEW_MAX_WM, | |
934 | .default_wm = PINEVIEW_DFT_WM, | |
935 | .guard_size = PINEVIEW_GUARD_WM, | |
936 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
937 | }; |
938 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
939 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
940 | .max_wm = PINEVIEW_MAX_WM, | |
941 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
942 | .guard_size = PINEVIEW_GUARD_WM, | |
943 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
944 | }; |
945 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
946 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
947 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
948 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
949 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
950 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
951 | }; |
952 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
953 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
954 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
955 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
956 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
957 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
958 | }; |
959 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
960 | .fifo_size = G4X_FIFO_SIZE, |
961 | .max_wm = G4X_MAX_WM, | |
962 | .default_wm = G4X_MAX_WM, | |
963 | .guard_size = 2, | |
964 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
965 | }; |
966 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
967 | .fifo_size = I965_CURSOR_FIFO, |
968 | .max_wm = I965_CURSOR_MAX_WM, | |
969 | .default_wm = I965_CURSOR_DFT_WM, | |
970 | .guard_size = 2, | |
971 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
972 | }; |
973 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
974 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
975 | .max_wm = VALLEYVIEW_MAX_WM, | |
976 | .default_wm = VALLEYVIEW_MAX_WM, | |
977 | .guard_size = 2, | |
978 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
979 | }; |
980 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
981 | .fifo_size = I965_CURSOR_FIFO, |
982 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
983 | .default_wm = I965_CURSOR_DFT_WM, | |
984 | .guard_size = 2, | |
985 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
986 | }; |
987 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
988 | .fifo_size = I965_CURSOR_FIFO, |
989 | .max_wm = I965_CURSOR_MAX_WM, | |
990 | .default_wm = I965_CURSOR_DFT_WM, | |
991 | .guard_size = 2, | |
992 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
993 | }; |
994 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
995 | .fifo_size = I945_FIFO_SIZE, |
996 | .max_wm = I915_MAX_WM, | |
997 | .default_wm = 1, | |
998 | .guard_size = 2, | |
999 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1000 | }; |
1001 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
1002 | .fifo_size = I915_FIFO_SIZE, |
1003 | .max_wm = I915_MAX_WM, | |
1004 | .default_wm = 1, | |
1005 | .guard_size = 2, | |
1006 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 1007 | }; |
9d539105 | 1008 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
1009 | .fifo_size = I855GM_FIFO_SIZE, |
1010 | .max_wm = I915_MAX_WM, | |
1011 | .default_wm = 1, | |
1012 | .guard_size = 2, | |
1013 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 1014 | }; |
9d539105 VS |
1015 | static const struct intel_watermark_params i830_bc_wm_info = { |
1016 | .fifo_size = I855GM_FIFO_SIZE, | |
1017 | .max_wm = I915_MAX_WM/2, | |
1018 | .default_wm = 1, | |
1019 | .guard_size = 2, | |
1020 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
1021 | }; | |
feb56b93 | 1022 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
1023 | .fifo_size = I830_FIFO_SIZE, |
1024 | .max_wm = I915_MAX_WM, | |
1025 | .default_wm = 1, | |
1026 | .guard_size = 2, | |
1027 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1028 | }; |
1029 | ||
b445e3b0 ED |
1030 | /** |
1031 | * intel_calculate_wm - calculate watermark level | |
1032 | * @clock_in_khz: pixel clock | |
1033 | * @wm: chip FIFO params | |
1034 | * @pixel_size: display pixel size | |
1035 | * @latency_ns: memory latency for the platform | |
1036 | * | |
1037 | * Calculate the watermark level (the level at which the display plane will | |
1038 | * start fetching from memory again). Each chip has a different display | |
1039 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
1040 | * in the correct intel_watermark_params structure. | |
1041 | * | |
1042 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
1043 | * on the pixel size. When it reaches the watermark level, it'll start | |
1044 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
1045 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
1046 | * will occur, and a display engine hang could result. | |
1047 | */ | |
1048 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
1049 | const struct intel_watermark_params *wm, | |
1050 | int fifo_size, | |
1051 | int pixel_size, | |
1052 | unsigned long latency_ns) | |
1053 | { | |
1054 | long entries_required, wm_size; | |
1055 | ||
1056 | /* | |
1057 | * Note: we need to make sure we don't overflow for various clock & | |
1058 | * latency values. | |
1059 | * clocks go from a few thousand to several hundred thousand. | |
1060 | * latency is usually a few thousand | |
1061 | */ | |
1062 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
1063 | 1000; | |
1064 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
1065 | ||
1066 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
1067 | ||
1068 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
1069 | ||
1070 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
1071 | ||
1072 | /* Don't promote wm_size to unsigned... */ | |
1073 | if (wm_size > (long)wm->max_wm) | |
1074 | wm_size = wm->max_wm; | |
1075 | if (wm_size <= 0) | |
1076 | wm_size = wm->default_wm; | |
1077 | return wm_size; | |
1078 | } | |
1079 | ||
1080 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
1081 | { | |
1082 | struct drm_crtc *crtc, *enabled = NULL; | |
1083 | ||
70e1e0ec | 1084 | for_each_crtc(dev, crtc) { |
3490ea5d | 1085 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
1086 | if (enabled) |
1087 | return NULL; | |
1088 | enabled = crtc; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | return enabled; | |
1093 | } | |
1094 | ||
46ba614c | 1095 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1096 | { |
46ba614c | 1097 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; |
1099 | struct drm_crtc *crtc; | |
1100 | const struct cxsr_latency *latency; | |
1101 | u32 reg; | |
1102 | unsigned long wm; | |
1103 | ||
1104 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
1105 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
1106 | if (!latency) { | |
1107 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 1108 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1109 | return; |
1110 | } | |
1111 | ||
1112 | crtc = single_enabled_crtc(dev); | |
1113 | if (crtc) { | |
241bfc38 | 1114 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1115 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
241bfc38 DL |
1116 | int clock; |
1117 | ||
1118 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | |
1119 | clock = adjusted_mode->crtc_clock; | |
b445e3b0 ED |
1120 | |
1121 | /* Display SR */ | |
1122 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
1123 | pineview_display_wm.fifo_size, | |
1124 | pixel_size, latency->display_sr); | |
1125 | reg = I915_READ(DSPFW1); | |
1126 | reg &= ~DSPFW_SR_MASK; | |
1127 | reg |= wm << DSPFW_SR_SHIFT; | |
1128 | I915_WRITE(DSPFW1, reg); | |
1129 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
1130 | ||
1131 | /* cursor SR */ | |
1132 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
1133 | pineview_display_wm.fifo_size, | |
1134 | pixel_size, latency->cursor_sr); | |
1135 | reg = I915_READ(DSPFW3); | |
1136 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
1137 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
1138 | I915_WRITE(DSPFW3, reg); | |
1139 | ||
1140 | /* Display HPLL off SR */ | |
1141 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
1142 | pineview_display_hplloff_wm.fifo_size, | |
1143 | pixel_size, latency->display_hpll_disable); | |
1144 | reg = I915_READ(DSPFW3); | |
1145 | reg &= ~DSPFW_HPLL_SR_MASK; | |
1146 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
1147 | I915_WRITE(DSPFW3, reg); | |
1148 | ||
1149 | /* cursor HPLL off SR */ | |
1150 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
1151 | pineview_display_hplloff_wm.fifo_size, | |
1152 | pixel_size, latency->cursor_hpll_disable); | |
1153 | reg = I915_READ(DSPFW3); | |
1154 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
1155 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
1156 | I915_WRITE(DSPFW3, reg); | |
1157 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
1158 | ||
5209b1f4 | 1159 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 1160 | } else { |
5209b1f4 | 1161 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1162 | } |
1163 | } | |
1164 | ||
1165 | static bool g4x_compute_wm0(struct drm_device *dev, | |
1166 | int plane, | |
1167 | const struct intel_watermark_params *display, | |
1168 | int display_latency_ns, | |
1169 | const struct intel_watermark_params *cursor, | |
1170 | int cursor_latency_ns, | |
1171 | int *plane_wm, | |
1172 | int *cursor_wm) | |
1173 | { | |
1174 | struct drm_crtc *crtc; | |
4fe8590a | 1175 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1176 | int htotal, hdisplay, clock, pixel_size; |
1177 | int line_time_us, line_count; | |
1178 | int entries, tlb_miss; | |
1179 | ||
1180 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1181 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
1182 | *cursor_wm = cursor->guard_size; |
1183 | *plane_wm = display->guard_size; | |
1184 | return false; | |
1185 | } | |
1186 | ||
4fe8590a | 1187 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1188 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1189 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1190 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1191 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1192 | |
1193 | /* Use the small buffer method to calculate plane watermark */ | |
1194 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1195 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
1196 | if (tlb_miss > 0) | |
1197 | entries += tlb_miss; | |
1198 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1199 | *plane_wm = entries + display->guard_size; | |
1200 | if (*plane_wm > (int)display->max_wm) | |
1201 | *plane_wm = display->max_wm; | |
1202 | ||
1203 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 1204 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 1205 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
7bb836dd | 1206 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
b445e3b0 ED |
1207 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1208 | if (tlb_miss > 0) | |
1209 | entries += tlb_miss; | |
1210 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1211 | *cursor_wm = entries + cursor->guard_size; | |
1212 | if (*cursor_wm > (int)cursor->max_wm) | |
1213 | *cursor_wm = (int)cursor->max_wm; | |
1214 | ||
1215 | return true; | |
1216 | } | |
1217 | ||
1218 | /* | |
1219 | * Check the wm result. | |
1220 | * | |
1221 | * If any calculated watermark values is larger than the maximum value that | |
1222 | * can be programmed into the associated watermark register, that watermark | |
1223 | * must be disabled. | |
1224 | */ | |
1225 | static bool g4x_check_srwm(struct drm_device *dev, | |
1226 | int display_wm, int cursor_wm, | |
1227 | const struct intel_watermark_params *display, | |
1228 | const struct intel_watermark_params *cursor) | |
1229 | { | |
1230 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1231 | display_wm, cursor_wm); | |
1232 | ||
1233 | if (display_wm > display->max_wm) { | |
1234 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1235 | display_wm, display->max_wm); | |
1236 | return false; | |
1237 | } | |
1238 | ||
1239 | if (cursor_wm > cursor->max_wm) { | |
1240 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1241 | cursor_wm, cursor->max_wm); | |
1242 | return false; | |
1243 | } | |
1244 | ||
1245 | if (!(display_wm || cursor_wm)) { | |
1246 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1247 | return false; | |
1248 | } | |
1249 | ||
1250 | return true; | |
1251 | } | |
1252 | ||
1253 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1254 | int plane, | |
1255 | int latency_ns, | |
1256 | const struct intel_watermark_params *display, | |
1257 | const struct intel_watermark_params *cursor, | |
1258 | int *display_wm, int *cursor_wm) | |
1259 | { | |
1260 | struct drm_crtc *crtc; | |
4fe8590a | 1261 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1262 | int hdisplay, htotal, pixel_size, clock; |
1263 | unsigned long line_time_us; | |
1264 | int line_count, line_size; | |
1265 | int small, large; | |
1266 | int entries; | |
1267 | ||
1268 | if (!latency_ns) { | |
1269 | *display_wm = *cursor_wm = 0; | |
1270 | return false; | |
1271 | } | |
1272 | ||
1273 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4fe8590a | 1274 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1275 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1276 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1277 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1278 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 | 1279 | |
922044c9 | 1280 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1281 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1282 | line_size = hdisplay * pixel_size; | |
1283 | ||
1284 | /* Use the minimum of the small and large buffer method for primary */ | |
1285 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1286 | large = line_count * line_size; | |
1287 | ||
1288 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1289 | *display_wm = entries + display->guard_size; | |
1290 | ||
1291 | /* calculate the self-refresh watermark for display cursor */ | |
7bb836dd | 1292 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1293 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1294 | *cursor_wm = entries + cursor->guard_size; | |
1295 | ||
1296 | return g4x_check_srwm(dev, | |
1297 | *display_wm, *cursor_wm, | |
1298 | display, cursor); | |
1299 | } | |
1300 | ||
0948c265 GB |
1301 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, |
1302 | int pixel_size, | |
1303 | int *prec_mult, | |
1304 | int *drain_latency) | |
b445e3b0 | 1305 | { |
b445e3b0 | 1306 | int entries; |
0948c265 | 1307 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
b445e3b0 | 1308 | |
0948c265 | 1309 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
b445e3b0 ED |
1310 | return false; |
1311 | ||
0948c265 GB |
1312 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
1313 | return false; | |
b445e3b0 | 1314 | |
a398e9c7 | 1315 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
0948c265 GB |
1316 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : |
1317 | DRAIN_LATENCY_PRECISION_32; | |
1318 | *drain_latency = (64 * (*prec_mult) * 4) / entries; | |
b445e3b0 | 1319 | |
a398e9c7 GB |
1320 | if (*drain_latency > DRAIN_LATENCY_MASK) |
1321 | *drain_latency = DRAIN_LATENCY_MASK; | |
b445e3b0 ED |
1322 | |
1323 | return true; | |
1324 | } | |
1325 | ||
1326 | /* | |
1327 | * Update drain latency registers of memory arbiter | |
1328 | * | |
1329 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1330 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1331 | * latency value. | |
1332 | */ | |
1333 | ||
41aad816 | 1334 | static void vlv_update_drain_latency(struct drm_crtc *crtc) |
b445e3b0 | 1335 | { |
0948c265 GB |
1336 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
1337 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1338 | int pixel_size; | |
1339 | int drain_latency; | |
1340 | enum pipe pipe = intel_crtc->pipe; | |
1341 | int plane_prec, prec_mult, plane_dl; | |
b445e3b0 | 1342 | |
0948c265 GB |
1343 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 | |
1344 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 | | |
1345 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); | |
1346 | ||
1347 | if (!intel_crtc_active(crtc)) { | |
1348 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
1349 | return; | |
1350 | } | |
b445e3b0 | 1351 | |
0948c265 GB |
1352 | /* Primary plane Drain Latency */ |
1353 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ | |
1354 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
1355 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? | |
1356 | DDL_PLANE_PRECISION_64 : | |
1357 | DDL_PLANE_PRECISION_32; | |
1358 | plane_dl |= plane_prec | drain_latency; | |
b445e3b0 ED |
1359 | } |
1360 | ||
0948c265 GB |
1361 | /* Cursor Drain Latency |
1362 | * BPP is always 4 for cursor | |
1363 | */ | |
1364 | pixel_size = 4; | |
b445e3b0 | 1365 | |
0948c265 GB |
1366 | /* Program cursor DL only if it is enabled */ |
1367 | if (intel_crtc->cursor_base && | |
1368 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
1369 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? | |
1370 | DDL_CURSOR_PRECISION_64 : | |
1371 | DDL_CURSOR_PRECISION_32; | |
1372 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); | |
b445e3b0 | 1373 | } |
0948c265 GB |
1374 | |
1375 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
b445e3b0 ED |
1376 | } |
1377 | ||
1378 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1379 | ||
46ba614c | 1380 | static void valleyview_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1381 | { |
46ba614c | 1382 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1383 | static const int sr_latency_ns = 12000; |
1384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1385 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1386 | int plane_sr, cursor_sr; | |
af6c4575 | 1387 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 | 1388 | unsigned int enabled = 0; |
9858425c | 1389 | bool cxsr_enabled; |
b445e3b0 | 1390 | |
41aad816 | 1391 | vlv_update_drain_latency(crtc); |
b445e3b0 | 1392 | |
51cea1f4 | 1393 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1394 | &valleyview_wm_info, pessimal_latency_ns, |
1395 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1396 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1397 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1398 | |
51cea1f4 | 1399 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1400 | &valleyview_wm_info, pessimal_latency_ns, |
1401 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1402 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1403 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1404 | |
b445e3b0 ED |
1405 | if (single_plane_enabled(enabled) && |
1406 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1407 | sr_latency_ns, | |
1408 | &valleyview_wm_info, | |
1409 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
1410 | &plane_sr, &ignore_cursor_sr) && |
1411 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1412 | 2*sr_latency_ns, | |
1413 | &valleyview_wm_info, | |
1414 | &valleyview_cursor_wm_info, | |
52bd02d8 | 1415 | &ignore_plane_sr, &cursor_sr)) { |
9858425c | 1416 | cxsr_enabled = true; |
52bd02d8 | 1417 | } else { |
9858425c | 1418 | cxsr_enabled = false; |
5209b1f4 | 1419 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1420 | plane_sr = cursor_sr = 0; |
1421 | } | |
b445e3b0 | 1422 | |
a5043453 VS |
1423 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1424 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1425 | planea_wm, cursora_wm, |
1426 | planeb_wm, cursorb_wm, | |
1427 | plane_sr, cursor_sr); | |
1428 | ||
1429 | I915_WRITE(DSPFW1, | |
1430 | (plane_sr << DSPFW_SR_SHIFT) | | |
1431 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1432 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1433 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1434 | I915_WRITE(DSPFW2, |
8c919b28 | 1435 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1436 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1437 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
1438 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1439 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1440 | |
1441 | if (cxsr_enabled) | |
1442 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1443 | } |
1444 | ||
3c2777fd VS |
1445 | static void cherryview_update_wm(struct drm_crtc *crtc) |
1446 | { | |
1447 | struct drm_device *dev = crtc->dev; | |
1448 | static const int sr_latency_ns = 12000; | |
1449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1450 | int planea_wm, planeb_wm, planec_wm; | |
1451 | int cursora_wm, cursorb_wm, cursorc_wm; | |
1452 | int plane_sr, cursor_sr; | |
1453 | int ignore_plane_sr, ignore_cursor_sr; | |
1454 | unsigned int enabled = 0; | |
1455 | bool cxsr_enabled; | |
1456 | ||
1457 | vlv_update_drain_latency(crtc); | |
1458 | ||
1459 | if (g4x_compute_wm0(dev, PIPE_A, | |
5aef6003 CW |
1460 | &valleyview_wm_info, pessimal_latency_ns, |
1461 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1462 | &planea_wm, &cursora_wm)) |
1463 | enabled |= 1 << PIPE_A; | |
1464 | ||
1465 | if (g4x_compute_wm0(dev, PIPE_B, | |
5aef6003 CW |
1466 | &valleyview_wm_info, pessimal_latency_ns, |
1467 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1468 | &planeb_wm, &cursorb_wm)) |
1469 | enabled |= 1 << PIPE_B; | |
1470 | ||
1471 | if (g4x_compute_wm0(dev, PIPE_C, | |
5aef6003 CW |
1472 | &valleyview_wm_info, pessimal_latency_ns, |
1473 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1474 | &planec_wm, &cursorc_wm)) |
1475 | enabled |= 1 << PIPE_C; | |
1476 | ||
1477 | if (single_plane_enabled(enabled) && | |
1478 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1479 | sr_latency_ns, | |
1480 | &valleyview_wm_info, | |
1481 | &valleyview_cursor_wm_info, | |
1482 | &plane_sr, &ignore_cursor_sr) && | |
1483 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1484 | 2*sr_latency_ns, | |
1485 | &valleyview_wm_info, | |
1486 | &valleyview_cursor_wm_info, | |
1487 | &ignore_plane_sr, &cursor_sr)) { | |
1488 | cxsr_enabled = true; | |
1489 | } else { | |
1490 | cxsr_enabled = false; | |
1491 | intel_set_memory_cxsr(dev_priv, false); | |
1492 | plane_sr = cursor_sr = 0; | |
1493 | } | |
1494 | ||
1495 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
1496 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " | |
1497 | "SR: plane=%d, cursor=%d\n", | |
1498 | planea_wm, cursora_wm, | |
1499 | planeb_wm, cursorb_wm, | |
1500 | planec_wm, cursorc_wm, | |
1501 | plane_sr, cursor_sr); | |
1502 | ||
1503 | I915_WRITE(DSPFW1, | |
1504 | (plane_sr << DSPFW_SR_SHIFT) | | |
1505 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1506 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1507 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
1508 | I915_WRITE(DSPFW2, | |
1509 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
1510 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
1511 | I915_WRITE(DSPFW3, | |
1512 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | | |
1513 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1514 | I915_WRITE(DSPFW9_CHV, | |
1515 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | | |
1516 | DSPFW_CURSORC_MASK)) | | |
1517 | (planec_wm << DSPFW_PLANEC_SHIFT) | | |
1518 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); | |
1519 | ||
1520 | if (cxsr_enabled) | |
1521 | intel_set_memory_cxsr(dev_priv, true); | |
1522 | } | |
1523 | ||
01e184cc GB |
1524 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
1525 | struct drm_crtc *crtc, | |
1526 | uint32_t sprite_width, | |
1527 | uint32_t sprite_height, | |
1528 | int pixel_size, | |
1529 | bool enabled, bool scaled) | |
1530 | { | |
1531 | struct drm_device *dev = crtc->dev; | |
1532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1533 | int pipe = to_intel_plane(plane)->pipe; | |
1534 | int sprite = to_intel_plane(plane)->plane; | |
1535 | int drain_latency; | |
1536 | int plane_prec; | |
1537 | int sprite_dl; | |
1538 | int prec_mult; | |
1539 | ||
1540 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) | | |
1541 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); | |
1542 | ||
1543 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, | |
1544 | &drain_latency)) { | |
1545 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? | |
1546 | DDL_SPRITE_PRECISION_64(sprite) : | |
1547 | DDL_SPRITE_PRECISION_32(sprite); | |
1548 | sprite_dl |= plane_prec | | |
1549 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); | |
1550 | } | |
1551 | ||
1552 | I915_WRITE(VLV_DDL(pipe), sprite_dl); | |
1553 | } | |
1554 | ||
46ba614c | 1555 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1556 | { |
46ba614c | 1557 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1558 | static const int sr_latency_ns = 12000; |
1559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1560 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1561 | int plane_sr, cursor_sr; | |
1562 | unsigned int enabled = 0; | |
9858425c | 1563 | bool cxsr_enabled; |
b445e3b0 | 1564 | |
51cea1f4 | 1565 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1566 | &g4x_wm_info, pessimal_latency_ns, |
1567 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1568 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1569 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1570 | |
51cea1f4 | 1571 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1572 | &g4x_wm_info, pessimal_latency_ns, |
1573 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1574 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1575 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1576 | |
b445e3b0 ED |
1577 | if (single_plane_enabled(enabled) && |
1578 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1579 | sr_latency_ns, | |
1580 | &g4x_wm_info, | |
1581 | &g4x_cursor_wm_info, | |
52bd02d8 | 1582 | &plane_sr, &cursor_sr)) { |
9858425c | 1583 | cxsr_enabled = true; |
52bd02d8 | 1584 | } else { |
9858425c | 1585 | cxsr_enabled = false; |
5209b1f4 | 1586 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1587 | plane_sr = cursor_sr = 0; |
1588 | } | |
b445e3b0 | 1589 | |
a5043453 VS |
1590 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1591 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1592 | planea_wm, cursora_wm, |
1593 | planeb_wm, cursorb_wm, | |
1594 | plane_sr, cursor_sr); | |
1595 | ||
1596 | I915_WRITE(DSPFW1, | |
1597 | (plane_sr << DSPFW_SR_SHIFT) | | |
1598 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1599 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1600 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1601 | I915_WRITE(DSPFW2, |
8c919b28 | 1602 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1603 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1604 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1605 | I915_WRITE(DSPFW3, | |
8c919b28 | 1606 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 | 1607 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
9858425c ID |
1608 | |
1609 | if (cxsr_enabled) | |
1610 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1611 | } |
1612 | ||
46ba614c | 1613 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1614 | { |
46ba614c | 1615 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
1617 | struct drm_crtc *crtc; | |
1618 | int srwm = 1; | |
1619 | int cursor_sr = 16; | |
9858425c | 1620 | bool cxsr_enabled; |
b445e3b0 ED |
1621 | |
1622 | /* Calc sr entries for one plane configs */ | |
1623 | crtc = single_enabled_crtc(dev); | |
1624 | if (crtc) { | |
1625 | /* self-refresh has much higher latency */ | |
1626 | static const int sr_latency_ns = 12000; | |
4fe8590a VS |
1627 | const struct drm_display_mode *adjusted_mode = |
1628 | &to_intel_crtc(crtc)->config.adjusted_mode; | |
241bfc38 | 1629 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1630 | int htotal = adjusted_mode->crtc_htotal; |
37327abd | 1631 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1632 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1633 | unsigned long line_time_us; |
1634 | int entries; | |
1635 | ||
922044c9 | 1636 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1637 | |
1638 | /* Use ns/us then divide to preserve precision */ | |
1639 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1640 | pixel_size * hdisplay; | |
1641 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1642 | srwm = I965_FIFO_SIZE - entries; | |
1643 | if (srwm < 0) | |
1644 | srwm = 1; | |
1645 | srwm &= 0x1ff; | |
1646 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1647 | entries, srwm); | |
1648 | ||
1649 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
7bb836dd | 1650 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1651 | entries = DIV_ROUND_UP(entries, |
1652 | i965_cursor_wm_info.cacheline_size); | |
1653 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1654 | (entries + i965_cursor_wm_info.guard_size); | |
1655 | ||
1656 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1657 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1658 | ||
1659 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1660 | "cursor %d\n", srwm, cursor_sr); | |
1661 | ||
9858425c | 1662 | cxsr_enabled = true; |
b445e3b0 | 1663 | } else { |
9858425c | 1664 | cxsr_enabled = false; |
b445e3b0 | 1665 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1666 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1667 | } |
1668 | ||
1669 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1670 | srwm); | |
1671 | ||
1672 | /* 965 has limitations... */ | |
1673 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
0a560674 VS |
1674 | (8 << DSPFW_CURSORB_SHIFT) | |
1675 | (8 << DSPFW_PLANEB_SHIFT) | | |
1676 | (8 << DSPFW_PLANEA_SHIFT)); | |
1677 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | | |
1678 | (8 << DSPFW_PLANEC_SHIFT_OLD)); | |
b445e3b0 ED |
1679 | /* update cursor SR watermark */ |
1680 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1681 | |
1682 | if (cxsr_enabled) | |
1683 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1684 | } |
1685 | ||
46ba614c | 1686 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1687 | { |
46ba614c | 1688 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
1690 | const struct intel_watermark_params *wm_info; | |
1691 | uint32_t fwater_lo; | |
1692 | uint32_t fwater_hi; | |
1693 | int cwm, srwm = 1; | |
1694 | int fifo_size; | |
1695 | int planea_wm, planeb_wm; | |
1696 | struct drm_crtc *crtc, *enabled = NULL; | |
1697 | ||
1698 | if (IS_I945GM(dev)) | |
1699 | wm_info = &i945_wm_info; | |
1700 | else if (!IS_GEN2(dev)) | |
1701 | wm_info = &i915_wm_info; | |
1702 | else | |
9d539105 | 1703 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1704 | |
1705 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1706 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1707 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1708 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1709 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1710 | if (IS_GEN2(dev)) |
1711 | cpp = 4; | |
1712 | ||
241bfc38 DL |
1713 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1714 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1715 | wm_info, fifo_size, cpp, |
5aef6003 | 1716 | pessimal_latency_ns); |
b445e3b0 | 1717 | enabled = crtc; |
9d539105 | 1718 | } else { |
b445e3b0 | 1719 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1720 | if (planea_wm > (long)wm_info->max_wm) |
1721 | planea_wm = wm_info->max_wm; | |
1722 | } | |
1723 | ||
1724 | if (IS_GEN2(dev)) | |
1725 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1726 | |
1727 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1728 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1729 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1730 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1731 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1732 | if (IS_GEN2(dev)) |
1733 | cpp = 4; | |
1734 | ||
241bfc38 DL |
1735 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1736 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1737 | wm_info, fifo_size, cpp, |
5aef6003 | 1738 | pessimal_latency_ns); |
b445e3b0 ED |
1739 | if (enabled == NULL) |
1740 | enabled = crtc; | |
1741 | else | |
1742 | enabled = NULL; | |
9d539105 | 1743 | } else { |
b445e3b0 | 1744 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1745 | if (planeb_wm > (long)wm_info->max_wm) |
1746 | planeb_wm = wm_info->max_wm; | |
1747 | } | |
b445e3b0 ED |
1748 | |
1749 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1750 | ||
2ab1bc9d | 1751 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1752 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1753 | |
2ff8fde1 | 1754 | obj = intel_fb_obj(enabled->primary->fb); |
2ab1bc9d DV |
1755 | |
1756 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1757 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1758 | enabled = NULL; |
1759 | } | |
1760 | ||
b445e3b0 ED |
1761 | /* |
1762 | * Overlay gets an aggressive default since video jitter is bad. | |
1763 | */ | |
1764 | cwm = 2; | |
1765 | ||
1766 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1767 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1768 | |
1769 | /* Calc sr entries for one plane configs */ | |
1770 | if (HAS_FW_BLC(dev) && enabled) { | |
1771 | /* self-refresh has much higher latency */ | |
1772 | static const int sr_latency_ns = 6000; | |
4fe8590a VS |
1773 | const struct drm_display_mode *adjusted_mode = |
1774 | &to_intel_crtc(enabled)->config.adjusted_mode; | |
241bfc38 | 1775 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1776 | int htotal = adjusted_mode->crtc_htotal; |
f727b490 | 1777 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
f4510a27 | 1778 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1779 | unsigned long line_time_us; |
1780 | int entries; | |
1781 | ||
922044c9 | 1782 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1783 | |
1784 | /* Use ns/us then divide to preserve precision */ | |
1785 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1786 | pixel_size * hdisplay; | |
1787 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1788 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1789 | srwm = wm_info->fifo_size - entries; | |
1790 | if (srwm < 0) | |
1791 | srwm = 1; | |
1792 | ||
1793 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1794 | I915_WRITE(FW_BLC_SELF, | |
1795 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1796 | else if (IS_I915GM(dev)) | |
1797 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1798 | } | |
1799 | ||
1800 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1801 | planea_wm, planeb_wm, cwm, srwm); | |
1802 | ||
1803 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1804 | fwater_hi = (cwm & 0x1f); | |
1805 | ||
1806 | /* Set request length to 8 cachelines per fetch */ | |
1807 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1808 | fwater_hi = fwater_hi | (1 << 8); | |
1809 | ||
1810 | I915_WRITE(FW_BLC, fwater_lo); | |
1811 | I915_WRITE(FW_BLC2, fwater_hi); | |
1812 | ||
5209b1f4 ID |
1813 | if (enabled) |
1814 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1815 | } |
1816 | ||
feb56b93 | 1817 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1818 | { |
46ba614c | 1819 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1820 | struct drm_i915_private *dev_priv = dev->dev_private; |
1821 | struct drm_crtc *crtc; | |
241bfc38 | 1822 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1823 | uint32_t fwater_lo; |
1824 | int planea_wm; | |
1825 | ||
1826 | crtc = single_enabled_crtc(dev); | |
1827 | if (crtc == NULL) | |
1828 | return; | |
1829 | ||
241bfc38 DL |
1830 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1831 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
feb56b93 | 1832 | &i845_wm_info, |
b445e3b0 | 1833 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1834 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1835 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1836 | fwater_lo |= (3<<8) | planea_wm; | |
1837 | ||
1838 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1839 | ||
1840 | I915_WRITE(FW_BLC, fwater_lo); | |
1841 | } | |
1842 | ||
3658729a VS |
1843 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1844 | struct drm_crtc *crtc) | |
801bcfff PZ |
1845 | { |
1846 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1847 | uint32_t pixel_rate; |
801bcfff | 1848 | |
241bfc38 | 1849 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
801bcfff PZ |
1850 | |
1851 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1852 | * adjust the pixel_rate here. */ | |
1853 | ||
fd4daa9c | 1854 | if (intel_crtc->config.pch_pfit.enabled) { |
801bcfff | 1855 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
fd4daa9c | 1856 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
801bcfff | 1857 | |
37327abd VS |
1858 | pipe_w = intel_crtc->config.pipe_src_w; |
1859 | pipe_h = intel_crtc->config.pipe_src_h; | |
801bcfff PZ |
1860 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1861 | pfit_h = pfit_size & 0xFFFF; | |
1862 | if (pipe_w < pfit_w) | |
1863 | pipe_w = pfit_w; | |
1864 | if (pipe_h < pfit_h) | |
1865 | pipe_h = pfit_h; | |
1866 | ||
1867 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1868 | pfit_w * pfit_h); | |
1869 | } | |
1870 | ||
1871 | return pixel_rate; | |
1872 | } | |
1873 | ||
37126462 | 1874 | /* latency must be in 0.1us units. */ |
23297044 | 1875 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1876 | uint32_t latency) |
1877 | { | |
1878 | uint64_t ret; | |
1879 | ||
3312ba65 VS |
1880 | if (WARN(latency == 0, "Latency value missing\n")) |
1881 | return UINT_MAX; | |
1882 | ||
801bcfff PZ |
1883 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1884 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1885 | ||
1886 | return ret; | |
1887 | } | |
1888 | ||
37126462 | 1889 | /* latency must be in 0.1us units. */ |
23297044 | 1890 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1891 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1892 | uint32_t latency) | |
1893 | { | |
1894 | uint32_t ret; | |
1895 | ||
3312ba65 VS |
1896 | if (WARN(latency == 0, "Latency value missing\n")) |
1897 | return UINT_MAX; | |
1898 | ||
801bcfff PZ |
1899 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1900 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1901 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1902 | return ret; | |
1903 | } | |
1904 | ||
23297044 | 1905 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1906 | uint8_t bytes_per_pixel) |
1907 | { | |
1908 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1909 | } | |
1910 | ||
820c1980 | 1911 | struct ilk_pipe_wm_parameters { |
801bcfff | 1912 | bool active; |
801bcfff PZ |
1913 | uint32_t pipe_htotal; |
1914 | uint32_t pixel_rate; | |
c35426d2 VS |
1915 | struct intel_plane_wm_parameters pri; |
1916 | struct intel_plane_wm_parameters spr; | |
1917 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1918 | }; |
1919 | ||
820c1980 | 1920 | struct ilk_wm_maximums { |
cca32e9a PZ |
1921 | uint16_t pri; |
1922 | uint16_t spr; | |
1923 | uint16_t cur; | |
1924 | uint16_t fbc; | |
1925 | }; | |
1926 | ||
240264f4 VS |
1927 | /* used in computing the new watermarks state */ |
1928 | struct intel_wm_config { | |
1929 | unsigned int num_pipes_active; | |
1930 | bool sprites_enabled; | |
1931 | bool sprites_scaled; | |
240264f4 VS |
1932 | }; |
1933 | ||
37126462 VS |
1934 | /* |
1935 | * For both WM_PIPE and WM_LP. | |
1936 | * mem_value must be in 0.1us units. | |
1937 | */ | |
820c1980 | 1938 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1939 | uint32_t mem_value, |
1940 | bool is_lp) | |
801bcfff | 1941 | { |
cca32e9a PZ |
1942 | uint32_t method1, method2; |
1943 | ||
c35426d2 | 1944 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1945 | return 0; |
1946 | ||
23297044 | 1947 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1948 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1949 | mem_value); |
1950 | ||
1951 | if (!is_lp) | |
1952 | return method1; | |
1953 | ||
23297044 | 1954 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1955 | params->pipe_htotal, |
c35426d2 VS |
1956 | params->pri.horiz_pixels, |
1957 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1958 | mem_value); |
1959 | ||
1960 | return min(method1, method2); | |
801bcfff PZ |
1961 | } |
1962 | ||
37126462 VS |
1963 | /* |
1964 | * For both WM_PIPE and WM_LP. | |
1965 | * mem_value must be in 0.1us units. | |
1966 | */ | |
820c1980 | 1967 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1968 | uint32_t mem_value) |
1969 | { | |
1970 | uint32_t method1, method2; | |
1971 | ||
c35426d2 | 1972 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1973 | return 0; |
1974 | ||
23297044 | 1975 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1976 | params->spr.bytes_per_pixel, |
801bcfff | 1977 | mem_value); |
23297044 | 1978 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1979 | params->pipe_htotal, |
c35426d2 VS |
1980 | params->spr.horiz_pixels, |
1981 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1982 | mem_value); |
1983 | return min(method1, method2); | |
1984 | } | |
1985 | ||
37126462 VS |
1986 | /* |
1987 | * For both WM_PIPE and WM_LP. | |
1988 | * mem_value must be in 0.1us units. | |
1989 | */ | |
820c1980 | 1990 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1991 | uint32_t mem_value) |
1992 | { | |
c35426d2 | 1993 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1994 | return 0; |
1995 | ||
23297044 | 1996 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1997 | params->pipe_htotal, |
c35426d2 VS |
1998 | params->cur.horiz_pixels, |
1999 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
2000 | mem_value); |
2001 | } | |
2002 | ||
cca32e9a | 2003 | /* Only for WM_LP. */ |
820c1980 | 2004 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 2005 | uint32_t pri_val) |
cca32e9a | 2006 | { |
c35426d2 | 2007 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
2008 | return 0; |
2009 | ||
23297044 | 2010 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
2011 | params->pri.horiz_pixels, |
2012 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
2013 | } |
2014 | ||
158ae64f VS |
2015 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
2016 | { | |
416f4727 VS |
2017 | if (INTEL_INFO(dev)->gen >= 8) |
2018 | return 3072; | |
2019 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
2020 | return 768; |
2021 | else | |
2022 | return 512; | |
2023 | } | |
2024 | ||
4e975081 VS |
2025 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
2026 | int level, bool is_sprite) | |
2027 | { | |
2028 | if (INTEL_INFO(dev)->gen >= 8) | |
2029 | /* BDW primary/sprite plane watermarks */ | |
2030 | return level == 0 ? 255 : 2047; | |
2031 | else if (INTEL_INFO(dev)->gen >= 7) | |
2032 | /* IVB/HSW primary/sprite plane watermarks */ | |
2033 | return level == 0 ? 127 : 1023; | |
2034 | else if (!is_sprite) | |
2035 | /* ILK/SNB primary plane watermarks */ | |
2036 | return level == 0 ? 127 : 511; | |
2037 | else | |
2038 | /* ILK/SNB sprite plane watermarks */ | |
2039 | return level == 0 ? 63 : 255; | |
2040 | } | |
2041 | ||
2042 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
2043 | int level) | |
2044 | { | |
2045 | if (INTEL_INFO(dev)->gen >= 7) | |
2046 | return level == 0 ? 63 : 255; | |
2047 | else | |
2048 | return level == 0 ? 31 : 63; | |
2049 | } | |
2050 | ||
2051 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
2052 | { | |
2053 | if (INTEL_INFO(dev)->gen >= 8) | |
2054 | return 31; | |
2055 | else | |
2056 | return 15; | |
2057 | } | |
2058 | ||
158ae64f VS |
2059 | /* Calculate the maximum primary/sprite plane watermark */ |
2060 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2061 | int level, | |
240264f4 | 2062 | const struct intel_wm_config *config, |
158ae64f VS |
2063 | enum intel_ddb_partitioning ddb_partitioning, |
2064 | bool is_sprite) | |
2065 | { | |
2066 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
2067 | |
2068 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2069 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2070 | return 0; |
2071 | ||
2072 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2073 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
2074 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
2075 | ||
2076 | /* | |
2077 | * For some reason the non self refresh | |
2078 | * FIFO size is only half of the self | |
2079 | * refresh FIFO size on ILK/SNB. | |
2080 | */ | |
2081 | if (INTEL_INFO(dev)->gen <= 6) | |
2082 | fifo_size /= 2; | |
2083 | } | |
2084 | ||
240264f4 | 2085 | if (config->sprites_enabled) { |
158ae64f VS |
2086 | /* level 0 is always calculated with 1:1 split */ |
2087 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2088 | if (is_sprite) | |
2089 | fifo_size *= 5; | |
2090 | fifo_size /= 6; | |
2091 | } else { | |
2092 | fifo_size /= 2; | |
2093 | } | |
2094 | } | |
2095 | ||
2096 | /* clamp to max that the registers can hold */ | |
4e975081 | 2097 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
2098 | } |
2099 | ||
2100 | /* Calculate the maximum cursor plane watermark */ | |
2101 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2102 | int level, |
2103 | const struct intel_wm_config *config) | |
158ae64f VS |
2104 | { |
2105 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2106 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2107 | return 64; |
2108 | ||
2109 | /* otherwise just report max that registers can hold */ | |
4e975081 | 2110 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
2111 | } |
2112 | ||
d34ff9c6 | 2113 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2114 | int level, |
2115 | const struct intel_wm_config *config, | |
2116 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2117 | struct ilk_wm_maximums *max) |
158ae64f | 2118 | { |
240264f4 VS |
2119 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2120 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2121 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 2122 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
2123 | } |
2124 | ||
a3cb4048 VS |
2125 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
2126 | int level, | |
2127 | struct ilk_wm_maximums *max) | |
2128 | { | |
2129 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
2130 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
2131 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
2132 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
2133 | } | |
2134 | ||
d9395655 | 2135 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2136 | const struct ilk_wm_maximums *max, |
d9395655 | 2137 | struct intel_wm_level *result) |
a9786a11 VS |
2138 | { |
2139 | bool ret; | |
2140 | ||
2141 | /* already determined to be invalid? */ | |
2142 | if (!result->enable) | |
2143 | return false; | |
2144 | ||
2145 | result->enable = result->pri_val <= max->pri && | |
2146 | result->spr_val <= max->spr && | |
2147 | result->cur_val <= max->cur; | |
2148 | ||
2149 | ret = result->enable; | |
2150 | ||
2151 | /* | |
2152 | * HACK until we can pre-compute everything, | |
2153 | * and thus fail gracefully if LP0 watermarks | |
2154 | * are exceeded... | |
2155 | */ | |
2156 | if (level == 0 && !result->enable) { | |
2157 | if (result->pri_val > max->pri) | |
2158 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2159 | level, result->pri_val, max->pri); | |
2160 | if (result->spr_val > max->spr) | |
2161 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2162 | level, result->spr_val, max->spr); | |
2163 | if (result->cur_val > max->cur) | |
2164 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2165 | level, result->cur_val, max->cur); | |
2166 | ||
2167 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2168 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2169 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2170 | result->enable = true; | |
2171 | } | |
2172 | ||
a9786a11 VS |
2173 | return ret; |
2174 | } | |
2175 | ||
d34ff9c6 | 2176 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 2177 | int level, |
820c1980 | 2178 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 2179 | struct intel_wm_level *result) |
6f5ddd17 VS |
2180 | { |
2181 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2182 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2183 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2184 | ||
2185 | /* WM1+ latency values stored in 0.5us units */ | |
2186 | if (level > 0) { | |
2187 | pri_latency *= 5; | |
2188 | spr_latency *= 5; | |
2189 | cur_latency *= 5; | |
2190 | } | |
2191 | ||
2192 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
2193 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
2194 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
2195 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
2196 | result->enable = true; | |
2197 | } | |
2198 | ||
801bcfff PZ |
2199 | static uint32_t |
2200 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
2201 | { |
2202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 2203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1011d8c4 | 2204 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
85a02deb | 2205 | u32 linetime, ips_linetime; |
1f8eeabf | 2206 | |
801bcfff PZ |
2207 | if (!intel_crtc_active(crtc)) |
2208 | return 0; | |
1011d8c4 | 2209 | |
1f8eeabf ED |
2210 | /* The WM are computed with base on how long it takes to fill a single |
2211 | * row at the given clock rate, multiplied by 8. | |
2212 | * */ | |
fec8cba3 JB |
2213 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
2214 | mode->crtc_clock); | |
2215 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 2216 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 2217 | |
801bcfff PZ |
2218 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2219 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2220 | } |
2221 | ||
12b134df VS |
2222 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2223 | { | |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2225 | ||
a42a5719 | 2226 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2227 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2228 | ||
2229 | wm[0] = (sskpd >> 56) & 0xFF; | |
2230 | if (wm[0] == 0) | |
2231 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2232 | wm[1] = (sskpd >> 4) & 0xFF; |
2233 | wm[2] = (sskpd >> 12) & 0xFF; | |
2234 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2235 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2236 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2237 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2238 | ||
2239 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2240 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2241 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2242 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2243 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2244 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2245 | ||
2246 | /* ILK primary LP0 latency is 700 ns */ | |
2247 | wm[0] = 7; | |
2248 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2249 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2250 | } |
2251 | } | |
2252 | ||
53615a5e VS |
2253 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2254 | { | |
2255 | /* ILK sprite LP0 latency is 1300 ns */ | |
2256 | if (INTEL_INFO(dev)->gen == 5) | |
2257 | wm[0] = 13; | |
2258 | } | |
2259 | ||
2260 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2261 | { | |
2262 | /* ILK cursor LP0 latency is 1300 ns */ | |
2263 | if (INTEL_INFO(dev)->gen == 5) | |
2264 | wm[0] = 13; | |
2265 | ||
2266 | /* WaDoubleCursorLP3Latency:ivb */ | |
2267 | if (IS_IVYBRIDGE(dev)) | |
2268 | wm[3] *= 2; | |
2269 | } | |
2270 | ||
546c81fd | 2271 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2272 | { |
26ec971e | 2273 | /* how many WM levels are we expecting */ |
a42a5719 | 2274 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ad0d6dc4 | 2275 | return 4; |
26ec971e | 2276 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2277 | return 3; |
26ec971e | 2278 | else |
ad0d6dc4 VS |
2279 | return 2; |
2280 | } | |
ad0d6dc4 VS |
2281 | static void intel_print_wm_latency(struct drm_device *dev, |
2282 | const char *name, | |
2283 | const uint16_t wm[5]) | |
2284 | { | |
2285 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2286 | |
2287 | for (level = 0; level <= max_level; level++) { | |
2288 | unsigned int latency = wm[level]; | |
2289 | ||
2290 | if (latency == 0) { | |
2291 | DRM_ERROR("%s WM%d latency not provided\n", | |
2292 | name, level); | |
2293 | continue; | |
2294 | } | |
2295 | ||
2296 | /* WM1+ latency values in 0.5us units */ | |
2297 | if (level > 0) | |
2298 | latency *= 5; | |
2299 | ||
2300 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2301 | name, level, wm[level], | |
2302 | latency / 10, latency % 10); | |
2303 | } | |
2304 | } | |
2305 | ||
e95a2f75 VS |
2306 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2307 | uint16_t wm[5], uint16_t min) | |
2308 | { | |
2309 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
2310 | ||
2311 | if (wm[0] >= min) | |
2312 | return false; | |
2313 | ||
2314 | wm[0] = max(wm[0], min); | |
2315 | for (level = 1; level <= max_level; level++) | |
2316 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2317 | ||
2318 | return true; | |
2319 | } | |
2320 | ||
2321 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2322 | { | |
2323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2324 | bool changed; | |
2325 | ||
2326 | /* | |
2327 | * The BIOS provided WM memory latency values are often | |
2328 | * inadequate for high resolution displays. Adjust them. | |
2329 | */ | |
2330 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2331 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2332 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2333 | ||
2334 | if (!changed) | |
2335 | return; | |
2336 | ||
2337 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2338 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2339 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2340 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2341 | } | |
2342 | ||
fa50ad61 | 2343 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2344 | { |
2345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2346 | ||
2347 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2348 | ||
2349 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2350 | sizeof(dev_priv->wm.pri_latency)); | |
2351 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2352 | sizeof(dev_priv->wm.pri_latency)); | |
2353 | ||
2354 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2355 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2356 | |
2357 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2358 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2359 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2360 | |
2361 | if (IS_GEN6(dev)) | |
2362 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2363 | } |
2364 | ||
820c1980 | 2365 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 2366 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 2367 | { |
7c4a395f VS |
2368 | struct drm_device *dev = crtc->dev; |
2369 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2370 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2371 | struct drm_plane *plane; |
1011d8c4 | 2372 | |
2a44b76b VS |
2373 | if (!intel_crtc_active(crtc)) |
2374 | return; | |
801bcfff | 2375 | |
2a44b76b VS |
2376 | p->active = true; |
2377 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; | |
2378 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); | |
2379 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; | |
2380 | p->cur.bytes_per_pixel = 4; | |
2381 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; | |
2382 | p->cur.horiz_pixels = intel_crtc->cursor_width; | |
2383 | /* TODO: for now, assume primary and cursor planes are always enabled. */ | |
2384 | p->pri.enabled = true; | |
2385 | p->cur.enabled = true; | |
7c4a395f | 2386 | |
af2b653b | 2387 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 2388 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 2389 | |
2a44b76b | 2390 | if (intel_plane->pipe == pipe) { |
7c4a395f | 2391 | p->spr = intel_plane->wm; |
2a44b76b VS |
2392 | break; |
2393 | } | |
2394 | } | |
2395 | } | |
2396 | ||
2397 | static void ilk_compute_wm_config(struct drm_device *dev, | |
2398 | struct intel_wm_config *config) | |
2399 | { | |
2400 | struct intel_crtc *intel_crtc; | |
2401 | ||
2402 | /* Compute the currently _active_ config */ | |
d3fcc808 | 2403 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 2404 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 2405 | |
2a44b76b VS |
2406 | if (!wm->pipe_enabled) |
2407 | continue; | |
cca32e9a | 2408 | |
2a44b76b VS |
2409 | config->sprites_enabled |= wm->sprites_enabled; |
2410 | config->sprites_scaled |= wm->sprites_scaled; | |
2411 | config->num_pipes_active++; | |
cca32e9a | 2412 | } |
801bcfff PZ |
2413 | } |
2414 | ||
0b2ae6d7 VS |
2415 | /* Compute new watermarks for the pipe */ |
2416 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2417 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2418 | struct intel_pipe_wm *pipe_wm) |
2419 | { | |
2420 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2421 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2422 | int level, max_level = ilk_wm_max_level(dev); |
2423 | /* LP0 watermark maximums depend on this pipe alone */ | |
2424 | struct intel_wm_config config = { | |
2425 | .num_pipes_active = 1, | |
2426 | .sprites_enabled = params->spr.enabled, | |
2427 | .sprites_scaled = params->spr.scaled, | |
2428 | }; | |
820c1980 | 2429 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2430 | |
2a44b76b VS |
2431 | pipe_wm->pipe_enabled = params->active; |
2432 | pipe_wm->sprites_enabled = params->spr.enabled; | |
2433 | pipe_wm->sprites_scaled = params->spr.scaled; | |
2434 | ||
7b39a0b7 VS |
2435 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2436 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2437 | max_level = 1; | |
2438 | ||
2439 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2440 | if (params->spr.scaled) | |
2441 | max_level = 0; | |
2442 | ||
a3cb4048 | 2443 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 2444 | |
a42a5719 | 2445 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2446 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2447 | |
a3cb4048 VS |
2448 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2449 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2450 | ||
0b2ae6d7 | 2451 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2452 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2453 | return false; | |
2454 | ||
2455 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2456 | ||
2457 | for (level = 1; level <= max_level; level++) { | |
2458 | struct intel_wm_level wm = {}; | |
2459 | ||
2460 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2461 | ||
2462 | /* | |
2463 | * Disable any watermark level that exceeds the | |
2464 | * register maximums since such watermarks are | |
2465 | * always invalid. | |
2466 | */ | |
2467 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2468 | break; | |
2469 | ||
2470 | pipe_wm->wm[level] = wm; | |
2471 | } | |
2472 | ||
2473 | return true; | |
0b2ae6d7 VS |
2474 | } |
2475 | ||
2476 | /* | |
2477 | * Merge the watermarks from all active pipes for a specific level. | |
2478 | */ | |
2479 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2480 | int level, | |
2481 | struct intel_wm_level *ret_wm) | |
2482 | { | |
2483 | const struct intel_crtc *intel_crtc; | |
2484 | ||
d52fea5b VS |
2485 | ret_wm->enable = true; |
2486 | ||
d3fcc808 | 2487 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2488 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2489 | const struct intel_wm_level *wm = &active->wm[level]; | |
2490 | ||
2491 | if (!active->pipe_enabled) | |
2492 | continue; | |
0b2ae6d7 | 2493 | |
d52fea5b VS |
2494 | /* |
2495 | * The watermark values may have been used in the past, | |
2496 | * so we must maintain them in the registers for some | |
2497 | * time even if the level is now disabled. | |
2498 | */ | |
0b2ae6d7 | 2499 | if (!wm->enable) |
d52fea5b | 2500 | ret_wm->enable = false; |
0b2ae6d7 VS |
2501 | |
2502 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2503 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2504 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2505 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2506 | } | |
0b2ae6d7 VS |
2507 | } |
2508 | ||
2509 | /* | |
2510 | * Merge all low power watermarks for all active pipes. | |
2511 | */ | |
2512 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2513 | const struct intel_wm_config *config, |
820c1980 | 2514 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2515 | struct intel_pipe_wm *merged) |
2516 | { | |
2517 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2518 | int last_enabled_level = max_level; |
0b2ae6d7 | 2519 | |
0ba22e26 VS |
2520 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2521 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2522 | config->num_pipes_active > 1) | |
2523 | return; | |
2524 | ||
6c8b6c28 VS |
2525 | /* ILK: FBC WM must be disabled always */ |
2526 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2527 | |
2528 | /* merge each WM1+ level */ | |
2529 | for (level = 1; level <= max_level; level++) { | |
2530 | struct intel_wm_level *wm = &merged->wm[level]; | |
2531 | ||
2532 | ilk_merge_wm_level(dev, level, wm); | |
2533 | ||
d52fea5b VS |
2534 | if (level > last_enabled_level) |
2535 | wm->enable = false; | |
2536 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2537 | /* make sure all following levels get disabled */ | |
2538 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2539 | |
2540 | /* | |
2541 | * The spec says it is preferred to disable | |
2542 | * FBC WMs instead of disabling a WM level. | |
2543 | */ | |
2544 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2545 | if (wm->enable) |
2546 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2547 | wm->fbc_val = 0; |
2548 | } | |
2549 | } | |
6c8b6c28 VS |
2550 | |
2551 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2552 | /* | |
2553 | * FIXME this is racy. FBC might get enabled later. | |
2554 | * What we should check here is whether FBC can be | |
2555 | * enabled sometime later. | |
2556 | */ | |
2557 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2558 | for (level = 2; level <= max_level; level++) { | |
2559 | struct intel_wm_level *wm = &merged->wm[level]; | |
2560 | ||
2561 | wm->enable = false; | |
2562 | } | |
2563 | } | |
0b2ae6d7 VS |
2564 | } |
2565 | ||
b380ca3c VS |
2566 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2567 | { | |
2568 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2569 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2570 | } | |
2571 | ||
a68d68ee VS |
2572 | /* The value we need to program into the WM_LPx latency field */ |
2573 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2574 | { | |
2575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2576 | ||
a42a5719 | 2577 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2578 | return 2 * level; |
2579 | else | |
2580 | return dev_priv->wm.pri_latency[level]; | |
2581 | } | |
2582 | ||
820c1980 | 2583 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2584 | const struct intel_pipe_wm *merged, |
609cedef | 2585 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2586 | struct ilk_wm_values *results) |
801bcfff | 2587 | { |
0b2ae6d7 VS |
2588 | struct intel_crtc *intel_crtc; |
2589 | int level, wm_lp; | |
cca32e9a | 2590 | |
0362c781 | 2591 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2592 | results->partitioning = partitioning; |
cca32e9a | 2593 | |
0b2ae6d7 | 2594 | /* LP1+ register values */ |
cca32e9a | 2595 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2596 | const struct intel_wm_level *r; |
801bcfff | 2597 | |
b380ca3c | 2598 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2599 | |
0362c781 | 2600 | r = &merged->wm[level]; |
cca32e9a | 2601 | |
d52fea5b VS |
2602 | /* |
2603 | * Maintain the watermark values even if the level is | |
2604 | * disabled. Doing otherwise could cause underruns. | |
2605 | */ | |
2606 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2607 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2608 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2609 | r->cur_val; | |
2610 | ||
d52fea5b VS |
2611 | if (r->enable) |
2612 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2613 | ||
416f4727 VS |
2614 | if (INTEL_INFO(dev)->gen >= 8) |
2615 | results->wm_lp[wm_lp - 1] |= | |
2616 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2617 | else | |
2618 | results->wm_lp[wm_lp - 1] |= | |
2619 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2620 | ||
d52fea5b VS |
2621 | /* |
2622 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2623 | * level is disabled. Doing otherwise could cause underruns. | |
2624 | */ | |
6cef2b8a VS |
2625 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2626 | WARN_ON(wm_lp != 1); | |
2627 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2628 | } else | |
2629 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2630 | } |
801bcfff | 2631 | |
0b2ae6d7 | 2632 | /* LP0 register values */ |
d3fcc808 | 2633 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2634 | enum pipe pipe = intel_crtc->pipe; |
2635 | const struct intel_wm_level *r = | |
2636 | &intel_crtc->wm.active.wm[0]; | |
2637 | ||
2638 | if (WARN_ON(!r->enable)) | |
2639 | continue; | |
2640 | ||
2641 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2642 | |
0b2ae6d7 VS |
2643 | results->wm_pipe[pipe] = |
2644 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2645 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2646 | r->cur_val; | |
801bcfff PZ |
2647 | } |
2648 | } | |
2649 | ||
861f3389 PZ |
2650 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2651 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2652 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2653 | struct intel_pipe_wm *r1, |
2654 | struct intel_pipe_wm *r2) | |
861f3389 | 2655 | { |
198a1e9b VS |
2656 | int level, max_level = ilk_wm_max_level(dev); |
2657 | int level1 = 0, level2 = 0; | |
861f3389 | 2658 | |
198a1e9b VS |
2659 | for (level = 1; level <= max_level; level++) { |
2660 | if (r1->wm[level].enable) | |
2661 | level1 = level; | |
2662 | if (r2->wm[level].enable) | |
2663 | level2 = level; | |
861f3389 PZ |
2664 | } |
2665 | ||
198a1e9b VS |
2666 | if (level1 == level2) { |
2667 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2668 | return r2; |
2669 | else | |
2670 | return r1; | |
198a1e9b | 2671 | } else if (level1 > level2) { |
861f3389 PZ |
2672 | return r1; |
2673 | } else { | |
2674 | return r2; | |
2675 | } | |
2676 | } | |
2677 | ||
49a687c4 VS |
2678 | /* dirty bits used to track which watermarks need changes */ |
2679 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2680 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2681 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2682 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2683 | #define WM_DIRTY_FBC (1 << 24) | |
2684 | #define WM_DIRTY_DDB (1 << 25) | |
2685 | ||
055e393f | 2686 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2687 | const struct ilk_wm_values *old, |
2688 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2689 | { |
2690 | unsigned int dirty = 0; | |
2691 | enum pipe pipe; | |
2692 | int wm_lp; | |
2693 | ||
055e393f | 2694 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2695 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2696 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2697 | /* Must disable LP1+ watermarks too */ | |
2698 | dirty |= WM_DIRTY_LP_ALL; | |
2699 | } | |
2700 | ||
2701 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2702 | dirty |= WM_DIRTY_PIPE(pipe); | |
2703 | /* Must disable LP1+ watermarks too */ | |
2704 | dirty |= WM_DIRTY_LP_ALL; | |
2705 | } | |
2706 | } | |
2707 | ||
2708 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2709 | dirty |= WM_DIRTY_FBC; | |
2710 | /* Must disable LP1+ watermarks too */ | |
2711 | dirty |= WM_DIRTY_LP_ALL; | |
2712 | } | |
2713 | ||
2714 | if (old->partitioning != new->partitioning) { | |
2715 | dirty |= WM_DIRTY_DDB; | |
2716 | /* Must disable LP1+ watermarks too */ | |
2717 | dirty |= WM_DIRTY_LP_ALL; | |
2718 | } | |
2719 | ||
2720 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2721 | if (dirty & WM_DIRTY_LP_ALL) | |
2722 | return dirty; | |
2723 | ||
2724 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2725 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2726 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2727 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2728 | break; | |
2729 | } | |
2730 | ||
2731 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2732 | for (; wm_lp <= 3; wm_lp++) | |
2733 | dirty |= WM_DIRTY_LP(wm_lp); | |
2734 | ||
2735 | return dirty; | |
2736 | } | |
2737 | ||
8553c18e VS |
2738 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2739 | unsigned int dirty) | |
801bcfff | 2740 | { |
820c1980 | 2741 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2742 | bool changed = false; |
801bcfff | 2743 | |
facd619b VS |
2744 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2745 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2746 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2747 | changed = true; |
facd619b VS |
2748 | } |
2749 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2750 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2751 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2752 | changed = true; |
facd619b VS |
2753 | } |
2754 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2755 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2756 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2757 | changed = true; |
facd619b | 2758 | } |
801bcfff | 2759 | |
facd619b VS |
2760 | /* |
2761 | * Don't touch WM1S_LP_EN here. | |
2762 | * Doing so could cause underruns. | |
2763 | */ | |
6cef2b8a | 2764 | |
8553c18e VS |
2765 | return changed; |
2766 | } | |
2767 | ||
2768 | /* | |
2769 | * The spec says we shouldn't write when we don't need, because every write | |
2770 | * causes WMs to be re-evaluated, expending some power. | |
2771 | */ | |
820c1980 ID |
2772 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2773 | struct ilk_wm_values *results) | |
8553c18e VS |
2774 | { |
2775 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2776 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2777 | unsigned int dirty; |
2778 | uint32_t val; | |
2779 | ||
055e393f | 2780 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2781 | if (!dirty) |
2782 | return; | |
2783 | ||
2784 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2785 | ||
49a687c4 | 2786 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2787 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2788 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2789 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2790 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2791 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2792 | ||
49a687c4 | 2793 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2794 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2795 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2796 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2797 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2798 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2799 | ||
49a687c4 | 2800 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2801 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2802 | val = I915_READ(WM_MISC); |
2803 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2804 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2805 | else | |
2806 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2807 | I915_WRITE(WM_MISC, val); | |
2808 | } else { | |
2809 | val = I915_READ(DISP_ARB_CTL2); | |
2810 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2811 | val &= ~DISP_DATA_PARTITION_5_6; | |
2812 | else | |
2813 | val |= DISP_DATA_PARTITION_5_6; | |
2814 | I915_WRITE(DISP_ARB_CTL2, val); | |
2815 | } | |
1011d8c4 PZ |
2816 | } |
2817 | ||
49a687c4 | 2818 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2819 | val = I915_READ(DISP_ARB_CTL); |
2820 | if (results->enable_fbc_wm) | |
2821 | val &= ~DISP_FBC_WM_DIS; | |
2822 | else | |
2823 | val |= DISP_FBC_WM_DIS; | |
2824 | I915_WRITE(DISP_ARB_CTL, val); | |
2825 | } | |
2826 | ||
954911eb ID |
2827 | if (dirty & WM_DIRTY_LP(1) && |
2828 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2829 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2830 | ||
2831 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2832 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2833 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2834 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2835 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2836 | } | |
801bcfff | 2837 | |
facd619b | 2838 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2839 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2840 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2841 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2842 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2843 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2844 | |
2845 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2846 | } |
2847 | ||
8553c18e VS |
2848 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2849 | { | |
2850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2851 | ||
2852 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2853 | } | |
2854 | ||
820c1980 | 2855 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 2856 | { |
7c4a395f | 2857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 2858 | struct drm_device *dev = crtc->dev; |
801bcfff | 2859 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
2860 | struct ilk_wm_maximums max; |
2861 | struct ilk_pipe_wm_parameters params = {}; | |
2862 | struct ilk_wm_values results = {}; | |
77c122bc | 2863 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 2864 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 2865 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 2866 | struct intel_wm_config config = {}; |
7c4a395f | 2867 | |
2a44b76b | 2868 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
2869 | |
2870 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
2871 | ||
2872 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
2873 | return; | |
861f3389 | 2874 | |
7c4a395f | 2875 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 2876 | |
2a44b76b VS |
2877 | ilk_compute_wm_config(dev, &config); |
2878 | ||
34982fe1 | 2879 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 2880 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
2881 | |
2882 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
2883 | if (INTEL_INFO(dev)->gen >= 7 && |
2884 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 2885 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 2886 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 2887 | |
820c1980 | 2888 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 2889 | } else { |
198a1e9b | 2890 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
2891 | } |
2892 | ||
198a1e9b | 2893 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 2894 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 2895 | |
820c1980 | 2896 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 2897 | |
820c1980 | 2898 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
2899 | } |
2900 | ||
ed57cb8a DL |
2901 | static void |
2902 | ilk_update_sprite_wm(struct drm_plane *plane, | |
2903 | struct drm_crtc *crtc, | |
2904 | uint32_t sprite_width, uint32_t sprite_height, | |
2905 | int pixel_size, bool enabled, bool scaled) | |
526682e9 | 2906 | { |
8553c18e | 2907 | struct drm_device *dev = plane->dev; |
adf3d35e | 2908 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 2909 | |
adf3d35e VS |
2910 | intel_plane->wm.enabled = enabled; |
2911 | intel_plane->wm.scaled = scaled; | |
2912 | intel_plane->wm.horiz_pixels = sprite_width; | |
ed57cb8a | 2913 | intel_plane->wm.vert_pixels = sprite_width; |
adf3d35e | 2914 | intel_plane->wm.bytes_per_pixel = pixel_size; |
526682e9 | 2915 | |
8553c18e VS |
2916 | /* |
2917 | * IVB workaround: must disable low power watermarks for at least | |
2918 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
2919 | * when scaling is disabled. | |
2920 | * | |
2921 | * WaCxSRDisabledForSpriteScaling:ivb | |
2922 | */ | |
2923 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
2924 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
2925 | ||
820c1980 | 2926 | ilk_update_wm(crtc); |
526682e9 PZ |
2927 | } |
2928 | ||
243e6a44 VS |
2929 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
2930 | { | |
2931 | struct drm_device *dev = crtc->dev; | |
2932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2933 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2934 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2935 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
2936 | enum pipe pipe = intel_crtc->pipe; | |
2937 | static const unsigned int wm0_pipe_reg[] = { | |
2938 | [PIPE_A] = WM0_PIPEA_ILK, | |
2939 | [PIPE_B] = WM0_PIPEB_ILK, | |
2940 | [PIPE_C] = WM0_PIPEC_IVB, | |
2941 | }; | |
2942 | ||
2943 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 2944 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2945 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 2946 | |
2a44b76b VS |
2947 | active->pipe_enabled = intel_crtc_active(crtc); |
2948 | ||
2949 | if (active->pipe_enabled) { | |
243e6a44 VS |
2950 | u32 tmp = hw->wm_pipe[pipe]; |
2951 | ||
2952 | /* | |
2953 | * For active pipes LP0 watermark is marked as | |
2954 | * enabled, and LP1+ watermaks as disabled since | |
2955 | * we can't really reverse compute them in case | |
2956 | * multiple pipes are active. | |
2957 | */ | |
2958 | active->wm[0].enable = true; | |
2959 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
2960 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
2961 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
2962 | active->linetime = hw->wm_linetime[pipe]; | |
2963 | } else { | |
2964 | int level, max_level = ilk_wm_max_level(dev); | |
2965 | ||
2966 | /* | |
2967 | * For inactive pipes, all watermark levels | |
2968 | * should be marked as enabled but zeroed, | |
2969 | * which is what we'd compute them to. | |
2970 | */ | |
2971 | for (level = 0; level <= max_level; level++) | |
2972 | active->wm[level].enable = true; | |
2973 | } | |
2974 | } | |
2975 | ||
2976 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
2977 | { | |
2978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2979 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2980 | struct drm_crtc *crtc; |
2981 | ||
70e1e0ec | 2982 | for_each_crtc(dev, crtc) |
243e6a44 VS |
2983 | ilk_pipe_wm_get_hw_state(crtc); |
2984 | ||
2985 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
2986 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
2987 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
2988 | ||
2989 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
2990 | if (INTEL_INFO(dev)->gen >= 7) { |
2991 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
2992 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
2993 | } | |
243e6a44 | 2994 | |
a42a5719 | 2995 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
2996 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
2997 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
2998 | else if (IS_IVYBRIDGE(dev)) | |
2999 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3000 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3001 | |
3002 | hw->enable_fbc_wm = | |
3003 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3004 | } | |
3005 | ||
b445e3b0 ED |
3006 | /** |
3007 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3008 | * | |
3009 | * Calculate watermark values for the various WM regs based on current mode | |
3010 | * and plane configuration. | |
3011 | * | |
3012 | * There are several cases to deal with here: | |
3013 | * - normal (i.e. non-self-refresh) | |
3014 | * - self-refresh (SR) mode | |
3015 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3016 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3017 | * lines), so need to account for TLB latency | |
3018 | * | |
3019 | * The normal calculation is: | |
3020 | * watermark = dotclock * bytes per pixel * latency | |
3021 | * where latency is platform & configuration dependent (we assume pessimal | |
3022 | * values here). | |
3023 | * | |
3024 | * The SR calculation is: | |
3025 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3026 | * bytes per pixel | |
3027 | * where | |
3028 | * line time = htotal / dotclock | |
3029 | * surface width = hdisplay for normal plane and 64 for cursor | |
3030 | * and latency is assumed to be high, as above. | |
3031 | * | |
3032 | * The final value programmed to the register should always be rounded up, | |
3033 | * and include an extra 2 entries to account for clock crossings. | |
3034 | * | |
3035 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3036 | * to set the non-SR watermarks to 8. | |
3037 | */ | |
46ba614c | 3038 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 3039 | { |
46ba614c | 3040 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
3041 | |
3042 | if (dev_priv->display.update_wm) | |
46ba614c | 3043 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
3044 | } |
3045 | ||
adf3d35e VS |
3046 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
3047 | struct drm_crtc *crtc, | |
ed57cb8a DL |
3048 | uint32_t sprite_width, |
3049 | uint32_t sprite_height, | |
3050 | int pixel_size, | |
39db4a4d | 3051 | bool enabled, bool scaled) |
b445e3b0 | 3052 | { |
adf3d35e | 3053 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
3054 | |
3055 | if (dev_priv->display.update_sprite_wm) | |
ed57cb8a DL |
3056 | dev_priv->display.update_sprite_wm(plane, crtc, |
3057 | sprite_width, sprite_height, | |
39db4a4d | 3058 | pixel_size, enabled, scaled); |
b445e3b0 ED |
3059 | } |
3060 | ||
2b4e57bd ED |
3061 | static struct drm_i915_gem_object * |
3062 | intel_alloc_context_page(struct drm_device *dev) | |
3063 | { | |
3064 | struct drm_i915_gem_object *ctx; | |
3065 | int ret; | |
3066 | ||
3067 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
3068 | ||
3069 | ctx = i915_gem_alloc_object(dev, 4096); | |
3070 | if (!ctx) { | |
3071 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
3072 | return NULL; | |
3073 | } | |
3074 | ||
c69766f2 | 3075 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
2b4e57bd ED |
3076 | if (ret) { |
3077 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
3078 | goto err_unref; | |
3079 | } | |
3080 | ||
3081 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
3082 | if (ret) { | |
3083 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
3084 | goto err_unpin; | |
3085 | } | |
3086 | ||
3087 | return ctx; | |
3088 | ||
3089 | err_unpin: | |
d7f46fc4 | 3090 | i915_gem_object_ggtt_unpin(ctx); |
2b4e57bd ED |
3091 | err_unref: |
3092 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
3093 | return NULL; |
3094 | } | |
3095 | ||
9270388e DV |
3096 | /** |
3097 | * Lock protecting IPS related data structures | |
9270388e DV |
3098 | */ |
3099 | DEFINE_SPINLOCK(mchdev_lock); | |
3100 | ||
3101 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3102 | * mchdev_lock. */ | |
3103 | static struct drm_i915_private *i915_mch_dev; | |
3104 | ||
2b4e57bd ED |
3105 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
3106 | { | |
3107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3108 | u16 rgvswctl; | |
3109 | ||
9270388e DV |
3110 | assert_spin_locked(&mchdev_lock); |
3111 | ||
2b4e57bd ED |
3112 | rgvswctl = I915_READ16(MEMSWCTL); |
3113 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3114 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3115 | return false; /* still busy with another command */ | |
3116 | } | |
3117 | ||
3118 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3119 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3120 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3121 | POSTING_READ16(MEMSWCTL); | |
3122 | ||
3123 | rgvswctl |= MEMCTL_CMD_STS; | |
3124 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3125 | ||
3126 | return true; | |
3127 | } | |
3128 | ||
8090c6b9 | 3129 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
3130 | { |
3131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3132 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3133 | u8 fmax, fmin, fstart, vstart; | |
3134 | ||
9270388e DV |
3135 | spin_lock_irq(&mchdev_lock); |
3136 | ||
2b4e57bd ED |
3137 | /* Enable temp reporting */ |
3138 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3139 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3140 | ||
3141 | /* 100ms RC evaluation intervals */ | |
3142 | I915_WRITE(RCUPEI, 100000); | |
3143 | I915_WRITE(RCDNEI, 100000); | |
3144 | ||
3145 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3146 | I915_WRITE(RCBMAXAVG, 90000); | |
3147 | I915_WRITE(RCBMINAVG, 80000); | |
3148 | ||
3149 | I915_WRITE(MEMIHYST, 1); | |
3150 | ||
3151 | /* Set up min, max, and cur for interrupt handling */ | |
3152 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3153 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3154 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3155 | MEMMODE_FSTART_SHIFT; | |
3156 | ||
3157 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3158 | PXVFREQ_PX_SHIFT; | |
3159 | ||
20e4d407 DV |
3160 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
3161 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 3162 | |
20e4d407 DV |
3163 | dev_priv->ips.max_delay = fstart; |
3164 | dev_priv->ips.min_delay = fmin; | |
3165 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
3166 | |
3167 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3168 | fmax, fmin, fstart); | |
3169 | ||
3170 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3171 | ||
3172 | /* | |
3173 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3174 | */ | |
3175 | ||
3176 | I915_WRITE(VIDSTART, vstart); | |
3177 | POSTING_READ(VIDSTART); | |
3178 | ||
3179 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3180 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3181 | ||
9270388e | 3182 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 3183 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 3184 | mdelay(1); |
2b4e57bd ED |
3185 | |
3186 | ironlake_set_drps(dev, fstart); | |
3187 | ||
20e4d407 | 3188 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 3189 | I915_READ(0x112e0); |
20e4d407 DV |
3190 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
3191 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
5ed0bdf2 | 3192 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
3193 | |
3194 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
3195 | } |
3196 | ||
8090c6b9 | 3197 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
3198 | { |
3199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
3200 | u16 rgvswctl; |
3201 | ||
3202 | spin_lock_irq(&mchdev_lock); | |
3203 | ||
3204 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
3205 | |
3206 | /* Ack interrupts, disable EFC interrupt */ | |
3207 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3208 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3209 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3210 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3211 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3212 | ||
3213 | /* Go back to the starting frequency */ | |
20e4d407 | 3214 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 3215 | mdelay(1); |
2b4e57bd ED |
3216 | rgvswctl |= MEMCTL_CMD_STS; |
3217 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 3218 | mdelay(1); |
2b4e57bd | 3219 | |
9270388e | 3220 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
3221 | } |
3222 | ||
acbe9475 DV |
3223 | /* There's a funny hw issue where the hw returns all 0 when reading from |
3224 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3225 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3226 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3227 | */ | |
6917c7b9 | 3228 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 3229 | { |
7b9e0ae6 | 3230 | u32 limits; |
2b4e57bd | 3231 | |
20b46e59 DV |
3232 | /* Only set the down limit when we've reached the lowest level to avoid |
3233 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3234 | * race in the hw when coming out of rc6: There's a tiny window where | |
3235 | * the hw runs at the minimal clock before selecting the desired | |
3236 | * frequency, if the down threshold expires in that window we will not | |
3237 | * receive a down interrupt. */ | |
b39fb297 BW |
3238 | limits = dev_priv->rps.max_freq_softlimit << 24; |
3239 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3240 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
3241 | |
3242 | return limits; | |
3243 | } | |
3244 | ||
dd75fdc8 CW |
3245 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
3246 | { | |
3247 | int new_power; | |
3248 | ||
c76bb61a DS |
3249 | if (dev_priv->rps.is_bdw_sw_turbo) |
3250 | return; | |
3251 | ||
dd75fdc8 CW |
3252 | new_power = dev_priv->rps.power; |
3253 | switch (dev_priv->rps.power) { | |
3254 | case LOW_POWER: | |
b39fb297 | 3255 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3256 | new_power = BETWEEN; |
3257 | break; | |
3258 | ||
3259 | case BETWEEN: | |
b39fb297 | 3260 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 3261 | new_power = LOW_POWER; |
b39fb297 | 3262 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3263 | new_power = HIGH_POWER; |
3264 | break; | |
3265 | ||
3266 | case HIGH_POWER: | |
b39fb297 | 3267 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3268 | new_power = BETWEEN; |
3269 | break; | |
3270 | } | |
3271 | /* Max/min bins are special */ | |
b39fb297 | 3272 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 3273 | new_power = LOW_POWER; |
b39fb297 | 3274 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
3275 | new_power = HIGH_POWER; |
3276 | if (new_power == dev_priv->rps.power) | |
3277 | return; | |
3278 | ||
3279 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3280 | switch (new_power) { | |
3281 | case LOW_POWER: | |
3282 | /* Upclock if more than 95% busy over 16ms */ | |
3283 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
3284 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
3285 | ||
3286 | /* Downclock if less than 85% busy over 32ms */ | |
3287 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3288 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
3289 | ||
3290 | I915_WRITE(GEN6_RP_CONTROL, | |
3291 | GEN6_RP_MEDIA_TURBO | | |
3292 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3293 | GEN6_RP_MEDIA_IS_GFX | | |
3294 | GEN6_RP_ENABLE | | |
3295 | GEN6_RP_UP_BUSY_AVG | | |
3296 | GEN6_RP_DOWN_IDLE_AVG); | |
3297 | break; | |
3298 | ||
3299 | case BETWEEN: | |
3300 | /* Upclock if more than 90% busy over 13ms */ | |
3301 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
3302 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
3303 | ||
3304 | /* Downclock if less than 75% busy over 32ms */ | |
3305 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3306 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
3307 | ||
3308 | I915_WRITE(GEN6_RP_CONTROL, | |
3309 | GEN6_RP_MEDIA_TURBO | | |
3310 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3311 | GEN6_RP_MEDIA_IS_GFX | | |
3312 | GEN6_RP_ENABLE | | |
3313 | GEN6_RP_UP_BUSY_AVG | | |
3314 | GEN6_RP_DOWN_IDLE_AVG); | |
3315 | break; | |
3316 | ||
3317 | case HIGH_POWER: | |
3318 | /* Upclock if more than 85% busy over 10ms */ | |
3319 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
3320 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
3321 | ||
3322 | /* Downclock if less than 60% busy over 32ms */ | |
3323 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3324 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
3325 | ||
3326 | I915_WRITE(GEN6_RP_CONTROL, | |
3327 | GEN6_RP_MEDIA_TURBO | | |
3328 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3329 | GEN6_RP_MEDIA_IS_GFX | | |
3330 | GEN6_RP_ENABLE | | |
3331 | GEN6_RP_UP_BUSY_AVG | | |
3332 | GEN6_RP_DOWN_IDLE_AVG); | |
3333 | break; | |
3334 | } | |
3335 | ||
3336 | dev_priv->rps.power = new_power; | |
3337 | dev_priv->rps.last_adj = 0; | |
3338 | } | |
3339 | ||
2876ce73 CW |
3340 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
3341 | { | |
3342 | u32 mask = 0; | |
3343 | ||
3344 | if (val > dev_priv->rps.min_freq_softlimit) | |
3345 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
3346 | if (val < dev_priv->rps.max_freq_softlimit) | |
3347 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
3348 | ||
7b3c29f6 CW |
3349 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
3350 | mask &= dev_priv->pm_rps_events; | |
3351 | ||
2876ce73 CW |
3352 | /* IVB and SNB hard hangs on looping batchbuffer |
3353 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
3354 | */ | |
3355 | if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) | |
3356 | mask |= GEN6_PM_RP_UP_EI_EXPIRED; | |
3357 | ||
baccd458 D |
3358 | if (IS_GEN8(dev_priv->dev)) |
3359 | mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
3360 | ||
2876ce73 CW |
3361 | return ~mask; |
3362 | } | |
3363 | ||
b8a5ff8d JM |
3364 | /* gen6_set_rps is called to update the frequency request, but should also be |
3365 | * called when the range (min_delay and max_delay) is modified so that we can | |
3366 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
20b46e59 DV |
3367 | void gen6_set_rps(struct drm_device *dev, u8 val) |
3368 | { | |
3369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 3370 | |
4fc688ce | 3371 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3372 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3373 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 3374 | |
eb64cad1 CW |
3375 | /* min/max delay may still have been modified so be sure to |
3376 | * write the limits value. | |
3377 | */ | |
3378 | if (val != dev_priv->rps.cur_freq) { | |
3379 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 3380 | |
50e6a2a7 | 3381 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
eb64cad1 CW |
3382 | I915_WRITE(GEN6_RPNSWREQ, |
3383 | HSW_FREQUENCY(val)); | |
3384 | else | |
3385 | I915_WRITE(GEN6_RPNSWREQ, | |
3386 | GEN6_FREQUENCY(val) | | |
3387 | GEN6_OFFSET(0) | | |
3388 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 3389 | } |
7b9e0ae6 | 3390 | |
7b9e0ae6 CW |
3391 | /* Make sure we continue to get interrupts |
3392 | * until we hit the minimum or maximum frequencies. | |
3393 | */ | |
eb64cad1 | 3394 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
2876ce73 | 3395 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 3396 | |
d5570a72 BW |
3397 | POSTING_READ(GEN6_RPNSWREQ); |
3398 | ||
b39fb297 | 3399 | dev_priv->rps.cur_freq = val; |
be2cde9a | 3400 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
3401 | } |
3402 | ||
76c3552f D |
3403 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
3404 | * | |
3405 | * * If Gfx is Idle, then | |
3406 | * 1. Mask Turbo interrupts | |
3407 | * 2. Bring up Gfx clock | |
3408 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3409 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3410 | * 5. Unmask Turbo interrupts | |
3411 | */ | |
3412 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
3413 | { | |
5549d25f D |
3414 | struct drm_device *dev = dev_priv->dev; |
3415 | ||
3416 | /* Latest VLV doesn't need to force the gfx clock */ | |
3417 | if (dev->pdev->revision >= 0xd) { | |
3418 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3419 | return; | |
3420 | } | |
3421 | ||
76c3552f D |
3422 | /* |
3423 | * When we are idle. Drop to min voltage state. | |
3424 | */ | |
3425 | ||
b39fb297 | 3426 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
3427 | return; |
3428 | ||
3429 | /* Mask turbo interrupt so that they will not come in between */ | |
3430 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
3431 | ||
650ad970 | 3432 | vlv_force_gfx_clock(dev_priv, true); |
76c3552f | 3433 | |
b39fb297 | 3434 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
3435 | |
3436 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 3437 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
3438 | |
3439 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
3440 | & GENFREQSTATUS) == 0, 5)) | |
3441 | DRM_ERROR("timed out waiting for Punit\n"); | |
3442 | ||
650ad970 | 3443 | vlv_force_gfx_clock(dev_priv, false); |
76c3552f | 3444 | |
2876ce73 CW |
3445 | I915_WRITE(GEN6_PMINTRMSK, |
3446 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
76c3552f D |
3447 | } |
3448 | ||
b29c19b6 CW |
3449 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
3450 | { | |
691bb717 DL |
3451 | struct drm_device *dev = dev_priv->dev; |
3452 | ||
b29c19b6 | 3453 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3454 | if (dev_priv->rps.enabled) { |
34638118 D |
3455 | if (IS_CHERRYVIEW(dev)) |
3456 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3457 | else if (IS_VALLEYVIEW(dev)) | |
76c3552f | 3458 | vlv_set_rps_idle(dev_priv); |
c76bb61a DS |
3459 | else if (!dev_priv->rps.is_bdw_sw_turbo |
3460 | || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){ | |
b39fb297 | 3461 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c76bb61a DS |
3462 | } |
3463 | ||
c0951f0c CW |
3464 | dev_priv->rps.last_adj = 0; |
3465 | } | |
b29c19b6 CW |
3466 | mutex_unlock(&dev_priv->rps.hw_lock); |
3467 | } | |
3468 | ||
3469 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
3470 | { | |
691bb717 DL |
3471 | struct drm_device *dev = dev_priv->dev; |
3472 | ||
b29c19b6 | 3473 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3474 | if (dev_priv->rps.enabled) { |
691bb717 | 3475 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3476 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c76bb61a DS |
3477 | else if (!dev_priv->rps.is_bdw_sw_turbo |
3478 | || atomic_read(&dev_priv->rps.sw_turbo.flip_received)){ | |
b39fb297 | 3479 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c76bb61a DS |
3480 | } |
3481 | ||
c0951f0c CW |
3482 | dev_priv->rps.last_adj = 0; |
3483 | } | |
b29c19b6 CW |
3484 | mutex_unlock(&dev_priv->rps.hw_lock); |
3485 | } | |
3486 | ||
0a073b84 JB |
3487 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
3488 | { | |
3489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a67092a | 3490 | |
0a073b84 | 3491 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3492 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3493 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
0a073b84 | 3494 | |
73008b98 | 3495 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
b39fb297 BW |
3496 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
3497 | dev_priv->rps.cur_freq, | |
2ec3815f | 3498 | vlv_gpu_freq(dev_priv, val), val); |
0a073b84 | 3499 | |
1c14762d VS |
3500 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
3501 | "Odd GPU freq value\n")) | |
3502 | val &= ~1; | |
3503 | ||
2876ce73 CW |
3504 | if (val != dev_priv->rps.cur_freq) |
3505 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
0a073b84 | 3506 | |
09c87db8 | 3507 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
0a073b84 | 3508 | |
b39fb297 | 3509 | dev_priv->rps.cur_freq = val; |
2ec3815f | 3510 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
3511 | } |
3512 | ||
0961021a BW |
3513 | static void gen8_disable_rps_interrupts(struct drm_device *dev) |
3514 | { | |
3515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c76bb61a DS |
3516 | if (IS_BROADWELL(dev) && dev_priv->rps.is_bdw_sw_turbo){ |
3517 | if (atomic_read(&dev_priv->rps.sw_turbo.flip_received)) | |
3518 | del_timer(&dev_priv->rps.sw_turbo.flip_timer); | |
3519 | dev_priv-> rps.is_bdw_sw_turbo = false; | |
3520 | } else { | |
3521 | I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); | |
3522 | I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) & | |
3523 | ~dev_priv->pm_rps_events); | |
3524 | /* Complete PM interrupt masking here doesn't race with the rps work | |
3525 | * item again unmasking PM interrupts because that is using a different | |
3526 | * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in | |
3527 | * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which | |
3528 | * gen8_enable_rps will clean up. */ | |
3529 | ||
3530 | spin_lock_irq(&dev_priv->irq_lock); | |
3531 | dev_priv->rps.pm_iir = 0; | |
3532 | spin_unlock_irq(&dev_priv->irq_lock); | |
3533 | ||
3534 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); | |
3535 | } | |
0961021a BW |
3536 | } |
3537 | ||
44fc7d5c | 3538 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
2b4e57bd ED |
3539 | { |
3540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3541 | ||
2b4e57bd | 3542 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
a6706b45 D |
3543 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
3544 | ~dev_priv->pm_rps_events); | |
2b4e57bd ED |
3545 | /* Complete PM interrupt masking here doesn't race with the rps work |
3546 | * item again unmasking PM interrupts because that is using a different | |
3547 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
3548 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
3549 | ||
59cdb63d | 3550 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 | 3551 | dev_priv->rps.pm_iir = 0; |
59cdb63d | 3552 | spin_unlock_irq(&dev_priv->irq_lock); |
2b4e57bd | 3553 | |
a6706b45 | 3554 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
2b4e57bd ED |
3555 | } |
3556 | ||
44fc7d5c | 3557 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
3558 | { |
3559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3560 | ||
3561 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 3562 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
d20d4f0c | 3563 | |
0961021a BW |
3564 | if (IS_BROADWELL(dev)) |
3565 | gen8_disable_rps_interrupts(dev); | |
3566 | else | |
3567 | gen6_disable_rps_interrupts(dev); | |
44fc7d5c DV |
3568 | } |
3569 | ||
38807746 D |
3570 | static void cherryview_disable_rps(struct drm_device *dev) |
3571 | { | |
3572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3573 | ||
3574 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3497a562 D |
3575 | |
3576 | gen8_disable_rps_interrupts(dev); | |
38807746 D |
3577 | } |
3578 | ||
44fc7d5c DV |
3579 | static void valleyview_disable_rps(struct drm_device *dev) |
3580 | { | |
3581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3582 | ||
98a2e5f9 D |
3583 | /* we're doing forcewake before Disabling RC6, |
3584 | * This what the BIOS expects when going into suspend */ | |
3585 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
3586 | ||
44fc7d5c | 3587 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 3588 | |
98a2e5f9 D |
3589 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
3590 | ||
44fc7d5c | 3591 | gen6_disable_rps_interrupts(dev); |
d20d4f0c JB |
3592 | } |
3593 | ||
dc39fff7 BW |
3594 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
3595 | { | |
91ca689a ID |
3596 | if (IS_VALLEYVIEW(dev)) { |
3597 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
3598 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
3599 | else | |
3600 | mode = 0; | |
3601 | } | |
8dfd1f04 DV |
3602 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
3603 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
3604 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
3605 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
3606 | } |
3607 | ||
e6069ca8 | 3608 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 3609 | { |
eb4926e4 DL |
3610 | /* No RC6 before Ironlake */ |
3611 | if (INTEL_INFO(dev)->gen < 5) | |
3612 | return 0; | |
3613 | ||
e6069ca8 ID |
3614 | /* RC6 is only on Ironlake mobile not on desktop */ |
3615 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
3616 | return 0; | |
3617 | ||
456470eb | 3618 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
3619 | if (enable_rc6 >= 0) { |
3620 | int mask; | |
3621 | ||
3622 | if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
3623 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | | |
3624 | INTEL_RC6pp_ENABLE; | |
3625 | else | |
3626 | mask = INTEL_RC6_ENABLE; | |
3627 | ||
3628 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
3629 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
3630 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
3631 | |
3632 | return enable_rc6 & mask; | |
3633 | } | |
2b4e57bd | 3634 | |
6567d748 CW |
3635 | /* Disable RC6 on Ironlake */ |
3636 | if (INTEL_INFO(dev)->gen == 5) | |
3637 | return 0; | |
2b4e57bd | 3638 | |
8bade1ad | 3639 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 3640 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
3641 | |
3642 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
3643 | } |
3644 | ||
e6069ca8 ID |
3645 | int intel_enable_rc6(const struct drm_device *dev) |
3646 | { | |
3647 | return i915.enable_rc6; | |
3648 | } | |
3649 | ||
0961021a BW |
3650 | static void gen8_enable_rps_interrupts(struct drm_device *dev) |
3651 | { | |
3652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3653 | ||
3654 | spin_lock_irq(&dev_priv->irq_lock); | |
3655 | WARN_ON(dev_priv->rps.pm_iir); | |
480c8033 | 3656 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a BW |
3657 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); |
3658 | spin_unlock_irq(&dev_priv->irq_lock); | |
3659 | } | |
3660 | ||
44fc7d5c DV |
3661 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
3662 | { | |
3663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3664 | ||
3665 | spin_lock_irq(&dev_priv->irq_lock); | |
a0b3335a | 3666 | WARN_ON(dev_priv->rps.pm_iir); |
480c8033 | 3667 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
a6706b45 | 3668 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
44fc7d5c | 3669 | spin_unlock_irq(&dev_priv->irq_lock); |
44fc7d5c DV |
3670 | } |
3671 | ||
3280e8b0 BW |
3672 | static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) |
3673 | { | |
3674 | /* All of these values are in units of 50MHz */ | |
3675 | dev_priv->rps.cur_freq = 0; | |
3676 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ | |
3677 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
3678 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
3679 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
3680 | /* XXX: only BYT has a special efficient freq */ | |
3681 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; | |
3682 | /* hw_max = RP0 until we check for overclocking */ | |
3683 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
3684 | ||
3685 | /* Preserve min/max settings in case of re-init */ | |
3686 | if (dev_priv->rps.max_freq_softlimit == 0) | |
3687 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
3688 | ||
3689 | if (dev_priv->rps.min_freq_softlimit == 0) | |
3690 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
3691 | } | |
3692 | ||
c76bb61a DS |
3693 | static void bdw_sw_calculate_freq(struct drm_device *dev, |
3694 | struct intel_rps_bdw_cal *c, u32 *cur_time, u32 *c0) | |
3695 | { | |
3696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3697 | u64 busy = 0; | |
3698 | u32 busyness_pct = 0; | |
3699 | u32 elapsed_time = 0; | |
3700 | u16 new_freq = 0; | |
3701 | ||
3702 | if (!c || !cur_time || !c0) | |
3703 | return; | |
3704 | ||
3705 | if (0 == c->last_c0) | |
3706 | goto out; | |
3707 | ||
3708 | /* Check Evaluation interval */ | |
3709 | elapsed_time = *cur_time - c->last_ts; | |
3710 | if (elapsed_time < c->eval_interval) | |
3711 | return; | |
3712 | ||
3713 | mutex_lock(&dev_priv->rps.hw_lock); | |
3714 | ||
3715 | /* | |
3716 | * c0 unit in 32*1.28 usec, elapsed_time unit in 1 usec. | |
3717 | * Whole busyness_pct calculation should be | |
3718 | * busy = ((u64)(*c0 - c->last_c0) << 5 << 7) / 100; | |
3719 | * busyness_pct = (u32)(busy * 100 / elapsed_time); | |
3720 | * The final formula is to simplify CPU calculation | |
3721 | */ | |
3722 | busy = (u64)(*c0 - c->last_c0) << 12; | |
3723 | do_div(busy, elapsed_time); | |
3724 | busyness_pct = (u32)busy; | |
3725 | ||
3726 | if (c->is_up && busyness_pct >= c->it_threshold_pct) | |
3727 | new_freq = (u16)dev_priv->rps.cur_freq + 3; | |
3728 | if (!c->is_up && busyness_pct <= c->it_threshold_pct) | |
3729 | new_freq = (u16)dev_priv->rps.cur_freq - 1; | |
3730 | ||
3731 | /* Adjust to new frequency busyness and compare with threshold */ | |
3732 | if (0 != new_freq) { | |
3733 | if (new_freq > dev_priv->rps.max_freq_softlimit) | |
3734 | new_freq = dev_priv->rps.max_freq_softlimit; | |
3735 | else if (new_freq < dev_priv->rps.min_freq_softlimit) | |
3736 | new_freq = dev_priv->rps.min_freq_softlimit; | |
3737 | ||
3738 | gen6_set_rps(dev, new_freq); | |
3739 | } | |
3740 | ||
3741 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3742 | ||
3743 | out: | |
3744 | c->last_c0 = *c0; | |
3745 | c->last_ts = *cur_time; | |
3746 | } | |
3747 | ||
3748 | static void gen8_set_frequency_RP0(struct work_struct *work) | |
3749 | { | |
3750 | struct intel_rps_bdw_turbo *p_bdw_turbo = | |
3751 | container_of(work, struct intel_rps_bdw_turbo, work_max_freq); | |
3752 | struct intel_gen6_power_mgmt *p_power_mgmt = | |
3753 | container_of(p_bdw_turbo, struct intel_gen6_power_mgmt, sw_turbo); | |
3754 | struct drm_i915_private *dev_priv = | |
3755 | container_of(p_power_mgmt, struct drm_i915_private, rps); | |
3756 | ||
3757 | mutex_lock(&dev_priv->rps.hw_lock); | |
3758 | gen6_set_rps(dev_priv->dev, dev_priv->rps.rp0_freq); | |
3759 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3760 | } | |
3761 | ||
3762 | static void flip_active_timeout_handler(unsigned long var) | |
3763 | { | |
3764 | struct drm_i915_private *dev_priv = (struct drm_i915_private *) var; | |
3765 | ||
3766 | del_timer(&dev_priv->rps.sw_turbo.flip_timer); | |
3767 | atomic_set(&dev_priv->rps.sw_turbo.flip_received, false); | |
3768 | ||
3769 | queue_work(dev_priv->wq, &dev_priv->rps.sw_turbo.work_max_freq); | |
3770 | } | |
3771 | ||
3772 | void bdw_software_turbo(struct drm_device *dev) | |
3773 | { | |
3774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3775 | ||
3776 | u32 current_time = I915_READ(TIMESTAMP_CTR); /* unit in usec */ | |
3777 | u32 current_c0 = I915_READ(MCHBAR_PCU_C0); /* unit in 32*1.28 usec */ | |
3778 | ||
3779 | bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.up, | |
3780 | ¤t_time, ¤t_c0); | |
3781 | bdw_sw_calculate_freq(dev, &dev_priv->rps.sw_turbo.down, | |
3782 | ¤t_time, ¤t_c0); | |
3783 | } | |
3784 | ||
6edee7f3 BW |
3785 | static void gen8_enable_rps(struct drm_device *dev) |
3786 | { | |
3787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 3788 | struct intel_engine_cs *ring; |
6edee7f3 | 3789 | uint32_t rc6_mask = 0, rp_state_cap; |
c76bb61a DS |
3790 | uint32_t threshold_up_pct, threshold_down_pct; |
3791 | uint32_t ei_up, ei_down; /* up and down evaluation interval */ | |
3792 | u32 rp_ctl_flag; | |
6edee7f3 BW |
3793 | int unused; |
3794 | ||
c76bb61a DS |
3795 | /* Use software Turbo for BDW */ |
3796 | dev_priv->rps.is_bdw_sw_turbo = IS_BROADWELL(dev); | |
3797 | ||
6edee7f3 BW |
3798 | /* 1a: Software RC state - RC0 */ |
3799 | I915_WRITE(GEN6_RC_STATE, 0); | |
3800 | ||
3801 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
3802 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
c8d9a590 | 3803 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3804 | |
3805 | /* 2a: Disable RC states. */ | |
3806 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3807 | ||
3808 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3280e8b0 | 3809 | parse_rp_state_cap(dev_priv, rp_state_cap); |
6edee7f3 BW |
3810 | |
3811 | /* 2b: Program RC6 thresholds.*/ | |
3812 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
3813 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
3814 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3815 | for_each_ring(ring, dev_priv, unused) | |
3816 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
3817 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
3818 | if (IS_BROADWELL(dev)) |
3819 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
3820 | else | |
3821 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
3822 | |
3823 | /* 3: Enable RC6 */ | |
3824 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
3825 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 3826 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
3827 | if (IS_BROADWELL(dev)) |
3828 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
3829 | GEN7_RC_CTL_TO_MODE | | |
3830 | rc6_mask); | |
3831 | else | |
3832 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
3833 | GEN6_RC_CTL_EI_MODE(1) | | |
3834 | rc6_mask); | |
6edee7f3 BW |
3835 | |
3836 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
3837 | I915_WRITE(GEN6_RPNSWREQ, |
3838 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
3839 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
3840 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
c76bb61a DS |
3841 | ei_up = 84480; /* 84.48ms */ |
3842 | ei_down = 448000; | |
3843 | threshold_up_pct = 90; /* x percent busy */ | |
3844 | threshold_down_pct = 70; | |
3845 | ||
3846 | if (dev_priv->rps.is_bdw_sw_turbo) { | |
3847 | dev_priv->rps.sw_turbo.up.it_threshold_pct = threshold_up_pct; | |
3848 | dev_priv->rps.sw_turbo.up.eval_interval = ei_up; | |
3849 | dev_priv->rps.sw_turbo.up.is_up = true; | |
3850 | dev_priv->rps.sw_turbo.up.last_ts = 0; | |
3851 | dev_priv->rps.sw_turbo.up.last_c0 = 0; | |
3852 | ||
3853 | dev_priv->rps.sw_turbo.down.it_threshold_pct = threshold_down_pct; | |
3854 | dev_priv->rps.sw_turbo.down.eval_interval = ei_down; | |
3855 | dev_priv->rps.sw_turbo.down.is_up = false; | |
3856 | dev_priv->rps.sw_turbo.down.last_ts = 0; | |
3857 | dev_priv->rps.sw_turbo.down.last_c0 = 0; | |
3858 | ||
3859 | /* Start the timer to track if flip comes*/ | |
3860 | dev_priv->rps.sw_turbo.timeout = 200*1000; /* in us */ | |
3861 | ||
3862 | init_timer(&dev_priv->rps.sw_turbo.flip_timer); | |
3863 | dev_priv->rps.sw_turbo.flip_timer.function = flip_active_timeout_handler; | |
3864 | dev_priv->rps.sw_turbo.flip_timer.data = (unsigned long) dev_priv; | |
3865 | dev_priv->rps.sw_turbo.flip_timer.expires = | |
3866 | usecs_to_jiffies(dev_priv->rps.sw_turbo.timeout) + jiffies; | |
3867 | add_timer(&dev_priv->rps.sw_turbo.flip_timer); | |
3868 | INIT_WORK(&dev_priv->rps.sw_turbo.work_max_freq, gen8_set_frequency_RP0); | |
3869 | ||
3870 | atomic_set(&dev_priv->rps.sw_turbo.flip_received, true); | |
3871 | } else { | |
3872 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent | |
3873 | * 1 second timeout*/ | |
3874 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, FREQ_1_28_US(1000000)); | |
3875 | ||
3876 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
3877 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
3878 | dev_priv->rps.max_freq_softlimit << 24 | | |
3879 | dev_priv->rps.min_freq_softlimit << 16); | |
3880 | ||
3881 | I915_WRITE(GEN6_RP_UP_THRESHOLD, | |
3882 | FREQ_1_28_US(ei_up * threshold_up_pct / 100)); | |
3883 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, | |
3884 | FREQ_1_28_US(ei_down * threshold_down_pct / 100)); | |
3885 | I915_WRITE(GEN6_RP_UP_EI, | |
3886 | FREQ_1_28_US(ei_up)); | |
3887 | I915_WRITE(GEN6_RP_DOWN_EI, | |
3888 | FREQ_1_28_US(ei_down)); | |
3889 | ||
3890 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
3891 | } | |
6edee7f3 BW |
3892 | |
3893 | /* 5: Enable RPS */ | |
c76bb61a DS |
3894 | rp_ctl_flag = GEN6_RP_MEDIA_TURBO | |
3895 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3896 | GEN6_RP_MEDIA_IS_GFX | | |
3897 | GEN6_RP_UP_BUSY_AVG | | |
3898 | GEN6_RP_DOWN_IDLE_AVG; | |
3899 | if (!dev_priv->rps.is_bdw_sw_turbo) | |
3900 | rp_ctl_flag |= GEN6_RP_ENABLE; | |
3901 | ||
3902 | I915_WRITE(GEN6_RP_CONTROL, rp_ctl_flag); | |
3903 | ||
3904 | /* 6: Ring frequency + overclocking | |
3905 | * (our driver does this later */ | |
6edee7f3 | 3906 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); |
c76bb61a DS |
3907 | if (!dev_priv->rps.is_bdw_sw_turbo) |
3908 | gen8_enable_rps_interrupts(dev); | |
6edee7f3 | 3909 | |
c8d9a590 | 3910 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3911 | } |
3912 | ||
79f5b2c7 | 3913 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 3914 | { |
79f5b2c7 | 3915 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3916 | struct intel_engine_cs *ring; |
2a5913a8 | 3917 | u32 rp_state_cap; |
d060c169 | 3918 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 3919 | u32 gtfifodbg; |
2b4e57bd | 3920 | int rc6_mode; |
42c0526c | 3921 | int i, ret; |
2b4e57bd | 3922 | |
4fc688ce | 3923 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 3924 | |
2b4e57bd ED |
3925 | /* Here begins a magic sequence of register writes to enable |
3926 | * auto-downclocking. | |
3927 | * | |
3928 | * Perhaps there might be some value in exposing these to | |
3929 | * userspace... | |
3930 | */ | |
3931 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
3932 | |
3933 | /* Clear the DBG now so we don't confuse earlier errors */ | |
3934 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
3935 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
3936 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
3937 | } | |
3938 | ||
c8d9a590 | 3939 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 3940 | |
7b9e0ae6 | 3941 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
7b9e0ae6 | 3942 | |
3280e8b0 | 3943 | parse_rp_state_cap(dev_priv, rp_state_cap); |
dd0a1aa1 | 3944 | |
2b4e57bd ED |
3945 | /* disable the counters and set deterministic thresholds */ |
3946 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3947 | ||
3948 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
3949 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
3950 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
3951 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
3952 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
3953 | ||
b4519513 CW |
3954 | for_each_ring(ring, dev_priv, i) |
3955 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
3956 | |
3957 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
3958 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 3959 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
3960 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
3961 | else | |
3962 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 3963 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
3964 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
3965 | ||
5a7dc92a | 3966 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
3967 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
3968 | if (rc6_mode & INTEL_RC6_ENABLE) | |
3969 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
3970 | ||
5a7dc92a ED |
3971 | /* We don't use those on Haswell */ |
3972 | if (!IS_HASWELL(dev)) { | |
3973 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
3974 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 3975 | |
5a7dc92a ED |
3976 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
3977 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
3978 | } | |
2b4e57bd | 3979 | |
dc39fff7 | 3980 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
3981 | |
3982 | I915_WRITE(GEN6_RC_CONTROL, | |
3983 | rc6_mask | | |
3984 | GEN6_RC_CTL_EI_MODE(1) | | |
3985 | GEN6_RC_CTL_HW_ENABLE); | |
3986 | ||
dd75fdc8 CW |
3987 | /* Power down if completely idle for over 50ms */ |
3988 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 3989 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 3990 | |
42c0526c | 3991 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 3992 | if (ret) |
42c0526c | 3993 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
3994 | |
3995 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
3996 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
3997 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 3998 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 3999 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4000 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4001 | } |
4002 | ||
dd75fdc8 | 4003 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 4004 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 4005 | |
44fc7d5c | 4006 | gen6_enable_rps_interrupts(dev); |
2b4e57bd | 4007 | |
31643d54 BW |
4008 | rc6vids = 0; |
4009 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4010 | if (IS_GEN6(dev) && ret) { | |
4011 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4012 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4013 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4014 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4015 | rc6vids &= 0xffff00; | |
4016 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4017 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4018 | if (ret) | |
4019 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4020 | } | |
4021 | ||
c8d9a590 | 4022 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4023 | } |
4024 | ||
c2bc2fc5 | 4025 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4026 | { |
79f5b2c7 | 4027 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4028 | int min_freq = 15; |
3ebecd07 CW |
4029 | unsigned int gpu_freq; |
4030 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 4031 | int scaling_factor = 180; |
eda79642 | 4032 | struct cpufreq_policy *policy; |
2b4e57bd | 4033 | |
4fc688ce | 4034 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4035 | |
eda79642 BW |
4036 | policy = cpufreq_cpu_get(0); |
4037 | if (policy) { | |
4038 | max_ia_freq = policy->cpuinfo.max_freq; | |
4039 | cpufreq_cpu_put(policy); | |
4040 | } else { | |
4041 | /* | |
4042 | * Default to measured freq if none found, PCU will ensure we | |
4043 | * don't go over | |
4044 | */ | |
2b4e57bd | 4045 | max_ia_freq = tsc_khz; |
eda79642 | 4046 | } |
2b4e57bd ED |
4047 | |
4048 | /* Convert from kHz to MHz */ | |
4049 | max_ia_freq /= 1000; | |
4050 | ||
153b4b95 | 4051 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4052 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4053 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4054 | |
2b4e57bd ED |
4055 | /* |
4056 | * For each potential GPU frequency, load a ring frequency we'd like | |
4057 | * to use for memory access. We do this by specifying the IA frequency | |
4058 | * the PCU should use as a reference to determine the ring frequency. | |
4059 | */ | |
b39fb297 | 4060 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
2b4e57bd | 4061 | gpu_freq--) { |
b39fb297 | 4062 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
3ebecd07 CW |
4063 | unsigned int ia_freq = 0, ring_freq = 0; |
4064 | ||
46c764d4 BW |
4065 | if (INTEL_INFO(dev)->gen >= 8) { |
4066 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4067 | ring_freq = max(min_ring_freq, gpu_freq); | |
4068 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4069 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4070 | ring_freq = max(min_ring_freq, ring_freq); |
4071 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4072 | } else { | |
4073 | /* On older processors, there is no separate ring | |
4074 | * clock domain, so in order to boost the bandwidth | |
4075 | * of the ring, we need to upclock the CPU (ia_freq). | |
4076 | * | |
4077 | * For GPU frequencies less than 750MHz, | |
4078 | * just use the lowest ring freq. | |
4079 | */ | |
4080 | if (gpu_freq < min_freq) | |
4081 | ia_freq = 800; | |
4082 | else | |
4083 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4084 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4085 | } | |
2b4e57bd | 4086 | |
42c0526c BW |
4087 | sandybridge_pcode_write(dev_priv, |
4088 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4089 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4090 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4091 | gpu_freq); | |
2b4e57bd | 4092 | } |
2b4e57bd ED |
4093 | } |
4094 | ||
c2bc2fc5 ID |
4095 | void gen6_update_ring_freq(struct drm_device *dev) |
4096 | { | |
4097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4098 | ||
4099 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4100 | return; | |
4101 | ||
4102 | mutex_lock(&dev_priv->rps.hw_lock); | |
4103 | __gen6_update_ring_freq(dev); | |
4104 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4105 | } | |
4106 | ||
03af2045 | 4107 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
4108 | { |
4109 | u32 val, rp0; | |
4110 | ||
4111 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4112 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4113 | ||
4114 | return rp0; | |
4115 | } | |
4116 | ||
4117 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4118 | { | |
4119 | u32 val, rpe; | |
4120 | ||
4121 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4122 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4123 | ||
4124 | return rpe; | |
4125 | } | |
4126 | ||
7707df4a D |
4127 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4128 | { | |
4129 | u32 val, rp1; | |
4130 | ||
4131 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4132 | rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4133 | ||
4134 | return rp1; | |
4135 | } | |
4136 | ||
03af2045 | 4137 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
4138 | { |
4139 | u32 val, rpn; | |
4140 | ||
4141 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4142 | rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK; | |
4143 | return rpn; | |
4144 | } | |
4145 | ||
f8f2b001 D |
4146 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4147 | { | |
4148 | u32 val, rp1; | |
4149 | ||
4150 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4151 | ||
4152 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4153 | ||
4154 | return rp1; | |
4155 | } | |
4156 | ||
03af2045 | 4157 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
4158 | { |
4159 | u32 val, rp0; | |
4160 | ||
64936258 | 4161 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
4162 | |
4163 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4164 | /* Clamp to max */ | |
4165 | rp0 = min_t(u32, rp0, 0xea); | |
4166 | ||
4167 | return rp0; | |
4168 | } | |
4169 | ||
4170 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4171 | { | |
4172 | u32 val, rpe; | |
4173 | ||
64936258 | 4174 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 4175 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 4176 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
4177 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
4178 | ||
4179 | return rpe; | |
4180 | } | |
4181 | ||
03af2045 | 4182 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 4183 | { |
64936258 | 4184 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
4185 | } |
4186 | ||
ae48434c ID |
4187 | /* Check that the pctx buffer wasn't move under us. */ |
4188 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4189 | { | |
4190 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4191 | ||
4192 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4193 | dev_priv->vlv_pctx->stolen->start); | |
4194 | } | |
4195 | ||
38807746 D |
4196 | |
4197 | /* Check that the pcbr address is not empty. */ | |
4198 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4199 | { | |
4200 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4201 | ||
4202 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4203 | } | |
4204 | ||
4205 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4206 | { | |
4207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4208 | unsigned long pctx_paddr, paddr; | |
4209 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4210 | u32 pcbr; | |
4211 | int pctx_size = 32*1024; | |
4212 | ||
4213 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4214 | ||
4215 | pcbr = I915_READ(VLV_PCBR); | |
4216 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
4217 | paddr = (dev_priv->mm.stolen_base + | |
4218 | (gtt->stolen_size - pctx_size)); | |
4219 | ||
4220 | pctx_paddr = (paddr & (~4095)); | |
4221 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4222 | } | |
4223 | } | |
4224 | ||
c9cddffc JB |
4225 | static void valleyview_setup_pctx(struct drm_device *dev) |
4226 | { | |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4228 | struct drm_i915_gem_object *pctx; | |
4229 | unsigned long pctx_paddr; | |
4230 | u32 pcbr; | |
4231 | int pctx_size = 24*1024; | |
4232 | ||
17b0c1f7 ID |
4233 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4234 | ||
c9cddffc JB |
4235 | pcbr = I915_READ(VLV_PCBR); |
4236 | if (pcbr) { | |
4237 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4238 | int pcbr_offset; | |
4239 | ||
4240 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4241 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4242 | pcbr_offset, | |
190d6cd5 | 4243 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
4244 | pctx_size); |
4245 | goto out; | |
4246 | } | |
4247 | ||
4248 | /* | |
4249 | * From the Gunit register HAS: | |
4250 | * The Gfx driver is expected to program this register and ensure | |
4251 | * proper allocation within Gfx stolen memory. For example, this | |
4252 | * register should be programmed such than the PCBR range does not | |
4253 | * overlap with other ranges, such as the frame buffer, protected | |
4254 | * memory, or any other relevant ranges. | |
4255 | */ | |
4256 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4257 | if (!pctx) { | |
4258 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4259 | return; | |
4260 | } | |
4261 | ||
4262 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4263 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4264 | ||
4265 | out: | |
4266 | dev_priv->vlv_pctx = pctx; | |
4267 | } | |
4268 | ||
ae48434c ID |
4269 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
4270 | { | |
4271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4272 | ||
4273 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4274 | return; | |
4275 | ||
4276 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4277 | dev_priv->vlv_pctx = NULL; | |
4278 | } | |
4279 | ||
4e80519e ID |
4280 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
4281 | { | |
4282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 4283 | u32 val; |
4e80519e ID |
4284 | |
4285 | valleyview_setup_pctx(dev); | |
4286 | ||
4287 | mutex_lock(&dev_priv->rps.hw_lock); | |
4288 | ||
2bb25c17 VS |
4289 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
4290 | switch ((val >> 6) & 3) { | |
4291 | case 0: | |
4292 | case 1: | |
4293 | dev_priv->mem_freq = 800; | |
4294 | break; | |
4295 | case 2: | |
4296 | dev_priv->mem_freq = 1066; | |
4297 | break; | |
4298 | case 3: | |
4299 | dev_priv->mem_freq = 1333; | |
4300 | break; | |
4301 | } | |
4302 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
4303 | ||
4e80519e ID |
4304 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
4305 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4306 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
4307 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
4308 | dev_priv->rps.max_freq); | |
4309 | ||
4310 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4311 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
4312 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4313 | dev_priv->rps.efficient_freq); | |
4314 | ||
f8f2b001 D |
4315 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
4316 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
4317 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
4318 | dev_priv->rps.rp1_freq); | |
4319 | ||
4e80519e ID |
4320 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
4321 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
4322 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
4323 | dev_priv->rps.min_freq); | |
4324 | ||
4325 | /* Preserve min/max settings in case of re-init */ | |
4326 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4327 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4328 | ||
4329 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4330 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4331 | ||
4332 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4333 | } | |
4334 | ||
38807746 D |
4335 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
4336 | { | |
2b6b3a09 | 4337 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 4338 | u32 val; |
2b6b3a09 | 4339 | |
38807746 | 4340 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
4341 | |
4342 | mutex_lock(&dev_priv->rps.hw_lock); | |
4343 | ||
2bb25c17 VS |
4344 | val = vlv_punit_read(dev_priv, CCK_FUSE_REG); |
4345 | switch ((val >> 2) & 0x7) { | |
4346 | case 0: | |
4347 | case 1: | |
4348 | dev_priv->rps.cz_freq = 200; | |
4349 | dev_priv->mem_freq = 1600; | |
4350 | break; | |
4351 | case 2: | |
4352 | dev_priv->rps.cz_freq = 267; | |
4353 | dev_priv->mem_freq = 1600; | |
4354 | break; | |
4355 | case 3: | |
4356 | dev_priv->rps.cz_freq = 333; | |
4357 | dev_priv->mem_freq = 2000; | |
4358 | break; | |
4359 | case 4: | |
4360 | dev_priv->rps.cz_freq = 320; | |
4361 | dev_priv->mem_freq = 1600; | |
4362 | break; | |
4363 | case 5: | |
4364 | dev_priv->rps.cz_freq = 400; | |
4365 | dev_priv->mem_freq = 1600; | |
4366 | break; | |
4367 | } | |
4368 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
4369 | ||
2b6b3a09 D |
4370 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
4371 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4372 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
4373 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
4374 | dev_priv->rps.max_freq); | |
4375 | ||
4376 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
4377 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
4378 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4379 | dev_priv->rps.efficient_freq); | |
4380 | ||
7707df4a D |
4381 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
4382 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
4383 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
4384 | dev_priv->rps.rp1_freq); | |
4385 | ||
2b6b3a09 D |
4386 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
4387 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
4388 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
4389 | dev_priv->rps.min_freq); | |
4390 | ||
1c14762d VS |
4391 | WARN_ONCE((dev_priv->rps.max_freq | |
4392 | dev_priv->rps.efficient_freq | | |
4393 | dev_priv->rps.rp1_freq | | |
4394 | dev_priv->rps.min_freq) & 1, | |
4395 | "Odd GPU freq values\n"); | |
4396 | ||
2b6b3a09 D |
4397 | /* Preserve min/max settings in case of re-init */ |
4398 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4399 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4400 | ||
4401 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4402 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4403 | ||
4404 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
4405 | } |
4406 | ||
4e80519e ID |
4407 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
4408 | { | |
4409 | valleyview_cleanup_pctx(dev); | |
4410 | } | |
4411 | ||
38807746 D |
4412 | static void cherryview_enable_rps(struct drm_device *dev) |
4413 | { | |
4414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4415 | struct intel_engine_cs *ring; | |
2b6b3a09 | 4416 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
4417 | int i; |
4418 | ||
4419 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4420 | ||
4421 | gtfifodbg = I915_READ(GTFIFODBG); | |
4422 | if (gtfifodbg) { | |
4423 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4424 | gtfifodbg); | |
4425 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4426 | } | |
4427 | ||
4428 | cherryview_check_pctx(dev_priv); | |
4429 | ||
4430 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
4431 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
4432 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
4433 | ||
4434 | /* 2a: Program RC6 thresholds.*/ | |
4435 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4436 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4437 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4438 | ||
4439 | for_each_ring(ring, dev_priv, i) | |
4440 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4441 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4442 | ||
4443 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
4444 | ||
4445 | /* allows RC6 residency counter to work */ | |
4446 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4447 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4448 | VLV_MEDIA_RC6_COUNT_EN | | |
4449 | VLV_RENDER_RC6_COUNT_EN)); | |
4450 | ||
4451 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
4452 | pcbr = I915_READ(VLV_PCBR); | |
4453 | ||
4454 | DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); | |
4455 | ||
4456 | /* 3: Enable RC6 */ | |
4457 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
4458 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
4459 | rc6_mode = GEN6_RC_CTL_EI_MODE(1); | |
4460 | ||
4461 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4462 | ||
2b6b3a09 D |
4463 | /* 4 Program defaults and thresholds for RPS*/ |
4464 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4465 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4466 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4467 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4468 | ||
4469 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4470 | ||
7405f42c TR |
4471 | /* WaDisablePwrmtrEvent:chv (pre-production hw) */ |
4472 | I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); | |
4473 | I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); | |
4474 | ||
2b6b3a09 D |
4475 | /* 5: Enable RPS */ |
4476 | I915_WRITE(GEN6_RP_CONTROL, | |
4477 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7405f42c | 4478 | GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ |
2b6b3a09 D |
4479 | GEN6_RP_ENABLE | |
4480 | GEN6_RP_UP_BUSY_AVG | | |
4481 | GEN6_RP_DOWN_IDLE_AVG); | |
4482 | ||
4483 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4484 | ||
4485 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
4486 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4487 | ||
4488 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4489 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
4490 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
4491 | dev_priv->rps.cur_freq); | |
4492 | ||
4493 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
4494 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4495 | dev_priv->rps.efficient_freq); | |
4496 | ||
4497 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
4498 | ||
3497a562 D |
4499 | gen8_enable_rps_interrupts(dev); |
4500 | ||
38807746 D |
4501 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
4502 | } | |
4503 | ||
0a073b84 JB |
4504 | static void valleyview_enable_rps(struct drm_device *dev) |
4505 | { | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4507 | struct intel_engine_cs *ring; |
2a5913a8 | 4508 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
4509 | int i; |
4510 | ||
4511 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4512 | ||
ae48434c ID |
4513 | valleyview_check_pctx(dev_priv); |
4514 | ||
0a073b84 | 4515 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
4516 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
4517 | gtfifodbg); | |
0a073b84 JB |
4518 | I915_WRITE(GTFIFODBG, gtfifodbg); |
4519 | } | |
4520 | ||
c8d9a590 D |
4521 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
4522 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
0a073b84 JB |
4523 | |
4524 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4525 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4526 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4527 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4528 | ||
4529 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
31685c25 | 4530 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); |
0a073b84 JB |
4531 | |
4532 | I915_WRITE(GEN6_RP_CONTROL, | |
4533 | GEN6_RP_MEDIA_TURBO | | |
4534 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4535 | GEN6_RP_MEDIA_IS_GFX | | |
4536 | GEN6_RP_ENABLE | | |
4537 | GEN6_RP_UP_BUSY_AVG | | |
4538 | GEN6_RP_DOWN_IDLE_CONT); | |
4539 | ||
4540 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
4541 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4542 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4543 | ||
4544 | for_each_ring(ring, dev_priv, i) | |
4545 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4546 | ||
2f0aa304 | 4547 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
4548 | |
4549 | /* allows RC6 residency counter to work */ | |
49798eb2 | 4550 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
4551 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
4552 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
4553 | VLV_MEDIA_RC6_COUNT_EN | |
4554 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 4555 | |
a2b23fe0 | 4556 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 4557 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
4558 | |
4559 | intel_print_rc6_info(dev, rc6_mode); | |
4560 | ||
a2b23fe0 | 4561 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 4562 | |
64936258 | 4563 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
4564 | |
4565 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
4566 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4567 | ||
b39fb297 | 4568 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 4569 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
b39fb297 BW |
4570 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
4571 | dev_priv->rps.cur_freq); | |
0a073b84 | 4572 | |
73008b98 | 4573 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
b39fb297 BW |
4574 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4575 | dev_priv->rps.efficient_freq); | |
0a073b84 | 4576 | |
b39fb297 | 4577 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 4578 | |
44fc7d5c | 4579 | gen6_enable_rps_interrupts(dev); |
0a073b84 | 4580 | |
c8d9a590 | 4581 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
4582 | } |
4583 | ||
930ebb46 | 4584 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
4585 | { |
4586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4587 | ||
3e373948 | 4588 | if (dev_priv->ips.renderctx) { |
d7f46fc4 | 4589 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
3e373948 DV |
4590 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
4591 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
4592 | } |
4593 | ||
3e373948 | 4594 | if (dev_priv->ips.pwrctx) { |
d7f46fc4 | 4595 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
3e373948 DV |
4596 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
4597 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
4598 | } |
4599 | } | |
4600 | ||
930ebb46 | 4601 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
4602 | { |
4603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4604 | ||
4605 | if (I915_READ(PWRCTXA)) { | |
4606 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
4607 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
4608 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
4609 | 50); | |
4610 | ||
4611 | I915_WRITE(PWRCTXA, 0); | |
4612 | POSTING_READ(PWRCTXA); | |
4613 | ||
4614 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
4615 | POSTING_READ(RSTDBYCTL); | |
4616 | } | |
2b4e57bd ED |
4617 | } |
4618 | ||
4619 | static int ironlake_setup_rc6(struct drm_device *dev) | |
4620 | { | |
4621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4622 | ||
3e373948 DV |
4623 | if (dev_priv->ips.renderctx == NULL) |
4624 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
4625 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
4626 | return -ENOMEM; |
4627 | ||
3e373948 DV |
4628 | if (dev_priv->ips.pwrctx == NULL) |
4629 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
4630 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
4631 | ironlake_teardown_rc6(dev); |
4632 | return -ENOMEM; | |
4633 | } | |
4634 | ||
4635 | return 0; | |
4636 | } | |
4637 | ||
930ebb46 | 4638 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
4639 | { |
4640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4641 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e960501 | 4642 | bool was_interruptible; |
2b4e57bd ED |
4643 | int ret; |
4644 | ||
4645 | /* rc6 disabled by default due to repeated reports of hanging during | |
4646 | * boot and resume. | |
4647 | */ | |
4648 | if (!intel_enable_rc6(dev)) | |
4649 | return; | |
4650 | ||
79f5b2c7 DV |
4651 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4652 | ||
2b4e57bd | 4653 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 4654 | if (ret) |
2b4e57bd | 4655 | return; |
2b4e57bd | 4656 | |
3e960501 CW |
4657 | was_interruptible = dev_priv->mm.interruptible; |
4658 | dev_priv->mm.interruptible = false; | |
4659 | ||
2b4e57bd ED |
4660 | /* |
4661 | * GPU can automatically power down the render unit if given a page | |
4662 | * to save state. | |
4663 | */ | |
6d90c952 | 4664 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
4665 | if (ret) { |
4666 | ironlake_teardown_rc6(dev); | |
3e960501 | 4667 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
4668 | return; |
4669 | } | |
4670 | ||
6d90c952 DV |
4671 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
4672 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 4673 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
6d90c952 DV |
4674 | MI_MM_SPACE_GTT | |
4675 | MI_SAVE_EXT_STATE_EN | | |
4676 | MI_RESTORE_EXT_STATE_EN | | |
4677 | MI_RESTORE_INHIBIT); | |
4678 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
4679 | intel_ring_emit(ring, MI_NOOP); | |
4680 | intel_ring_emit(ring, MI_FLUSH); | |
4681 | intel_ring_advance(ring); | |
2b4e57bd ED |
4682 | |
4683 | /* | |
4684 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
4685 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
4686 | * safe to assume that renderctx is valid | |
4687 | */ | |
3e960501 CW |
4688 | ret = intel_ring_idle(ring); |
4689 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 4690 | if (ret) { |
def27a58 | 4691 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 4692 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
4693 | return; |
4694 | } | |
4695 | ||
f343c5f6 | 4696 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
2b4e57bd | 4697 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
dc39fff7 | 4698 | |
91ca689a | 4699 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
2b4e57bd ED |
4700 | } |
4701 | ||
dde18883 ED |
4702 | static unsigned long intel_pxfreq(u32 vidfreq) |
4703 | { | |
4704 | unsigned long freq; | |
4705 | int div = (vidfreq & 0x3f0000) >> 16; | |
4706 | int post = (vidfreq & 0x3000) >> 12; | |
4707 | int pre = (vidfreq & 0x7); | |
4708 | ||
4709 | if (!pre) | |
4710 | return 0; | |
4711 | ||
4712 | freq = ((div * 133333) / ((1<<post) * pre)); | |
4713 | ||
4714 | return freq; | |
4715 | } | |
4716 | ||
eb48eb00 DV |
4717 | static const struct cparams { |
4718 | u16 i; | |
4719 | u16 t; | |
4720 | u16 m; | |
4721 | u16 c; | |
4722 | } cparams[] = { | |
4723 | { 1, 1333, 301, 28664 }, | |
4724 | { 1, 1066, 294, 24460 }, | |
4725 | { 1, 800, 294, 25192 }, | |
4726 | { 0, 1333, 276, 27605 }, | |
4727 | { 0, 1066, 276, 27605 }, | |
4728 | { 0, 800, 231, 23784 }, | |
4729 | }; | |
4730 | ||
f531dcb2 | 4731 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4732 | { |
4733 | u64 total_count, diff, ret; | |
4734 | u32 count1, count2, count3, m = 0, c = 0; | |
4735 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
4736 | int i; | |
4737 | ||
02d71956 DV |
4738 | assert_spin_locked(&mchdev_lock); |
4739 | ||
20e4d407 | 4740 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
4741 | |
4742 | /* Prevent division-by-zero if we are asking too fast. | |
4743 | * Also, we don't get interesting results if we are polling | |
4744 | * faster than once in 10ms, so just return the saved value | |
4745 | * in such cases. | |
4746 | */ | |
4747 | if (diff1 <= 10) | |
20e4d407 | 4748 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
4749 | |
4750 | count1 = I915_READ(DMIEC); | |
4751 | count2 = I915_READ(DDREC); | |
4752 | count3 = I915_READ(CSIEC); | |
4753 | ||
4754 | total_count = count1 + count2 + count3; | |
4755 | ||
4756 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
4757 | if (total_count < dev_priv->ips.last_count1) { |
4758 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
4759 | diff += total_count; |
4760 | } else { | |
20e4d407 | 4761 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
4762 | } |
4763 | ||
4764 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
4765 | if (cparams[i].i == dev_priv->ips.c_m && |
4766 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
4767 | m = cparams[i].m; |
4768 | c = cparams[i].c; | |
4769 | break; | |
4770 | } | |
4771 | } | |
4772 | ||
4773 | diff = div_u64(diff, diff1); | |
4774 | ret = ((m * diff) + c); | |
4775 | ret = div_u64(ret, 10); | |
4776 | ||
20e4d407 DV |
4777 | dev_priv->ips.last_count1 = total_count; |
4778 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 4779 | |
20e4d407 | 4780 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
4781 | |
4782 | return ret; | |
4783 | } | |
4784 | ||
f531dcb2 CW |
4785 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
4786 | { | |
3d13ef2e | 4787 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
4788 | unsigned long val; |
4789 | ||
3d13ef2e | 4790 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
4791 | return 0; |
4792 | ||
4793 | spin_lock_irq(&mchdev_lock); | |
4794 | ||
4795 | val = __i915_chipset_val(dev_priv); | |
4796 | ||
4797 | spin_unlock_irq(&mchdev_lock); | |
4798 | ||
4799 | return val; | |
4800 | } | |
4801 | ||
eb48eb00 DV |
4802 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
4803 | { | |
4804 | unsigned long m, x, b; | |
4805 | u32 tsfs; | |
4806 | ||
4807 | tsfs = I915_READ(TSFS); | |
4808 | ||
4809 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
4810 | x = I915_READ8(TR1); | |
4811 | ||
4812 | b = tsfs & TSFS_INTR_MASK; | |
4813 | ||
4814 | return ((m * x) / 127) - b; | |
4815 | } | |
4816 | ||
4817 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
4818 | { | |
3d13ef2e | 4819 | struct drm_device *dev = dev_priv->dev; |
eb48eb00 DV |
4820 | static const struct v_table { |
4821 | u16 vd; /* in .1 mil */ | |
4822 | u16 vm; /* in .1 mil */ | |
4823 | } v_table[] = { | |
4824 | { 0, 0, }, | |
4825 | { 375, 0, }, | |
4826 | { 500, 0, }, | |
4827 | { 625, 0, }, | |
4828 | { 750, 0, }, | |
4829 | { 875, 0, }, | |
4830 | { 1000, 0, }, | |
4831 | { 1125, 0, }, | |
4832 | { 4125, 3000, }, | |
4833 | { 4125, 3000, }, | |
4834 | { 4125, 3000, }, | |
4835 | { 4125, 3000, }, | |
4836 | { 4125, 3000, }, | |
4837 | { 4125, 3000, }, | |
4838 | { 4125, 3000, }, | |
4839 | { 4125, 3000, }, | |
4840 | { 4125, 3000, }, | |
4841 | { 4125, 3000, }, | |
4842 | { 4125, 3000, }, | |
4843 | { 4125, 3000, }, | |
4844 | { 4125, 3000, }, | |
4845 | { 4125, 3000, }, | |
4846 | { 4125, 3000, }, | |
4847 | { 4125, 3000, }, | |
4848 | { 4125, 3000, }, | |
4849 | { 4125, 3000, }, | |
4850 | { 4125, 3000, }, | |
4851 | { 4125, 3000, }, | |
4852 | { 4125, 3000, }, | |
4853 | { 4125, 3000, }, | |
4854 | { 4125, 3000, }, | |
4855 | { 4125, 3000, }, | |
4856 | { 4250, 3125, }, | |
4857 | { 4375, 3250, }, | |
4858 | { 4500, 3375, }, | |
4859 | { 4625, 3500, }, | |
4860 | { 4750, 3625, }, | |
4861 | { 4875, 3750, }, | |
4862 | { 5000, 3875, }, | |
4863 | { 5125, 4000, }, | |
4864 | { 5250, 4125, }, | |
4865 | { 5375, 4250, }, | |
4866 | { 5500, 4375, }, | |
4867 | { 5625, 4500, }, | |
4868 | { 5750, 4625, }, | |
4869 | { 5875, 4750, }, | |
4870 | { 6000, 4875, }, | |
4871 | { 6125, 5000, }, | |
4872 | { 6250, 5125, }, | |
4873 | { 6375, 5250, }, | |
4874 | { 6500, 5375, }, | |
4875 | { 6625, 5500, }, | |
4876 | { 6750, 5625, }, | |
4877 | { 6875, 5750, }, | |
4878 | { 7000, 5875, }, | |
4879 | { 7125, 6000, }, | |
4880 | { 7250, 6125, }, | |
4881 | { 7375, 6250, }, | |
4882 | { 7500, 6375, }, | |
4883 | { 7625, 6500, }, | |
4884 | { 7750, 6625, }, | |
4885 | { 7875, 6750, }, | |
4886 | { 8000, 6875, }, | |
4887 | { 8125, 7000, }, | |
4888 | { 8250, 7125, }, | |
4889 | { 8375, 7250, }, | |
4890 | { 8500, 7375, }, | |
4891 | { 8625, 7500, }, | |
4892 | { 8750, 7625, }, | |
4893 | { 8875, 7750, }, | |
4894 | { 9000, 7875, }, | |
4895 | { 9125, 8000, }, | |
4896 | { 9250, 8125, }, | |
4897 | { 9375, 8250, }, | |
4898 | { 9500, 8375, }, | |
4899 | { 9625, 8500, }, | |
4900 | { 9750, 8625, }, | |
4901 | { 9875, 8750, }, | |
4902 | { 10000, 8875, }, | |
4903 | { 10125, 9000, }, | |
4904 | { 10250, 9125, }, | |
4905 | { 10375, 9250, }, | |
4906 | { 10500, 9375, }, | |
4907 | { 10625, 9500, }, | |
4908 | { 10750, 9625, }, | |
4909 | { 10875, 9750, }, | |
4910 | { 11000, 9875, }, | |
4911 | { 11125, 10000, }, | |
4912 | { 11250, 10125, }, | |
4913 | { 11375, 10250, }, | |
4914 | { 11500, 10375, }, | |
4915 | { 11625, 10500, }, | |
4916 | { 11750, 10625, }, | |
4917 | { 11875, 10750, }, | |
4918 | { 12000, 10875, }, | |
4919 | { 12125, 11000, }, | |
4920 | { 12250, 11125, }, | |
4921 | { 12375, 11250, }, | |
4922 | { 12500, 11375, }, | |
4923 | { 12625, 11500, }, | |
4924 | { 12750, 11625, }, | |
4925 | { 12875, 11750, }, | |
4926 | { 13000, 11875, }, | |
4927 | { 13125, 12000, }, | |
4928 | { 13250, 12125, }, | |
4929 | { 13375, 12250, }, | |
4930 | { 13500, 12375, }, | |
4931 | { 13625, 12500, }, | |
4932 | { 13750, 12625, }, | |
4933 | { 13875, 12750, }, | |
4934 | { 14000, 12875, }, | |
4935 | { 14125, 13000, }, | |
4936 | { 14250, 13125, }, | |
4937 | { 14375, 13250, }, | |
4938 | { 14500, 13375, }, | |
4939 | { 14625, 13500, }, | |
4940 | { 14750, 13625, }, | |
4941 | { 14875, 13750, }, | |
4942 | { 15000, 13875, }, | |
4943 | { 15125, 14000, }, | |
4944 | { 15250, 14125, }, | |
4945 | { 15375, 14250, }, | |
4946 | { 15500, 14375, }, | |
4947 | { 15625, 14500, }, | |
4948 | { 15750, 14625, }, | |
4949 | { 15875, 14750, }, | |
4950 | { 16000, 14875, }, | |
4951 | { 16125, 15000, }, | |
4952 | }; | |
3d13ef2e | 4953 | if (INTEL_INFO(dev)->is_mobile) |
eb48eb00 DV |
4954 | return v_table[pxvid].vm; |
4955 | else | |
4956 | return v_table[pxvid].vd; | |
4957 | } | |
4958 | ||
02d71956 | 4959 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 4960 | { |
5ed0bdf2 | 4961 | u64 now, diff, diffms; |
eb48eb00 DV |
4962 | u32 count; |
4963 | ||
02d71956 | 4964 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 4965 | |
5ed0bdf2 TG |
4966 | now = ktime_get_raw_ns(); |
4967 | diffms = now - dev_priv->ips.last_time2; | |
4968 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
4969 | |
4970 | /* Don't divide by 0 */ | |
eb48eb00 DV |
4971 | if (!diffms) |
4972 | return; | |
4973 | ||
4974 | count = I915_READ(GFXEC); | |
4975 | ||
20e4d407 DV |
4976 | if (count < dev_priv->ips.last_count2) { |
4977 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
4978 | diff += count; |
4979 | } else { | |
20e4d407 | 4980 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
4981 | } |
4982 | ||
20e4d407 DV |
4983 | dev_priv->ips.last_count2 = count; |
4984 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
4985 | |
4986 | /* More magic constants... */ | |
4987 | diff = diff * 1181; | |
4988 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 4989 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
4990 | } |
4991 | ||
02d71956 DV |
4992 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
4993 | { | |
3d13ef2e DL |
4994 | struct drm_device *dev = dev_priv->dev; |
4995 | ||
4996 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
4997 | return; |
4998 | ||
9270388e | 4999 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5000 | |
5001 | __i915_update_gfx_val(dev_priv); | |
5002 | ||
9270388e | 5003 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5004 | } |
5005 | ||
f531dcb2 | 5006 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5007 | { |
5008 | unsigned long t, corr, state1, corr2, state2; | |
5009 | u32 pxvid, ext_v; | |
5010 | ||
02d71956 DV |
5011 | assert_spin_locked(&mchdev_lock); |
5012 | ||
b39fb297 | 5013 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
5014 | pxvid = (pxvid >> 24) & 0x7f; |
5015 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5016 | ||
5017 | state1 = ext_v; | |
5018 | ||
5019 | t = i915_mch_val(dev_priv); | |
5020 | ||
5021 | /* Revel in the empirically derived constants */ | |
5022 | ||
5023 | /* Correction factor in 1/100000 units */ | |
5024 | if (t > 80) | |
5025 | corr = ((t * 2349) + 135940); | |
5026 | else if (t >= 50) | |
5027 | corr = ((t * 964) + 29317); | |
5028 | else /* < 50 */ | |
5029 | corr = ((t * 301) + 1004); | |
5030 | ||
5031 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5032 | corr /= 100000; | |
20e4d407 | 5033 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5034 | |
5035 | state2 = (corr2 * state1) / 10000; | |
5036 | state2 /= 100; /* convert to mW */ | |
5037 | ||
02d71956 | 5038 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5039 | |
20e4d407 | 5040 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5041 | } |
5042 | ||
f531dcb2 CW |
5043 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5044 | { | |
3d13ef2e | 5045 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5046 | unsigned long val; |
5047 | ||
3d13ef2e | 5048 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5049 | return 0; |
5050 | ||
5051 | spin_lock_irq(&mchdev_lock); | |
5052 | ||
5053 | val = __i915_gfx_val(dev_priv); | |
5054 | ||
5055 | spin_unlock_irq(&mchdev_lock); | |
5056 | ||
5057 | return val; | |
5058 | } | |
5059 | ||
eb48eb00 DV |
5060 | /** |
5061 | * i915_read_mch_val - return value for IPS use | |
5062 | * | |
5063 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5064 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5065 | */ | |
5066 | unsigned long i915_read_mch_val(void) | |
5067 | { | |
5068 | struct drm_i915_private *dev_priv; | |
5069 | unsigned long chipset_val, graphics_val, ret = 0; | |
5070 | ||
9270388e | 5071 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5072 | if (!i915_mch_dev) |
5073 | goto out_unlock; | |
5074 | dev_priv = i915_mch_dev; | |
5075 | ||
f531dcb2 CW |
5076 | chipset_val = __i915_chipset_val(dev_priv); |
5077 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5078 | |
5079 | ret = chipset_val + graphics_val; | |
5080 | ||
5081 | out_unlock: | |
9270388e | 5082 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5083 | |
5084 | return ret; | |
5085 | } | |
5086 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5087 | ||
5088 | /** | |
5089 | * i915_gpu_raise - raise GPU frequency limit | |
5090 | * | |
5091 | * Raise the limit; IPS indicates we have thermal headroom. | |
5092 | */ | |
5093 | bool i915_gpu_raise(void) | |
5094 | { | |
5095 | struct drm_i915_private *dev_priv; | |
5096 | bool ret = true; | |
5097 | ||
9270388e | 5098 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5099 | if (!i915_mch_dev) { |
5100 | ret = false; | |
5101 | goto out_unlock; | |
5102 | } | |
5103 | dev_priv = i915_mch_dev; | |
5104 | ||
20e4d407 DV |
5105 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5106 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5107 | |
5108 | out_unlock: | |
9270388e | 5109 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5110 | |
5111 | return ret; | |
5112 | } | |
5113 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5114 | ||
5115 | /** | |
5116 | * i915_gpu_lower - lower GPU frequency limit | |
5117 | * | |
5118 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5119 | * frequency maximum. | |
5120 | */ | |
5121 | bool i915_gpu_lower(void) | |
5122 | { | |
5123 | struct drm_i915_private *dev_priv; | |
5124 | bool ret = true; | |
5125 | ||
9270388e | 5126 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5127 | if (!i915_mch_dev) { |
5128 | ret = false; | |
5129 | goto out_unlock; | |
5130 | } | |
5131 | dev_priv = i915_mch_dev; | |
5132 | ||
20e4d407 DV |
5133 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5134 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5135 | |
5136 | out_unlock: | |
9270388e | 5137 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5138 | |
5139 | return ret; | |
5140 | } | |
5141 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5142 | ||
5143 | /** | |
5144 | * i915_gpu_busy - indicate GPU business to IPS | |
5145 | * | |
5146 | * Tell the IPS driver whether or not the GPU is busy. | |
5147 | */ | |
5148 | bool i915_gpu_busy(void) | |
5149 | { | |
5150 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5151 | struct intel_engine_cs *ring; |
eb48eb00 | 5152 | bool ret = false; |
f047e395 | 5153 | int i; |
eb48eb00 | 5154 | |
9270388e | 5155 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5156 | if (!i915_mch_dev) |
5157 | goto out_unlock; | |
5158 | dev_priv = i915_mch_dev; | |
5159 | ||
f047e395 CW |
5160 | for_each_ring(ring, dev_priv, i) |
5161 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5162 | |
5163 | out_unlock: | |
9270388e | 5164 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5165 | |
5166 | return ret; | |
5167 | } | |
5168 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5169 | ||
5170 | /** | |
5171 | * i915_gpu_turbo_disable - disable graphics turbo | |
5172 | * | |
5173 | * Disable graphics turbo by resetting the max frequency and setting the | |
5174 | * current frequency to the default. | |
5175 | */ | |
5176 | bool i915_gpu_turbo_disable(void) | |
5177 | { | |
5178 | struct drm_i915_private *dev_priv; | |
5179 | bool ret = true; | |
5180 | ||
9270388e | 5181 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5182 | if (!i915_mch_dev) { |
5183 | ret = false; | |
5184 | goto out_unlock; | |
5185 | } | |
5186 | dev_priv = i915_mch_dev; | |
5187 | ||
20e4d407 | 5188 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5189 | |
20e4d407 | 5190 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5191 | ret = false; |
5192 | ||
5193 | out_unlock: | |
9270388e | 5194 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5195 | |
5196 | return ret; | |
5197 | } | |
5198 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5199 | ||
5200 | /** | |
5201 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5202 | * IPS got loaded first. | |
5203 | * | |
5204 | * This awkward dance is so that neither module has to depend on the | |
5205 | * other in order for IPS to do the appropriate communication of | |
5206 | * GPU turbo limits to i915. | |
5207 | */ | |
5208 | static void | |
5209 | ips_ping_for_i915_load(void) | |
5210 | { | |
5211 | void (*link)(void); | |
5212 | ||
5213 | link = symbol_get(ips_link_to_i915_driver); | |
5214 | if (link) { | |
5215 | link(); | |
5216 | symbol_put(ips_link_to_i915_driver); | |
5217 | } | |
5218 | } | |
5219 | ||
5220 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5221 | { | |
02d71956 DV |
5222 | /* We only register the i915 ips part with intel-ips once everything is |
5223 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5224 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5225 | i915_mch_dev = dev_priv; |
9270388e | 5226 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5227 | |
5228 | ips_ping_for_i915_load(); | |
5229 | } | |
5230 | ||
5231 | void intel_gpu_ips_teardown(void) | |
5232 | { | |
9270388e | 5233 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5234 | i915_mch_dev = NULL; |
9270388e | 5235 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5236 | } |
76c3552f | 5237 | |
8090c6b9 | 5238 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5239 | { |
5240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5241 | u32 lcfuse; | |
5242 | u8 pxw[16]; | |
5243 | int i; | |
5244 | ||
5245 | /* Disable to program */ | |
5246 | I915_WRITE(ECR, 0); | |
5247 | POSTING_READ(ECR); | |
5248 | ||
5249 | /* Program energy weights for various events */ | |
5250 | I915_WRITE(SDEW, 0x15040d00); | |
5251 | I915_WRITE(CSIEW0, 0x007f0000); | |
5252 | I915_WRITE(CSIEW1, 0x1e220004); | |
5253 | I915_WRITE(CSIEW2, 0x04000004); | |
5254 | ||
5255 | for (i = 0; i < 5; i++) | |
5256 | I915_WRITE(PEW + (i * 4), 0); | |
5257 | for (i = 0; i < 3; i++) | |
5258 | I915_WRITE(DEW + (i * 4), 0); | |
5259 | ||
5260 | /* Program P-state weights to account for frequency power adjustment */ | |
5261 | for (i = 0; i < 16; i++) { | |
5262 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5263 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5264 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5265 | PXVFREQ_PX_SHIFT; | |
5266 | unsigned long val; | |
5267 | ||
5268 | val = vid * vid; | |
5269 | val *= (freq / 1000); | |
5270 | val *= 255; | |
5271 | val /= (127*127*900); | |
5272 | if (val > 0xff) | |
5273 | DRM_ERROR("bad pxval: %ld\n", val); | |
5274 | pxw[i] = val; | |
5275 | } | |
5276 | /* Render standby states get 0 weight */ | |
5277 | pxw[14] = 0; | |
5278 | pxw[15] = 0; | |
5279 | ||
5280 | for (i = 0; i < 4; i++) { | |
5281 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5282 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5283 | I915_WRITE(PXW + (i * 4), val); | |
5284 | } | |
5285 | ||
5286 | /* Adjust magic regs to magic values (more experimental results) */ | |
5287 | I915_WRITE(OGW0, 0); | |
5288 | I915_WRITE(OGW1, 0); | |
5289 | I915_WRITE(EG0, 0x00007f00); | |
5290 | I915_WRITE(EG1, 0x0000000e); | |
5291 | I915_WRITE(EG2, 0x000e0000); | |
5292 | I915_WRITE(EG3, 0x68000300); | |
5293 | I915_WRITE(EG4, 0x42000000); | |
5294 | I915_WRITE(EG5, 0x00140031); | |
5295 | I915_WRITE(EG6, 0); | |
5296 | I915_WRITE(EG7, 0); | |
5297 | ||
5298 | for (i = 0; i < 8; i++) | |
5299 | I915_WRITE(PXWL + (i * 4), 0); | |
5300 | ||
5301 | /* Enable PMON + select events */ | |
5302 | I915_WRITE(ECR, 0x80000019); | |
5303 | ||
5304 | lcfuse = I915_READ(LCFUSE02); | |
5305 | ||
20e4d407 | 5306 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5307 | } |
5308 | ||
ae48434c ID |
5309 | void intel_init_gt_powersave(struct drm_device *dev) |
5310 | { | |
e6069ca8 ID |
5311 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5312 | ||
38807746 D |
5313 | if (IS_CHERRYVIEW(dev)) |
5314 | cherryview_init_gt_powersave(dev); | |
5315 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5316 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
5317 | } |
5318 | ||
5319 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5320 | { | |
38807746 D |
5321 | if (IS_CHERRYVIEW(dev)) |
5322 | return; | |
5323 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5324 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
5325 | } |
5326 | ||
156c7ca0 JB |
5327 | /** |
5328 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
5329 | * @dev: drm device | |
5330 | * | |
5331 | * We don't want to disable RC6 or other features here, we just want | |
5332 | * to make sure any work we've queued has finished and won't bother | |
5333 | * us while we're suspended. | |
5334 | */ | |
5335 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
5336 | { | |
5337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5338 | ||
5339 | /* Interrupts should be disabled already to avoid re-arming. */ | |
9df7575f | 5340 | WARN_ON(intel_irqs_enabled(dev_priv)); |
156c7ca0 JB |
5341 | |
5342 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
5343 | ||
5344 | cancel_work_sync(&dev_priv->rps.work); | |
b47adc17 D |
5345 | |
5346 | /* Force GPU to min freq during suspend */ | |
5347 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
5348 | } |
5349 | ||
8090c6b9 DV |
5350 | void intel_disable_gt_powersave(struct drm_device *dev) |
5351 | { | |
1a01ab3b JB |
5352 | struct drm_i915_private *dev_priv = dev->dev_private; |
5353 | ||
fd0c0642 | 5354 | /* Interrupts should be disabled already to avoid re-arming. */ |
9df7575f | 5355 | WARN_ON(intel_irqs_enabled(dev_priv)); |
fd0c0642 | 5356 | |
930ebb46 | 5357 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 5358 | ironlake_disable_drps(dev); |
930ebb46 | 5359 | ironlake_disable_rc6(dev); |
38807746 | 5360 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 5361 | intel_suspend_gt_powersave(dev); |
e494837a | 5362 | |
4fc688ce | 5363 | mutex_lock(&dev_priv->rps.hw_lock); |
38807746 D |
5364 | if (IS_CHERRYVIEW(dev)) |
5365 | cherryview_disable_rps(dev); | |
5366 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
5367 | valleyview_disable_rps(dev); |
5368 | else | |
5369 | gen6_disable_rps(dev); | |
c0951f0c | 5370 | dev_priv->rps.enabled = false; |
4fc688ce | 5371 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 5372 | } |
8090c6b9 DV |
5373 | } |
5374 | ||
1a01ab3b JB |
5375 | static void intel_gen6_powersave_work(struct work_struct *work) |
5376 | { | |
5377 | struct drm_i915_private *dev_priv = | |
5378 | container_of(work, struct drm_i915_private, | |
5379 | rps.delayed_resume_work.work); | |
5380 | struct drm_device *dev = dev_priv->dev; | |
5381 | ||
c76bb61a DS |
5382 | dev_priv->rps.is_bdw_sw_turbo = false; |
5383 | ||
4fc688ce | 5384 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 5385 | |
38807746 D |
5386 | if (IS_CHERRYVIEW(dev)) { |
5387 | cherryview_enable_rps(dev); | |
5388 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 5389 | valleyview_enable_rps(dev); |
6edee7f3 BW |
5390 | } else if (IS_BROADWELL(dev)) { |
5391 | gen8_enable_rps(dev); | |
c2bc2fc5 | 5392 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
5393 | } else { |
5394 | gen6_enable_rps(dev); | |
c2bc2fc5 | 5395 | __gen6_update_ring_freq(dev); |
0a073b84 | 5396 | } |
c0951f0c | 5397 | dev_priv->rps.enabled = true; |
4fc688ce | 5398 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
5399 | |
5400 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
5401 | } |
5402 | ||
8090c6b9 DV |
5403 | void intel_enable_gt_powersave(struct drm_device *dev) |
5404 | { | |
1a01ab3b JB |
5405 | struct drm_i915_private *dev_priv = dev->dev_private; |
5406 | ||
8090c6b9 | 5407 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 5408 | mutex_lock(&dev->struct_mutex); |
8090c6b9 DV |
5409 | ironlake_enable_drps(dev); |
5410 | ironlake_enable_rc6(dev); | |
5411 | intel_init_emon(dev); | |
dc1d0136 | 5412 | mutex_unlock(&dev->struct_mutex); |
38807746 | 5413 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
5414 | /* |
5415 | * PCU communication is slow and this doesn't need to be | |
5416 | * done at any specific time, so do this out of our fast path | |
5417 | * to make resume and init faster. | |
c6df39b5 ID |
5418 | * |
5419 | * We depend on the HW RC6 power context save/restore | |
5420 | * mechanism when entering D3 through runtime PM suspend. So | |
5421 | * disable RPM until RPS/RC6 is properly setup. We can only | |
5422 | * get here via the driver load/system resume/runtime resume | |
5423 | * paths, so the _noresume version is enough (and in case of | |
5424 | * runtime resume it's necessary). | |
1a01ab3b | 5425 | */ |
c6df39b5 ID |
5426 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
5427 | round_jiffies_up_relative(HZ))) | |
5428 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
5429 | } |
5430 | } | |
5431 | ||
c6df39b5 ID |
5432 | void intel_reset_gt_powersave(struct drm_device *dev) |
5433 | { | |
5434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5435 | ||
5436 | dev_priv->rps.enabled = false; | |
5437 | intel_enable_gt_powersave(dev); | |
5438 | } | |
5439 | ||
3107bd48 DV |
5440 | static void ibx_init_clock_gating(struct drm_device *dev) |
5441 | { | |
5442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5443 | ||
5444 | /* | |
5445 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5446 | * gating for the panel power sequencer or it will fail to | |
5447 | * start up when no ports are active. | |
5448 | */ | |
5449 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5450 | } | |
5451 | ||
0e088b8f VS |
5452 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
5453 | { | |
5454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5455 | int pipe; | |
5456 | ||
055e393f | 5457 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
5458 | I915_WRITE(DSPCNTR(pipe), |
5459 | I915_READ(DSPCNTR(pipe)) | | |
5460 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 5461 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
5462 | } |
5463 | } | |
5464 | ||
017636cc VS |
5465 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
5466 | { | |
5467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5468 | ||
5469 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5470 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5471 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5472 | ||
5473 | /* | |
5474 | * Don't touch WM1S_LP_EN here. | |
5475 | * Doing so could cause underruns. | |
5476 | */ | |
5477 | } | |
5478 | ||
1fa61106 | 5479 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5480 | { |
5481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5482 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5483 | |
f1e8fa56 DL |
5484 | /* |
5485 | * Required for FBC | |
5486 | * WaFbcDisableDpfcClockGating:ilk | |
5487 | */ | |
4d47e4f5 DL |
5488 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
5489 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5490 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
5491 | |
5492 | I915_WRITE(PCH_3DCGDIS0, | |
5493 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5494 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5495 | I915_WRITE(PCH_3DCGDIS1, | |
5496 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5497 | ||
6f1d69b0 ED |
5498 | /* |
5499 | * According to the spec the following bits should be set in | |
5500 | * order to enable memory self-refresh | |
5501 | * The bit 22/21 of 0x42004 | |
5502 | * The bit 5 of 0x42020 | |
5503 | * The bit 15 of 0x45000 | |
5504 | */ | |
5505 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5506 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5507 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 5508 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
5509 | I915_WRITE(DISP_ARB_CTL, |
5510 | (I915_READ(DISP_ARB_CTL) | | |
5511 | DISP_FBC_WM_DIS)); | |
017636cc VS |
5512 | |
5513 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
5514 | |
5515 | /* | |
5516 | * Based on the document from hardware guys the following bits | |
5517 | * should be set unconditionally in order to enable FBC. | |
5518 | * The bit 22 of 0x42000 | |
5519 | * The bit 22 of 0x42004 | |
5520 | * The bit 7,8,9 of 0x42020. | |
5521 | */ | |
5522 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 5523 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
5524 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
5525 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5526 | ILK_FBCQ_DIS); | |
5527 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5528 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5529 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
5530 | } |
5531 | ||
4d47e4f5 DL |
5532 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
5533 | ||
6f1d69b0 ED |
5534 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5535 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5536 | ILK_ELPIN_409_SELECT); | |
5537 | I915_WRITE(_3D_CHICKEN2, | |
5538 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5539 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 5540 | |
ecdb4eb7 | 5541 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
5542 | I915_WRITE(CACHE_MODE_0, |
5543 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 5544 | |
4e04632e AG |
5545 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
5546 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5547 | ||
0e088b8f | 5548 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 5549 | |
3107bd48 DV |
5550 | ibx_init_clock_gating(dev); |
5551 | } | |
5552 | ||
5553 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5554 | { | |
5555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5556 | int pipe; | |
3f704fa2 | 5557 | uint32_t val; |
3107bd48 DV |
5558 | |
5559 | /* | |
5560 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5561 | * gating for the panel power sequencer or it will fail to | |
5562 | * start up when no ports are active. | |
5563 | */ | |
cd664078 JB |
5564 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
5565 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
5566 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
5567 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
5568 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
5569 | /* The below fixes the weird display corruption, a few pixels shifted |
5570 | * downward, on (only) LVDS of some HP laptops with IVY. | |
5571 | */ | |
055e393f | 5572 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
5573 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
5574 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
5575 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 5576 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 5577 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
5578 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
5579 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
5580 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
5581 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
5582 | } | |
3107bd48 | 5583 | /* WADP0ClockGatingDisable */ |
055e393f | 5584 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
5585 | I915_WRITE(TRANS_CHICKEN1(pipe), |
5586 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5587 | } | |
6f1d69b0 ED |
5588 | } |
5589 | ||
1d7aaa0c DV |
5590 | static void gen6_check_mch_setup(struct drm_device *dev) |
5591 | { | |
5592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5593 | uint32_t tmp; | |
5594 | ||
5595 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
5596 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
5597 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
5598 | tmp); | |
1d7aaa0c DV |
5599 | } |
5600 | ||
1fa61106 | 5601 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5602 | { |
5603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5604 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5605 | |
231e54f6 | 5606 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
5607 | |
5608 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5609 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5610 | ILK_ELPIN_409_SELECT); | |
5611 | ||
ecdb4eb7 | 5612 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
5613 | I915_WRITE(_3D_CHICKEN, |
5614 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
5615 | ||
ecdb4eb7 | 5616 | /* WaSetupGtModeTdRowDispatch:snb */ |
6547fbdb DV |
5617 | if (IS_SNB_GT1(dev)) |
5618 | I915_WRITE(GEN6_GT_MODE, | |
5619 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); | |
5620 | ||
4e04632e AG |
5621 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
5622 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5623 | ||
8d85d272 VS |
5624 | /* |
5625 | * BSpec recoomends 8x4 when MSAA is used, | |
5626 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5627 | * |
5628 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5629 | * disable bit, which we don't touch here, but it's good | |
5630 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
5631 | */ |
5632 | I915_WRITE(GEN6_GT_MODE, | |
5633 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5634 | ||
017636cc | 5635 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5636 | |
6f1d69b0 | 5637 | I915_WRITE(CACHE_MODE_0, |
50743298 | 5638 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
5639 | |
5640 | I915_WRITE(GEN6_UCGCTL1, | |
5641 | I915_READ(GEN6_UCGCTL1) | | |
5642 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
5643 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
5644 | ||
5645 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
5646 | * gating disable must be set. Failure to set it results in | |
5647 | * flickering pixels due to Z write ordering failures after | |
5648 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
5649 | * Sanctuary and Tropics, and apparently anything else with | |
5650 | * alpha test or pixel discard. | |
5651 | * | |
5652 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
5653 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 5654 | * |
ef59318c VS |
5655 | * WaDisableRCCUnitClockGating:snb |
5656 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
5657 | */ |
5658 | I915_WRITE(GEN6_UCGCTL2, | |
5659 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
5660 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
5661 | ||
5eb146dd | 5662 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
5663 | I915_WRITE(_3D_CHICKEN3, |
5664 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 5665 | |
e927ecde VS |
5666 | /* |
5667 | * Bspec says: | |
5668 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
5669 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
5670 | */ | |
5671 | I915_WRITE(_3D_CHICKEN3, | |
5672 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
5673 | ||
6f1d69b0 ED |
5674 | /* |
5675 | * According to the spec the following bits should be | |
5676 | * set in order to enable memory self-refresh and fbc: | |
5677 | * The bit21 and bit22 of 0x42000 | |
5678 | * The bit21 and bit22 of 0x42004 | |
5679 | * The bit5 and bit7 of 0x42020 | |
5680 | * The bit14 of 0x70180 | |
5681 | * The bit14 of 0x71180 | |
4bb35334 DL |
5682 | * |
5683 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
5684 | */ |
5685 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5686 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5687 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
5688 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5689 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5690 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
5691 | I915_WRITE(ILK_DSPCLK_GATE_D, |
5692 | I915_READ(ILK_DSPCLK_GATE_D) | | |
5693 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
5694 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 5695 | |
0e088b8f | 5696 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 5697 | |
3107bd48 | 5698 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
5699 | |
5700 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5701 | } |
5702 | ||
5703 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
5704 | { | |
5705 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
5706 | ||
3aad9059 | 5707 | /* |
46680e0a | 5708 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
5709 | * |
5710 | * This actually overrides the dispatch | |
5711 | * mode for all thread types. | |
5712 | */ | |
6f1d69b0 ED |
5713 | reg &= ~GEN7_FF_SCHED_MASK; |
5714 | reg |= GEN7_FF_TS_SCHED_HW; | |
5715 | reg |= GEN7_FF_VS_SCHED_HW; | |
5716 | reg |= GEN7_FF_DS_SCHED_HW; | |
5717 | ||
5718 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
5719 | } | |
5720 | ||
17a303ec PZ |
5721 | static void lpt_init_clock_gating(struct drm_device *dev) |
5722 | { | |
5723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5724 | ||
5725 | /* | |
5726 | * TODO: this bit should only be enabled when really needed, then | |
5727 | * disabled when not needed anymore in order to save power. | |
5728 | */ | |
5729 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
5730 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
5731 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
5732 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
5733 | |
5734 | /* WADPOClockGatingDisable:hsw */ | |
5735 | I915_WRITE(_TRANSA_CHICKEN1, | |
5736 | I915_READ(_TRANSA_CHICKEN1) | | |
5737 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
5738 | } |
5739 | ||
7d708ee4 ID |
5740 | static void lpt_suspend_hw(struct drm_device *dev) |
5741 | { | |
5742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5743 | ||
5744 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
5745 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
5746 | ||
5747 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
5748 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
5749 | } | |
5750 | } | |
5751 | ||
47c2bd97 | 5752 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
5753 | { |
5754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 5755 | enum pipe pipe; |
1020a5c2 BW |
5756 | |
5757 | I915_WRITE(WM3_LP_ILK, 0); | |
5758 | I915_WRITE(WM2_LP_ILK, 0); | |
5759 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd BW |
5760 | |
5761 | /* FIXME(BDW): Check all the w/a, some might only apply to | |
5762 | * pre-production hw. */ | |
5763 | ||
c8966e10 | 5764 | |
4afe8d33 BW |
5765 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); |
5766 | ||
7f88da0c | 5767 | I915_WRITE(_3D_CHICKEN3, |
b3f9ad93 | 5768 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); |
7f88da0c | 5769 | |
242a4018 | 5770 | |
ab57fff1 | 5771 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 5772 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 5773 | |
ab57fff1 | 5774 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
5775 | I915_WRITE(CHICKEN_PAR1_1, |
5776 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
5777 | ||
ab57fff1 | 5778 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 5779 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 5780 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 5781 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 5782 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 5783 | } |
63801f21 | 5784 | |
ab57fff1 BW |
5785 | /* WaVSRefCountFullforceMissDisable:bdw */ |
5786 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
5787 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
5788 | I915_READ(GEN7_FF_THREAD_MODE) & | |
5789 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 5790 | |
295e8bb7 VS |
5791 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
5792 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
5793 | |
5794 | /* WaDisableSDEUnitClockGating:bdw */ | |
5795 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
5796 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 5797 | |
89d6b2b8 | 5798 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
5799 | } |
5800 | ||
cad2a2d7 ED |
5801 | static void haswell_init_clock_gating(struct drm_device *dev) |
5802 | { | |
5803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 5804 | |
017636cc | 5805 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 5806 | |
f3fc4884 FJ |
5807 | /* L3 caching of data atomics doesn't work -- disable it. */ |
5808 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
5809 | I915_WRITE(HSW_ROW_CHICKEN3, | |
5810 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
5811 | ||
ecdb4eb7 | 5812 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
5813 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5814 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5815 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5816 | ||
e36ea7ff VS |
5817 | /* WaVSRefCountFullforceMissDisable:hsw */ |
5818 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
5819 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 5820 | |
4e04632e AG |
5821 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
5822 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5823 | ||
fe27c606 CW |
5824 | /* enable HiZ Raw Stall Optimization */ |
5825 | I915_WRITE(CACHE_MODE_0_GEN7, | |
5826 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
5827 | ||
ecdb4eb7 | 5828 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
5829 | I915_WRITE(CACHE_MODE_1, |
5830 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 5831 | |
a12c4967 VS |
5832 | /* |
5833 | * BSpec recommends 8x4 when MSAA is used, | |
5834 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5835 | * |
5836 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5837 | * disable bit, which we don't touch here, but it's good | |
5838 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
5839 | */ |
5840 | I915_WRITE(GEN7_GT_MODE, | |
5841 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5842 | ||
ecdb4eb7 | 5843 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
5844 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
5845 | ||
90a88643 PZ |
5846 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
5847 | I915_WRITE(CHICKEN_PAR1_1, | |
5848 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 5849 | |
17a303ec | 5850 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
5851 | } |
5852 | ||
1fa61106 | 5853 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5854 | { |
5855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 5856 | uint32_t snpcr; |
6f1d69b0 | 5857 | |
017636cc | 5858 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5859 | |
231e54f6 | 5860 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 5861 | |
ecdb4eb7 | 5862 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
5863 | I915_WRITE(_3D_CHICKEN3, |
5864 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
5865 | ||
ecdb4eb7 | 5866 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
5867 | I915_WRITE(IVB_CHICKEN3, |
5868 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
5869 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
5870 | ||
ecdb4eb7 | 5871 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
5872 | if (IS_IVB_GT1(dev)) |
5873 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
5874 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 5875 | |
4e04632e AG |
5876 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
5877 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5878 | ||
ecdb4eb7 | 5879 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
5880 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
5881 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
5882 | ||
ecdb4eb7 | 5883 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
5884 | I915_WRITE(GEN7_L3CNTLREG1, |
5885 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
5886 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
5887 | GEN7_WA_L3_CHICKEN_MODE); |
5888 | if (IS_IVB_GT1(dev)) | |
5889 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5890 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
5891 | else { |
5892 | /* must write both registers */ | |
5893 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5894 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
5895 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
5896 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 5897 | } |
6f1d69b0 | 5898 | |
ecdb4eb7 | 5899 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
5900 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
5901 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
5902 | ||
1b80a19a | 5903 | /* |
0f846f81 | 5904 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 5905 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
5906 | */ |
5907 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 5908 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 5909 | |
ecdb4eb7 | 5910 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
5911 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5912 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5913 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5914 | ||
0e088b8f | 5915 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
5916 | |
5917 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 5918 | |
22721343 CW |
5919 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
5920 | /* enable HiZ Raw Stall Optimization */ | |
5921 | I915_WRITE(CACHE_MODE_0_GEN7, | |
5922 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
5923 | } | |
116f2b6d | 5924 | |
ecdb4eb7 | 5925 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
5926 | I915_WRITE(CACHE_MODE_1, |
5927 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 5928 | |
a607c1a4 VS |
5929 | /* |
5930 | * BSpec recommends 8x4 when MSAA is used, | |
5931 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5932 | * |
5933 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5934 | * disable bit, which we don't touch here, but it's good | |
5935 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
5936 | */ |
5937 | I915_WRITE(GEN7_GT_MODE, | |
5938 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5939 | ||
20848223 BW |
5940 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
5941 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5942 | snpcr |= GEN6_MBC_SNPCR_MED; | |
5943 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 5944 | |
ab5c608b BW |
5945 | if (!HAS_PCH_NOP(dev)) |
5946 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
5947 | |
5948 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5949 | } |
5950 | ||
1fa61106 | 5951 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5952 | { |
5953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 5954 | |
d7fe0cc0 | 5955 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 5956 | |
ecdb4eb7 | 5957 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
5958 | I915_WRITE(_3D_CHICKEN3, |
5959 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
5960 | ||
ecdb4eb7 | 5961 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
5962 | I915_WRITE(IVB_CHICKEN3, |
5963 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
5964 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
5965 | ||
fad7d36e | 5966 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 5967 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 5968 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
5969 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
5970 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 5971 | |
4e04632e AG |
5972 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
5973 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5974 | ||
ecdb4eb7 | 5975 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
5976 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
5977 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
5978 | ||
ecdb4eb7 | 5979 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
5980 | I915_WRITE(GEN7_ROW_CHICKEN2, |
5981 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
5982 | ||
ecdb4eb7 | 5983 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
5984 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5985 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5986 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5987 | ||
46680e0a VS |
5988 | gen7_setup_fixed_func_scheduler(dev_priv); |
5989 | ||
3c0edaeb | 5990 | /* |
0f846f81 | 5991 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 5992 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
5993 | */ |
5994 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 5995 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 5996 | |
c98f5062 AG |
5997 | /* WaDisableL3Bank2xClockGate:vlv |
5998 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
5999 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6000 | I915_WRITE(GEN7_UCGCTL4, | |
6001 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6002 | |
e0d8d59b | 6003 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6f1d69b0 | 6004 | |
afd58e79 VS |
6005 | /* |
6006 | * BSpec says this must be set, even though | |
6007 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6008 | */ | |
6b26c86d DV |
6009 | I915_WRITE(CACHE_MODE_1, |
6010 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6011 | |
031994ee VS |
6012 | /* |
6013 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6014 | * This is the hardware default actually. | |
6015 | */ | |
6016 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6017 | ||
2d809570 | 6018 | /* |
ecdb4eb7 | 6019 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6020 | * Disable clock gating on th GCFG unit to prevent a delay |
6021 | * in the reporting of vblank events. | |
6022 | */ | |
7a0d1eed | 6023 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6024 | } |
6025 | ||
a4565da8 VS |
6026 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6027 | { | |
6028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6029 | ||
6030 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6031 | ||
6032 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
dd811e70 | 6033 | |
232ce337 VS |
6034 | /* WaVSRefCountFullforceMissDisable:chv */ |
6035 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6036 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6037 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6038 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6039 | |
6040 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6041 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6042 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6043 | |
6044 | /* WaDisableCSUnitClockGating:chv */ | |
6045 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6046 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6047 | |
6048 | /* WaDisableSDEUnitClockGating:chv */ | |
6049 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6050 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
e0d34ce7 | 6051 | |
e4443e45 VS |
6052 | /* WaDisableGunitClockGating:chv (pre-production hw) */ |
6053 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) | | |
6054 | GINT_DIS); | |
6055 | ||
6056 | /* WaDisableFfDopClockGating:chv (pre-production hw) */ | |
6057 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6058 | _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); | |
6059 | ||
6060 | /* WaDisableDopClockGating:chv (pre-production hw) */ | |
e4443e45 VS |
6061 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
6062 | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
a4565da8 VS |
6063 | } |
6064 | ||
1fa61106 | 6065 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6066 | { |
6067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6068 | uint32_t dspclk_gate; | |
6069 | ||
6070 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6071 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6072 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6073 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6074 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6075 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6076 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6077 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6078 | if (IS_GM45(dev)) | |
6079 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6080 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6081 | |
6082 | /* WaDisableRenderCachePipelinedFlush */ | |
6083 | I915_WRITE(CACHE_MODE_0, | |
6084 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6085 | |
4e04632e AG |
6086 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6087 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6088 | ||
0e088b8f | 6089 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6090 | } |
6091 | ||
1fa61106 | 6092 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6093 | { |
6094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6095 | ||
6096 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6097 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6098 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6099 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6100 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6101 | I915_WRITE(MI_ARB_STATE, |
6102 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6103 | |
6104 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6105 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6106 | } |
6107 | ||
1fa61106 | 6108 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6109 | { |
6110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6111 | ||
6112 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6113 | I965_RCC_CLOCK_GATE_DISABLE | | |
6114 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6115 | I965_ISC_CLOCK_GATE_DISABLE | | |
6116 | I965_FBC_CLOCK_GATE_DISABLE); | |
6117 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6118 | I915_WRITE(MI_ARB_STATE, |
6119 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6120 | |
6121 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6122 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6123 | } |
6124 | ||
1fa61106 | 6125 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6126 | { |
6127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6128 | u32 dstate = I915_READ(D_STATE); | |
6129 | ||
6130 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6131 | DSTATE_DOT_CLOCK_GATING; | |
6132 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6133 | |
6134 | if (IS_PINEVIEW(dev)) | |
6135 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6136 | |
6137 | /* IIR "flip pending" means done if this bit is set */ | |
6138 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6139 | |
6140 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6141 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6142 | |
6143 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6144 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6145 | |
6146 | I915_WRITE(MI_ARB_STATE, | |
6147 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6148 | } |
6149 | ||
1fa61106 | 6150 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6151 | { |
6152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6153 | ||
6154 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6155 | |
6156 | /* interrupts should cause a wake up from C3 */ | |
6157 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6158 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6159 | |
6160 | I915_WRITE(MEM_MODE, | |
6161 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6162 | } |
6163 | ||
1fa61106 | 6164 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6165 | { |
6166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6167 | ||
6168 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6169 | |
6170 | I915_WRITE(MEM_MODE, | |
6171 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6172 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6173 | } |
6174 | ||
6f1d69b0 ED |
6175 | void intel_init_clock_gating(struct drm_device *dev) |
6176 | { | |
6177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6178 | ||
6179 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6180 | } |
6181 | ||
7d708ee4 ID |
6182 | void intel_suspend_hw(struct drm_device *dev) |
6183 | { | |
6184 | if (HAS_PCH_LPT(dev)) | |
6185 | lpt_suspend_hw(dev); | |
6186 | } | |
6187 | ||
c1ca727f ID |
6188 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
6189 | for (i = 0; \ | |
6190 | i < (power_domains)->power_well_count && \ | |
6191 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
6192 | i++) \ | |
6193 | if ((power_well)->domains & (domain_mask)) | |
6194 | ||
6195 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
6196 | for (i = (power_domains)->power_well_count - 1; \ | |
6197 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
6198 | i--) \ | |
6199 | if ((power_well)->domains & (domain_mask)) | |
6200 | ||
15d199ea PZ |
6201 | /** |
6202 | * We should only use the power well if we explicitly asked the hardware to | |
6203 | * enable it, so check if it's enabled and also check if we've requested it to | |
6204 | * be enabled. | |
6205 | */ | |
da7e29bd | 6206 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
c1ca727f ID |
6207 | struct i915_power_well *power_well) |
6208 | { | |
c1ca727f ID |
6209 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
6210 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
6211 | } | |
6212 | ||
bfafe93a ID |
6213 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
6214 | enum intel_display_power_domain domain) | |
ddf9c536 | 6215 | { |
ddf9c536 | 6216 | struct i915_power_domains *power_domains; |
b8c000d9 ID |
6217 | struct i915_power_well *power_well; |
6218 | bool is_enabled; | |
6219 | int i; | |
6220 | ||
6221 | if (dev_priv->pm.suspended) | |
6222 | return false; | |
ddf9c536 ID |
6223 | |
6224 | power_domains = &dev_priv->power_domains; | |
bfafe93a | 6225 | |
b8c000d9 | 6226 | is_enabled = true; |
bfafe93a | 6227 | |
b8c000d9 ID |
6228 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
6229 | if (power_well->always_on) | |
6230 | continue; | |
ddf9c536 | 6231 | |
bfafe93a | 6232 | if (!power_well->hw_enabled) { |
b8c000d9 ID |
6233 | is_enabled = false; |
6234 | break; | |
6235 | } | |
6236 | } | |
bfafe93a | 6237 | |
b8c000d9 | 6238 | return is_enabled; |
ddf9c536 ID |
6239 | } |
6240 | ||
da7e29bd | 6241 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
b97186f0 | 6242 | enum intel_display_power_domain domain) |
15d199ea | 6243 | { |
c1ca727f | 6244 | struct i915_power_domains *power_domains; |
bfafe93a | 6245 | bool ret; |
882244a3 | 6246 | |
c1ca727f ID |
6247 | power_domains = &dev_priv->power_domains; |
6248 | ||
c1ca727f | 6249 | mutex_lock(&power_domains->lock); |
bfafe93a | 6250 | ret = intel_display_power_enabled_unlocked(dev_priv, domain); |
c1ca727f ID |
6251 | mutex_unlock(&power_domains->lock); |
6252 | ||
bfafe93a | 6253 | return ret; |
15d199ea PZ |
6254 | } |
6255 | ||
93c73e8c ID |
6256 | /* |
6257 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
6258 | * when not needed anymore. We have 4 registers that can request the power well | |
6259 | * to be enabled, and it will only be disabled if none of the registers is | |
6260 | * requesting it to be enabled. | |
6261 | */ | |
d5e8fdc8 PZ |
6262 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
6263 | { | |
6264 | struct drm_device *dev = dev_priv->dev; | |
d5e8fdc8 | 6265 | |
f9dcb0df PZ |
6266 | /* |
6267 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
6268 | * we'll get unclaimed register interrupts. This stops after we write | |
6269 | * anything to the VGA MSR register. The vgacon module uses this | |
6270 | * register all the time, so if we unbind our driver and, as a | |
6271 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
6272 | * console_unlock(). So make here we touch the VGA MSR register, making | |
6273 | * sure vgacon can keep working normally without triggering interrupts | |
6274 | * and error messages. | |
6275 | */ | |
6276 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6277 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
6278 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6279 | ||
08524a9f | 6280 | if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) |
d49bdb0e | 6281 | gen8_irq_power_well_post_enable(dev_priv); |
d5e8fdc8 PZ |
6282 | } |
6283 | ||
da7e29bd | 6284 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
c1ca727f | 6285 | struct i915_power_well *power_well, bool enable) |
d0d3e513 | 6286 | { |
fa42e23c PZ |
6287 | bool is_enabled, enable_requested; |
6288 | uint32_t tmp; | |
d0d3e513 | 6289 | |
fa42e23c | 6290 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
6aedd1f5 PZ |
6291 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
6292 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
d0d3e513 | 6293 | |
fa42e23c PZ |
6294 | if (enable) { |
6295 | if (!enable_requested) | |
6aedd1f5 PZ |
6296 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
6297 | HSW_PWR_WELL_ENABLE_REQUEST); | |
d0d3e513 | 6298 | |
fa42e23c PZ |
6299 | if (!is_enabled) { |
6300 | DRM_DEBUG_KMS("Enabling power well\n"); | |
6301 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
6aedd1f5 | 6302 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
fa42e23c PZ |
6303 | DRM_ERROR("Timeout enabling power well\n"); |
6304 | } | |
596cc11e | 6305 | |
d5e8fdc8 | 6306 | hsw_power_well_post_enable(dev_priv); |
fa42e23c PZ |
6307 | } else { |
6308 | if (enable_requested) { | |
6309 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
9dbd8feb | 6310 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
fa42e23c | 6311 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
d0d3e513 ED |
6312 | } |
6313 | } | |
fa42e23c | 6314 | } |
d0d3e513 | 6315 | |
c6cb582e ID |
6316 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
6317 | struct i915_power_well *power_well) | |
6318 | { | |
6319 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
6320 | ||
6321 | /* | |
6322 | * We're taking over the BIOS, so clear any requests made by it since | |
6323 | * the driver is in charge now. | |
6324 | */ | |
6325 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
6326 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
6327 | } | |
6328 | ||
6329 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
6330 | struct i915_power_well *power_well) | |
6331 | { | |
c6cb582e ID |
6332 | hsw_set_power_well(dev_priv, power_well, true); |
6333 | } | |
6334 | ||
6335 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
6336 | struct i915_power_well *power_well) | |
6337 | { | |
6338 | hsw_set_power_well(dev_priv, power_well, false); | |
c6cb582e ID |
6339 | } |
6340 | ||
a45f4466 ID |
6341 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
6342 | struct i915_power_well *power_well) | |
6343 | { | |
6344 | } | |
6345 | ||
6346 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
6347 | struct i915_power_well *power_well) | |
6348 | { | |
6349 | return true; | |
6350 | } | |
6351 | ||
d2011dc8 VS |
6352 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
6353 | struct i915_power_well *power_well, bool enable) | |
77961eb9 | 6354 | { |
d2011dc8 | 6355 | enum punit_power_well power_well_id = power_well->data; |
77961eb9 ID |
6356 | u32 mask; |
6357 | u32 state; | |
6358 | u32 ctrl; | |
6359 | ||
6360 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
6361 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
6362 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
6363 | ||
6364 | mutex_lock(&dev_priv->rps.hw_lock); | |
6365 | ||
6366 | #define COND \ | |
6367 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
6368 | ||
6369 | if (COND) | |
6370 | goto out; | |
6371 | ||
6372 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
6373 | ctrl &= ~mask; | |
6374 | ctrl |= state; | |
6375 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
6376 | ||
6377 | if (wait_for(COND, 100)) | |
6378 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
6379 | state, | |
6380 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
6381 | ||
6382 | #undef COND | |
6383 | ||
6384 | out: | |
6385 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6386 | } | |
6387 | ||
6388 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
6389 | struct i915_power_well *power_well) | |
6390 | { | |
6391 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
6392 | } | |
6393 | ||
6394 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
6395 | struct i915_power_well *power_well) | |
6396 | { | |
6397 | vlv_set_power_well(dev_priv, power_well, true); | |
6398 | } | |
6399 | ||
6400 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
6401 | struct i915_power_well *power_well) | |
6402 | { | |
6403 | vlv_set_power_well(dev_priv, power_well, false); | |
6404 | } | |
6405 | ||
6406 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
6407 | struct i915_power_well *power_well) | |
6408 | { | |
6409 | int power_well_id = power_well->data; | |
6410 | bool enabled = false; | |
6411 | u32 mask; | |
6412 | u32 state; | |
6413 | u32 ctrl; | |
6414 | ||
6415 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
6416 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
6417 | ||
6418 | mutex_lock(&dev_priv->rps.hw_lock); | |
6419 | ||
6420 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
6421 | /* | |
6422 | * We only ever set the power-on and power-gate states, anything | |
6423 | * else is unexpected. | |
6424 | */ | |
6425 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
6426 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
6427 | if (state == ctrl) | |
6428 | enabled = true; | |
6429 | ||
6430 | /* | |
6431 | * A transient state at this point would mean some unexpected party | |
6432 | * is poking at the power controls too. | |
6433 | */ | |
6434 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
6435 | WARN_ON(ctrl != state); | |
6436 | ||
6437 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6438 | ||
6439 | return enabled; | |
6440 | } | |
6441 | ||
6442 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
6443 | struct i915_power_well *power_well) | |
6444 | { | |
6445 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
6446 | ||
6447 | vlv_set_power_well(dev_priv, power_well, true); | |
6448 | ||
6449 | spin_lock_irq(&dev_priv->irq_lock); | |
6450 | valleyview_enable_display_irqs(dev_priv); | |
6451 | spin_unlock_irq(&dev_priv->irq_lock); | |
6452 | ||
6453 | /* | |
0d116a29 ID |
6454 | * During driver initialization/resume we can avoid restoring the |
6455 | * part of the HW/SW state that will be inited anyway explicitly. | |
77961eb9 | 6456 | */ |
0d116a29 ID |
6457 | if (dev_priv->power_domains.initializing) |
6458 | return; | |
6459 | ||
6460 | intel_hpd_init(dev_priv->dev); | |
77961eb9 ID |
6461 | |
6462 | i915_redisable_vga_power_on(dev_priv->dev); | |
6463 | } | |
6464 | ||
6465 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, | |
6466 | struct i915_power_well *power_well) | |
6467 | { | |
77961eb9 ID |
6468 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
6469 | ||
6470 | spin_lock_irq(&dev_priv->irq_lock); | |
77961eb9 ID |
6471 | valleyview_disable_display_irqs(dev_priv); |
6472 | spin_unlock_irq(&dev_priv->irq_lock); | |
6473 | ||
77961eb9 | 6474 | vlv_set_power_well(dev_priv, power_well, false); |
773538e8 VS |
6475 | |
6476 | vlv_power_sequencer_reset(dev_priv); | |
77961eb9 ID |
6477 | } |
6478 | ||
aa519f23 VS |
6479 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
6480 | struct i915_power_well *power_well) | |
6481 | { | |
6482 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
6483 | ||
6484 | /* | |
6485 | * Enable the CRI clock source so we can get at the | |
6486 | * display and the reference clock for VGA | |
6487 | * hotplug / manual detection. | |
6488 | */ | |
6489 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
6490 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
6491 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
6492 | ||
6493 | vlv_set_power_well(dev_priv, power_well, true); | |
6494 | ||
6495 | /* | |
6496 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
6497 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
6498 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
6499 | * b. The other bits such as sfr settings / modesel may all | |
6500 | * be set to 0. | |
6501 | * | |
6502 | * This should only be done on init and resume from S3 with | |
6503 | * both PLLs disabled, or we risk losing DPIO and PLL | |
6504 | * synchronization. | |
6505 | */ | |
6506 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
6507 | } | |
6508 | ||
6509 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
6510 | struct i915_power_well *power_well) | |
6511 | { | |
aa519f23 VS |
6512 | enum pipe pipe; |
6513 | ||
6514 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
6515 | ||
055e393f | 6516 | for_each_pipe(dev_priv, pipe) |
aa519f23 VS |
6517 | assert_pll_disabled(dev_priv, pipe); |
6518 | ||
6519 | /* Assert common reset */ | |
6520 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
6521 | ||
6522 | vlv_set_power_well(dev_priv, power_well, false); | |
6523 | } | |
6524 | ||
5d6f7ea7 VS |
6525 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
6526 | struct i915_power_well *power_well) | |
6527 | { | |
6528 | enum dpio_phy phy; | |
6529 | ||
6530 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
6531 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
6532 | ||
6533 | /* | |
6534 | * Enable the CRI clock source so we can get at the | |
6535 | * display and the reference clock for VGA | |
6536 | * hotplug / manual detection. | |
6537 | */ | |
6538 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
6539 | phy = DPIO_PHY0; | |
6540 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
6541 | DPLL_REFA_CLK_ENABLE_VLV); | |
6542 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
6543 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
6544 | } else { | |
6545 | phy = DPIO_PHY1; | |
6546 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | | |
6547 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
6548 | } | |
6549 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
6550 | vlv_set_power_well(dev_priv, power_well, true); | |
6551 | ||
6552 | /* Poll for phypwrgood signal */ | |
6553 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
6554 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
6555 | ||
efd814b7 VS |
6556 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | |
6557 | PHY_COM_LANE_RESET_DEASSERT(phy)); | |
5d6f7ea7 VS |
6558 | } |
6559 | ||
6560 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
6561 | struct i915_power_well *power_well) | |
6562 | { | |
6563 | enum dpio_phy phy; | |
6564 | ||
6565 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
6566 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
6567 | ||
6568 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
6569 | phy = DPIO_PHY0; | |
6570 | assert_pll_disabled(dev_priv, PIPE_A); | |
6571 | assert_pll_disabled(dev_priv, PIPE_B); | |
6572 | } else { | |
6573 | phy = DPIO_PHY1; | |
6574 | assert_pll_disabled(dev_priv, PIPE_C); | |
6575 | } | |
6576 | ||
efd814b7 VS |
6577 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & |
6578 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); | |
5d6f7ea7 VS |
6579 | |
6580 | vlv_set_power_well(dev_priv, power_well, false); | |
6581 | } | |
6582 | ||
26972b0a VS |
6583 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, |
6584 | struct i915_power_well *power_well) | |
6585 | { | |
6586 | enum pipe pipe = power_well->data; | |
6587 | bool enabled; | |
6588 | u32 state, ctrl; | |
6589 | ||
6590 | mutex_lock(&dev_priv->rps.hw_lock); | |
6591 | ||
6592 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
6593 | /* | |
6594 | * We only ever set the power-on and power-gate states, anything | |
6595 | * else is unexpected. | |
6596 | */ | |
6597 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
6598 | enabled = state == DP_SSS_PWR_ON(pipe); | |
6599 | ||
6600 | /* | |
6601 | * A transient state at this point would mean some unexpected party | |
6602 | * is poking at the power controls too. | |
6603 | */ | |
6604 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
6605 | WARN_ON(ctrl << 16 != state); | |
6606 | ||
6607 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6608 | ||
6609 | return enabled; | |
6610 | } | |
6611 | ||
6612 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
6613 | struct i915_power_well *power_well, | |
6614 | bool enable) | |
6615 | { | |
6616 | enum pipe pipe = power_well->data; | |
6617 | u32 state; | |
6618 | u32 ctrl; | |
6619 | ||
6620 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
6621 | ||
6622 | mutex_lock(&dev_priv->rps.hw_lock); | |
6623 | ||
6624 | #define COND \ | |
6625 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
6626 | ||
6627 | if (COND) | |
6628 | goto out; | |
6629 | ||
6630 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6631 | ctrl &= ~DP_SSC_MASK(pipe); | |
6632 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
6633 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
6634 | ||
6635 | if (wait_for(COND, 100)) | |
6636 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
6637 | state, | |
6638 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
6639 | ||
6640 | #undef COND | |
6641 | ||
6642 | out: | |
6643 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6644 | } | |
6645 | ||
6646 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
6647 | struct i915_power_well *power_well) | |
6648 | { | |
6649 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); | |
6650 | } | |
6651 | ||
6652 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
6653 | struct i915_power_well *power_well) | |
6654 | { | |
6655 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
6656 | power_well->data != PIPE_B && | |
6657 | power_well->data != PIPE_C); | |
6658 | ||
6659 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
6660 | } | |
6661 | ||
6662 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
6663 | struct i915_power_well *power_well) | |
6664 | { | |
6665 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
6666 | power_well->data != PIPE_B && | |
6667 | power_well->data != PIPE_C); | |
6668 | ||
6669 | chv_set_pipe_power_well(dev_priv, power_well, false); | |
6670 | } | |
6671 | ||
25eaa003 ID |
6672 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
6673 | struct i915_power_well *power_well) | |
6674 | { | |
6675 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); | |
6676 | ||
6677 | if (power_well->always_on || !i915.disable_power_well) { | |
6678 | if (!enabled) | |
6679 | goto mismatch; | |
6680 | ||
6681 | return; | |
6682 | } | |
6683 | ||
6684 | if (enabled != (power_well->count > 0)) | |
6685 | goto mismatch; | |
6686 | ||
6687 | return; | |
6688 | ||
6689 | mismatch: | |
6690 | WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", | |
6691 | power_well->name, power_well->always_on, enabled, | |
6692 | power_well->count, i915.disable_power_well); | |
6693 | } | |
6694 | ||
da7e29bd | 6695 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
6765625e VS |
6696 | enum intel_display_power_domain domain) |
6697 | { | |
83c00f55 | 6698 | struct i915_power_domains *power_domains; |
c1ca727f ID |
6699 | struct i915_power_well *power_well; |
6700 | int i; | |
6765625e | 6701 | |
9e6ea71a PZ |
6702 | intel_runtime_pm_get(dev_priv); |
6703 | ||
83c00f55 ID |
6704 | power_domains = &dev_priv->power_domains; |
6705 | ||
6706 | mutex_lock(&power_domains->lock); | |
1da51581 | 6707 | |
25eaa003 ID |
6708 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
6709 | if (!power_well->count++) { | |
6710 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
c6cb582e | 6711 | power_well->ops->enable(dev_priv, power_well); |
bfafe93a | 6712 | power_well->hw_enabled = true; |
25eaa003 ID |
6713 | } |
6714 | ||
6715 | check_power_well_state(dev_priv, power_well); | |
6716 | } | |
1da51581 | 6717 | |
ddf9c536 ID |
6718 | power_domains->domain_use_count[domain]++; |
6719 | ||
83c00f55 | 6720 | mutex_unlock(&power_domains->lock); |
6765625e VS |
6721 | } |
6722 | ||
da7e29bd | 6723 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
6765625e VS |
6724 | enum intel_display_power_domain domain) |
6725 | { | |
83c00f55 | 6726 | struct i915_power_domains *power_domains; |
c1ca727f ID |
6727 | struct i915_power_well *power_well; |
6728 | int i; | |
6765625e | 6729 | |
83c00f55 ID |
6730 | power_domains = &dev_priv->power_domains; |
6731 | ||
6732 | mutex_lock(&power_domains->lock); | |
1da51581 | 6733 | |
1da51581 ID |
6734 | WARN_ON(!power_domains->domain_use_count[domain]); |
6735 | power_domains->domain_use_count[domain]--; | |
ddf9c536 | 6736 | |
70bf407c ID |
6737 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
6738 | WARN_ON(!power_well->count); | |
6739 | ||
25eaa003 ID |
6740 | if (!--power_well->count && i915.disable_power_well) { |
6741 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
bfafe93a | 6742 | power_well->hw_enabled = false; |
c6cb582e | 6743 | power_well->ops->disable(dev_priv, power_well); |
25eaa003 ID |
6744 | } |
6745 | ||
6746 | check_power_well_state(dev_priv, power_well); | |
70bf407c | 6747 | } |
1da51581 | 6748 | |
83c00f55 | 6749 | mutex_unlock(&power_domains->lock); |
9e6ea71a PZ |
6750 | |
6751 | intel_runtime_pm_put(dev_priv); | |
6765625e VS |
6752 | } |
6753 | ||
83c00f55 | 6754 | static struct i915_power_domains *hsw_pwr; |
a38911a3 WX |
6755 | |
6756 | /* Display audio driver power well request */ | |
74b0c2d7 | 6757 | int i915_request_power_well(void) |
a38911a3 | 6758 | { |
b4ed4484 ID |
6759 | struct drm_i915_private *dev_priv; |
6760 | ||
74b0c2d7 TI |
6761 | if (!hsw_pwr) |
6762 | return -ENODEV; | |
a38911a3 | 6763 | |
b4ed4484 ID |
6764 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6765 | power_domains); | |
da7e29bd | 6766 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
74b0c2d7 | 6767 | return 0; |
a38911a3 WX |
6768 | } |
6769 | EXPORT_SYMBOL_GPL(i915_request_power_well); | |
6770 | ||
6771 | /* Display audio driver power well release */ | |
74b0c2d7 | 6772 | int i915_release_power_well(void) |
a38911a3 | 6773 | { |
b4ed4484 ID |
6774 | struct drm_i915_private *dev_priv; |
6775 | ||
74b0c2d7 TI |
6776 | if (!hsw_pwr) |
6777 | return -ENODEV; | |
a38911a3 | 6778 | |
b4ed4484 ID |
6779 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6780 | power_domains); | |
da7e29bd | 6781 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
74b0c2d7 | 6782 | return 0; |
a38911a3 WX |
6783 | } |
6784 | EXPORT_SYMBOL_GPL(i915_release_power_well); | |
6785 | ||
c149dcb5 JN |
6786 | /* |
6787 | * Private interface for the audio driver to get CDCLK in kHz. | |
6788 | * | |
6789 | * Caller must request power well using i915_request_power_well() prior to | |
6790 | * making the call. | |
6791 | */ | |
6792 | int i915_get_cdclk_freq(void) | |
6793 | { | |
6794 | struct drm_i915_private *dev_priv; | |
6795 | ||
6796 | if (!hsw_pwr) | |
6797 | return -ENODEV; | |
6798 | ||
6799 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, | |
6800 | power_domains); | |
6801 | ||
6802 | return intel_ddi_get_cdclk_freq(dev_priv); | |
6803 | } | |
6804 | EXPORT_SYMBOL_GPL(i915_get_cdclk_freq); | |
6805 | ||
6806 | ||
efcad917 ID |
6807 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
6808 | ||
6809 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
6810 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
f5938f36 | 6811 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
319be8ae ID |
6812 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
6813 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
6814 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6815 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6816 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6817 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6818 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
6819 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
6820 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
bd2bb1b9 | 6821 | BIT(POWER_DOMAIN_PLLS) | \ |
f5938f36 | 6822 | BIT(POWER_DOMAIN_INIT)) |
efcad917 ID |
6823 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
6824 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
6825 | BIT(POWER_DOMAIN_INIT)) | |
6826 | ||
6827 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
6828 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
6829 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
6830 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
6831 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
6832 | BIT(POWER_DOMAIN_INIT)) | |
6833 | ||
77961eb9 ID |
6834 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
6835 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
6836 | ||
6837 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
6838 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6839 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6840 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6841 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6842 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
6843 | BIT(POWER_DOMAIN_INIT)) | |
6844 | ||
6845 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
6846 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6847 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6848 | BIT(POWER_DOMAIN_INIT)) | |
6849 | ||
6850 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
6851 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6852 | BIT(POWER_DOMAIN_INIT)) | |
6853 | ||
6854 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
6855 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6856 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6857 | BIT(POWER_DOMAIN_INIT)) | |
6858 | ||
6859 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
6860 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6861 | BIT(POWER_DOMAIN_INIT)) | |
6862 | ||
26972b0a VS |
6863 | #define CHV_PIPE_A_POWER_DOMAINS ( \ |
6864 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
6865 | BIT(POWER_DOMAIN_INIT)) | |
6866 | ||
6867 | #define CHV_PIPE_B_POWER_DOMAINS ( \ | |
6868 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
6869 | BIT(POWER_DOMAIN_INIT)) | |
6870 | ||
6871 | #define CHV_PIPE_C_POWER_DOMAINS ( \ | |
6872 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
6873 | BIT(POWER_DOMAIN_INIT)) | |
6874 | ||
5d6f7ea7 VS |
6875 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
6876 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6877 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6878 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6879 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6880 | BIT(POWER_DOMAIN_INIT)) | |
6881 | ||
6882 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
6883 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
6884 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
6885 | BIT(POWER_DOMAIN_INIT)) | |
6886 | ||
2ce147f3 VS |
6887 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ |
6888 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
6889 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
6890 | BIT(POWER_DOMAIN_INIT)) | |
6891 | ||
6892 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ | |
6893 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
6894 | BIT(POWER_DOMAIN_INIT)) | |
6895 | ||
a45f4466 ID |
6896 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
6897 | .sync_hw = i9xx_always_on_power_well_noop, | |
6898 | .enable = i9xx_always_on_power_well_noop, | |
6899 | .disable = i9xx_always_on_power_well_noop, | |
6900 | .is_enabled = i9xx_always_on_power_well_enabled, | |
6901 | }; | |
c6cb582e | 6902 | |
26972b0a VS |
6903 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { |
6904 | .sync_hw = chv_pipe_power_well_sync_hw, | |
6905 | .enable = chv_pipe_power_well_enable, | |
6906 | .disable = chv_pipe_power_well_disable, | |
6907 | .is_enabled = chv_pipe_power_well_enabled, | |
6908 | }; | |
6909 | ||
5d6f7ea7 VS |
6910 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { |
6911 | .sync_hw = vlv_power_well_sync_hw, | |
6912 | .enable = chv_dpio_cmn_power_well_enable, | |
6913 | .disable = chv_dpio_cmn_power_well_disable, | |
6914 | .is_enabled = vlv_power_well_enabled, | |
6915 | }; | |
6916 | ||
1c2256df ID |
6917 | static struct i915_power_well i9xx_always_on_power_well[] = { |
6918 | { | |
6919 | .name = "always-on", | |
6920 | .always_on = 1, | |
6921 | .domains = POWER_DOMAIN_MASK, | |
c6cb582e | 6922 | .ops = &i9xx_always_on_power_well_ops, |
1c2256df ID |
6923 | }, |
6924 | }; | |
6925 | ||
c6cb582e ID |
6926 | static const struct i915_power_well_ops hsw_power_well_ops = { |
6927 | .sync_hw = hsw_power_well_sync_hw, | |
6928 | .enable = hsw_power_well_enable, | |
6929 | .disable = hsw_power_well_disable, | |
6930 | .is_enabled = hsw_power_well_enabled, | |
6931 | }; | |
6932 | ||
c1ca727f | 6933 | static struct i915_power_well hsw_power_wells[] = { |
6f3ef5dd ID |
6934 | { |
6935 | .name = "always-on", | |
6936 | .always_on = 1, | |
6937 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 6938 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 6939 | }, |
c1ca727f ID |
6940 | { |
6941 | .name = "display", | |
efcad917 | 6942 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 6943 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
6944 | }, |
6945 | }; | |
6946 | ||
6947 | static struct i915_power_well bdw_power_wells[] = { | |
6f3ef5dd ID |
6948 | { |
6949 | .name = "always-on", | |
6950 | .always_on = 1, | |
6951 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 6952 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 6953 | }, |
c1ca727f ID |
6954 | { |
6955 | .name = "display", | |
efcad917 | 6956 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 6957 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
6958 | }, |
6959 | }; | |
6960 | ||
77961eb9 ID |
6961 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
6962 | .sync_hw = vlv_power_well_sync_hw, | |
6963 | .enable = vlv_display_power_well_enable, | |
6964 | .disable = vlv_display_power_well_disable, | |
6965 | .is_enabled = vlv_power_well_enabled, | |
6966 | }; | |
6967 | ||
aa519f23 VS |
6968 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
6969 | .sync_hw = vlv_power_well_sync_hw, | |
6970 | .enable = vlv_dpio_cmn_power_well_enable, | |
6971 | .disable = vlv_dpio_cmn_power_well_disable, | |
6972 | .is_enabled = vlv_power_well_enabled, | |
6973 | }; | |
6974 | ||
77961eb9 ID |
6975 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
6976 | .sync_hw = vlv_power_well_sync_hw, | |
6977 | .enable = vlv_power_well_enable, | |
6978 | .disable = vlv_power_well_disable, | |
6979 | .is_enabled = vlv_power_well_enabled, | |
6980 | }; | |
6981 | ||
6982 | static struct i915_power_well vlv_power_wells[] = { | |
6983 | { | |
6984 | .name = "always-on", | |
6985 | .always_on = 1, | |
6986 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
6987 | .ops = &i9xx_always_on_power_well_ops, | |
6988 | }, | |
6989 | { | |
6990 | .name = "display", | |
6991 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
6992 | .data = PUNIT_POWER_WELL_DISP2D, | |
6993 | .ops = &vlv_display_power_well_ops, | |
6994 | }, | |
77961eb9 ID |
6995 | { |
6996 | .name = "dpio-tx-b-01", | |
6997 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
6998 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
6999 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7000 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7001 | .ops = &vlv_dpio_power_well_ops, | |
7002 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
7003 | }, | |
7004 | { | |
7005 | .name = "dpio-tx-b-23", | |
7006 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
7007 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
7008 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7009 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7010 | .ops = &vlv_dpio_power_well_ops, | |
7011 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
7012 | }, | |
7013 | { | |
7014 | .name = "dpio-tx-c-01", | |
7015 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
7016 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
7017 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7018 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7019 | .ops = &vlv_dpio_power_well_ops, | |
7020 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
7021 | }, | |
7022 | { | |
7023 | .name = "dpio-tx-c-23", | |
7024 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
7025 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
7026 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7027 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7028 | .ops = &vlv_dpio_power_well_ops, | |
7029 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
7030 | }, | |
f099a3c6 JB |
7031 | { |
7032 | .name = "dpio-common", | |
7033 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
7034 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
aa519f23 | 7035 | .ops = &vlv_dpio_cmn_power_well_ops, |
f099a3c6 | 7036 | }, |
77961eb9 ID |
7037 | }; |
7038 | ||
4811ff4f VS |
7039 | static struct i915_power_well chv_power_wells[] = { |
7040 | { | |
7041 | .name = "always-on", | |
7042 | .always_on = 1, | |
7043 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
7044 | .ops = &i9xx_always_on_power_well_ops, | |
7045 | }, | |
f07057d1 VS |
7046 | #if 0 |
7047 | { | |
7048 | .name = "display", | |
7049 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
7050 | .data = PUNIT_POWER_WELL_DISP2D, | |
7051 | .ops = &vlv_display_power_well_ops, | |
7052 | }, | |
26972b0a VS |
7053 | { |
7054 | .name = "pipe-a", | |
7055 | .domains = CHV_PIPE_A_POWER_DOMAINS, | |
7056 | .data = PIPE_A, | |
7057 | .ops = &chv_pipe_power_well_ops, | |
7058 | }, | |
7059 | { | |
7060 | .name = "pipe-b", | |
7061 | .domains = CHV_PIPE_B_POWER_DOMAINS, | |
7062 | .data = PIPE_B, | |
7063 | .ops = &chv_pipe_power_well_ops, | |
7064 | }, | |
7065 | { | |
7066 | .name = "pipe-c", | |
7067 | .domains = CHV_PIPE_C_POWER_DOMAINS, | |
7068 | .data = PIPE_C, | |
7069 | .ops = &chv_pipe_power_well_ops, | |
7070 | }, | |
f07057d1 | 7071 | #endif |
5d6f7ea7 VS |
7072 | { |
7073 | .name = "dpio-common-bc", | |
3dd7b974 VS |
7074 | /* |
7075 | * XXX: cmnreset for one PHY seems to disturb the other. | |
7076 | * As a workaround keep both powered on at the same | |
7077 | * time for now. | |
7078 | */ | |
7079 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
5d6f7ea7 VS |
7080 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
7081 | .ops = &chv_dpio_cmn_power_well_ops, | |
7082 | }, | |
7083 | { | |
7084 | .name = "dpio-common-d", | |
3dd7b974 VS |
7085 | /* |
7086 | * XXX: cmnreset for one PHY seems to disturb the other. | |
7087 | * As a workaround keep both powered on at the same | |
7088 | * time for now. | |
7089 | */ | |
7090 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
5d6f7ea7 VS |
7091 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
7092 | .ops = &chv_dpio_cmn_power_well_ops, | |
7093 | }, | |
82583565 VS |
7094 | #if 0 |
7095 | { | |
7096 | .name = "dpio-tx-b-01", | |
7097 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
7098 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
7099 | .ops = &vlv_dpio_power_well_ops, | |
7100 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
7101 | }, | |
7102 | { | |
7103 | .name = "dpio-tx-b-23", | |
7104 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
7105 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
7106 | .ops = &vlv_dpio_power_well_ops, | |
7107 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
7108 | }, | |
7109 | { | |
7110 | .name = "dpio-tx-c-01", | |
7111 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7112 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7113 | .ops = &vlv_dpio_power_well_ops, | |
7114 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
7115 | }, | |
7116 | { | |
7117 | .name = "dpio-tx-c-23", | |
7118 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
7119 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
7120 | .ops = &vlv_dpio_power_well_ops, | |
7121 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
7122 | }, | |
2ce147f3 VS |
7123 | { |
7124 | .name = "dpio-tx-d-01", | |
7125 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
7126 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
7127 | .ops = &vlv_dpio_power_well_ops, | |
7128 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, | |
7129 | }, | |
7130 | { | |
7131 | .name = "dpio-tx-d-23", | |
7132 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
7133 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
7134 | .ops = &vlv_dpio_power_well_ops, | |
7135 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, | |
7136 | }, | |
82583565 | 7137 | #endif |
4811ff4f VS |
7138 | }; |
7139 | ||
d2011dc8 VS |
7140 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
7141 | enum punit_power_well power_well_id) | |
7142 | { | |
7143 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
7144 | struct i915_power_well *power_well; | |
7145 | int i; | |
7146 | ||
7147 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
7148 | if (power_well->data == power_well_id) | |
7149 | return power_well; | |
7150 | } | |
7151 | ||
7152 | return NULL; | |
7153 | } | |
7154 | ||
c1ca727f ID |
7155 | #define set_power_wells(power_domains, __power_wells) ({ \ |
7156 | (power_domains)->power_wells = (__power_wells); \ | |
7157 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
7158 | }) | |
7159 | ||
da7e29bd | 7160 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
a38911a3 | 7161 | { |
83c00f55 | 7162 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
c1ca727f | 7163 | |
83c00f55 | 7164 | mutex_init(&power_domains->lock); |
a38911a3 | 7165 | |
c1ca727f ID |
7166 | /* |
7167 | * The enabling order will be from lower to higher indexed wells, | |
7168 | * the disabling order is reversed. | |
7169 | */ | |
da7e29bd | 7170 | if (IS_HASWELL(dev_priv->dev)) { |
c1ca727f ID |
7171 | set_power_wells(power_domains, hsw_power_wells); |
7172 | hsw_pwr = power_domains; | |
da7e29bd | 7173 | } else if (IS_BROADWELL(dev_priv->dev)) { |
c1ca727f ID |
7174 | set_power_wells(power_domains, bdw_power_wells); |
7175 | hsw_pwr = power_domains; | |
4811ff4f VS |
7176 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
7177 | set_power_wells(power_domains, chv_power_wells); | |
77961eb9 ID |
7178 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
7179 | set_power_wells(power_domains, vlv_power_wells); | |
c1ca727f | 7180 | } else { |
1c2256df | 7181 | set_power_wells(power_domains, i9xx_always_on_power_well); |
c1ca727f | 7182 | } |
a38911a3 WX |
7183 | |
7184 | return 0; | |
7185 | } | |
7186 | ||
da7e29bd | 7187 | void intel_power_domains_remove(struct drm_i915_private *dev_priv) |
a38911a3 WX |
7188 | { |
7189 | hsw_pwr = NULL; | |
7190 | } | |
7191 | ||
da7e29bd | 7192 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
9cdb826c | 7193 | { |
83c00f55 ID |
7194 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
7195 | struct i915_power_well *power_well; | |
c1ca727f | 7196 | int i; |
9cdb826c | 7197 | |
83c00f55 | 7198 | mutex_lock(&power_domains->lock); |
bfafe93a | 7199 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
a45f4466 | 7200 | power_well->ops->sync_hw(dev_priv, power_well); |
bfafe93a ID |
7201 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
7202 | power_well); | |
7203 | } | |
83c00f55 | 7204 | mutex_unlock(&power_domains->lock); |
a38911a3 WX |
7205 | } |
7206 | ||
d2011dc8 VS |
7207 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
7208 | { | |
7209 | struct i915_power_well *cmn = | |
7210 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
7211 | struct i915_power_well *disp2d = | |
7212 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
7213 | ||
7214 | /* nothing to do if common lane is already off */ | |
7215 | if (!cmn->ops->is_enabled(dev_priv, cmn)) | |
7216 | return; | |
7217 | ||
7218 | /* If the display might be already active skip this */ | |
7219 | if (disp2d->ops->is_enabled(dev_priv, disp2d) && | |
7220 | I915_READ(DPIO_CTL) & DPIO_CMNRST) | |
7221 | return; | |
7222 | ||
7223 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
7224 | ||
7225 | /* cmnlane needs DPLL registers */ | |
7226 | disp2d->ops->enable(dev_priv, disp2d); | |
7227 | ||
7228 | /* | |
7229 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
7230 | * Need to assert and de-assert PHY SB reset by gating the | |
7231 | * common lane power, then un-gating it. | |
7232 | * Simply ungating isn't enough to reset the PHY enough to get | |
7233 | * ports and lanes running. | |
7234 | */ | |
7235 | cmn->ops->disable(dev_priv, cmn); | |
7236 | } | |
7237 | ||
da7e29bd | 7238 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
d0d3e513 | 7239 | { |
d2011dc8 | 7240 | struct drm_device *dev = dev_priv->dev; |
0d116a29 ID |
7241 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
7242 | ||
7243 | power_domains->initializing = true; | |
d2011dc8 VS |
7244 | |
7245 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
7246 | mutex_lock(&power_domains->lock); | |
7247 | vlv_cmnlane_wa(dev_priv); | |
7248 | mutex_unlock(&power_domains->lock); | |
7249 | } | |
7250 | ||
fa42e23c | 7251 | /* For now, we need the power well to be always enabled. */ |
da7e29bd ID |
7252 | intel_display_set_init_power(dev_priv, true); |
7253 | intel_power_domains_resume(dev_priv); | |
0d116a29 | 7254 | power_domains->initializing = false; |
d0d3e513 ED |
7255 | } |
7256 | ||
c67a470b PZ |
7257 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
7258 | { | |
d361ae26 | 7259 | intel_runtime_pm_get(dev_priv); |
c67a470b PZ |
7260 | } |
7261 | ||
7262 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) | |
7263 | { | |
d361ae26 | 7264 | intel_runtime_pm_put(dev_priv); |
c67a470b PZ |
7265 | } |
7266 | ||
8a187455 PZ |
7267 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
7268 | { | |
7269 | struct drm_device *dev = dev_priv->dev; | |
7270 | struct device *device = &dev->pdev->dev; | |
7271 | ||
7272 | if (!HAS_RUNTIME_PM(dev)) | |
7273 | return; | |
7274 | ||
7275 | pm_runtime_get_sync(device); | |
7276 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
7277 | } | |
7278 | ||
c6df39b5 ID |
7279 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
7280 | { | |
7281 | struct drm_device *dev = dev_priv->dev; | |
7282 | struct device *device = &dev->pdev->dev; | |
7283 | ||
7284 | if (!HAS_RUNTIME_PM(dev)) | |
7285 | return; | |
7286 | ||
7287 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
7288 | pm_runtime_get_noresume(device); | |
7289 | } | |
7290 | ||
8a187455 PZ |
7291 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
7292 | { | |
7293 | struct drm_device *dev = dev_priv->dev; | |
7294 | struct device *device = &dev->pdev->dev; | |
7295 | ||
7296 | if (!HAS_RUNTIME_PM(dev)) | |
7297 | return; | |
7298 | ||
7299 | pm_runtime_mark_last_busy(device); | |
7300 | pm_runtime_put_autosuspend(device); | |
7301 | } | |
7302 | ||
7303 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv) | |
7304 | { | |
7305 | struct drm_device *dev = dev_priv->dev; | |
7306 | struct device *device = &dev->pdev->dev; | |
7307 | ||
8a187455 PZ |
7308 | if (!HAS_RUNTIME_PM(dev)) |
7309 | return; | |
7310 | ||
7311 | pm_runtime_set_active(device); | |
7312 | ||
aeab0b5a ID |
7313 | /* |
7314 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
7315 | * requirement. | |
7316 | */ | |
7317 | if (!intel_enable_rc6(dev)) { | |
7318 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
7319 | return; | |
7320 | } | |
7321 | ||
8a187455 PZ |
7322 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
7323 | pm_runtime_mark_last_busy(device); | |
7324 | pm_runtime_use_autosuspend(device); | |
ba0239e0 PZ |
7325 | |
7326 | pm_runtime_put_autosuspend(device); | |
8a187455 PZ |
7327 | } |
7328 | ||
7329 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) | |
7330 | { | |
7331 | struct drm_device *dev = dev_priv->dev; | |
7332 | struct device *device = &dev->pdev->dev; | |
7333 | ||
7334 | if (!HAS_RUNTIME_PM(dev)) | |
7335 | return; | |
7336 | ||
aeab0b5a ID |
7337 | if (!intel_enable_rc6(dev)) |
7338 | return; | |
7339 | ||
8a187455 PZ |
7340 | /* Make sure we're not suspended first. */ |
7341 | pm_runtime_get_sync(device); | |
7342 | pm_runtime_disable(device); | |
7343 | } | |
7344 | ||
1fa61106 ED |
7345 | /* Set up chip specific power management-related functions */ |
7346 | void intel_init_pm(struct drm_device *dev) | |
7347 | { | |
7348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7349 | ||
3a77c4c4 | 7350 | if (HAS_FBC(dev)) { |
40045465 | 7351 | if (INTEL_INFO(dev)->gen >= 7) { |
1fa61106 | 7352 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
40045465 VS |
7353 | dev_priv->display.enable_fbc = gen7_enable_fbc; |
7354 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
7355 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
7356 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
7357 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
1fa61106 ED |
7358 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
7359 | } else if (IS_GM45(dev)) { | |
7360 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
7361 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
7362 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
40045465 | 7363 | } else { |
1fa61106 ED |
7364 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
7365 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
7366 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
993495ae VS |
7367 | |
7368 | /* This value was pulled out of someone's hat */ | |
7369 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1fa61106 | 7370 | } |
1fa61106 ED |
7371 | } |
7372 | ||
c921aba8 DV |
7373 | /* For cxsr */ |
7374 | if (IS_PINEVIEW(dev)) | |
7375 | i915_pineview_get_mem_freq(dev); | |
7376 | else if (IS_GEN5(dev)) | |
7377 | i915_ironlake_get_mem_freq(dev); | |
7378 | ||
1fa61106 ED |
7379 | /* For FIFO watermark updates */ |
7380 | if (HAS_PCH_SPLIT(dev)) { | |
fa50ad61 | 7381 | ilk_setup_wm_latency(dev); |
53615a5e | 7382 | |
bd602544 VS |
7383 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
7384 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
7385 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
7386 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
7387 | dev_priv->display.update_wm = ilk_update_wm; | |
7388 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
7389 | } else { | |
7390 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
7391 | "Disable CxSR\n"); | |
7392 | } | |
7393 | ||
7394 | if (IS_GEN5(dev)) | |
1fa61106 | 7395 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 7396 | else if (IS_GEN6(dev)) |
1fa61106 | 7397 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 7398 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 7399 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 7400 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 7401 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 7402 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 7403 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
da2078cd DL |
7404 | else if (INTEL_INFO(dev)->gen == 9) |
7405 | dev_priv->display.init_clock_gating = gen9_init_clock_gating; | |
a4565da8 | 7406 | } else if (IS_CHERRYVIEW(dev)) { |
3c2777fd | 7407 | dev_priv->display.update_wm = cherryview_update_wm; |
01e184cc | 7408 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
a4565da8 VS |
7409 | dev_priv->display.init_clock_gating = |
7410 | cherryview_init_clock_gating; | |
1fa61106 ED |
7411 | } else if (IS_VALLEYVIEW(dev)) { |
7412 | dev_priv->display.update_wm = valleyview_update_wm; | |
01e184cc | 7413 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
1fa61106 ED |
7414 | dev_priv->display.init_clock_gating = |
7415 | valleyview_init_clock_gating; | |
1fa61106 ED |
7416 | } else if (IS_PINEVIEW(dev)) { |
7417 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
7418 | dev_priv->is_ddr3, | |
7419 | dev_priv->fsb_freq, | |
7420 | dev_priv->mem_freq)) { | |
7421 | DRM_INFO("failed to find known CxSR latency " | |
7422 | "(found ddr%s fsb freq %d, mem freq %d), " | |
7423 | "disabling CxSR\n", | |
7424 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
7425 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
7426 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 7427 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
7428 | dev_priv->display.update_wm = NULL; |
7429 | } else | |
7430 | dev_priv->display.update_wm = pineview_update_wm; | |
7431 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
7432 | } else if (IS_G4X(dev)) { | |
7433 | dev_priv->display.update_wm = g4x_update_wm; | |
7434 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
7435 | } else if (IS_GEN4(dev)) { | |
7436 | dev_priv->display.update_wm = i965_update_wm; | |
7437 | if (IS_CRESTLINE(dev)) | |
7438 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
7439 | else if (IS_BROADWATER(dev)) | |
7440 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
7441 | } else if (IS_GEN3(dev)) { | |
7442 | dev_priv->display.update_wm = i9xx_update_wm; | |
7443 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
7444 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
7445 | } else if (IS_GEN2(dev)) { |
7446 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
7447 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 7448 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
7449 | } else { |
7450 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 7451 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
7452 | } |
7453 | ||
7454 | if (IS_I85X(dev) || IS_I865G(dev)) | |
7455 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
7456 | else | |
7457 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
7458 | } else { | |
7459 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
7460 | } |
7461 | } | |
7462 | ||
42c0526c BW |
7463 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
7464 | { | |
4fc688ce | 7465 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7466 | |
7467 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7468 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
7469 | return -EAGAIN; | |
7470 | } | |
7471 | ||
7472 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
7473 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
7474 | ||
7475 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7476 | 500)) { | |
7477 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
7478 | return -ETIMEDOUT; | |
7479 | } | |
7480 | ||
7481 | *val = I915_READ(GEN6_PCODE_DATA); | |
7482 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7483 | ||
7484 | return 0; | |
7485 | } | |
7486 | ||
7487 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) | |
7488 | { | |
4fc688ce | 7489 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7490 | |
7491 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7492 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
7493 | return -EAGAIN; | |
7494 | } | |
7495 | ||
7496 | I915_WRITE(GEN6_PCODE_DATA, val); | |
7497 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
7498 | ||
7499 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7500 | 500)) { | |
7501 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
7502 | return -ETIMEDOUT; | |
7503 | } | |
7504 | ||
7505 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7506 | ||
7507 | return 0; | |
7508 | } | |
a0e4e199 | 7509 | |
b55dd647 | 7510 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7511 | { |
07ab118b | 7512 | int div; |
855ba3be | 7513 | |
07ab118b | 7514 | /* 4 x czclk */ |
2ec3815f | 7515 | switch (dev_priv->mem_freq) { |
855ba3be | 7516 | case 800: |
07ab118b | 7517 | div = 10; |
855ba3be JB |
7518 | break; |
7519 | case 1066: | |
07ab118b | 7520 | div = 12; |
855ba3be JB |
7521 | break; |
7522 | case 1333: | |
07ab118b | 7523 | div = 16; |
855ba3be JB |
7524 | break; |
7525 | default: | |
7526 | return -1; | |
7527 | } | |
7528 | ||
2ec3815f | 7529 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
855ba3be JB |
7530 | } |
7531 | ||
b55dd647 | 7532 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7533 | { |
07ab118b | 7534 | int mul; |
855ba3be | 7535 | |
07ab118b | 7536 | /* 4 x czclk */ |
2ec3815f | 7537 | switch (dev_priv->mem_freq) { |
855ba3be | 7538 | case 800: |
07ab118b | 7539 | mul = 10; |
855ba3be JB |
7540 | break; |
7541 | case 1066: | |
07ab118b | 7542 | mul = 12; |
855ba3be JB |
7543 | break; |
7544 | case 1333: | |
07ab118b | 7545 | mul = 16; |
855ba3be JB |
7546 | break; |
7547 | default: | |
7548 | return -1; | |
7549 | } | |
7550 | ||
2ec3815f | 7551 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
855ba3be JB |
7552 | } |
7553 | ||
b55dd647 | 7554 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 D |
7555 | { |
7556 | int div, freq; | |
7557 | ||
7558 | switch (dev_priv->rps.cz_freq) { | |
7559 | case 200: | |
7560 | div = 5; | |
7561 | break; | |
7562 | case 267: | |
7563 | div = 6; | |
7564 | break; | |
7565 | case 320: | |
7566 | case 333: | |
7567 | case 400: | |
7568 | div = 8; | |
7569 | break; | |
7570 | default: | |
7571 | return -1; | |
7572 | } | |
7573 | ||
7574 | freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); | |
7575 | ||
7576 | return freq; | |
7577 | } | |
7578 | ||
b55dd647 | 7579 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 D |
7580 | { |
7581 | int mul, opcode; | |
7582 | ||
7583 | switch (dev_priv->rps.cz_freq) { | |
7584 | case 200: | |
7585 | mul = 5; | |
7586 | break; | |
7587 | case 267: | |
7588 | mul = 6; | |
7589 | break; | |
7590 | case 320: | |
7591 | case 333: | |
7592 | case 400: | |
7593 | mul = 8; | |
7594 | break; | |
7595 | default: | |
7596 | return -1; | |
7597 | } | |
7598 | ||
1c14762d | 7599 | /* CHV needs even values */ |
22b1b2f8 D |
7600 | opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); |
7601 | ||
7602 | return opcode; | |
7603 | } | |
7604 | ||
7605 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
7606 | { | |
7607 | int ret = -1; | |
7608 | ||
7609 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
7610 | ret = chv_gpu_freq(dev_priv, val); | |
7611 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
7612 | ret = byt_gpu_freq(dev_priv, val); | |
7613 | ||
7614 | return ret; | |
7615 | } | |
7616 | ||
7617 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
7618 | { | |
7619 | int ret = -1; | |
7620 | ||
7621 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
7622 | ret = chv_freq_opcode(dev_priv, val); | |
7623 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
7624 | ret = byt_freq_opcode(dev_priv, val); | |
7625 | ||
7626 | return ret; | |
7627 | } | |
7628 | ||
f742a552 | 7629 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
7630 | { |
7631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7632 | ||
f742a552 DV |
7633 | mutex_init(&dev_priv->rps.hw_lock); |
7634 | ||
907b28c5 CW |
7635 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7636 | intel_gen6_powersave_work); | |
5d584b2e | 7637 | |
33688d95 | 7638 | dev_priv->pm.suspended = false; |
9df7575f | 7639 | dev_priv->pm._irqs_disabled = false; |
907b28c5 | 7640 | } |