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drm/i915: fix panel unlock register mask
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 96 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0
ED		 97 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
98 int cfb_pitch;
7f2cf220 99 int i;
159f9875 100 u32 fbc_ctl;
85208be0 101
5c3fe8b0 102 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 103 if (fb->pitches[0] < cfb_pitch)
104 cfb_pitch = fb->pitches[0];
105
42a430f5
VS		 106 /* FBC_CTL wants 32B or 64B units */
107 if (IS_GEN2(dev))
108 cfb_pitch = (cfb_pitch / 32) - 1;
109 else
110 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 111
112 /* Clear old tags */
113 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
114 I915_WRITE(FBC_TAG + (i * 4), 0);
115
159f9875
VS		 116 if (IS_GEN4(dev)) {
117 u32 fbc_ctl2;
118
119 /* Set it up... */
120 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 121 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 122 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
123 I915_WRITE(FBC_FENCE_OFF, crtc->y);
124 }
85208be0
ED		 125
126 /* enable it... */
993495ae
VS		 127 fbc_ctl = I915_READ(FBC_CONTROL);
128 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
129 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 130 if (IS_I945GM(dev))
131 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
132 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 133 fbc_ctl |= obj->fence_reg;
134 I915_WRITE(FBC_CONTROL, fbc_ctl);
135
5cd5410e 136 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 137 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 138}
139
1fa61106 140static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
145}
146
993495ae 147static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 148{
149 struct drm_device *dev = crtc->dev;
150 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 151 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 152 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 154 u32 dpfc_ctl;
155
3fa2e0ee
VS		 156 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
157 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
158 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
159 else
160 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 162
85208be0
ED		 163 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
164
165 /* enable it... */
fe74c1a5 166 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 167
84f44ce7 168 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 169}
170
1fa61106 171static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 172{
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 u32 dpfc_ctl;
175
176 /* Disable compression */
177 dpfc_ctl = I915_READ(DPFC_CONTROL);
178 if (dpfc_ctl & DPFC_CTL_EN) {
179 dpfc_ctl &= ~DPFC_CTL_EN;
180 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
181
182 DRM_DEBUG_KMS("disabled FBC\n");
183 }
184}
185
1fa61106 186static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 187{
188 struct drm_i915_private *dev_priv = dev->dev_private;
189
190 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
191}
192
193static void sandybridge_blit_fbc_update(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 u32 blt_ecoskpd;
197
198 /* Make sure blitter notifies FBC of writes */
940aece4
D		 199
200 /* Blitter is part of Media powerwell on VLV. No impact of
201 * his param in other platforms for now */
202 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 203
85208be0
ED		 204 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
206 GEN6_BLITTER_LOCK_SHIFT;
207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
208 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
211 GEN6_BLITTER_LOCK_SHIFT);
212 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
213 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 214
940aece4 215 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 216}
217
993495ae 218static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 219{
220 struct drm_device *dev = crtc->dev;
221 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 222 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 223 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
85208be0 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 225 u32 dpfc_ctl;
226
46f3dab9 227 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee 228 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 229 dev_priv->fbc.threshold++;
230
231 switch (dev_priv->fbc.threshold) {
232 case 4:
233 case 3:
234 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
235 break;
236 case 2:
3fa2e0ee 237 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 238 break;
239 case 1:
3fa2e0ee 240 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 241 break;
242 }
d629336b
VS		 243 dpfc_ctl |= DPFC_CTL_FENCE_EN;
244 if (IS_GEN5(dev))
245 dpfc_ctl |= obj->fence_reg;
85208be0 246
85208be0 247 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 248 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 249 /* enable it... */
250 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
251
252 if (IS_GEN6(dev)) {
253 I915_WRITE(SNB_DPFC_CTL_SA,
254 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
255 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
256 sandybridge_blit_fbc_update(dev);
257 }
258
84f44ce7 259 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 260}
261
1fa61106 262static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 u32 dpfc_ctl;
266
267 /* Disable compression */
268 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
269 if (dpfc_ctl & DPFC_CTL_EN) {
270 dpfc_ctl &= ~DPFC_CTL_EN;
271 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
272
273 DRM_DEBUG_KMS("disabled FBC\n");
274 }
275}
276
1fa61106 277static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280
281 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
282}
283
993495ae 284static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 285{
286 struct drm_device *dev = crtc->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 288 struct drm_framebuffer *fb = crtc->primary->fb;
2ff8fde1 289 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
abe959c7 290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 291 u32 dpfc_ctl;
abe959c7 292
3fa2e0ee
VS		 293 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
294 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
5e59f717
BW		 295 dev_priv->fbc.threshold++;
296
297 switch (dev_priv->fbc.threshold) {
298 case 4:
299 case 3:
300 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
301 break;
302 case 2:
3fa2e0ee 303 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
5e59f717
BW		 304 break;
305 case 1:
3fa2e0ee 306 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
5e59f717
BW		 307 break;
308 }
309
3fa2e0ee
VS		 310 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
311
da46f936
RV		 312 if (dev_priv->fbc.false_color)
313 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
314
3fa2e0ee 315 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 316
891348b2 317 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 318 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 319 I915_WRITE(ILK_DISPLAY_CHICKEN1,
320 I915_READ(ILK_DISPLAY_CHICKEN1) |
321 ILK_FBCQ_DIS);
28554164 322 } else {
2adb6db8 323 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 324 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
325 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
326 HSW_FBCQ_DIS);
891348b2 327 }
b74ea102 328
abe959c7
RV		 329 I915_WRITE(SNB_DPFC_CTL_SA,
330 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
331 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
332
333 sandybridge_blit_fbc_update(dev);
334
b19870ee 335 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 336}
337
85208be0
ED		 338bool intel_fbc_enabled(struct drm_device *dev)
339{
340 struct drm_i915_private *dev_priv = dev->dev_private;
341
342 if (!dev_priv->display.fbc_enabled)
343 return false;
344
345 return dev_priv->display.fbc_enabled(dev);
346}
347
348static void intel_fbc_work_fn(struct work_struct *__work)
349{
350 struct intel_fbc_work *work =
351 container_of(to_delayed_work(__work),
352 struct intel_fbc_work, work);
353 struct drm_device *dev = work->crtc->dev;
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 mutex_lock(&dev->struct_mutex);
5c3fe8b0 357 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 358 /* Double check that we haven't switched fb without cancelling
359 * the prior work.
360 */
f4510a27 361 if (work->crtc->primary->fb == work->fb) {
993495ae 362 dev_priv->display.enable_fbc(work->crtc);
85208be0 363
5c3fe8b0 364 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 365 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 366 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 367 }
368
5c3fe8b0 369 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 370 }
371 mutex_unlock(&dev->struct_mutex);
372
373 kfree(work);
374}
375
376static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
377{
5c3fe8b0 378 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 379 return;
380
381 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
382
383 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 384 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 385 * entirely asynchronously.
386 */
5c3fe8b0 387 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 388 /* tasklet was killed before being run, clean up */
5c3fe8b0 389 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 390
391 /* Mark the work as no longer wanted so that if it does
392 * wake-up (because the work was already running and waiting
393 * for our mutex), it will discover that is no longer
394 * necessary to run.
395 */
5c3fe8b0 396 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 397}
398
993495ae 399static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 400{
401 struct intel_fbc_work *work;
402 struct drm_device *dev = crtc->dev;
403 struct drm_i915_private *dev_priv = dev->dev_private;
404
405 if (!dev_priv->display.enable_fbc)
406 return;
407
408 intel_cancel_fbc_work(dev_priv);
409
b14c5679 410 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 411 if (work == NULL) {
6cdcb5e7 412 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 413 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 414 return;
415 }
416
417 work->crtc = crtc;
f4510a27 418 work->fb = crtc->primary->fb;
85208be0
ED		 419 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
420
5c3fe8b0 421 dev_priv->fbc.fbc_work = work;
85208be0 422
85208be0
ED		 423 /* Delay the actual enabling to let pageflipping cease and the
424 * display to settle before starting the compression. Note that
425 * this delay also serves a second purpose: it allows for a
426 * vblank to pass after disabling the FBC before we attempt
427 * to modify the control registers.
428 *
429 * A more complicated solution would involve tracking vblanks
430 * following the termination of the page-flipping sequence
431 * and indeed performing the enable as a co-routine and not
432 * waiting synchronously upon the vblank.
7457d617
DL		 433 *
434 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 435 */
436 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
437}
438
439void intel_disable_fbc(struct drm_device *dev)
440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442
443 intel_cancel_fbc_work(dev_priv);
444
445 if (!dev_priv->display.disable_fbc)
446 return;
447
448 dev_priv->display.disable_fbc(dev);
5c3fe8b0 449 dev_priv->fbc.plane = -1;
85208be0
ED		 450}
451
29ebf90f
CW		 452static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
453 enum no_fbc_reason reason)
454{
455 if (dev_priv->fbc.no_fbc_reason == reason)
456 return false;
457
458 dev_priv->fbc.no_fbc_reason = reason;
459 return true;
460}
461
85208be0
ED		 462/**
463 * intel_update_fbc - enable/disable FBC as needed
464 * @dev: the drm_device
465 *
466 * Set up the framebuffer compression hardware at mode set time. We
467 * enable it if possible:
468 * - plane A only (on pre-965)
469 * - no pixel mulitply/line duplication
470 * - no alpha buffer discard
471 * - no dual wide
f85da868 472 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 473 *
474 * We can't assume that any compression will take place (worst case),
475 * so the compressed buffer has to be the same size as the uncompressed
476 * one. It also must reside (along with the line length buffer) in
477 * stolen memory.
478 *
479 * We need to enable/disable FBC on a global basis.
480 */
481void intel_update_fbc(struct drm_device *dev)
482{
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_crtc *crtc = NULL, *tmp_crtc;
485 struct intel_crtc *intel_crtc;
486 struct drm_framebuffer *fb;
85208be0 487 struct drm_i915_gem_object *obj;
ef644fda 488 const struct drm_display_mode *adjusted_mode;
37327abd 489 unsigned int max_width, max_height;
85208be0 490
3a77c4c4 491 if (!HAS_FBC(dev)) {
29ebf90f 492 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 493 return;
29ebf90f 494 }
85208be0 495
d330a953 496 if (!i915.powersave) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
498 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 499 return;
29ebf90f 500 }
85208be0
ED		 501
502 /*
503 * If FBC is already on, we just have to verify that we can
504 * keep it that way...
505 * Need to disable if:
506 * - more than one pipe is active
507 * - changing FBC params (stride, fence, mode)
508 * - new fb is too large to fit in compressed buffer
509 * - going to an unsupported config (interlace, pixel multiply, etc.)
510 */
70e1e0ec 511 for_each_crtc(dev, tmp_crtc) {
3490ea5d 512 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 513 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 514 if (crtc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
516 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 517 goto out_disable;
518 }
519 crtc = tmp_crtc;
520 }
521 }
522
f4510a27 523 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 524 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
525 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 526 goto out_disable;
527 }
528
529 intel_crtc = to_intel_crtc(crtc);
f4510a27 530 fb = crtc->primary->fb;
2ff8fde1 531 obj = intel_fb_obj(fb);
ef644fda 532 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 533
0368920e 534 if (i915.enable_fbc < 0) {
29ebf90f
CW		 535 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
536 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 537 goto out_disable;
85208be0 538 }
d330a953 539 if (!i915.enable_fbc) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
541 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 542 goto out_disable;
543 }
ef644fda
VS		 544 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
545 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 546 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
547 DRM_DEBUG_KMS("mode incompatible with compression, "
548 "disabling\n");
85208be0
ED		 549 goto out_disable;
550 }
f85da868 551
032843a5
DS		 552 if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) {
553 max_width = 4096;
554 max_height = 4096;
555 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 556 max_width = 4096;
557 max_height = 2048;
f85da868 558 } else {
37327abd
VS		 559 max_width = 2048;
560 max_height = 1536;
f85da868 561 }
37327abd
VS		 562 if (intel_crtc->config.pipe_src_w > max_width ||
563 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 564 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
565 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 566 goto out_disable;
567 }
8f94d24b 568 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 569 intel_crtc->plane != PLANE_A) {
29ebf90f 570 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 571 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 572 goto out_disable;
573 }
574
575 /* The use of a CPU fence is mandatory in order to detect writes
576 * by the CPU to the scanout and trigger updates to the FBC.
577 */
578 if (obj->tiling_mode != I915_TILING_X ||
579 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 580 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
581 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 582 goto out_disable;
583 }
48404c1e
SJ		 584 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
585 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) {
586 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
587 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
588 goto out_disable;
589 }
85208be0
ED		 590
591 /* If the kernel debugger is active, always disable compression */
592 if (in_dbg_master())
593 goto out_disable;
594
2ff8fde1 595 if (i915_gem_stolen_setup_compression(dev, obj->base.size,
5e59f717 596 drm_format_plane_cpp(fb->pixel_format, 0))) {
29ebf90f
CW		 597 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
598 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 599 goto out_disable;
600 }
601
85208be0
ED		 602 /* If the scanout has not changed, don't modify the FBC settings.
603 * Note that we make the fundamental assumption that the fb->obj
604 * cannot be unpinned (and have its GTT offset and fence revoked)
605 * without first being decoupled from the scanout and FBC disabled.
606 */
5c3fe8b0
BW		 607 if (dev_priv->fbc.plane == intel_crtc->plane &&
608 dev_priv->fbc.fb_id == fb->base.id &&
609 dev_priv->fbc.y == crtc->y)
85208be0
ED		 610 return;
611
612 if (intel_fbc_enabled(dev)) {
613 /* We update FBC along two paths, after changing fb/crtc
614 * configuration (modeswitching) and after page-flipping
615 * finishes. For the latter, we know that not only did
616 * we disable the FBC at the start of the page-flip
617 * sequence, but also more than one vblank has passed.
618 *
619 * For the former case of modeswitching, it is possible
620 * to switch between two FBC valid configurations
621 * instantaneously so we do need to disable the FBC
622 * before we can modify its control registers. We also
623 * have to wait for the next vblank for that to take
624 * effect. However, since we delay enabling FBC we can
625 * assume that a vblank has passed since disabling and
626 * that we can safely alter the registers in the deferred
627 * callback.
628 *
629 * In the scenario that we go from a valid to invalid
630 * and then back to valid FBC configuration we have
631 * no strict enforcement that a vblank occurred since
632 * disabling the FBC. However, along all current pipe
633 * disabling paths we do need to wait for a vblank at
634 * some point. And we wait before enabling FBC anyway.
635 */
636 DRM_DEBUG_KMS("disabling active FBC for update\n");
637 intel_disable_fbc(dev);
638 }
639
993495ae 640 intel_enable_fbc(crtc);
29ebf90f 641 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 642 return;
643
644out_disable:
645 /* Multiple disables should be harmless */
646 if (intel_fbc_enabled(dev)) {
647 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
648 intel_disable_fbc(dev);
649 }
11be49eb 650 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 651}
652
c921aba8
DV		 653static void i915_pineview_get_mem_freq(struct drm_device *dev)
654{
50227e1c 655 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 656 u32 tmp;
657
658 tmp = I915_READ(CLKCFG);
659
660 switch (tmp & CLKCFG_FSB_MASK) {
661 case CLKCFG_FSB_533:
662 dev_priv->fsb_freq = 533; /* 133*4 */
663 break;
664 case CLKCFG_FSB_800:
665 dev_priv->fsb_freq = 800; /* 200*4 */
666 break;
667 case CLKCFG_FSB_667:
668 dev_priv->fsb_freq = 667; /* 167*4 */
669 break;
670 case CLKCFG_FSB_400:
671 dev_priv->fsb_freq = 400; /* 100*4 */
672 break;
673 }
674
675 switch (tmp & CLKCFG_MEM_MASK) {
676 case CLKCFG_MEM_533:
677 dev_priv->mem_freq = 533;
678 break;
679 case CLKCFG_MEM_667:
680 dev_priv->mem_freq = 667;
681 break;
682 case CLKCFG_MEM_800:
683 dev_priv->mem_freq = 800;
684 break;
685 }
686
687 /* detect pineview DDR3 setting */
688 tmp = I915_READ(CSHRDDR3CTL);
689 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
690}
691
692static void i915_ironlake_get_mem_freq(struct drm_device *dev)
693{
50227e1c 694 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 695 u16 ddrpll, csipll;
696
697 ddrpll = I915_READ16(DDRMPLL1);
698 csipll = I915_READ16(CSIPLL0);
699
700 switch (ddrpll & 0xff) {
701 case 0xc:
702 dev_priv->mem_freq = 800;
703 break;
704 case 0x10:
705 dev_priv->mem_freq = 1066;
706 break;
707 case 0x14:
708 dev_priv->mem_freq = 1333;
709 break;
710 case 0x18:
711 dev_priv->mem_freq = 1600;
712 break;
713 default:
714 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
715 ddrpll & 0xff);
716 dev_priv->mem_freq = 0;
717 break;
718 }
719
20e4d407 720 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 721
722 switch (csipll & 0x3ff) {
723 case 0x00c:
724 dev_priv->fsb_freq = 3200;
725 break;
726 case 0x00e:
727 dev_priv->fsb_freq = 3733;
728 break;
729 case 0x010:
730 dev_priv->fsb_freq = 4266;
731 break;
732 case 0x012:
733 dev_priv->fsb_freq = 4800;
734 break;
735 case 0x014:
736 dev_priv->fsb_freq = 5333;
737 break;
738 case 0x016:
739 dev_priv->fsb_freq = 5866;
740 break;
741 case 0x018:
742 dev_priv->fsb_freq = 6400;
743 break;
744 default:
745 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
746 csipll & 0x3ff);
747 dev_priv->fsb_freq = 0;
748 break;
749 }
750
751 if (dev_priv->fsb_freq == 3200) {
20e4d407 752 dev_priv->ips.c_m = 0;
c921aba8 753 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 754 dev_priv->ips.c_m = 1;
c921aba8 755 } else {
20e4d407 756 dev_priv->ips.c_m = 2;
c921aba8
DV		 757 }
758}
759
b445e3b0
ED		 760static const struct cxsr_latency cxsr_latency_table[] = {
761 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
762 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
763 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
764 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
765 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
766
767 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
768 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
769 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
770 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
771 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
772
773 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
774 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
775 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
776 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
777 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
778
779 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
780 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
781 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
782 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
783 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
784
785 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
786 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
787 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
788 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
789 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
790
791 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
792 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
793 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
794 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
795 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
796};
797
63c62275 798static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 799 int is_ddr3,
800 int fsb,
801 int mem)
802{
803 const struct cxsr_latency *latency;
804 int i;
805
806 if (fsb == 0 || mem == 0)
807 return NULL;
808
809 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
810 latency = &cxsr_latency_table[i];
811 if (is_desktop == latency->is_desktop &&
812 is_ddr3 == latency->is_ddr3 &&
813 fsb == latency->fsb_freq && mem == latency->mem_freq)
814 return latency;
815 }
816
817 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
818
819 return NULL;
820}
821
5209b1f4 822void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 823{
5209b1f4
ID		 824 struct drm_device *dev = dev_priv->dev;
825 u32 val;
b445e3b0 826
5209b1f4
ID		 827 if (IS_VALLEYVIEW(dev)) {
828 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
829 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
830 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
831 } else if (IS_PINEVIEW(dev)) {
832 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
833 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
834 I915_WRITE(DSPFW3, val);
835 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
836 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
837 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
838 I915_WRITE(FW_BLC_SELF, val);
839 } else if (IS_I915GM(dev)) {
840 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
841 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
842 I915_WRITE(INSTPM, val);
843 } else {
844 return;
845 }
b445e3b0 846
5209b1f4
ID		 847 DRM_DEBUG_KMS("memory self-refresh is %s\n",
848 enable ? "enabled" : "disabled");
b445e3b0
ED		 849}
850
851/*
852 * Latency for FIFO fetches is dependent on several factors:
853 * - memory configuration (speed, channels)
854 * - chipset
855 * - current MCH state
856 * It can be fairly high in some situations, so here we assume a fairly
857 * pessimal value. It's a tradeoff between extra memory fetches (if we
858 * set this value too high, the FIFO will fetch frequently to stay full)
859 * and power consumption (set it too low to save power and we might see
860 * FIFO underruns and display "flicker").
861 *
862 * A value of 5us seems to be a good balance; safe for very low end
863 * platforms but not overly aggressive on lower latency configs.
864 */
865static const int latency_ns = 5000;
866
1fa61106 867static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 868{
869 struct drm_i915_private *dev_priv = dev->dev_private;
870 uint32_t dsparb = I915_READ(DSPARB);
871 int size;
872
873 size = dsparb & 0x7f;
874 if (plane)
875 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
876
877 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
878 plane ? "B" : "A", size);
879
880 return size;
881}
882
feb56b93 883static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 884{
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 uint32_t dsparb = I915_READ(DSPARB);
887 int size;
888
889 size = dsparb & 0x1ff;
890 if (plane)
891 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
892 size >>= 1; /* Convert to cachelines */
893
894 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
895 plane ? "B" : "A", size);
896
897 return size;
898}
899
1fa61106 900static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 901{
902 struct drm_i915_private *dev_priv = dev->dev_private;
903 uint32_t dsparb = I915_READ(DSPARB);
904 int size;
905
906 size = dsparb & 0x7f;
907 size >>= 2; /* Convert to cachelines */
908
909 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
910 plane ? "B" : "A",
911 size);
912
913 return size;
914}
915
b445e3b0
ED		 916/* Pineview has different values for various configs */
917static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 918 .fifo_size = PINEVIEW_DISPLAY_FIFO,
919 .max_wm = PINEVIEW_MAX_WM,
920 .default_wm = PINEVIEW_DFT_WM,
921 .guard_size = PINEVIEW_GUARD_WM,
922 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 923};
924static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 925 .fifo_size = PINEVIEW_DISPLAY_FIFO,
926 .max_wm = PINEVIEW_MAX_WM,
927 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
928 .guard_size = PINEVIEW_GUARD_WM,
929 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 930};
931static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 932 .fifo_size = PINEVIEW_CURSOR_FIFO,
933 .max_wm = PINEVIEW_CURSOR_MAX_WM,
934 .default_wm = PINEVIEW_CURSOR_DFT_WM,
935 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
936 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 937};
938static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 939 .fifo_size = PINEVIEW_CURSOR_FIFO,
940 .max_wm = PINEVIEW_CURSOR_MAX_WM,
941 .default_wm = PINEVIEW_CURSOR_DFT_WM,
942 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
943 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 944};
945static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 946 .fifo_size = G4X_FIFO_SIZE,
947 .max_wm = G4X_MAX_WM,
948 .default_wm = G4X_MAX_WM,
949 .guard_size = 2,
950 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 951};
952static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 953 .fifo_size = I965_CURSOR_FIFO,
954 .max_wm = I965_CURSOR_MAX_WM,
955 .default_wm = I965_CURSOR_DFT_WM,
956 .guard_size = 2,
957 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 958};
959static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 960 .fifo_size = VALLEYVIEW_FIFO_SIZE,
961 .max_wm = VALLEYVIEW_MAX_WM,
962 .default_wm = VALLEYVIEW_MAX_WM,
963 .guard_size = 2,
964 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 965};
966static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 967 .fifo_size = I965_CURSOR_FIFO,
968 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
969 .default_wm = I965_CURSOR_DFT_WM,
970 .guard_size = 2,
971 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 972};
973static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 974 .fifo_size = I965_CURSOR_FIFO,
975 .max_wm = I965_CURSOR_MAX_WM,
976 .default_wm = I965_CURSOR_DFT_WM,
977 .guard_size = 2,
978 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 979};
980static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 981 .fifo_size = I945_FIFO_SIZE,
982 .max_wm = I915_MAX_WM,
983 .default_wm = 1,
984 .guard_size = 2,
985 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 986};
987static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 988 .fifo_size = I915_FIFO_SIZE,
989 .max_wm = I915_MAX_WM,
990 .default_wm = 1,
991 .guard_size = 2,
992 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 993};
feb56b93 994static const struct intel_watermark_params i830_wm_info = {
e0f0273e
VS		 995 .fifo_size = I855GM_FIFO_SIZE,
996 .max_wm = I915_MAX_WM,
997 .default_wm = 1,
998 .guard_size = 2,
999 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 1000};
feb56b93 1001static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 1002 .fifo_size = I830_FIFO_SIZE,
1003 .max_wm = I915_MAX_WM,
1004 .default_wm = 1,
1005 .guard_size = 2,
1006 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 1007};
1008
b445e3b0
ED		 1009/**
1010 * intel_calculate_wm - calculate watermark level
1011 * @clock_in_khz: pixel clock
1012 * @wm: chip FIFO params
1013 * @pixel_size: display pixel size
1014 * @latency_ns: memory latency for the platform
1015 *
1016 * Calculate the watermark level (the level at which the display plane will
1017 * start fetching from memory again). Each chip has a different display
1018 * FIFO size and allocation, so the caller needs to figure that out and pass
1019 * in the correct intel_watermark_params structure.
1020 *
1021 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1022 * on the pixel size. When it reaches the watermark level, it'll start
1023 * fetching FIFO line sized based chunks from memory until the FIFO fills
1024 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1025 * will occur, and a display engine hang could result.
1026 */
1027static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1028 const struct intel_watermark_params *wm,
1029 int fifo_size,
1030 int pixel_size,
1031 unsigned long latency_ns)
1032{
1033 long entries_required, wm_size;
1034
1035 /*
1036 * Note: we need to make sure we don't overflow for various clock &
1037 * latency values.
1038 * clocks go from a few thousand to several hundred thousand.
1039 * latency is usually a few thousand
1040 */
1041 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1042 1000;
1043 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1044
1045 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1046
1047 wm_size = fifo_size - (entries_required + wm->guard_size);
1048
1049 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1050
1051 /* Don't promote wm_size to unsigned... */
1052 if (wm_size > (long)wm->max_wm)
1053 wm_size = wm->max_wm;
1054 if (wm_size <= 0)
1055 wm_size = wm->default_wm;
1056 return wm_size;
1057}
1058
1059static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1060{
1061 struct drm_crtc *crtc, *enabled = NULL;
1062
70e1e0ec 1063 for_each_crtc(dev, crtc) {
3490ea5d 1064 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1065 if (enabled)
1066 return NULL;
1067 enabled = crtc;
1068 }
1069 }
1070
1071 return enabled;
1072}
1073
46ba614c 1074static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1075{
46ba614c 1076 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 struct drm_crtc *crtc;
1079 const struct cxsr_latency *latency;
1080 u32 reg;
1081 unsigned long wm;
1082
1083 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1084 dev_priv->fsb_freq, dev_priv->mem_freq);
1085 if (!latency) {
1086 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 1087 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1088 return;
1089 }
1090
1091 crtc = single_enabled_crtc(dev);
1092 if (crtc) {
241bfc38 1093 const struct drm_display_mode *adjusted_mode;
f4510a27 1094 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1095 int clock;
1096
1097 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1098 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1099
1100 /* Display SR */
1101 wm = intel_calculate_wm(clock, &pineview_display_wm,
1102 pineview_display_wm.fifo_size,
1103 pixel_size, latency->display_sr);
1104 reg = I915_READ(DSPFW1);
1105 reg &= ~DSPFW_SR_MASK;
1106 reg |= wm << DSPFW_SR_SHIFT;
1107 I915_WRITE(DSPFW1, reg);
1108 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1109
1110 /* cursor SR */
1111 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->cursor_sr);
1114 reg = I915_READ(DSPFW3);
1115 reg &= ~DSPFW_CURSOR_SR_MASK;
1116 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1117 I915_WRITE(DSPFW3, reg);
1118
1119 /* Display HPLL off SR */
1120 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1121 pineview_display_hplloff_wm.fifo_size,
1122 pixel_size, latency->display_hpll_disable);
1123 reg = I915_READ(DSPFW3);
1124 reg &= ~DSPFW_HPLL_SR_MASK;
1125 reg |= wm & DSPFW_HPLL_SR_MASK;
1126 I915_WRITE(DSPFW3, reg);
1127
1128 /* cursor HPLL off SR */
1129 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1130 pineview_display_hplloff_wm.fifo_size,
1131 pixel_size, latency->cursor_hpll_disable);
1132 reg = I915_READ(DSPFW3);
1133 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1134 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1135 I915_WRITE(DSPFW3, reg);
1136 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1137
5209b1f4 1138 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 1139 } else {
5209b1f4 1140 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1141 }
1142}
1143
1144static bool g4x_compute_wm0(struct drm_device *dev,
1145 int plane,
1146 const struct intel_watermark_params *display,
1147 int display_latency_ns,
1148 const struct intel_watermark_params *cursor,
1149 int cursor_latency_ns,
1150 int *plane_wm,
1151 int *cursor_wm)
1152{
1153 struct drm_crtc *crtc;
4fe8590a 1154 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1155 int htotal, hdisplay, clock, pixel_size;
1156 int line_time_us, line_count;
1157 int entries, tlb_miss;
1158
1159 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1160 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1161 *cursor_wm = cursor->guard_size;
1162 *plane_wm = display->guard_size;
1163 return false;
1164 }
1165
4fe8590a 1166 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1167 clock = adjusted_mode->crtc_clock;
fec8cba3 1168 htotal = adjusted_mode->crtc_htotal;
37327abd 1169 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1170 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1171
1172 /* Use the small buffer method to calculate plane watermark */
1173 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1174 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1175 if (tlb_miss > 0)
1176 entries += tlb_miss;
1177 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1178 *plane_wm = entries + display->guard_size;
1179 if (*plane_wm > (int)display->max_wm)
1180 *plane_wm = display->max_wm;
1181
1182 /* Use the large buffer method to calculate cursor watermark */
922044c9 1183 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1184 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1185 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1186 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1187 if (tlb_miss > 0)
1188 entries += tlb_miss;
1189 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1190 *cursor_wm = entries + cursor->guard_size;
1191 if (*cursor_wm > (int)cursor->max_wm)
1192 *cursor_wm = (int)cursor->max_wm;
1193
1194 return true;
1195}
1196
1197/*
1198 * Check the wm result.
1199 *
1200 * If any calculated watermark values is larger than the maximum value that
1201 * can be programmed into the associated watermark register, that watermark
1202 * must be disabled.
1203 */
1204static bool g4x_check_srwm(struct drm_device *dev,
1205 int display_wm, int cursor_wm,
1206 const struct intel_watermark_params *display,
1207 const struct intel_watermark_params *cursor)
1208{
1209 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1210 display_wm, cursor_wm);
1211
1212 if (display_wm > display->max_wm) {
1213 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1214 display_wm, display->max_wm);
1215 return false;
1216 }
1217
1218 if (cursor_wm > cursor->max_wm) {
1219 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1220 cursor_wm, cursor->max_wm);
1221 return false;
1222 }
1223
1224 if (!(display_wm || cursor_wm)) {
1225 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1226 return false;
1227 }
1228
1229 return true;
1230}
1231
1232static bool g4x_compute_srwm(struct drm_device *dev,
1233 int plane,
1234 int latency_ns,
1235 const struct intel_watermark_params *display,
1236 const struct intel_watermark_params *cursor,
1237 int *display_wm, int *cursor_wm)
1238{
1239 struct drm_crtc *crtc;
4fe8590a 1240 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1241 int hdisplay, htotal, pixel_size, clock;
1242 unsigned long line_time_us;
1243 int line_count, line_size;
1244 int small, large;
1245 int entries;
1246
1247 if (!latency_ns) {
1248 *display_wm = *cursor_wm = 0;
1249 return false;
1250 }
1251
1252 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1253 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1254 clock = adjusted_mode->crtc_clock;
fec8cba3 1255 htotal = adjusted_mode->crtc_htotal;
37327abd 1256 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1257 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1258
922044c9 1259 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1260 line_count = (latency_ns / line_time_us + 1000) / 1000;
1261 line_size = hdisplay * pixel_size;
1262
1263 /* Use the minimum of the small and large buffer method for primary */
1264 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1265 large = line_count * line_size;
1266
1267 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1268 *display_wm = entries + display->guard_size;
1269
1270 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1271 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1272 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1273 *cursor_wm = entries + cursor->guard_size;
1274
1275 return g4x_check_srwm(dev,
1276 *display_wm, *cursor_wm,
1277 display, cursor);
1278}
1279
0948c265
GB		 1280static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
1281 int pixel_size,
1282 int *prec_mult,
1283 int *drain_latency)
b445e3b0 1284{
b445e3b0 1285 int entries;
0948c265 1286 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0 1287
0948c265 1288 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED		 1289 return false;
1290
0948c265
GB		 1291 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
1292 return false;
b445e3b0 1293
a398e9c7 1294 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
0948c265
GB		 1295 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
1296 DRAIN_LATENCY_PRECISION_32;
1297 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 1298
a398e9c7
GB		 1299 if (*drain_latency > DRAIN_LATENCY_MASK)
1300 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED		 1301
1302 return true;
1303}
1304
1305/*
1306 * Update drain latency registers of memory arbiter
1307 *
1308 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1309 * to be programmed. Each plane has a drain latency multiplier and a drain
1310 * latency value.
1311 */
1312
41aad816 1313static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 1314{
0948c265
GB		 1315 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1317 int pixel_size;
1318 int drain_latency;
1319 enum pipe pipe = intel_crtc->pipe;
1320 int plane_prec, prec_mult, plane_dl;
b445e3b0 1321
0948c265
GB		 1322 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 |
1323 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 |
1324 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
1325
1326 if (!intel_crtc_active(crtc)) {
1327 I915_WRITE(VLV_DDL(pipe), plane_dl);
1328 return;
1329 }
b445e3b0 1330
0948c265
GB		 1331 /* Primary plane Drain Latency */
1332 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1333 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1334 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1335 DDL_PLANE_PRECISION_64 :
1336 DDL_PLANE_PRECISION_32;
1337 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED		 1338 }
1339
0948c265
GB		 1340 /* Cursor Drain Latency
1341 * BPP is always 4 for cursor
1342 */
1343 pixel_size = 4;
b445e3b0 1344
0948c265
GB		 1345 /* Program cursor DL only if it is enabled */
1346 if (intel_crtc->cursor_base &&
1347 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
1348 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1349 DDL_CURSOR_PRECISION_64 :
1350 DDL_CURSOR_PRECISION_32;
1351 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 1352 }
0948c265
GB		 1353
1354 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED		 1355}
1356
1357#define single_plane_enabled(mask) is_power_of_2(mask)
1358
46ba614c 1359static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1360{
46ba614c 1361 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1362 static const int sr_latency_ns = 12000;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1365 int plane_sr, cursor_sr;
af6c4575 1366 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 1367 unsigned int enabled = 0;
9858425c 1368 bool cxsr_enabled;
b445e3b0 1369
41aad816 1370 vlv_update_drain_latency(crtc);
b445e3b0 1371
51cea1f4 1372 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1373 &valleyview_wm_info, latency_ns,
1374 &valleyview_cursor_wm_info, latency_ns,
1375 &planea_wm, &cursora_wm))
51cea1f4 1376 enabled |= 1 << PIPE_A;
b445e3b0 1377
51cea1f4 1378 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1379 &valleyview_wm_info, latency_ns,
1380 &valleyview_cursor_wm_info, latency_ns,
1381 &planeb_wm, &cursorb_wm))
51cea1f4 1382 enabled |= 1 << PIPE_B;
b445e3b0 1383
b445e3b0
ED		 1384 if (single_plane_enabled(enabled) &&
1385 g4x_compute_srwm(dev, ffs(enabled) - 1,
1386 sr_latency_ns,
1387 &valleyview_wm_info,
1388 &valleyview_cursor_wm_info,
af6c4575
CW		 1389 &plane_sr, &ignore_cursor_sr) &&
1390 g4x_compute_srwm(dev, ffs(enabled) - 1,
1391 2*sr_latency_ns,
1392 &valleyview_wm_info,
1393 &valleyview_cursor_wm_info,
52bd02d8 1394 &ignore_plane_sr, &cursor_sr)) {
9858425c 1395 cxsr_enabled = true;
52bd02d8 1396 } else {
9858425c 1397 cxsr_enabled = false;
5209b1f4 1398 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1399 plane_sr = cursor_sr = 0;
1400 }
b445e3b0 1401
a5043453
VS		 1402 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1403 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1404 planea_wm, cursora_wm,
1405 planeb_wm, cursorb_wm,
1406 plane_sr, cursor_sr);
1407
1408 I915_WRITE(DSPFW1,
1409 (plane_sr << DSPFW_SR_SHIFT) |
1410 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1411 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1412 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1413 I915_WRITE(DSPFW2,
8c919b28 1414 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1415 (cursora_wm << DSPFW_CURSORA_SHIFT));
1416 I915_WRITE(DSPFW3,
8c919b28
CW		 1417 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1418 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1419
1420 if (cxsr_enabled)
1421 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1422}
1423
3c2777fd
VS		 1424static void cherryview_update_wm(struct drm_crtc *crtc)
1425{
1426 struct drm_device *dev = crtc->dev;
1427 static const int sr_latency_ns = 12000;
1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 int planea_wm, planeb_wm, planec_wm;
1430 int cursora_wm, cursorb_wm, cursorc_wm;
1431 int plane_sr, cursor_sr;
1432 int ignore_plane_sr, ignore_cursor_sr;
1433 unsigned int enabled = 0;
1434 bool cxsr_enabled;
1435
1436 vlv_update_drain_latency(crtc);
1437
1438 if (g4x_compute_wm0(dev, PIPE_A,
1439 &valleyview_wm_info, latency_ns,
1440 &valleyview_cursor_wm_info, latency_ns,
1441 &planea_wm, &cursora_wm))
1442 enabled |= 1 << PIPE_A;
1443
1444 if (g4x_compute_wm0(dev, PIPE_B,
1445 &valleyview_wm_info, latency_ns,
1446 &valleyview_cursor_wm_info, latency_ns,
1447 &planeb_wm, &cursorb_wm))
1448 enabled |= 1 << PIPE_B;
1449
1450 if (g4x_compute_wm0(dev, PIPE_C,
1451 &valleyview_wm_info, latency_ns,
1452 &valleyview_cursor_wm_info, latency_ns,
1453 &planec_wm, &cursorc_wm))
1454 enabled |= 1 << PIPE_C;
1455
1456 if (single_plane_enabled(enabled) &&
1457 g4x_compute_srwm(dev, ffs(enabled) - 1,
1458 sr_latency_ns,
1459 &valleyview_wm_info,
1460 &valleyview_cursor_wm_info,
1461 &plane_sr, &ignore_cursor_sr) &&
1462 g4x_compute_srwm(dev, ffs(enabled) - 1,
1463 2*sr_latency_ns,
1464 &valleyview_wm_info,
1465 &valleyview_cursor_wm_info,
1466 &ignore_plane_sr, &cursor_sr)) {
1467 cxsr_enabled = true;
1468 } else {
1469 cxsr_enabled = false;
1470 intel_set_memory_cxsr(dev_priv, false);
1471 plane_sr = cursor_sr = 0;
1472 }
1473
1474 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1475 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
1476 "SR: plane=%d, cursor=%d\n",
1477 planea_wm, cursora_wm,
1478 planeb_wm, cursorb_wm,
1479 planec_wm, cursorc_wm,
1480 plane_sr, cursor_sr);
1481
1482 I915_WRITE(DSPFW1,
1483 (plane_sr << DSPFW_SR_SHIFT) |
1484 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1485 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1486 (planea_wm << DSPFW_PLANEA_SHIFT));
1487 I915_WRITE(DSPFW2,
1488 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1489 (cursora_wm << DSPFW_CURSORA_SHIFT));
1490 I915_WRITE(DSPFW3,
1491 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1492 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1493 I915_WRITE(DSPFW9_CHV,
1494 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
1495 DSPFW_CURSORC_MASK)) |
1496 (planec_wm << DSPFW_PLANEC_SHIFT) |
1497 (cursorc_wm << DSPFW_CURSORC_SHIFT));
1498
1499 if (cxsr_enabled)
1500 intel_set_memory_cxsr(dev_priv, true);
1501}
1502
01e184cc
GB		 1503static void valleyview_update_sprite_wm(struct drm_plane *plane,
1504 struct drm_crtc *crtc,
1505 uint32_t sprite_width,
1506 uint32_t sprite_height,
1507 int pixel_size,
1508 bool enabled, bool scaled)
1509{
1510 struct drm_device *dev = crtc->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int pipe = to_intel_plane(plane)->pipe;
1513 int sprite = to_intel_plane(plane)->plane;
1514 int drain_latency;
1515 int plane_prec;
1516 int sprite_dl;
1517 int prec_mult;
1518
1519 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) |
1520 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
1521
1522 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
1523 &drain_latency)) {
1524 plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ?
1525 DDL_SPRITE_PRECISION_64(sprite) :
1526 DDL_SPRITE_PRECISION_32(sprite);
1527 sprite_dl |= plane_prec |
1528 (drain_latency << DDL_SPRITE_SHIFT(sprite));
1529 }
1530
1531 I915_WRITE(VLV_DDL(pipe), sprite_dl);
1532}
1533
46ba614c 1534static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1535{
46ba614c 1536 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1537 static const int sr_latency_ns = 12000;
1538 struct drm_i915_private *dev_priv = dev->dev_private;
1539 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1540 int plane_sr, cursor_sr;
1541 unsigned int enabled = 0;
9858425c 1542 bool cxsr_enabled;
b445e3b0 1543
51cea1f4 1544 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1545 &g4x_wm_info, latency_ns,
1546 &g4x_cursor_wm_info, latency_ns,
1547 &planea_wm, &cursora_wm))
51cea1f4 1548 enabled |= 1 << PIPE_A;
b445e3b0 1549
51cea1f4 1550 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1551 &g4x_wm_info, latency_ns,
1552 &g4x_cursor_wm_info, latency_ns,
1553 &planeb_wm, &cursorb_wm))
51cea1f4 1554 enabled |= 1 << PIPE_B;
b445e3b0 1555
b445e3b0
ED		 1556 if (single_plane_enabled(enabled) &&
1557 g4x_compute_srwm(dev, ffs(enabled) - 1,
1558 sr_latency_ns,
1559 &g4x_wm_info,
1560 &g4x_cursor_wm_info,
52bd02d8 1561 &plane_sr, &cursor_sr)) {
9858425c 1562 cxsr_enabled = true;
52bd02d8 1563 } else {
9858425c 1564 cxsr_enabled = false;
5209b1f4 1565 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1566 plane_sr = cursor_sr = 0;
1567 }
b445e3b0 1568
a5043453
VS		 1569 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1570 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1571 planea_wm, cursora_wm,
1572 planeb_wm, cursorb_wm,
1573 plane_sr, cursor_sr);
1574
1575 I915_WRITE(DSPFW1,
1576 (plane_sr << DSPFW_SR_SHIFT) |
1577 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1578 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1579 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1580 I915_WRITE(DSPFW2,
8c919b28 1581 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1582 (cursora_wm << DSPFW_CURSORA_SHIFT));
1583 /* HPLL off in SR has some issues on G4x... disable it */
1584 I915_WRITE(DSPFW3,
8c919b28 1585 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1586 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1587
1588 if (cxsr_enabled)
1589 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1590}
1591
46ba614c 1592static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1593{
46ba614c 1594 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596 struct drm_crtc *crtc;
1597 int srwm = 1;
1598 int cursor_sr = 16;
9858425c 1599 bool cxsr_enabled;
b445e3b0
ED		 1600
1601 /* Calc sr entries for one plane configs */
1602 crtc = single_enabled_crtc(dev);
1603 if (crtc) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1606 const struct drm_display_mode *adjusted_mode =
1607 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1608 int clock = adjusted_mode->crtc_clock;
fec8cba3 1609 int htotal = adjusted_mode->crtc_htotal;
37327abd 1610 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1611 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1612 unsigned long line_time_us;
1613 int entries;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619 pixel_size * hdisplay;
1620 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1621 srwm = I965_FIFO_SIZE - entries;
1622 if (srwm < 0)
1623 srwm = 1;
1624 srwm &= 0x1ff;
1625 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1626 entries, srwm);
1627
1628 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1629 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1630 entries = DIV_ROUND_UP(entries,
1631 i965_cursor_wm_info.cacheline_size);
1632 cursor_sr = i965_cursor_wm_info.fifo_size -
1633 (entries + i965_cursor_wm_info.guard_size);
1634
1635 if (cursor_sr > i965_cursor_wm_info.max_wm)
1636 cursor_sr = i965_cursor_wm_info.max_wm;
1637
1638 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1639 "cursor %d\n", srwm, cursor_sr);
1640
9858425c 1641 cxsr_enabled = true;
b445e3b0 1642 } else {
9858425c 1643 cxsr_enabled = false;
b445e3b0 1644 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1645 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1646 }
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1649 srwm);
1650
1651 /* 965 has limitations... */
1652 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS		 1653 (8 << DSPFW_CURSORB_SHIFT) |
1654 (8 << DSPFW_PLANEB_SHIFT) |
1655 (8 << DSPFW_PLANEA_SHIFT));
1656 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1657 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED		 1658 /* update cursor SR watermark */
1659 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID		 1660
1661 if (cxsr_enabled)
1662 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1663}
1664
46ba614c 1665static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1666{
46ba614c 1667 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 const struct intel_watermark_params *wm_info;
1670 uint32_t fwater_lo;
1671 uint32_t fwater_hi;
1672 int cwm, srwm = 1;
1673 int fifo_size;
1674 int planea_wm, planeb_wm;
1675 struct drm_crtc *crtc, *enabled = NULL;
1676
1677 if (IS_I945GM(dev))
1678 wm_info = &i945_wm_info;
1679 else if (!IS_GEN2(dev))
1680 wm_info = &i915_wm_info;
1681 else
feb56b93 1682 wm_info = &i830_wm_info;
b445e3b0
ED		 1683
1684 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1685 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1686 if (intel_crtc_active(crtc)) {
241bfc38 1687 const struct drm_display_mode *adjusted_mode;
f4510a27 1688 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1689 if (IS_GEN2(dev))
1690 cpp = 4;
1691
241bfc38
DL		 1692 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1693 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1694 wm_info, fifo_size, cpp,
b445e3b0
ED		 1695 latency_ns);
1696 enabled = crtc;
1697 } else
1698 planea_wm = fifo_size - wm_info->guard_size;
1699
1700 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1701 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1702 if (intel_crtc_active(crtc)) {
241bfc38 1703 const struct drm_display_mode *adjusted_mode;
f4510a27 1704 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1705 if (IS_GEN2(dev))
1706 cpp = 4;
1707
241bfc38
DL		 1708 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1709 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1710 wm_info, fifo_size, cpp,
b445e3b0
ED		 1711 latency_ns);
1712 if (enabled == NULL)
1713 enabled = crtc;
1714 else
1715 enabled = NULL;
1716 } else
1717 planeb_wm = fifo_size - wm_info->guard_size;
1718
1719 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1720
2ab1bc9d 1721 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1722 struct drm_i915_gem_object *obj;
2ab1bc9d 1723
2ff8fde1 1724 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV		 1725
1726 /* self-refresh seems busted with untiled */
2ff8fde1 1727 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1728 enabled = NULL;
1729 }
1730
b445e3b0
ED		 1731 /*
1732 * Overlay gets an aggressive default since video jitter is bad.
1733 */
1734 cwm = 2;
1735
1736 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1737 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1738
1739 /* Calc sr entries for one plane configs */
1740 if (HAS_FW_BLC(dev) && enabled) {
1741 /* self-refresh has much higher latency */
1742 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1743 const struct drm_display_mode *adjusted_mode =
1744 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1745 int clock = adjusted_mode->crtc_clock;
fec8cba3 1746 int htotal = adjusted_mode->crtc_htotal;
f727b490 1747 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1748 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1749 unsigned long line_time_us;
1750 int entries;
1751
922044c9 1752 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1753
1754 /* Use ns/us then divide to preserve precision */
1755 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1756 pixel_size * hdisplay;
1757 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1758 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1759 srwm = wm_info->fifo_size - entries;
1760 if (srwm < 0)
1761 srwm = 1;
1762
1763 if (IS_I945G(dev) || IS_I945GM(dev))
1764 I915_WRITE(FW_BLC_SELF,
1765 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1766 else if (IS_I915GM(dev))
1767 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1768 }
1769
1770 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1771 planea_wm, planeb_wm, cwm, srwm);
1772
1773 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1774 fwater_hi = (cwm & 0x1f);
1775
1776 /* Set request length to 8 cachelines per fetch */
1777 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1778 fwater_hi = fwater_hi | (1 << 8);
1779
1780 I915_WRITE(FW_BLC, fwater_lo);
1781 I915_WRITE(FW_BLC2, fwater_hi);
1782
5209b1f4
ID		 1783 if (enabled)
1784 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1785}
1786
feb56b93 1787static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1788{
46ba614c 1789 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct drm_crtc *crtc;
241bfc38 1792 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1793 uint32_t fwater_lo;
1794 int planea_wm;
1795
1796 crtc = single_enabled_crtc(dev);
1797 if (crtc == NULL)
1798 return;
1799
241bfc38
DL		 1800 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1801 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1802 &i845_wm_info,
b445e3b0 1803 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1804 4, latency_ns);
b445e3b0
ED		 1805 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1806 fwater_lo |= (3<<8) | planea_wm;
1807
1808 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1809
1810 I915_WRITE(FW_BLC, fwater_lo);
1811}
1812
3658729a
VS		 1813static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1814 struct drm_crtc *crtc)
801bcfff
PZ		 1815{
1816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1817 uint32_t pixel_rate;
801bcfff 1818
241bfc38 1819 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1820
1821 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1822 * adjust the pixel_rate here. */
1823
fd4daa9c 1824 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1825 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1826 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1827
37327abd
VS		 1828 pipe_w = intel_crtc->config.pipe_src_w;
1829 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1830 pfit_w = (pfit_size >> 16) & 0xFFFF;
1831 pfit_h = pfit_size & 0xFFFF;
1832 if (pipe_w < pfit_w)
1833 pipe_w = pfit_w;
1834 if (pipe_h < pfit_h)
1835 pipe_h = pfit_h;
1836
1837 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1838 pfit_w * pfit_h);
1839 }
1840
1841 return pixel_rate;
1842}
1843
37126462 1844/* latency must be in 0.1us units. */
23297044 1845static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1846 uint32_t latency)
1847{
1848 uint64_t ret;
1849
3312ba65
VS		 1850 if (WARN(latency == 0, "Latency value missing\n"))
1851 return UINT_MAX;
1852
801bcfff
PZ		 1853 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1854 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1855
1856 return ret;
1857}
1858
37126462 1859/* latency must be in 0.1us units. */
23297044 1860static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1861 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1862 uint32_t latency)
1863{
1864 uint32_t ret;
1865
3312ba65
VS		 1866 if (WARN(latency == 0, "Latency value missing\n"))
1867 return UINT_MAX;
1868
801bcfff
PZ		 1869 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1870 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1871 ret = DIV_ROUND_UP(ret, 64) + 2;
1872 return ret;
1873}
1874
23297044 1875static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1876 uint8_t bytes_per_pixel)
1877{
1878 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1879}
1880
820c1980 1881struct ilk_pipe_wm_parameters {
801bcfff 1882 bool active;
801bcfff
PZ		 1883 uint32_t pipe_htotal;
1884 uint32_t pixel_rate;
c35426d2
VS		 1885 struct intel_plane_wm_parameters pri;
1886 struct intel_plane_wm_parameters spr;
1887 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1888};
1889
820c1980 1890struct ilk_wm_maximums {
cca32e9a
PZ		 1891 uint16_t pri;
1892 uint16_t spr;
1893 uint16_t cur;
1894 uint16_t fbc;
1895};
1896
240264f4
VS		 1897/* used in computing the new watermarks state */
1898struct intel_wm_config {
1899 unsigned int num_pipes_active;
1900 bool sprites_enabled;
1901 bool sprites_scaled;
240264f4
VS		 1902};
1903
37126462
VS		 1904/*
1905 * For both WM_PIPE and WM_LP.
1906 * mem_value must be in 0.1us units.
1907 */
820c1980 1908static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1909 uint32_t mem_value,
1910 bool is_lp)
801bcfff 1911{
cca32e9a
PZ		 1912 uint32_t method1, method2;
1913
c35426d2 1914 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1915 return 0;
1916
23297044 1917 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1918 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1919 mem_value);
1920
1921 if (!is_lp)
1922 return method1;
1923
23297044 1924 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1925 params->pipe_htotal,
c35426d2
VS		 1926 params->pri.horiz_pixels,
1927 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1928 mem_value);
1929
1930 return min(method1, method2);
801bcfff
PZ		 1931}
1932
37126462
VS		 1933/*
1934 * For both WM_PIPE and WM_LP.
1935 * mem_value must be in 0.1us units.
1936 */
820c1980 1937static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1938 uint32_t mem_value)
1939{
1940 uint32_t method1, method2;
1941
c35426d2 1942 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1943 return 0;
1944
23297044 1945 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1946 params->spr.bytes_per_pixel,
801bcfff 1947 mem_value);
23297044 1948 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1949 params->pipe_htotal,
c35426d2
VS		 1950 params->spr.horiz_pixels,
1951 params->spr.bytes_per_pixel,
801bcfff
PZ		 1952 mem_value);
1953 return min(method1, method2);
1954}
1955
37126462
VS		 1956/*
1957 * For both WM_PIPE and WM_LP.
1958 * mem_value must be in 0.1us units.
1959 */
820c1980 1960static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1961 uint32_t mem_value)
1962{
c35426d2 1963 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1964 return 0;
1965
23297044 1966 return ilk_wm_method2(params->pixel_rate,
801bcfff 1967 params->pipe_htotal,
c35426d2
VS		 1968 params->cur.horiz_pixels,
1969 params->cur.bytes_per_pixel,
801bcfff
PZ		 1970 mem_value);
1971}
1972
cca32e9a 1973/* Only for WM_LP. */
820c1980 1974static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1975 uint32_t pri_val)
cca32e9a 1976{
c35426d2 1977 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1978 return 0;
1979
23297044 1980 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1981 params->pri.horiz_pixels,
1982 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1983}
1984
158ae64f
VS		 1985static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1986{
416f4727
VS		 1987 if (INTEL_INFO(dev)->gen >= 8)
1988 return 3072;
1989 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1990 return 768;
1991 else
1992 return 512;
1993}
1994
4e975081
VS		 1995static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1996 int level, bool is_sprite)
1997{
1998 if (INTEL_INFO(dev)->gen >= 8)
1999 /* BDW primary/sprite plane watermarks */
2000 return level == 0 ? 255 : 2047;
2001 else if (INTEL_INFO(dev)->gen >= 7)
2002 /* IVB/HSW primary/sprite plane watermarks */
2003 return level == 0 ? 127 : 1023;
2004 else if (!is_sprite)
2005 /* ILK/SNB primary plane watermarks */
2006 return level == 0 ? 127 : 511;
2007 else
2008 /* ILK/SNB sprite plane watermarks */
2009 return level == 0 ? 63 : 255;
2010}
2011
2012static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
2013 int level)
2014{
2015 if (INTEL_INFO(dev)->gen >= 7)
2016 return level == 0 ? 63 : 255;
2017 else
2018 return level == 0 ? 31 : 63;
2019}
2020
2021static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
2022{
2023 if (INTEL_INFO(dev)->gen >= 8)
2024 return 31;
2025 else
2026 return 15;
2027}
2028
158ae64f
VS		 2029/* Calculate the maximum primary/sprite plane watermark */
2030static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2031 int level,
240264f4 2032 const struct intel_wm_config *config,
158ae64f
VS		 2033 enum intel_ddb_partitioning ddb_partitioning,
2034 bool is_sprite)
2035{
2036 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 2037
2038 /* if sprites aren't enabled, sprites get nothing */
240264f4 2039 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2040 return 0;
2041
2042 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2043 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2044 fifo_size /= INTEL_INFO(dev)->num_pipes;
2045
2046 /*
2047 * For some reason the non self refresh
2048 * FIFO size is only half of the self
2049 * refresh FIFO size on ILK/SNB.
2050 */
2051 if (INTEL_INFO(dev)->gen <= 6)
2052 fifo_size /= 2;
2053 }
2054
240264f4 2055 if (config->sprites_enabled) {
158ae64f
VS		 2056 /* level 0 is always calculated with 1:1 split */
2057 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2058 if (is_sprite)
2059 fifo_size *= 5;
2060 fifo_size /= 6;
2061 } else {
2062 fifo_size /= 2;
2063 }
2064 }
2065
2066 /* clamp to max that the registers can hold */
4e975081 2067 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 2068}
2069
2070/* Calculate the maximum cursor plane watermark */
2071static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2072 int level,
2073 const struct intel_wm_config *config)
158ae64f
VS		 2074{
2075 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2076 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2077 return 64;
2078
2079 /* otherwise just report max that registers can hold */
4e975081 2080 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 2081}
2082
d34ff9c6 2083static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 2084 int level,
2085 const struct intel_wm_config *config,
2086 enum intel_ddb_partitioning ddb_partitioning,
820c1980 2087 struct ilk_wm_maximums *max)
158ae64f 2088{
240264f4
VS		 2089 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2090 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2091 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2092 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2093}
2094
a3cb4048
VS		 2095static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2096 int level,
2097 struct ilk_wm_maximums *max)
2098{
2099 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2100 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2101 max->cur = ilk_cursor_wm_reg_max(dev, level);
2102 max->fbc = ilk_fbc_wm_reg_max(dev);
2103}
2104
d9395655 2105static bool ilk_validate_wm_level(int level,
820c1980 2106 const struct ilk_wm_maximums *max,
d9395655 2107 struct intel_wm_level *result)
a9786a11
VS		 2108{
2109 bool ret;
2110
2111 /* already determined to be invalid? */
2112 if (!result->enable)
2113 return false;
2114
2115 result->enable = result->pri_val <= max->pri &&
2116 result->spr_val <= max->spr &&
2117 result->cur_val <= max->cur;
2118
2119 ret = result->enable;
2120
2121 /*
2122 * HACK until we can pre-compute everything,
2123 * and thus fail gracefully if LP0 watermarks
2124 * are exceeded...
2125 */
2126 if (level == 0 && !result->enable) {
2127 if (result->pri_val > max->pri)
2128 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2129 level, result->pri_val, max->pri);
2130 if (result->spr_val > max->spr)
2131 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2132 level, result->spr_val, max->spr);
2133 if (result->cur_val > max->cur)
2134 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2135 level, result->cur_val, max->cur);
2136
2137 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2138 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2139 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2140 result->enable = true;
2141 }
2142
a9786a11
VS		 2143 return ret;
2144}
2145
d34ff9c6 2146static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2147 int level,
820c1980 2148 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2149 struct intel_wm_level *result)
6f5ddd17
VS		 2150{
2151 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2152 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2153 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2154
2155 /* WM1+ latency values stored in 0.5us units */
2156 if (level > 0) {
2157 pri_latency *= 5;
2158 spr_latency *= 5;
2159 cur_latency *= 5;
2160 }
2161
2162 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2163 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2164 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2165 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2166 result->enable = true;
2167}
2168
801bcfff
PZ		 2169static uint32_t
2170hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2171{
2172 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2174 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2175 u32 linetime, ips_linetime;
1f8eeabf 2176
801bcfff
PZ		 2177 if (!intel_crtc_active(crtc))
2178 return 0;
1011d8c4 2179
1f8eeabf
ED		 2180 /* The WM are computed with base on how long it takes to fill a single
2181 * row at the given clock rate, multiplied by 8.
2182 * */
fec8cba3
JB		 2183 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2184 mode->crtc_clock);
2185 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2186 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2187
801bcfff
PZ		 2188 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2189 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2190}
2191
12b134df
VS		 2192static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195
a42a5719 2196 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2197 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2198
2199 wm[0] = (sskpd >> 56) & 0xFF;
2200 if (wm[0] == 0)
2201 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2202 wm[1] = (sskpd >> 4) & 0xFF;
2203 wm[2] = (sskpd >> 12) & 0xFF;
2204 wm[3] = (sskpd >> 20) & 0x1FF;
2205 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2206 } else if (INTEL_INFO(dev)->gen >= 6) {
2207 uint32_t sskpd = I915_READ(MCH_SSKPD);
2208
2209 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2210 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2211 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2212 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2213 } else if (INTEL_INFO(dev)->gen >= 5) {
2214 uint32_t mltr = I915_READ(MLTR_ILK);
2215
2216 /* ILK primary LP0 latency is 700 ns */
2217 wm[0] = 7;
2218 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2219 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2220 }
2221}
2222
53615a5e
VS		 2223static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2224{
2225 /* ILK sprite LP0 latency is 1300 ns */
2226 if (INTEL_INFO(dev)->gen == 5)
2227 wm[0] = 13;
2228}
2229
2230static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2231{
2232 /* ILK cursor LP0 latency is 1300 ns */
2233 if (INTEL_INFO(dev)->gen == 5)
2234 wm[0] = 13;
2235
2236 /* WaDoubleCursorLP3Latency:ivb */
2237 if (IS_IVYBRIDGE(dev))
2238 wm[3] *= 2;
2239}
2240
546c81fd 2241int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2242{
26ec971e 2243 /* how many WM levels are we expecting */
a42a5719 2244 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2245 return 4;
26ec971e 2246 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2247 return 3;
26ec971e 2248 else
ad0d6dc4
VS		 2249 return 2;
2250}
2251
2252static void intel_print_wm_latency(struct drm_device *dev,
2253 const char *name,
2254 const uint16_t wm[5])
2255{
2256 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2257
2258 for (level = 0; level <= max_level; level++) {
2259 unsigned int latency = wm[level];
2260
2261 if (latency == 0) {
2262 DRM_ERROR("%s WM%d latency not provided\n",
2263 name, level);
2264 continue;
2265 }
2266
2267 /* WM1+ latency values in 0.5us units */
2268 if (level > 0)
2269 latency *= 5;
2270
2271 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2272 name, level, wm[level],
2273 latency / 10, latency % 10);
2274 }
2275}
2276
e95a2f75
VS		 2277static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2278 uint16_t wm[5], uint16_t min)
2279{
2280 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2281
2282 if (wm[0] >= min)
2283 return false;
2284
2285 wm[0] = max(wm[0], min);
2286 for (level = 1; level <= max_level; level++)
2287 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2288
2289 return true;
2290}
2291
2292static void snb_wm_latency_quirk(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 bool changed;
2296
2297 /*
2298 * The BIOS provided WM memory latency values are often
2299 * inadequate for high resolution displays. Adjust them.
2300 */
2301 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2302 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2303 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2304
2305 if (!changed)
2306 return;
2307
2308 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2309 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2310 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2311 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2312}
2313
fa50ad61 2314static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2315{
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317
2318 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2319
2320 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2321 sizeof(dev_priv->wm.pri_latency));
2322 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2323 sizeof(dev_priv->wm.pri_latency));
2324
2325 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2326 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2327
2328 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2329 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2330 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2331
2332 if (IS_GEN6(dev))
2333 snb_wm_latency_quirk(dev);
53615a5e
VS		 2334}
2335
820c1980 2336static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2337 struct ilk_pipe_wm_parameters *p)
1011d8c4 2338{
7c4a395f
VS		 2339 struct drm_device *dev = crtc->dev;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2341 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2342 struct drm_plane *plane;
1011d8c4 2343
2a44b76b
VS		 2344 if (!intel_crtc_active(crtc))
2345 return;
801bcfff 2346
2a44b76b
VS		 2347 p->active = true;
2348 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2349 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2350 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2351 p->cur.bytes_per_pixel = 4;
2352 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2353 p->cur.horiz_pixels = intel_crtc->cursor_width;
2354 /* TODO: for now, assume primary and cursor planes are always enabled. */
2355 p->pri.enabled = true;
2356 p->cur.enabled = true;
7c4a395f 2357
af2b653b 2358 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2359 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2360
2a44b76b 2361 if (intel_plane->pipe == pipe) {
7c4a395f 2362 p->spr = intel_plane->wm;
2a44b76b
VS		 2363 break;
2364 }
2365 }
2366}
2367
2368static void ilk_compute_wm_config(struct drm_device *dev,
2369 struct intel_wm_config *config)
2370{
2371 struct intel_crtc *intel_crtc;
2372
2373 /* Compute the currently _active_ config */
d3fcc808 2374 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2375 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2376
2a44b76b
VS		 2377 if (!wm->pipe_enabled)
2378 continue;
cca32e9a 2379
2a44b76b
VS		 2380 config->sprites_enabled |= wm->sprites_enabled;
2381 config->sprites_scaled |= wm->sprites_scaled;
2382 config->num_pipes_active++;
cca32e9a 2383 }
801bcfff
PZ		 2384}
2385
0b2ae6d7
VS		 2386/* Compute new watermarks for the pipe */
2387static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2388 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2389 struct intel_pipe_wm *pipe_wm)
2390{
2391 struct drm_device *dev = crtc->dev;
d34ff9c6 2392 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2393 int level, max_level = ilk_wm_max_level(dev);
2394 /* LP0 watermark maximums depend on this pipe alone */
2395 struct intel_wm_config config = {
2396 .num_pipes_active = 1,
2397 .sprites_enabled = params->spr.enabled,
2398 .sprites_scaled = params->spr.scaled,
2399 };
820c1980 2400 struct ilk_wm_maximums max;
0b2ae6d7 2401
2a44b76b
VS		 2402 pipe_wm->pipe_enabled = params->active;
2403 pipe_wm->sprites_enabled = params->spr.enabled;
2404 pipe_wm->sprites_scaled = params->spr.scaled;
2405
7b39a0b7
VS		 2406 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2407 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2408 max_level = 1;
2409
2410 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2411 if (params->spr.scaled)
2412 max_level = 0;
2413
a3cb4048 2414 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2415
a42a5719 2416 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2417 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2418
a3cb4048
VS		 2419 /* LP0 watermarks always use 1/2 DDB partitioning */
2420 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2421
0b2ae6d7 2422 /* At least LP0 must be valid */
a3cb4048
VS		 2423 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2424 return false;
2425
2426 ilk_compute_wm_reg_maximums(dev, 1, &max);
2427
2428 for (level = 1; level <= max_level; level++) {
2429 struct intel_wm_level wm = {};
2430
2431 ilk_compute_wm_level(dev_priv, level, params, &wm);
2432
2433 /*
2434 * Disable any watermark level that exceeds the
2435 * register maximums since such watermarks are
2436 * always invalid.
2437 */
2438 if (!ilk_validate_wm_level(level, &max, &wm))
2439 break;
2440
2441 pipe_wm->wm[level] = wm;
2442 }
2443
2444 return true;
0b2ae6d7
VS		 2445}
2446
2447/*
2448 * Merge the watermarks from all active pipes for a specific level.
2449 */
2450static void ilk_merge_wm_level(struct drm_device *dev,
2451 int level,
2452 struct intel_wm_level *ret_wm)
2453{
2454 const struct intel_crtc *intel_crtc;
2455
d52fea5b
VS		 2456 ret_wm->enable = true;
2457
d3fcc808 2458 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2459 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2460 const struct intel_wm_level *wm = &active->wm[level];
2461
2462 if (!active->pipe_enabled)
2463 continue;
0b2ae6d7 2464
d52fea5b
VS		 2465 /*
2466 * The watermark values may have been used in the past,
2467 * so we must maintain them in the registers for some
2468 * time even if the level is now disabled.
2469 */
0b2ae6d7 2470 if (!wm->enable)
d52fea5b 2471 ret_wm->enable = false;
0b2ae6d7
VS		 2472
2473 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2474 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2475 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2476 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2477 }
0b2ae6d7
VS		 2478}
2479
2480/*
2481 * Merge all low power watermarks for all active pipes.
2482 */
2483static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2484 const struct intel_wm_config *config,
820c1980 2485 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2486 struct intel_pipe_wm *merged)
2487{
2488 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2489 int last_enabled_level = max_level;
0b2ae6d7 2490
0ba22e26
VS		 2491 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2492 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2493 config->num_pipes_active > 1)
2494 return;
2495
6c8b6c28
VS		 2496 /* ILK: FBC WM must be disabled always */
2497 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2498
2499 /* merge each WM1+ level */
2500 for (level = 1; level <= max_level; level++) {
2501 struct intel_wm_level *wm = &merged->wm[level];
2502
2503 ilk_merge_wm_level(dev, level, wm);
2504
d52fea5b
VS		 2505 if (level > last_enabled_level)
2506 wm->enable = false;
2507 else if (!ilk_validate_wm_level(level, max, wm))
2508 /* make sure all following levels get disabled */
2509 last_enabled_level = level - 1;
0b2ae6d7
VS		 2510
2511 /*
2512 * The spec says it is preferred to disable
2513 * FBC WMs instead of disabling a WM level.
2514 */
2515 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2516 if (wm->enable)
2517 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2518 wm->fbc_val = 0;
2519 }
2520 }
6c8b6c28
VS		 2521
2522 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2523 /*
2524 * FIXME this is racy. FBC might get enabled later.
2525 * What we should check here is whether FBC can be
2526 * enabled sometime later.
2527 */
2528 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2529 for (level = 2; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 wm->enable = false;
2533 }
2534 }
0b2ae6d7
VS		 2535}
2536
b380ca3c
VS		 2537static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2538{
2539 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2540 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2541}
2542
a68d68ee
VS		 2543/* The value we need to program into the WM_LPx latency field */
2544static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2545{
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547
a42a5719 2548 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2549 return 2 * level;
2550 else
2551 return dev_priv->wm.pri_latency[level];
2552}
2553
820c1980 2554static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2555 const struct intel_pipe_wm *merged,
609cedef 2556 enum intel_ddb_partitioning partitioning,
820c1980 2557 struct ilk_wm_values *results)
801bcfff 2558{
0b2ae6d7
VS		 2559 struct intel_crtc *intel_crtc;
2560 int level, wm_lp;
cca32e9a 2561
0362c781 2562 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2563 results->partitioning = partitioning;
cca32e9a 2564
0b2ae6d7 2565 /* LP1+ register values */
cca32e9a 2566 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2567 const struct intel_wm_level *r;
801bcfff 2568
b380ca3c 2569 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2570
0362c781 2571 r = &merged->wm[level];
cca32e9a 2572
d52fea5b
VS		 2573 /*
2574 * Maintain the watermark values even if the level is
2575 * disabled. Doing otherwise could cause underruns.
2576 */
2577 results->wm_lp[wm_lp - 1] =
a68d68ee 2578 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2579 (r->pri_val << WM1_LP_SR_SHIFT) |
2580 r->cur_val;
2581
d52fea5b
VS		 2582 if (r->enable)
2583 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2584
416f4727
VS		 2585 if (INTEL_INFO(dev)->gen >= 8)
2586 results->wm_lp[wm_lp - 1] |=
2587 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2588 else
2589 results->wm_lp[wm_lp - 1] |=
2590 r->fbc_val << WM1_LP_FBC_SHIFT;
2591
d52fea5b
VS		 2592 /*
2593 * Always set WM1S_LP_EN when spr_val != 0, even if the
2594 * level is disabled. Doing otherwise could cause underruns.
2595 */
6cef2b8a
VS		 2596 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2597 WARN_ON(wm_lp != 1);
2598 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2599 } else
2600 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2601 }
801bcfff 2602
0b2ae6d7 2603 /* LP0 register values */
d3fcc808 2604 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2605 enum pipe pipe = intel_crtc->pipe;
2606 const struct intel_wm_level *r =
2607 &intel_crtc->wm.active.wm[0];
2608
2609 if (WARN_ON(!r->enable))
2610 continue;
2611
2612 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2613
0b2ae6d7
VS		 2614 results->wm_pipe[pipe] =
2615 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2616 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2617 r->cur_val;
801bcfff
PZ		 2618 }
2619}
2620
861f3389
PZ		 2621/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2622 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2623static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2624 struct intel_pipe_wm *r1,
2625 struct intel_pipe_wm *r2)
861f3389 2626{
198a1e9b
VS		 2627 int level, max_level = ilk_wm_max_level(dev);
2628 int level1 = 0, level2 = 0;
861f3389 2629
198a1e9b
VS		 2630 for (level = 1; level <= max_level; level++) {
2631 if (r1->wm[level].enable)
2632 level1 = level;
2633 if (r2->wm[level].enable)
2634 level2 = level;
861f3389
PZ		 2635 }
2636
198a1e9b
VS		 2637 if (level1 == level2) {
2638 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2639 return r2;
2640 else
2641 return r1;
198a1e9b 2642 } else if (level1 > level2) {
861f3389
PZ		 2643 return r1;
2644 } else {
2645 return r2;
2646 }
2647}
2648
49a687c4
VS		 2649/* dirty bits used to track which watermarks need changes */
2650#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2651#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2652#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2653#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2654#define WM_DIRTY_FBC (1 << 24)
2655#define WM_DIRTY_DDB (1 << 25)
2656
055e393f 2657static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2658 const struct ilk_wm_values *old,
2659 const struct ilk_wm_values *new)
49a687c4
VS		 2660{
2661 unsigned int dirty = 0;
2662 enum pipe pipe;
2663 int wm_lp;
2664
055e393f 2665 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2666 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2667 dirty |= WM_DIRTY_LINETIME(pipe);
2668 /* Must disable LP1+ watermarks too */
2669 dirty |= WM_DIRTY_LP_ALL;
2670 }
2671
2672 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2673 dirty |= WM_DIRTY_PIPE(pipe);
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677 }
2678
2679 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2680 dirty |= WM_DIRTY_FBC;
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684
2685 if (old->partitioning != new->partitioning) {
2686 dirty |= WM_DIRTY_DDB;
2687 /* Must disable LP1+ watermarks too */
2688 dirty |= WM_DIRTY_LP_ALL;
2689 }
2690
2691 /* LP1+ watermarks already deemed dirty, no need to continue */
2692 if (dirty & WM_DIRTY_LP_ALL)
2693 return dirty;
2694
2695 /* Find the lowest numbered LP1+ watermark in need of an update... */
2696 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2697 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2698 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2699 break;
2700 }
2701
2702 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2703 for (; wm_lp <= 3; wm_lp++)
2704 dirty |= WM_DIRTY_LP(wm_lp);
2705
2706 return dirty;
2707}
2708
8553c18e
VS		 2709static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2710 unsigned int dirty)
801bcfff 2711{
820c1980 2712 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2713 bool changed = false;
801bcfff 2714
facd619b
VS		 2715 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2716 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2718 changed = true;
facd619b
VS		 2719 }
2720 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2721 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2722 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2723 changed = true;
facd619b
VS		 2724 }
2725 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2726 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2727 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2728 changed = true;
facd619b 2729 }
801bcfff 2730
facd619b
VS		 2731 /*
2732 * Don't touch WM1S_LP_EN here.
2733 * Doing so could cause underruns.
2734 */
6cef2b8a 2735
8553c18e
VS		 2736 return changed;
2737}
2738
2739/*
2740 * The spec says we shouldn't write when we don't need, because every write
2741 * causes WMs to be re-evaluated, expending some power.
2742 */
820c1980
ID		 2743static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2744 struct ilk_wm_values *results)
8553c18e
VS		 2745{
2746 struct drm_device *dev = dev_priv->dev;
820c1980 2747 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2748 unsigned int dirty;
2749 uint32_t val;
2750
055e393f 2751 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2752 if (!dirty)
2753 return;
2754
2755 _ilk_disable_lp_wm(dev_priv, dirty);
2756
49a687c4 2757 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2758 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2759 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2760 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2761 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2762 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2763
49a687c4 2764 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2766 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2767 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2768 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2769 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2770
49a687c4 2771 if (dirty & WM_DIRTY_DDB) {
a42a5719 2772 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2773 val = I915_READ(WM_MISC);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~WM_MISC_DATA_PARTITION_5_6;
2776 else
2777 val |= WM_MISC_DATA_PARTITION_5_6;
2778 I915_WRITE(WM_MISC, val);
2779 } else {
2780 val = I915_READ(DISP_ARB_CTL2);
2781 if (results->partitioning == INTEL_DDB_PART_1_2)
2782 val &= ~DISP_DATA_PARTITION_5_6;
2783 else
2784 val |= DISP_DATA_PARTITION_5_6;
2785 I915_WRITE(DISP_ARB_CTL2, val);
2786 }
1011d8c4
PZ		 2787 }
2788
49a687c4 2789 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2790 val = I915_READ(DISP_ARB_CTL);
2791 if (results->enable_fbc_wm)
2792 val &= ~DISP_FBC_WM_DIS;
2793 else
2794 val |= DISP_FBC_WM_DIS;
2795 I915_WRITE(DISP_ARB_CTL, val);
2796 }
2797
954911eb
ID		 2798 if (dirty & WM_DIRTY_LP(1) &&
2799 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2800 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2801
2802 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2803 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2804 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2805 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2806 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2807 }
801bcfff 2808
facd619b 2809 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2810 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2811 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2812 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2813 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2814 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2815
2816 dev_priv->wm.hw = *results;
801bcfff
PZ		 2817}
2818
8553c18e
VS		 2819static bool ilk_disable_lp_wm(struct drm_device *dev)
2820{
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2824}
2825
820c1980 2826static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2827{
7c4a395f 2828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2829 struct drm_device *dev = crtc->dev;
801bcfff 2830 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2831 struct ilk_wm_maximums max;
2832 struct ilk_pipe_wm_parameters params = {};
2833 struct ilk_wm_values results = {};
77c122bc 2834 enum intel_ddb_partitioning partitioning;
7c4a395f 2835 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2836 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2837 struct intel_wm_config config = {};
7c4a395f 2838
2a44b76b 2839 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2840
2841 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2842
2843 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2844 return;
861f3389 2845
7c4a395f 2846 intel_crtc->wm.active = pipe_wm;
861f3389 2847
2a44b76b
VS		 2848 ilk_compute_wm_config(dev, &config);
2849
34982fe1 2850 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2851 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2852
2853 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2854 if (INTEL_INFO(dev)->gen >= 7 &&
2855 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2856 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2857 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2858
820c1980 2859 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2860 } else {
198a1e9b 2861 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2862 }
2863
198a1e9b 2864 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2865 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2866
820c1980 2867 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2868
820c1980 2869 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2870}
2871
ed57cb8a
DL		 2872static void
2873ilk_update_sprite_wm(struct drm_plane *plane,
2874 struct drm_crtc *crtc,
2875 uint32_t sprite_width, uint32_t sprite_height,
2876 int pixel_size, bool enabled, bool scaled)
526682e9 2877{
8553c18e 2878 struct drm_device *dev = plane->dev;
adf3d35e 2879 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2880
adf3d35e
VS		 2881 intel_plane->wm.enabled = enabled;
2882 intel_plane->wm.scaled = scaled;
2883 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 2884 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 2885 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2886
8553c18e
VS		 2887 /*
2888 * IVB workaround: must disable low power watermarks for at least
2889 * one frame before enabling scaling. LP watermarks can be re-enabled
2890 * when scaling is disabled.
2891 *
2892 * WaCxSRDisabledForSpriteScaling:ivb
2893 */
2894 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2895 intel_wait_for_vblank(dev, intel_plane->pipe);
2896
820c1980 2897 ilk_update_wm(crtc);
526682e9
PZ		 2898}
2899
243e6a44
VS		 2900static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2901{
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2904 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2907 enum pipe pipe = intel_crtc->pipe;
2908 static const unsigned int wm0_pipe_reg[] = {
2909 [PIPE_A] = WM0_PIPEA_ILK,
2910 [PIPE_B] = WM0_PIPEB_ILK,
2911 [PIPE_C] = WM0_PIPEC_IVB,
2912 };
2913
2914 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2915 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2916 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2917
2a44b76b
VS		 2918 active->pipe_enabled = intel_crtc_active(crtc);
2919
2920 if (active->pipe_enabled) {
243e6a44
VS		 2921 u32 tmp = hw->wm_pipe[pipe];
2922
2923 /*
2924 * For active pipes LP0 watermark is marked as
2925 * enabled, and LP1+ watermaks as disabled since
2926 * we can't really reverse compute them in case
2927 * multiple pipes are active.
2928 */
2929 active->wm[0].enable = true;
2930 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2931 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2932 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2933 active->linetime = hw->wm_linetime[pipe];
2934 } else {
2935 int level, max_level = ilk_wm_max_level(dev);
2936
2937 /*
2938 * For inactive pipes, all watermark levels
2939 * should be marked as enabled but zeroed,
2940 * which is what we'd compute them to.
2941 */
2942 for (level = 0; level <= max_level; level++)
2943 active->wm[level].enable = true;
2944 }
2945}
2946
2947void ilk_wm_get_hw_state(struct drm_device *dev)
2948{
2949 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2950 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2951 struct drm_crtc *crtc;
2952
70e1e0ec 2953 for_each_crtc(dev, crtc)
243e6a44
VS		 2954 ilk_pipe_wm_get_hw_state(crtc);
2955
2956 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2957 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2958 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2959
2960 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2961 if (INTEL_INFO(dev)->gen >= 7) {
2962 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2963 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2964 }
243e6a44 2965
a42a5719 2966 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2967 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2968 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2969 else if (IS_IVYBRIDGE(dev))
2970 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2971 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2972
2973 hw->enable_fbc_wm =
2974 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2975}
2976
b445e3b0
ED		 2977/**
2978 * intel_update_watermarks - update FIFO watermark values based on current modes
2979 *
2980 * Calculate watermark values for the various WM regs based on current mode
2981 * and plane configuration.
2982 *
2983 * There are several cases to deal with here:
2984 * - normal (i.e. non-self-refresh)
2985 * - self-refresh (SR) mode
2986 * - lines are large relative to FIFO size (buffer can hold up to 2)
2987 * - lines are small relative to FIFO size (buffer can hold more than 2
2988 * lines), so need to account for TLB latency
2989 *
2990 * The normal calculation is:
2991 * watermark = dotclock * bytes per pixel * latency
2992 * where latency is platform & configuration dependent (we assume pessimal
2993 * values here).
2994 *
2995 * The SR calculation is:
2996 * watermark = (trunc(latency/line time)+1) * surface width *
2997 * bytes per pixel
2998 * where
2999 * line time = htotal / dotclock
3000 * surface width = hdisplay for normal plane and 64 for cursor
3001 * and latency is assumed to be high, as above.
3002 *
3003 * The final value programmed to the register should always be rounded up,
3004 * and include an extra 2 entries to account for clock crossings.
3005 *
3006 * We don't use the sprite, so we can ignore that. And on Crestline we have
3007 * to set the non-SR watermarks to 8.
3008 */
46ba614c 3009void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3010{
46ba614c 3011 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3012
3013 if (dev_priv->display.update_wm)
46ba614c 3014 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3015}
3016
adf3d35e
VS		 3017void intel_update_sprite_watermarks(struct drm_plane *plane,
3018 struct drm_crtc *crtc,
ed57cb8a
DL		 3019 uint32_t sprite_width,
3020 uint32_t sprite_height,
3021 int pixel_size,
39db4a4d 3022 bool enabled, bool scaled)
b445e3b0 3023{
adf3d35e 3024 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3025
3026 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3027 dev_priv->display.update_sprite_wm(plane, crtc,
3028 sprite_width, sprite_height,
39db4a4d 3029 pixel_size, enabled, scaled);
b445e3b0
ED		 3030}
3031
2b4e57bd
ED		 3032static struct drm_i915_gem_object *
3033intel_alloc_context_page(struct drm_device *dev)
3034{
3035 struct drm_i915_gem_object *ctx;
3036 int ret;
3037
3038 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3039
3040 ctx = i915_gem_alloc_object(dev, 4096);
3041 if (!ctx) {
3042 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3043 return NULL;
3044 }
3045
c69766f2 3046 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 3047 if (ret) {
3048 DRM_ERROR("failed to pin power context: %d\n", ret);
3049 goto err_unref;
3050 }
3051
3052 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3053 if (ret) {
3054 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3055 goto err_unpin;
3056 }
3057
3058 return ctx;
3059
3060err_unpin:
d7f46fc4 3061 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 3062err_unref:
3063 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3064 return NULL;
3065}
3066
9270388e
DV		 3067/**
3068 * Lock protecting IPS related data structures
9270388e
DV		 3069 */
3070DEFINE_SPINLOCK(mchdev_lock);
3071
3072/* Global for IPS driver to get at the current i915 device. Protected by
3073 * mchdev_lock. */
3074static struct drm_i915_private *i915_mch_dev;
3075
2b4e57bd
ED		 3076bool ironlake_set_drps(struct drm_device *dev, u8 val)
3077{
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 u16 rgvswctl;
3080
9270388e
DV		 3081 assert_spin_locked(&mchdev_lock);
3082
2b4e57bd
ED		 3083 rgvswctl = I915_READ16(MEMSWCTL);
3084 if (rgvswctl & MEMCTL_CMD_STS) {
3085 DRM_DEBUG("gpu busy, RCS change rejected\n");
3086 return false; /* still busy with another command */
3087 }
3088
3089 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3090 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3091 I915_WRITE16(MEMSWCTL, rgvswctl);
3092 POSTING_READ16(MEMSWCTL);
3093
3094 rgvswctl |= MEMCTL_CMD_STS;
3095 I915_WRITE16(MEMSWCTL, rgvswctl);
3096
3097 return true;
3098}
3099
8090c6b9 3100static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3101{
3102 struct drm_i915_private *dev_priv = dev->dev_private;
3103 u32 rgvmodectl = I915_READ(MEMMODECTL);
3104 u8 fmax, fmin, fstart, vstart;
3105
9270388e
DV		 3106 spin_lock_irq(&mchdev_lock);
3107
2b4e57bd
ED		 3108 /* Enable temp reporting */
3109 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3110 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3111
3112 /* 100ms RC evaluation intervals */
3113 I915_WRITE(RCUPEI, 100000);
3114 I915_WRITE(RCDNEI, 100000);
3115
3116 /* Set max/min thresholds to 90ms and 80ms respectively */
3117 I915_WRITE(RCBMAXAVG, 90000);
3118 I915_WRITE(RCBMINAVG, 80000);
3119
3120 I915_WRITE(MEMIHYST, 1);
3121
3122 /* Set up min, max, and cur for interrupt handling */
3123 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3124 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3125 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3126 MEMMODE_FSTART_SHIFT;
3127
3128 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3129 PXVFREQ_PX_SHIFT;
3130
20e4d407
DV		 3131 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3132 dev_priv->ips.fstart = fstart;
2b4e57bd 3133
20e4d407
DV		 3134 dev_priv->ips.max_delay = fstart;
3135 dev_priv->ips.min_delay = fmin;
3136 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3137
3138 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3139 fmax, fmin, fstart);
3140
3141 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3142
3143 /*
3144 * Interrupts will be enabled in ironlake_irq_postinstall
3145 */
3146
3147 I915_WRITE(VIDSTART, vstart);
3148 POSTING_READ(VIDSTART);
3149
3150 rgvmodectl |= MEMMODE_SWMODE_EN;
3151 I915_WRITE(MEMMODECTL, rgvmodectl);
3152
9270388e 3153 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3154 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3155 mdelay(1);
2b4e57bd
ED		 3156
3157 ironlake_set_drps(dev, fstart);
3158
20e4d407 3159 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3160 I915_READ(0x112e0);
20e4d407
DV		 3161 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3162 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3163 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3164
3165 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3166}
3167
8090c6b9 3168static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3169{
3170 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3171 u16 rgvswctl;
3172
3173 spin_lock_irq(&mchdev_lock);
3174
3175 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3176
3177 /* Ack interrupts, disable EFC interrupt */
3178 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3179 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3180 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3181 I915_WRITE(DEIIR, DE_PCU_EVENT);
3182 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3183
3184 /* Go back to the starting frequency */
20e4d407 3185 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3186 mdelay(1);
2b4e57bd
ED		 3187 rgvswctl |= MEMCTL_CMD_STS;
3188 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3189 mdelay(1);
2b4e57bd 3190
9270388e 3191 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3192}
3193
acbe9475
DV		 3194/* There's a funny hw issue where the hw returns all 0 when reading from
3195 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3196 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3197 * all limits and the gpu stuck at whatever frequency it is at atm).
3198 */
6917c7b9 3199static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3200{
7b9e0ae6 3201 u32 limits;
2b4e57bd 3202
20b46e59
DV		 3203 /* Only set the down limit when we've reached the lowest level to avoid
3204 * getting more interrupts, otherwise leave this clear. This prevents a
3205 * race in the hw when coming out of rc6: There's a tiny window where
3206 * the hw runs at the minimal clock before selecting the desired
3207 * frequency, if the down threshold expires in that window we will not
3208 * receive a down interrupt. */
b39fb297
BW		 3209 limits = dev_priv->rps.max_freq_softlimit << 24;
3210 if (val <= dev_priv->rps.min_freq_softlimit)
3211 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3212
3213 return limits;
3214}
3215
dd75fdc8
CW		 3216static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3217{
3218 int new_power;
3219
3220 new_power = dev_priv->rps.power;
3221 switch (dev_priv->rps.power) {
3222 case LOW_POWER:
b39fb297 3223 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3224 new_power = BETWEEN;
3225 break;
3226
3227 case BETWEEN:
b39fb297 3228 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3229 new_power = LOW_POWER;
b39fb297 3230 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3231 new_power = HIGH_POWER;
3232 break;
3233
3234 case HIGH_POWER:
b39fb297 3235 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3236 new_power = BETWEEN;
3237 break;
3238 }
3239 /* Max/min bins are special */
b39fb297 3240 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3241 new_power = LOW_POWER;
b39fb297 3242 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3243 new_power = HIGH_POWER;
3244 if (new_power == dev_priv->rps.power)
3245 return;
3246
3247 /* Note the units here are not exactly 1us, but 1280ns. */
3248 switch (new_power) {
3249 case LOW_POWER:
3250 /* Upclock if more than 95% busy over 16ms */
3251 I915_WRITE(GEN6_RP_UP_EI, 12500);
3252 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3253
3254 /* Downclock if less than 85% busy over 32ms */
3255 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3256 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3257
3258 I915_WRITE(GEN6_RP_CONTROL,
3259 GEN6_RP_MEDIA_TURBO |
3260 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3261 GEN6_RP_MEDIA_IS_GFX |
3262 GEN6_RP_ENABLE |
3263 GEN6_RP_UP_BUSY_AVG |
3264 GEN6_RP_DOWN_IDLE_AVG);
3265 break;
3266
3267 case BETWEEN:
3268 /* Upclock if more than 90% busy over 13ms */
3269 I915_WRITE(GEN6_RP_UP_EI, 10250);
3270 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3271
3272 /* Downclock if less than 75% busy over 32ms */
3273 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3274 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3275
3276 I915_WRITE(GEN6_RP_CONTROL,
3277 GEN6_RP_MEDIA_TURBO |
3278 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3279 GEN6_RP_MEDIA_IS_GFX |
3280 GEN6_RP_ENABLE |
3281 GEN6_RP_UP_BUSY_AVG |
3282 GEN6_RP_DOWN_IDLE_AVG);
3283 break;
3284
3285 case HIGH_POWER:
3286 /* Upclock if more than 85% busy over 10ms */
3287 I915_WRITE(GEN6_RP_UP_EI, 8000);
3288 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3289
3290 /* Downclock if less than 60% busy over 32ms */
3291 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3292 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3293
3294 I915_WRITE(GEN6_RP_CONTROL,
3295 GEN6_RP_MEDIA_TURBO |
3296 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3297 GEN6_RP_MEDIA_IS_GFX |
3298 GEN6_RP_ENABLE |
3299 GEN6_RP_UP_BUSY_AVG |
3300 GEN6_RP_DOWN_IDLE_AVG);
3301 break;
3302 }
3303
3304 dev_priv->rps.power = new_power;
3305 dev_priv->rps.last_adj = 0;
3306}
3307
2876ce73
CW		 3308static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3309{
3310 u32 mask = 0;
3311
3312 if (val > dev_priv->rps.min_freq_softlimit)
3313 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3314 if (val < dev_priv->rps.max_freq_softlimit)
3315 mask |= GEN6_PM_RP_UP_THRESHOLD;
3316
7b3c29f6
CW		 3317 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3318 mask &= dev_priv->pm_rps_events;
3319
2876ce73
CW		 3320 /* IVB and SNB hard hangs on looping batchbuffer
3321 * if GEN6_PM_UP_EI_EXPIRED is masked.
3322 */
3323 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3324 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3325
baccd458
D		 3326 if (IS_GEN8(dev_priv->dev))
3327 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3328
2876ce73
CW		 3329 return ~mask;
3330}
3331
b8a5ff8d
JM		 3332/* gen6_set_rps is called to update the frequency request, but should also be
3333 * called when the range (min_delay and max_delay) is modified so that we can
3334 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3335void gen6_set_rps(struct drm_device *dev, u8 val)
3336{
3337 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3338
4fc688ce 3339 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3340 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3341 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3342
eb64cad1
CW		 3343 /* min/max delay may still have been modified so be sure to
3344 * write the limits value.
3345 */
3346 if (val != dev_priv->rps.cur_freq) {
3347 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3348
50e6a2a7 3349 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3350 I915_WRITE(GEN6_RPNSWREQ,
3351 HSW_FREQUENCY(val));
3352 else
3353 I915_WRITE(GEN6_RPNSWREQ,
3354 GEN6_FREQUENCY(val) |
3355 GEN6_OFFSET(0) |
3356 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3357 }
7b9e0ae6 3358
7b9e0ae6
CW		 3359 /* Make sure we continue to get interrupts
3360 * until we hit the minimum or maximum frequencies.
3361 */
eb64cad1 3362 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3363 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3364
d5570a72
BW		 3365 POSTING_READ(GEN6_RPNSWREQ);
3366
b39fb297 3367 dev_priv->rps.cur_freq = val;
be2cde9a 3368 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3369}
3370
76c3552f
D		 3371/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3372 *
3373 * * If Gfx is Idle, then
3374 * 1. Mask Turbo interrupts
3375 * 2. Bring up Gfx clock
3376 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3377 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3378 * 5. Unmask Turbo interrupts
3379*/
3380static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3381{
5549d25f
D		 3382 struct drm_device *dev = dev_priv->dev;
3383
3384 /* Latest VLV doesn't need to force the gfx clock */
3385 if (dev->pdev->revision >= 0xd) {
3386 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3387 return;
3388 }
3389
76c3552f
D		 3390 /*
3391 * When we are idle. Drop to min voltage state.
3392 */
3393
b39fb297 3394 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3395 return;
3396
3397 /* Mask turbo interrupt so that they will not come in between */
3398 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3399
650ad970 3400 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3401
b39fb297 3402 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3403
3404 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3405 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3406
3407 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3408 & GENFREQSTATUS) == 0, 5))
3409 DRM_ERROR("timed out waiting for Punit\n");
3410
650ad970 3411 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3412
2876ce73
CW		 3413 I915_WRITE(GEN6_PMINTRMSK,
3414 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3415}
3416
b29c19b6
CW		 3417void gen6_rps_idle(struct drm_i915_private *dev_priv)
3418{
691bb717
DL		 3419 struct drm_device *dev = dev_priv->dev;
3420
b29c19b6 3421 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3422 if (dev_priv->rps.enabled) {
34638118
D		 3423 if (IS_CHERRYVIEW(dev))
3424 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3425 else if (IS_VALLEYVIEW(dev))
76c3552f 3426 vlv_set_rps_idle(dev_priv);
c0951f0c 3427 else
b39fb297 3428 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3429 dev_priv->rps.last_adj = 0;
3430 }
b29c19b6
CW		 3431 mutex_unlock(&dev_priv->rps.hw_lock);
3432}
3433
3434void gen6_rps_boost(struct drm_i915_private *dev_priv)
3435{
691bb717
DL		 3436 struct drm_device *dev = dev_priv->dev;
3437
b29c19b6 3438 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3439 if (dev_priv->rps.enabled) {
691bb717 3440 if (IS_VALLEYVIEW(dev))
b39fb297 3441 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3442 else
b39fb297 3443 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3444 dev_priv->rps.last_adj = 0;
3445 }
b29c19b6
CW		 3446 mutex_unlock(&dev_priv->rps.hw_lock);
3447}
3448
0a073b84
JB		 3449void valleyview_set_rps(struct drm_device *dev, u8 val)
3450{
3451 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3452
0a073b84 3453 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3454 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3455 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3456
73008b98 3457 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3458 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3459 dev_priv->rps.cur_freq,
2ec3815f 3460 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3461
2876ce73
CW		 3462 if (val != dev_priv->rps.cur_freq)
3463 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3464
09c87db8 3465 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3466
b39fb297 3467 dev_priv->rps.cur_freq = val;
2ec3815f 3468 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3469}
3470
0961021a
BW		 3471static void gen8_disable_rps_interrupts(struct drm_device *dev)
3472{
3473 struct drm_i915_private *dev_priv = dev->dev_private;
3474
992f191f 3475 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3476 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3477 ~dev_priv->pm_rps_events);
3478 /* Complete PM interrupt masking here doesn't race with the rps work
3479 * item again unmasking PM interrupts because that is using a different
3480 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3481 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3482 * gen8_enable_rps will clean up. */
3483
3484 spin_lock_irq(&dev_priv->irq_lock);
3485 dev_priv->rps.pm_iir = 0;
3486 spin_unlock_irq(&dev_priv->irq_lock);
3487
3488 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3489}
3490
44fc7d5c 3491static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3492{
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494
2b4e57bd 3495 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3496 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3497 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3498 /* Complete PM interrupt masking here doesn't race with the rps work
3499 * item again unmasking PM interrupts because that is using a different
3500 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3501 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3502
59cdb63d 3503 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3504 dev_priv->rps.pm_iir = 0;
59cdb63d 3505 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3506
a6706b45 3507 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3508}
3509
44fc7d5c 3510static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3511{
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513
3514 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3515 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3516
0961021a
BW		 3517 if (IS_BROADWELL(dev))
3518 gen8_disable_rps_interrupts(dev);
3519 else
3520 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3521}
3522
38807746
D		 3523static void cherryview_disable_rps(struct drm_device *dev)
3524{
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526
3527 I915_WRITE(GEN6_RC_CONTROL, 0);
3497a562
D		 3528
3529 gen8_disable_rps_interrupts(dev);
38807746
D		 3530}
3531
44fc7d5c
DV		 3532static void valleyview_disable_rps(struct drm_device *dev)
3533{
3534 struct drm_i915_private *dev_priv = dev->dev_private;
3535
98a2e5f9
D		 3536 /* we're doing forcewake before Disabling RC6,
3537 * This what the BIOS expects when going into suspend */
3538 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3539
44fc7d5c 3540 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3541
98a2e5f9
D		 3542 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3543
44fc7d5c 3544 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3545}
3546
dc39fff7
BW		 3547static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3548{
91ca689a
ID		 3549 if (IS_VALLEYVIEW(dev)) {
3550 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3551 mode = GEN6_RC_CTL_RC6_ENABLE;
3552 else
3553 mode = 0;
3554 }
8dfd1f04
DV		 3555 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3556 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3557 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3558 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3559}
3560
e6069ca8 3561static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3562{
eb4926e4
DL		 3563 /* No RC6 before Ironlake */
3564 if (INTEL_INFO(dev)->gen < 5)
3565 return 0;
3566
e6069ca8
ID		 3567 /* RC6 is only on Ironlake mobile not on desktop */
3568 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3569 return 0;
3570
456470eb 3571 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3572 if (enable_rc6 >= 0) {
3573 int mask;
3574
3575 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3576 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3577 INTEL_RC6pp_ENABLE;
3578 else
3579 mask = INTEL_RC6_ENABLE;
3580
3581 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 3582 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3583 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3584
3585 return enable_rc6 & mask;
3586 }
2b4e57bd 3587
6567d748
CW		 3588 /* Disable RC6 on Ironlake */
3589 if (INTEL_INFO(dev)->gen == 5)
3590 return 0;
2b4e57bd 3591
8bade1ad 3592 if (IS_IVYBRIDGE(dev))
cca84a1f 3593 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3594
3595 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3596}
3597
e6069ca8
ID		 3598int intel_enable_rc6(const struct drm_device *dev)
3599{
3600 return i915.enable_rc6;
3601}
3602
0961021a
BW		 3603static void gen8_enable_rps_interrupts(struct drm_device *dev)
3604{
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606
3607 spin_lock_irq(&dev_priv->irq_lock);
3608 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3609 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
0961021a
BW		 3610 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3611 spin_unlock_irq(&dev_priv->irq_lock);
3612}
3613
44fc7d5c
DV		 3614static void gen6_enable_rps_interrupts(struct drm_device *dev)
3615{
3616 struct drm_i915_private *dev_priv = dev->dev_private;
3617
3618 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3619 WARN_ON(dev_priv->rps.pm_iir);
480c8033 3620 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
a6706b45 3621 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3622 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3623}
3624
3280e8b0
BW		 3625static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3626{
3627 /* All of these values are in units of 50MHz */
3628 dev_priv->rps.cur_freq = 0;
3629 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3630 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3631 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3632 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3633 /* XXX: only BYT has a special efficient freq */
3634 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3635 /* hw_max = RP0 until we check for overclocking */
3636 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3637
3638 /* Preserve min/max settings in case of re-init */
3639 if (dev_priv->rps.max_freq_softlimit == 0)
3640 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3641
3642 if (dev_priv->rps.min_freq_softlimit == 0)
3643 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3644}
3645
6edee7f3
BW		 3646static void gen8_enable_rps(struct drm_device *dev)
3647{
3648 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3649 struct intel_engine_cs *ring;
6edee7f3
BW		 3650 uint32_t rc6_mask = 0, rp_state_cap;
3651 int unused;
3652
3653 /* 1a: Software RC state - RC0 */
3654 I915_WRITE(GEN6_RC_STATE, 0);
3655
3656 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3657 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3658 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3659
3660 /* 2a: Disable RC states. */
3661 I915_WRITE(GEN6_RC_CONTROL, 0);
3662
3663 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3664 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3665
3666 /* 2b: Program RC6 thresholds.*/
3667 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3668 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3669 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3670 for_each_ring(ring, dev_priv, unused)
3671 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3672 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 3673 if (IS_BROADWELL(dev))
3674 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
3675 else
3676 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 3677
3678 /* 3: Enable RC6 */
3679 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3680 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3681 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 3682 if (IS_BROADWELL(dev))
3683 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3684 GEN7_RC_CTL_TO_MODE |
3685 rc6_mask);
3686 else
3687 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3688 GEN6_RC_CTL_EI_MODE(1) |
3689 rc6_mask);
6edee7f3
BW		 3690
3691 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3692 I915_WRITE(GEN6_RPNSWREQ,
3693 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3694 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3695 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3696 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3697 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3698
3699 /* Docs recommend 900MHz, and 300 MHz respectively */
3700 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3701 dev_priv->rps.max_freq_softlimit << 24 |
3702 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3703
3704 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3705 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3706 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3707 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3708
3709 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3710
3711 /* 5: Enable RPS */
3712 I915_WRITE(GEN6_RP_CONTROL,
3713 GEN6_RP_MEDIA_TURBO |
3714 GEN6_RP_MEDIA_HW_NORMAL_MODE |
223a6f2b 3715 GEN6_RP_MEDIA_IS_GFX |
6edee7f3
BW		 3716 GEN6_RP_ENABLE |
3717 GEN6_RP_UP_BUSY_AVG |
3718 GEN6_RP_DOWN_IDLE_AVG);
3719
3720 /* 6: Ring frequency + overclocking (our driver does this later */
3721
3722 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3723
0961021a 3724 gen8_enable_rps_interrupts(dev);
6edee7f3 3725
c8d9a590 3726 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3727}
3728
79f5b2c7 3729static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3730{
79f5b2c7 3731 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 3732 struct intel_engine_cs *ring;
2a5913a8 3733 u32 rp_state_cap;
d060c169 3734 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3735 u32 gtfifodbg;
2b4e57bd 3736 int rc6_mode;
42c0526c 3737 int i, ret;
2b4e57bd 3738
4fc688ce 3739 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3740
2b4e57bd
ED		 3741 /* Here begins a magic sequence of register writes to enable
3742 * auto-downclocking.
3743 *
3744 * Perhaps there might be some value in exposing these to
3745 * userspace...
3746 */
3747 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3748
3749 /* Clear the DBG now so we don't confuse earlier errors */
3750 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3751 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3752 I915_WRITE(GTFIFODBG, gtfifodbg);
3753 }
3754
c8d9a590 3755 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3756
7b9e0ae6 3757 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7b9e0ae6 3758
3280e8b0 3759 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3760
2b4e57bd
ED		 3761 /* disable the counters and set deterministic thresholds */
3762 I915_WRITE(GEN6_RC_CONTROL, 0);
3763
3764 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3765 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3766 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3767 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3768 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3769
b4519513
CW		 3770 for_each_ring(ring, dev_priv, i)
3771 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3772
3773 I915_WRITE(GEN6_RC_SLEEP, 0);
3774 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3775 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3776 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3777 else
3778 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3779 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3780 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3781
5a7dc92a 3782 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3783 rc6_mode = intel_enable_rc6(dev_priv->dev);
3784 if (rc6_mode & INTEL_RC6_ENABLE)
3785 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3786
5a7dc92a
ED		 3787 /* We don't use those on Haswell */
3788 if (!IS_HASWELL(dev)) {
3789 if (rc6_mode & INTEL_RC6p_ENABLE)
3790 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3791
5a7dc92a
ED		 3792 if (rc6_mode & INTEL_RC6pp_ENABLE)
3793 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3794 }
2b4e57bd 3795
dc39fff7 3796 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3797
3798 I915_WRITE(GEN6_RC_CONTROL,
3799 rc6_mask |
3800 GEN6_RC_CTL_EI_MODE(1) |
3801 GEN6_RC_CTL_HW_ENABLE);
3802
dd75fdc8
CW		 3803 /* Power down if completely idle for over 50ms */
3804 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3805 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3806
42c0526c 3807 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3808 if (ret)
42c0526c 3809 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3810
3811 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3812 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3813 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3814 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3815 (pcu_mbox & 0xff) * 50);
b39fb297 3816 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3817 }
3818
dd75fdc8 3819 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3820 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3821
44fc7d5c 3822 gen6_enable_rps_interrupts(dev);
2b4e57bd 3823
31643d54
BW		 3824 rc6vids = 0;
3825 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3826 if (IS_GEN6(dev) && ret) {
3827 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3828 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3829 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3830 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3831 rc6vids &= 0xffff00;
3832 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3833 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3834 if (ret)
3835 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3836 }
3837
c8d9a590 3838 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3839}
3840
c2bc2fc5 3841static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3842{
79f5b2c7 3843 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3844 int min_freq = 15;
3ebecd07
CW		 3845 unsigned int gpu_freq;
3846 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3847 int scaling_factor = 180;
eda79642 3848 struct cpufreq_policy *policy;
2b4e57bd 3849
4fc688ce 3850 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3851
eda79642
BW		 3852 policy = cpufreq_cpu_get(0);
3853 if (policy) {
3854 max_ia_freq = policy->cpuinfo.max_freq;
3855 cpufreq_cpu_put(policy);
3856 } else {
3857 /*
3858 * Default to measured freq if none found, PCU will ensure we
3859 * don't go over
3860 */
2b4e57bd 3861 max_ia_freq = tsc_khz;
eda79642 3862 }
2b4e57bd
ED		 3863
3864 /* Convert from kHz to MHz */
3865 max_ia_freq /= 1000;
3866
153b4b95 3867 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3868 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3869 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3870
2b4e57bd
ED		 3871 /*
3872 * For each potential GPU frequency, load a ring frequency we'd like
3873 * to use for memory access. We do this by specifying the IA frequency
3874 * the PCU should use as a reference to determine the ring frequency.
3875 */
b39fb297 3876 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3877 gpu_freq--) {
b39fb297 3878 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3879 unsigned int ia_freq = 0, ring_freq = 0;
3880
46c764d4
BW		 3881 if (INTEL_INFO(dev)->gen >= 8) {
3882 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3883 ring_freq = max(min_ring_freq, gpu_freq);
3884 } else if (IS_HASWELL(dev)) {
f6aca45c 3885 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3886 ring_freq = max(min_ring_freq, ring_freq);
3887 /* leave ia_freq as the default, chosen by cpufreq */
3888 } else {
3889 /* On older processors, there is no separate ring
3890 * clock domain, so in order to boost the bandwidth
3891 * of the ring, we need to upclock the CPU (ia_freq).
3892 *
3893 * For GPU frequencies less than 750MHz,
3894 * just use the lowest ring freq.
3895 */
3896 if (gpu_freq < min_freq)
3897 ia_freq = 800;
3898 else
3899 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3900 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3901 }
2b4e57bd 3902
42c0526c
BW		 3903 sandybridge_pcode_write(dev_priv,
3904 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3905 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3906 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3907 gpu_freq);
2b4e57bd 3908 }
2b4e57bd
ED		 3909}
3910
c2bc2fc5
ID		 3911void gen6_update_ring_freq(struct drm_device *dev)
3912{
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914
3915 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3916 return;
3917
3918 mutex_lock(&dev_priv->rps.hw_lock);
3919 __gen6_update_ring_freq(dev);
3920 mutex_unlock(&dev_priv->rps.hw_lock);
3921}
3922
03af2045 3923static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3924{
3925 u32 val, rp0;
3926
3927 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3928 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3929
3930 return rp0;
3931}
3932
3933static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3934{
3935 u32 val, rpe;
3936
3937 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
3938 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
3939
3940 return rpe;
3941}
3942
7707df4a
D		 3943static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
3944{
3945 u32 val, rp1;
3946
3947 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3948 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK;
3949
3950 return rp1;
3951}
3952
03af2045 3953static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 3954{
3955 u32 val, rpn;
3956
3957 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
3958 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK;
3959 return rpn;
3960}
3961
f8f2b001
D		 3962static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
3963{
3964 u32 val, rp1;
3965
3966 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3967
3968 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
3969
3970 return rp1;
3971}
3972
03af2045 3973static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 3974{
3975 u32 val, rp0;
3976
64936258 3977 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3978
3979 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3980 /* Clamp to max */
3981 rp0 = min_t(u32, rp0, 0xea);
3982
3983 return rp0;
3984}
3985
3986static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3987{
3988 u32 val, rpe;
3989
64936258 3990 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3991 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3992 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3993 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3994
3995 return rpe;
3996}
3997
03af2045 3998static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 3999{
64936258 4000 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4001}
4002
ae48434c
ID		 4003/* Check that the pctx buffer wasn't move under us. */
4004static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4005{
4006 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4007
4008 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4009 dev_priv->vlv_pctx->stolen->start);
4010}
4011
38807746
D		 4012
4013/* Check that the pcbr address is not empty. */
4014static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4015{
4016 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4017
4018 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4019}
4020
4021static void cherryview_setup_pctx(struct drm_device *dev)
4022{
4023 struct drm_i915_private *dev_priv = dev->dev_private;
4024 unsigned long pctx_paddr, paddr;
4025 struct i915_gtt *gtt = &dev_priv->gtt;
4026 u32 pcbr;
4027 int pctx_size = 32*1024;
4028
4029 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4030
4031 pcbr = I915_READ(VLV_PCBR);
4032 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
4033 paddr = (dev_priv->mm.stolen_base +
4034 (gtt->stolen_size - pctx_size));
4035
4036 pctx_paddr = (paddr & (~4095));
4037 I915_WRITE(VLV_PCBR, pctx_paddr);
4038 }
4039}
4040
c9cddffc
JB		 4041static void valleyview_setup_pctx(struct drm_device *dev)
4042{
4043 struct drm_i915_private *dev_priv = dev->dev_private;
4044 struct drm_i915_gem_object *pctx;
4045 unsigned long pctx_paddr;
4046 u32 pcbr;
4047 int pctx_size = 24*1024;
4048
17b0c1f7
ID		 4049 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4050
c9cddffc
JB		 4051 pcbr = I915_READ(VLV_PCBR);
4052 if (pcbr) {
4053 /* BIOS set it up already, grab the pre-alloc'd space */
4054 int pcbr_offset;
4055
4056 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4057 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4058 pcbr_offset,
190d6cd5 4059 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4060 pctx_size);
4061 goto out;
4062 }
4063
4064 /*
4065 * From the Gunit register HAS:
4066 * The Gfx driver is expected to program this register and ensure
4067 * proper allocation within Gfx stolen memory. For example, this
4068 * register should be programmed such than the PCBR range does not
4069 * overlap with other ranges, such as the frame buffer, protected
4070 * memory, or any other relevant ranges.
4071 */
4072 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4073 if (!pctx) {
4074 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4075 return;
4076 }
4077
4078 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4079 I915_WRITE(VLV_PCBR, pctx_paddr);
4080
4081out:
4082 dev_priv->vlv_pctx = pctx;
4083}
4084
ae48434c
ID		 4085static void valleyview_cleanup_pctx(struct drm_device *dev)
4086{
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088
4089 if (WARN_ON(!dev_priv->vlv_pctx))
4090 return;
4091
4092 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4093 dev_priv->vlv_pctx = NULL;
4094}
4095
4e80519e
ID		 4096static void valleyview_init_gt_powersave(struct drm_device *dev)
4097{
4098 struct drm_i915_private *dev_priv = dev->dev_private;
4099
4100 valleyview_setup_pctx(dev);
4101
4102 mutex_lock(&dev_priv->rps.hw_lock);
4103
4104 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4105 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4106 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4107 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4108 dev_priv->rps.max_freq);
4109
4110 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4111 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4112 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4113 dev_priv->rps.efficient_freq);
4114
f8f2b001
D		 4115 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4116 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4117 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4118 dev_priv->rps.rp1_freq);
4119
4e80519e
ID		 4120 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4121 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4122 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4123 dev_priv->rps.min_freq);
4124
4125 /* Preserve min/max settings in case of re-init */
4126 if (dev_priv->rps.max_freq_softlimit == 0)
4127 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4128
4129 if (dev_priv->rps.min_freq_softlimit == 0)
4130 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4131
4132 mutex_unlock(&dev_priv->rps.hw_lock);
4133}
4134
38807746
D		 4135static void cherryview_init_gt_powersave(struct drm_device *dev)
4136{
2b6b3a09
D		 4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138
38807746 4139 cherryview_setup_pctx(dev);
2b6b3a09
D		 4140
4141 mutex_lock(&dev_priv->rps.hw_lock);
4142
4143 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4144 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4145 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4146 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4147 dev_priv->rps.max_freq);
4148
4149 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4150 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4151 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4152 dev_priv->rps.efficient_freq);
4153
7707df4a
D		 4154 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4155 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4156 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4157 dev_priv->rps.rp1_freq);
4158
2b6b3a09
D		 4159 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4160 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4161 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4162 dev_priv->rps.min_freq);
4163
4164 /* Preserve min/max settings in case of re-init */
4165 if (dev_priv->rps.max_freq_softlimit == 0)
4166 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4167
4168 if (dev_priv->rps.min_freq_softlimit == 0)
4169 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4170
4171 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4172}
4173
4e80519e
ID		 4174static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4175{
4176 valleyview_cleanup_pctx(dev);
4177}
4178
38807746
D		 4179static void cherryview_enable_rps(struct drm_device *dev)
4180{
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_engine_cs *ring;
2b6b3a09 4183 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4184 int i;
4185
4186 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4187
4188 gtfifodbg = I915_READ(GTFIFODBG);
4189 if (gtfifodbg) {
4190 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4191 gtfifodbg);
4192 I915_WRITE(GTFIFODBG, gtfifodbg);
4193 }
4194
4195 cherryview_check_pctx(dev_priv);
4196
4197 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4198 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4199 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4200
4201 /* 2a: Program RC6 thresholds.*/
4202 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4203 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4204 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4205
4206 for_each_ring(ring, dev_priv, i)
4207 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4208 I915_WRITE(GEN6_RC_SLEEP, 0);
4209
4210 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4211
4212 /* allows RC6 residency counter to work */
4213 I915_WRITE(VLV_COUNTER_CONTROL,
4214 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4215 VLV_MEDIA_RC6_COUNT_EN |
4216 VLV_RENDER_RC6_COUNT_EN));
4217
4218 /* For now we assume BIOS is allocating and populating the PCBR */
4219 pcbr = I915_READ(VLV_PCBR);
4220
4221 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
4222
4223 /* 3: Enable RC6 */
4224 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4225 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4226 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
4227
4228 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4229
2b6b3a09
D		 4230 /* 4 Program defaults and thresholds for RPS*/
4231 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4232 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4233 I915_WRITE(GEN6_RP_UP_EI, 66000);
4234 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4235
4236 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4237
7405f42c
TR		 4238 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4239 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4240 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4241
2b6b3a09
D		 4242 /* 5: Enable RPS */
4243 I915_WRITE(GEN6_RP_CONTROL,
4244 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4245 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D		 4246 GEN6_RP_ENABLE |
4247 GEN6_RP_UP_BUSY_AVG |
4248 GEN6_RP_DOWN_IDLE_AVG);
4249
4250 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4251
4252 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4253 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4254
4255 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4256 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4257 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4258 dev_priv->rps.cur_freq);
4259
4260 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4261 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4262 dev_priv->rps.efficient_freq);
4263
4264 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4265
3497a562
D		 4266 gen8_enable_rps_interrupts(dev);
4267
38807746
D		 4268 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4269}
4270
0a073b84
JB		 4271static void valleyview_enable_rps(struct drm_device *dev)
4272{
4273 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4274 struct intel_engine_cs *ring;
2a5913a8 4275 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4276 int i;
4277
4278 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4279
ae48434c
ID		 4280 valleyview_check_pctx(dev_priv);
4281
0a073b84 4282 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4283 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4284 gtfifodbg);
0a073b84
JB		 4285 I915_WRITE(GTFIFODBG, gtfifodbg);
4286 }
4287
c8d9a590
D		 4288 /* If VLV, Forcewake all wells, else re-direct to regular path */
4289 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4290
4291 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4292 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4293 I915_WRITE(GEN6_RP_UP_EI, 66000);
4294 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4295
4296 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
31685c25 4297 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
0a073b84
JB		 4298
4299 I915_WRITE(GEN6_RP_CONTROL,
4300 GEN6_RP_MEDIA_TURBO |
4301 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4302 GEN6_RP_MEDIA_IS_GFX |
4303 GEN6_RP_ENABLE |
4304 GEN6_RP_UP_BUSY_AVG |
4305 GEN6_RP_DOWN_IDLE_CONT);
4306
4307 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4308 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4309 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4310
4311 for_each_ring(ring, dev_priv, i)
4312 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4313
2f0aa304 4314 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4315
4316 /* allows RC6 residency counter to work */
49798eb2 4317 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 4318 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4319 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 4320 VLV_MEDIA_RC6_COUNT_EN |
4321 VLV_RENDER_RC6_COUNT_EN));
31685c25 4322
a2b23fe0 4323 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4324 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4325
4326 intel_print_rc6_info(dev, rc6_mode);
4327
a2b23fe0 4328 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4329
64936258 4330 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4331
4332 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4333 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4334
b39fb297 4335 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4336 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 4337 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4338 dev_priv->rps.cur_freq);
0a073b84 4339
73008b98 4340 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 4341 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4342 dev_priv->rps.efficient_freq);
0a073b84 4343
b39fb297 4344 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4345
44fc7d5c 4346 gen6_enable_rps_interrupts(dev);
0a073b84 4347
c8d9a590 4348 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4349}
4350
930ebb46 4351void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4352{
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354
3e373948 4355 if (dev_priv->ips.renderctx) {
d7f46fc4 4356 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 4357 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4358 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4359 }
4360
3e373948 4361 if (dev_priv->ips.pwrctx) {
d7f46fc4 4362 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 4363 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4364 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4365 }
4366}
4367
930ebb46 4368static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4369{
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371
4372 if (I915_READ(PWRCTXA)) {
4373 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4374 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4375 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4376 50);
4377
4378 I915_WRITE(PWRCTXA, 0);
4379 POSTING_READ(PWRCTXA);
4380
4381 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4382 POSTING_READ(RSTDBYCTL);
4383 }
2b4e57bd
ED		 4384}
4385
4386static int ironlake_setup_rc6(struct drm_device *dev)
4387{
4388 struct drm_i915_private *dev_priv = dev->dev_private;
4389
3e373948
DV		 4390 if (dev_priv->ips.renderctx == NULL)
4391 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4392 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4393 return -ENOMEM;
4394
3e373948
DV		 4395 if (dev_priv->ips.pwrctx == NULL)
4396 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4397 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4398 ironlake_teardown_rc6(dev);
4399 return -ENOMEM;
4400 }
4401
4402 return 0;
4403}
4404
930ebb46 4405static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4406{
4407 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4408 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4409 bool was_interruptible;
2b4e57bd
ED		 4410 int ret;
4411
4412 /* rc6 disabled by default due to repeated reports of hanging during
4413 * boot and resume.
4414 */
4415 if (!intel_enable_rc6(dev))
4416 return;
4417
79f5b2c7
DV		 4418 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4419
2b4e57bd 4420 ret = ironlake_setup_rc6(dev);
79f5b2c7 4421 if (ret)
2b4e57bd 4422 return;
2b4e57bd 4423
3e960501
CW		 4424 was_interruptible = dev_priv->mm.interruptible;
4425 dev_priv->mm.interruptible = false;
4426
2b4e57bd
ED		 4427 /*
4428 * GPU can automatically power down the render unit if given a page
4429 * to save state.
4430 */
6d90c952 4431 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4432 if (ret) {
4433 ironlake_teardown_rc6(dev);
3e960501 4434 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4435 return;
4436 }
4437
6d90c952
DV		 4438 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4439 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4440 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4441 MI_MM_SPACE_GTT |
4442 MI_SAVE_EXT_STATE_EN |
4443 MI_RESTORE_EXT_STATE_EN |
4444 MI_RESTORE_INHIBIT);
4445 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4446 intel_ring_emit(ring, MI_NOOP);
4447 intel_ring_emit(ring, MI_FLUSH);
4448 intel_ring_advance(ring);
2b4e57bd
ED		 4449
4450 /*
4451 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4452 * does an implicit flush, combined with MI_FLUSH above, it should be
4453 * safe to assume that renderctx is valid
4454 */
3e960501
CW		 4455 ret = intel_ring_idle(ring);
4456 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4457 if (ret) {
def27a58 4458 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4459 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4460 return;
4461 }
4462
f343c5f6 4463 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4464 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4465
91ca689a 4466 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4467}
4468
dde18883
ED		 4469static unsigned long intel_pxfreq(u32 vidfreq)
4470{
4471 unsigned long freq;
4472 int div = (vidfreq & 0x3f0000) >> 16;
4473 int post = (vidfreq & 0x3000) >> 12;
4474 int pre = (vidfreq & 0x7);
4475
4476 if (!pre)
4477 return 0;
4478
4479 freq = ((div * 133333) / ((1<<post) * pre));
4480
4481 return freq;
4482}
4483
eb48eb00
DV		 4484static const struct cparams {
4485 u16 i;
4486 u16 t;
4487 u16 m;
4488 u16 c;
4489} cparams[] = {
4490 { 1, 1333, 301, 28664 },
4491 { 1, 1066, 294, 24460 },
4492 { 1, 800, 294, 25192 },
4493 { 0, 1333, 276, 27605 },
4494 { 0, 1066, 276, 27605 },
4495 { 0, 800, 231, 23784 },
4496};
4497
f531dcb2 4498static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4499{
4500 u64 total_count, diff, ret;
4501 u32 count1, count2, count3, m = 0, c = 0;
4502 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4503 int i;
4504
02d71956
DV		 4505 assert_spin_locked(&mchdev_lock);
4506
20e4d407 4507 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4508
4509 /* Prevent division-by-zero if we are asking too fast.
4510 * Also, we don't get interesting results if we are polling
4511 * faster than once in 10ms, so just return the saved value
4512 * in such cases.
4513 */
4514 if (diff1 <= 10)
20e4d407 4515 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4516
4517 count1 = I915_READ(DMIEC);
4518 count2 = I915_READ(DDREC);
4519 count3 = I915_READ(CSIEC);
4520
4521 total_count = count1 + count2 + count3;
4522
4523 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4524 if (total_count < dev_priv->ips.last_count1) {
4525 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4526 diff += total_count;
4527 } else {
20e4d407 4528 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4529 }
4530
4531 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4532 if (cparams[i].i == dev_priv->ips.c_m &&
4533 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4534 m = cparams[i].m;
4535 c = cparams[i].c;
4536 break;
4537 }
4538 }
4539
4540 diff = div_u64(diff, diff1);
4541 ret = ((m * diff) + c);
4542 ret = div_u64(ret, 10);
4543
20e4d407
DV		 4544 dev_priv->ips.last_count1 = total_count;
4545 dev_priv->ips.last_time1 = now;
eb48eb00 4546
20e4d407 4547 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4548
4549 return ret;
4550}
4551
f531dcb2
CW		 4552unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4553{
3d13ef2e 4554 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4555 unsigned long val;
4556
3d13ef2e 4557 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4558 return 0;
4559
4560 spin_lock_irq(&mchdev_lock);
4561
4562 val = __i915_chipset_val(dev_priv);
4563
4564 spin_unlock_irq(&mchdev_lock);
4565
4566 return val;
4567}
4568
eb48eb00
DV		 4569unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4570{
4571 unsigned long m, x, b;
4572 u32 tsfs;
4573
4574 tsfs = I915_READ(TSFS);
4575
4576 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4577 x = I915_READ8(TR1);
4578
4579 b = tsfs & TSFS_INTR_MASK;
4580
4581 return ((m * x) / 127) - b;
4582}
4583
4584static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4585{
3d13ef2e 4586 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4587 static const struct v_table {
4588 u16 vd; /* in .1 mil */
4589 u16 vm; /* in .1 mil */
4590 } v_table[] = {
4591 { 0, 0, },
4592 { 375, 0, },
4593 { 500, 0, },
4594 { 625, 0, },
4595 { 750, 0, },
4596 { 875, 0, },
4597 { 1000, 0, },
4598 { 1125, 0, },
4599 { 4125, 3000, },
4600 { 4125, 3000, },
4601 { 4125, 3000, },
4602 { 4125, 3000, },
4603 { 4125, 3000, },
4604 { 4125, 3000, },
4605 { 4125, 3000, },
4606 { 4125, 3000, },
4607 { 4125, 3000, },
4608 { 4125, 3000, },
4609 { 4125, 3000, },
4610 { 4125, 3000, },
4611 { 4125, 3000, },
4612 { 4125, 3000, },
4613 { 4125, 3000, },
4614 { 4125, 3000, },
4615 { 4125, 3000, },
4616 { 4125, 3000, },
4617 { 4125, 3000, },
4618 { 4125, 3000, },
4619 { 4125, 3000, },
4620 { 4125, 3000, },
4621 { 4125, 3000, },
4622 { 4125, 3000, },
4623 { 4250, 3125, },
4624 { 4375, 3250, },
4625 { 4500, 3375, },
4626 { 4625, 3500, },
4627 { 4750, 3625, },
4628 { 4875, 3750, },
4629 { 5000, 3875, },
4630 { 5125, 4000, },
4631 { 5250, 4125, },
4632 { 5375, 4250, },
4633 { 5500, 4375, },
4634 { 5625, 4500, },
4635 { 5750, 4625, },
4636 { 5875, 4750, },
4637 { 6000, 4875, },
4638 { 6125, 5000, },
4639 { 6250, 5125, },
4640 { 6375, 5250, },
4641 { 6500, 5375, },
4642 { 6625, 5500, },
4643 { 6750, 5625, },
4644 { 6875, 5750, },
4645 { 7000, 5875, },
4646 { 7125, 6000, },
4647 { 7250, 6125, },
4648 { 7375, 6250, },
4649 { 7500, 6375, },
4650 { 7625, 6500, },
4651 { 7750, 6625, },
4652 { 7875, 6750, },
4653 { 8000, 6875, },
4654 { 8125, 7000, },
4655 { 8250, 7125, },
4656 { 8375, 7250, },
4657 { 8500, 7375, },
4658 { 8625, 7500, },
4659 { 8750, 7625, },
4660 { 8875, 7750, },
4661 { 9000, 7875, },
4662 { 9125, 8000, },
4663 { 9250, 8125, },
4664 { 9375, 8250, },
4665 { 9500, 8375, },
4666 { 9625, 8500, },
4667 { 9750, 8625, },
4668 { 9875, 8750, },
4669 { 10000, 8875, },
4670 { 10125, 9000, },
4671 { 10250, 9125, },
4672 { 10375, 9250, },
4673 { 10500, 9375, },
4674 { 10625, 9500, },
4675 { 10750, 9625, },
4676 { 10875, 9750, },
4677 { 11000, 9875, },
4678 { 11125, 10000, },
4679 { 11250, 10125, },
4680 { 11375, 10250, },
4681 { 11500, 10375, },
4682 { 11625, 10500, },
4683 { 11750, 10625, },
4684 { 11875, 10750, },
4685 { 12000, 10875, },
4686 { 12125, 11000, },
4687 { 12250, 11125, },
4688 { 12375, 11250, },
4689 { 12500, 11375, },
4690 { 12625, 11500, },
4691 { 12750, 11625, },
4692 { 12875, 11750, },
4693 { 13000, 11875, },
4694 { 13125, 12000, },
4695 { 13250, 12125, },
4696 { 13375, 12250, },
4697 { 13500, 12375, },
4698 { 13625, 12500, },
4699 { 13750, 12625, },
4700 { 13875, 12750, },
4701 { 14000, 12875, },
4702 { 14125, 13000, },
4703 { 14250, 13125, },
4704 { 14375, 13250, },
4705 { 14500, 13375, },
4706 { 14625, 13500, },
4707 { 14750, 13625, },
4708 { 14875, 13750, },
4709 { 15000, 13875, },
4710 { 15125, 14000, },
4711 { 15250, 14125, },
4712 { 15375, 14250, },
4713 { 15500, 14375, },
4714 { 15625, 14500, },
4715 { 15750, 14625, },
4716 { 15875, 14750, },
4717 { 16000, 14875, },
4718 { 16125, 15000, },
4719 };
3d13ef2e 4720 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4721 return v_table[pxvid].vm;
4722 else
4723 return v_table[pxvid].vd;
4724}
4725
02d71956 4726static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 4727{
5ed0bdf2 4728 u64 now, diff, diffms;
eb48eb00
DV		 4729 u32 count;
4730
02d71956 4731 assert_spin_locked(&mchdev_lock);
eb48eb00 4732
5ed0bdf2
TG		 4733 now = ktime_get_raw_ns();
4734 diffms = now - dev_priv->ips.last_time2;
4735 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 4736
4737 /* Don't divide by 0 */
eb48eb00
DV		 4738 if (!diffms)
4739 return;
4740
4741 count = I915_READ(GFXEC);
4742
20e4d407
DV		 4743 if (count < dev_priv->ips.last_count2) {
4744 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4745 diff += count;
4746 } else {
20e4d407 4747 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4748 }
4749
20e4d407
DV		 4750 dev_priv->ips.last_count2 = count;
4751 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4752
4753 /* More magic constants... */
4754 diff = diff * 1181;
4755 diff = div_u64(diff, diffms * 10);
20e4d407 4756 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4757}
4758
02d71956
DV		 4759void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4760{
3d13ef2e
DL		 4761 struct drm_device *dev = dev_priv->dev;
4762
4763 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4764 return;
4765
9270388e 4766 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4767
4768 __i915_update_gfx_val(dev_priv);
4769
9270388e 4770 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4771}
4772
f531dcb2 4773static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4774{
4775 unsigned long t, corr, state1, corr2, state2;
4776 u32 pxvid, ext_v;
4777
02d71956
DV		 4778 assert_spin_locked(&mchdev_lock);
4779
b39fb297 4780 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4781 pxvid = (pxvid >> 24) & 0x7f;
4782 ext_v = pvid_to_extvid(dev_priv, pxvid);
4783
4784 state1 = ext_v;
4785
4786 t = i915_mch_val(dev_priv);
4787
4788 /* Revel in the empirically derived constants */
4789
4790 /* Correction factor in 1/100000 units */
4791 if (t > 80)
4792 corr = ((t * 2349) + 135940);
4793 else if (t >= 50)
4794 corr = ((t * 964) + 29317);
4795 else /* < 50 */
4796 corr = ((t * 301) + 1004);
4797
4798 corr = corr * ((150142 * state1) / 10000 - 78642);
4799 corr /= 100000;
20e4d407 4800 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4801
4802 state2 = (corr2 * state1) / 10000;
4803 state2 /= 100; /* convert to mW */
4804
02d71956 4805 __i915_update_gfx_val(dev_priv);
eb48eb00 4806
20e4d407 4807 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4808}
4809
f531dcb2
CW		 4810unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4811{
3d13ef2e 4812 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4813 unsigned long val;
4814
3d13ef2e 4815 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4816 return 0;
4817
4818 spin_lock_irq(&mchdev_lock);
4819
4820 val = __i915_gfx_val(dev_priv);
4821
4822 spin_unlock_irq(&mchdev_lock);
4823
4824 return val;
4825}
4826
eb48eb00
DV		 4827/**
4828 * i915_read_mch_val - return value for IPS use
4829 *
4830 * Calculate and return a value for the IPS driver to use when deciding whether
4831 * we have thermal and power headroom to increase CPU or GPU power budget.
4832 */
4833unsigned long i915_read_mch_val(void)
4834{
4835 struct drm_i915_private *dev_priv;
4836 unsigned long chipset_val, graphics_val, ret = 0;
4837
9270388e 4838 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4839 if (!i915_mch_dev)
4840 goto out_unlock;
4841 dev_priv = i915_mch_dev;
4842
f531dcb2
CW		 4843 chipset_val = __i915_chipset_val(dev_priv);
4844 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4845
4846 ret = chipset_val + graphics_val;
4847
4848out_unlock:
9270388e 4849 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4850
4851 return ret;
4852}
4853EXPORT_SYMBOL_GPL(i915_read_mch_val);
4854
4855/**
4856 * i915_gpu_raise - raise GPU frequency limit
4857 *
4858 * Raise the limit; IPS indicates we have thermal headroom.
4859 */
4860bool i915_gpu_raise(void)
4861{
4862 struct drm_i915_private *dev_priv;
4863 bool ret = true;
4864
9270388e 4865 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4866 if (!i915_mch_dev) {
4867 ret = false;
4868 goto out_unlock;
4869 }
4870 dev_priv = i915_mch_dev;
4871
20e4d407
DV		 4872 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4873 dev_priv->ips.max_delay--;
eb48eb00
DV		 4874
4875out_unlock:
9270388e 4876 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4877
4878 return ret;
4879}
4880EXPORT_SYMBOL_GPL(i915_gpu_raise);
4881
4882/**
4883 * i915_gpu_lower - lower GPU frequency limit
4884 *
4885 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4886 * frequency maximum.
4887 */
4888bool i915_gpu_lower(void)
4889{
4890 struct drm_i915_private *dev_priv;
4891 bool ret = true;
4892
9270388e 4893 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4894 if (!i915_mch_dev) {
4895 ret = false;
4896 goto out_unlock;
4897 }
4898 dev_priv = i915_mch_dev;
4899
20e4d407
DV		 4900 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4901 dev_priv->ips.max_delay++;
eb48eb00
DV		 4902
4903out_unlock:
9270388e 4904 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4905
4906 return ret;
4907}
4908EXPORT_SYMBOL_GPL(i915_gpu_lower);
4909
4910/**
4911 * i915_gpu_busy - indicate GPU business to IPS
4912 *
4913 * Tell the IPS driver whether or not the GPU is busy.
4914 */
4915bool i915_gpu_busy(void)
4916{
4917 struct drm_i915_private *dev_priv;
a4872ba6 4918 struct intel_engine_cs *ring;
eb48eb00 4919 bool ret = false;
f047e395 4920 int i;
eb48eb00 4921
9270388e 4922 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4923 if (!i915_mch_dev)
4924 goto out_unlock;
4925 dev_priv = i915_mch_dev;
4926
f047e395
CW		 4927 for_each_ring(ring, dev_priv, i)
4928 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4929
4930out_unlock:
9270388e 4931 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4932
4933 return ret;
4934}
4935EXPORT_SYMBOL_GPL(i915_gpu_busy);
4936
4937/**
4938 * i915_gpu_turbo_disable - disable graphics turbo
4939 *
4940 * Disable graphics turbo by resetting the max frequency and setting the
4941 * current frequency to the default.
4942 */
4943bool i915_gpu_turbo_disable(void)
4944{
4945 struct drm_i915_private *dev_priv;
4946 bool ret = true;
4947
9270388e 4948 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4949 if (!i915_mch_dev) {
4950 ret = false;
4951 goto out_unlock;
4952 }
4953 dev_priv = i915_mch_dev;
4954
20e4d407 4955 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4956
20e4d407 4957 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4958 ret = false;
4959
4960out_unlock:
9270388e 4961 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4962
4963 return ret;
4964}
4965EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4966
4967/**
4968 * Tells the intel_ips driver that the i915 driver is now loaded, if
4969 * IPS got loaded first.
4970 *
4971 * This awkward dance is so that neither module has to depend on the
4972 * other in order for IPS to do the appropriate communication of
4973 * GPU turbo limits to i915.
4974 */
4975static void
4976ips_ping_for_i915_load(void)
4977{
4978 void (*link)(void);
4979
4980 link = symbol_get(ips_link_to_i915_driver);
4981 if (link) {
4982 link();
4983 symbol_put(ips_link_to_i915_driver);
4984 }
4985}
4986
4987void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4988{
02d71956
DV		 4989 /* We only register the i915 ips part with intel-ips once everything is
4990 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4991 spin_lock_irq(&mchdev_lock);
eb48eb00 4992 i915_mch_dev = dev_priv;
9270388e 4993 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4994
4995 ips_ping_for_i915_load();
4996}
4997
4998void intel_gpu_ips_teardown(void)
4999{
9270388e 5000 spin_lock_irq(&mchdev_lock);
eb48eb00 5001 i915_mch_dev = NULL;
9270388e 5002 spin_unlock_irq(&mchdev_lock);
eb48eb00 5003}
76c3552f 5004
8090c6b9 5005static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5006{
5007 struct drm_i915_private *dev_priv = dev->dev_private;
5008 u32 lcfuse;
5009 u8 pxw[16];
5010 int i;
5011
5012 /* Disable to program */
5013 I915_WRITE(ECR, 0);
5014 POSTING_READ(ECR);
5015
5016 /* Program energy weights for various events */
5017 I915_WRITE(SDEW, 0x15040d00);
5018 I915_WRITE(CSIEW0, 0x007f0000);
5019 I915_WRITE(CSIEW1, 0x1e220004);
5020 I915_WRITE(CSIEW2, 0x04000004);
5021
5022 for (i = 0; i < 5; i++)
5023 I915_WRITE(PEW + (i * 4), 0);
5024 for (i = 0; i < 3; i++)
5025 I915_WRITE(DEW + (i * 4), 0);
5026
5027 /* Program P-state weights to account for frequency power adjustment */
5028 for (i = 0; i < 16; i++) {
5029 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5030 unsigned long freq = intel_pxfreq(pxvidfreq);
5031 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5032 PXVFREQ_PX_SHIFT;
5033 unsigned long val;
5034
5035 val = vid * vid;
5036 val *= (freq / 1000);
5037 val *= 255;
5038 val /= (127*127*900);
5039 if (val > 0xff)
5040 DRM_ERROR("bad pxval: %ld\n", val);
5041 pxw[i] = val;
5042 }
5043 /* Render standby states get 0 weight */
5044 pxw[14] = 0;
5045 pxw[15] = 0;
5046
5047 for (i = 0; i < 4; i++) {
5048 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5049 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5050 I915_WRITE(PXW + (i * 4), val);
5051 }
5052
5053 /* Adjust magic regs to magic values (more experimental results) */
5054 I915_WRITE(OGW0, 0);
5055 I915_WRITE(OGW1, 0);
5056 I915_WRITE(EG0, 0x00007f00);
5057 I915_WRITE(EG1, 0x0000000e);
5058 I915_WRITE(EG2, 0x000e0000);
5059 I915_WRITE(EG3, 0x68000300);
5060 I915_WRITE(EG4, 0x42000000);
5061 I915_WRITE(EG5, 0x00140031);
5062 I915_WRITE(EG6, 0);
5063 I915_WRITE(EG7, 0);
5064
5065 for (i = 0; i < 8; i++)
5066 I915_WRITE(PXWL + (i * 4), 0);
5067
5068 /* Enable PMON + select events */
5069 I915_WRITE(ECR, 0x80000019);
5070
5071 lcfuse = I915_READ(LCFUSE02);
5072
20e4d407 5073 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5074}
5075
ae48434c
ID		 5076void intel_init_gt_powersave(struct drm_device *dev)
5077{
e6069ca8
ID		 5078 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5079
38807746
D		 5080 if (IS_CHERRYVIEW(dev))
5081 cherryview_init_gt_powersave(dev);
5082 else if (IS_VALLEYVIEW(dev))
4e80519e 5083 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5084}
5085
5086void intel_cleanup_gt_powersave(struct drm_device *dev)
5087{
38807746
D		 5088 if (IS_CHERRYVIEW(dev))
5089 return;
5090 else if (IS_VALLEYVIEW(dev))
4e80519e 5091 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5092}
5093
156c7ca0
JB		 5094/**
5095 * intel_suspend_gt_powersave - suspend PM work and helper threads
5096 * @dev: drm device
5097 *
5098 * We don't want to disable RC6 or other features here, we just want
5099 * to make sure any work we've queued has finished and won't bother
5100 * us while we're suspended.
5101 */
5102void intel_suspend_gt_powersave(struct drm_device *dev)
5103{
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105
5106 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5107 WARN_ON(intel_irqs_enabled(dev_priv));
156c7ca0
JB		 5108
5109 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5110
5111 cancel_work_sync(&dev_priv->rps.work);
b47adc17
D		 5112
5113 /* Force GPU to min freq during suspend */
5114 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5115}
5116
8090c6b9
DV		 5117void intel_disable_gt_powersave(struct drm_device *dev)
5118{
1a01ab3b
JB		 5119 struct drm_i915_private *dev_priv = dev->dev_private;
5120
fd0c0642 5121 /* Interrupts should be disabled already to avoid re-arming. */
9df7575f 5122 WARN_ON(intel_irqs_enabled(dev_priv));
fd0c0642 5123
930ebb46 5124 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5125 ironlake_disable_drps(dev);
930ebb46 5126 ironlake_disable_rc6(dev);
38807746 5127 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5128 intel_suspend_gt_powersave(dev);
e494837a 5129
4fc688ce 5130 mutex_lock(&dev_priv->rps.hw_lock);
38807746
D		 5131 if (IS_CHERRYVIEW(dev))
5132 cherryview_disable_rps(dev);
5133 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5134 valleyview_disable_rps(dev);
5135 else
5136 gen6_disable_rps(dev);
c0951f0c 5137 dev_priv->rps.enabled = false;
4fc688ce 5138 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5139 }
8090c6b9
DV		 5140}
5141
1a01ab3b
JB		 5142static void intel_gen6_powersave_work(struct work_struct *work)
5143{
5144 struct drm_i915_private *dev_priv =
5145 container_of(work, struct drm_i915_private,
5146 rps.delayed_resume_work.work);
5147 struct drm_device *dev = dev_priv->dev;
5148
4fc688ce 5149 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5150
38807746
D		 5151 if (IS_CHERRYVIEW(dev)) {
5152 cherryview_enable_rps(dev);
5153 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5154 valleyview_enable_rps(dev);
6edee7f3
BW		 5155 } else if (IS_BROADWELL(dev)) {
5156 gen8_enable_rps(dev);
c2bc2fc5 5157 __gen6_update_ring_freq(dev);
0a073b84
JB		 5158 } else {
5159 gen6_enable_rps(dev);
c2bc2fc5 5160 __gen6_update_ring_freq(dev);
0a073b84 5161 }
c0951f0c 5162 dev_priv->rps.enabled = true;
4fc688ce 5163 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5164
5165 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5166}
5167
8090c6b9
DV		 5168void intel_enable_gt_powersave(struct drm_device *dev)
5169{
1a01ab3b
JB		 5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171
8090c6b9 5172 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5173 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 5174 ironlake_enable_drps(dev);
5175 ironlake_enable_rc6(dev);
5176 intel_init_emon(dev);
dc1d0136 5177 mutex_unlock(&dev->struct_mutex);
38807746 5178 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5179 /*
5180 * PCU communication is slow and this doesn't need to be
5181 * done at any specific time, so do this out of our fast path
5182 * to make resume and init faster.
c6df39b5
ID		 5183 *
5184 * We depend on the HW RC6 power context save/restore
5185 * mechanism when entering D3 through runtime PM suspend. So
5186 * disable RPM until RPS/RC6 is properly setup. We can only
5187 * get here via the driver load/system resume/runtime resume
5188 * paths, so the _noresume version is enough (and in case of
5189 * runtime resume it's necessary).
1a01ab3b 5190 */
c6df39b5
ID		 5191 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5192 round_jiffies_up_relative(HZ)))
5193 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5194 }
5195}
5196
c6df39b5
ID		 5197void intel_reset_gt_powersave(struct drm_device *dev)
5198{
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5200
5201 dev_priv->rps.enabled = false;
5202 intel_enable_gt_powersave(dev);
5203}
5204
3107bd48
DV		 5205static void ibx_init_clock_gating(struct drm_device *dev)
5206{
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209 /*
5210 * On Ibex Peak and Cougar Point, we need to disable clock
5211 * gating for the panel power sequencer or it will fail to
5212 * start up when no ports are active.
5213 */
5214 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5215}
5216
0e088b8f
VS		 5217static void g4x_disable_trickle_feed(struct drm_device *dev)
5218{
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 int pipe;
5221
055e393f 5222 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5223 I915_WRITE(DSPCNTR(pipe),
5224 I915_READ(DSPCNTR(pipe)) |
5225 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5226 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5227 }
5228}
5229
017636cc
VS		 5230static void ilk_init_lp_watermarks(struct drm_device *dev)
5231{
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233
5234 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5235 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5236 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5237
5238 /*
5239 * Don't touch WM1S_LP_EN here.
5240 * Doing so could cause underruns.
5241 */
5242}
5243
1fa61106 5244static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5245{
5246 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5247 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5248
f1e8fa56
DL		 5249 /*
5250 * Required for FBC
5251 * WaFbcDisableDpfcClockGating:ilk
5252 */
4d47e4f5
DL		 5253 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5254 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5255 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5256
5257 I915_WRITE(PCH_3DCGDIS0,
5258 MARIUNIT_CLOCK_GATE_DISABLE |
5259 SVSMUNIT_CLOCK_GATE_DISABLE);
5260 I915_WRITE(PCH_3DCGDIS1,
5261 VFMUNIT_CLOCK_GATE_DISABLE);
5262
6f1d69b0
ED		 5263 /*
5264 * According to the spec the following bits should be set in
5265 * order to enable memory self-refresh
5266 * The bit 22/21 of 0x42004
5267 * The bit 5 of 0x42020
5268 * The bit 15 of 0x45000
5269 */
5270 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5271 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5272 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5273 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5274 I915_WRITE(DISP_ARB_CTL,
5275 (I915_READ(DISP_ARB_CTL) |
5276 DISP_FBC_WM_DIS));
017636cc
VS		 5277
5278 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5279
5280 /*
5281 * Based on the document from hardware guys the following bits
5282 * should be set unconditionally in order to enable FBC.
5283 * The bit 22 of 0x42000
5284 * The bit 22 of 0x42004
5285 * The bit 7,8,9 of 0x42020.
5286 */
5287 if (IS_IRONLAKE_M(dev)) {
4bb35334 5288 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5289 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5290 I915_READ(ILK_DISPLAY_CHICKEN1) |
5291 ILK_FBCQ_DIS);
5292 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5293 I915_READ(ILK_DISPLAY_CHICKEN2) |
5294 ILK_DPARB_GATE);
6f1d69b0
ED		 5295 }
5296
4d47e4f5
DL		 5297 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5298
6f1d69b0
ED		 5299 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5300 I915_READ(ILK_DISPLAY_CHICKEN2) |
5301 ILK_ELPIN_409_SELECT);
5302 I915_WRITE(_3D_CHICKEN2,
5303 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5304 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5305
ecdb4eb7 5306 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5307 I915_WRITE(CACHE_MODE_0,
5308 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5309
4e04632e
AG		 5310 /* WaDisable_RenderCache_OperationalFlush:ilk */
5311 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5312
0e088b8f 5313 g4x_disable_trickle_feed(dev);
bdad2b2f 5314
3107bd48
DV		 5315 ibx_init_clock_gating(dev);
5316}
5317
5318static void cpt_init_clock_gating(struct drm_device *dev)
5319{
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 int pipe;
3f704fa2 5322 uint32_t val;
3107bd48
DV		 5323
5324 /*
5325 * On Ibex Peak and Cougar Point, we need to disable clock
5326 * gating for the panel power sequencer or it will fail to
5327 * start up when no ports are active.
5328 */
cd664078
JB		 5329 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5330 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5331 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5332 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5333 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5334 /* The below fixes the weird display corruption, a few pixels shifted
5335 * downward, on (only) LVDS of some HP laptops with IVY.
5336 */
055e393f 5337 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5338 val = I915_READ(TRANS_CHICKEN2(pipe));
5339 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5340 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5341 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5342 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5343 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5344 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5345 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5346 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5347 }
3107bd48 5348 /* WADP0ClockGatingDisable */
055e393f 5349 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5350 I915_WRITE(TRANS_CHICKEN1(pipe),
5351 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5352 }
6f1d69b0
ED		 5353}
5354
1d7aaa0c
DV		 5355static void gen6_check_mch_setup(struct drm_device *dev)
5356{
5357 struct drm_i915_private *dev_priv = dev->dev_private;
5358 uint32_t tmp;
5359
5360 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5361 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5362 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5363 tmp);
1d7aaa0c
DV		 5364}
5365
1fa61106 5366static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5367{
5368 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5369 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5370
231e54f6 5371 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5372
5373 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5374 I915_READ(ILK_DISPLAY_CHICKEN2) |
5375 ILK_ELPIN_409_SELECT);
5376
ecdb4eb7 5377 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5378 I915_WRITE(_3D_CHICKEN,
5379 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5380
ecdb4eb7 5381 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5382 if (IS_SNB_GT1(dev))
5383 I915_WRITE(GEN6_GT_MODE,
5384 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5385
4e04632e
AG		 5386 /* WaDisable_RenderCache_OperationalFlush:snb */
5387 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5388
8d85d272
VS		 5389 /*
5390 * BSpec recoomends 8x4 when MSAA is used,
5391 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5392 *
5393 * Note that PS/WM thread counts depend on the WIZ hashing
5394 * disable bit, which we don't touch here, but it's good
5395 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5396 */
5397 I915_WRITE(GEN6_GT_MODE,
5398 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5399
017636cc 5400 ilk_init_lp_watermarks(dev);
6f1d69b0 5401
6f1d69b0 5402 I915_WRITE(CACHE_MODE_0,
50743298 5403 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5404
5405 I915_WRITE(GEN6_UCGCTL1,
5406 I915_READ(GEN6_UCGCTL1) |
5407 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5408 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5409
5410 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5411 * gating disable must be set. Failure to set it results in
5412 * flickering pixels due to Z write ordering failures after
5413 * some amount of runtime in the Mesa "fire" demo, and Unigine
5414 * Sanctuary and Tropics, and apparently anything else with
5415 * alpha test or pixel discard.
5416 *
5417 * According to the spec, bit 11 (RCCUNIT) must also be set,
5418 * but we didn't debug actual testcases to find it out.
0f846f81 5419 *
ef59318c
VS		 5420 * WaDisableRCCUnitClockGating:snb
5421 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5422 */
5423 I915_WRITE(GEN6_UCGCTL2,
5424 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5425 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5426
5eb146dd 5427 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5428 I915_WRITE(_3D_CHICKEN3,
5429 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5430
e927ecde
VS		 5431 /*
5432 * Bspec says:
5433 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5434 * 3DSTATE_SF number of SF output attributes is more than 16."
5435 */
5436 I915_WRITE(_3D_CHICKEN3,
5437 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5438
6f1d69b0
ED		 5439 /*
5440 * According to the spec the following bits should be
5441 * set in order to enable memory self-refresh and fbc:
5442 * The bit21 and bit22 of 0x42000
5443 * The bit21 and bit22 of 0x42004
5444 * The bit5 and bit7 of 0x42020
5445 * The bit14 of 0x70180
5446 * The bit14 of 0x71180
4bb35334
DL		 5447 *
5448 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5449 */
5450 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5451 I915_READ(ILK_DISPLAY_CHICKEN1) |
5452 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5453 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5454 I915_READ(ILK_DISPLAY_CHICKEN2) |
5455 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5456 I915_WRITE(ILK_DSPCLK_GATE_D,
5457 I915_READ(ILK_DSPCLK_GATE_D) |
5458 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5459 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5460
0e088b8f 5461 g4x_disable_trickle_feed(dev);
f8f2ac9a 5462
3107bd48 5463 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5464
5465 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5466}
5467
5468static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5469{
5470 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5471
3aad9059 5472 /*
46680e0a 5473 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 5474 *
5475 * This actually overrides the dispatch
5476 * mode for all thread types.
5477 */
6f1d69b0
ED		 5478 reg &= ~GEN7_FF_SCHED_MASK;
5479 reg |= GEN7_FF_TS_SCHED_HW;
5480 reg |= GEN7_FF_VS_SCHED_HW;
5481 reg |= GEN7_FF_DS_SCHED_HW;
5482
5483 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5484}
5485
17a303ec
PZ		 5486static void lpt_init_clock_gating(struct drm_device *dev)
5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489
5490 /*
5491 * TODO: this bit should only be enabled when really needed, then
5492 * disabled when not needed anymore in order to save power.
5493 */
5494 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5495 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5496 I915_READ(SOUTH_DSPCLK_GATE_D) |
5497 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5498
5499 /* WADPOClockGatingDisable:hsw */
5500 I915_WRITE(_TRANSA_CHICKEN1,
5501 I915_READ(_TRANSA_CHICKEN1) |
5502 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5503}
5504
7d708ee4
ID		 5505static void lpt_suspend_hw(struct drm_device *dev)
5506{
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5508
5509 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5510 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5511
5512 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5513 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5514 }
5515}
5516
1020a5c2
BW		 5517static void gen8_init_clock_gating(struct drm_device *dev)
5518{
5519 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5520 enum pipe pipe;
1020a5c2
BW		 5521
5522 I915_WRITE(WM3_LP_ILK, 0);
5523 I915_WRITE(WM2_LP_ILK, 0);
5524 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5525
5526 /* FIXME(BDW): Check all the w/a, some might only apply to
5527 * pre-production hw. */
5528
c8966e10
KG		 5529 /* WaDisablePartialInstShootdown:bdw */
5530 I915_WRITE(GEN8_ROW_CHICKEN,
5531 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5532
1411e6a5
KG		 5533 /* WaDisableThreadStallDopClockGating:bdw */
5534 /* FIXME: Unclear whether we really need this on production bdw. */
5535 I915_WRITE(GEN8_ROW_CHICKEN,
5536 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5537
4167e32c
DL		 5538 /*
5539 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5540 * pre-production hardware
5541 */
fd392b60
BW		 5542 I915_WRITE(HALF_SLICE_CHICKEN3,
5543 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5544 I915_WRITE(HALF_SLICE_CHICKEN3,
5545 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5546 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5547
7f88da0c 5548 I915_WRITE(_3D_CHICKEN3,
b3f9ad93 5549 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)));
7f88da0c 5550
a75f3628
BW		 5551 I915_WRITE(COMMON_SLICE_CHICKEN2,
5552 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5553
4c2e7a5f
BW		 5554 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5555 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5556
242a4018
BW		 5557 /* WaDisableDopClockGating:bdw May not be needed for production */
5558 I915_WRITE(GEN7_ROW_CHICKEN2,
5559 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5560
ab57fff1 5561 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5562 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5563
ab57fff1 5564 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5565 I915_WRITE(CHICKEN_PAR1_1,
5566 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5567
ab57fff1 5568 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 5569 for_each_pipe(dev_priv, pipe) {
07d27e20 5570 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5571 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5572 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5573 }
63801f21
BW		 5574
5575 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5576 * workaround for for a possible hang in the unlikely event a TLB
5577 * invalidation occurs during a PSD flush.
5578 */
5579 I915_WRITE(HDC_CHICKEN0,
5580 I915_READ(HDC_CHICKEN0) |
5581 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5582
5583 /* WaVSRefCountFullforceMissDisable:bdw */
5584 /* WaDSRefCountFullforceMissDisable:bdw */
5585 I915_WRITE(GEN7_FF_THREAD_MODE,
5586 I915_READ(GEN7_FF_THREAD_MODE) &
5587 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5588
5589 /*
5590 * BSpec recommends 8x4 when MSAA is used,
5591 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5592 *
5593 * Note that PS/WM thread counts depend on the WIZ hashing
5594 * disable bit, which we don't touch here, but it's good
5595 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5596 */
5597 I915_WRITE(GEN7_GT_MODE,
5598 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5599
5600 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5601 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5602
5603 /* WaDisableSDEUnitClockGating:bdw */
5604 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5605 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5606
5607 /* Wa4x4STCOptimizationDisable:bdw */
5608 I915_WRITE(CACHE_MODE_1,
5609 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5610}
5611
cad2a2d7
ED		 5612static void haswell_init_clock_gating(struct drm_device *dev)
5613{
5614 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5615
017636cc 5616 ilk_init_lp_watermarks(dev);
cad2a2d7 5617
f3fc4884
FJ		 5618 /* L3 caching of data atomics doesn't work -- disable it. */
5619 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5620 I915_WRITE(HSW_ROW_CHICKEN3,
5621 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5622
ecdb4eb7 5623 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5624 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5625 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5626 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5627
e36ea7ff
VS		 5628 /* WaVSRefCountFullforceMissDisable:hsw */
5629 I915_WRITE(GEN7_FF_THREAD_MODE,
5630 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5631
4e04632e
AG		 5632 /* WaDisable_RenderCache_OperationalFlush:hsw */
5633 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5634
fe27c606
CW		 5635 /* enable HiZ Raw Stall Optimization */
5636 I915_WRITE(CACHE_MODE_0_GEN7,
5637 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5638
ecdb4eb7 5639 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5640 I915_WRITE(CACHE_MODE_1,
5641 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5642
a12c4967
VS		 5643 /*
5644 * BSpec recommends 8x4 when MSAA is used,
5645 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5646 *
5647 * Note that PS/WM thread counts depend on the WIZ hashing
5648 * disable bit, which we don't touch here, but it's good
5649 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5650 */
5651 I915_WRITE(GEN7_GT_MODE,
5652 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5653
ecdb4eb7 5654 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5655 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5656
90a88643
PZ		 5657 /* WaRsPkgCStateDisplayPMReq:hsw */
5658 I915_WRITE(CHICKEN_PAR1_1,
5659 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5660
17a303ec 5661 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5662}
5663
1fa61106 5664static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5665{
5666 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5667 uint32_t snpcr;
6f1d69b0 5668
017636cc 5669 ilk_init_lp_watermarks(dev);
6f1d69b0 5670
231e54f6 5671 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5672
ecdb4eb7 5673 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5674 I915_WRITE(_3D_CHICKEN3,
5675 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5676
ecdb4eb7 5677 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5678 I915_WRITE(IVB_CHICKEN3,
5679 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5680 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5681
ecdb4eb7 5682 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5683 if (IS_IVB_GT1(dev))
5684 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5685 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5686
4e04632e
AG		 5687 /* WaDisable_RenderCache_OperationalFlush:ivb */
5688 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5689
ecdb4eb7 5690 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5691 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5692 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5693
ecdb4eb7 5694 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5695 I915_WRITE(GEN7_L3CNTLREG1,
5696 GEN7_WA_FOR_GEN7_L3_CONTROL);
5697 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5698 GEN7_WA_L3_CHICKEN_MODE);
5699 if (IS_IVB_GT1(dev))
5700 I915_WRITE(GEN7_ROW_CHICKEN2,
5701 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5702 else {
5703 /* must write both registers */
5704 I915_WRITE(GEN7_ROW_CHICKEN2,
5705 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5706 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5707 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5708 }
6f1d69b0 5709
ecdb4eb7 5710 /* WaForceL3Serialization:ivb */
61939d97
JB		 5711 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5712 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5713
1b80a19a 5714 /*
0f846f81 5715 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5716 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5717 */
5718 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5719 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5720
ecdb4eb7 5721 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5722 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5723 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5724 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5725
0e088b8f 5726 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5727
5728 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5729
22721343
CW		 5730 if (0) { /* causes HiZ corruption on ivb:gt1 */
5731 /* enable HiZ Raw Stall Optimization */
5732 I915_WRITE(CACHE_MODE_0_GEN7,
5733 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5734 }
116f2b6d 5735
ecdb4eb7 5736 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5737 I915_WRITE(CACHE_MODE_1,
5738 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5739
a607c1a4
VS		 5740 /*
5741 * BSpec recommends 8x4 when MSAA is used,
5742 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5743 *
5744 * Note that PS/WM thread counts depend on the WIZ hashing
5745 * disable bit, which we don't touch here, but it's good
5746 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5747 */
5748 I915_WRITE(GEN7_GT_MODE,
5749 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5750
20848223
BW		 5751 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5752 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5753 snpcr |= GEN6_MBC_SNPCR_MED;
5754 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5755
ab5c608b
BW		 5756 if (!HAS_PCH_NOP(dev))
5757 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5758
5759 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5760}
5761
1fa61106 5762static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5763{
5764 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5765 u32 val;
5766
5767 mutex_lock(&dev_priv->rps.hw_lock);
5768 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5769 mutex_unlock(&dev_priv->rps.hw_lock);
5770 switch ((val >> 6) & 3) {
5771 case 0:
f64a28a7 5772 case 1:
f6d51948 5773 dev_priv->mem_freq = 800;
85b1d7b3 5774 break;
f64a28a7 5775 case 2:
f6d51948 5776 dev_priv->mem_freq = 1066;
85b1d7b3 5777 break;
f64a28a7 5778 case 3:
2325991e 5779 dev_priv->mem_freq = 1333;
f64a28a7 5780 break;
85b1d7b3
JB		 5781 }
5782 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5783
d7fe0cc0 5784 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5785
ecdb4eb7 5786 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5787 I915_WRITE(_3D_CHICKEN3,
5788 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5789
ecdb4eb7 5790 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5791 I915_WRITE(IVB_CHICKEN3,
5792 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5793 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5794
fad7d36e 5795 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5796 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5797 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5798 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5799 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5800
4e04632e
AG		 5801 /* WaDisable_RenderCache_OperationalFlush:vlv */
5802 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5803
ecdb4eb7 5804 /* WaForceL3Serialization:vlv */
61939d97
JB		 5805 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5806 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5807
ecdb4eb7 5808 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5809 I915_WRITE(GEN7_ROW_CHICKEN2,
5810 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5811
ecdb4eb7 5812 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5813 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5814 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5815 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5816
46680e0a
VS		 5817 gen7_setup_fixed_func_scheduler(dev_priv);
5818
3c0edaeb 5819 /*
0f846f81 5820 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5821 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5822 */
5823 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5824 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5825
c98f5062
AG		 5826 /* WaDisableL3Bank2xClockGate:vlv
5827 * Disabling L3 clock gating- MMIO 940c[25] = 1
5828 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5829 I915_WRITE(GEN7_UCGCTL4,
5830 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 5831
e0d8d59b 5832 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5833
afd58e79
VS		 5834 /*
5835 * BSpec says this must be set, even though
5836 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5837 */
6b26c86d
DV		 5838 I915_WRITE(CACHE_MODE_1,
5839 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5840
031994ee
VS		 5841 /*
5842 * WaIncreaseL3CreditsForVLVB0:vlv
5843 * This is the hardware default actually.
5844 */
5845 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5846
2d809570 5847 /*
ecdb4eb7 5848 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5849 * Disable clock gating on th GCFG unit to prevent a delay
5850 * in the reporting of vblank events.
5851 */
7a0d1eed 5852 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5853}
5854
a4565da8
VS		 5855static void cherryview_init_clock_gating(struct drm_device *dev)
5856{
5857 struct drm_i915_private *dev_priv = dev->dev_private;
67c3bf6f
D		 5858 u32 val;
5859
5860 mutex_lock(&dev_priv->rps.hw_lock);
5861 val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
5862 mutex_unlock(&dev_priv->rps.hw_lock);
5863 switch ((val >> 2) & 0x7) {
5864 case 0:
5865 case 1:
5866 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
5867 dev_priv->mem_freq = 1600;
5868 break;
5869 case 2:
5870 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
5871 dev_priv->mem_freq = 1600;
5872 break;
5873 case 3:
5874 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
5875 dev_priv->mem_freq = 2000;
5876 break;
5877 case 4:
5878 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
5879 dev_priv->mem_freq = 1600;
5880 break;
5881 case 5:
5882 dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
5883 dev_priv->mem_freq = 1600;
5884 break;
5885 }
5886 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
a4565da8
VS		 5887
5888 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5889
5890 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5891
5892 /* WaDisablePartialInstShootdown:chv */
5893 I915_WRITE(GEN8_ROW_CHICKEN,
5894 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5895
5896 /* WaDisableThreadStallDopClockGating:chv */
5897 I915_WRITE(GEN8_ROW_CHICKEN,
5898 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
232ce337
VS		 5899
5900 /* WaVSRefCountFullforceMissDisable:chv */
5901 /* WaDSRefCountFullforceMissDisable:chv */
5902 I915_WRITE(GEN7_FF_THREAD_MODE,
5903 I915_READ(GEN7_FF_THREAD_MODE) &
5904 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 5905
5906 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5907 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5908 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 5909
5910 /* WaDisableCSUnitClockGating:chv */
5911 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5912 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 5913
5914 /* WaDisableSDEUnitClockGating:chv */
5915 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5916 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
e0d34ce7
RB		 5917
5918 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5919 I915_WRITE(HALF_SLICE_CHICKEN3,
5920 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
e4443e45
VS		 5921
5922 /* WaDisableGunitClockGating:chv (pre-production hw) */
5923 I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5924 GINT_DIS);
5925
5926 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5927 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5928 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5929
5930 /* WaDisableDopClockGating:chv (pre-production hw) */
5931 I915_WRITE(GEN7_ROW_CHICKEN2,
5932 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5933 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5934 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 5935}
5936
1fa61106 5937static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5938{
5939 struct drm_i915_private *dev_priv = dev->dev_private;
5940 uint32_t dspclk_gate;
5941
5942 I915_WRITE(RENCLK_GATE_D1, 0);
5943 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5944 GS_UNIT_CLOCK_GATE_DISABLE |
5945 CL_UNIT_CLOCK_GATE_DISABLE);
5946 I915_WRITE(RAMCLK_GATE_D, 0);
5947 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5948 OVRUNIT_CLOCK_GATE_DISABLE |
5949 OVCUNIT_CLOCK_GATE_DISABLE;
5950 if (IS_GM45(dev))
5951 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5952 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5953
5954 /* WaDisableRenderCachePipelinedFlush */
5955 I915_WRITE(CACHE_MODE_0,
5956 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5957
4e04632e
AG		 5958 /* WaDisable_RenderCache_OperationalFlush:g4x */
5959 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5960
0e088b8f 5961 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5962}
5963
1fa61106 5964static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5965{
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967
5968 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5969 I915_WRITE(RENCLK_GATE_D2, 0);
5970 I915_WRITE(DSPCLK_GATE_D, 0);
5971 I915_WRITE(RAMCLK_GATE_D, 0);
5972 I915_WRITE16(DEUC, 0);
20f94967
VS		 5973 I915_WRITE(MI_ARB_STATE,
5974 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5975
5976 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5977 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5978}
5979
1fa61106 5980static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5981{
5982 struct drm_i915_private *dev_priv = dev->dev_private;
5983
5984 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5985 I965_RCC_CLOCK_GATE_DISABLE |
5986 I965_RCPB_CLOCK_GATE_DISABLE |
5987 I965_ISC_CLOCK_GATE_DISABLE |
5988 I965_FBC_CLOCK_GATE_DISABLE);
5989 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5990 I915_WRITE(MI_ARB_STATE,
5991 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5992
5993 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5994 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5995}
5996
1fa61106 5997static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5998{
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 u32 dstate = I915_READ(D_STATE);
6001
6002 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6003 DSTATE_DOT_CLOCK_GATING;
6004 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6005
6006 if (IS_PINEVIEW(dev))
6007 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6008
6009 /* IIR "flip pending" means done if this bit is set */
6010 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6011
6012 /* interrupts should cause a wake up from C3 */
3299254f 6013 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6014
6015 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6016 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6f1d69b0
ED		 6017}
6018
1fa61106 6019static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6020{
6021 struct drm_i915_private *dev_priv = dev->dev_private;
6022
6023 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6024
6025 /* interrupts should cause a wake up from C3 */
6026 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6027 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6f1d69b0
ED		 6028}
6029
1fa61106 6030static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6031{
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033
6034 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6035}
6036
6f1d69b0
ED		 6037void intel_init_clock_gating(struct drm_device *dev)
6038{
6039 struct drm_i915_private *dev_priv = dev->dev_private;
6040
6041 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6042}
6043
7d708ee4
ID		 6044void intel_suspend_hw(struct drm_device *dev)
6045{
6046 if (HAS_PCH_LPT(dev))
6047 lpt_suspend_hw(dev);
6048}
6049
c1ca727f
ID		 6050#define for_each_power_well(i, power_well, domain_mask, power_domains) \
6051 for (i = 0; \
6052 i < (power_domains)->power_well_count && \
6053 ((power_well) = &(power_domains)->power_wells[i]); \
6054 i++) \
6055 if ((power_well)->domains & (domain_mask))
6056
6057#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
6058 for (i = (power_domains)->power_well_count - 1; \
6059 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
6060 i--) \
6061 if ((power_well)->domains & (domain_mask))
6062
15d199ea
PZ		 6063/**
6064 * We should only use the power well if we explicitly asked the hardware to
6065 * enable it, so check if it's enabled and also check if we've requested it to
6066 * be enabled.
6067 */
da7e29bd 6068static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 6069 struct i915_power_well *power_well)
6070{
c1ca727f
ID		 6071 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6072 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
6073}
6074
bfafe93a
ID		 6075bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
6076 enum intel_display_power_domain domain)
ddf9c536 6077{
ddf9c536 6078 struct i915_power_domains *power_domains;
b8c000d9
ID		 6079 struct i915_power_well *power_well;
6080 bool is_enabled;
6081 int i;
6082
6083 if (dev_priv->pm.suspended)
6084 return false;
ddf9c536
ID		 6085
6086 power_domains = &dev_priv->power_domains;
bfafe93a 6087
b8c000d9 6088 is_enabled = true;
bfafe93a 6089
b8c000d9
ID		 6090 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6091 if (power_well->always_on)
6092 continue;
ddf9c536 6093
bfafe93a 6094 if (!power_well->hw_enabled) {
b8c000d9
ID		 6095 is_enabled = false;
6096 break;
6097 }
6098 }
bfafe93a 6099
b8c000d9 6100 return is_enabled;
ddf9c536
ID		 6101}
6102
da7e29bd 6103bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 6104 enum intel_display_power_domain domain)
15d199ea 6105{
c1ca727f 6106 struct i915_power_domains *power_domains;
bfafe93a 6107 bool ret;
882244a3 6108
c1ca727f
ID		 6109 power_domains = &dev_priv->power_domains;
6110
c1ca727f 6111 mutex_lock(&power_domains->lock);
bfafe93a 6112 ret = intel_display_power_enabled_unlocked(dev_priv, domain);
c1ca727f
ID		 6113 mutex_unlock(&power_domains->lock);
6114
bfafe93a 6115 return ret;
15d199ea
PZ		 6116}
6117
93c73e8c
ID		 6118/*
6119 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6120 * when not needed anymore. We have 4 registers that can request the power well
6121 * to be enabled, and it will only be disabled if none of the registers is
6122 * requesting it to be enabled.
6123 */
d5e8fdc8
PZ		 6124static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
6125{
6126 struct drm_device *dev = dev_priv->dev;
d5e8fdc8 6127
f9dcb0df
PZ		 6128 /*
6129 * After we re-enable the power well, if we touch VGA register 0x3d5
6130 * we'll get unclaimed register interrupts. This stops after we write
6131 * anything to the VGA MSR register. The vgacon module uses this
6132 * register all the time, so if we unbind our driver and, as a
6133 * consequence, bind vgacon, we'll get stuck in an infinite loop at
6134 * console_unlock(). So make here we touch the VGA MSR register, making
6135 * sure vgacon can keep working normally without triggering interrupts
6136 * and error messages.
6137 */
6138 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6139 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
6140 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6141
d49bdb0e
PZ		 6142 if (IS_BROADWELL(dev))
6143 gen8_irq_power_well_post_enable(dev_priv);
d5e8fdc8
PZ		 6144}
6145
da7e29bd 6146static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 6147 struct i915_power_well *power_well, bool enable)
d0d3e513 6148{
fa42e23c
PZ		 6149 bool is_enabled, enable_requested;
6150 uint32_t tmp;
d0d3e513 6151
fa42e23c 6152 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 6153 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
6154 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 6155
fa42e23c
PZ		 6156 if (enable) {
6157 if (!enable_requested)
6aedd1f5
PZ		 6158 I915_WRITE(HSW_PWR_WELL_DRIVER,
6159 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 6160
fa42e23c
PZ		 6161 if (!is_enabled) {
6162 DRM_DEBUG_KMS("Enabling power well\n");
6163 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 6164 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 6165 DRM_ERROR("Timeout enabling power well\n");
6166 }
596cc11e 6167
d5e8fdc8 6168 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 6169 } else {
6170 if (enable_requested) {
6171 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 6172 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 6173 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 6174 }
6175 }
fa42e23c 6176}
d0d3e513 6177
c6cb582e
ID		 6178static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
6179 struct i915_power_well *power_well)
6180{
6181 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
6182
6183 /*
6184 * We're taking over the BIOS, so clear any requests made by it since
6185 * the driver is in charge now.
6186 */
6187 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
6188 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
6189}
6190
6191static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
6192 struct i915_power_well *power_well)
6193{
c6cb582e
ID		 6194 hsw_set_power_well(dev_priv, power_well, true);
6195}
6196
6197static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
6198 struct i915_power_well *power_well)
6199{
6200 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 6201}
6202
a45f4466
ID		 6203static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
6204 struct i915_power_well *power_well)
6205{
6206}
6207
6208static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
6209 struct i915_power_well *power_well)
6210{
6211 return true;
6212}
6213
d2011dc8
VS		 6214static void vlv_set_power_well(struct drm_i915_private *dev_priv,
6215 struct i915_power_well *power_well, bool enable)
77961eb9 6216{
d2011dc8 6217 enum punit_power_well power_well_id = power_well->data;
77961eb9
ID		 6218 u32 mask;
6219 u32 state;
6220 u32 ctrl;
6221
6222 mask = PUNIT_PWRGT_MASK(power_well_id);
6223 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
6224 PUNIT_PWRGT_PWR_GATE(power_well_id);
6225
6226 mutex_lock(&dev_priv->rps.hw_lock);
6227
6228#define COND \
6229 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6230
6231 if (COND)
6232 goto out;
6233
6234 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
6235 ctrl &= ~mask;
6236 ctrl |= state;
6237 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
6238
6239 if (wait_for(COND, 100))
6240 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6241 state,
6242 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
6243
6244#undef COND
6245
6246out:
6247 mutex_unlock(&dev_priv->rps.hw_lock);
6248}
6249
6250static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
6251 struct i915_power_well *power_well)
6252{
6253 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
6254}
6255
6256static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
6257 struct i915_power_well *power_well)
6258{
6259 vlv_set_power_well(dev_priv, power_well, true);
6260}
6261
6262static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
6263 struct i915_power_well *power_well)
6264{
6265 vlv_set_power_well(dev_priv, power_well, false);
6266}
6267
6268static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
6269 struct i915_power_well *power_well)
6270{
6271 int power_well_id = power_well->data;
6272 bool enabled = false;
6273 u32 mask;
6274 u32 state;
6275 u32 ctrl;
6276
6277 mask = PUNIT_PWRGT_MASK(power_well_id);
6278 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
6279
6280 mutex_lock(&dev_priv->rps.hw_lock);
6281
6282 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
6283 /*
6284 * We only ever set the power-on and power-gate states, anything
6285 * else is unexpected.
6286 */
6287 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
6288 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
6289 if (state == ctrl)
6290 enabled = true;
6291
6292 /*
6293 * A transient state at this point would mean some unexpected party
6294 * is poking at the power controls too.
6295 */
6296 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
6297 WARN_ON(ctrl != state);
6298
6299 mutex_unlock(&dev_priv->rps.hw_lock);
6300
6301 return enabled;
6302}
6303
6304static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
6305 struct i915_power_well *power_well)
6306{
6307 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6308
6309 vlv_set_power_well(dev_priv, power_well, true);
6310
6311 spin_lock_irq(&dev_priv->irq_lock);
6312 valleyview_enable_display_irqs(dev_priv);
6313 spin_unlock_irq(&dev_priv->irq_lock);
6314
6315 /*
0d116a29
ID		 6316 * During driver initialization/resume we can avoid restoring the
6317 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 6318 */
0d116a29
ID		 6319 if (dev_priv->power_domains.initializing)
6320 return;
6321
6322 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 6323
6324 i915_redisable_vga_power_on(dev_priv->dev);
6325}
6326
6327static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
6328 struct i915_power_well *power_well)
6329{
77961eb9
ID		 6330 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
6331
6332 spin_lock_irq(&dev_priv->irq_lock);
77961eb9
ID		 6333 valleyview_disable_display_irqs(dev_priv);
6334 spin_unlock_irq(&dev_priv->irq_lock);
6335
77961eb9
ID		 6336 vlv_set_power_well(dev_priv, power_well, false);
6337}
6338
aa519f23
VS		 6339static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6340 struct i915_power_well *power_well)
6341{
6342 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6343
6344 /*
6345 * Enable the CRI clock source so we can get at the
6346 * display and the reference clock for VGA
6347 * hotplug / manual detection.
6348 */
6349 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6350 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6351 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6352
6353 vlv_set_power_well(dev_priv, power_well, true);
6354
6355 /*
6356 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6357 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6358 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6359 * b. The other bits such as sfr settings / modesel may all
6360 * be set to 0.
6361 *
6362 * This should only be done on init and resume from S3 with
6363 * both PLLs disabled, or we risk losing DPIO and PLL
6364 * synchronization.
6365 */
6366 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
6367}
6368
6369static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6370 struct i915_power_well *power_well)
6371{
aa519f23
VS		 6372 enum pipe pipe;
6373
6374 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
6375
055e393f 6376 for_each_pipe(dev_priv, pipe)
aa519f23
VS		 6377 assert_pll_disabled(dev_priv, pipe);
6378
6379 /* Assert common reset */
6380 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
6381
6382 vlv_set_power_well(dev_priv, power_well, false);
6383}
6384
5d6f7ea7
VS		 6385static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
6386 struct i915_power_well *power_well)
6387{
6388 enum dpio_phy phy;
6389
6390 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6391 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6392
6393 /*
6394 * Enable the CRI clock source so we can get at the
6395 * display and the reference clock for VGA
6396 * hotplug / manual detection.
6397 */
6398 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6399 phy = DPIO_PHY0;
6400 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6401 DPLL_REFA_CLK_ENABLE_VLV);
6402 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
6403 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6404 } else {
6405 phy = DPIO_PHY1;
6406 I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) |
6407 DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV);
6408 }
6409 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
6410 vlv_set_power_well(dev_priv, power_well, true);
6411
6412 /* Poll for phypwrgood signal */
6413 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
6414 DRM_ERROR("Display PHY %d is not power up\n", phy);
6415
efd814b7
VS		 6416 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) |
6417 PHY_COM_LANE_RESET_DEASSERT(phy));
5d6f7ea7
VS		 6418}
6419
6420static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
6421 struct i915_power_well *power_well)
6422{
6423 enum dpio_phy phy;
6424
6425 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
6426 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
6427
6428 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
6429 phy = DPIO_PHY0;
6430 assert_pll_disabled(dev_priv, PIPE_A);
6431 assert_pll_disabled(dev_priv, PIPE_B);
6432 } else {
6433 phy = DPIO_PHY1;
6434 assert_pll_disabled(dev_priv, PIPE_C);
6435 }
6436
efd814b7
VS		 6437 I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) &
6438 ~PHY_COM_LANE_RESET_DEASSERT(phy));
5d6f7ea7
VS		 6439
6440 vlv_set_power_well(dev_priv, power_well, false);
6441}
6442
26972b0a
VS		 6443static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
6444 struct i915_power_well *power_well)
6445{
6446 enum pipe pipe = power_well->data;
6447 bool enabled;
6448 u32 state, ctrl;
6449
6450 mutex_lock(&dev_priv->rps.hw_lock);
6451
6452 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
6453 /*
6454 * We only ever set the power-on and power-gate states, anything
6455 * else is unexpected.
6456 */
6457 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
6458 enabled = state == DP_SSS_PWR_ON(pipe);
6459
6460 /*
6461 * A transient state at this point would mean some unexpected party
6462 * is poking at the power controls too.
6463 */
6464 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
6465 WARN_ON(ctrl << 16 != state);
6466
6467 mutex_unlock(&dev_priv->rps.hw_lock);
6468
6469 return enabled;
6470}
6471
6472static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
6473 struct i915_power_well *power_well,
6474 bool enable)
6475{
6476 enum pipe pipe = power_well->data;
6477 u32 state;
6478 u32 ctrl;
6479
6480 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
6481
6482 mutex_lock(&dev_priv->rps.hw_lock);
6483
6484#define COND \
6485 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
6486
6487 if (COND)
6488 goto out;
6489
6490 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6491 ctrl &= ~DP_SSC_MASK(pipe);
6492 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
6493 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
6494
6495 if (wait_for(COND, 100))
6496 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6497 state,
6498 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
6499
6500#undef COND
6501
6502out:
6503 mutex_unlock(&dev_priv->rps.hw_lock);
6504}
6505
6506static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
6507 struct i915_power_well *power_well)
6508{
6509 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
6510}
6511
6512static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
6513 struct i915_power_well *power_well)
6514{
6515 WARN_ON_ONCE(power_well->data != PIPE_A &&
6516 power_well->data != PIPE_B &&
6517 power_well->data != PIPE_C);
6518
6519 chv_set_pipe_power_well(dev_priv, power_well, true);
6520}
6521
6522static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
6523 struct i915_power_well *power_well)
6524{
6525 WARN_ON_ONCE(power_well->data != PIPE_A &&
6526 power_well->data != PIPE_B &&
6527 power_well->data != PIPE_C);
6528
6529 chv_set_pipe_power_well(dev_priv, power_well, false);
6530}
6531
25eaa003
ID		 6532static void check_power_well_state(struct drm_i915_private *dev_priv,
6533 struct i915_power_well *power_well)
6534{
6535 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
6536
6537 if (power_well->always_on || !i915.disable_power_well) {
6538 if (!enabled)
6539 goto mismatch;
6540
6541 return;
6542 }
6543
6544 if (enabled != (power_well->count > 0))
6545 goto mismatch;
6546
6547 return;
6548
6549mismatch:
6550 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6551 power_well->name, power_well->always_on, enabled,
6552 power_well->count, i915.disable_power_well);
6553}
6554
da7e29bd 6555void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 6556 enum intel_display_power_domain domain)
6557{
83c00f55 6558 struct i915_power_domains *power_domains;
c1ca727f
ID		 6559 struct i915_power_well *power_well;
6560 int i;
6765625e 6561
9e6ea71a
PZ		 6562 intel_runtime_pm_get(dev_priv);
6563
83c00f55
ID		 6564 power_domains = &dev_priv->power_domains;
6565
6566 mutex_lock(&power_domains->lock);
1da51581 6567
25eaa003
ID		 6568 for_each_power_well(i, power_well, BIT(domain), power_domains) {
6569 if (!power_well->count++) {
6570 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 6571 power_well->ops->enable(dev_priv, power_well);
bfafe93a 6572 power_well->hw_enabled = true;
25eaa003
ID		 6573 }
6574
6575 check_power_well_state(dev_priv, power_well);
6576 }
1da51581 6577
ddf9c536
ID		 6578 power_domains->domain_use_count[domain]++;
6579
83c00f55 6580 mutex_unlock(&power_domains->lock);
6765625e
VS		 6581}
6582
da7e29bd 6583void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 6584 enum intel_display_power_domain domain)
6585{
83c00f55 6586 struct i915_power_domains *power_domains;
c1ca727f
ID		 6587 struct i915_power_well *power_well;
6588 int i;
6765625e 6589
83c00f55
ID		 6590 power_domains = &dev_priv->power_domains;
6591
6592 mutex_lock(&power_domains->lock);
1da51581 6593
1da51581
ID		 6594 WARN_ON(!power_domains->domain_use_count[domain]);
6595 power_domains->domain_use_count[domain]--;
ddf9c536 6596
70bf407c
ID		 6597 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6598 WARN_ON(!power_well->count);
6599
25eaa003
ID		 6600 if (!--power_well->count && i915.disable_power_well) {
6601 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
bfafe93a 6602 power_well->hw_enabled = false;
c6cb582e 6603 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 6604 }
6605
6606 check_power_well_state(dev_priv, power_well);
70bf407c 6607 }
1da51581 6608
83c00f55 6609 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 6610
6611 intel_runtime_pm_put(dev_priv);
6765625e
VS		 6612}
6613
83c00f55 6614static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 6615
6616/* Display audio driver power well request */
74b0c2d7 6617int i915_request_power_well(void)
a38911a3 6618{
b4ed4484
ID		 6619 struct drm_i915_private *dev_priv;
6620
74b0c2d7
TI		 6621 if (!hsw_pwr)
6622 return -ENODEV;
a38911a3 6623
b4ed4484
ID		 6624 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6625 power_domains);
da7e29bd 6626 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6627 return 0;
a38911a3
WX		 6628}
6629EXPORT_SYMBOL_GPL(i915_request_power_well);
6630
6631/* Display audio driver power well release */
74b0c2d7 6632int i915_release_power_well(void)
a38911a3 6633{
b4ed4484
ID		 6634 struct drm_i915_private *dev_priv;
6635
74b0c2d7
TI		 6636 if (!hsw_pwr)
6637 return -ENODEV;
a38911a3 6638
b4ed4484
ID		 6639 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6640 power_domains);
da7e29bd 6641 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
74b0c2d7 6642 return 0;
a38911a3
WX		 6643}
6644EXPORT_SYMBOL_GPL(i915_release_power_well);
6645
c149dcb5
JN		 6646/*
6647 * Private interface for the audio driver to get CDCLK in kHz.
6648 *
6649 * Caller must request power well using i915_request_power_well() prior to
6650 * making the call.
6651 */
6652int i915_get_cdclk_freq(void)
6653{
6654 struct drm_i915_private *dev_priv;
6655
6656 if (!hsw_pwr)
6657 return -ENODEV;
6658
6659 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6660 power_domains);
6661
6662 return intel_ddi_get_cdclk_freq(dev_priv);
6663}
6664EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6665
6666
efcad917
ID		 6667#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6668
6669#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6670 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 6671 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 6672 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6673 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6674 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6675 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6676 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6677 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6678 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6679 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6680 BIT(POWER_DOMAIN_PORT_CRT) | \
bd2bb1b9 6681 BIT(POWER_DOMAIN_PLLS) | \
f5938f36 6682 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 6683#define HSW_DISPLAY_POWER_DOMAINS ( \
6684 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6685 BIT(POWER_DOMAIN_INIT))
6686
6687#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6688 HSW_ALWAYS_ON_POWER_DOMAINS | \
6689 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6690#define BDW_DISPLAY_POWER_DOMAINS ( \
6691 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6692 BIT(POWER_DOMAIN_INIT))
6693
77961eb9
ID		 6694#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6695#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6696
6697#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6698 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6699 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6700 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6701 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6702 BIT(POWER_DOMAIN_PORT_CRT) | \
6703 BIT(POWER_DOMAIN_INIT))
6704
6705#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6706 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6707 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6708 BIT(POWER_DOMAIN_INIT))
6709
6710#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6711 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6712 BIT(POWER_DOMAIN_INIT))
6713
6714#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6715 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6716 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6717 BIT(POWER_DOMAIN_INIT))
6718
6719#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6720 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6721 BIT(POWER_DOMAIN_INIT))
6722
26972b0a
VS		 6723#define CHV_PIPE_A_POWER_DOMAINS ( \
6724 BIT(POWER_DOMAIN_PIPE_A) | \
6725 BIT(POWER_DOMAIN_INIT))
6726
6727#define CHV_PIPE_B_POWER_DOMAINS ( \
6728 BIT(POWER_DOMAIN_PIPE_B) | \
6729 BIT(POWER_DOMAIN_INIT))
6730
6731#define CHV_PIPE_C_POWER_DOMAINS ( \
6732 BIT(POWER_DOMAIN_PIPE_C) | \
6733 BIT(POWER_DOMAIN_INIT))
6734
5d6f7ea7
VS		 6735#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6736 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6737 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6738 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6739 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6740 BIT(POWER_DOMAIN_INIT))
6741
6742#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6743 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6744 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6745 BIT(POWER_DOMAIN_INIT))
6746
2ce147f3
VS		 6747#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
6748 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6749 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6750 BIT(POWER_DOMAIN_INIT))
6751
6752#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
6753 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6754 BIT(POWER_DOMAIN_INIT))
6755
a45f4466
ID		 6756static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6757 .sync_hw = i9xx_always_on_power_well_noop,
6758 .enable = i9xx_always_on_power_well_noop,
6759 .disable = i9xx_always_on_power_well_noop,
6760 .is_enabled = i9xx_always_on_power_well_enabled,
6761};
c6cb582e 6762
26972b0a
VS		 6763static const struct i915_power_well_ops chv_pipe_power_well_ops = {
6764 .sync_hw = chv_pipe_power_well_sync_hw,
6765 .enable = chv_pipe_power_well_enable,
6766 .disable = chv_pipe_power_well_disable,
6767 .is_enabled = chv_pipe_power_well_enabled,
6768};
6769
5d6f7ea7
VS		 6770static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
6771 .sync_hw = vlv_power_well_sync_hw,
6772 .enable = chv_dpio_cmn_power_well_enable,
6773 .disable = chv_dpio_cmn_power_well_disable,
6774 .is_enabled = vlv_power_well_enabled,
6775};
6776
1c2256df
ID		 6777static struct i915_power_well i9xx_always_on_power_well[] = {
6778 {
6779 .name = "always-on",
6780 .always_on = 1,
6781 .domains = POWER_DOMAIN_MASK,
c6cb582e 6782 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6783 },
6784};
6785
c6cb582e
ID		 6786static const struct i915_power_well_ops hsw_power_well_ops = {
6787 .sync_hw = hsw_power_well_sync_hw,
6788 .enable = hsw_power_well_enable,
6789 .disable = hsw_power_well_disable,
6790 .is_enabled = hsw_power_well_enabled,
6791};
6792
c1ca727f 6793static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6794 {
6795 .name = "always-on",
6796 .always_on = 1,
6797 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6798 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6799 },
c1ca727f
ID		 6800 {
6801 .name = "display",
efcad917 6802 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6803 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6804 },
6805};
6806
6807static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6808 {
6809 .name = "always-on",
6810 .always_on = 1,
6811 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6812 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6813 },
c1ca727f
ID		 6814 {
6815 .name = "display",
efcad917 6816 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6817 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6818 },
6819};
6820
77961eb9
ID		 6821static const struct i915_power_well_ops vlv_display_power_well_ops = {
6822 .sync_hw = vlv_power_well_sync_hw,
6823 .enable = vlv_display_power_well_enable,
6824 .disable = vlv_display_power_well_disable,
6825 .is_enabled = vlv_power_well_enabled,
6826};
6827
aa519f23
VS		 6828static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
6829 .sync_hw = vlv_power_well_sync_hw,
6830 .enable = vlv_dpio_cmn_power_well_enable,
6831 .disable = vlv_dpio_cmn_power_well_disable,
6832 .is_enabled = vlv_power_well_enabled,
6833};
6834
77961eb9
ID		 6835static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6836 .sync_hw = vlv_power_well_sync_hw,
6837 .enable = vlv_power_well_enable,
6838 .disable = vlv_power_well_disable,
6839 .is_enabled = vlv_power_well_enabled,
6840};
6841
6842static struct i915_power_well vlv_power_wells[] = {
6843 {
6844 .name = "always-on",
6845 .always_on = 1,
6846 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6847 .ops = &i9xx_always_on_power_well_ops,
6848 },
6849 {
6850 .name = "display",
6851 .domains = VLV_DISPLAY_POWER_DOMAINS,
6852 .data = PUNIT_POWER_WELL_DISP2D,
6853 .ops = &vlv_display_power_well_ops,
6854 },
77961eb9
ID		 6855 {
6856 .name = "dpio-tx-b-01",
6857 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6858 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6859 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6860 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6861 .ops = &vlv_dpio_power_well_ops,
6862 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6863 },
6864 {
6865 .name = "dpio-tx-b-23",
6866 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6867 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6868 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6869 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6870 .ops = &vlv_dpio_power_well_ops,
6871 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6872 },
6873 {
6874 .name = "dpio-tx-c-01",
6875 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6876 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6877 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6878 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6879 .ops = &vlv_dpio_power_well_ops,
6880 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6881 },
6882 {
6883 .name = "dpio-tx-c-23",
6884 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6885 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6886 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6887 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6888 .ops = &vlv_dpio_power_well_ops,
6889 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6890 },
f099a3c6
JB		 6891 {
6892 .name = "dpio-common",
6893 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6894 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
aa519f23 6895 .ops = &vlv_dpio_cmn_power_well_ops,
f099a3c6 6896 },
77961eb9
ID		 6897};
6898
4811ff4f
VS		 6899static struct i915_power_well chv_power_wells[] = {
6900 {
6901 .name = "always-on",
6902 .always_on = 1,
6903 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6904 .ops = &i9xx_always_on_power_well_ops,
6905 },
f07057d1
VS		 6906#if 0
6907 {
6908 .name = "display",
6909 .domains = VLV_DISPLAY_POWER_DOMAINS,
6910 .data = PUNIT_POWER_WELL_DISP2D,
6911 .ops = &vlv_display_power_well_ops,
6912 },
26972b0a
VS		 6913 {
6914 .name = "pipe-a",
6915 .domains = CHV_PIPE_A_POWER_DOMAINS,
6916 .data = PIPE_A,
6917 .ops = &chv_pipe_power_well_ops,
6918 },
6919 {
6920 .name = "pipe-b",
6921 .domains = CHV_PIPE_B_POWER_DOMAINS,
6922 .data = PIPE_B,
6923 .ops = &chv_pipe_power_well_ops,
6924 },
6925 {
6926 .name = "pipe-c",
6927 .domains = CHV_PIPE_C_POWER_DOMAINS,
6928 .data = PIPE_C,
6929 .ops = &chv_pipe_power_well_ops,
6930 },
f07057d1 6931#endif
5d6f7ea7
VS		 6932 {
6933 .name = "dpio-common-bc",
3dd7b974
VS		 6934 /*
6935 * XXX: cmnreset for one PHY seems to disturb the other.
6936 * As a workaround keep both powered on at the same
6937 * time for now.
6938 */
6939 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
5d6f7ea7
VS		 6940 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6941 .ops = &chv_dpio_cmn_power_well_ops,
6942 },
6943 {
6944 .name = "dpio-common-d",
3dd7b974
VS		 6945 /*
6946 * XXX: cmnreset for one PHY seems to disturb the other.
6947 * As a workaround keep both powered on at the same
6948 * time for now.
6949 */
6950 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS,
5d6f7ea7
VS		 6951 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
6952 .ops = &chv_dpio_cmn_power_well_ops,
6953 },
82583565
VS		 6954#if 0
6955 {
6956 .name = "dpio-tx-b-01",
6957 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6958 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6959 .ops = &vlv_dpio_power_well_ops,
6960 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6961 },
6962 {
6963 .name = "dpio-tx-b-23",
6964 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6965 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
6966 .ops = &vlv_dpio_power_well_ops,
6967 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6968 },
6969 {
6970 .name = "dpio-tx-c-01",
6971 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6972 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6973 .ops = &vlv_dpio_power_well_ops,
6974 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6975 },
6976 {
6977 .name = "dpio-tx-c-23",
6978 .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6979 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6980 .ops = &vlv_dpio_power_well_ops,
6981 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6982 },
2ce147f3
VS		 6983 {
6984 .name = "dpio-tx-d-01",
6985 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6986 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6987 .ops = &vlv_dpio_power_well_ops,
6988 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
6989 },
6990 {
6991 .name = "dpio-tx-d-23",
6992 .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
6993 CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
6994 .ops = &vlv_dpio_power_well_ops,
6995 .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
6996 },
82583565 6997#endif
4811ff4f
VS		 6998};
6999
d2011dc8
VS		 7000static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
7001 enum punit_power_well power_well_id)
7002{
7003 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7004 struct i915_power_well *power_well;
7005 int i;
7006
7007 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
7008 if (power_well->data == power_well_id)
7009 return power_well;
7010 }
7011
7012 return NULL;
7013}
7014
c1ca727f
ID		 7015#define set_power_wells(power_domains, __power_wells) ({ \
7016 (power_domains)->power_wells = (__power_wells); \
7017 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
7018})
7019
da7e29bd 7020int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 7021{
83c00f55 7022 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 7023
83c00f55 7024 mutex_init(&power_domains->lock);
a38911a3 7025
c1ca727f
ID		 7026 /*
7027 * The enabling order will be from lower to higher indexed wells,
7028 * the disabling order is reversed.
7029 */
da7e29bd 7030 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 7031 set_power_wells(power_domains, hsw_power_wells);
7032 hsw_pwr = power_domains;
da7e29bd 7033 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 7034 set_power_wells(power_domains, bdw_power_wells);
7035 hsw_pwr = power_domains;
4811ff4f
VS		 7036 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
7037 set_power_wells(power_domains, chv_power_wells);
77961eb9
ID		 7038 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
7039 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 7040 } else {
1c2256df 7041 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 7042 }
a38911a3
WX		 7043
7044 return 0;
7045}
7046
da7e29bd 7047void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 7048{
7049 hsw_pwr = NULL;
7050}
7051
da7e29bd 7052static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 7053{
83c00f55
ID		 7054 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7055 struct i915_power_well *power_well;
c1ca727f 7056 int i;
9cdb826c 7057
83c00f55 7058 mutex_lock(&power_domains->lock);
bfafe93a 7059 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
a45f4466 7060 power_well->ops->sync_hw(dev_priv, power_well);
bfafe93a
ID		 7061 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
7062 power_well);
7063 }
83c00f55 7064 mutex_unlock(&power_domains->lock);
a38911a3
WX		 7065}
7066
d2011dc8
VS		 7067static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
7068{
7069 struct i915_power_well *cmn =
7070 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
7071 struct i915_power_well *disp2d =
7072 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
7073
7074 /* nothing to do if common lane is already off */
7075 if (!cmn->ops->is_enabled(dev_priv, cmn))
7076 return;
7077
7078 /* If the display might be already active skip this */
7079 if (disp2d->ops->is_enabled(dev_priv, disp2d) &&
7080 I915_READ(DPIO_CTL) & DPIO_CMNRST)
7081 return;
7082
7083 DRM_DEBUG_KMS("toggling display PHY side reset\n");
7084
7085 /* cmnlane needs DPLL registers */
7086 disp2d->ops->enable(dev_priv, disp2d);
7087
7088 /*
7089 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
7090 * Need to assert and de-assert PHY SB reset by gating the
7091 * common lane power, then un-gating it.
7092 * Simply ungating isn't enough to reset the PHY enough to get
7093 * ports and lanes running.
7094 */
7095 cmn->ops->disable(dev_priv, cmn);
7096}
7097
da7e29bd 7098void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 7099{
d2011dc8 7100 struct drm_device *dev = dev_priv->dev;
0d116a29
ID		 7101 struct i915_power_domains *power_domains = &dev_priv->power_domains;
7102
7103 power_domains->initializing = true;
d2011dc8
VS		 7104
7105 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7106 mutex_lock(&power_domains->lock);
7107 vlv_cmnlane_wa(dev_priv);
7108 mutex_unlock(&power_domains->lock);
7109 }
7110
fa42e23c 7111 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 7112 intel_display_set_init_power(dev_priv, true);
7113 intel_power_domains_resume(dev_priv);
0d116a29 7114 power_domains->initializing = false;
d0d3e513
ED		 7115}
7116
c67a470b
PZ		 7117void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
7118{
d361ae26 7119 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 7120}
7121
7122void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
7123{
d361ae26 7124 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 7125}
7126
8a187455
PZ		 7127void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
7128{
7129 struct drm_device *dev = dev_priv->dev;
7130 struct device *device = &dev->pdev->dev;
7131
7132 if (!HAS_RUNTIME_PM(dev))
7133 return;
7134
7135 pm_runtime_get_sync(device);
7136 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
7137}
7138
c6df39b5
ID		 7139void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
7140{
7141 struct drm_device *dev = dev_priv->dev;
7142 struct device *device = &dev->pdev->dev;
7143
7144 if (!HAS_RUNTIME_PM(dev))
7145 return;
7146
7147 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
7148 pm_runtime_get_noresume(device);
7149}
7150
8a187455
PZ		 7151void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
7152{
7153 struct drm_device *dev = dev_priv->dev;
7154 struct device *device = &dev->pdev->dev;
7155
7156 if (!HAS_RUNTIME_PM(dev))
7157 return;
7158
7159 pm_runtime_mark_last_busy(device);
7160 pm_runtime_put_autosuspend(device);
7161}
7162
7163void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
7164{
7165 struct drm_device *dev = dev_priv->dev;
7166 struct device *device = &dev->pdev->dev;
7167
8a187455
PZ		 7168 if (!HAS_RUNTIME_PM(dev))
7169 return;
7170
7171 pm_runtime_set_active(device);
7172
aeab0b5a
ID		 7173 /*
7174 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
7175 * requirement.
7176 */
7177 if (!intel_enable_rc6(dev)) {
7178 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
7179 return;
7180 }
7181
8a187455
PZ		 7182 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
7183 pm_runtime_mark_last_busy(device);
7184 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 7185
7186 pm_runtime_put_autosuspend(device);
8a187455
PZ		 7187}
7188
7189void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
7190{
7191 struct drm_device *dev = dev_priv->dev;
7192 struct device *device = &dev->pdev->dev;
7193
7194 if (!HAS_RUNTIME_PM(dev))
7195 return;
7196
aeab0b5a
ID		 7197 if (!intel_enable_rc6(dev))
7198 return;
7199
8a187455
PZ		 7200 /* Make sure we're not suspended first. */
7201 pm_runtime_get_sync(device);
7202 pm_runtime_disable(device);
7203}
7204
1fa61106
ED		 7205/* Set up chip specific power management-related functions */
7206void intel_init_pm(struct drm_device *dev)
7207{
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209
3a77c4c4 7210 if (HAS_FBC(dev)) {
40045465 7211 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 7212 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 7213 dev_priv->display.enable_fbc = gen7_enable_fbc;
7214 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7215 } else if (INTEL_INFO(dev)->gen >= 5) {
7216 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7217 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 7218 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7219 } else if (IS_GM45(dev)) {
7220 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7221 dev_priv->display.enable_fbc = g4x_enable_fbc;
7222 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 7223 } else {
1fa61106
ED		 7224 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7225 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7226 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 7227
7228 /* This value was pulled out of someone's hat */
7229 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 7230 }
1fa61106
ED		 7231 }
7232
c921aba8
DV		 7233 /* For cxsr */
7234 if (IS_PINEVIEW(dev))
7235 i915_pineview_get_mem_freq(dev);
7236 else if (IS_GEN5(dev))
7237 i915_ironlake_get_mem_freq(dev);
7238
1fa61106
ED		 7239 /* For FIFO watermark updates */
7240 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7241 ilk_setup_wm_latency(dev);
53615a5e 7242
bd602544
VS		 7243 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7244 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7245 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7246 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7247 dev_priv->display.update_wm = ilk_update_wm;
7248 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7249 } else {
7250 DRM_DEBUG_KMS("Failed to read display plane latency. "
7251 "Disable CxSR\n");
7252 }
7253
7254 if (IS_GEN5(dev))
1fa61106 7255 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7256 else if (IS_GEN6(dev))
1fa61106 7257 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7258 else if (IS_IVYBRIDGE(dev))
1fa61106 7259 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7260 else if (IS_HASWELL(dev))
cad2a2d7 7261 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7262 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 7263 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8 7264 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 7265 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 7266 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 7267 dev_priv->display.init_clock_gating =
7268 cherryview_init_clock_gating;
1fa61106
ED		 7269 } else if (IS_VALLEYVIEW(dev)) {
7270 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 7271 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 7272 dev_priv->display.init_clock_gating =
7273 valleyview_init_clock_gating;
1fa61106
ED		 7274 } else if (IS_PINEVIEW(dev)) {
7275 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7276 dev_priv->is_ddr3,
7277 dev_priv->fsb_freq,
7278 dev_priv->mem_freq)) {
7279 DRM_INFO("failed to find known CxSR latency "
7280 "(found ddr%s fsb freq %d, mem freq %d), "
7281 "disabling CxSR\n",
7282 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7283 dev_priv->fsb_freq, dev_priv->mem_freq);
7284 /* Disable CxSR and never update its watermark again */
5209b1f4 7285 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7286 dev_priv->display.update_wm = NULL;
7287 } else
7288 dev_priv->display.update_wm = pineview_update_wm;
7289 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7290 } else if (IS_G4X(dev)) {
7291 dev_priv->display.update_wm = g4x_update_wm;
7292 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7293 } else if (IS_GEN4(dev)) {
7294 dev_priv->display.update_wm = i965_update_wm;
7295 if (IS_CRESTLINE(dev))
7296 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7297 else if (IS_BROADWATER(dev))
7298 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7299 } else if (IS_GEN3(dev)) {
7300 dev_priv->display.update_wm = i9xx_update_wm;
7301 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7302 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7303 } else if (IS_GEN2(dev)) {
7304 if (INTEL_INFO(dev)->num_pipes == 1) {
7305 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7306 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7307 } else {
7308 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7309 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7310 }
7311
7312 if (IS_I85X(dev) || IS_I865G(dev))
7313 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7314 else
7315 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7316 } else {
7317 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7318 }
7319}
7320
42c0526c
BW		 7321int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
7322{
4fc688ce 7323 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7324
7325 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7326 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7327 return -EAGAIN;
7328 }
7329
7330 I915_WRITE(GEN6_PCODE_DATA, *val);
7331 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7332
7333 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7334 500)) {
7335 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7336 return -ETIMEDOUT;
7337 }
7338
7339 *val = I915_READ(GEN6_PCODE_DATA);
7340 I915_WRITE(GEN6_PCODE_DATA, 0);
7341
7342 return 0;
7343}
7344
7345int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
7346{
4fc688ce 7347 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7348
7349 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7350 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7351 return -EAGAIN;
7352 }
7353
7354 I915_WRITE(GEN6_PCODE_DATA, val);
7355 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7356
7357 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7358 500)) {
7359 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7360 return -ETIMEDOUT;
7361 }
7362
7363 I915_WRITE(GEN6_PCODE_DATA, 0);
7364
7365 return 0;
7366}
a0e4e199 7367
b55dd647 7368static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 7369{
07ab118b 7370 int div;
855ba3be 7371
07ab118b 7372 /* 4 x czclk */
2ec3815f 7373 switch (dev_priv->mem_freq) {
855ba3be 7374 case 800:
07ab118b 7375 div = 10;
855ba3be
JB		 7376 break;
7377 case 1066:
07ab118b 7378 div = 12;
855ba3be
JB		 7379 break;
7380 case 1333:
07ab118b 7381 div = 16;
855ba3be
JB		 7382 break;
7383 default:
7384 return -1;
7385 }
7386
2ec3815f 7387 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 7388}
7389
b55dd647 7390static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7391{
07ab118b 7392 int mul;
855ba3be 7393
07ab118b 7394 /* 4 x czclk */
2ec3815f 7395 switch (dev_priv->mem_freq) {
855ba3be 7396 case 800:
07ab118b 7397 mul = 10;
855ba3be
JB		 7398 break;
7399 case 1066:
07ab118b 7400 mul = 12;
855ba3be
JB		 7401 break;
7402 case 1333:
07ab118b 7403 mul = 16;
855ba3be
JB		 7404 break;
7405 default:
7406 return -1;
7407 }
7408
2ec3815f 7409 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 7410}
7411
b55dd647 7412static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7413{
7414 int div, freq;
7415
7416 switch (dev_priv->rps.cz_freq) {
7417 case 200:
7418 div = 5;
7419 break;
7420 case 267:
7421 div = 6;
7422 break;
7423 case 320:
7424 case 333:
7425 case 400:
7426 div = 8;
7427 break;
7428 default:
7429 return -1;
7430 }
7431
7432 freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2);
7433
7434 return freq;
7435}
7436
b55dd647 7437static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8
D		 7438{
7439 int mul, opcode;
7440
7441 switch (dev_priv->rps.cz_freq) {
7442 case 200:
7443 mul = 5;
7444 break;
7445 case 267:
7446 mul = 6;
7447 break;
7448 case 320:
7449 case 333:
7450 case 400:
7451 mul = 8;
7452 break;
7453 default:
7454 return -1;
7455 }
7456
7457 opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2);
7458
7459 return opcode;
7460}
7461
7462int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7463{
7464 int ret = -1;
7465
7466 if (IS_CHERRYVIEW(dev_priv->dev))
7467 ret = chv_gpu_freq(dev_priv, val);
7468 else if (IS_VALLEYVIEW(dev_priv->dev))
7469 ret = byt_gpu_freq(dev_priv, val);
7470
7471 return ret;
7472}
7473
7474int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7475{
7476 int ret = -1;
7477
7478 if (IS_CHERRYVIEW(dev_priv->dev))
7479 ret = chv_freq_opcode(dev_priv, val);
7480 else if (IS_VALLEYVIEW(dev_priv->dev))
7481 ret = byt_freq_opcode(dev_priv, val);
7482
7483 return ret;
7484}
7485
f742a552 7486void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7487{
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489
f742a552
DV		 7490 mutex_init(&dev_priv->rps.hw_lock);
7491
907b28c5
CW		 7492 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7493 intel_gen6_powersave_work);
5d584b2e 7494
33688d95 7495 dev_priv->pm.suspended = false;
9df7575f 7496 dev_priv->pm._irqs_disabled = false;
907b28c5 7497}
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