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drm/i915: Remove LVDS and PPS suspend time save/restore
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
968 if (!state->visible)
969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
1010 if (state->visible) {
1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
1026 if (!state->visible) {
1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
1126 if (!state->visible)
1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
7221fc33 1778 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1788 drm_rect_width(&pstate->dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
7221fc33 1806 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1812 drm_rect_width(&pstate->dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
1831 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
7221fc33 1849 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1850 return 0;
1851
ac484963 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
367294be 2129 /*
6f97235b
DL		 2130 * WaWmMemoryReadLatency:skl
2131 *
367294be
VK		 2132 * punit doesn't take into account the read latency so we need
2133 * to add 2us to the various latency levels we retrieve from
2134 * the punit.
2135 * - W0 is a bit special in that it's the only level that
2136 * can't be disabled if we want to have display working, so
2137 * we always add 2us there.
2138 * - For levels >=1, punit returns 0us latency when they are
2139 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2140 *
2141 * Additionally, if a level n (n > 1) has a 0us latency, all
2142 * levels m (m >= n) need to be disabled. We make sure to
2143 * sanitize the values out of the punit to satisfy this
2144 * requirement.
367294be
VK		 2145 */
2146 wm[0] += 2;
2147 for (level = 1; level <= max_level; level++)
2148 if (wm[level] != 0)
2149 wm[level] += 2;
4f947386
VK		 2150 else {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
367294be 2153
4f947386
VK		 2154 break;
2155 }
2af30a5c 2156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2157 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159 wm[0] = (sskpd >> 56) & 0xFF;
2160 if (wm[0] == 0)
2161 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2162 wm[1] = (sskpd >> 4) & 0xFF;
2163 wm[2] = (sskpd >> 12) & 0xFF;
2164 wm[3] = (sskpd >> 20) & 0x1FF;
2165 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2166 } else if (INTEL_INFO(dev)->gen >= 6) {
2167 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2173 } else if (INTEL_INFO(dev)->gen >= 5) {
2174 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176 /* ILK primary LP0 latency is 700 ns */
2177 wm[0] = 7;
2178 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2180 }
2181}
2182
53615a5e
VS		 2183static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184{
2185 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2186 if (IS_GEN5(dev))
53615a5e
VS		 2187 wm[0] = 13;
2188}
2189
2190static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191{
2192 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2193 if (IS_GEN5(dev))
53615a5e
VS		 2194 wm[0] = 13;
2195
2196 /* WaDoubleCursorLP3Latency:ivb */
2197 if (IS_IVYBRIDGE(dev))
2198 wm[3] *= 2;
2199}
2200
546c81fd 2201int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2202{
26ec971e 2203 /* how many WM levels are we expecting */
b6e742f6 2204 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2205 return 7;
2206 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2207 return 4;
26ec971e 2208 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2209 return 3;
26ec971e 2210 else
ad0d6dc4
VS		 2211 return 2;
2212}
7526ed79 2213
ad0d6dc4
VS		 2214static void intel_print_wm_latency(struct drm_device *dev,
2215 const char *name,
2af30a5c 2216 const uint16_t wm[8])
ad0d6dc4
VS		 2217{
2218 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2219
2220 for (level = 0; level <= max_level; level++) {
2221 unsigned int latency = wm[level];
2222
2223 if (latency == 0) {
2224 DRM_ERROR("%s WM%d latency not provided\n",
2225 name, level);
2226 continue;
2227 }
2228
2af30a5c
PB		 2229 /*
2230 * - latencies are in us on gen9.
2231 * - before then, WM1+ latency values are in 0.5us units
2232 */
2233 if (IS_GEN9(dev))
2234 latency *= 10;
2235 else if (level > 0)
26ec971e
VS		 2236 latency *= 5;
2237
2238 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239 name, level, wm[level],
2240 latency / 10, latency % 10);
2241 }
2242}
2243
e95a2f75
VS		 2244static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245 uint16_t wm[5], uint16_t min)
2246{
91c8a326 2247 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2248
2249 if (wm[0] >= min)
2250 return false;
2251
2252 wm[0] = max(wm[0], min);
2253 for (level = 1; level <= max_level; level++)
2254 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256 return true;
2257}
2258
2259static void snb_wm_latency_quirk(struct drm_device *dev)
2260{
fac5e23e 2261 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2262 bool changed;
2263
2264 /*
2265 * The BIOS provided WM memory latency values are often
2266 * inadequate for high resolution displays. Adjust them.
2267 */
2268 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272 if (!changed)
2273 return;
2274
2275 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279}
2280
fa50ad61 2281static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2282{
fac5e23e 2283 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2284
2285 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288 sizeof(dev_priv->wm.pri_latency));
2289 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291
2292 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2294
2295 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2298
2299 if (IS_GEN6(dev))
2300 snb_wm_latency_quirk(dev);
53615a5e
VS		 2301}
2302
2af30a5c
PB		 2303static void skl_setup_wm_latency(struct drm_device *dev)
2304{
fac5e23e 2305 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2306
2307 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309}
2310
ed4a6a7c
MR		 2311static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312 struct intel_pipe_wm *pipe_wm)
2313{
2314 /* LP0 watermark maximums depend on this pipe alone */
2315 const struct intel_wm_config config = {
2316 .num_pipes_active = 1,
2317 .sprites_enabled = pipe_wm->sprites_enabled,
2318 .sprites_scaled = pipe_wm->sprites_scaled,
2319 };
2320 struct ilk_wm_maximums max;
2321
2322 /* LP0 watermarks always use 1/2 DDB partitioning */
2323 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325 /* At least LP0 must be valid */
2326 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328 return false;
2329 }
2330
2331 return true;
2332}
2333
0b2ae6d7 2334/* Compute new watermarks for the pipe */
e3bddded 2335static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2336{
e3bddded
ML		 2337 struct drm_atomic_state *state = cstate->base.state;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2339 struct intel_pipe_wm *pipe_wm;
e3bddded 2340 struct drm_device *dev = state->dev;
fac5e23e 2341 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2342 struct intel_plane *intel_plane;
86c8bbbe 2343 struct intel_plane_state *pristate = NULL;
43d59eda 2344 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2345 struct intel_plane_state *curstate = NULL;
d81f04c5 2346 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2347 struct ilk_wm_maximums max;
0b2ae6d7 2348
e8f1f02e 2349 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2350
43d59eda 2351 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2352 struct intel_plane_state *ps;
2353
2354 ps = intel_atomic_get_existing_plane_state(state,
2355 intel_plane);
2356 if (!ps)
2357 continue;
86c8bbbe
MR		 2358
2359 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2360 pristate = ps;
86c8bbbe 2361 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2362 sprstate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2364 curstate = ps;
43d59eda
MR		 2365 }
2366
ed4a6a7c 2367 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2368 if (sprstate) {
2369 pipe_wm->sprites_enabled = sprstate->visible;
2370 pipe_wm->sprites_scaled = sprstate->visible &&
2371 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2372 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2373 }
2374
d81f04c5
ML		 2375 usable_level = max_level;
2376
7b39a0b7 2377 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2378 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2379 usable_level = 1;
7b39a0b7
VS		 2380
2381 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2382 if (pipe_wm->sprites_scaled)
d81f04c5 2383 usable_level = 0;
7b39a0b7 2384
86c8bbbe 2385 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2386 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2390
a42a5719 2391 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2392 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2393
ed4a6a7c 2394 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2395 return -EINVAL;
a3cb4048
VS		 2396
2397 ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399 for (level = 1; level <= max_level; level++) {
71f0a626 2400 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2401
86c8bbbe 2402 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2403 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2404
2405 /*
2406 * Disable any watermark level that exceeds the
2407 * register maximums since such watermarks are
2408 * always invalid.
2409 */
71f0a626
ML		 2410 if (level > usable_level)
2411 continue;
2412
2413 if (ilk_validate_wm_level(level, &max, wm))
2414 pipe_wm->wm[level] = *wm;
2415 else
d81f04c5 2416 usable_level = level;
a3cb4048
VS		 2417 }
2418
86c8bbbe 2419 return 0;
0b2ae6d7
VS		 2420}
2421
ed4a6a7c
MR		 2422/*
2423 * Build a set of 'intermediate' watermark values that satisfy both the old
2424 * state and the new state. These can be programmed to the hardware
2425 * immediately.
2426 */
2427static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428 struct intel_crtc *intel_crtc,
2429 struct intel_crtc_state *newstate)
2430{
e8f1f02e 2431 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2432 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433 int level, max_level = ilk_wm_max_level(dev);
2434
2435 /*
2436 * Start with the final, target watermarks, then combine with the
2437 * currently active watermarks to get values that are safe both before
2438 * and after the vblank.
2439 */
e8f1f02e 2440 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2441 a->pipe_enabled |= b->pipe_enabled;
2442 a->sprites_enabled |= b->sprites_enabled;
2443 a->sprites_scaled |= b->sprites_scaled;
2444
2445 for (level = 0; level <= max_level; level++) {
2446 struct intel_wm_level *a_wm = &a->wm[level];
2447 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449 a_wm->enable &= b_wm->enable;
2450 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454 }
2455
2456 /*
2457 * We need to make sure that these merged watermark values are
2458 * actually a valid configuration themselves. If they're not,
2459 * there's no safe way to transition from the old state to
2460 * the new state, so we need to fail the atomic transaction.
2461 */
2462 if (!ilk_validate_pipe_wm(dev, a))
2463 return -EINVAL;
2464
2465 /*
2466 * If our intermediate WM are identical to the final WM, then we can
2467 * omit the post-vblank programming; only update if it's different.
2468 */
e8f1f02e 2469 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2470 newstate->wm.need_postvbl_update = false;
2471
2472 return 0;
2473}
2474
0b2ae6d7
VS		 2475/*
2476 * Merge the watermarks from all active pipes for a specific level.
2477 */
2478static void ilk_merge_wm_level(struct drm_device *dev,
2479 int level,
2480 struct intel_wm_level *ret_wm)
2481{
2482 const struct intel_crtc *intel_crtc;
2483
d52fea5b
VS		 2484 ret_wm->enable = true;
2485
d3fcc808 2486 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2487 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2488 const struct intel_wm_level *wm = &active->wm[level];
2489
2490 if (!active->pipe_enabled)
2491 continue;
0b2ae6d7 2492
d52fea5b
VS		 2493 /*
2494 * The watermark values may have been used in the past,
2495 * so we must maintain them in the registers for some
2496 * time even if the level is now disabled.
2497 */
0b2ae6d7 2498 if (!wm->enable)
d52fea5b 2499 ret_wm->enable = false;
0b2ae6d7
VS		 2500
2501 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505 }
0b2ae6d7
VS		 2506}
2507
2508/*
2509 * Merge all low power watermarks for all active pipes.
2510 */
2511static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2512 const struct intel_wm_config *config,
820c1980 2513 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2514 struct intel_pipe_wm *merged)
2515{
fac5e23e 2516 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2517 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2518 int last_enabled_level = max_level;
0b2ae6d7 2519
0ba22e26
VS		 2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522 config->num_pipes_active > 1)
1204d5ba 2523 last_enabled_level = 0;
0ba22e26 2524
6c8b6c28
VS		 2525 /* ILK: FBC WM must be disabled always */
2526 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2527
2528 /* merge each WM1+ level */
2529 for (level = 1; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 ilk_merge_wm_level(dev, level, wm);
2533
d52fea5b
VS		 2534 if (level > last_enabled_level)
2535 wm->enable = false;
2536 else if (!ilk_validate_wm_level(level, max, wm))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level = level - 1;
0b2ae6d7
VS		 2539
2540 /*
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2543 */
2544 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2545 if (wm->enable)
2546 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2547 wm->fbc_val = 0;
2548 }
2549 }
6c8b6c28
VS		 2550
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552 /*
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2556 */
7733b49b 2557 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2558 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2559 for (level = 2; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 wm->enable = false;
2563 }
2564 }
0b2ae6d7
VS		 2565}
2566
b380ca3c
VS		 2567static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568{
2569 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571}
2572
a68d68ee
VS		 2573/* The value we need to program into the WM_LPx latency field */
2574static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575{
fac5e23e 2576 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2577
a42a5719 2578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2579 return 2 * level;
2580 else
2581 return dev_priv->wm.pri_latency[level];
2582}
2583
820c1980 2584static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2585 const struct intel_pipe_wm *merged,
609cedef 2586 enum intel_ddb_partitioning partitioning,
820c1980 2587 struct ilk_wm_values *results)
801bcfff 2588{
0b2ae6d7
VS		 2589 struct intel_crtc *intel_crtc;
2590 int level, wm_lp;
cca32e9a 2591
0362c781 2592 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2593 results->partitioning = partitioning;
cca32e9a 2594
0b2ae6d7 2595 /* LP1+ register values */
cca32e9a 2596 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2597 const struct intel_wm_level *r;
801bcfff 2598
b380ca3c 2599 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2600
0362c781 2601 r = &merged->wm[level];
cca32e9a 2602
d52fea5b
VS		 2603 /*
2604 * Maintain the watermark values even if the level is
2605 * disabled. Doing otherwise could cause underruns.
2606 */
2607 results->wm_lp[wm_lp - 1] =
a68d68ee 2608 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2609 (r->pri_val << WM1_LP_SR_SHIFT) |
2610 r->cur_val;
2611
d52fea5b
VS		 2612 if (r->enable)
2613 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
416f4727
VS		 2615 if (INTEL_INFO(dev)->gen >= 8)
2616 results->wm_lp[wm_lp - 1] |=
2617 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618 else
2619 results->wm_lp[wm_lp - 1] |=
2620 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
d52fea5b
VS		 2622 /*
2623 * Always set WM1S_LP_EN when spr_val != 0, even if the
2624 * level is disabled. Doing otherwise could cause underruns.
2625 */
6cef2b8a
VS		 2626 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627 WARN_ON(wm_lp != 1);
2628 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629 } else
2630 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2631 }
801bcfff 2632
0b2ae6d7 2633 /* LP0 register values */
d3fcc808 2634 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2635 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2636 const struct intel_wm_level *r =
2637 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2638
2639 if (WARN_ON(!r->enable))
2640 continue;
2641
ed4a6a7c 2642 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2643
0b2ae6d7
VS		 2644 results->wm_pipe[pipe] =
2645 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647 r->cur_val;
801bcfff
PZ		 2648 }
2649}
2650
861f3389
PZ		 2651/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2653static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2654 struct intel_pipe_wm *r1,
2655 struct intel_pipe_wm *r2)
861f3389 2656{
198a1e9b
VS		 2657 int level, max_level = ilk_wm_max_level(dev);
2658 int level1 = 0, level2 = 0;
861f3389 2659
198a1e9b
VS		 2660 for (level = 1; level <= max_level; level++) {
2661 if (r1->wm[level].enable)
2662 level1 = level;
2663 if (r2->wm[level].enable)
2664 level2 = level;
861f3389
PZ		 2665 }
2666
198a1e9b
VS		 2667 if (level1 == level2) {
2668 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2669 return r2;
2670 else
2671 return r1;
198a1e9b 2672 } else if (level1 > level2) {
861f3389
PZ		 2673 return r1;
2674 } else {
2675 return r2;
2676 }
2677}
2678
49a687c4
VS		 2679/* dirty bits used to track which watermarks need changes */
2680#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684#define WM_DIRTY_FBC (1 << 24)
2685#define WM_DIRTY_DDB (1 << 25)
2686
055e393f 2687static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2688 const struct ilk_wm_values *old,
2689 const struct ilk_wm_values *new)
49a687c4
VS		 2690{
2691 unsigned int dirty = 0;
2692 enum pipe pipe;
2693 int wm_lp;
2694
055e393f 2695 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2696 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697 dirty |= WM_DIRTY_LINETIME(pipe);
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2700 }
2701
2702 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703 dirty |= WM_DIRTY_PIPE(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707 }
2708
2709 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710 dirty |= WM_DIRTY_FBC;
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714
2715 if (old->partitioning != new->partitioning) {
2716 dirty |= WM_DIRTY_DDB;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 /* LP1+ watermarks already deemed dirty, no need to continue */
2722 if (dirty & WM_DIRTY_LP_ALL)
2723 return dirty;
2724
2725 /* Find the lowest numbered LP1+ watermark in need of an update... */
2726 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729 break;
2730 }
2731
2732 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733 for (; wm_lp <= 3; wm_lp++)
2734 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736 return dirty;
2737}
2738
8553c18e
VS		 2739static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740 unsigned int dirty)
801bcfff 2741{
820c1980 2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2743 bool changed = false;
801bcfff 2744
facd619b
VS		 2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2748 changed = true;
facd619b
VS		 2749 }
2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2753 changed = true;
facd619b
VS		 2754 }
2755 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2758 changed = true;
facd619b 2759 }
801bcfff 2760
facd619b
VS		 2761 /*
2762 * Don't touch WM1S_LP_EN here.
2763 * Doing so could cause underruns.
2764 */
6cef2b8a 2765
8553c18e
VS		 2766 return changed;
2767}
2768
2769/*
2770 * The spec says we shouldn't write when we don't need, because every write
2771 * causes WMs to be re-evaluated, expending some power.
2772 */
820c1980
ID		 2773static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774 struct ilk_wm_values *results)
8553c18e 2775{
91c8a326 2776 struct drm_device *dev = &dev_priv->drm;
820c1980 2777 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2778 unsigned int dirty;
2779 uint32_t val;
2780
055e393f 2781 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2782 if (!dirty)
2783 return;
2784
2785 _ilk_disable_lp_wm(dev_priv, dirty);
2786
49a687c4 2787 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2788 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2790 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2792 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
49a687c4 2794 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2795 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_DDB) {
a42a5719 2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2803 val = I915_READ(WM_MISC);
2804 if (results->partitioning == INTEL_DDB_PART_1_2)
2805 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806 else
2807 val |= WM_MISC_DATA_PARTITION_5_6;
2808 I915_WRITE(WM_MISC, val);
2809 } else {
2810 val = I915_READ(DISP_ARB_CTL2);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~DISP_DATA_PARTITION_5_6;
2813 else
2814 val |= DISP_DATA_PARTITION_5_6;
2815 I915_WRITE(DISP_ARB_CTL2, val);
2816 }
1011d8c4
PZ		 2817 }
2818
49a687c4 2819 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2820 val = I915_READ(DISP_ARB_CTL);
2821 if (results->enable_fbc_wm)
2822 val &= ~DISP_FBC_WM_DIS;
2823 else
2824 val |= DISP_FBC_WM_DIS;
2825 I915_WRITE(DISP_ARB_CTL, val);
2826 }
2827
954911eb
ID		 2828 if (dirty & WM_DIRTY_LP(1) &&
2829 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837 }
801bcfff 2838
facd619b 2839 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2840 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2841 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2842 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2843 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2844 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2845
2846 dev_priv->wm.hw = *results;
801bcfff
PZ		 2847}
2848
ed4a6a7c 2849bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2850{
fac5e23e 2851 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2852
2853 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854}
2855
b9cec075
DL		 2856/*
2857 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2858 * different active planes.
2859 */
2860
2861#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2862#define BXT_DDB_SIZE 512
b9cec075 2863
024c9045
MR		 2864/*
2865 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2866 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867 * other universal planes are in indices 1..n. Note that this may leave unused
2868 * indices between the top "sprite" plane and the cursor.
2869 */
2870static int
2871skl_wm_plane_id(const struct intel_plane *plane)
2872{
2873 switch (plane->base.type) {
2874 case DRM_PLANE_TYPE_PRIMARY:
2875 return 0;
2876 case DRM_PLANE_TYPE_CURSOR:
2877 return PLANE_CURSOR;
2878 case DRM_PLANE_TYPE_OVERLAY:
2879 return plane->plane + 1;
2880 default:
2881 MISSING_CASE(plane->base.type);
2882 return plane->plane;
2883 }
2884}
2885
b9cec075
DL		 2886static void
2887skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2888 const struct intel_crtc_state *cstate,
c107acfe
MR		 2889 struct skl_ddb_entry *alloc, /* out */
2890 int *num_active /* out */)
b9cec075 2891{
c107acfe
MR		 2892 struct drm_atomic_state *state = cstate->base.state;
2893 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2894 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2895 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2896 unsigned int pipe_size, ddb_size;
2897 int nth_active_pipe;
c107acfe
MR		 2898 int pipe = to_intel_crtc(for_crtc)->pipe;
2899
a6d3460e 2900 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2901 alloc->start = 0;
2902 alloc->end = 0;
a6d3460e 2903 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2904 return;
2905 }
2906
a6d3460e
MR		 2907 if (intel_state->active_pipe_changes)
2908 *num_active = hweight32(intel_state->active_crtcs);
2909 else
2910 *num_active = hweight32(dev_priv->active_crtcs);
2911
43d735a6
DL		 2912 if (IS_BROXTON(dev))
2913 ddb_size = BXT_DDB_SIZE;
2914 else
2915 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2916
2917 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2918
c107acfe 2919 /*
a6d3460e
MR		 2920 * If the state doesn't change the active CRTC's, then there's
2921 * no need to recalculate; the existing pipe allocation limits
2922 * should remain unchanged. Note that we're safe from racing
2923 * commits since any racing commit that changes the active CRTC
2924 * list would need to grab _all_ crtc locks, including the one
2925 * we currently hold.
c107acfe 2926 */
a6d3460e
MR		 2927 if (!intel_state->active_pipe_changes) {
2928 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2929 return;
c107acfe 2930 }
a6d3460e
MR		 2931
2932 nth_active_pipe = hweight32(intel_state->active_crtcs &
2933 (drm_crtc_mask(for_crtc) - 1));
2934 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2935 alloc->start = nth_active_pipe * ddb_size / *num_active;
2936 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2937}
2938
c107acfe 2939static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2940{
c107acfe 2941 if (num_active == 1)
b9cec075
DL		 2942 return 32;
2943
2944 return 8;
2945}
2946
a269c583
DL		 2947static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2948{
2949 entry->start = reg & 0x3ff;
2950 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2951 if (entry->end)
2952 entry->end += 1;
a269c583
DL		 2953}
2954
08db6652
DL		 2955void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2956 struct skl_ddb_allocation *ddb /* out */)
a269c583 2957{
a269c583
DL		 2958 enum pipe pipe;
2959 int plane;
2960 u32 val;
2961
b10f1b20
ML		 2962 memset(ddb, 0, sizeof(*ddb));
2963
a269c583 2964 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2965 enum intel_display_power_domain power_domain;
2966
2967 power_domain = POWER_DOMAIN_PIPE(pipe);
2968 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2969 continue;
2970
dd740780 2971 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2972 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2973 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2974 val);
2975 }
2976
2977 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2978 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2979 val);
4d800030
ID		 2980
2981 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2982 }
2983}
2984
9c2f7a9d
KM		 2985/*
2986 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2987 * The bspec defines downscale amount as:
2988 *
2989 * """
2990 * Horizontal down scale amount = maximum[1, Horizontal source size /
2991 * Horizontal destination size]
2992 * Vertical down scale amount = maximum[1, Vertical source size /
2993 * Vertical destination size]
2994 * Total down scale amount = Horizontal down scale amount *
2995 * Vertical down scale amount
2996 * """
2997 *
2998 * Return value is provided in 16.16 fixed point form to retain fractional part.
2999 * Caller should take care of dividing & rounding off the value.
3000 */
3001static uint32_t
3002skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3003{
3004 uint32_t downscale_h, downscale_w;
3005 uint32_t src_w, src_h, dst_w, dst_h;
3006
3007 if (WARN_ON(!pstate->visible))
3008 return DRM_PLANE_HELPER_NO_SCALING;
3009
3010 /* n.b., src is 16.16 fixed point, dst is whole integer */
3011 src_w = drm_rect_width(&pstate->src);
3012 src_h = drm_rect_height(&pstate->src);
3013 dst_w = drm_rect_width(&pstate->dst);
3014 dst_h = drm_rect_height(&pstate->dst);
3015 if (intel_rotation_90_or_270(pstate->base.rotation))
3016 swap(dst_w, dst_h);
3017
3018 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3019 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3020
3021 /* Provide result in 16.16 fixed point */
3022 return (uint64_t)downscale_w * downscale_h >> 16;
3023}
3024
b9cec075 3025static unsigned int
024c9045
MR		 3026skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3027 const struct drm_plane_state *pstate,
3028 int y)
b9cec075 3029{
a280f7dd 3030 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3031 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3032 uint32_t down_scale_amount, data_rate;
a280f7dd 3033 uint32_t width = 0, height = 0;
a1de91e5
MR		 3034 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3035
3036 if (!intel_pstate->visible)
3037 return 0;
3038 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3039 return 0;
3040 if (y && format != DRM_FORMAT_NV12)
3041 return 0;
a280f7dd
KM		 3042
3043 width = drm_rect_width(&intel_pstate->src) >> 16;
3044 height = drm_rect_height(&intel_pstate->src) >> 16;
3045
3046 if (intel_rotation_90_or_270(pstate->rotation))
3047 swap(width, height);
2cd601c6
CK		 3048
3049 /* for planar format */
a1de91e5 3050 if (format == DRM_FORMAT_NV12) {
2cd601c6 3051 if (y) /* y-plane data rate */
8d19d7d9 3052 data_rate = width * height *
a1de91e5 3053 drm_format_plane_cpp(format, 0);
2cd601c6 3054 else /* uv-plane data rate */
8d19d7d9 3055 data_rate = (width / 2) * (height / 2) *
a1de91e5 3056 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3057 } else {
3058 /* for packed formats */
3059 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3060 }
3061
8d19d7d9
KM		 3062 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3063
3064 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3065}
3066
3067/*
3068 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3069 * a 8192x4096@32bpp framebuffer:
3070 * 3 * 4096 * 8192 * 4 < 2^32
3071 */
3072static unsigned int
9c74d826 3073skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3074{
9c74d826
MR		 3075 struct drm_crtc_state *cstate = &intel_cstate->base;
3076 struct drm_atomic_state *state = cstate->state;
3077 struct drm_crtc *crtc = cstate->crtc;
3078 struct drm_device *dev = crtc->dev;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3080 const struct drm_plane *plane;
024c9045 3081 const struct intel_plane *intel_plane;
a6d3460e 3082 struct drm_plane_state *pstate;
a1de91e5 3083 unsigned int rate, total_data_rate = 0;
9c74d826 3084 int id;
a6d3460e
MR		 3085 int i;
3086
3087 if (WARN_ON(!state))
3088 return 0;
b9cec075 3089
a1de91e5 3090 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3091 for_each_plane_in_state(state, plane, pstate, i) {
3092 id = skl_wm_plane_id(to_intel_plane(plane));
3093 intel_plane = to_intel_plane(plane);
3094
3095 if (intel_plane->pipe != intel_crtc->pipe)
3096 continue;
3097
3098 /* packed/uv */
3099 rate = skl_plane_relative_data_rate(intel_cstate,
3100 pstate, 0);
3101 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3102
3103 /* y-plane */
3104 rate = skl_plane_relative_data_rate(intel_cstate,
3105 pstate, 1);
3106 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3107 }
024c9045 3108
a1de91e5
MR		 3109 /* Calculate CRTC's total data rate from cached values */
3110 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3111 int id = skl_wm_plane_id(intel_plane);
024c9045 3112
a1de91e5 3113 /* packed/uv */
9c74d826
MR		 3114 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3115 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3116 }
3117
9c74d826
MR		 3118 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3119
b9cec075
DL		 3120 return total_data_rate;
3121}
3122
cbcfd14b
KM		 3123static uint16_t
3124skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3125 const int y)
3126{
3127 struct drm_framebuffer *fb = pstate->fb;
3128 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3129 uint32_t src_w, src_h;
3130 uint32_t min_scanlines = 8;
3131 uint8_t plane_bpp;
3132
3133 if (WARN_ON(!fb))
3134 return 0;
3135
3136 /* For packed formats, no y-plane, return 0 */
3137 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3138 return 0;
3139
3140 /* For Non Y-tile return 8-blocks */
3141 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3142 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3143 return 8;
3144
3145 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3146 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3147
3148 if (intel_rotation_90_or_270(pstate->rotation))
3149 swap(src_w, src_h);
3150
3151 /* Halve UV plane width and height for NV12 */
3152 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3153 src_w /= 2;
3154 src_h /= 2;
3155 }
3156
3157 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3158 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3159 else
3160 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3161
3162 if (intel_rotation_90_or_270(pstate->rotation)) {
3163 switch (plane_bpp) {
3164 case 1:
3165 min_scanlines = 32;
3166 break;
3167 case 2:
3168 min_scanlines = 16;
3169 break;
3170 case 4:
3171 min_scanlines = 8;
3172 break;
3173 case 8:
3174 min_scanlines = 4;
3175 break;
3176 default:
3177 WARN(1, "Unsupported pixel depth %u for rotation",
3178 plane_bpp);
3179 min_scanlines = 32;
3180 }
3181 }
3182
3183 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3184}
3185
c107acfe 3186static int
024c9045 3187skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3188 struct skl_ddb_allocation *ddb /* out */)
3189{
c107acfe 3190 struct drm_atomic_state *state = cstate->base.state;
024c9045 3191 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3192 struct drm_device *dev = crtc->dev;
3193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3194 struct intel_plane *intel_plane;
c107acfe
MR		 3195 struct drm_plane *plane;
3196 struct drm_plane_state *pstate;
b9cec075 3197 enum pipe pipe = intel_crtc->pipe;
34bb56af 3198 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3199 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3200 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3201 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3202 unsigned int total_data_rate;
c107acfe
MR		 3203 int num_active;
3204 int id, i;
b9cec075 3205
a6d3460e
MR		 3206 if (WARN_ON(!state))
3207 return 0;
3208
c107acfe
MR		 3209 if (!cstate->base.active) {
3210 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3211 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3212 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3213 return 0;
3214 }
3215
a6d3460e 3216 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3217 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3218 if (alloc_size == 0) {
3219 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3220 return 0;
b9cec075
DL		 3221 }
3222
c107acfe 3223 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3224 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3225 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3226
3227 alloc_size -= cursor_blocks;
b9cec075 3228
80958155 3229 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3230 for_each_plane_in_state(state, plane, pstate, i) {
3231 intel_plane = to_intel_plane(plane);
3232 id = skl_wm_plane_id(intel_plane);
c107acfe 3233
a6d3460e
MR		 3234 if (intel_plane->pipe != pipe)
3235 continue;
c107acfe 3236
a6d3460e
MR		 3237 if (!to_intel_plane_state(pstate)->visible) {
3238 minimum[id] = 0;
3239 y_minimum[id] = 0;
3240 continue;
3241 }
3242 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3243 minimum[id] = 0;
3244 y_minimum[id] = 0;
3245 continue;
c107acfe 3246 }
a6d3460e 3247
cbcfd14b
KM		 3248 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3249 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3250 }
80958155 3251
c107acfe
MR		 3252 for (i = 0; i < PLANE_CURSOR; i++) {
3253 alloc_size -= minimum[i];
3254 alloc_size -= y_minimum[i];
80958155
DL		 3255 }
3256
b9cec075 3257 /*
80958155
DL		 3258 * 2. Distribute the remaining space in proportion to the amount of
3259 * data each plane needs to fetch from memory.
b9cec075
DL		 3260 *
3261 * FIXME: we may not allocate every single block here.
3262 */
024c9045 3263 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3264 if (total_data_rate == 0)
c107acfe 3265 return 0;
b9cec075 3266
34bb56af 3267 start = alloc->start;
024c9045 3268 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3269 unsigned int data_rate, y_data_rate;
3270 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3271 int id = skl_wm_plane_id(intel_plane);
b9cec075 3272
a1de91e5 3273 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3274
3275 /*
2cd601c6 3276 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3277 * promote the expression to 64 bits to avoid overflowing, the
3278 * result is < available as data_rate / total_data_rate < 1
3279 */
024c9045 3280 plane_blocks = minimum[id];
80958155
DL		 3281 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3282 total_data_rate);
b9cec075 3283
c107acfe
MR		 3284 /* Leave disabled planes at (0,0) */
3285 if (data_rate) {
3286 ddb->plane[pipe][id].start = start;
3287 ddb->plane[pipe][id].end = start + plane_blocks;
3288 }
b9cec075
DL		 3289
3290 start += plane_blocks;
2cd601c6
CK		 3291
3292 /*
3293 * allocation for y_plane part of planar format:
3294 */
a1de91e5
MR		 3295 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3296
3297 y_plane_blocks = y_minimum[id];
3298 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3299 total_data_rate);
2cd601c6 3300
c107acfe
MR		 3301 if (y_data_rate) {
3302 ddb->y_plane[pipe][id].start = start;
3303 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3304 }
a1de91e5
MR		 3305
3306 start += y_plane_blocks;
b9cec075
DL		 3307 }
3308
c107acfe 3309 return 0;
b9cec075
DL		 3310}
3311
5cec258b 3312static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3313{
3314 /* TODO: Take into account the scalers once we support them */
2d112de7 3315 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3316}
3317
3318/*
3319 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3320 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3321 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3322 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3323*/
ac484963 3324static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3325{
3326 uint32_t wm_intermediate_val, ret;
3327
3328 if (latency == 0)
3329 return UINT_MAX;
3330
ac484963 3331 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3332 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3333
3334 return ret;
3335}
3336
3337static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3338 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3339 uint64_t tiling, uint32_t latency)
2d41c0b5 3340{
d4c2aa60
TU		 3341 uint32_t ret;
3342 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3343 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3344
3345 if (latency == 0)
3346 return UINT_MAX;
3347
ac484963 3348 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3349
3350 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3351 tiling == I915_FORMAT_MOD_Yf_TILED) {
3352 plane_bytes_per_line *= 4;
3353 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3354 plane_blocks_per_line /= 4;
055c3ff6
MR		 3355 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3356 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3357 } else {
3358 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3359 }
3360
2d41c0b5
PB		 3361 wm_intermediate_val = latency * pixel_rate;
3362 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3363 plane_blocks_per_line;
2d41c0b5
PB		 3364
3365 return ret;
3366}
3367
9c2f7a9d
KM		 3368static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3369 struct intel_plane_state *pstate)
3370{
3371 uint64_t adjusted_pixel_rate;
3372 uint64_t downscale_amount;
3373 uint64_t pixel_rate;
3374
3375 /* Shouldn't reach here on disabled planes... */
3376 if (WARN_ON(!pstate->visible))
3377 return 0;
3378
3379 /*
3380 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3381 * with additional adjustments for plane-specific scaling.
3382 */
3383 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3384 downscale_amount = skl_plane_downscale_amount(pstate);
3385
3386 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3387 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3388
3389 return pixel_rate;
3390}
3391
55994c2c
MR		 3392static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3393 struct intel_crtc_state *cstate,
3394 struct intel_plane_state *intel_pstate,
3395 uint16_t ddb_allocation,
3396 int level,
3397 uint16_t *out_blocks, /* out */
3398 uint8_t *out_lines, /* out */
3399 bool *enabled /* out */)
2d41c0b5 3400{
33815fa5
MR		 3401 struct drm_plane_state *pstate = &intel_pstate->base;
3402 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3403 uint32_t latency = dev_priv->wm.skl_latency[level];
3404 uint32_t method1, method2;
3405 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3406 uint32_t res_blocks, res_lines;
3407 uint32_t selected_result;
ac484963 3408 uint8_t cpp;
a280f7dd 3409 uint32_t width = 0, height = 0;
9c2f7a9d 3410 uint32_t plane_pixel_rate;
2d41c0b5 3411
55994c2c
MR		 3412 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3413 *enabled = false;
3414 return 0;
3415 }
2d41c0b5 3416
a280f7dd
KM		 3417 width = drm_rect_width(&intel_pstate->src) >> 16;
3418 height = drm_rect_height(&intel_pstate->src) >> 16;
3419
33815fa5 3420 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3421 swap(width, height);
3422
ac484963 3423 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3424 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3425
3426 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3427 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3428 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3429 width,
3430 cpp,
3431 fb->modifier[0],
d4c2aa60 3432 latency);
2d41c0b5 3433
a280f7dd 3434 plane_bytes_per_line = width * cpp;
d4c2aa60 3435 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3436
024c9045
MR		 3437 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3438 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3439 uint32_t min_scanlines = 4;
3440 uint32_t y_tile_minimum;
33815fa5 3441 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3442 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3443 drm_format_plane_cpp(fb->pixel_format, 1) :
3444 drm_format_plane_cpp(fb->pixel_format, 0);
3445
ac484963 3446 switch (cpp) {
1fc0a8f7
TU		 3447 case 1:
3448 min_scanlines = 16;
3449 break;
3450 case 2:
3451 min_scanlines = 8;
3452 break;
3453 case 8:
3454 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3455 }
1fc0a8f7
TU		 3456 }
3457 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3458 selected_result = max(method2, y_tile_minimum);
3459 } else {
3460 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3461 selected_result = min(method1, method2);
3462 else
3463 selected_result = method1;
3464 }
2d41c0b5 3465
d4c2aa60
TU		 3466 res_blocks = selected_result + 1;
3467 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3468
0fda6568 3469 if (level >= 1 && level <= 7) {
024c9045
MR		 3470 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3471 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3472 res_lines += 4;
3473 else
3474 res_blocks++;
3475 }
e6d66171 3476
55994c2c
MR		 3477 if (res_blocks >= ddb_allocation || res_lines > 31) {
3478 *enabled = false;
6b6bada7
MR		 3479
3480 /*
3481 * If there are no valid level 0 watermarks, then we can't
3482 * support this display configuration.
3483 */
3484 if (level) {
3485 return 0;
3486 } else {
3487 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3488 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3489 to_intel_crtc(cstate->base.crtc)->pipe,
3490 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3491 res_blocks, ddb_allocation, res_lines);
3492
3493 return -EINVAL;
3494 }
55994c2c 3495 }
e6d66171
DL		 3496
3497 *out_blocks = res_blocks;
3498 *out_lines = res_lines;
55994c2c 3499 *enabled = true;
2d41c0b5 3500
55994c2c 3501 return 0;
2d41c0b5
PB		 3502}
3503
f4a96752
MR		 3504static int
3505skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3506 struct skl_ddb_allocation *ddb,
3507 struct intel_crtc_state *cstate,
3508 int level,
3509 struct skl_wm_level *result)
2d41c0b5 3510{
f4a96752 3511 struct drm_atomic_state *state = cstate->base.state;
024c9045 3512 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3513 struct drm_plane *plane;
024c9045 3514 struct intel_plane *intel_plane;
33815fa5 3515 struct intel_plane_state *intel_pstate;
2d41c0b5 3516 uint16_t ddb_blocks;
024c9045 3517 enum pipe pipe = intel_crtc->pipe;
55994c2c 3518 int ret;
024c9045 3519
f4a96752
MR		 3520 /*
3521 * We'll only calculate watermarks for planes that are actually
3522 * enabled, so make sure all other planes are set as disabled.
3523 */
3524 memset(result, 0, sizeof(*result));
3525
91c8a326
CW		 3526 for_each_intel_plane_mask(&dev_priv->drm,
3527 intel_plane,
3528 cstate->base.plane_mask) {
024c9045 3529 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3530
f4a96752
MR		 3531 plane = &intel_plane->base;
3532 intel_pstate = NULL;
3533 if (state)
3534 intel_pstate =
3535 intel_atomic_get_existing_plane_state(state,
3536 intel_plane);
3537
3538 /*
3539 * Note: If we start supporting multiple pending atomic commits
3540 * against the same planes/CRTC's in the future, plane->state
3541 * will no longer be the correct pre-state to use for the
3542 * calculations here and we'll need to change where we get the
3543 * 'unchanged' plane data from.
3544 *
3545 * For now this is fine because we only allow one queued commit
3546 * against a CRTC. Even if the plane isn't modified by this
3547 * transaction and we don't have a plane lock, we still have
3548 * the CRTC's lock, so we know that no other transactions are
3549 * racing with us to update it.
3550 */
3551 if (!intel_pstate)
3552 intel_pstate = to_intel_plane_state(plane->state);
3553
3554 WARN_ON(!intel_pstate->base.fb);
3555
2d41c0b5
PB		 3556 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3557
55994c2c
MR		 3558 ret = skl_compute_plane_wm(dev_priv,
3559 cstate,
3560 intel_pstate,
3561 ddb_blocks,
3562 level,
3563 &result->plane_res_b[i],
3564 &result->plane_res_l[i],
3565 &result->plane_en[i]);
3566 if (ret)
3567 return ret;
2d41c0b5 3568 }
f4a96752
MR		 3569
3570 return 0;
2d41c0b5
PB		 3571}
3572
407b50f3 3573static uint32_t
024c9045 3574skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3575{
024c9045 3576 if (!cstate->base.active)
407b50f3
DL		 3577 return 0;
3578
024c9045 3579 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3580 return 0;
407b50f3 3581
024c9045
MR		 3582 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3583 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3584}
3585
024c9045 3586static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3587 struct skl_wm_level *trans_wm /* out */)
407b50f3 3588{
024c9045 3589 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3591 struct intel_plane *intel_plane;
9414f563 3592
024c9045 3593 if (!cstate->base.active)
407b50f3 3594 return;
9414f563
DL		 3595
3596 /* Until we know more, just disable transition WMs */
024c9045
MR		 3597 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3598 int i = skl_wm_plane_id(intel_plane);
3599
9414f563 3600 trans_wm->plane_en[i] = false;
024c9045 3601 }
407b50f3
DL		 3602}
3603
55994c2c
MR		 3604static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3605 struct skl_ddb_allocation *ddb,
3606 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3607{
024c9045 3608 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3609 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3610 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3611 int ret;
2d41c0b5
PB		 3612
3613 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3614 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3615 level, &pipe_wm->wm[level]);
3616 if (ret)
3617 return ret;
2d41c0b5 3618 }
024c9045 3619 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3620
024c9045 3621 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3622
3623 return 0;
2d41c0b5
PB		 3624}
3625
3626static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3627 struct skl_pipe_wm *p_wm,
3628 struct skl_wm_values *r,
3629 struct intel_crtc *intel_crtc)
3630{
3631 int level, max_level = ilk_wm_max_level(dev);
3632 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3633 uint32_t temp;
3634 int i;
2d41c0b5
PB		 3635
3636 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3637 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3638 temp = 0;
2d41c0b5
PB		 3639
3640 temp |= p_wm->wm[level].plane_res_l[i] <<
3641 PLANE_WM_LINES_SHIFT;
3642 temp |= p_wm->wm[level].plane_res_b[i];
3643 if (p_wm->wm[level].plane_en[i])
3644 temp |= PLANE_WM_EN;
3645
3646 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3647 }
3648
3649 temp = 0;
2d41c0b5 3650
4969d33e
MR		 3651 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3652 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3653
4969d33e 3654 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3655 temp |= PLANE_WM_EN;
3656
4969d33e 3657 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3658
3659 }
3660
9414f563
DL		 3661 /* transition WMs */
3662 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3663 temp = 0;
3664 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3665 temp |= p_wm->trans_wm.plane_res_b[i];
3666 if (p_wm->trans_wm.plane_en[i])
3667 temp |= PLANE_WM_EN;
3668
3669 r->plane_trans[pipe][i] = temp;
3670 }
3671
3672 temp = 0;
4969d33e
MR		 3673 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3674 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3675 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3676 temp |= PLANE_WM_EN;
3677
4969d33e 3678 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3679
2d41c0b5
PB		 3680 r->wm_linetime[pipe] = p_wm->linetime;
3681}
3682
f0f59a00
VS		 3683static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3684 i915_reg_t reg,
16160e3d
DL		 3685 const struct skl_ddb_entry *entry)
3686{
3687 if (entry->end)
3688 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3689 else
3690 I915_WRITE(reg, 0);
3691}
3692
2d41c0b5
PB		 3693static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3694 const struct skl_wm_values *new)
3695{
91c8a326 3696 struct drm_device *dev = &dev_priv->drm;
2d41c0b5
PB		 3697 struct intel_crtc *crtc;
3698
19c8054c 3699 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3700 int i, level, max_level = ilk_wm_max_level(dev);
3701 enum pipe pipe = crtc->pipe;
3702
2b4b9f35 3703 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3704 continue;
734fa01f
MR		 3705 if (!crtc->active)
3706 continue;
8211bd5b 3707
5d374d96 3708 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3709
5d374d96
DL		 3710 for (level = 0; level <= max_level; level++) {
3711 for (i = 0; i < intel_num_planes(crtc); i++)
3712 I915_WRITE(PLANE_WM(pipe, i, level),
3713 new->plane[pipe][i][level]);
3714 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3715 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3716 }
5d374d96
DL		 3717 for (i = 0; i < intel_num_planes(crtc); i++)
3718 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3719 new->plane_trans[pipe][i]);
4969d33e
MR		 3720 I915_WRITE(CUR_WM_TRANS(pipe),
3721 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3722
2cd601c6 3723 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3724 skl_ddb_entry_write(dev_priv,
3725 PLANE_BUF_CFG(pipe, i),
3726 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3727 skl_ddb_entry_write(dev_priv,
3728 PLANE_NV12_BUF_CFG(pipe, i),
3729 &new->ddb.y_plane[pipe][i]);
3730 }
5d374d96
DL		 3731
3732 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3733 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3734 }
2d41c0b5
PB		 3735}
3736
0e8fb7ba
DL		 3737/*
3738 * When setting up a new DDB allocation arrangement, we need to correctly
3739 * sequence the times at which the new allocations for the pipes are taken into
3740 * account or we'll have pipes fetching from space previously allocated to
3741 * another pipe.
3742 *
3743 * Roughly the sequence looks like:
3744 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3745 * overlapping with a previous light-up pipe (another way to put it is:
3746 * pipes with their new allocation strickly included into their old ones).
3747 * 2. re-allocate the other pipes that get their allocation reduced
3748 * 3. allocate the pipes having their allocation increased
3749 *
3750 * Steps 1. and 2. are here to take care of the following case:
3751 * - Initially DDB looks like this:
3752 * | B | C |
3753 * - enable pipe A.
3754 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3755 * allocation
3756 * | A | B | C |
3757 *
3758 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3759 */
3760
d21b795c
DL		 3761static void
3762skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3763{
0e8fb7ba
DL		 3764 int plane;
3765
d21b795c
DL		 3766 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3767
dd740780 3768 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3769 I915_WRITE(PLANE_SURF(pipe, plane),
3770 I915_READ(PLANE_SURF(pipe, plane)));
3771 }
3772 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3773}
3774
3775static bool
3776skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3777 const struct skl_ddb_allocation *new,
3778 enum pipe pipe)
3779{
3780 uint16_t old_size, new_size;
3781
3782 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3783 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3784
3785 return old_size != new_size &&
3786 new->pipe[pipe].start >= old->pipe[pipe].start &&
3787 new->pipe[pipe].end <= old->pipe[pipe].end;
3788}
3789
3790static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3791 struct skl_wm_values *new_values)
3792{
91c8a326 3793 struct drm_device *dev = &dev_priv->drm;
0e8fb7ba 3794 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3795 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3796 struct intel_crtc *crtc;
3797 enum pipe pipe;
3798
3799 new_ddb = &new_values->ddb;
3800 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3801
3802 /*
3803 * First pass: flush the pipes with the new allocation contained into
3804 * the old space.
3805 *
3806 * We'll wait for the vblank on those pipes to ensure we can safely
3807 * re-allocate the freed space without this pipe fetching from it.
3808 */
3809 for_each_intel_crtc(dev, crtc) {
3810 if (!crtc->active)
3811 continue;
3812
3813 pipe = crtc->pipe;
3814
3815 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3816 continue;
3817
d21b795c 3818 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3819 intel_wait_for_vblank(dev, pipe);
3820
3821 reallocated[pipe] = true;
3822 }
3823
3824
3825 /*
3826 * Second pass: flush the pipes that are having their allocation
3827 * reduced, but overlapping with a previous allocation.
3828 *
3829 * Here as well we need to wait for the vblank to make sure the freed
3830 * space is not used anymore.
3831 */
3832 for_each_intel_crtc(dev, crtc) {
3833 if (!crtc->active)
3834 continue;
3835
3836 pipe = crtc->pipe;
3837
3838 if (reallocated[pipe])
3839 continue;
3840
3841 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3842 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3843 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3844 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3845 reallocated[pipe] = true;
0e8fb7ba 3846 }
0e8fb7ba
DL		 3847 }
3848
3849 /*
3850 * Third pass: flush the pipes that got more space allocated.
3851 *
3852 * We don't need to actively wait for the update here, next vblank
3853 * will just get more DDB space with the correct WM values.
3854 */
3855 for_each_intel_crtc(dev, crtc) {
3856 if (!crtc->active)
3857 continue;
3858
3859 pipe = crtc->pipe;
3860
3861 /*
3862 * At this point, only the pipes more space than before are
3863 * left to re-allocate.
3864 */
3865 if (reallocated[pipe])
3866 continue;
3867
d21b795c 3868 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3869 }
3870}
3871
55994c2c
MR		 3872static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3873 struct skl_ddb_allocation *ddb, /* out */
3874 struct skl_pipe_wm *pipe_wm, /* out */
3875 bool *changed /* out */)
2d41c0b5 3876{
f4a96752
MR		 3877 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3878 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3879 int ret;
2d41c0b5 3880
55994c2c
MR		 3881 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3882 if (ret)
3883 return ret;
2d41c0b5 3884
4e0963c7 3885 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3886 *changed = false;
3887 else
3888 *changed = true;
2d41c0b5 3889
55994c2c 3890 return 0;
2d41c0b5
PB		 3891}
3892
9b613022
MR		 3893static uint32_t
3894pipes_modified(struct drm_atomic_state *state)
3895{
3896 struct drm_crtc *crtc;
3897 struct drm_crtc_state *cstate;
3898 uint32_t i, ret = 0;
3899
3900 for_each_crtc_in_state(state, crtc, cstate, i)
3901 ret |= drm_crtc_mask(crtc);
3902
3903 return ret;
3904}
3905
98d39494
MR		 3906static int
3907skl_compute_ddb(struct drm_atomic_state *state)
3908{
3909 struct drm_device *dev = state->dev;
3910 struct drm_i915_private *dev_priv = to_i915(dev);
3911 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3912 struct intel_crtc *intel_crtc;
734fa01f 3913 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3914 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3915 int ret;
3916
3917 /*
3918 * If this is our first atomic update following hardware readout,
3919 * we can't trust the DDB that the BIOS programmed for us. Let's
3920 * pretend that all pipes switched active status so that we'll
3921 * ensure a full DDB recompute.
3922 */
3923 if (dev_priv->wm.distrust_bios_wm)
3924 intel_state->active_pipe_changes = ~0;
3925
3926 /*
3927 * If the modeset changes which CRTC's are active, we need to
3928 * recompute the DDB allocation for *all* active pipes, even
3929 * those that weren't otherwise being modified in any way by this
3930 * atomic commit. Due to the shrinking of the per-pipe allocations
3931 * when new active CRTC's are added, it's possible for a pipe that
3932 * we were already using and aren't changing at all here to suddenly
3933 * become invalid if its DDB needs exceeds its new allocation.
3934 *
3935 * Note that if we wind up doing a full DDB recompute, we can't let
3936 * any other display updates race with this transaction, so we need
3937 * to grab the lock on *all* CRTC's.
3938 */
734fa01f 3939 if (intel_state->active_pipe_changes) {
98d39494 3940 realloc_pipes = ~0;
734fa01f
MR		 3941 intel_state->wm_results.dirty_pipes = ~0;
3942 }
98d39494
MR		 3943
3944 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3945 struct intel_crtc_state *cstate;
3946
3947 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3948 if (IS_ERR(cstate))
3949 return PTR_ERR(cstate);
3950
734fa01f 3951 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 3952 if (ret)
3953 return ret;
3954 }
3955
3956 return 0;
3957}
3958
3959static int
3960skl_compute_wm(struct drm_atomic_state *state)
3961{
3962 struct drm_crtc *crtc;
3963 struct drm_crtc_state *cstate;
734fa01f
MR		 3964 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3965 struct skl_wm_values *results = &intel_state->wm_results;
3966 struct skl_pipe_wm *pipe_wm;
98d39494 3967 bool changed = false;
734fa01f 3968 int ret, i;
98d39494
MR		 3969
3970 /*
3971 * If this transaction isn't actually touching any CRTC's, don't
3972 * bother with watermark calculation. Note that if we pass this
3973 * test, we're guaranteed to hold at least one CRTC state mutex,
3974 * which means we can safely use values like dev_priv->active_crtcs
3975 * since any racing commits that want to update them would need to
3976 * hold _all_ CRTC state mutexes.
3977 */
3978 for_each_crtc_in_state(state, crtc, cstate, i)
3979 changed = true;
3980 if (!changed)
3981 return 0;
3982
734fa01f
MR		 3983 /* Clear all dirty flags */
3984 results->dirty_pipes = 0;
3985
98d39494
MR		 3986 ret = skl_compute_ddb(state);
3987 if (ret)
3988 return ret;
3989
734fa01f
MR		 3990 /*
3991 * Calculate WM's for all pipes that are part of this transaction.
3992 * Note that the DDB allocation above may have added more CRTC's that
3993 * weren't otherwise being modified (and set bits in dirty_pipes) if
3994 * pipe allocations had to change.
3995 *
3996 * FIXME: Now that we're doing this in the atomic check phase, we
3997 * should allow skl_update_pipe_wm() to return failure in cases where
3998 * no suitable watermark values can be found.
3999 */
4000 for_each_crtc_in_state(state, crtc, cstate, i) {
4001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002 struct intel_crtc_state *intel_cstate =
4003 to_intel_crtc_state(cstate);
4004
4005 pipe_wm = &intel_cstate->wm.skl.optimal;
4006 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4007 &changed);
4008 if (ret)
4009 return ret;
4010
4011 if (changed)
4012 results->dirty_pipes |= drm_crtc_mask(crtc);
4013
4014 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4015 /* This pipe's WM's did not change */
4016 continue;
4017
4018 intel_cstate->update_wm_pre = true;
4019 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4020 }
4021
98d39494
MR		 4022 return 0;
4023}
4024
2d41c0b5
PB		 4025static void skl_update_wm(struct drm_crtc *crtc)
4026{
4027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4028 struct drm_device *dev = crtc->dev;
fac5e23e 4029 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4030 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 4031 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4032 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
adda50b8 4033
734fa01f 4034 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4035 return;
4036
734fa01f
MR		 4037 intel_crtc->wm.active.skl = *pipe_wm;
4038
4039 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4040
2d41c0b5 4041 skl_write_wm_values(dev_priv, results);
0e8fb7ba 4042 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 4043
4044 /* store the new configuration */
4045 dev_priv->wm.skl_hw = *results;
734fa01f
MR		 4046
4047 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4048}
4049
d890565c
VS		 4050static void ilk_compute_wm_config(struct drm_device *dev,
4051 struct intel_wm_config *config)
4052{
4053 struct intel_crtc *crtc;
4054
4055 /* Compute the currently _active_ config */
4056 for_each_intel_crtc(dev, crtc) {
4057 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4058
4059 if (!wm->pipe_enabled)
4060 continue;
4061
4062 config->sprites_enabled |= wm->sprites_enabled;
4063 config->sprites_scaled |= wm->sprites_scaled;
4064 config->num_pipes_active++;
4065 }
4066}
4067
ed4a6a7c 4068static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4069{
91c8a326 4070 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4071 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4072 struct ilk_wm_maximums max;
d890565c 4073 struct intel_wm_config config = {};
820c1980 4074 struct ilk_wm_values results = {};
77c122bc 4075 enum intel_ddb_partitioning partitioning;
261a27d1 4076
d890565c
VS		 4077 ilk_compute_wm_config(dev, &config);
4078
4079 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4080 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4081
4082 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4083 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4084 config.num_pipes_active == 1 && config.sprites_enabled) {
4085 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4086 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4087
820c1980 4088 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4089 } else {
198a1e9b 4090 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4091 }
4092
198a1e9b 4093 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4094 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4095
820c1980 4096 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4097
820c1980 4098 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4099}
4100
ed4a6a7c 4101static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4102{
ed4a6a7c
MR		 4103 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4104 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4105
ed4a6a7c 4106 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4107 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4108 ilk_program_watermarks(dev_priv);
4109 mutex_unlock(&dev_priv->wm.wm_mutex);
4110}
bf220452 4111
ed4a6a7c
MR		 4112static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4113{
4114 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4115 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4116
ed4a6a7c
MR		 4117 mutex_lock(&dev_priv->wm.wm_mutex);
4118 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4119 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4120 ilk_program_watermarks(dev_priv);
4121 }
4122 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4123}
4124
3078999f
PB		 4125static void skl_pipe_wm_active_state(uint32_t val,
4126 struct skl_pipe_wm *active,
4127 bool is_transwm,
4128 bool is_cursor,
4129 int i,
4130 int level)
4131{
4132 bool is_enabled = (val & PLANE_WM_EN) != 0;
4133
4134 if (!is_transwm) {
4135 if (!is_cursor) {
4136 active->wm[level].plane_en[i] = is_enabled;
4137 active->wm[level].plane_res_b[i] =
4138 val & PLANE_WM_BLOCKS_MASK;
4139 active->wm[level].plane_res_l[i] =
4140 (val >> PLANE_WM_LINES_SHIFT) &
4141 PLANE_WM_LINES_MASK;
4142 } else {
4969d33e
MR		 4143 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4144 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4145 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4146 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4147 (val >> PLANE_WM_LINES_SHIFT) &
4148 PLANE_WM_LINES_MASK;
4149 }
4150 } else {
4151 if (!is_cursor) {
4152 active->trans_wm.plane_en[i] = is_enabled;
4153 active->trans_wm.plane_res_b[i] =
4154 val & PLANE_WM_BLOCKS_MASK;
4155 active->trans_wm.plane_res_l[i] =
4156 (val >> PLANE_WM_LINES_SHIFT) &
4157 PLANE_WM_LINES_MASK;
4158 } else {
4969d33e
MR		 4159 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4160 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4161 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4162 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4163 (val >> PLANE_WM_LINES_SHIFT) &
4164 PLANE_WM_LINES_MASK;
4165 }
4166 }
4167}
4168
4169static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4170{
4171 struct drm_device *dev = crtc->dev;
fac5e23e 4172 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4173 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4175 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4176 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4177 enum pipe pipe = intel_crtc->pipe;
4178 int level, i, max_level;
4179 uint32_t temp;
4180
4181 max_level = ilk_wm_max_level(dev);
4182
4183 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4184
4185 for (level = 0; level <= max_level; level++) {
4186 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4187 hw->plane[pipe][i][level] =
4188 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4189 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4190 }
4191
4192 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4193 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4194 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4195
3ef00284 4196 if (!intel_crtc->active)
3078999f
PB		 4197 return;
4198
2b4b9f35 4199 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4200
4201 active->linetime = hw->wm_linetime[pipe];
4202
4203 for (level = 0; level <= max_level; level++) {
4204 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4205 temp = hw->plane[pipe][i][level];
4206 skl_pipe_wm_active_state(temp, active, false,
4207 false, i, level);
4208 }
4969d33e 4209 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4210 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4211 }
4212
4213 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4214 temp = hw->plane_trans[pipe][i];
4215 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4216 }
4217
4969d33e 4218 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4219 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4220
4221 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4222}
4223
4224void skl_wm_get_hw_state(struct drm_device *dev)
4225{
fac5e23e 4226 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4227 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4228 struct drm_crtc *crtc;
4229
a269c583 4230 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4231 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4232 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4233
279e99d7
MR		 4234 if (dev_priv->active_crtcs) {
4235 /* Fully recompute DDB on first atomic commit */
4236 dev_priv->wm.distrust_bios_wm = true;
4237 } else {
4238 /* Easy/common case; just sanitize DDB now if everything off */
4239 memset(ddb, 0, sizeof(*ddb));
4240 }
3078999f
PB		 4241}
4242
243e6a44
VS		 4243static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4244{
4245 struct drm_device *dev = crtc->dev;
fac5e23e 4246 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4247 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4249 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4250 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4251 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4252 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4253 [PIPE_A] = WM0_PIPEA_ILK,
4254 [PIPE_B] = WM0_PIPEB_ILK,
4255 [PIPE_C] = WM0_PIPEC_IVB,
4256 };
4257
4258 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4259 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4260 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4261
15606534
VS		 4262 memset(active, 0, sizeof(*active));
4263
3ef00284 4264 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4265
4266 if (active->pipe_enabled) {
243e6a44
VS		 4267 u32 tmp = hw->wm_pipe[pipe];
4268
4269 /*
4270 * For active pipes LP0 watermark is marked as
4271 * enabled, and LP1+ watermaks as disabled since
4272 * we can't really reverse compute them in case
4273 * multiple pipes are active.
4274 */
4275 active->wm[0].enable = true;
4276 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4277 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4278 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4279 active->linetime = hw->wm_linetime[pipe];
4280 } else {
4281 int level, max_level = ilk_wm_max_level(dev);
4282
4283 /*
4284 * For inactive pipes, all watermark levels
4285 * should be marked as enabled but zeroed,
4286 * which is what we'd compute them to.
4287 */
4288 for (level = 0; level <= max_level; level++)
4289 active->wm[level].enable = true;
4290 }
4e0963c7
MR		 4291
4292 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4293}
4294
6eb1a681
VS		 4295#define _FW_WM(value, plane) \
4296 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4297#define _FW_WM_VLV(value, plane) \
4298 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4299
4300static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4301 struct vlv_wm_values *wm)
4302{
4303 enum pipe pipe;
4304 uint32_t tmp;
4305
4306 for_each_pipe(dev_priv, pipe) {
4307 tmp = I915_READ(VLV_DDL(pipe));
4308
4309 wm->ddl[pipe].primary =
4310 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4311 wm->ddl[pipe].cursor =
4312 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4313 wm->ddl[pipe].sprite[0] =
4314 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4315 wm->ddl[pipe].sprite[1] =
4316 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4317 }
4318
4319 tmp = I915_READ(DSPFW1);
4320 wm->sr.plane = _FW_WM(tmp, SR);
4321 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4322 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4323 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4324
4325 tmp = I915_READ(DSPFW2);
4326 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4327 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4328 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4329
4330 tmp = I915_READ(DSPFW3);
4331 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4332
4333 if (IS_CHERRYVIEW(dev_priv)) {
4334 tmp = I915_READ(DSPFW7_CHV);
4335 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4336 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4337
4338 tmp = I915_READ(DSPFW8_CHV);
4339 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4340 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4341
4342 tmp = I915_READ(DSPFW9_CHV);
4343 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4344 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4345
4346 tmp = I915_READ(DSPHOWM);
4347 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4348 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4349 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4350 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4351 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4352 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4353 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4354 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4355 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4356 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4357 } else {
4358 tmp = I915_READ(DSPFW7);
4359 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4360 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4361
4362 tmp = I915_READ(DSPHOWM);
4363 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4364 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4365 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4366 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4367 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4368 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4369 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4370 }
4371}
4372
4373#undef _FW_WM
4374#undef _FW_WM_VLV
4375
4376void vlv_wm_get_hw_state(struct drm_device *dev)
4377{
4378 struct drm_i915_private *dev_priv = to_i915(dev);
4379 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4380 struct intel_plane *plane;
4381 enum pipe pipe;
4382 u32 val;
4383
4384 vlv_read_wm_values(dev_priv, wm);
4385
4386 for_each_intel_plane(dev, plane) {
4387 switch (plane->base.type) {
4388 int sprite;
4389 case DRM_PLANE_TYPE_CURSOR:
4390 plane->wm.fifo_size = 63;
4391 break;
4392 case DRM_PLANE_TYPE_PRIMARY:
4393 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4394 break;
4395 case DRM_PLANE_TYPE_OVERLAY:
4396 sprite = plane->plane;
4397 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4398 break;
4399 }
4400 }
4401
4402 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4403 wm->level = VLV_WM_LEVEL_PM2;
4404
4405 if (IS_CHERRYVIEW(dev_priv)) {
4406 mutex_lock(&dev_priv->rps.hw_lock);
4407
4408 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4409 if (val & DSP_MAXFIFO_PM5_ENABLE)
4410 wm->level = VLV_WM_LEVEL_PM5;
4411
58590c14
VS		 4412 /*
4413 * If DDR DVFS is disabled in the BIOS, Punit
4414 * will never ack the request. So if that happens
4415 * assume we don't have to enable/disable DDR DVFS
4416 * dynamically. To test that just set the REQ_ACK
4417 * bit to poke the Punit, but don't change the
4418 * HIGH/LOW bits so that we don't actually change
4419 * the current state.
4420 */
6eb1a681 4421 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4422 val |= FORCE_DDR_FREQ_REQ_ACK;
4423 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4424
4425 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4426 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4427 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4428 "assuming DDR DVFS is disabled\n");
4429 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4430 } else {
4431 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4432 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4433 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4434 }
6eb1a681
VS		 4435
4436 mutex_unlock(&dev_priv->rps.hw_lock);
4437 }
4438
4439 for_each_pipe(dev_priv, pipe)
4440 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4441 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4442 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4443
4444 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4445 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4446}
4447
243e6a44
VS		 4448void ilk_wm_get_hw_state(struct drm_device *dev)
4449{
fac5e23e 4450 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4451 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4452 struct drm_crtc *crtc;
4453
70e1e0ec 4454 for_each_crtc(dev, crtc)
243e6a44
VS		 4455 ilk_pipe_wm_get_hw_state(crtc);
4456
4457 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4458 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4459 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4460
4461 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4462 if (INTEL_INFO(dev)->gen >= 7) {
4463 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4464 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4465 }
243e6a44 4466
a42a5719 4467 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4468 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4469 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4470 else if (IS_IVYBRIDGE(dev))
4471 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4472 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4473
4474 hw->enable_fbc_wm =
4475 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4476}
4477
b445e3b0
ED		 4478/**
4479 * intel_update_watermarks - update FIFO watermark values based on current modes
4480 *
4481 * Calculate watermark values for the various WM regs based on current mode
4482 * and plane configuration.
4483 *
4484 * There are several cases to deal with here:
4485 * - normal (i.e. non-self-refresh)
4486 * - self-refresh (SR) mode
4487 * - lines are large relative to FIFO size (buffer can hold up to 2)
4488 * - lines are small relative to FIFO size (buffer can hold more than 2
4489 * lines), so need to account for TLB latency
4490 *
4491 * The normal calculation is:
4492 * watermark = dotclock * bytes per pixel * latency
4493 * where latency is platform & configuration dependent (we assume pessimal
4494 * values here).
4495 *
4496 * The SR calculation is:
4497 * watermark = (trunc(latency/line time)+1) * surface width *
4498 * bytes per pixel
4499 * where
4500 * line time = htotal / dotclock
4501 * surface width = hdisplay for normal plane and 64 for cursor
4502 * and latency is assumed to be high, as above.
4503 *
4504 * The final value programmed to the register should always be rounded up,
4505 * and include an extra 2 entries to account for clock crossings.
4506 *
4507 * We don't use the sprite, so we can ignore that. And on Crestline we have
4508 * to set the non-SR watermarks to 8.
4509 */
46ba614c 4510void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4511{
fac5e23e 4512 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4513
4514 if (dev_priv->display.update_wm)
46ba614c 4515 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4516}
4517
e2828914 4518/*
9270388e 4519 * Lock protecting IPS related data structures
9270388e
DV		 4520 */
4521DEFINE_SPINLOCK(mchdev_lock);
4522
4523/* Global for IPS driver to get at the current i915 device. Protected by
4524 * mchdev_lock. */
4525static struct drm_i915_private *i915_mch_dev;
4526
91d14251 4527bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4528{
2b4e57bd
ED		 4529 u16 rgvswctl;
4530
9270388e
DV		 4531 assert_spin_locked(&mchdev_lock);
4532
2b4e57bd
ED		 4533 rgvswctl = I915_READ16(MEMSWCTL);
4534 if (rgvswctl & MEMCTL_CMD_STS) {
4535 DRM_DEBUG("gpu busy, RCS change rejected\n");
4536 return false; /* still busy with another command */
4537 }
4538
4539 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4540 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4541 I915_WRITE16(MEMSWCTL, rgvswctl);
4542 POSTING_READ16(MEMSWCTL);
4543
4544 rgvswctl |= MEMCTL_CMD_STS;
4545 I915_WRITE16(MEMSWCTL, rgvswctl);
4546
4547 return true;
4548}
4549
91d14251 4550static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4551{
84f1b20f 4552 u32 rgvmodectl;
2b4e57bd
ED		 4553 u8 fmax, fmin, fstart, vstart;
4554
9270388e
DV		 4555 spin_lock_irq(&mchdev_lock);
4556
84f1b20f
TU		 4557 rgvmodectl = I915_READ(MEMMODECTL);
4558
2b4e57bd
ED		 4559 /* Enable temp reporting */
4560 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4561 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4562
4563 /* 100ms RC evaluation intervals */
4564 I915_WRITE(RCUPEI, 100000);
4565 I915_WRITE(RCDNEI, 100000);
4566
4567 /* Set max/min thresholds to 90ms and 80ms respectively */
4568 I915_WRITE(RCBMAXAVG, 90000);
4569 I915_WRITE(RCBMINAVG, 80000);
4570
4571 I915_WRITE(MEMIHYST, 1);
4572
4573 /* Set up min, max, and cur for interrupt handling */
4574 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4575 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4576 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4577 MEMMODE_FSTART_SHIFT;
4578
616847e7 4579 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4580 PXVFREQ_PX_SHIFT;
4581
20e4d407
DV		 4582 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4583 dev_priv->ips.fstart = fstart;
2b4e57bd 4584
20e4d407
DV		 4585 dev_priv->ips.max_delay = fstart;
4586 dev_priv->ips.min_delay = fmin;
4587 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4588
4589 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4590 fmax, fmin, fstart);
4591
4592 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4593
4594 /*
4595 * Interrupts will be enabled in ironlake_irq_postinstall
4596 */
4597
4598 I915_WRITE(VIDSTART, vstart);
4599 POSTING_READ(VIDSTART);
4600
4601 rgvmodectl |= MEMMODE_SWMODE_EN;
4602 I915_WRITE(MEMMODECTL, rgvmodectl);
4603
9270388e 4604 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4605 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4606 mdelay(1);
2b4e57bd 4607
91d14251 4608 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4609
7d81c3e0
VS		 4610 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4611 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4612 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4613 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4614 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4615
4616 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4617}
4618
91d14251 4619static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4620{
9270388e
DV		 4621 u16 rgvswctl;
4622
4623 spin_lock_irq(&mchdev_lock);
4624
4625 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4626
4627 /* Ack interrupts, disable EFC interrupt */
4628 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4629 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4630 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4631 I915_WRITE(DEIIR, DE_PCU_EVENT);
4632 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4633
4634 /* Go back to the starting frequency */
91d14251 4635 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4636 mdelay(1);
2b4e57bd
ED		 4637 rgvswctl |= MEMCTL_CMD_STS;
4638 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4639 mdelay(1);
2b4e57bd 4640
9270388e 4641 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4642}
4643
acbe9475
DV		 4644/* There's a funny hw issue where the hw returns all 0 when reading from
4645 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4646 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4647 * all limits and the gpu stuck at whatever frequency it is at atm).
4648 */
74ef1173 4649static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4650{
7b9e0ae6 4651 u32 limits;
2b4e57bd 4652
20b46e59
DV		 4653 /* Only set the down limit when we've reached the lowest level to avoid
4654 * getting more interrupts, otherwise leave this clear. This prevents a
4655 * race in the hw when coming out of rc6: There's a tiny window where
4656 * the hw runs at the minimal clock before selecting the desired
4657 * frequency, if the down threshold expires in that window we will not
4658 * receive a down interrupt. */
2d1fe073 4659 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4660 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4661 if (val <= dev_priv->rps.min_freq_softlimit)
4662 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4663 } else {
4664 limits = dev_priv->rps.max_freq_softlimit << 24;
4665 if (val <= dev_priv->rps.min_freq_softlimit)
4666 limits |= dev_priv->rps.min_freq_softlimit << 16;
4667 }
20b46e59
DV		 4668
4669 return limits;
4670}
4671
dd75fdc8
CW		 4672static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4673{
4674 int new_power;
8a586437
AG		 4675 u32 threshold_up = 0, threshold_down = 0; /* in % */
4676 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4677
4678 new_power = dev_priv->rps.power;
4679 switch (dev_priv->rps.power) {
4680 case LOW_POWER:
a72b5623
CW		 4681 if (val > dev_priv->rps.efficient_freq + 1 &&
4682 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4683 new_power = BETWEEN;
4684 break;
4685
4686 case BETWEEN:
a72b5623
CW		 4687 if (val <= dev_priv->rps.efficient_freq &&
4688 val < dev_priv->rps.cur_freq)
dd75fdc8 4689 new_power = LOW_POWER;
a72b5623
CW		 4690 else if (val >= dev_priv->rps.rp0_freq &&
4691 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4692 new_power = HIGH_POWER;
4693 break;
4694
4695 case HIGH_POWER:
a72b5623
CW		 4696 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4697 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4698 new_power = BETWEEN;
4699 break;
4700 }
4701 /* Max/min bins are special */
aed242ff 4702 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4703 new_power = LOW_POWER;
aed242ff 4704 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4705 new_power = HIGH_POWER;
4706 if (new_power == dev_priv->rps.power)
4707 return;
4708
4709 /* Note the units here are not exactly 1us, but 1280ns. */
4710 switch (new_power) {
4711 case LOW_POWER:
4712 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4713 ei_up = 16000;
4714 threshold_up = 95;
dd75fdc8
CW		 4715
4716 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4717 ei_down = 32000;
4718 threshold_down = 85;
dd75fdc8
CW		 4719 break;
4720
4721 case BETWEEN:
4722 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4723 ei_up = 13000;
4724 threshold_up = 90;
dd75fdc8
CW		 4725
4726 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4727 ei_down = 32000;
4728 threshold_down = 75;
dd75fdc8
CW		 4729 break;
4730
4731 case HIGH_POWER:
4732 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4733 ei_up = 10000;
4734 threshold_up = 85;
dd75fdc8
CW		 4735
4736 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4737 ei_down = 32000;
4738 threshold_down = 60;
dd75fdc8
CW		 4739 break;
4740 }
4741
8a586437 4742 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4743 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4744 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4745 GT_INTERVAL_FROM_US(dev_priv,
4746 ei_up * threshold_up / 100));
8a586437
AG		 4747
4748 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4749 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4750 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4751 GT_INTERVAL_FROM_US(dev_priv,
4752 ei_down * threshold_down / 100));
4753
4754 I915_WRITE(GEN6_RP_CONTROL,
4755 GEN6_RP_MEDIA_TURBO |
4756 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4757 GEN6_RP_MEDIA_IS_GFX |
4758 GEN6_RP_ENABLE |
4759 GEN6_RP_UP_BUSY_AVG |
4760 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4761
dd75fdc8 4762 dev_priv->rps.power = new_power;
8fb55197
CW		 4763 dev_priv->rps.up_threshold = threshold_up;
4764 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4765 dev_priv->rps.last_adj = 0;
4766}
4767
2876ce73
CW		 4768static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4769{
4770 u32 mask = 0;
4771
4772 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4773 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4774 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4775 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4776
7b3c29f6
CW		 4777 mask &= dev_priv->pm_rps_events;
4778
59d02a1f 4779 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4780}
4781
b8a5ff8d
JM		 4782/* gen6_set_rps is called to update the frequency request, but should also be
4783 * called when the range (min_delay and max_delay) is modified so that we can
4784 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4785static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4786{
23eafea6 4787 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4788 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4789 return;
4790
4fc688ce 4791 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4792 WARN_ON(val > dev_priv->rps.max_freq);
4793 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4794
eb64cad1
CW		 4795 /* min/max delay may still have been modified so be sure to
4796 * write the limits value.
4797 */
4798 if (val != dev_priv->rps.cur_freq) {
4799 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4800
dc97997a 4801 if (IS_GEN9(dev_priv))
5704195c
AG		 4802 I915_WRITE(GEN6_RPNSWREQ,
4803 GEN9_FREQUENCY(val));
dc97997a 4804 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4805 I915_WRITE(GEN6_RPNSWREQ,
4806 HSW_FREQUENCY(val));
4807 else
4808 I915_WRITE(GEN6_RPNSWREQ,
4809 GEN6_FREQUENCY(val) |
4810 GEN6_OFFSET(0) |
4811 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4812 }
7b9e0ae6 4813
7b9e0ae6
CW		 4814 /* Make sure we continue to get interrupts
4815 * until we hit the minimum or maximum frequencies.
4816 */
74ef1173 4817 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4818 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4819
d5570a72
BW		 4820 POSTING_READ(GEN6_RPNSWREQ);
4821
b39fb297 4822 dev_priv->rps.cur_freq = val;
0f94592e 4823 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4824}
4825
dc97997a 4826static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4827{
ffe02b40 4828 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4829 WARN_ON(val > dev_priv->rps.max_freq);
4830 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4831
dc97997a 4832 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4833 "Odd GPU freq value\n"))
4834 val &= ~1;
4835
cd25dd5b
D		 4836 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4837
8fb55197 4838 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4839 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4840 if (!IS_CHERRYVIEW(dev_priv))
4841 gen6_set_rps_thresholds(dev_priv, val);
4842 }
ffe02b40 4843
ffe02b40
VS		 4844 dev_priv->rps.cur_freq = val;
4845 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4846}
4847
a7f6e231 4848/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4849 *
4850 * * If Gfx is Idle, then
a7f6e231
D		 4851 * 1. Forcewake Media well.
4852 * 2. Request idle freq.
4853 * 3. Release Forcewake of Media well.
76c3552f
D		 4854*/
4855static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4856{
aed242ff 4857 u32 val = dev_priv->rps.idle_freq;
5549d25f 4858
aed242ff 4859 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4860 return;
4861
a7f6e231
D		 4862 /* Wake up the media well, as that takes a lot less
4863 * power than the Render well. */
4864 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4865 valleyview_set_rps(dev_priv, val);
a7f6e231 4866 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4867}
4868
43cf3bf0
CW		 4869void gen6_rps_busy(struct drm_i915_private *dev_priv)
4870{
4871 mutex_lock(&dev_priv->rps.hw_lock);
4872 if (dev_priv->rps.enabled) {
4873 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4874 gen6_rps_reset_ei(dev_priv);
4875 I915_WRITE(GEN6_PMINTRMSK,
4876 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 4877
c33d247d
CW		 4878 gen6_enable_rps_interrupts(dev_priv);
4879
2b83c4c4
MW		 4880 /* Ensure we start at the user's desired frequency */
4881 intel_set_rps(dev_priv,
4882 clamp(dev_priv->rps.cur_freq,
4883 dev_priv->rps.min_freq_softlimit,
4884 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 4885 }
4886 mutex_unlock(&dev_priv->rps.hw_lock);
4887}
4888
b29c19b6
CW		 4889void gen6_rps_idle(struct drm_i915_private *dev_priv)
4890{
c33d247d
CW		 4891 /* Flush our bottom-half so that it does not race with us
4892 * setting the idle frequency and so that it is bounded by
4893 * our rpm wakeref. And then disable the interrupts to stop any
4894 * futher RPS reclocking whilst we are asleep.
4895 */
4896 gen6_disable_rps_interrupts(dev_priv);
4897
b29c19b6 4898 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4899 if (dev_priv->rps.enabled) {
dc97997a 4900 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4901 vlv_set_rps_idle(dev_priv);
7526ed79 4902 else
dc97997a 4903 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4904 dev_priv->rps.last_adj = 0;
12c100bf
VS		 4905 I915_WRITE(GEN6_PMINTRMSK,
4906 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 4907 }
8d3afd7d 4908 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4909
8d3afd7d 4910 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4911 while (!list_empty(&dev_priv->rps.clients))
4912 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4913 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4914}
4915
1854d5ca 4916void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4917 struct intel_rps_client *rps,
4918 unsigned long submitted)
b29c19b6 4919{
8d3afd7d
CW		 4920 /* This is intentionally racy! We peek at the state here, then
4921 * validate inside the RPS worker.
4922 */
67d97da3 4923 if (!(dev_priv->gt.awake &&
8d3afd7d 4924 dev_priv->rps.enabled &&
29ecd78d 4925 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 4926 return;
43cf3bf0 4927
e61b9958
CW		 4928 /* Force a RPS boost (and don't count it against the client) if
4929 * the GPU is severely congested.
4930 */
d0bc54f2 4931 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4932 rps = NULL;
4933
8d3afd7d
CW		 4934 spin_lock(&dev_priv->rps.client_lock);
4935 if (rps == NULL || list_empty(&rps->link)) {
4936 spin_lock_irq(&dev_priv->irq_lock);
4937 if (dev_priv->rps.interrupts_enabled) {
4938 dev_priv->rps.client_boost = true;
c33d247d 4939 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 4940 }
4941 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4942
2e1b8730
CW		 4943 if (rps != NULL) {
4944 list_add(&rps->link, &dev_priv->rps.clients);
4945 rps->boosts++;
1854d5ca
CW		 4946 } else
4947 dev_priv->rps.boosts++;
c0951f0c 4948 }
8d3afd7d 4949 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4950}
4951
dc97997a 4952void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4953{
dc97997a
CW		 4954 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4955 valleyview_set_rps(dev_priv, val);
ffe02b40 4956 else
dc97997a 4957 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4958}
4959
dc97997a 4960static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4961{
20e49366 4962 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4963 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4964}
4965
dc97997a 4966static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4967{
2030d684
AG		 4968 I915_WRITE(GEN6_RP_CONTROL, 0);
4969}
4970
dc97997a 4971static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4972{
d20d4f0c 4973 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4974 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4975 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4976}
4977
dc97997a 4978static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4979{
38807746
D		 4980 I915_WRITE(GEN6_RC_CONTROL, 0);
4981}
4982
dc97997a 4983static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4984{
98a2e5f9
D		 4985 /* we're doing forcewake before Disabling RC6,
4986 * This what the BIOS expects when going into suspend */
59bad947 4987 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4988
44fc7d5c 4989 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4990
59bad947 4991 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4992}
4993
dc97997a 4994static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4995{
dc97997a 4996 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4997 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4998 mode = GEN6_RC_CTL_RC6_ENABLE;
4999 else
5000 mode = 0;
5001 }
dc97997a 5002 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5003 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5004 "RC6 %s RC6p %s RC6pp %s\n",
5005 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5006 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5007 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5008
5009 else
b99d49cc
ID		 5010 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5011 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5012}
5013
dc97997a 5014static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5015{
72e96d64 5016 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5017 bool enable_rc6 = true;
5018 unsigned long rc6_ctx_base;
fc619841
ID		 5019 u32 rc_ctl;
5020 int rc_sw_target;
5021
5022 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5023 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5024 RC_SW_TARGET_STATE_SHIFT;
5025 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5026 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5027 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5028 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5029 rc_sw_target);
274008e8
SAK		 5030
5031 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5032 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5033 enable_rc6 = false;
5034 }
5035
5036 /*
5037 * The exact context size is not known for BXT, so assume a page size
5038 * for this check.
5039 */
5040 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5041 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5042 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5043 ggtt->stolen_reserved_size))) {
b99d49cc 5044 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5045 enable_rc6 = false;
5046 }
5047
5048 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5049 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5050 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5051 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5052 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5053 enable_rc6 = false;
5054 }
5055
fc619841
ID		 5056 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5057 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5058 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5059 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5060 enable_rc6 = false;
5061 }
5062
5063 if (!I915_READ(GEN6_GFXPAUSE)) {
5064 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5065 enable_rc6 = false;
5066 }
5067
5068 if (!I915_READ(GEN8_MISC_CTRL0)) {
5069 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5070 enable_rc6 = false;
5071 }
5072
5073 return enable_rc6;
5074}
5075
dc97997a 5076int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5077{
e7d66d89 5078 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5079 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5080 return 0;
5081
274008e8
SAK		 5082 if (!enable_rc6)
5083 return 0;
5084
dc97997a 5085 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5086 DRM_INFO("RC6 disabled by BIOS\n");
5087 return 0;
5088 }
5089
456470eb 5090 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5091 if (enable_rc6 >= 0) {
5092 int mask;
5093
dc97997a 5094 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5095 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5096 INTEL_RC6pp_ENABLE;
5097 else
5098 mask = INTEL_RC6_ENABLE;
5099
5100 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5101 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5102 "(requested %d, valid %d)\n",
5103 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5104
5105 return enable_rc6 & mask;
5106 }
2b4e57bd 5107
dc97997a 5108 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5109 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5110
5111 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5112}
5113
dc97997a 5114static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5115{
5116 /* All of these values are in units of 50MHz */
773ea9a8 5117
93ee2920 5118 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5119 if (IS_BROXTON(dev_priv)) {
773ea9a8 5120 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5121 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5122 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5123 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5124 } else {
773ea9a8 5125 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5126 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5127 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5128 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5129 }
3280e8b0 5130 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5131 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5132
93ee2920 5133 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5134 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5135 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5136 u32 ddcc_status = 0;
5137
5138 if (sandybridge_pcode_read(dev_priv,
5139 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5140 &ddcc_status) == 0)
93ee2920 5141 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5142 clamp_t(u8,
5143 ((ddcc_status >> 8) & 0xff),
5144 dev_priv->rps.min_freq,
5145 dev_priv->rps.max_freq);
93ee2920
TR		 5146 }
5147
dc97997a 5148 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5149 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5150 * the natural hardware unit for SKL
5151 */
c5e0688c
AG		 5152 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5153 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5154 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5155 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5156 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5157 }
3280e8b0
BW		 5158}
5159
3a45b05c
CW		 5160static void reset_rps(struct drm_i915_private *dev_priv,
5161 void (*set)(struct drm_i915_private *, u8))
5162{
5163 u8 freq = dev_priv->rps.cur_freq;
5164
5165 /* force a reset */
5166 dev_priv->rps.power = -1;
5167 dev_priv->rps.cur_freq = -1;
5168
5169 set(dev_priv, freq);
5170}
5171
b6fef0ef 5172/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5173static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5174{
b6fef0ef
JB		 5175 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5176
23eafea6 5177 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5178 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5179 /*
5180 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5181 * clear out the Control register just to avoid inconsitency
5182 * with debugfs interface, which will show Turbo as enabled
5183 * only and that is not expected by the User after adding the
5184 * WaGsvDisableTurbo. Apart from this there is no problem even
5185 * if the Turbo is left enabled in the Control register, as the
5186 * Up/Down interrupts would remain masked.
5187 */
dc97997a 5188 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5189 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5190 return;
5191 }
5192
0beb059a
AG		 5193 /* Program defaults and thresholds for RPS*/
5194 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5195 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5196
5197 /* 1 second timeout*/
5198 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5199 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5200
b6fef0ef 5201 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5202
0beb059a
AG		 5203 /* Leaning on the below call to gen6_set_rps to program/setup the
5204 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5205 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5206 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5207
5208 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5209}
5210
dc97997a 5211static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5212{
e2f80391 5213 struct intel_engine_cs *engine;
20e49366 5214 uint32_t rc6_mask = 0;
20e49366
ZW		 5215
5216 /* 1a: Software RC state - RC0 */
5217 I915_WRITE(GEN6_RC_STATE, 0);
5218
5219 /* 1b: Get forcewake during program sequence. Although the driver
5220 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5221 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5222
5223 /* 2a: Disable RC states. */
5224 I915_WRITE(GEN6_RC_CONTROL, 0);
5225
5226 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5227
5228 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5229 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5230 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5231 else
5232 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5233 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5234 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5235 for_each_engine(engine, dev_priv)
e2f80391 5236 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5237
1a3d1898 5238 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5239 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5240
20e49366 5241 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5242
38c23527
ZW		 5243 /* 2c: Program Coarse Power Gating Policies. */
5244 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5245 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5246
20e49366 5247 /* 3a: Enable RC6 */
dc97997a 5248 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5249 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5250 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5251 /* WaRsUseTimeoutMode */
dc97997a
CW		 5252 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5253 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5254 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5255 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5256 GEN7_RC_CTL_TO_MODE |
5257 rc6_mask);
3e7732a0
SAK		 5258 } else {
5259 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5260 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5261 GEN6_RC_CTL_EI_MODE(1) |
5262 rc6_mask);
3e7732a0 5263 }
20e49366 5264
cb07bae0
SK		 5265 /*
5266 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5267 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5268 */
dc97997a 5269 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5270 I915_WRITE(GEN9_PG_ENABLE, 0);
5271 else
5272 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5273 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5274
59bad947 5275 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5276}
5277
dc97997a 5278static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5279{
e2f80391 5280 struct intel_engine_cs *engine;
93ee2920 5281 uint32_t rc6_mask = 0;
6edee7f3
BW		 5282
5283 /* 1a: Software RC state - RC0 */
5284 I915_WRITE(GEN6_RC_STATE, 0);
5285
5286 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5287 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5288 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5289
5290 /* 2a: Disable RC states. */
5291 I915_WRITE(GEN6_RC_CONTROL, 0);
5292
6edee7f3
BW		 5293 /* 2b: Program RC6 thresholds.*/
5294 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5295 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5296 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5297 for_each_engine(engine, dev_priv)
e2f80391 5298 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5299 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5300 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5301 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5302 else
5303 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5304
5305 /* 3: Enable RC6 */
dc97997a 5306 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5307 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5308 intel_print_rc6_info(dev_priv, rc6_mask);
5309 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5310 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5311 GEN7_RC_CTL_TO_MODE |
5312 rc6_mask);
5313 else
5314 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5315 GEN6_RC_CTL_EI_MODE(1) |
5316 rc6_mask);
6edee7f3
BW		 5317
5318 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5319 I915_WRITE(GEN6_RPNSWREQ,
5320 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5321 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5322 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5323 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5324 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5325
5326 /* Docs recommend 900MHz, and 300 MHz respectively */
5327 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5328 dev_priv->rps.max_freq_softlimit << 24 |
5329 dev_priv->rps.min_freq_softlimit << 16);
5330
5331 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5332 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5333 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5334 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5335
5336 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5337
5338 /* 5: Enable RPS */
7526ed79
DV		 5339 I915_WRITE(GEN6_RP_CONTROL,
5340 GEN6_RP_MEDIA_TURBO |
5341 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5342 GEN6_RP_MEDIA_IS_GFX |
5343 GEN6_RP_ENABLE |
5344 GEN6_RP_UP_BUSY_AVG |
5345 GEN6_RP_DOWN_IDLE_AVG);
5346
5347 /* 6: Ring frequency + overclocking (our driver does this later */
5348
3a45b05c 5349 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5350
59bad947 5351 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5352}
5353
dc97997a 5354static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5355{
e2f80391 5356 struct intel_engine_cs *engine;
99ac9612 5357 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5358 u32 gtfifodbg;
2b4e57bd 5359 int rc6_mode;
b4ac5afc 5360 int ret;
2b4e57bd 5361
4fc688ce 5362 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5363
2b4e57bd
ED		 5364 /* Here begins a magic sequence of register writes to enable
5365 * auto-downclocking.
5366 *
5367 * Perhaps there might be some value in exposing these to
5368 * userspace...
5369 */
5370 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5371
5372 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5373 gtfifodbg = I915_READ(GTFIFODBG);
5374 if (gtfifodbg) {
2b4e57bd
ED		 5375 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5376 I915_WRITE(GTFIFODBG, gtfifodbg);
5377 }
5378
59bad947 5379 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5380
5381 /* disable the counters and set deterministic thresholds */
5382 I915_WRITE(GEN6_RC_CONTROL, 0);
5383
5384 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5385 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5386 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5387 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5388 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5389
b4ac5afc 5390 for_each_engine(engine, dev_priv)
e2f80391 5391 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5392
5393 I915_WRITE(GEN6_RC_SLEEP, 0);
5394 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5395 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5396 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5397 else
5398 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5399 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5400 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5401
5a7dc92a 5402 /* Check if we are enabling RC6 */
dc97997a 5403 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5404 if (rc6_mode & INTEL_RC6_ENABLE)
5405 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5406
5a7dc92a 5407 /* We don't use those on Haswell */
dc97997a 5408 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5409 if (rc6_mode & INTEL_RC6p_ENABLE)
5410 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5411
5a7dc92a
ED		 5412 if (rc6_mode & INTEL_RC6pp_ENABLE)
5413 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5414 }
2b4e57bd 5415
dc97997a 5416 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5417
5418 I915_WRITE(GEN6_RC_CONTROL,
5419 rc6_mask |
5420 GEN6_RC_CTL_EI_MODE(1) |
5421 GEN6_RC_CTL_HW_ENABLE);
5422
dd75fdc8
CW		 5423 /* Power down if completely idle for over 50ms */
5424 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5425 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5426
42c0526c 5427 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5428 if (ret)
42c0526c 5429 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5430
3a45b05c 5431 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5432
31643d54
BW		 5433 rc6vids = 0;
5434 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5435 if (IS_GEN6(dev_priv) && ret) {
31643d54 5436 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5437 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5438 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5439 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5440 rc6vids &= 0xffff00;
5441 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5442 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5443 if (ret)
5444 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5445 }
5446
59bad947 5447 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5448}
5449
fb7404e8 5450static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5451{
5452 int min_freq = 15;
3ebecd07
CW		 5453 unsigned int gpu_freq;
5454 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5455 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5456 int scaling_factor = 180;
eda79642 5457 struct cpufreq_policy *policy;
2b4e57bd 5458
4fc688ce 5459 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5460
eda79642
BW		 5461 policy = cpufreq_cpu_get(0);
5462 if (policy) {
5463 max_ia_freq = policy->cpuinfo.max_freq;
5464 cpufreq_cpu_put(policy);
5465 } else {
5466 /*
5467 * Default to measured freq if none found, PCU will ensure we
5468 * don't go over
5469 */
2b4e57bd 5470 max_ia_freq = tsc_khz;
eda79642 5471 }
2b4e57bd
ED		 5472
5473 /* Convert from kHz to MHz */
5474 max_ia_freq /= 1000;
5475
153b4b95 5476 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5477 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5478 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5479
dc97997a 5480 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5481 /* Convert GT frequency to 50 HZ units */
5482 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5483 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5484 } else {
5485 min_gpu_freq = dev_priv->rps.min_freq;
5486 max_gpu_freq = dev_priv->rps.max_freq;
5487 }
5488
2b4e57bd
ED		 5489 /*
5490 * For each potential GPU frequency, load a ring frequency we'd like
5491 * to use for memory access. We do this by specifying the IA frequency
5492 * the PCU should use as a reference to determine the ring frequency.
5493 */
4c8c7743
AG		 5494 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5495 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5496 unsigned int ia_freq = 0, ring_freq = 0;
5497
dc97997a 5498 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5499 /*
5500 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5501 * No floor required for ring frequency on SKL.
5502 */
5503 ring_freq = gpu_freq;
dc97997a 5504 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5505 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5506 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5507 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5508 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5509 ring_freq = max(min_ring_freq, ring_freq);
5510 /* leave ia_freq as the default, chosen by cpufreq */
5511 } else {
5512 /* On older processors, there is no separate ring
5513 * clock domain, so in order to boost the bandwidth
5514 * of the ring, we need to upclock the CPU (ia_freq).
5515 *
5516 * For GPU frequencies less than 750MHz,
5517 * just use the lowest ring freq.
5518 */
5519 if (gpu_freq < min_freq)
5520 ia_freq = 800;
5521 else
5522 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5523 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5524 }
2b4e57bd 5525
42c0526c
BW		 5526 sandybridge_pcode_write(dev_priv,
5527 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5528 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5529 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5530 gpu_freq);
2b4e57bd 5531 }
2b4e57bd
ED		 5532}
5533
03af2045 5534static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5535{
5536 u32 val, rp0;
5537
5b5929cb 5538 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5539
dc97997a 5540 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5541 case 8:
5542 /* (2 * 4) config */
5543 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5544 break;
5545 case 12:
5546 /* (2 * 6) config */
5547 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5548 break;
5549 case 16:
5550 /* (2 * 8) config */
5551 default:
5552 /* Setting (2 * 8) Min RP0 for any other combination */
5553 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5554 break;
095acd5f 5555 }
5b5929cb
JN		 5556
5557 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5558
2b6b3a09
D		 5559 return rp0;
5560}
5561
5562static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5563{
5564 u32 val, rpe;
5565
5566 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5567 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5568
5569 return rpe;
5570}
5571
7707df4a
D		 5572static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5573{
5574 u32 val, rp1;
5575
5b5929cb
JN		 5576 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5577 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5578
7707df4a
D		 5579 return rp1;
5580}
5581
f8f2b001
D		 5582static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5583{
5584 u32 val, rp1;
5585
5586 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5587
5588 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5589
5590 return rp1;
5591}
5592
03af2045 5593static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5594{
5595 u32 val, rp0;
5596
64936258 5597 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5598
5599 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5600 /* Clamp to max */
5601 rp0 = min_t(u32, rp0, 0xea);
5602
5603 return rp0;
5604}
5605
5606static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5607{
5608 u32 val, rpe;
5609
64936258 5610 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5611 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5612 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5613 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5614
5615 return rpe;
5616}
5617
03af2045 5618static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5619{
36146035
ID		 5620 u32 val;
5621
5622 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5623 /*
5624 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5625 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5626 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5627 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5628 * to make sure it matches what Punit accepts.
5629 */
5630 return max_t(u32, val, 0xc0);
0a073b84
JB		 5631}
5632
ae48434c
ID		 5633/* Check that the pctx buffer wasn't move under us. */
5634static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5635{
5636 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5637
5638 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5639 dev_priv->vlv_pctx->stolen->start);
5640}
5641
38807746
D		 5642
5643/* Check that the pcbr address is not empty. */
5644static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5645{
5646 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5647
5648 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5649}
5650
dc97997a 5651static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5652{
62106b4f 5653 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5654 unsigned long pctx_paddr, paddr;
38807746
D		 5655 u32 pcbr;
5656 int pctx_size = 32*1024;
5657
38807746
D		 5658 pcbr = I915_READ(VLV_PCBR);
5659 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5660 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5661 paddr = (dev_priv->mm.stolen_base +
62106b4f 5662 (ggtt->stolen_size - pctx_size));
38807746
D		 5663
5664 pctx_paddr = (paddr & (~4095));
5665 I915_WRITE(VLV_PCBR, pctx_paddr);
5666 }
ce611ef8
VS		 5667
5668 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5669}
5670
dc97997a 5671static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5672{
c9cddffc
JB		 5673 struct drm_i915_gem_object *pctx;
5674 unsigned long pctx_paddr;
5675 u32 pcbr;
5676 int pctx_size = 24*1024;
5677
91c8a326 5678 mutex_lock(&dev_priv->drm.struct_mutex);
17b0c1f7 5679
c9cddffc
JB		 5680 pcbr = I915_READ(VLV_PCBR);
5681 if (pcbr) {
5682 /* BIOS set it up already, grab the pre-alloc'd space */
5683 int pcbr_offset;
5684
5685 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5686 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5687 pcbr_offset,
190d6cd5 5688 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5689 pctx_size);
5690 goto out;
5691 }
5692
ce611ef8
VS		 5693 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5694
c9cddffc
JB		 5695 /*
5696 * From the Gunit register HAS:
5697 * The Gfx driver is expected to program this register and ensure
5698 * proper allocation within Gfx stolen memory. For example, this
5699 * register should be programmed such than the PCBR range does not
5700 * overlap with other ranges, such as the frame buffer, protected
5701 * memory, or any other relevant ranges.
5702 */
91c8a326 5703 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5704 if (!pctx) {
5705 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5706 goto out;
c9cddffc
JB		 5707 }
5708
5709 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5710 I915_WRITE(VLV_PCBR, pctx_paddr);
5711
5712out:
ce611ef8 5713 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5714 dev_priv->vlv_pctx = pctx;
91c8a326 5715 mutex_unlock(&dev_priv->drm.struct_mutex);
c9cddffc
JB		 5716}
5717
dc97997a 5718static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5719{
ae48434c
ID		 5720 if (WARN_ON(!dev_priv->vlv_pctx))
5721 return;
5722
34911fd3 5723 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5724 dev_priv->vlv_pctx = NULL;
5725}
5726
c30fec65
VS		 5727static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5728{
5729 dev_priv->rps.gpll_ref_freq =
5730 vlv_get_cck_clock(dev_priv, "GPLL ref",
5731 CCK_GPLL_CLOCK_CONTROL,
5732 dev_priv->czclk_freq);
5733
5734 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5735 dev_priv->rps.gpll_ref_freq);
5736}
5737
dc97997a 5738static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5739{
2bb25c17 5740 u32 val;
4e80519e 5741
dc97997a 5742 valleyview_setup_pctx(dev_priv);
4e80519e 5743
c30fec65
VS		 5744 vlv_init_gpll_ref_freq(dev_priv);
5745
2bb25c17
VS		 5746 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5747 switch ((val >> 6) & 3) {
5748 case 0:
5749 case 1:
5750 dev_priv->mem_freq = 800;
5751 break;
5752 case 2:
5753 dev_priv->mem_freq = 1066;
5754 break;
5755 case 3:
5756 dev_priv->mem_freq = 1333;
5757 break;
5758 }
80b83b62 5759 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5760
4e80519e
ID		 5761 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5762 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5763 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5764 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5765 dev_priv->rps.max_freq);
5766
5767 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5768 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5769 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5770 dev_priv->rps.efficient_freq);
5771
f8f2b001
D		 5772 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5773 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5774 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5775 dev_priv->rps.rp1_freq);
5776
4e80519e
ID		 5777 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5778 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5779 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5780 dev_priv->rps.min_freq);
4e80519e
ID		 5781}
5782
dc97997a 5783static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5784{
2bb25c17 5785 u32 val;
2b6b3a09 5786
dc97997a 5787 cherryview_setup_pctx(dev_priv);
2b6b3a09 5788
c30fec65
VS		 5789 vlv_init_gpll_ref_freq(dev_priv);
5790
a580516d 5791 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5792 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5793 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5794
2bb25c17 5795 switch ((val >> 2) & 0x7) {
2bb25c17 5796 case 3:
2bb25c17
VS		 5797 dev_priv->mem_freq = 2000;
5798 break;
bfa7df01 5799 default:
2bb25c17
VS		 5800 dev_priv->mem_freq = 1600;
5801 break;
5802 }
80b83b62 5803 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5804
2b6b3a09
D		 5805 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5806 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5807 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5808 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5809 dev_priv->rps.max_freq);
5810
5811 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5812 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5813 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5814 dev_priv->rps.efficient_freq);
5815
7707df4a
D		 5816 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5817 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5818 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5819 dev_priv->rps.rp1_freq);
5820
5b7c91b7
D		 5821 /* PUnit validated range is only [RPe, RP0] */
5822 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5823 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5824 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5825 dev_priv->rps.min_freq);
5826
1c14762d
VS		 5827 WARN_ONCE((dev_priv->rps.max_freq |
5828 dev_priv->rps.efficient_freq |
5829 dev_priv->rps.rp1_freq |
5830 dev_priv->rps.min_freq) & 1,
5831 "Odd GPU freq values\n");
38807746
D		 5832}
5833
dc97997a 5834static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5835{
dc97997a 5836 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5837}
5838
dc97997a 5839static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5840{
e2f80391 5841 struct intel_engine_cs *engine;
2b6b3a09 5842 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5843
5844 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5845
297b32ec
VS		 5846 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5847 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5848 if (gtfifodbg) {
5849 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5850 gtfifodbg);
5851 I915_WRITE(GTFIFODBG, gtfifodbg);
5852 }
5853
5854 cherryview_check_pctx(dev_priv);
5855
5856 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5857 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5858 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5859
160614a2
VS		 5860 /* Disable RC states. */
5861 I915_WRITE(GEN6_RC_CONTROL, 0);
5862
38807746
D		 5863 /* 2a: Program RC6 thresholds.*/
5864 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5865 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5866 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5867
b4ac5afc 5868 for_each_engine(engine, dev_priv)
e2f80391 5869 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5870 I915_WRITE(GEN6_RC_SLEEP, 0);
5871
f4f71c7d
D		 5872 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5873 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5874
5875 /* allows RC6 residency counter to work */
5876 I915_WRITE(VLV_COUNTER_CONTROL,
5877 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5878 VLV_MEDIA_RC6_COUNT_EN |
5879 VLV_RENDER_RC6_COUNT_EN));
5880
5881 /* For now we assume BIOS is allocating and populating the PCBR */
5882 pcbr = I915_READ(VLV_PCBR);
5883
38807746 5884 /* 3: Enable RC6 */
dc97997a
CW		 5885 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5886 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5887 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5888
5889 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5890
2b6b3a09 5891 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5893 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5894 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5895 I915_WRITE(GEN6_RP_UP_EI, 66000);
5896 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5897
5898 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5899
5900 /* 5: Enable RPS */
5901 I915_WRITE(GEN6_RP_CONTROL,
5902 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5903 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5904 GEN6_RP_ENABLE |
5905 GEN6_RP_UP_BUSY_AVG |
5906 GEN6_RP_DOWN_IDLE_AVG);
5907
3ef62342
D		 5908 /* Setting Fixed Bias */
5909 val = VLV_OVERRIDE_EN |
5910 VLV_SOC_TDP_EN |
5911 CHV_BIAS_CPU_50_SOC_50;
5912 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5913
2b6b3a09
D		 5914 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5915
8d40c3ae
VS		 5916 /* RPS code assumes GPLL is used */
5917 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5918
742f491d 5919 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5920 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5921
3a45b05c 5922 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 5923
59bad947 5924 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5925}
5926
dc97997a 5927static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5928{
e2f80391 5929 struct intel_engine_cs *engine;
2a5913a8 5930 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5931
5932 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5933
ae48434c
ID		 5934 valleyview_check_pctx(dev_priv);
5935
297b32ec
VS		 5936 gtfifodbg = I915_READ(GTFIFODBG);
5937 if (gtfifodbg) {
f7d85c1e
JB		 5938 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5939 gtfifodbg);
0a073b84
JB		 5940 I915_WRITE(GTFIFODBG, gtfifodbg);
5941 }
5942
c8d9a590 5943 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5944 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5945
160614a2
VS		 5946 /* Disable RC states. */
5947 I915_WRITE(GEN6_RC_CONTROL, 0);
5948
cad725fe 5949 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5950 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5951 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5952 I915_WRITE(GEN6_RP_UP_EI, 66000);
5953 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5954
5955 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5956
5957 I915_WRITE(GEN6_RP_CONTROL,
5958 GEN6_RP_MEDIA_TURBO |
5959 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5960 GEN6_RP_MEDIA_IS_GFX |
5961 GEN6_RP_ENABLE |
5962 GEN6_RP_UP_BUSY_AVG |
5963 GEN6_RP_DOWN_IDLE_CONT);
5964
5965 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5966 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5967 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5968
b4ac5afc 5969 for_each_engine(engine, dev_priv)
e2f80391 5970 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5971
2f0aa304 5972 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5973
5974 /* allows RC6 residency counter to work */
49798eb2 5975 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5976 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5977 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5978 VLV_MEDIA_RC6_COUNT_EN |
5979 VLV_RENDER_RC6_COUNT_EN));
31685c25 5980
dc97997a 5981 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5982 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5983
dc97997a 5984 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5985
a2b23fe0 5986 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5987
3ef62342
D		 5988 /* Setting Fixed Bias */
5989 val = VLV_OVERRIDE_EN |
5990 VLV_SOC_TDP_EN |
5991 VLV_BIAS_CPU_125_SOC_875;
5992 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5993
64936258 5994 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5995
8d40c3ae
VS		 5996 /* RPS code assumes GPLL is used */
5997 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5998
742f491d 5999 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6000 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6001
3a45b05c 6002 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6003
59bad947 6004 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6005}
6006
dde18883
ED		 6007static unsigned long intel_pxfreq(u32 vidfreq)
6008{
6009 unsigned long freq;
6010 int div = (vidfreq & 0x3f0000) >> 16;
6011 int post = (vidfreq & 0x3000) >> 12;
6012 int pre = (vidfreq & 0x7);
6013
6014 if (!pre)
6015 return 0;
6016
6017 freq = ((div * 133333) / ((1<<post) * pre));
6018
6019 return freq;
6020}
6021
eb48eb00
DV		 6022static const struct cparams {
6023 u16 i;
6024 u16 t;
6025 u16 m;
6026 u16 c;
6027} cparams[] = {
6028 { 1, 1333, 301, 28664 },
6029 { 1, 1066, 294, 24460 },
6030 { 1, 800, 294, 25192 },
6031 { 0, 1333, 276, 27605 },
6032 { 0, 1066, 276, 27605 },
6033 { 0, 800, 231, 23784 },
6034};
6035
f531dcb2 6036static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6037{
6038 u64 total_count, diff, ret;
6039 u32 count1, count2, count3, m = 0, c = 0;
6040 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6041 int i;
6042
02d71956
DV		 6043 assert_spin_locked(&mchdev_lock);
6044
20e4d407 6045 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6046
6047 /* Prevent division-by-zero if we are asking too fast.
6048 * Also, we don't get interesting results if we are polling
6049 * faster than once in 10ms, so just return the saved value
6050 * in such cases.
6051 */
6052 if (diff1 <= 10)
20e4d407 6053 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6054
6055 count1 = I915_READ(DMIEC);
6056 count2 = I915_READ(DDREC);
6057 count3 = I915_READ(CSIEC);
6058
6059 total_count = count1 + count2 + count3;
6060
6061 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6062 if (total_count < dev_priv->ips.last_count1) {
6063 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6064 diff += total_count;
6065 } else {
20e4d407 6066 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6067 }
6068
6069 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6070 if (cparams[i].i == dev_priv->ips.c_m &&
6071 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6072 m = cparams[i].m;
6073 c = cparams[i].c;
6074 break;
6075 }
6076 }
6077
6078 diff = div_u64(diff, diff1);
6079 ret = ((m * diff) + c);
6080 ret = div_u64(ret, 10);
6081
20e4d407
DV		 6082 dev_priv->ips.last_count1 = total_count;
6083 dev_priv->ips.last_time1 = now;
eb48eb00 6084
20e4d407 6085 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6086
6087 return ret;
6088}
6089
f531dcb2
CW		 6090unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6091{
6092 unsigned long val;
6093
dc97997a 6094 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6095 return 0;
6096
6097 spin_lock_irq(&mchdev_lock);
6098
6099 val = __i915_chipset_val(dev_priv);
6100
6101 spin_unlock_irq(&mchdev_lock);
6102
6103 return val;
6104}
6105
eb48eb00
DV		 6106unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6107{
6108 unsigned long m, x, b;
6109 u32 tsfs;
6110
6111 tsfs = I915_READ(TSFS);
6112
6113 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6114 x = I915_READ8(TR1);
6115
6116 b = tsfs & TSFS_INTR_MASK;
6117
6118 return ((m * x) / 127) - b;
6119}
6120
d972d6ee
MK		 6121static int _pxvid_to_vd(u8 pxvid)
6122{
6123 if (pxvid == 0)
6124 return 0;
6125
6126 if (pxvid >= 8 && pxvid < 31)
6127 pxvid = 31;
6128
6129 return (pxvid + 2) * 125;
6130}
6131
6132static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6133{
d972d6ee
MK		 6134 const int vd = _pxvid_to_vd(pxvid);
6135 const int vm = vd - 1125;
6136
dc97997a 6137 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6138 return vm > 0 ? vm : 0;
6139
6140 return vd;
eb48eb00
DV		 6141}
6142
02d71956 6143static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6144{
5ed0bdf2 6145 u64 now, diff, diffms;
eb48eb00
DV		 6146 u32 count;
6147
02d71956 6148 assert_spin_locked(&mchdev_lock);
eb48eb00 6149
5ed0bdf2
TG		 6150 now = ktime_get_raw_ns();
6151 diffms = now - dev_priv->ips.last_time2;
6152 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6153
6154 /* Don't divide by 0 */
eb48eb00
DV		 6155 if (!diffms)
6156 return;
6157
6158 count = I915_READ(GFXEC);
6159
20e4d407
DV		 6160 if (count < dev_priv->ips.last_count2) {
6161 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6162 diff += count;
6163 } else {
20e4d407 6164 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6165 }
6166
20e4d407
DV		 6167 dev_priv->ips.last_count2 = count;
6168 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6169
6170 /* More magic constants... */
6171 diff = diff * 1181;
6172 diff = div_u64(diff, diffms * 10);
20e4d407 6173 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6174}
6175
02d71956
DV		 6176void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6177{
dc97997a 6178 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6179 return;
6180
9270388e 6181 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6182
6183 __i915_update_gfx_val(dev_priv);
6184
9270388e 6185 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6186}
6187
f531dcb2 6188static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6189{
6190 unsigned long t, corr, state1, corr2, state2;
6191 u32 pxvid, ext_v;
6192
02d71956
DV		 6193 assert_spin_locked(&mchdev_lock);
6194
616847e7 6195 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6196 pxvid = (pxvid >> 24) & 0x7f;
6197 ext_v = pvid_to_extvid(dev_priv, pxvid);
6198
6199 state1 = ext_v;
6200
6201 t = i915_mch_val(dev_priv);
6202
6203 /* Revel in the empirically derived constants */
6204
6205 /* Correction factor in 1/100000 units */
6206 if (t > 80)
6207 corr = ((t * 2349) + 135940);
6208 else if (t >= 50)
6209 corr = ((t * 964) + 29317);
6210 else /* < 50 */
6211 corr = ((t * 301) + 1004);
6212
6213 corr = corr * ((150142 * state1) / 10000 - 78642);
6214 corr /= 100000;
20e4d407 6215 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6216
6217 state2 = (corr2 * state1) / 10000;
6218 state2 /= 100; /* convert to mW */
6219
02d71956 6220 __i915_update_gfx_val(dev_priv);
eb48eb00 6221
20e4d407 6222 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6223}
6224
f531dcb2
CW		 6225unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6226{
6227 unsigned long val;
6228
dc97997a 6229 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6230 return 0;
6231
6232 spin_lock_irq(&mchdev_lock);
6233
6234 val = __i915_gfx_val(dev_priv);
6235
6236 spin_unlock_irq(&mchdev_lock);
6237
6238 return val;
6239}
6240
eb48eb00
DV		 6241/**
6242 * i915_read_mch_val - return value for IPS use
6243 *
6244 * Calculate and return a value for the IPS driver to use when deciding whether
6245 * we have thermal and power headroom to increase CPU or GPU power budget.
6246 */
6247unsigned long i915_read_mch_val(void)
6248{
6249 struct drm_i915_private *dev_priv;
6250 unsigned long chipset_val, graphics_val, ret = 0;
6251
9270388e 6252 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6253 if (!i915_mch_dev)
6254 goto out_unlock;
6255 dev_priv = i915_mch_dev;
6256
f531dcb2
CW		 6257 chipset_val = __i915_chipset_val(dev_priv);
6258 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6259
6260 ret = chipset_val + graphics_val;
6261
6262out_unlock:
9270388e 6263 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6264
6265 return ret;
6266}
6267EXPORT_SYMBOL_GPL(i915_read_mch_val);
6268
6269/**
6270 * i915_gpu_raise - raise GPU frequency limit
6271 *
6272 * Raise the limit; IPS indicates we have thermal headroom.
6273 */
6274bool i915_gpu_raise(void)
6275{
6276 struct drm_i915_private *dev_priv;
6277 bool ret = true;
6278
9270388e 6279 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6280 if (!i915_mch_dev) {
6281 ret = false;
6282 goto out_unlock;
6283 }
6284 dev_priv = i915_mch_dev;
6285
20e4d407
DV		 6286 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6287 dev_priv->ips.max_delay--;
eb48eb00
DV		 6288
6289out_unlock:
9270388e 6290 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6291
6292 return ret;
6293}
6294EXPORT_SYMBOL_GPL(i915_gpu_raise);
6295
6296/**
6297 * i915_gpu_lower - lower GPU frequency limit
6298 *
6299 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6300 * frequency maximum.
6301 */
6302bool i915_gpu_lower(void)
6303{
6304 struct drm_i915_private *dev_priv;
6305 bool ret = true;
6306
9270388e 6307 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6308 if (!i915_mch_dev) {
6309 ret = false;
6310 goto out_unlock;
6311 }
6312 dev_priv = i915_mch_dev;
6313
20e4d407
DV		 6314 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6315 dev_priv->ips.max_delay++;
eb48eb00
DV		 6316
6317out_unlock:
9270388e 6318 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6319
6320 return ret;
6321}
6322EXPORT_SYMBOL_GPL(i915_gpu_lower);
6323
6324/**
6325 * i915_gpu_busy - indicate GPU business to IPS
6326 *
6327 * Tell the IPS driver whether or not the GPU is busy.
6328 */
6329bool i915_gpu_busy(void)
6330{
eb48eb00
DV		 6331 bool ret = false;
6332
9270388e 6333 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6334 if (i915_mch_dev)
6335 ret = i915_mch_dev->gt.awake;
9270388e 6336 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6337
6338 return ret;
6339}
6340EXPORT_SYMBOL_GPL(i915_gpu_busy);
6341
6342/**
6343 * i915_gpu_turbo_disable - disable graphics turbo
6344 *
6345 * Disable graphics turbo by resetting the max frequency and setting the
6346 * current frequency to the default.
6347 */
6348bool i915_gpu_turbo_disable(void)
6349{
6350 struct drm_i915_private *dev_priv;
6351 bool ret = true;
6352
9270388e 6353 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6354 if (!i915_mch_dev) {
6355 ret = false;
6356 goto out_unlock;
6357 }
6358 dev_priv = i915_mch_dev;
6359
20e4d407 6360 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6361
91d14251 6362 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6363 ret = false;
6364
6365out_unlock:
9270388e 6366 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6367
6368 return ret;
6369}
6370EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6371
6372/**
6373 * Tells the intel_ips driver that the i915 driver is now loaded, if
6374 * IPS got loaded first.
6375 *
6376 * This awkward dance is so that neither module has to depend on the
6377 * other in order for IPS to do the appropriate communication of
6378 * GPU turbo limits to i915.
6379 */
6380static void
6381ips_ping_for_i915_load(void)
6382{
6383 void (*link)(void);
6384
6385 link = symbol_get(ips_link_to_i915_driver);
6386 if (link) {
6387 link();
6388 symbol_put(ips_link_to_i915_driver);
6389 }
6390}
6391
6392void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6393{
02d71956
DV		 6394 /* We only register the i915 ips part with intel-ips once everything is
6395 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6396 spin_lock_irq(&mchdev_lock);
eb48eb00 6397 i915_mch_dev = dev_priv;
9270388e 6398 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6399
6400 ips_ping_for_i915_load();
6401}
6402
6403void intel_gpu_ips_teardown(void)
6404{
9270388e 6405 spin_lock_irq(&mchdev_lock);
eb48eb00 6406 i915_mch_dev = NULL;
9270388e 6407 spin_unlock_irq(&mchdev_lock);
eb48eb00 6408}
76c3552f 6409
dc97997a 6410static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6411{
dde18883
ED		 6412 u32 lcfuse;
6413 u8 pxw[16];
6414 int i;
6415
6416 /* Disable to program */
6417 I915_WRITE(ECR, 0);
6418 POSTING_READ(ECR);
6419
6420 /* Program energy weights for various events */
6421 I915_WRITE(SDEW, 0x15040d00);
6422 I915_WRITE(CSIEW0, 0x007f0000);
6423 I915_WRITE(CSIEW1, 0x1e220004);
6424 I915_WRITE(CSIEW2, 0x04000004);
6425
6426 for (i = 0; i < 5; i++)
616847e7 6427 I915_WRITE(PEW(i), 0);
dde18883 6428 for (i = 0; i < 3; i++)
616847e7 6429 I915_WRITE(DEW(i), 0);
dde18883
ED		 6430
6431 /* Program P-state weights to account for frequency power adjustment */
6432 for (i = 0; i < 16; i++) {
616847e7 6433 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6434 unsigned long freq = intel_pxfreq(pxvidfreq);
6435 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6436 PXVFREQ_PX_SHIFT;
6437 unsigned long val;
6438
6439 val = vid * vid;
6440 val *= (freq / 1000);
6441 val *= 255;
6442 val /= (127*127*900);
6443 if (val > 0xff)
6444 DRM_ERROR("bad pxval: %ld\n", val);
6445 pxw[i] = val;
6446 }
6447 /* Render standby states get 0 weight */
6448 pxw[14] = 0;
6449 pxw[15] = 0;
6450
6451 for (i = 0; i < 4; i++) {
6452 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6453 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6454 I915_WRITE(PXW(i), val);
dde18883
ED		 6455 }
6456
6457 /* Adjust magic regs to magic values (more experimental results) */
6458 I915_WRITE(OGW0, 0);
6459 I915_WRITE(OGW1, 0);
6460 I915_WRITE(EG0, 0x00007f00);
6461 I915_WRITE(EG1, 0x0000000e);
6462 I915_WRITE(EG2, 0x000e0000);
6463 I915_WRITE(EG3, 0x68000300);
6464 I915_WRITE(EG4, 0x42000000);
6465 I915_WRITE(EG5, 0x00140031);
6466 I915_WRITE(EG6, 0);
6467 I915_WRITE(EG7, 0);
6468
6469 for (i = 0; i < 8; i++)
616847e7 6470 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6471
6472 /* Enable PMON + select events */
6473 I915_WRITE(ECR, 0x80000019);
6474
6475 lcfuse = I915_READ(LCFUSE02);
6476
20e4d407 6477 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6478}
6479
dc97997a 6480void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6481{
b268c699
ID		 6482 /*
6483 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6484 * requirement.
6485 */
6486 if (!i915.enable_rc6) {
6487 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6488 intel_runtime_pm_get(dev_priv);
6489 }
e6069ca8 6490
773ea9a8
CW		 6491 mutex_lock(&dev_priv->rps.hw_lock);
6492
6493 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6494 if (IS_CHERRYVIEW(dev_priv))
6495 cherryview_init_gt_powersave(dev_priv);
6496 else if (IS_VALLEYVIEW(dev_priv))
6497 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6498 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6499 gen6_init_rps_frequencies(dev_priv);
6500
6501 /* Derive initial user preferences/limits from the hardware limits */
6502 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6503 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6504
6505 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6506 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6507
6508 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6509 dev_priv->rps.min_freq_softlimit =
6510 max_t(int,
6511 dev_priv->rps.efficient_freq,
6512 intel_freq_opcode(dev_priv, 450));
6513
99ac9612
CW		 6514 /* After setting max-softlimit, find the overclock max freq */
6515 if (IS_GEN6(dev_priv) ||
6516 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6517 u32 params = 0;
6518
6519 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6520 if (params & BIT(31)) { /* OC supported */
6521 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6522 (dev_priv->rps.max_freq & 0xff) * 50,
6523 (params & 0xff) * 50);
6524 dev_priv->rps.max_freq = params & 0xff;
6525 }
6526 }
6527
29ecd78d
CW		 6528 /* Finally allow us to boost to max by default */
6529 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6530
773ea9a8 6531 mutex_unlock(&dev_priv->rps.hw_lock);
54b4f68f
CW		 6532
6533 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6534}
6535
dc97997a 6536void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6537{
8dac1e1f 6538 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6539 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6540
6541 if (!i915.enable_rc6)
6542 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6543}
6544
54b4f68f
CW		 6545/**
6546 * intel_suspend_gt_powersave - suspend PM work and helper threads
6547 * @dev_priv: i915 device
6548 *
6549 * We don't want to disable RC6 or other features here, we just want
6550 * to make sure any work we've queued has finished and won't bother
6551 * us while we're suspended.
6552 */
6553void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6554{
6555 if (INTEL_GEN(dev_priv) < 6)
6556 return;
6557
6558 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6559 intel_runtime_pm_put(dev_priv);
6560
6561 /* gen6_rps_idle() will be called later to disable interrupts */
6562}
6563
b7137e0c
CW		 6564void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6565{
6566 dev_priv->rps.enabled = true; /* force disabling */
6567 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6568
6569 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6570}
6571
dc97997a 6572void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6573{
b7137e0c
CW		 6574 if (!READ_ONCE(dev_priv->rps.enabled))
6575 return;
e494837a 6576
b7137e0c 6577 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6578
b7137e0c
CW		 6579 if (INTEL_GEN(dev_priv) >= 9) {
6580 gen9_disable_rc6(dev_priv);
6581 gen9_disable_rps(dev_priv);
6582 } else if (IS_CHERRYVIEW(dev_priv)) {
6583 cherryview_disable_rps(dev_priv);
6584 } else if (IS_VALLEYVIEW(dev_priv)) {
6585 valleyview_disable_rps(dev_priv);
6586 } else if (INTEL_GEN(dev_priv) >= 6) {
6587 gen6_disable_rps(dev_priv);
6588 } else if (IS_IRONLAKE_M(dev_priv)) {
6589 ironlake_disable_drps(dev_priv);
930ebb46 6590 }
b7137e0c
CW		 6591
6592 dev_priv->rps.enabled = false;
6593 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6594}
6595
b7137e0c 6596void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6597{
54b4f68f
CW		 6598 /* We shouldn't be disabling as we submit, so this should be less
6599 * racy than it appears!
6600 */
b7137e0c
CW		 6601 if (READ_ONCE(dev_priv->rps.enabled))
6602 return;
1a01ab3b 6603
b7137e0c
CW		 6604 /* Powersaving is controlled by the host when inside a VM */
6605 if (intel_vgpu_active(dev_priv))
6606 return;
0a073b84 6607
b7137e0c 6608 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6609
6610 if (IS_CHERRYVIEW(dev_priv)) {
6611 cherryview_enable_rps(dev_priv);
6612 } else if (IS_VALLEYVIEW(dev_priv)) {
6613 valleyview_enable_rps(dev_priv);
b7137e0c 6614 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6615 gen9_enable_rc6(dev_priv);
6616 gen9_enable_rps(dev_priv);
6617 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6618 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6619 } else if (IS_BROADWELL(dev_priv)) {
6620 gen8_enable_rps(dev_priv);
fb7404e8 6621 gen6_update_ring_freq(dev_priv);
b7137e0c 6622 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6623 gen6_enable_rps(dev_priv);
fb7404e8 6624 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6625 } else if (IS_IRONLAKE_M(dev_priv)) {
6626 ironlake_enable_drps(dev_priv);
6627 intel_init_emon(dev_priv);
0a073b84 6628 }
aed242ff
CW		 6629
6630 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6631 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6632
6633 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6634 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6635
54b4f68f 6636 dev_priv->rps.enabled = true;
b7137e0c
CW		 6637 mutex_unlock(&dev_priv->rps.hw_lock);
6638}
3cc134e3 6639
54b4f68f
CW		 6640static void __intel_autoenable_gt_powersave(struct work_struct *work)
6641{
6642 struct drm_i915_private *dev_priv =
6643 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6644 struct intel_engine_cs *rcs;
6645 struct drm_i915_gem_request *req;
6646
6647 if (READ_ONCE(dev_priv->rps.enabled))
6648 goto out;
6649
6650 rcs = &dev_priv->engine[RCS];
6651 if (rcs->last_context)
6652 goto out;
6653
6654 if (!rcs->init_context)
6655 goto out;
6656
6657 mutex_lock(&dev_priv->drm.struct_mutex);
6658
6659 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6660 if (IS_ERR(req))
6661 goto unlock;
6662
6663 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6664 rcs->init_context(req);
6665
6666 /* Mark the device busy, calling intel_enable_gt_powersave() */
6667 i915_add_request_no_flush(req);
6668
6669unlock:
6670 mutex_unlock(&dev_priv->drm.struct_mutex);
6671out:
6672 intel_runtime_pm_put(dev_priv);
6673}
6674
6675void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6676{
6677 if (READ_ONCE(dev_priv->rps.enabled))
6678 return;
6679
6680 if (IS_IRONLAKE_M(dev_priv)) {
6681 ironlake_enable_drps(dev_priv);
6682 mutex_lock(&dev_priv->drm.struct_mutex);
6683 intel_init_emon(dev_priv);
6684 mutex_unlock(&dev_priv->drm.struct_mutex);
6685 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6686 /*
6687 * PCU communication is slow and this doesn't need to be
6688 * done at any specific time, so do this out of our fast path
6689 * to make resume and init faster.
6690 *
6691 * We depend on the HW RC6 power context save/restore
6692 * mechanism when entering D3 through runtime PM suspend. So
6693 * disable RPM until RPS/RC6 is properly setup. We can only
6694 * get here via the driver load/system resume/runtime resume
6695 * paths, so the _noresume version is enough (and in case of
6696 * runtime resume it's necessary).
6697 */
6698 if (queue_delayed_work(dev_priv->wq,
6699 &dev_priv->rps.autoenable_work,
6700 round_jiffies_up_relative(HZ)))
6701 intel_runtime_pm_get_noresume(dev_priv);
6702 }
6703}
6704
3107bd48
DV		 6705static void ibx_init_clock_gating(struct drm_device *dev)
6706{
fac5e23e 6707 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6708
6709 /*
6710 * On Ibex Peak and Cougar Point, we need to disable clock
6711 * gating for the panel power sequencer or it will fail to
6712 * start up when no ports are active.
6713 */
6714 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6715}
6716
0e088b8f
VS		 6717static void g4x_disable_trickle_feed(struct drm_device *dev)
6718{
fac5e23e 6719 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6720 enum pipe pipe;
0e088b8f 6721
055e393f 6722 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6723 I915_WRITE(DSPCNTR(pipe),
6724 I915_READ(DSPCNTR(pipe)) |
6725 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6726
6727 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6728 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6729 }
6730}
6731
017636cc
VS		 6732static void ilk_init_lp_watermarks(struct drm_device *dev)
6733{
fac5e23e 6734 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6735
6736 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6737 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6738 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6739
6740 /*
6741 * Don't touch WM1S_LP_EN here.
6742 * Doing so could cause underruns.
6743 */
6744}
6745
1fa61106 6746static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6747{
fac5e23e 6748 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6749 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6750
f1e8fa56
DL		 6751 /*
6752 * Required for FBC
6753 * WaFbcDisableDpfcClockGating:ilk
6754 */
4d47e4f5
DL		 6755 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6756 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6757 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6758
6759 I915_WRITE(PCH_3DCGDIS0,
6760 MARIUNIT_CLOCK_GATE_DISABLE |
6761 SVSMUNIT_CLOCK_GATE_DISABLE);
6762 I915_WRITE(PCH_3DCGDIS1,
6763 VFMUNIT_CLOCK_GATE_DISABLE);
6764
6f1d69b0
ED		 6765 /*
6766 * According to the spec the following bits should be set in
6767 * order to enable memory self-refresh
6768 * The bit 22/21 of 0x42004
6769 * The bit 5 of 0x42020
6770 * The bit 15 of 0x45000
6771 */
6772 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6773 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6774 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6775 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6776 I915_WRITE(DISP_ARB_CTL,
6777 (I915_READ(DISP_ARB_CTL) |
6778 DISP_FBC_WM_DIS));
017636cc
VS		 6779
6780 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6781
6782 /*
6783 * Based on the document from hardware guys the following bits
6784 * should be set unconditionally in order to enable FBC.
6785 * The bit 22 of 0x42000
6786 * The bit 22 of 0x42004
6787 * The bit 7,8,9 of 0x42020.
6788 */
6789 if (IS_IRONLAKE_M(dev)) {
4bb35334 6790 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6791 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6792 I915_READ(ILK_DISPLAY_CHICKEN1) |
6793 ILK_FBCQ_DIS);
6794 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6795 I915_READ(ILK_DISPLAY_CHICKEN2) |
6796 ILK_DPARB_GATE);
6f1d69b0
ED		 6797 }
6798
4d47e4f5
DL		 6799 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6800
6f1d69b0
ED		 6801 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6802 I915_READ(ILK_DISPLAY_CHICKEN2) |
6803 ILK_ELPIN_409_SELECT);
6804 I915_WRITE(_3D_CHICKEN2,
6805 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6806 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6807
ecdb4eb7 6808 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6809 I915_WRITE(CACHE_MODE_0,
6810 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6811
4e04632e
AG		 6812 /* WaDisable_RenderCache_OperationalFlush:ilk */
6813 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6814
0e088b8f 6815 g4x_disable_trickle_feed(dev);
bdad2b2f 6816
3107bd48
DV		 6817 ibx_init_clock_gating(dev);
6818}
6819
6820static void cpt_init_clock_gating(struct drm_device *dev)
6821{
fac5e23e 6822 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6823 int pipe;
3f704fa2 6824 uint32_t val;
3107bd48
DV		 6825
6826 /*
6827 * On Ibex Peak and Cougar Point, we need to disable clock
6828 * gating for the panel power sequencer or it will fail to
6829 * start up when no ports are active.
6830 */
cd664078
JB		 6831 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6832 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6833 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6834 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6835 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6836 /* The below fixes the weird display corruption, a few pixels shifted
6837 * downward, on (only) LVDS of some HP laptops with IVY.
6838 */
055e393f 6839 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6840 val = I915_READ(TRANS_CHICKEN2(pipe));
6841 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6842 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6843 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6844 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6845 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6846 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6847 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6848 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6849 }
3107bd48 6850 /* WADP0ClockGatingDisable */
055e393f 6851 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6852 I915_WRITE(TRANS_CHICKEN1(pipe),
6853 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6854 }
6f1d69b0
ED		 6855}
6856
1d7aaa0c
DV		 6857static void gen6_check_mch_setup(struct drm_device *dev)
6858{
fac5e23e 6859 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6860 uint32_t tmp;
6861
6862 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6863 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6864 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6865 tmp);
1d7aaa0c
DV		 6866}
6867
1fa61106 6868static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 6869{
fac5e23e 6870 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6871 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6872
231e54f6 6873 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6874
6875 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6876 I915_READ(ILK_DISPLAY_CHICKEN2) |
6877 ILK_ELPIN_409_SELECT);
6878
ecdb4eb7 6879 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6880 I915_WRITE(_3D_CHICKEN,
6881 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6882
4e04632e
AG		 6883 /* WaDisable_RenderCache_OperationalFlush:snb */
6884 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6885
8d85d272
VS		 6886 /*
6887 * BSpec recoomends 8x4 when MSAA is used,
6888 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6889 *
6890 * Note that PS/WM thread counts depend on the WIZ hashing
6891 * disable bit, which we don't touch here, but it's good
6892 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6893 */
6894 I915_WRITE(GEN6_GT_MODE,
98533251 6895 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6896
017636cc 6897 ilk_init_lp_watermarks(dev);
6f1d69b0 6898
6f1d69b0 6899 I915_WRITE(CACHE_MODE_0,
50743298 6900 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6901
6902 I915_WRITE(GEN6_UCGCTL1,
6903 I915_READ(GEN6_UCGCTL1) |
6904 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6905 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6906
6907 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6908 * gating disable must be set. Failure to set it results in
6909 * flickering pixels due to Z write ordering failures after
6910 * some amount of runtime in the Mesa "fire" demo, and Unigine
6911 * Sanctuary and Tropics, and apparently anything else with
6912 * alpha test or pixel discard.
6913 *
6914 * According to the spec, bit 11 (RCCUNIT) must also be set,
6915 * but we didn't debug actual testcases to find it out.
0f846f81 6916 *
ef59318c
VS		 6917 * WaDisableRCCUnitClockGating:snb
6918 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6919 */
6920 I915_WRITE(GEN6_UCGCTL2,
6921 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6922 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6923
5eb146dd 6924 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6925 I915_WRITE(_3D_CHICKEN3,
6926 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6927
e927ecde
VS		 6928 /*
6929 * Bspec says:
6930 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6931 * 3DSTATE_SF number of SF output attributes is more than 16."
6932 */
6933 I915_WRITE(_3D_CHICKEN3,
6934 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6935
6f1d69b0
ED		 6936 /*
6937 * According to the spec the following bits should be
6938 * set in order to enable memory self-refresh and fbc:
6939 * The bit21 and bit22 of 0x42000
6940 * The bit21 and bit22 of 0x42004
6941 * The bit5 and bit7 of 0x42020
6942 * The bit14 of 0x70180
6943 * The bit14 of 0x71180
4bb35334
DL		 6944 *
6945 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6946 */
6947 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6948 I915_READ(ILK_DISPLAY_CHICKEN1) |
6949 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6950 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6951 I915_READ(ILK_DISPLAY_CHICKEN2) |
6952 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6953 I915_WRITE(ILK_DSPCLK_GATE_D,
6954 I915_READ(ILK_DSPCLK_GATE_D) |
6955 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6956 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6957
0e088b8f 6958 g4x_disable_trickle_feed(dev);
f8f2ac9a 6959
3107bd48 6960 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6961
6962 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6963}
6964
6965static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6966{
6967 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6968
3aad9059 6969 /*
46680e0a 6970 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6971 *
6972 * This actually overrides the dispatch
6973 * mode for all thread types.
6974 */
6f1d69b0
ED		 6975 reg &= ~GEN7_FF_SCHED_MASK;
6976 reg |= GEN7_FF_TS_SCHED_HW;
6977 reg |= GEN7_FF_VS_SCHED_HW;
6978 reg |= GEN7_FF_DS_SCHED_HW;
6979
6980 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6981}
6982
17a303ec
PZ		 6983static void lpt_init_clock_gating(struct drm_device *dev)
6984{
fac5e23e 6985 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 6986
6987 /*
6988 * TODO: this bit should only be enabled when really needed, then
6989 * disabled when not needed anymore in order to save power.
6990 */
c2699524 6991 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6992 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6993 I915_READ(SOUTH_DSPCLK_GATE_D) |
6994 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6995
6996 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6997 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6998 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6999 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7000}
7001
7d708ee4
ID		 7002static void lpt_suspend_hw(struct drm_device *dev)
7003{
fac5e23e 7004 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7005
c2699524 7006 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7007 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7008
7009 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7010 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7011 }
7012}
7013
450174fe
ID		 7014static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7015 int general_prio_credits,
7016 int high_prio_credits)
7017{
7018 u32 misccpctl;
7019
7020 /* WaTempDisableDOPClkGating:bdw */
7021 misccpctl = I915_READ(GEN7_MISCCPCTL);
7022 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7023
7024 I915_WRITE(GEN8_L3SQCREG1,
7025 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7026 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7027
7028 /*
7029 * Wait at least 100 clocks before re-enabling clock gating.
7030 * See the definition of L3SQCREG1 in BSpec.
7031 */
7032 POSTING_READ(GEN8_L3SQCREG1);
7033 udelay(1);
7034 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7035}
7036
9498dba7
MK		 7037static void kabylake_init_clock_gating(struct drm_device *dev)
7038{
9146f308 7039 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7040
b033bb6d 7041 gen9_init_clock_gating(dev);
9498dba7
MK		 7042
7043 /* WaDisableSDEUnitClockGating:kbl */
7044 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7045 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7046 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7047
7048 /* WaDisableGamClockGating:kbl */
7049 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7050 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7051 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7052
7053 /* WaFbcNukeOnHostModify:kbl */
7054 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7055 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7056}
7057
dc00b6a0
DV		 7058static void skylake_init_clock_gating(struct drm_device *dev)
7059{
c584e2d3 7060 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7061
b033bb6d 7062 gen9_init_clock_gating(dev);
44fff99f
MK		 7063
7064 /* WAC6entrylatency:skl */
7065 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7066 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7067
7068 /* WaFbcNukeOnHostModify:skl */
7069 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7070 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7071}
7072
47c2bd97 7073static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7074{
fac5e23e 7075 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7076 enum pipe pipe;
1020a5c2 7077
7ad0dbab 7078 ilk_init_lp_watermarks(dev);
50ed5fbd 7079
ab57fff1 7080 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7081 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7082
ab57fff1 7083 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7084 I915_WRITE(CHICKEN_PAR1_1,
7085 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7086
ab57fff1 7087 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7088 for_each_pipe(dev_priv, pipe) {
07d27e20 7089 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7090 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7091 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7092 }
63801f21 7093
ab57fff1
BW		 7094 /* WaVSRefCountFullforceMissDisable:bdw */
7095 /* WaDSRefCountFullforceMissDisable:bdw */
7096 I915_WRITE(GEN7_FF_THREAD_MODE,
7097 I915_READ(GEN7_FF_THREAD_MODE) &
7098 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7099
295e8bb7
VS		 7100 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7101 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7102
7103 /* WaDisableSDEUnitClockGating:bdw */
7104 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7105 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7106
450174fe
ID		 7107 /* WaProgramL3SqcReg1Default:bdw */
7108 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7109
6d50b065
VS		 7110 /*
7111 * WaGttCachingOffByDefault:bdw
7112 * GTT cache may not work with big pages, so if those
7113 * are ever enabled GTT cache may need to be disabled.
7114 */
7115 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7116
17e0adf0
MK		 7117 /* WaKVMNotificationOnConfigChange:bdw */
7118 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7119 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7120
89d6b2b8 7121 lpt_init_clock_gating(dev);
1020a5c2
BW		 7122}
7123
cad2a2d7
ED		 7124static void haswell_init_clock_gating(struct drm_device *dev)
7125{
fac5e23e 7126 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7127
017636cc 7128 ilk_init_lp_watermarks(dev);
cad2a2d7 7129
f3fc4884
FJ		 7130 /* L3 caching of data atomics doesn't work -- disable it. */
7131 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7132 I915_WRITE(HSW_ROW_CHICKEN3,
7133 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7134
ecdb4eb7 7135 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7136 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7137 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7138 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7139
e36ea7ff
VS		 7140 /* WaVSRefCountFullforceMissDisable:hsw */
7141 I915_WRITE(GEN7_FF_THREAD_MODE,
7142 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7143
4e04632e
AG		 7144 /* WaDisable_RenderCache_OperationalFlush:hsw */
7145 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7146
fe27c606
CW		 7147 /* enable HiZ Raw Stall Optimization */
7148 I915_WRITE(CACHE_MODE_0_GEN7,
7149 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7150
ecdb4eb7 7151 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7152 I915_WRITE(CACHE_MODE_1,
7153 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7154
a12c4967
VS		 7155 /*
7156 * BSpec recommends 8x4 when MSAA is used,
7157 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7158 *
7159 * Note that PS/WM thread counts depend on the WIZ hashing
7160 * disable bit, which we don't touch here, but it's good
7161 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7162 */
7163 I915_WRITE(GEN7_GT_MODE,
98533251 7164 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7165
94411593
KG		 7166 /* WaSampleCChickenBitEnable:hsw */
7167 I915_WRITE(HALF_SLICE_CHICKEN3,
7168 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7169
ecdb4eb7 7170 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7171 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7172
90a88643
PZ		 7173 /* WaRsPkgCStateDisplayPMReq:hsw */
7174 I915_WRITE(CHICKEN_PAR1_1,
7175 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7176
17a303ec 7177 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7178}
7179
1fa61106 7180static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7181{
fac5e23e 7182 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7183 uint32_t snpcr;
6f1d69b0 7184
017636cc 7185 ilk_init_lp_watermarks(dev);
6f1d69b0 7186
231e54f6 7187 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7188
ecdb4eb7 7189 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7190 I915_WRITE(_3D_CHICKEN3,
7191 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7192
ecdb4eb7 7193 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7194 I915_WRITE(IVB_CHICKEN3,
7195 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7196 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7197
ecdb4eb7 7198 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7199 if (IS_IVB_GT1(dev))
7200 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7201 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7202
4e04632e
AG		 7203 /* WaDisable_RenderCache_OperationalFlush:ivb */
7204 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7205
ecdb4eb7 7206 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7207 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7208 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7209
ecdb4eb7 7210 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7211 I915_WRITE(GEN7_L3CNTLREG1,
7212 GEN7_WA_FOR_GEN7_L3_CONTROL);
7213 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7214 GEN7_WA_L3_CHICKEN_MODE);
7215 if (IS_IVB_GT1(dev))
7216 I915_WRITE(GEN7_ROW_CHICKEN2,
7217 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7218 else {
7219 /* must write both registers */
7220 I915_WRITE(GEN7_ROW_CHICKEN2,
7221 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7222 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7223 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7224 }
6f1d69b0 7225
ecdb4eb7 7226 /* WaForceL3Serialization:ivb */
61939d97
JB		 7227 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7228 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7229
1b80a19a 7230 /*
0f846f81 7231 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7232 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7233 */
7234 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7235 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7236
ecdb4eb7 7237 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7238 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7239 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7240 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7241
0e088b8f 7242 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7243
7244 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7245
22721343
CW		 7246 if (0) { /* causes HiZ corruption on ivb:gt1 */
7247 /* enable HiZ Raw Stall Optimization */
7248 I915_WRITE(CACHE_MODE_0_GEN7,
7249 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7250 }
116f2b6d 7251
ecdb4eb7 7252 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7253 I915_WRITE(CACHE_MODE_1,
7254 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7255
a607c1a4
VS		 7256 /*
7257 * BSpec recommends 8x4 when MSAA is used,
7258 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7259 *
7260 * Note that PS/WM thread counts depend on the WIZ hashing
7261 * disable bit, which we don't touch here, but it's good
7262 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7263 */
7264 I915_WRITE(GEN7_GT_MODE,
98533251 7265 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7266
20848223
BW		 7267 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7268 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7269 snpcr |= GEN6_MBC_SNPCR_MED;
7270 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7271
ab5c608b
BW		 7272 if (!HAS_PCH_NOP(dev))
7273 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7274
7275 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7276}
7277
1fa61106 7278static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7279{
fac5e23e 7280 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7281
ecdb4eb7 7282 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7283 I915_WRITE(_3D_CHICKEN3,
7284 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7285
ecdb4eb7 7286 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7287 I915_WRITE(IVB_CHICKEN3,
7288 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7289 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7290
fad7d36e 7291 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7292 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7293 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7294 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7295 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7296
4e04632e
AG		 7297 /* WaDisable_RenderCache_OperationalFlush:vlv */
7298 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7299
ecdb4eb7 7300 /* WaForceL3Serialization:vlv */
61939d97
JB		 7301 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7302 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7303
ecdb4eb7 7304 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7305 I915_WRITE(GEN7_ROW_CHICKEN2,
7306 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7307
ecdb4eb7 7308 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7309 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7310 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7311 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7312
46680e0a
VS		 7313 gen7_setup_fixed_func_scheduler(dev_priv);
7314
3c0edaeb 7315 /*
0f846f81 7316 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7317 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7318 */
7319 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7320 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7321
c98f5062
AG		 7322 /* WaDisableL3Bank2xClockGate:vlv
7323 * Disabling L3 clock gating- MMIO 940c[25] = 1
7324 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7325 I915_WRITE(GEN7_UCGCTL4,
7326 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7327
afd58e79
VS		 7328 /*
7329 * BSpec says this must be set, even though
7330 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7331 */
6b26c86d
DV		 7332 I915_WRITE(CACHE_MODE_1,
7333 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7334
da2518f9
VS		 7335 /*
7336 * BSpec recommends 8x4 when MSAA is used,
7337 * however in practice 16x4 seems fastest.
7338 *
7339 * Note that PS/WM thread counts depend on the WIZ hashing
7340 * disable bit, which we don't touch here, but it's good
7341 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7342 */
7343 I915_WRITE(GEN7_GT_MODE,
7344 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7345
031994ee
VS		 7346 /*
7347 * WaIncreaseL3CreditsForVLVB0:vlv
7348 * This is the hardware default actually.
7349 */
7350 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7351
2d809570 7352 /*
ecdb4eb7 7353 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7354 * Disable clock gating on th GCFG unit to prevent a delay
7355 * in the reporting of vblank events.
7356 */
7a0d1eed 7357 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7358}
7359
a4565da8
VS		 7360static void cherryview_init_clock_gating(struct drm_device *dev)
7361{
fac5e23e 7362 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7363
232ce337
VS		 7364 /* WaVSRefCountFullforceMissDisable:chv */
7365 /* WaDSRefCountFullforceMissDisable:chv */
7366 I915_WRITE(GEN7_FF_THREAD_MODE,
7367 I915_READ(GEN7_FF_THREAD_MODE) &
7368 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7369
7370 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7371 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7372 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7373
7374 /* WaDisableCSUnitClockGating:chv */
7375 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7376 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7377
7378 /* WaDisableSDEUnitClockGating:chv */
7379 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7380 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7381
450174fe
ID		 7382 /*
7383 * WaProgramL3SqcReg1Default:chv
7384 * See gfxspecs/Related Documents/Performance Guide/
7385 * LSQC Setting Recommendations.
7386 */
7387 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7388
6d50b065
VS		 7389 /*
7390 * GTT cache may not work with big pages, so if those
7391 * are ever enabled GTT cache may need to be disabled.
7392 */
7393 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7394}
7395
1fa61106 7396static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7397{
fac5e23e 7398 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7399 uint32_t dspclk_gate;
7400
7401 I915_WRITE(RENCLK_GATE_D1, 0);
7402 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7403 GS_UNIT_CLOCK_GATE_DISABLE |
7404 CL_UNIT_CLOCK_GATE_DISABLE);
7405 I915_WRITE(RAMCLK_GATE_D, 0);
7406 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7407 OVRUNIT_CLOCK_GATE_DISABLE |
7408 OVCUNIT_CLOCK_GATE_DISABLE;
7409 if (IS_GM45(dev))
7410 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7411 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7412
7413 /* WaDisableRenderCachePipelinedFlush */
7414 I915_WRITE(CACHE_MODE_0,
7415 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7416
4e04632e
AG		 7417 /* WaDisable_RenderCache_OperationalFlush:g4x */
7418 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7419
0e088b8f 7420 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7421}
7422
1fa61106 7423static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7424{
fac5e23e 7425 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7426
7427 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7428 I915_WRITE(RENCLK_GATE_D2, 0);
7429 I915_WRITE(DSPCLK_GATE_D, 0);
7430 I915_WRITE(RAMCLK_GATE_D, 0);
7431 I915_WRITE16(DEUC, 0);
20f94967
VS		 7432 I915_WRITE(MI_ARB_STATE,
7433 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7434
7435 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7436 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7437}
7438
1fa61106 7439static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7440{
fac5e23e 7441 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7442
7443 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7444 I965_RCC_CLOCK_GATE_DISABLE |
7445 I965_RCPB_CLOCK_GATE_DISABLE |
7446 I965_ISC_CLOCK_GATE_DISABLE |
7447 I965_FBC_CLOCK_GATE_DISABLE);
7448 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7449 I915_WRITE(MI_ARB_STATE,
7450 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7451
7452 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7453 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7454}
7455
1fa61106 7456static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7457{
fac5e23e 7458 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7459 u32 dstate = I915_READ(D_STATE);
7460
7461 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7462 DSTATE_DOT_CLOCK_GATING;
7463 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7464
7465 if (IS_PINEVIEW(dev))
7466 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7467
7468 /* IIR "flip pending" means done if this bit is set */
7469 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7470
7471 /* interrupts should cause a wake up from C3 */
3299254f 7472 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7473
7474 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7475 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7476
7477 I915_WRITE(MI_ARB_STATE,
7478 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7479}
7480
1fa61106 7481static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7482{
fac5e23e 7483 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7484
7485 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7486
7487 /* interrupts should cause a wake up from C3 */
7488 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7489 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7490
7491 I915_WRITE(MEM_MODE,
7492 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7493}
7494
1fa61106 7495static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7496{
fac5e23e 7497 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7498
7499 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7500
7501 I915_WRITE(MEM_MODE,
7502 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7503 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7504}
7505
6f1d69b0
ED		 7506void intel_init_clock_gating(struct drm_device *dev)
7507{
fac5e23e 7508 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7509
bb400da9 7510 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7511}
7512
7d708ee4
ID		 7513void intel_suspend_hw(struct drm_device *dev)
7514{
7515 if (HAS_PCH_LPT(dev))
7516 lpt_suspend_hw(dev);
7517}
7518
bb400da9
ID		 7519static void nop_init_clock_gating(struct drm_device *dev)
7520{
7521 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7522}
7523
7524/**
7525 * intel_init_clock_gating_hooks - setup the clock gating hooks
7526 * @dev_priv: device private
7527 *
7528 * Setup the hooks that configure which clocks of a given platform can be
7529 * gated and also apply various GT and display specific workarounds for these
7530 * platforms. Note that some GT specific workarounds are applied separately
7531 * when GPU contexts or batchbuffers start their execution.
7532 */
7533void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7534{
7535 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7536 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7537 else if (IS_KABYLAKE(dev_priv))
9498dba7 7538 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7539 else if (IS_BROXTON(dev_priv))
7540 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7541 else if (IS_BROADWELL(dev_priv))
7542 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7543 else if (IS_CHERRYVIEW(dev_priv))
7544 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7545 else if (IS_HASWELL(dev_priv))
7546 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7547 else if (IS_IVYBRIDGE(dev_priv))
7548 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7549 else if (IS_VALLEYVIEW(dev_priv))
7550 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7551 else if (IS_GEN6(dev_priv))
7552 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7553 else if (IS_GEN5(dev_priv))
7554 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7555 else if (IS_G4X(dev_priv))
7556 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7557 else if (IS_CRESTLINE(dev_priv))
7558 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7559 else if (IS_BROADWATER(dev_priv))
7560 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7561 else if (IS_GEN3(dev_priv))
7562 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7563 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7564 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7565 else if (IS_GEN2(dev_priv))
7566 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7567 else {
7568 MISSING_CASE(INTEL_DEVID(dev_priv));
7569 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7570 }
7571}
7572
1fa61106
ED		 7573/* Set up chip specific power management-related functions */
7574void intel_init_pm(struct drm_device *dev)
7575{
fac5e23e 7576 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7577
7ff0ebcc 7578 intel_fbc_init(dev_priv);
1fa61106 7579
c921aba8
DV		 7580 /* For cxsr */
7581 if (IS_PINEVIEW(dev))
7582 i915_pineview_get_mem_freq(dev);
7583 else if (IS_GEN5(dev))
7584 i915_ironlake_get_mem_freq(dev);
7585
1fa61106 7586 /* For FIFO watermark updates */
f5ed50cb 7587 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7588 skl_setup_wm_latency(dev);
2d41c0b5 7589 dev_priv->display.update_wm = skl_update_wm;
98d39494 7590 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7591 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7592 ilk_setup_wm_latency(dev);
53615a5e 7593
bd602544
VS		 7594 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7595 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7596 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7597 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7598 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7599 dev_priv->display.compute_intermediate_wm =
7600 ilk_compute_intermediate_wm;
7601 dev_priv->display.initial_watermarks =
7602 ilk_initial_watermarks;
7603 dev_priv->display.optimize_watermarks =
7604 ilk_optimize_watermarks;
bd602544
VS		 7605 } else {
7606 DRM_DEBUG_KMS("Failed to read display plane latency. "
7607 "Disable CxSR\n");
7608 }
a4565da8 7609 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7610 vlv_setup_wm_latency(dev);
262cd2e1 7611 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7612 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7613 vlv_setup_wm_latency(dev);
26e1fe4f 7614 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7615 } else if (IS_PINEVIEW(dev)) {
7616 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7617 dev_priv->is_ddr3,
7618 dev_priv->fsb_freq,
7619 dev_priv->mem_freq)) {
7620 DRM_INFO("failed to find known CxSR latency "
7621 "(found ddr%s fsb freq %d, mem freq %d), "
7622 "disabling CxSR\n",
7623 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7624 dev_priv->fsb_freq, dev_priv->mem_freq);
7625 /* Disable CxSR and never update its watermark again */
5209b1f4 7626 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7627 dev_priv->display.update_wm = NULL;
7628 } else
7629 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7630 } else if (IS_G4X(dev)) {
7631 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7632 } else if (IS_GEN4(dev)) {
7633 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7634 } else if (IS_GEN3(dev)) {
7635 dev_priv->display.update_wm = i9xx_update_wm;
7636 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7637 } else if (IS_GEN2(dev)) {
7638 if (INTEL_INFO(dev)->num_pipes == 1) {
7639 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7640 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7641 } else {
7642 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7643 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7644 }
feb56b93
DV		 7645 } else {
7646 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7647 }
7648}
7649
151a49d0 7650int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7651{
4fc688ce 7652 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7653
3f5582dd
CW		 7654 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7655 * use te fw I915_READ variants to reduce the amount of work
7656 * required when reading/writing.
7657 */
7658
7659 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7660 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7661 return -EAGAIN;
7662 }
7663
3f5582dd
CW		 7664 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7665 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7666 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7667
3f5582dd
CW		 7668 if (intel_wait_for_register_fw(dev_priv,
7669 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7670 500)) {
42c0526c
BW		 7671 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7672 return -ETIMEDOUT;
7673 }
7674
3f5582dd
CW		 7675 *val = I915_READ_FW(GEN6_PCODE_DATA);
7676 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c
BW		 7677
7678 return 0;
7679}
7680
3f5582dd
CW		 7681int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7682 u32 mbox, u32 val)
42c0526c 7683{
4fc688ce 7684 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7685
3f5582dd
CW		 7686 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7687 * use te fw I915_READ variants to reduce the amount of work
7688 * required when reading/writing.
7689 */
7690
7691 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7692 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7693 return -EAGAIN;
7694 }
7695
3f5582dd
CW		 7696 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7697 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7698
3f5582dd
CW		 7699 if (intel_wait_for_register_fw(dev_priv,
7700 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7701 500)) {
42c0526c
BW		 7702 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7703 return -ETIMEDOUT;
7704 }
7705
3f5582dd 7706 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c
BW		 7707
7708 return 0;
7709}
a0e4e199 7710
dd06f88c
VS		 7711static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7712{
c30fec65
VS		 7713 /*
7714 * N = val - 0xb7
7715 * Slow = Fast = GPLL ref * N
7716 */
7717 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7718}
7719
b55dd647 7720static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7721{
c30fec65 7722 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7723}
7724
b55dd647 7725static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7726{
c30fec65
VS		 7727 /*
7728 * N = val / 2
7729 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7730 */
7731 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7732}
7733
b55dd647 7734static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7735{
1c14762d 7736 /* CHV needs even values */
c30fec65 7737 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7738}
7739
616bc820 7740int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7741{
2d1fe073 7742 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7743 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7744 GEN9_FREQ_SCALER);
2d1fe073 7745 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7746 return chv_gpu_freq(dev_priv, val);
2d1fe073 7747 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7748 return byt_gpu_freq(dev_priv, val);
7749 else
7750 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7751}
7752
616bc820
VS		 7753int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7754{
2d1fe073 7755 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7756 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7757 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7758 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7759 return chv_freq_opcode(dev_priv, val);
2d1fe073 7760 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7761 return byt_freq_opcode(dev_priv, val);
7762 else
500a3d2e 7763 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7764}
22b1b2f8 7765
6ad790c0
CW		 7766struct request_boost {
7767 struct work_struct work;
eed29a5b 7768 struct drm_i915_gem_request *req;
6ad790c0
CW		 7769};
7770
7771static void __intel_rps_boost_work(struct work_struct *work)
7772{
7773 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7774 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7775
f69a02c9 7776 if (!i915_gem_request_completed(req))
c033666a 7777 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7778
e8a261ea 7779 i915_gem_request_put(req);
6ad790c0
CW		 7780 kfree(boost);
7781}
7782
91d14251 7783void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7784{
7785 struct request_boost *boost;
7786
91d14251 7787 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7788 return;
7789
f69a02c9 7790 if (i915_gem_request_completed(req))
e61b9958
CW		 7791 return;
7792
6ad790c0
CW		 7793 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7794 if (boost == NULL)
7795 return;
7796
e8a261ea 7797 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7798
7799 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7800 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7801}
7802
f742a552 7803void intel_pm_setup(struct drm_device *dev)
907b28c5 7804{
fac5e23e 7805 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7806
f742a552 7807 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7808 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7809
54b4f68f
CW		 7810 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7811 __intel_autoenable_gt_powersave);
1854d5ca 7812 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7813
33688d95 7814 dev_priv->pm.suspended = false;
1f814dac 7815 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7816 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7817}
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