]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: touch VGA MSR after we enable the power well
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
1fa61106 91static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
101 u32 fbc_ctl, fbc_ctl2;
102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
107 /* FBC_CTL wants 64B units */
108 cfb_pitch = (cfb_pitch / 64) - 1;
109 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
110
111 /* Clear old tags */
112 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
113 I915_WRITE(FBC_TAG + (i * 4), 0);
114
115 /* Set it up... */
116 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
117 fbc_ctl2 |= plane;
118 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
119 I915_WRITE(FBC_FENCE_OFF, crtc->y);
120
121 /* enable it... */
122 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
123 if (IS_I945GM(dev))
124 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
125 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
126 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
127 fbc_ctl |= obj->fence_reg;
128 I915_WRITE(FBC_CONTROL, fbc_ctl);
129
84f44ce7
VS		 130 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
131 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 132}
133
1fa61106 134static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 135{
136 struct drm_i915_private *dev_priv = dev->dev_private;
137
138 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
139}
140
1fa61106 141static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 142{
143 struct drm_device *dev = crtc->dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 struct drm_framebuffer *fb = crtc->fb;
146 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
147 struct drm_i915_gem_object *obj = intel_fb->obj;
148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
149 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
150 unsigned long stall_watermark = 200;
151 u32 dpfc_ctl;
152
153 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
154 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
155 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
156
157 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
158 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
159 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
160 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
161
162 /* enable it... */
163 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
164
84f44ce7 165 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 166}
167
1fa61106 168static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 u32 dpfc_ctl;
172
173 /* Disable compression */
174 dpfc_ctl = I915_READ(DPFC_CONTROL);
175 if (dpfc_ctl & DPFC_CTL_EN) {
176 dpfc_ctl &= ~DPFC_CTL_EN;
177 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
178
179 DRM_DEBUG_KMS("disabled FBC\n");
180 }
181}
182
1fa61106 183static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 184{
185 struct drm_i915_private *dev_priv = dev->dev_private;
186
187 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
188}
189
190static void sandybridge_blit_fbc_update(struct drm_device *dev)
191{
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 u32 blt_ecoskpd;
194
195 /* Make sure blitter notifies FBC of writes */
940aece4
D		 196
197 /* Blitter is part of Media powerwell on VLV. No impact of
198 * his param in other platforms for now */
199 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 200
85208be0
ED		 201 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
202 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
203 GEN6_BLITTER_LOCK_SHIFT;
204 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
205 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
206 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
207 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT);
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 211
940aece4 212 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 213}
214
1fa61106 215static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 216{
217 struct drm_device *dev = crtc->dev;
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 struct drm_framebuffer *fb = crtc->fb;
220 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
221 struct drm_i915_gem_object *obj = intel_fb->obj;
222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
223 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
224 unsigned long stall_watermark = 200;
225 u32 dpfc_ctl;
226
227 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
228 dpfc_ctl &= DPFC_RESERVED;
229 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
230 /* Set persistent mode for front-buffer rendering, ala X. */
231 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
d629336b
VS		 232 dpfc_ctl |= DPFC_CTL_FENCE_EN;
233 if (IS_GEN5(dev))
234 dpfc_ctl |= obj->fence_reg;
85208be0
ED		 235 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
236
237 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
238 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
239 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
84f44ce7 252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 253}
254
1fa61106 255static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268}
269
1fa61106 270static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 271{
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275}
276
abe959c7
RV		 277static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
278{
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
f343c5f6 286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
891348b2 292 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 295 } else {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
891348b2 299 }
b74ea102 300
abe959c7
RV		 301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
b19870ee 307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 308}
309
85208be0
ED		 310bool intel_fbc_enabled(struct drm_device *dev)
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318}
319
320static void intel_fbc_work_fn(struct work_struct *__work)
321{
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
5c3fe8b0 329 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
334 dev_priv->display.enable_fbc(work->crtc,
335 work->interval);
336
5c3fe8b0
BW		 337 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
338 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
339 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 340 }
341
5c3fe8b0 342 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 343 }
344 mutex_unlock(&dev->struct_mutex);
345
346 kfree(work);
347}
348
349static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
350{
5c3fe8b0 351 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 352 return;
353
354 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355
356 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 357 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 358 * entirely asynchronously.
359 */
5c3fe8b0 360 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 361 /* tasklet was killed before being run, clean up */
5c3fe8b0 362 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 363
364 /* Mark the work as no longer wanted so that if it does
365 * wake-up (because the work was already running and waiting
366 * for our mutex), it will discover that is no longer
367 * necessary to run.
368 */
5c3fe8b0 369 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 370}
371
b63fb44c 372static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 373{
374 struct intel_fbc_work *work;
375 struct drm_device *dev = crtc->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377
378 if (!dev_priv->display.enable_fbc)
379 return;
380
381 intel_cancel_fbc_work(dev_priv);
382
b14c5679 383 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 384 if (work == NULL) {
6cdcb5e7 385 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 386 dev_priv->display.enable_fbc(crtc, interval);
387 return;
388 }
389
390 work->crtc = crtc;
391 work->fb = crtc->fb;
392 work->interval = interval;
393 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
394
5c3fe8b0 395 dev_priv->fbc.fbc_work = work;
85208be0 396
85208be0
ED		 397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
402 *
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
7457d617
DL		 407 *
408 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 409 */
410 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
411}
412
413void intel_disable_fbc(struct drm_device *dev)
414{
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 intel_cancel_fbc_work(dev_priv);
418
419 if (!dev_priv->display.disable_fbc)
420 return;
421
422 dev_priv->display.disable_fbc(dev);
5c3fe8b0 423 dev_priv->fbc.plane = -1;
85208be0
ED		 424}
425
29ebf90f
CW		 426static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
427 enum no_fbc_reason reason)
428{
429 if (dev_priv->fbc.no_fbc_reason == reason)
430 return false;
431
432 dev_priv->fbc.no_fbc_reason = reason;
433 return true;
434}
435
85208be0
ED		 436/**
437 * intel_update_fbc - enable/disable FBC as needed
438 * @dev: the drm_device
439 *
440 * Set up the framebuffer compression hardware at mode set time. We
441 * enable it if possible:
442 * - plane A only (on pre-965)
443 * - no pixel mulitply/line duplication
444 * - no alpha buffer discard
445 * - no dual wide
f85da868 446 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 447 *
448 * We can't assume that any compression will take place (worst case),
449 * so the compressed buffer has to be the same size as the uncompressed
450 * one. It also must reside (along with the line length buffer) in
451 * stolen memory.
452 *
453 * We need to enable/disable FBC on a global basis.
454 */
455void intel_update_fbc(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458 struct drm_crtc *crtc = NULL, *tmp_crtc;
459 struct intel_crtc *intel_crtc;
460 struct drm_framebuffer *fb;
461 struct intel_framebuffer *intel_fb;
462 struct drm_i915_gem_object *obj;
ef644fda 463 const struct drm_display_mode *adjusted_mode;
37327abd 464 unsigned int max_width, max_height;
85208be0 465
29ebf90f
CW		 466 if (!I915_HAS_FBC(dev)) {
467 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 468 return;
29ebf90f 469 }
85208be0 470
29ebf90f
CW		 471 if (!i915_powersave) {
472 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
473 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 474 return;
29ebf90f 475 }
85208be0
ED		 476
477 /*
478 * If FBC is already on, we just have to verify that we can
479 * keep it that way...
480 * Need to disable if:
481 * - more than one pipe is active
482 * - changing FBC params (stride, fence, mode)
483 * - new fb is too large to fit in compressed buffer
484 * - going to an unsupported config (interlace, pixel multiply, etc.)
485 */
486 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 487 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 488 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 489 if (crtc) {
29ebf90f
CW		 490 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
491 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 492 goto out_disable;
493 }
494 crtc = tmp_crtc;
495 }
496 }
497
498 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 499 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
500 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 501 goto out_disable;
502 }
503
504 intel_crtc = to_intel_crtc(crtc);
505 fb = crtc->fb;
506 intel_fb = to_intel_framebuffer(fb);
507 obj = intel_fb->obj;
ef644fda 508 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 509
8a5729a3
DL		 510 if (i915_enable_fbc < 0 &&
511 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 512 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
513 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 514 goto out_disable;
85208be0 515 }
8a5729a3 516 if (!i915_enable_fbc) {
29ebf90f
CW		 517 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
518 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 519 goto out_disable;
520 }
ef644fda
VS		 521 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
522 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 523 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
524 DRM_DEBUG_KMS("mode incompatible with compression, "
525 "disabling\n");
85208be0
ED		 526 goto out_disable;
527 }
f85da868
PZ		 528
529 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 530 max_width = 4096;
531 max_height = 2048;
f85da868 532 } else {
37327abd
VS		 533 max_width = 2048;
534 max_height = 1536;
f85da868 535 }
37327abd
VS		 536 if (intel_crtc->config.pipe_src_w > max_width ||
537 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 538 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
539 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 540 goto out_disable;
541 }
c5a44aa0
VS		 542 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
543 intel_crtc->plane != PLANE_A) {
29ebf90f 544 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 545 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 546 goto out_disable;
547 }
548
549 /* The use of a CPU fence is mandatory in order to detect writes
550 * by the CPU to the scanout and trigger updates to the FBC.
551 */
552 if (obj->tiling_mode != I915_TILING_X ||
553 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 554 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
555 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 556 goto out_disable;
557 }
558
559 /* If the kernel debugger is active, always disable compression */
560 if (in_dbg_master())
561 goto out_disable;
562
11be49eb 563 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 564 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
565 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 566 goto out_disable;
567 }
568
85208be0
ED		 569 /* If the scanout has not changed, don't modify the FBC settings.
570 * Note that we make the fundamental assumption that the fb->obj
571 * cannot be unpinned (and have its GTT offset and fence revoked)
572 * without first being decoupled from the scanout and FBC disabled.
573 */
5c3fe8b0
BW		 574 if (dev_priv->fbc.plane == intel_crtc->plane &&
575 dev_priv->fbc.fb_id == fb->base.id &&
576 dev_priv->fbc.y == crtc->y)
85208be0
ED		 577 return;
578
579 if (intel_fbc_enabled(dev)) {
580 /* We update FBC along two paths, after changing fb/crtc
581 * configuration (modeswitching) and after page-flipping
582 * finishes. For the latter, we know that not only did
583 * we disable the FBC at the start of the page-flip
584 * sequence, but also more than one vblank has passed.
585 *
586 * For the former case of modeswitching, it is possible
587 * to switch between two FBC valid configurations
588 * instantaneously so we do need to disable the FBC
589 * before we can modify its control registers. We also
590 * have to wait for the next vblank for that to take
591 * effect. However, since we delay enabling FBC we can
592 * assume that a vblank has passed since disabling and
593 * that we can safely alter the registers in the deferred
594 * callback.
595 *
596 * In the scenario that we go from a valid to invalid
597 * and then back to valid FBC configuration we have
598 * no strict enforcement that a vblank occurred since
599 * disabling the FBC. However, along all current pipe
600 * disabling paths we do need to wait for a vblank at
601 * some point. And we wait before enabling FBC anyway.
602 */
603 DRM_DEBUG_KMS("disabling active FBC for update\n");
604 intel_disable_fbc(dev);
605 }
606
607 intel_enable_fbc(crtc, 500);
29ebf90f 608 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 609 return;
610
611out_disable:
612 /* Multiple disables should be harmless */
613 if (intel_fbc_enabled(dev)) {
614 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
615 intel_disable_fbc(dev);
616 }
11be49eb 617 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 618}
619
c921aba8
DV		 620static void i915_pineview_get_mem_freq(struct drm_device *dev)
621{
622 drm_i915_private_t *dev_priv = dev->dev_private;
623 u32 tmp;
624
625 tmp = I915_READ(CLKCFG);
626
627 switch (tmp & CLKCFG_FSB_MASK) {
628 case CLKCFG_FSB_533:
629 dev_priv->fsb_freq = 533; /* 133*4 */
630 break;
631 case CLKCFG_FSB_800:
632 dev_priv->fsb_freq = 800; /* 200*4 */
633 break;
634 case CLKCFG_FSB_667:
635 dev_priv->fsb_freq = 667; /* 167*4 */
636 break;
637 case CLKCFG_FSB_400:
638 dev_priv->fsb_freq = 400; /* 100*4 */
639 break;
640 }
641
642 switch (tmp & CLKCFG_MEM_MASK) {
643 case CLKCFG_MEM_533:
644 dev_priv->mem_freq = 533;
645 break;
646 case CLKCFG_MEM_667:
647 dev_priv->mem_freq = 667;
648 break;
649 case CLKCFG_MEM_800:
650 dev_priv->mem_freq = 800;
651 break;
652 }
653
654 /* detect pineview DDR3 setting */
655 tmp = I915_READ(CSHRDDR3CTL);
656 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
657}
658
659static void i915_ironlake_get_mem_freq(struct drm_device *dev)
660{
661 drm_i915_private_t *dev_priv = dev->dev_private;
662 u16 ddrpll, csipll;
663
664 ddrpll = I915_READ16(DDRMPLL1);
665 csipll = I915_READ16(CSIPLL0);
666
667 switch (ddrpll & 0xff) {
668 case 0xc:
669 dev_priv->mem_freq = 800;
670 break;
671 case 0x10:
672 dev_priv->mem_freq = 1066;
673 break;
674 case 0x14:
675 dev_priv->mem_freq = 1333;
676 break;
677 case 0x18:
678 dev_priv->mem_freq = 1600;
679 break;
680 default:
681 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
682 ddrpll & 0xff);
683 dev_priv->mem_freq = 0;
684 break;
685 }
686
20e4d407 687 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 688
689 switch (csipll & 0x3ff) {
690 case 0x00c:
691 dev_priv->fsb_freq = 3200;
692 break;
693 case 0x00e:
694 dev_priv->fsb_freq = 3733;
695 break;
696 case 0x010:
697 dev_priv->fsb_freq = 4266;
698 break;
699 case 0x012:
700 dev_priv->fsb_freq = 4800;
701 break;
702 case 0x014:
703 dev_priv->fsb_freq = 5333;
704 break;
705 case 0x016:
706 dev_priv->fsb_freq = 5866;
707 break;
708 case 0x018:
709 dev_priv->fsb_freq = 6400;
710 break;
711 default:
712 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
713 csipll & 0x3ff);
714 dev_priv->fsb_freq = 0;
715 break;
716 }
717
718 if (dev_priv->fsb_freq == 3200) {
20e4d407 719 dev_priv->ips.c_m = 0;
c921aba8 720 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 721 dev_priv->ips.c_m = 1;
c921aba8 722 } else {
20e4d407 723 dev_priv->ips.c_m = 2;
c921aba8
DV		 724 }
725}
726
b445e3b0
ED		 727static const struct cxsr_latency cxsr_latency_table[] = {
728 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
729 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
730 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
731 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
732 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
733
734 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
735 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
736 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
737 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
738 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
739
740 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
741 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
742 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
743 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
744 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
745
746 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
747 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
748 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
749 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
750 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
751
752 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
753 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
754 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
755 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
756 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
757
758 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
759 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
760 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
761 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
762 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
763};
764
63c62275 765static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 766 int is_ddr3,
767 int fsb,
768 int mem)
769{
770 const struct cxsr_latency *latency;
771 int i;
772
773 if (fsb == 0 || mem == 0)
774 return NULL;
775
776 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
777 latency = &cxsr_latency_table[i];
778 if (is_desktop == latency->is_desktop &&
779 is_ddr3 == latency->is_ddr3 &&
780 fsb == latency->fsb_freq && mem == latency->mem_freq)
781 return latency;
782 }
783
784 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
785
786 return NULL;
787}
788
1fa61106 789static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 790{
791 struct drm_i915_private *dev_priv = dev->dev_private;
792
793 /* deactivate cxsr */
794 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
795}
796
797/*
798 * Latency for FIFO fetches is dependent on several factors:
799 * - memory configuration (speed, channels)
800 * - chipset
801 * - current MCH state
802 * It can be fairly high in some situations, so here we assume a fairly
803 * pessimal value. It's a tradeoff between extra memory fetches (if we
804 * set this value too high, the FIFO will fetch frequently to stay full)
805 * and power consumption (set it too low to save power and we might see
806 * FIFO underruns and display "flicker").
807 *
808 * A value of 5us seems to be a good balance; safe for very low end
809 * platforms but not overly aggressive on lower latency configs.
810 */
811static const int latency_ns = 5000;
812
1fa61106 813static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 814{
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 uint32_t dsparb = I915_READ(DSPARB);
817 int size;
818
819 size = dsparb & 0x7f;
820 if (plane)
821 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
822
823 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
824 plane ? "B" : "A", size);
825
826 return size;
827}
828
1fa61106 829static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 830{
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 uint32_t dsparb = I915_READ(DSPARB);
833 int size;
834
835 size = dsparb & 0x1ff;
836 if (plane)
837 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
838 size >>= 1; /* Convert to cachelines */
839
840 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
841 plane ? "B" : "A", size);
842
843 return size;
844}
845
1fa61106 846static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 847{
848 struct drm_i915_private *dev_priv = dev->dev_private;
849 uint32_t dsparb = I915_READ(DSPARB);
850 int size;
851
852 size = dsparb & 0x7f;
853 size >>= 2; /* Convert to cachelines */
854
855 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
856 plane ? "B" : "A",
857 size);
858
859 return size;
860}
861
1fa61106 862static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 863{
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 uint32_t dsparb = I915_READ(DSPARB);
866 int size;
867
868 size = dsparb & 0x7f;
869 size >>= 1; /* Convert to cachelines */
870
871 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
872 plane ? "B" : "A", size);
873
874 return size;
875}
876
877/* Pineview has different values for various configs */
878static const struct intel_watermark_params pineview_display_wm = {
879 PINEVIEW_DISPLAY_FIFO,
880 PINEVIEW_MAX_WM,
881 PINEVIEW_DFT_WM,
882 PINEVIEW_GUARD_WM,
883 PINEVIEW_FIFO_LINE_SIZE
884};
885static const struct intel_watermark_params pineview_display_hplloff_wm = {
886 PINEVIEW_DISPLAY_FIFO,
887 PINEVIEW_MAX_WM,
888 PINEVIEW_DFT_HPLLOFF_WM,
889 PINEVIEW_GUARD_WM,
890 PINEVIEW_FIFO_LINE_SIZE
891};
892static const struct intel_watermark_params pineview_cursor_wm = {
893 PINEVIEW_CURSOR_FIFO,
894 PINEVIEW_CURSOR_MAX_WM,
895 PINEVIEW_CURSOR_DFT_WM,
896 PINEVIEW_CURSOR_GUARD_WM,
897 PINEVIEW_FIFO_LINE_SIZE,
898};
899static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
900 PINEVIEW_CURSOR_FIFO,
901 PINEVIEW_CURSOR_MAX_WM,
902 PINEVIEW_CURSOR_DFT_WM,
903 PINEVIEW_CURSOR_GUARD_WM,
904 PINEVIEW_FIFO_LINE_SIZE
905};
906static const struct intel_watermark_params g4x_wm_info = {
907 G4X_FIFO_SIZE,
908 G4X_MAX_WM,
909 G4X_MAX_WM,
910 2,
911 G4X_FIFO_LINE_SIZE,
912};
913static const struct intel_watermark_params g4x_cursor_wm_info = {
914 I965_CURSOR_FIFO,
915 I965_CURSOR_MAX_WM,
916 I965_CURSOR_DFT_WM,
917 2,
918 G4X_FIFO_LINE_SIZE,
919};
920static const struct intel_watermark_params valleyview_wm_info = {
921 VALLEYVIEW_FIFO_SIZE,
922 VALLEYVIEW_MAX_WM,
923 VALLEYVIEW_MAX_WM,
924 2,
925 G4X_FIFO_LINE_SIZE,
926};
927static const struct intel_watermark_params valleyview_cursor_wm_info = {
928 I965_CURSOR_FIFO,
929 VALLEYVIEW_CURSOR_MAX_WM,
930 I965_CURSOR_DFT_WM,
931 2,
932 G4X_FIFO_LINE_SIZE,
933};
934static const struct intel_watermark_params i965_cursor_wm_info = {
935 I965_CURSOR_FIFO,
936 I965_CURSOR_MAX_WM,
937 I965_CURSOR_DFT_WM,
938 2,
939 I915_FIFO_LINE_SIZE,
940};
941static const struct intel_watermark_params i945_wm_info = {
942 I945_FIFO_SIZE,
943 I915_MAX_WM,
944 1,
945 2,
946 I915_FIFO_LINE_SIZE
947};
948static const struct intel_watermark_params i915_wm_info = {
949 I915_FIFO_SIZE,
950 I915_MAX_WM,
951 1,
952 2,
953 I915_FIFO_LINE_SIZE
954};
955static const struct intel_watermark_params i855_wm_info = {
956 I855GM_FIFO_SIZE,
957 I915_MAX_WM,
958 1,
959 2,
960 I830_FIFO_LINE_SIZE
961};
962static const struct intel_watermark_params i830_wm_info = {
963 I830_FIFO_SIZE,
964 I915_MAX_WM,
965 1,
966 2,
967 I830_FIFO_LINE_SIZE
968};
969
970static const struct intel_watermark_params ironlake_display_wm_info = {
971 ILK_DISPLAY_FIFO,
972 ILK_DISPLAY_MAXWM,
973 ILK_DISPLAY_DFTWM,
974 2,
975 ILK_FIFO_LINE_SIZE
976};
977static const struct intel_watermark_params ironlake_cursor_wm_info = {
978 ILK_CURSOR_FIFO,
979 ILK_CURSOR_MAXWM,
980 ILK_CURSOR_DFTWM,
981 2,
982 ILK_FIFO_LINE_SIZE
983};
984static const struct intel_watermark_params ironlake_display_srwm_info = {
985 ILK_DISPLAY_SR_FIFO,
986 ILK_DISPLAY_MAX_SRWM,
987 ILK_DISPLAY_DFT_SRWM,
988 2,
989 ILK_FIFO_LINE_SIZE
990};
991static const struct intel_watermark_params ironlake_cursor_srwm_info = {
992 ILK_CURSOR_SR_FIFO,
993 ILK_CURSOR_MAX_SRWM,
994 ILK_CURSOR_DFT_SRWM,
995 2,
996 ILK_FIFO_LINE_SIZE
997};
998
999static const struct intel_watermark_params sandybridge_display_wm_info = {
1000 SNB_DISPLAY_FIFO,
1001 SNB_DISPLAY_MAXWM,
1002 SNB_DISPLAY_DFTWM,
1003 2,
1004 SNB_FIFO_LINE_SIZE
1005};
1006static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1007 SNB_CURSOR_FIFO,
1008 SNB_CURSOR_MAXWM,
1009 SNB_CURSOR_DFTWM,
1010 2,
1011 SNB_FIFO_LINE_SIZE
1012};
1013static const struct intel_watermark_params sandybridge_display_srwm_info = {
1014 SNB_DISPLAY_SR_FIFO,
1015 SNB_DISPLAY_MAX_SRWM,
1016 SNB_DISPLAY_DFT_SRWM,
1017 2,
1018 SNB_FIFO_LINE_SIZE
1019};
1020static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1021 SNB_CURSOR_SR_FIFO,
1022 SNB_CURSOR_MAX_SRWM,
1023 SNB_CURSOR_DFT_SRWM,
1024 2,
1025 SNB_FIFO_LINE_SIZE
1026};
1027
1028
1029/**
1030 * intel_calculate_wm - calculate watermark level
1031 * @clock_in_khz: pixel clock
1032 * @wm: chip FIFO params
1033 * @pixel_size: display pixel size
1034 * @latency_ns: memory latency for the platform
1035 *
1036 * Calculate the watermark level (the level at which the display plane will
1037 * start fetching from memory again). Each chip has a different display
1038 * FIFO size and allocation, so the caller needs to figure that out and pass
1039 * in the correct intel_watermark_params structure.
1040 *
1041 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1042 * on the pixel size. When it reaches the watermark level, it'll start
1043 * fetching FIFO line sized based chunks from memory until the FIFO fills
1044 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1045 * will occur, and a display engine hang could result.
1046 */
1047static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1048 const struct intel_watermark_params *wm,
1049 int fifo_size,
1050 int pixel_size,
1051 unsigned long latency_ns)
1052{
1053 long entries_required, wm_size;
1054
1055 /*
1056 * Note: we need to make sure we don't overflow for various clock &
1057 * latency values.
1058 * clocks go from a few thousand to several hundred thousand.
1059 * latency is usually a few thousand
1060 */
1061 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1062 1000;
1063 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1064
1065 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1066
1067 wm_size = fifo_size - (entries_required + wm->guard_size);
1068
1069 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1070
1071 /* Don't promote wm_size to unsigned... */
1072 if (wm_size > (long)wm->max_wm)
1073 wm_size = wm->max_wm;
1074 if (wm_size <= 0)
1075 wm_size = wm->default_wm;
1076 return wm_size;
1077}
1078
1079static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1080{
1081 struct drm_crtc *crtc, *enabled = NULL;
1082
1083 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1084 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1085 if (enabled)
1086 return NULL;
1087 enabled = crtc;
1088 }
1089 }
1090
1091 return enabled;
1092}
1093
46ba614c 1094static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1095{
46ba614c 1096 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 struct drm_crtc *crtc;
1099 const struct cxsr_latency *latency;
1100 u32 reg;
1101 unsigned long wm;
1102
1103 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1104 dev_priv->fsb_freq, dev_priv->mem_freq);
1105 if (!latency) {
1106 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1107 pineview_disable_cxsr(dev);
1108 return;
1109 }
1110
1111 crtc = single_enabled_crtc(dev);
1112 if (crtc) {
241bfc38 1113 const struct drm_display_mode *adjusted_mode;
b445e3b0 1114 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1115 int clock;
1116
1117 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1118 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1119
1120 /* Display SR */
1121 wm = intel_calculate_wm(clock, &pineview_display_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->display_sr);
1124 reg = I915_READ(DSPFW1);
1125 reg &= ~DSPFW_SR_MASK;
1126 reg |= wm << DSPFW_SR_SHIFT;
1127 I915_WRITE(DSPFW1, reg);
1128 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1129
1130 /* cursor SR */
1131 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1132 pineview_display_wm.fifo_size,
1133 pixel_size, latency->cursor_sr);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_CURSOR_SR_MASK;
1136 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* Display HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->display_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_SR_MASK;
1145 reg |= wm & DSPFW_HPLL_SR_MASK;
1146 I915_WRITE(DSPFW3, reg);
1147
1148 /* cursor HPLL off SR */
1149 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1150 pineview_display_hplloff_wm.fifo_size,
1151 pixel_size, latency->cursor_hpll_disable);
1152 reg = I915_READ(DSPFW3);
1153 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1154 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1155 I915_WRITE(DSPFW3, reg);
1156 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1157
1158 /* activate cxsr */
1159 I915_WRITE(DSPFW3,
1160 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1161 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1162 } else {
1163 pineview_disable_cxsr(dev);
1164 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1165 }
1166}
1167
1168static bool g4x_compute_wm0(struct drm_device *dev,
1169 int plane,
1170 const struct intel_watermark_params *display,
1171 int display_latency_ns,
1172 const struct intel_watermark_params *cursor,
1173 int cursor_latency_ns,
1174 int *plane_wm,
1175 int *cursor_wm)
1176{
1177 struct drm_crtc *crtc;
4fe8590a 1178 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1179 int htotal, hdisplay, clock, pixel_size;
1180 int line_time_us, line_count;
1181 int entries, tlb_miss;
1182
1183 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1184 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1185 *cursor_wm = cursor->guard_size;
1186 *plane_wm = display->guard_size;
1187 return false;
1188 }
1189
4fe8590a 1190 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1191 clock = adjusted_mode->crtc_clock;
4fe8590a 1192 htotal = adjusted_mode->htotal;
37327abd 1193 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1194 pixel_size = crtc->fb->bits_per_pixel / 8;
1195
1196 /* Use the small buffer method to calculate plane watermark */
1197 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1198 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1199 if (tlb_miss > 0)
1200 entries += tlb_miss;
1201 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1202 *plane_wm = entries + display->guard_size;
1203 if (*plane_wm > (int)display->max_wm)
1204 *plane_wm = display->max_wm;
1205
1206 /* Use the large buffer method to calculate cursor watermark */
1207 line_time_us = ((htotal * 1000) / clock);
1208 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1209 entries = line_count * 64 * pixel_size;
1210 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1211 if (tlb_miss > 0)
1212 entries += tlb_miss;
1213 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1214 *cursor_wm = entries + cursor->guard_size;
1215 if (*cursor_wm > (int)cursor->max_wm)
1216 *cursor_wm = (int)cursor->max_wm;
1217
1218 return true;
1219}
1220
1221/*
1222 * Check the wm result.
1223 *
1224 * If any calculated watermark values is larger than the maximum value that
1225 * can be programmed into the associated watermark register, that watermark
1226 * must be disabled.
1227 */
1228static bool g4x_check_srwm(struct drm_device *dev,
1229 int display_wm, int cursor_wm,
1230 const struct intel_watermark_params *display,
1231 const struct intel_watermark_params *cursor)
1232{
1233 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1234 display_wm, cursor_wm);
1235
1236 if (display_wm > display->max_wm) {
1237 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1238 display_wm, display->max_wm);
1239 return false;
1240 }
1241
1242 if (cursor_wm > cursor->max_wm) {
1243 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1244 cursor_wm, cursor->max_wm);
1245 return false;
1246 }
1247
1248 if (!(display_wm || cursor_wm)) {
1249 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1250 return false;
1251 }
1252
1253 return true;
1254}
1255
1256static bool g4x_compute_srwm(struct drm_device *dev,
1257 int plane,
1258 int latency_ns,
1259 const struct intel_watermark_params *display,
1260 const struct intel_watermark_params *cursor,
1261 int *display_wm, int *cursor_wm)
1262{
1263 struct drm_crtc *crtc;
4fe8590a 1264 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1265 int hdisplay, htotal, pixel_size, clock;
1266 unsigned long line_time_us;
1267 int line_count, line_size;
1268 int small, large;
1269 int entries;
1270
1271 if (!latency_ns) {
1272 *display_wm = *cursor_wm = 0;
1273 return false;
1274 }
1275
1276 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1277 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1278 clock = adjusted_mode->crtc_clock;
4fe8590a 1279 htotal = adjusted_mode->htotal;
37327abd 1280 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1281 pixel_size = crtc->fb->bits_per_pixel / 8;
1282
1283 line_time_us = (htotal * 1000) / clock;
1284 line_count = (latency_ns / line_time_us + 1000) / 1000;
1285 line_size = hdisplay * pixel_size;
1286
1287 /* Use the minimum of the small and large buffer method for primary */
1288 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1289 large = line_count * line_size;
1290
1291 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1292 *display_wm = entries + display->guard_size;
1293
1294 /* calculate the self-refresh watermark for display cursor */
1295 entries = line_count * pixel_size * 64;
1296 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1297 *cursor_wm = entries + cursor->guard_size;
1298
1299 return g4x_check_srwm(dev,
1300 *display_wm, *cursor_wm,
1301 display, cursor);
1302}
1303
1304static bool vlv_compute_drain_latency(struct drm_device *dev,
1305 int plane,
1306 int *plane_prec_mult,
1307 int *plane_dl,
1308 int *cursor_prec_mult,
1309 int *cursor_dl)
1310{
1311 struct drm_crtc *crtc;
1312 int clock, pixel_size;
1313 int entries;
1314
1315 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1316 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1317 return false;
1318
241bfc38 1319 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1320 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1321
1322 entries = (clock / 1000) * pixel_size;
1323 *plane_prec_mult = (entries > 256) ?
1324 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1325 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1326 pixel_size);
1327
1328 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1329 *cursor_prec_mult = (entries > 256) ?
1330 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1331 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1332
1333 return true;
1334}
1335
1336/*
1337 * Update drain latency registers of memory arbiter
1338 *
1339 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1340 * to be programmed. Each plane has a drain latency multiplier and a drain
1341 * latency value.
1342 */
1343
1344static void vlv_update_drain_latency(struct drm_device *dev)
1345{
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1348 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1349 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1350 either 16 or 32 */
1351
1352 /* For plane A, Cursor A */
1353 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1354 &cursor_prec_mult, &cursora_dl)) {
1355 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1357 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1359
1360 I915_WRITE(VLV_DDL1, cursora_prec |
1361 (cursora_dl << DDL_CURSORA_SHIFT) |
1362 planea_prec | planea_dl);
1363 }
1364
1365 /* For plane B, Cursor B */
1366 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1367 &cursor_prec_mult, &cursorb_dl)) {
1368 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1370 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1371 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1372
1373 I915_WRITE(VLV_DDL2, cursorb_prec |
1374 (cursorb_dl << DDL_CURSORB_SHIFT) |
1375 planeb_prec | planeb_dl);
1376 }
1377}
1378
1379#define single_plane_enabled(mask) is_power_of_2(mask)
1380
46ba614c 1381static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1382{
46ba614c 1383 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1384 static const int sr_latency_ns = 12000;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1387 int plane_sr, cursor_sr;
af6c4575 1388 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1389 unsigned int enabled = 0;
1390
1391 vlv_update_drain_latency(dev);
1392
51cea1f4 1393 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1394 &valleyview_wm_info, latency_ns,
1395 &valleyview_cursor_wm_info, latency_ns,
1396 &planea_wm, &cursora_wm))
51cea1f4 1397 enabled |= 1 << PIPE_A;
b445e3b0 1398
51cea1f4 1399 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1400 &valleyview_wm_info, latency_ns,
1401 &valleyview_cursor_wm_info, latency_ns,
1402 &planeb_wm, &cursorb_wm))
51cea1f4 1403 enabled |= 1 << PIPE_B;
b445e3b0 1404
b445e3b0
ED		 1405 if (single_plane_enabled(enabled) &&
1406 g4x_compute_srwm(dev, ffs(enabled) - 1,
1407 sr_latency_ns,
1408 &valleyview_wm_info,
1409 &valleyview_cursor_wm_info,
af6c4575
CW		 1410 &plane_sr, &ignore_cursor_sr) &&
1411 g4x_compute_srwm(dev, ffs(enabled) - 1,
1412 2*sr_latency_ns,
1413 &valleyview_wm_info,
1414 &valleyview_cursor_wm_info,
52bd02d8 1415 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1416 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1417 } else {
b445e3b0
ED		 1418 I915_WRITE(FW_BLC_SELF_VLV,
1419 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1420 plane_sr = cursor_sr = 0;
1421 }
b445e3b0
ED		 1422
1423 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1424 planea_wm, cursora_wm,
1425 planeb_wm, cursorb_wm,
1426 plane_sr, cursor_sr);
1427
1428 I915_WRITE(DSPFW1,
1429 (plane_sr << DSPFW_SR_SHIFT) |
1430 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1431 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1432 planea_wm);
1433 I915_WRITE(DSPFW2,
8c919b28 1434 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1435 (cursora_wm << DSPFW_CURSORA_SHIFT));
1436 I915_WRITE(DSPFW3,
8c919b28
CW		 1437 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1438 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1439}
1440
46ba614c 1441static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1442{
46ba614c 1443 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1444 static const int sr_latency_ns = 12000;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1447 int plane_sr, cursor_sr;
1448 unsigned int enabled = 0;
1449
51cea1f4 1450 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1451 &g4x_wm_info, latency_ns,
1452 &g4x_cursor_wm_info, latency_ns,
1453 &planea_wm, &cursora_wm))
51cea1f4 1454 enabled |= 1 << PIPE_A;
b445e3b0 1455
51cea1f4 1456 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1457 &g4x_wm_info, latency_ns,
1458 &g4x_cursor_wm_info, latency_ns,
1459 &planeb_wm, &cursorb_wm))
51cea1f4 1460 enabled |= 1 << PIPE_B;
b445e3b0 1461
b445e3b0
ED		 1462 if (single_plane_enabled(enabled) &&
1463 g4x_compute_srwm(dev, ffs(enabled) - 1,
1464 sr_latency_ns,
1465 &g4x_wm_info,
1466 &g4x_cursor_wm_info,
52bd02d8 1467 &plane_sr, &cursor_sr)) {
b445e3b0 1468 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1469 } else {
b445e3b0
ED		 1470 I915_WRITE(FW_BLC_SELF,
1471 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1472 plane_sr = cursor_sr = 0;
1473 }
b445e3b0
ED		 1474
1475 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1476 planea_wm, cursora_wm,
1477 planeb_wm, cursorb_wm,
1478 plane_sr, cursor_sr);
1479
1480 I915_WRITE(DSPFW1,
1481 (plane_sr << DSPFW_SR_SHIFT) |
1482 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1483 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1484 planea_wm);
1485 I915_WRITE(DSPFW2,
8c919b28 1486 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1487 (cursora_wm << DSPFW_CURSORA_SHIFT));
1488 /* HPLL off in SR has some issues on G4x... disable it */
1489 I915_WRITE(DSPFW3,
8c919b28 1490 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1491 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1492}
1493
46ba614c 1494static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1495{
46ba614c 1496 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 struct drm_crtc *crtc;
1499 int srwm = 1;
1500 int cursor_sr = 16;
1501
1502 /* Calc sr entries for one plane configs */
1503 crtc = single_enabled_crtc(dev);
1504 if (crtc) {
1505 /* self-refresh has much higher latency */
1506 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1507 const struct drm_display_mode *adjusted_mode =
1508 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1509 int clock = adjusted_mode->crtc_clock;
4fe8590a 1510 int htotal = adjusted_mode->htotal;
37327abd 1511 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1512 int pixel_size = crtc->fb->bits_per_pixel / 8;
1513 unsigned long line_time_us;
1514 int entries;
1515
1516 line_time_us = ((htotal * 1000) / clock);
1517
1518 /* Use ns/us then divide to preserve precision */
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520 pixel_size * hdisplay;
1521 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1522 srwm = I965_FIFO_SIZE - entries;
1523 if (srwm < 0)
1524 srwm = 1;
1525 srwm &= 0x1ff;
1526 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1527 entries, srwm);
1528
1529 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1530 pixel_size * 64;
1531 entries = DIV_ROUND_UP(entries,
1532 i965_cursor_wm_info.cacheline_size);
1533 cursor_sr = i965_cursor_wm_info.fifo_size -
1534 (entries + i965_cursor_wm_info.guard_size);
1535
1536 if (cursor_sr > i965_cursor_wm_info.max_wm)
1537 cursor_sr = i965_cursor_wm_info.max_wm;
1538
1539 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1540 "cursor %d\n", srwm, cursor_sr);
1541
1542 if (IS_CRESTLINE(dev))
1543 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1544 } else {
1545 /* Turn off self refresh if both pipes are enabled */
1546 if (IS_CRESTLINE(dev))
1547 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1548 & ~FW_BLC_SELF_EN);
1549 }
1550
1551 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1552 srwm);
1553
1554 /* 965 has limitations... */
1555 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1556 (8 << 16) | (8 << 8) | (8 << 0));
1557 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1558 /* update cursor SR watermark */
1559 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1560}
1561
46ba614c 1562static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1563{
46ba614c 1564 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 const struct intel_watermark_params *wm_info;
1567 uint32_t fwater_lo;
1568 uint32_t fwater_hi;
1569 int cwm, srwm = 1;
1570 int fifo_size;
1571 int planea_wm, planeb_wm;
1572 struct drm_crtc *crtc, *enabled = NULL;
1573
1574 if (IS_I945GM(dev))
1575 wm_info = &i945_wm_info;
1576 else if (!IS_GEN2(dev))
1577 wm_info = &i915_wm_info;
1578 else
1579 wm_info = &i855_wm_info;
1580
1581 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1582 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1583 if (intel_crtc_active(crtc)) {
241bfc38 1584 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1585 int cpp = crtc->fb->bits_per_pixel / 8;
1586 if (IS_GEN2(dev))
1587 cpp = 4;
1588
241bfc38
DL		 1589 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1590 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1591 wm_info, fifo_size, cpp,
b445e3b0
ED		 1592 latency_ns);
1593 enabled = crtc;
1594 } else
1595 planea_wm = fifo_size - wm_info->guard_size;
1596
1597 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1598 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1599 if (intel_crtc_active(crtc)) {
241bfc38 1600 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1601 int cpp = crtc->fb->bits_per_pixel / 8;
1602 if (IS_GEN2(dev))
1603 cpp = 4;
1604
241bfc38
DL		 1605 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1606 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1607 wm_info, fifo_size, cpp,
b445e3b0
ED		 1608 latency_ns);
1609 if (enabled == NULL)
1610 enabled = crtc;
1611 else
1612 enabled = NULL;
1613 } else
1614 planeb_wm = fifo_size - wm_info->guard_size;
1615
1616 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1617
1618 /*
1619 * Overlay gets an aggressive default since video jitter is bad.
1620 */
1621 cwm = 2;
1622
1623 /* Play safe and disable self-refresh before adjusting watermarks. */
1624 if (IS_I945G(dev) || IS_I945GM(dev))
1625 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1626 else if (IS_I915GM(dev))
1627 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1628
1629 /* Calc sr entries for one plane configs */
1630 if (HAS_FW_BLC(dev) && enabled) {
1631 /* self-refresh has much higher latency */
1632 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1633 const struct drm_display_mode *adjusted_mode =
1634 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1635 int clock = adjusted_mode->crtc_clock;
4fe8590a 1636 int htotal = adjusted_mode->htotal;
f727b490 1637 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
b445e3b0
ED		 1638 int pixel_size = enabled->fb->bits_per_pixel / 8;
1639 unsigned long line_time_us;
1640 int entries;
1641
1642 line_time_us = (htotal * 1000) / clock;
1643
1644 /* Use ns/us then divide to preserve precision */
1645 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1646 pixel_size * hdisplay;
1647 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1648 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1649 srwm = wm_info->fifo_size - entries;
1650 if (srwm < 0)
1651 srwm = 1;
1652
1653 if (IS_I945G(dev) || IS_I945GM(dev))
1654 I915_WRITE(FW_BLC_SELF,
1655 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1656 else if (IS_I915GM(dev))
1657 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1658 }
1659
1660 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1661 planea_wm, planeb_wm, cwm, srwm);
1662
1663 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1664 fwater_hi = (cwm & 0x1f);
1665
1666 /* Set request length to 8 cachelines per fetch */
1667 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1668 fwater_hi = fwater_hi | (1 << 8);
1669
1670 I915_WRITE(FW_BLC, fwater_lo);
1671 I915_WRITE(FW_BLC2, fwater_hi);
1672
1673 if (HAS_FW_BLC(dev)) {
1674 if (enabled) {
1675 if (IS_I945G(dev) || IS_I945GM(dev))
1676 I915_WRITE(FW_BLC_SELF,
1677 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1678 else if (IS_I915GM(dev))
1679 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1680 DRM_DEBUG_KMS("memory self refresh enabled\n");
1681 } else
1682 DRM_DEBUG_KMS("memory self refresh disabled\n");
1683 }
1684}
1685
46ba614c 1686static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1687{
46ba614c 1688 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 struct drm_crtc *crtc;
241bfc38 1691 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1692 uint32_t fwater_lo;
1693 int planea_wm;
1694
1695 crtc = single_enabled_crtc(dev);
1696 if (crtc == NULL)
1697 return;
1698
241bfc38
DL		 1699 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1700 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1701 &i830_wm_info,
b445e3b0 1702 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1703 4, latency_ns);
b445e3b0
ED		 1704 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1705 fwater_lo |= (3<<8) | planea_wm;
1706
1707 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1708
1709 I915_WRITE(FW_BLC, fwater_lo);
1710}
1711
b445e3b0
ED		 1712/*
1713 * Check the wm result.
1714 *
1715 * If any calculated watermark values is larger than the maximum value that
1716 * can be programmed into the associated watermark register, that watermark
1717 * must be disabled.
1718 */
1719static bool ironlake_check_srwm(struct drm_device *dev, int level,
1720 int fbc_wm, int display_wm, int cursor_wm,
1721 const struct intel_watermark_params *display,
1722 const struct intel_watermark_params *cursor)
1723{
1724 struct drm_i915_private *dev_priv = dev->dev_private;
1725
1726 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1727 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1728
1729 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1730 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1731 fbc_wm, SNB_FBC_MAX_SRWM, level);
1732
1733 /* fbc has it's own way to disable FBC WM */
1734 I915_WRITE(DISP_ARB_CTL,
1735 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1736 return false;
615aaa5f
VS		 1737 } else if (INTEL_INFO(dev)->gen >= 6) {
1738 /* enable FBC WM (except on ILK, where it must remain off) */
1739 I915_WRITE(DISP_ARB_CTL,
1740 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1741 }
1742
1743 if (display_wm > display->max_wm) {
1744 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1745 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1746 return false;
1747 }
1748
1749 if (cursor_wm > cursor->max_wm) {
1750 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1751 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1752 return false;
1753 }
1754
1755 if (!(fbc_wm || display_wm || cursor_wm)) {
1756 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1757 return false;
1758 }
1759
1760 return true;
1761}
1762
1763/*
1764 * Compute watermark values of WM[1-3],
1765 */
1766static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1767 int latency_ns,
1768 const struct intel_watermark_params *display,
1769 const struct intel_watermark_params *cursor,
1770 int *fbc_wm, int *display_wm, int *cursor_wm)
1771{
1772 struct drm_crtc *crtc;
4fe8590a 1773 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1774 unsigned long line_time_us;
1775 int hdisplay, htotal, pixel_size, clock;
1776 int line_count, line_size;
1777 int small, large;
1778 int entries;
1779
1780 if (!latency_ns) {
1781 *fbc_wm = *display_wm = *cursor_wm = 0;
1782 return false;
1783 }
1784
1785 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1786 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1787 clock = adjusted_mode->crtc_clock;
4fe8590a 1788 htotal = adjusted_mode->htotal;
37327abd 1789 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1790 pixel_size = crtc->fb->bits_per_pixel / 8;
1791
1792 line_time_us = (htotal * 1000) / clock;
1793 line_count = (latency_ns / line_time_us + 1000) / 1000;
1794 line_size = hdisplay * pixel_size;
1795
1796 /* Use the minimum of the small and large buffer method for primary */
1797 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1798 large = line_count * line_size;
1799
1800 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1801 *display_wm = entries + display->guard_size;
1802
1803 /*
1804 * Spec says:
1805 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1806 */
1807 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1808
1809 /* calculate the self-refresh watermark for display cursor */
1810 entries = line_count * pixel_size * 64;
1811 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1812 *cursor_wm = entries + cursor->guard_size;
1813
1814 return ironlake_check_srwm(dev, level,
1815 *fbc_wm, *display_wm, *cursor_wm,
1816 display, cursor);
1817}
1818
46ba614c 1819static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1820{
46ba614c 1821 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 int fbc_wm, plane_wm, cursor_wm;
1824 unsigned int enabled;
1825
1826 enabled = 0;
51cea1f4 1827 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1828 &ironlake_display_wm_info,
b0aea5dc 1829 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1830 &ironlake_cursor_wm_info,
b0aea5dc 1831 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1832 &plane_wm, &cursor_wm)) {
1833 I915_WRITE(WM0_PIPEA_ILK,
1834 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1835 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1836 " plane %d, " "cursor: %d\n",
1837 plane_wm, cursor_wm);
51cea1f4 1838 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1839 }
1840
51cea1f4 1841 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1842 &ironlake_display_wm_info,
b0aea5dc 1843 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1844 &ironlake_cursor_wm_info,
b0aea5dc 1845 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1846 &plane_wm, &cursor_wm)) {
1847 I915_WRITE(WM0_PIPEB_ILK,
1848 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1849 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1850 " plane %d, cursor: %d\n",
1851 plane_wm, cursor_wm);
51cea1f4 1852 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1853 }
1854
1855 /*
1856 * Calculate and update the self-refresh watermark only when one
1857 * display plane is used.
1858 */
1859 I915_WRITE(WM3_LP_ILK, 0);
1860 I915_WRITE(WM2_LP_ILK, 0);
1861 I915_WRITE(WM1_LP_ILK, 0);
1862
1863 if (!single_plane_enabled(enabled))
1864 return;
1865 enabled = ffs(enabled) - 1;
1866
1867 /* WM1 */
1868 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1869 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1870 &ironlake_display_srwm_info,
1871 &ironlake_cursor_srwm_info,
1872 &fbc_wm, &plane_wm, &cursor_wm))
1873 return;
1874
1875 I915_WRITE(WM1_LP_ILK,
1876 WM1_LP_SR_EN |
b0aea5dc 1877 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1878 (fbc_wm << WM1_LP_FBC_SHIFT) |
1879 (plane_wm << WM1_LP_SR_SHIFT) |
1880 cursor_wm);
1881
1882 /* WM2 */
1883 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1884 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1885 &ironlake_display_srwm_info,
1886 &ironlake_cursor_srwm_info,
1887 &fbc_wm, &plane_wm, &cursor_wm))
1888 return;
1889
1890 I915_WRITE(WM2_LP_ILK,
1891 WM2_LP_EN |
b0aea5dc 1892 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1893 (fbc_wm << WM1_LP_FBC_SHIFT) |
1894 (plane_wm << WM1_LP_SR_SHIFT) |
1895 cursor_wm);
1896
1897 /*
1898 * WM3 is unsupported on ILK, probably because we don't have latency
1899 * data for that power state
1900 */
1901}
1902
46ba614c 1903static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1904{
46ba614c 1905 struct drm_device *dev = crtc->dev;
b445e3b0 1906 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1907 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1908 u32 val;
1909 int fbc_wm, plane_wm, cursor_wm;
1910 unsigned int enabled;
1911
1912 enabled = 0;
51cea1f4 1913 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1914 &sandybridge_display_wm_info, latency,
1915 &sandybridge_cursor_wm_info, latency,
1916 &plane_wm, &cursor_wm)) {
1917 val = I915_READ(WM0_PIPEA_ILK);
1918 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1919 I915_WRITE(WM0_PIPEA_ILK, val |
1920 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1921 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1922 " plane %d, " "cursor: %d\n",
1923 plane_wm, cursor_wm);
51cea1f4 1924 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1925 }
1926
51cea1f4 1927 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1928 &sandybridge_display_wm_info, latency,
1929 &sandybridge_cursor_wm_info, latency,
1930 &plane_wm, &cursor_wm)) {
1931 val = I915_READ(WM0_PIPEB_ILK);
1932 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1933 I915_WRITE(WM0_PIPEB_ILK, val |
1934 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1935 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1936 " plane %d, cursor: %d\n",
1937 plane_wm, cursor_wm);
51cea1f4 1938 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1939 }
1940
c43d0188
CW		 1941 /*
1942 * Calculate and update the self-refresh watermark only when one
1943 * display plane is used.
1944 *
1945 * SNB support 3 levels of watermark.
1946 *
1947 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1948 * and disabled in the descending order
1949 *
1950 */
1951 I915_WRITE(WM3_LP_ILK, 0);
1952 I915_WRITE(WM2_LP_ILK, 0);
1953 I915_WRITE(WM1_LP_ILK, 0);
1954
1955 if (!single_plane_enabled(enabled) ||
1956 dev_priv->sprite_scaling_enabled)
1957 return;
1958 enabled = ffs(enabled) - 1;
1959
1960 /* WM1 */
1961 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1962 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1963 &sandybridge_display_srwm_info,
1964 &sandybridge_cursor_srwm_info,
1965 &fbc_wm, &plane_wm, &cursor_wm))
1966 return;
1967
1968 I915_WRITE(WM1_LP_ILK,
1969 WM1_LP_SR_EN |
b0aea5dc 1970 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1971 (fbc_wm << WM1_LP_FBC_SHIFT) |
1972 (plane_wm << WM1_LP_SR_SHIFT) |
1973 cursor_wm);
1974
1975 /* WM2 */
1976 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1977 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1978 &sandybridge_display_srwm_info,
1979 &sandybridge_cursor_srwm_info,
1980 &fbc_wm, &plane_wm, &cursor_wm))
1981 return;
1982
1983 I915_WRITE(WM2_LP_ILK,
1984 WM2_LP_EN |
b0aea5dc 1985 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1986 (fbc_wm << WM1_LP_FBC_SHIFT) |
1987 (plane_wm << WM1_LP_SR_SHIFT) |
1988 cursor_wm);
1989
1990 /* WM3 */
1991 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1992 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1993 &sandybridge_display_srwm_info,
1994 &sandybridge_cursor_srwm_info,
1995 &fbc_wm, &plane_wm, &cursor_wm))
1996 return;
1997
1998 I915_WRITE(WM3_LP_ILK,
1999 WM3_LP_EN |
b0aea5dc 2000 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 2001 (fbc_wm << WM1_LP_FBC_SHIFT) |
2002 (plane_wm << WM1_LP_SR_SHIFT) |
2003 cursor_wm);
2004}
2005
46ba614c 2006static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 2007{
46ba614c 2008 struct drm_device *dev = crtc->dev;
c43d0188 2009 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2010 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2011 u32 val;
2012 int fbc_wm, plane_wm, cursor_wm;
2013 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2014 unsigned int enabled;
2015
2016 enabled = 0;
51cea1f4 2017 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2018 &sandybridge_display_wm_info, latency,
2019 &sandybridge_cursor_wm_info, latency,
2020 &plane_wm, &cursor_wm)) {
2021 val = I915_READ(WM0_PIPEA_ILK);
2022 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2023 I915_WRITE(WM0_PIPEA_ILK, val |
2024 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2025 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2026 " plane %d, " "cursor: %d\n",
2027 plane_wm, cursor_wm);
51cea1f4 2028 enabled |= 1 << PIPE_A;
c43d0188
CW		 2029 }
2030
51cea1f4 2031 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2032 &sandybridge_display_wm_info, latency,
2033 &sandybridge_cursor_wm_info, latency,
2034 &plane_wm, &cursor_wm)) {
2035 val = I915_READ(WM0_PIPEB_ILK);
2036 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2037 I915_WRITE(WM0_PIPEB_ILK, val |
2038 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2039 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2040 " plane %d, cursor: %d\n",
2041 plane_wm, cursor_wm);
51cea1f4 2042 enabled |= 1 << PIPE_B;
c43d0188
CW		 2043 }
2044
51cea1f4 2045 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2046 &sandybridge_display_wm_info, latency,
2047 &sandybridge_cursor_wm_info, latency,
2048 &plane_wm, &cursor_wm)) {
2049 val = I915_READ(WM0_PIPEC_IVB);
2050 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2051 I915_WRITE(WM0_PIPEC_IVB, val |
2052 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2053 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2054 " plane %d, cursor: %d\n",
2055 plane_wm, cursor_wm);
51cea1f4 2056 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2057 }
2058
2059 /*
2060 * Calculate and update the self-refresh watermark only when one
2061 * display plane is used.
2062 *
2063 * SNB support 3 levels of watermark.
2064 *
2065 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2066 * and disabled in the descending order
2067 *
2068 */
2069 I915_WRITE(WM3_LP_ILK, 0);
2070 I915_WRITE(WM2_LP_ILK, 0);
2071 I915_WRITE(WM1_LP_ILK, 0);
2072
2073 if (!single_plane_enabled(enabled) ||
2074 dev_priv->sprite_scaling_enabled)
2075 return;
2076 enabled = ffs(enabled) - 1;
2077
2078 /* WM1 */
2079 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2080 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2081 &sandybridge_display_srwm_info,
2082 &sandybridge_cursor_srwm_info,
2083 &fbc_wm, &plane_wm, &cursor_wm))
2084 return;
2085
2086 I915_WRITE(WM1_LP_ILK,
2087 WM1_LP_SR_EN |
b0aea5dc 2088 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2089 (fbc_wm << WM1_LP_FBC_SHIFT) |
2090 (plane_wm << WM1_LP_SR_SHIFT) |
2091 cursor_wm);
2092
2093 /* WM2 */
2094 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2095 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2096 &sandybridge_display_srwm_info,
2097 &sandybridge_cursor_srwm_info,
2098 &fbc_wm, &plane_wm, &cursor_wm))
2099 return;
2100
2101 I915_WRITE(WM2_LP_ILK,
2102 WM2_LP_EN |
b0aea5dc 2103 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2104 (fbc_wm << WM1_LP_FBC_SHIFT) |
2105 (plane_wm << WM1_LP_SR_SHIFT) |
2106 cursor_wm);
2107
c43d0188 2108 /* WM3, note we have to correct the cursor latency */
b445e3b0 2109 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2110 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2111 &sandybridge_display_srwm_info,
2112 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2113 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2114 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2115 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2116 &sandybridge_display_srwm_info,
2117 &sandybridge_cursor_srwm_info,
2118 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2119 return;
2120
2121 I915_WRITE(WM3_LP_ILK,
2122 WM3_LP_EN |
b0aea5dc 2123 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2124 (fbc_wm << WM1_LP_FBC_SHIFT) |
2125 (plane_wm << WM1_LP_SR_SHIFT) |
2126 cursor_wm);
2127}
2128
3658729a
VS		 2129static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2130 struct drm_crtc *crtc)
801bcfff
PZ		 2131{
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2133 uint32_t pixel_rate;
801bcfff 2134
241bfc38 2135 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2136
2137 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2138 * adjust the pixel_rate here. */
2139
fd4daa9c 2140 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2141 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2142 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2143
37327abd
VS		 2144 pipe_w = intel_crtc->config.pipe_src_w;
2145 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2146 pfit_w = (pfit_size >> 16) & 0xFFFF;
2147 pfit_h = pfit_size & 0xFFFF;
2148 if (pipe_w < pfit_w)
2149 pipe_w = pfit_w;
2150 if (pipe_h < pfit_h)
2151 pipe_h = pfit_h;
2152
2153 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2154 pfit_w * pfit_h);
2155 }
2156
2157 return pixel_rate;
2158}
2159
37126462 2160/* latency must be in 0.1us units. */
23297044 2161static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2162 uint32_t latency)
2163{
2164 uint64_t ret;
2165
3312ba65
VS		 2166 if (WARN(latency == 0, "Latency value missing\n"))
2167 return UINT_MAX;
2168
801bcfff
PZ		 2169 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2170 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2171
2172 return ret;
2173}
2174
37126462 2175/* latency must be in 0.1us units. */
23297044 2176static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2177 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2178 uint32_t latency)
2179{
2180 uint32_t ret;
2181
3312ba65
VS		 2182 if (WARN(latency == 0, "Latency value missing\n"))
2183 return UINT_MAX;
2184
801bcfff
PZ		 2185 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2186 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2187 ret = DIV_ROUND_UP(ret, 64) + 2;
2188 return ret;
2189}
2190
23297044 2191static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2192 uint8_t bytes_per_pixel)
2193{
2194 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2195}
2196
801bcfff
PZ		 2197struct hsw_pipe_wm_parameters {
2198 bool active;
801bcfff
PZ		 2199 uint32_t pipe_htotal;
2200 uint32_t pixel_rate;
c35426d2
VS		 2201 struct intel_plane_wm_parameters pri;
2202 struct intel_plane_wm_parameters spr;
2203 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2204};
2205
cca32e9a
PZ		 2206struct hsw_wm_maximums {
2207 uint16_t pri;
2208 uint16_t spr;
2209 uint16_t cur;
2210 uint16_t fbc;
2211};
2212
240264f4
VS		 2213/* used in computing the new watermarks state */
2214struct intel_wm_config {
2215 unsigned int num_pipes_active;
2216 bool sprites_enabled;
2217 bool sprites_scaled;
240264f4
VS		 2218};
2219
37126462
VS		 2220/*
2221 * For both WM_PIPE and WM_LP.
2222 * mem_value must be in 0.1us units.
2223 */
ac830fe1 2224static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2225 uint32_t mem_value,
2226 bool is_lp)
801bcfff 2227{
cca32e9a
PZ		 2228 uint32_t method1, method2;
2229
c35426d2 2230 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2231 return 0;
2232
23297044 2233 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2234 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2235 mem_value);
2236
2237 if (!is_lp)
2238 return method1;
2239
23297044 2240 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2241 params->pipe_htotal,
c35426d2
VS		 2242 params->pri.horiz_pixels,
2243 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2244 mem_value);
2245
2246 return min(method1, method2);
801bcfff
PZ		 2247}
2248
37126462
VS		 2249/*
2250 * For both WM_PIPE and WM_LP.
2251 * mem_value must be in 0.1us units.
2252 */
ac830fe1 2253static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2254 uint32_t mem_value)
2255{
2256 uint32_t method1, method2;
2257
c35426d2 2258 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2259 return 0;
2260
23297044 2261 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2262 params->spr.bytes_per_pixel,
801bcfff 2263 mem_value);
23297044 2264 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2265 params->pipe_htotal,
c35426d2
VS		 2266 params->spr.horiz_pixels,
2267 params->spr.bytes_per_pixel,
801bcfff
PZ		 2268 mem_value);
2269 return min(method1, method2);
2270}
2271
37126462
VS		 2272/*
2273 * For both WM_PIPE and WM_LP.
2274 * mem_value must be in 0.1us units.
2275 */
ac830fe1 2276static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2277 uint32_t mem_value)
2278{
c35426d2 2279 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2280 return 0;
2281
23297044 2282 return ilk_wm_method2(params->pixel_rate,
801bcfff 2283 params->pipe_htotal,
c35426d2
VS		 2284 params->cur.horiz_pixels,
2285 params->cur.bytes_per_pixel,
801bcfff
PZ		 2286 mem_value);
2287}
2288
cca32e9a 2289/* Only for WM_LP. */
ac830fe1 2290static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2291 uint32_t pri_val)
cca32e9a 2292{
c35426d2 2293 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2294 return 0;
2295
23297044 2296 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2297 params->pri.horiz_pixels,
2298 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2299}
2300
158ae64f
VS		 2301static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2302{
416f4727
VS		 2303 if (INTEL_INFO(dev)->gen >= 8)
2304 return 3072;
2305 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2306 return 768;
2307 else
2308 return 512;
2309}
2310
2311/* Calculate the maximum primary/sprite plane watermark */
2312static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2313 int level,
240264f4 2314 const struct intel_wm_config *config,
158ae64f
VS		 2315 enum intel_ddb_partitioning ddb_partitioning,
2316 bool is_sprite)
2317{
2318 unsigned int fifo_size = ilk_display_fifo_size(dev);
2319 unsigned int max;
2320
2321 /* if sprites aren't enabled, sprites get nothing */
240264f4 2322 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2323 return 0;
2324
2325 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2326 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2327 fifo_size /= INTEL_INFO(dev)->num_pipes;
2328
2329 /*
2330 * For some reason the non self refresh
2331 * FIFO size is only half of the self
2332 * refresh FIFO size on ILK/SNB.
2333 */
2334 if (INTEL_INFO(dev)->gen <= 6)
2335 fifo_size /= 2;
2336 }
2337
240264f4 2338 if (config->sprites_enabled) {
158ae64f
VS		 2339 /* level 0 is always calculated with 1:1 split */
2340 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2341 if (is_sprite)
2342 fifo_size *= 5;
2343 fifo_size /= 6;
2344 } else {
2345 fifo_size /= 2;
2346 }
2347 }
2348
2349 /* clamp to max that the registers can hold */
416f4727
VS		 2350 if (INTEL_INFO(dev)->gen >= 8)
2351 max = level == 0 ? 255 : 2047;
2352 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2353 /* IVB/HSW primary/sprite plane watermarks */
2354 max = level == 0 ? 127 : 1023;
2355 else if (!is_sprite)
2356 /* ILK/SNB primary plane watermarks */
2357 max = level == 0 ? 127 : 511;
2358 else
2359 /* ILK/SNB sprite plane watermarks */
2360 max = level == 0 ? 63 : 255;
2361
2362 return min(fifo_size, max);
2363}
2364
2365/* Calculate the maximum cursor plane watermark */
2366static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2367 int level,
2368 const struct intel_wm_config *config)
158ae64f
VS		 2369{
2370 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2371 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2372 return 64;
2373
2374 /* otherwise just report max that registers can hold */
2375 if (INTEL_INFO(dev)->gen >= 7)
2376 return level == 0 ? 63 : 255;
2377 else
2378 return level == 0 ? 31 : 63;
2379}
2380
2381/* Calculate the maximum FBC watermark */
416f4727 2382static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 2383{
2384 /* max that registers can hold */
416f4727
VS		 2385 if (INTEL_INFO(dev)->gen >= 8)
2386 return 31;
2387 else
2388 return 15;
158ae64f
VS		 2389}
2390
34982fe1
VS		 2391static void ilk_compute_wm_maximums(struct drm_device *dev,
2392 int level,
2393 const struct intel_wm_config *config,
2394 enum intel_ddb_partitioning ddb_partitioning,
2395 struct hsw_wm_maximums *max)
158ae64f 2396{
240264f4
VS		 2397 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2398 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2399 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 2400 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 2401}
2402
d9395655
VS		 2403static bool ilk_validate_wm_level(int level,
2404 const struct hsw_wm_maximums *max,
2405 struct intel_wm_level *result)
a9786a11
VS		 2406{
2407 bool ret;
2408
2409 /* already determined to be invalid? */
2410 if (!result->enable)
2411 return false;
2412
2413 result->enable = result->pri_val <= max->pri &&
2414 result->spr_val <= max->spr &&
2415 result->cur_val <= max->cur;
2416
2417 ret = result->enable;
2418
2419 /*
2420 * HACK until we can pre-compute everything,
2421 * and thus fail gracefully if LP0 watermarks
2422 * are exceeded...
2423 */
2424 if (level == 0 && !result->enable) {
2425 if (result->pri_val > max->pri)
2426 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2427 level, result->pri_val, max->pri);
2428 if (result->spr_val > max->spr)
2429 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2430 level, result->spr_val, max->spr);
2431 if (result->cur_val > max->cur)
2432 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2433 level, result->cur_val, max->cur);
2434
2435 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2436 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2437 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2438 result->enable = true;
2439 }
2440
a9786a11
VS		 2441 return ret;
2442}
2443
6f5ddd17
VS		 2444static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2445 int level,
ac830fe1 2446 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2447 struct intel_wm_level *result)
6f5ddd17
VS		 2448{
2449 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2450 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2451 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2452
2453 /* WM1+ latency values stored in 0.5us units */
2454 if (level > 0) {
2455 pri_latency *= 5;
2456 spr_latency *= 5;
2457 cur_latency *= 5;
2458 }
2459
2460 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2461 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2462 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2463 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2464 result->enable = true;
2465}
2466
801bcfff
PZ		 2467static uint32_t
2468hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2472 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2473 u32 linetime, ips_linetime;
1f8eeabf 2474
801bcfff
PZ		 2475 if (!intel_crtc_active(crtc))
2476 return 0;
1011d8c4 2477
1f8eeabf
ED		 2478 /* The WM are computed with base on how long it takes to fill a single
2479 * row at the given clock rate, multiplied by 8.
2480 * */
85a02deb
PZ		 2481 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2482 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2483 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2484
801bcfff
PZ		 2485 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2486 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2487}
2488
12b134df
VS		 2489static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2490{
2491 struct drm_i915_private *dev_priv = dev->dev_private;
2492
2493 if (IS_HASWELL(dev)) {
2494 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2495
2496 wm[0] = (sskpd >> 56) & 0xFF;
2497 if (wm[0] == 0)
2498 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2499 wm[1] = (sskpd >> 4) & 0xFF;
2500 wm[2] = (sskpd >> 12) & 0xFF;
2501 wm[3] = (sskpd >> 20) & 0x1FF;
2502 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2503 } else if (INTEL_INFO(dev)->gen >= 6) {
2504 uint32_t sskpd = I915_READ(MCH_SSKPD);
2505
2506 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2507 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2508 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2509 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2510 } else if (INTEL_INFO(dev)->gen >= 5) {
2511 uint32_t mltr = I915_READ(MLTR_ILK);
2512
2513 /* ILK primary LP0 latency is 700 ns */
2514 wm[0] = 7;
2515 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2516 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2517 }
2518}
2519
53615a5e
VS		 2520static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2521{
2522 /* ILK sprite LP0 latency is 1300 ns */
2523 if (INTEL_INFO(dev)->gen == 5)
2524 wm[0] = 13;
2525}
2526
2527static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2528{
2529 /* ILK cursor LP0 latency is 1300 ns */
2530 if (INTEL_INFO(dev)->gen == 5)
2531 wm[0] = 13;
2532
2533 /* WaDoubleCursorLP3Latency:ivb */
2534 if (IS_IVYBRIDGE(dev))
2535 wm[3] *= 2;
2536}
2537
ad0d6dc4 2538static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2539{
26ec971e
VS		 2540 /* how many WM levels are we expecting */
2541 if (IS_HASWELL(dev))
ad0d6dc4 2542 return 4;
26ec971e 2543 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2544 return 3;
26ec971e 2545 else
ad0d6dc4
VS		 2546 return 2;
2547}
2548
2549static void intel_print_wm_latency(struct drm_device *dev,
2550 const char *name,
2551 const uint16_t wm[5])
2552{
2553 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2554
2555 for (level = 0; level <= max_level; level++) {
2556 unsigned int latency = wm[level];
2557
2558 if (latency == 0) {
2559 DRM_ERROR("%s WM%d latency not provided\n",
2560 name, level);
2561 continue;
2562 }
2563
2564 /* WM1+ latency values in 0.5us units */
2565 if (level > 0)
2566 latency *= 5;
2567
2568 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2569 name, level, wm[level],
2570 latency / 10, latency % 10);
2571 }
2572}
2573
53615a5e
VS		 2574static void intel_setup_wm_latency(struct drm_device *dev)
2575{
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577
2578 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2579
2580 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2581 sizeof(dev_priv->wm.pri_latency));
2582 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2583 sizeof(dev_priv->wm.pri_latency));
2584
2585 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2586 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2587
2588 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2589 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2590 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2591}
2592
7c4a395f
VS		 2593static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2594 struct hsw_pipe_wm_parameters *p,
a485bfb8 2595 struct intel_wm_config *config)
1011d8c4 2596{
7c4a395f
VS		 2597 struct drm_device *dev = crtc->dev;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2600 struct drm_plane *plane;
1011d8c4 2601
7c4a395f
VS		 2602 p->active = intel_crtc_active(crtc);
2603 if (p->active) {
801bcfff 2604 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2605 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2606 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2607 p->cur.bytes_per_pixel = 4;
37327abd 2608 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2609 p->cur.horiz_pixels = 64;
2610 /* TODO: for now, assume primary and cursor planes are always enabled. */
2611 p->pri.enabled = true;
2612 p->cur.enabled = true;
801bcfff
PZ		 2613 }
2614
7c4a395f 2615 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2616 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2617
801bcfff
PZ		 2618 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2619 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2620
7c4a395f
VS		 2621 if (intel_plane->pipe == pipe)
2622 p->spr = intel_plane->wm;
cca32e9a 2623
a485bfb8
VS		 2624 config->sprites_enabled |= intel_plane->wm.enabled;
2625 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2626 }
801bcfff
PZ		 2627}
2628
0b2ae6d7
VS		 2629/* Compute new watermarks for the pipe */
2630static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2631 const struct hsw_pipe_wm_parameters *params,
2632 struct intel_pipe_wm *pipe_wm)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 int level, max_level = ilk_wm_max_level(dev);
2637 /* LP0 watermark maximums depend on this pipe alone */
2638 struct intel_wm_config config = {
2639 .num_pipes_active = 1,
2640 .sprites_enabled = params->spr.enabled,
2641 .sprites_scaled = params->spr.scaled,
2642 };
2643 struct hsw_wm_maximums max;
2644
0b2ae6d7 2645 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2646 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7
VS		 2647
2648 for (level = 0; level <= max_level; level++)
2649 ilk_compute_wm_level(dev_priv, level, params,
2650 &pipe_wm->wm[level]);
2651
2652 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2653
2654 /* At least LP0 must be valid */
d9395655 2655 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2656}
2657
2658/*
2659 * Merge the watermarks from all active pipes for a specific level.
2660 */
2661static void ilk_merge_wm_level(struct drm_device *dev,
2662 int level,
2663 struct intel_wm_level *ret_wm)
2664{
2665 const struct intel_crtc *intel_crtc;
2666
2667 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2668 const struct intel_wm_level *wm =
2669 &intel_crtc->wm.active.wm[level];
2670
2671 if (!wm->enable)
2672 return;
2673
2674 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2675 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2676 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2677 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2678 }
2679
2680 ret_wm->enable = true;
2681}
2682
2683/*
2684 * Merge all low power watermarks for all active pipes.
2685 */
2686static void ilk_wm_merge(struct drm_device *dev,
2687 const struct hsw_wm_maximums *max,
2688 struct intel_pipe_wm *merged)
2689{
2690 int level, max_level = ilk_wm_max_level(dev);
2691
2692 merged->fbc_wm_enabled = true;
2693
2694 /* merge each WM1+ level */
2695 for (level = 1; level <= max_level; level++) {
2696 struct intel_wm_level *wm = &merged->wm[level];
2697
2698 ilk_merge_wm_level(dev, level, wm);
2699
d9395655 2700 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2701 break;
2702
2703 /*
2704 * The spec says it is preferred to disable
2705 * FBC WMs instead of disabling a WM level.
2706 */
2707 if (wm->fbc_val > max->fbc) {
2708 merged->fbc_wm_enabled = false;
2709 wm->fbc_val = 0;
2710 }
2711 }
2712}
2713
b380ca3c
VS		 2714static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2715{
2716 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2717 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2718}
2719
801bcfff 2720static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2721 const struct intel_pipe_wm *merged,
609cedef 2722 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2723 struct hsw_wm_values *results)
2724{
0b2ae6d7
VS		 2725 struct intel_crtc *intel_crtc;
2726 int level, wm_lp;
cca32e9a 2727
0362c781 2728 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2729 results->partitioning = partitioning;
cca32e9a 2730
0b2ae6d7 2731 /* LP1+ register values */
cca32e9a 2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2733 const struct intel_wm_level *r;
801bcfff 2734
b380ca3c 2735 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2736
0362c781 2737 r = &merged->wm[level];
0b2ae6d7 2738 if (!r->enable)
cca32e9a
PZ		 2739 break;
2740
416f4727
VS		 2741 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
2742 ((level * 2) << WM1_LP_LATENCY_SHIFT) |
2743 (r->pri_val << WM1_LP_SR_SHIFT) |
2744 r->cur_val;
2745
2746 if (INTEL_INFO(dev)->gen >= 8)
2747 results->wm_lp[wm_lp - 1] |=
2748 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2749 else
2750 results->wm_lp[wm_lp - 1] |=
2751 r->fbc_val << WM1_LP_FBC_SHIFT;
2752
cca32e9a
PZ		 2753 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2754 }
801bcfff 2755
0b2ae6d7
VS		 2756 /* LP0 register values */
2757 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2758 enum pipe pipe = intel_crtc->pipe;
2759 const struct intel_wm_level *r =
2760 &intel_crtc->wm.active.wm[0];
2761
2762 if (WARN_ON(!r->enable))
2763 continue;
2764
2765 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2766
0b2ae6d7
VS		 2767 results->wm_pipe[pipe] =
2768 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2769 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2770 r->cur_val;
801bcfff
PZ		 2771 }
2772}
2773
861f3389
PZ		 2774/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2775 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2776static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2777 struct intel_pipe_wm *r1,
2778 struct intel_pipe_wm *r2)
861f3389 2779{
198a1e9b
VS		 2780 int level, max_level = ilk_wm_max_level(dev);
2781 int level1 = 0, level2 = 0;
861f3389 2782
198a1e9b
VS		 2783 for (level = 1; level <= max_level; level++) {
2784 if (r1->wm[level].enable)
2785 level1 = level;
2786 if (r2->wm[level].enable)
2787 level2 = level;
861f3389
PZ		 2788 }
2789
198a1e9b
VS		 2790 if (level1 == level2) {
2791 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2792 return r2;
2793 else
2794 return r1;
198a1e9b 2795 } else if (level1 > level2) {
861f3389
PZ		 2796 return r1;
2797 } else {
2798 return r2;
2799 }
2800}
2801
49a687c4
VS		 2802/* dirty bits used to track which watermarks need changes */
2803#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2804#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2805#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2806#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2807#define WM_DIRTY_FBC (1 << 24)
2808#define WM_DIRTY_DDB (1 << 25)
2809
2810static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2811 const struct hsw_wm_values *old,
2812 const struct hsw_wm_values *new)
2813{
2814 unsigned int dirty = 0;
2815 enum pipe pipe;
2816 int wm_lp;
2817
2818 for_each_pipe(pipe) {
2819 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2820 dirty |= WM_DIRTY_LINETIME(pipe);
2821 /* Must disable LP1+ watermarks too */
2822 dirty |= WM_DIRTY_LP_ALL;
2823 }
2824
2825 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2826 dirty |= WM_DIRTY_PIPE(pipe);
2827 /* Must disable LP1+ watermarks too */
2828 dirty |= WM_DIRTY_LP_ALL;
2829 }
2830 }
2831
2832 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2833 dirty |= WM_DIRTY_FBC;
2834 /* Must disable LP1+ watermarks too */
2835 dirty |= WM_DIRTY_LP_ALL;
2836 }
2837
2838 if (old->partitioning != new->partitioning) {
2839 dirty |= WM_DIRTY_DDB;
2840 /* Must disable LP1+ watermarks too */
2841 dirty |= WM_DIRTY_LP_ALL;
2842 }
2843
2844 /* LP1+ watermarks already deemed dirty, no need to continue */
2845 if (dirty & WM_DIRTY_LP_ALL)
2846 return dirty;
2847
2848 /* Find the lowest numbered LP1+ watermark in need of an update... */
2849 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2850 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2851 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2852 break;
2853 }
2854
2855 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2856 for (; wm_lp <= 3; wm_lp++)
2857 dirty |= WM_DIRTY_LP(wm_lp);
2858
2859 return dirty;
2860}
2861
801bcfff
PZ		 2862/*
2863 * The spec says we shouldn't write when we don't need, because every write
2864 * causes WMs to be re-evaluated, expending some power.
2865 */
2866static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
609cedef 2867 struct hsw_wm_values *results)
801bcfff 2868{
243e6a44 2869 struct hsw_wm_values *previous = &dev_priv->wm.hw;
49a687c4 2870 unsigned int dirty;
801bcfff 2871 uint32_t val;
801bcfff 2872
243e6a44 2873 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
49a687c4 2874 if (!dirty)
801bcfff
PZ		 2875 return;
2876
243e6a44 2877 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
801bcfff 2878 I915_WRITE(WM3_LP_ILK, 0);
243e6a44 2879 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
801bcfff 2880 I915_WRITE(WM2_LP_ILK, 0);
243e6a44 2881 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
801bcfff
PZ		 2882 I915_WRITE(WM1_LP_ILK, 0);
2883
49a687c4 2884 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2885 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2886 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2887 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2888 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2889 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2890
49a687c4 2891 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2892 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2893 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2894 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2895 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2896 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2897
49a687c4 2898 if (dirty & WM_DIRTY_DDB) {
801bcfff 2899 val = I915_READ(WM_MISC);
609cedef 2900 if (results->partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2901 val &= ~WM_MISC_DATA_PARTITION_5_6;
2902 else
2903 val |= WM_MISC_DATA_PARTITION_5_6;
2904 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2905 }
2906
49a687c4 2907 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2908 val = I915_READ(DISP_ARB_CTL);
2909 if (results->enable_fbc_wm)
2910 val &= ~DISP_FBC_WM_DIS;
2911 else
2912 val |= DISP_FBC_WM_DIS;
2913 I915_WRITE(DISP_ARB_CTL, val);
2914 }
2915
243e6a44 2916 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
801bcfff 2917 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
243e6a44 2918 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
801bcfff 2919 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
243e6a44 2920 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
801bcfff
PZ		 2921 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2922
49a687c4 2923 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
801bcfff 2924 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
49a687c4 2925 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
801bcfff 2926 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
49a687c4 2927 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
801bcfff 2928 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2929
2930 dev_priv->wm.hw = *results;
801bcfff
PZ		 2931}
2932
46ba614c 2933static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2934{
7c4a395f 2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2936 struct drm_device *dev = crtc->dev;
801bcfff 2937 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2938 struct hsw_wm_maximums max;
7c4a395f 2939 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2940 struct hsw_wm_values results = {};
77c122bc 2941 enum intel_ddb_partitioning partitioning;
7c4a395f 2942 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2943 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2944 struct intel_wm_config config = {};
7c4a395f 2945
a485bfb8 2946 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2947
2948 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2949
2950 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2951 return;
861f3389 2952
7c4a395f 2953 intel_crtc->wm.active = pipe_wm;
861f3389 2954
34982fe1 2955 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
a485bfb8
VS		 2956 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2957
2958 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2959 if (INTEL_INFO(dev)->gen >= 7 &&
2960 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2961 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
a485bfb8 2962 ilk_wm_merge(dev, &max, &lp_wm_5_6);
0362c781 2963
198a1e9b 2964 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2965 } else {
198a1e9b 2966 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2967 }
2968
198a1e9b 2969 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2970 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2971
609cedef
VS		 2972 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2973
2974 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2975}
2976
adf3d35e
VS		 2977static void haswell_update_sprite_wm(struct drm_plane *plane,
2978 struct drm_crtc *crtc,
526682e9 2979 uint32_t sprite_width, int pixel_size,
bdd57d03 2980 bool enabled, bool scaled)
526682e9 2981{
adf3d35e 2982 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2983
adf3d35e
VS		 2984 intel_plane->wm.enabled = enabled;
2985 intel_plane->wm.scaled = scaled;
2986 intel_plane->wm.horiz_pixels = sprite_width;
2987 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2988
46ba614c 2989 haswell_update_wm(crtc);
526682e9
PZ		 2990}
2991
b445e3b0
ED		 2992static bool
2993sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2994 uint32_t sprite_width, int pixel_size,
2995 const struct intel_watermark_params *display,
2996 int display_latency_ns, int *sprite_wm)
2997{
2998 struct drm_crtc *crtc;
2999 int clock;
3000 int entries, tlb_miss;
3001
3002 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 3003 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 3004 *sprite_wm = display->guard_size;
3005 return false;
3006 }
3007
241bfc38 3008 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3009
3010 /* Use the small buffer method to calculate the sprite watermark */
3011 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3012 tlb_miss = display->fifo_size*display->cacheline_size -
3013 sprite_width * 8;
3014 if (tlb_miss > 0)
3015 entries += tlb_miss;
3016 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3017 *sprite_wm = entries + display->guard_size;
3018 if (*sprite_wm > (int)display->max_wm)
3019 *sprite_wm = display->max_wm;
3020
3021 return true;
3022}
3023
3024static bool
3025sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3026 uint32_t sprite_width, int pixel_size,
3027 const struct intel_watermark_params *display,
3028 int latency_ns, int *sprite_wm)
3029{
3030 struct drm_crtc *crtc;
3031 unsigned long line_time_us;
3032 int clock;
3033 int line_count, line_size;
3034 int small, large;
3035 int entries;
3036
3037 if (!latency_ns) {
3038 *sprite_wm = 0;
3039 return false;
3040 }
3041
3042 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 3043 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3044 if (!clock) {
3045 *sprite_wm = 0;
3046 return false;
3047 }
3048
3049 line_time_us = (sprite_width * 1000) / clock;
3050 if (!line_time_us) {
3051 *sprite_wm = 0;
3052 return false;
3053 }
3054
3055 line_count = (latency_ns / line_time_us + 1000) / 1000;
3056 line_size = sprite_width * pixel_size;
3057
3058 /* Use the minimum of the small and large buffer method for primary */
3059 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3060 large = line_count * line_size;
3061
3062 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3063 *sprite_wm = entries + display->guard_size;
3064
3065 return *sprite_wm > 0x3ff ? false : true;
3066}
3067
adf3d35e
VS		 3068static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3069 struct drm_crtc *crtc,
4c4ff43a 3070 uint32_t sprite_width, int pixel_size,
39db4a4d 3071 bool enabled, bool scaled)
b445e3b0 3072{
adf3d35e 3073 struct drm_device *dev = plane->dev;
b445e3b0 3074 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 3075 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 3076 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 3077 u32 val;
3078 int sprite_wm, reg;
3079 int ret;
3080
39db4a4d 3081 if (!enabled)
4c4ff43a
PZ		 3082 return;
3083
b445e3b0
ED		 3084 switch (pipe) {
3085 case 0:
3086 reg = WM0_PIPEA_ILK;
3087 break;
3088 case 1:
3089 reg = WM0_PIPEB_ILK;
3090 break;
3091 case 2:
3092 reg = WM0_PIPEC_IVB;
3093 break;
3094 default:
3095 return; /* bad pipe */
3096 }
3097
3098 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3099 &sandybridge_display_wm_info,
3100 latency, &sprite_wm);
3101 if (!ret) {
84f44ce7
VS		 3102 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3103 pipe_name(pipe));
b445e3b0
ED		 3104 return;
3105 }
3106
3107 val = I915_READ(reg);
3108 val &= ~WM0_PIPE_SPRITE_MASK;
3109 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3110 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3111
3112
3113 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3114 pixel_size,
3115 &sandybridge_display_srwm_info,
b0aea5dc 3116 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3117 &sprite_wm);
3118 if (!ret) {
84f44ce7
VS		 3119 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3120 pipe_name(pipe));
b445e3b0
ED		 3121 return;
3122 }
3123 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3124
3125 /* Only IVB has two more LP watermarks for sprite */
3126 if (!IS_IVYBRIDGE(dev))
3127 return;
3128
3129 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3130 pixel_size,
3131 &sandybridge_display_srwm_info,
b0aea5dc 3132 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3133 &sprite_wm);
3134 if (!ret) {
84f44ce7
VS		 3135 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3136 pipe_name(pipe));
b445e3b0
ED		 3137 return;
3138 }
3139 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3140
3141 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3142 pixel_size,
3143 &sandybridge_display_srwm_info,
b0aea5dc 3144 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3145 &sprite_wm);
3146 if (!ret) {
84f44ce7
VS		 3147 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3148 pipe_name(pipe));
b445e3b0
ED		 3149 return;
3150 }
3151 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3152}
3153
243e6a44
VS		 3154static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3155{
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3160 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3161 enum pipe pipe = intel_crtc->pipe;
3162 static const unsigned int wm0_pipe_reg[] = {
3163 [PIPE_A] = WM0_PIPEA_ILK,
3164 [PIPE_B] = WM0_PIPEB_ILK,
3165 [PIPE_C] = WM0_PIPEC_IVB,
3166 };
3167
3168 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3169 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3170
3171 if (intel_crtc_active(crtc)) {
3172 u32 tmp = hw->wm_pipe[pipe];
3173
3174 /*
3175 * For active pipes LP0 watermark is marked as
3176 * enabled, and LP1+ watermaks as disabled since
3177 * we can't really reverse compute them in case
3178 * multiple pipes are active.
3179 */
3180 active->wm[0].enable = true;
3181 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3182 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3183 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3184 active->linetime = hw->wm_linetime[pipe];
3185 } else {
3186 int level, max_level = ilk_wm_max_level(dev);
3187
3188 /*
3189 * For inactive pipes, all watermark levels
3190 * should be marked as enabled but zeroed,
3191 * which is what we'd compute them to.
3192 */
3193 for (level = 0; level <= max_level; level++)
3194 active->wm[level].enable = true;
3195 }
3196}
3197
3198void ilk_wm_get_hw_state(struct drm_device *dev)
3199{
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3202 struct drm_crtc *crtc;
3203
3204 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3205 ilk_pipe_wm_get_hw_state(crtc);
3206
3207 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3208 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3209 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3210
3211 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3212 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3213 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3214
3215 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3216 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3217
3218 hw->enable_fbc_wm =
3219 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3220}
3221
b445e3b0
ED		 3222/**
3223 * intel_update_watermarks - update FIFO watermark values based on current modes
3224 *
3225 * Calculate watermark values for the various WM regs based on current mode
3226 * and plane configuration.
3227 *
3228 * There are several cases to deal with here:
3229 * - normal (i.e. non-self-refresh)
3230 * - self-refresh (SR) mode
3231 * - lines are large relative to FIFO size (buffer can hold up to 2)
3232 * - lines are small relative to FIFO size (buffer can hold more than 2
3233 * lines), so need to account for TLB latency
3234 *
3235 * The normal calculation is:
3236 * watermark = dotclock * bytes per pixel * latency
3237 * where latency is platform & configuration dependent (we assume pessimal
3238 * values here).
3239 *
3240 * The SR calculation is:
3241 * watermark = (trunc(latency/line time)+1) * surface width *
3242 * bytes per pixel
3243 * where
3244 * line time = htotal / dotclock
3245 * surface width = hdisplay for normal plane and 64 for cursor
3246 * and latency is assumed to be high, as above.
3247 *
3248 * The final value programmed to the register should always be rounded up,
3249 * and include an extra 2 entries to account for clock crossings.
3250 *
3251 * We don't use the sprite, so we can ignore that. And on Crestline we have
3252 * to set the non-SR watermarks to 8.
3253 */
46ba614c 3254void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3255{
46ba614c 3256 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3257
3258 if (dev_priv->display.update_wm)
46ba614c 3259 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3260}
3261
adf3d35e
VS		 3262void intel_update_sprite_watermarks(struct drm_plane *plane,
3263 struct drm_crtc *crtc,
4c4ff43a 3264 uint32_t sprite_width, int pixel_size,
39db4a4d 3265 bool enabled, bool scaled)
b445e3b0 3266{
adf3d35e 3267 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3268
3269 if (dev_priv->display.update_sprite_wm)
adf3d35e 3270 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3271 pixel_size, enabled, scaled);
b445e3b0
ED		 3272}
3273
2b4e57bd
ED		 3274static struct drm_i915_gem_object *
3275intel_alloc_context_page(struct drm_device *dev)
3276{
3277 struct drm_i915_gem_object *ctx;
3278 int ret;
3279
3280 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3281
3282 ctx = i915_gem_alloc_object(dev, 4096);
3283 if (!ctx) {
3284 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3285 return NULL;
3286 }
3287
c37e2204 3288 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3289 if (ret) {
3290 DRM_ERROR("failed to pin power context: %d\n", ret);
3291 goto err_unref;
3292 }
3293
3294 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3295 if (ret) {
3296 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3297 goto err_unpin;
3298 }
3299
3300 return ctx;
3301
3302err_unpin:
3303 i915_gem_object_unpin(ctx);
3304err_unref:
3305 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3306 return NULL;
3307}
3308
9270388e
DV		 3309/**
3310 * Lock protecting IPS related data structures
9270388e
DV		 3311 */
3312DEFINE_SPINLOCK(mchdev_lock);
3313
3314/* Global for IPS driver to get at the current i915 device. Protected by
3315 * mchdev_lock. */
3316static struct drm_i915_private *i915_mch_dev;
3317
2b4e57bd
ED		 3318bool ironlake_set_drps(struct drm_device *dev, u8 val)
3319{
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 u16 rgvswctl;
3322
9270388e
DV		 3323 assert_spin_locked(&mchdev_lock);
3324
2b4e57bd
ED		 3325 rgvswctl = I915_READ16(MEMSWCTL);
3326 if (rgvswctl & MEMCTL_CMD_STS) {
3327 DRM_DEBUG("gpu busy, RCS change rejected\n");
3328 return false; /* still busy with another command */
3329 }
3330
3331 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3332 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3333 I915_WRITE16(MEMSWCTL, rgvswctl);
3334 POSTING_READ16(MEMSWCTL);
3335
3336 rgvswctl |= MEMCTL_CMD_STS;
3337 I915_WRITE16(MEMSWCTL, rgvswctl);
3338
3339 return true;
3340}
3341
8090c6b9 3342static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3343{
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 u32 rgvmodectl = I915_READ(MEMMODECTL);
3346 u8 fmax, fmin, fstart, vstart;
3347
9270388e
DV		 3348 spin_lock_irq(&mchdev_lock);
3349
2b4e57bd
ED		 3350 /* Enable temp reporting */
3351 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3352 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3353
3354 /* 100ms RC evaluation intervals */
3355 I915_WRITE(RCUPEI, 100000);
3356 I915_WRITE(RCDNEI, 100000);
3357
3358 /* Set max/min thresholds to 90ms and 80ms respectively */
3359 I915_WRITE(RCBMAXAVG, 90000);
3360 I915_WRITE(RCBMINAVG, 80000);
3361
3362 I915_WRITE(MEMIHYST, 1);
3363
3364 /* Set up min, max, and cur for interrupt handling */
3365 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3366 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3367 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3368 MEMMODE_FSTART_SHIFT;
3369
3370 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3371 PXVFREQ_PX_SHIFT;
3372
20e4d407
DV		 3373 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3374 dev_priv->ips.fstart = fstart;
2b4e57bd 3375
20e4d407
DV		 3376 dev_priv->ips.max_delay = fstart;
3377 dev_priv->ips.min_delay = fmin;
3378 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3379
3380 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3381 fmax, fmin, fstart);
3382
3383 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3384
3385 /*
3386 * Interrupts will be enabled in ironlake_irq_postinstall
3387 */
3388
3389 I915_WRITE(VIDSTART, vstart);
3390 POSTING_READ(VIDSTART);
3391
3392 rgvmodectl |= MEMMODE_SWMODE_EN;
3393 I915_WRITE(MEMMODECTL, rgvmodectl);
3394
9270388e 3395 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3396 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3397 mdelay(1);
2b4e57bd
ED		 3398
3399 ironlake_set_drps(dev, fstart);
3400
20e4d407 3401 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3402 I915_READ(0x112e0);
20e4d407
DV		 3403 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3404 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3405 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3406
3407 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3408}
3409
8090c6b9 3410static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3411{
3412 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3413 u16 rgvswctl;
3414
3415 spin_lock_irq(&mchdev_lock);
3416
3417 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3418
3419 /* Ack interrupts, disable EFC interrupt */
3420 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3421 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3422 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3423 I915_WRITE(DEIIR, DE_PCU_EVENT);
3424 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3425
3426 /* Go back to the starting frequency */
20e4d407 3427 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3428 mdelay(1);
2b4e57bd
ED		 3429 rgvswctl |= MEMCTL_CMD_STS;
3430 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3431 mdelay(1);
2b4e57bd 3432
9270388e 3433 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3434}
3435
acbe9475
DV		 3436/* There's a funny hw issue where the hw returns all 0 when reading from
3437 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3438 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3439 * all limits and the gpu stuck at whatever frequency it is at atm).
3440 */
6917c7b9 3441static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3442{
7b9e0ae6 3443 u32 limits;
2b4e57bd 3444
20b46e59
DV		 3445 /* Only set the down limit when we've reached the lowest level to avoid
3446 * getting more interrupts, otherwise leave this clear. This prevents a
3447 * race in the hw when coming out of rc6: There's a tiny window where
3448 * the hw runs at the minimal clock before selecting the desired
3449 * frequency, if the down threshold expires in that window we will not
3450 * receive a down interrupt. */
6917c7b9
CW		 3451 limits = dev_priv->rps.max_delay << 24;
3452 if (val <= dev_priv->rps.min_delay)
c6a828d3 3453 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3454
3455 return limits;
3456}
3457
dd75fdc8
CW		 3458static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3459{
3460 int new_power;
3461
3462 new_power = dev_priv->rps.power;
3463 switch (dev_priv->rps.power) {
3464 case LOW_POWER:
3465 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3466 new_power = BETWEEN;
3467 break;
3468
3469 case BETWEEN:
3470 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3471 new_power = LOW_POWER;
3472 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3473 new_power = HIGH_POWER;
3474 break;
3475
3476 case HIGH_POWER:
3477 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3478 new_power = BETWEEN;
3479 break;
3480 }
3481 /* Max/min bins are special */
3482 if (val == dev_priv->rps.min_delay)
3483 new_power = LOW_POWER;
3484 if (val == dev_priv->rps.max_delay)
3485 new_power = HIGH_POWER;
3486 if (new_power == dev_priv->rps.power)
3487 return;
3488
3489 /* Note the units here are not exactly 1us, but 1280ns. */
3490 switch (new_power) {
3491 case LOW_POWER:
3492 /* Upclock if more than 95% busy over 16ms */
3493 I915_WRITE(GEN6_RP_UP_EI, 12500);
3494 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3495
3496 /* Downclock if less than 85% busy over 32ms */
3497 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3498 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3499
3500 I915_WRITE(GEN6_RP_CONTROL,
3501 GEN6_RP_MEDIA_TURBO |
3502 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3503 GEN6_RP_MEDIA_IS_GFX |
3504 GEN6_RP_ENABLE |
3505 GEN6_RP_UP_BUSY_AVG |
3506 GEN6_RP_DOWN_IDLE_AVG);
3507 break;
3508
3509 case BETWEEN:
3510 /* Upclock if more than 90% busy over 13ms */
3511 I915_WRITE(GEN6_RP_UP_EI, 10250);
3512 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3513
3514 /* Downclock if less than 75% busy over 32ms */
3515 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3516 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3517
3518 I915_WRITE(GEN6_RP_CONTROL,
3519 GEN6_RP_MEDIA_TURBO |
3520 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3521 GEN6_RP_MEDIA_IS_GFX |
3522 GEN6_RP_ENABLE |
3523 GEN6_RP_UP_BUSY_AVG |
3524 GEN6_RP_DOWN_IDLE_AVG);
3525 break;
3526
3527 case HIGH_POWER:
3528 /* Upclock if more than 85% busy over 10ms */
3529 I915_WRITE(GEN6_RP_UP_EI, 8000);
3530 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3531
3532 /* Downclock if less than 60% busy over 32ms */
3533 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3534 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3535
3536 I915_WRITE(GEN6_RP_CONTROL,
3537 GEN6_RP_MEDIA_TURBO |
3538 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3539 GEN6_RP_MEDIA_IS_GFX |
3540 GEN6_RP_ENABLE |
3541 GEN6_RP_UP_BUSY_AVG |
3542 GEN6_RP_DOWN_IDLE_AVG);
3543 break;
3544 }
3545
3546 dev_priv->rps.power = new_power;
3547 dev_priv->rps.last_adj = 0;
3548}
3549
20b46e59
DV		 3550void gen6_set_rps(struct drm_device *dev, u8 val)
3551{
3552 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3553
4fc688ce 3554 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3555 WARN_ON(val > dev_priv->rps.max_delay);
3556 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3557
c6a828d3 3558 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3559 return;
3560
dd75fdc8
CW		 3561 gen6_set_rps_thresholds(dev_priv, val);
3562
92bd1bf0
RV		 3563 if (IS_HASWELL(dev))
3564 I915_WRITE(GEN6_RPNSWREQ,
3565 HSW_FREQUENCY(val));
3566 else
3567 I915_WRITE(GEN6_RPNSWREQ,
3568 GEN6_FREQUENCY(val) |
3569 GEN6_OFFSET(0) |
3570 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3571
3572 /* Make sure we continue to get interrupts
3573 * until we hit the minimum or maximum frequencies.
3574 */
6917c7b9
CW		 3575 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3576 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3577
d5570a72
BW		 3578 POSTING_READ(GEN6_RPNSWREQ);
3579
c6a828d3 3580 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3581
3582 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3583}
3584
b29c19b6
CW		 3585void gen6_rps_idle(struct drm_i915_private *dev_priv)
3586{
3587 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3588 if (dev_priv->rps.enabled) {
3589 if (dev_priv->info->is_valleyview)
3590 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3591 else
3592 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3593 dev_priv->rps.last_adj = 0;
3594 }
b29c19b6
CW		 3595 mutex_unlock(&dev_priv->rps.hw_lock);
3596}
3597
3598void gen6_rps_boost(struct drm_i915_private *dev_priv)
3599{
3600 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3601 if (dev_priv->rps.enabled) {
3602 if (dev_priv->info->is_valleyview)
3603 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3604 else
3605 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3606 dev_priv->rps.last_adj = 0;
3607 }
b29c19b6
CW		 3608 mutex_unlock(&dev_priv->rps.hw_lock);
3609}
3610
0a073b84
JB		 3611void valleyview_set_rps(struct drm_device *dev, u8 val)
3612{
3613 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3614
0a073b84
JB		 3615 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3616 WARN_ON(val > dev_priv->rps.max_delay);
3617 WARN_ON(val < dev_priv->rps.min_delay);
3618
73008b98 3619 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3620 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3621 dev_priv->rps.cur_delay,
2ec3815f 3622 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3623
3624 if (val == dev_priv->rps.cur_delay)
3625 return;
3626
ae99258f 3627 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3628
80814ae4 3629 dev_priv->rps.cur_delay = val;
0a073b84 3630
2ec3815f 3631 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3632}
3633
44fc7d5c 3634static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3635{
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637
2b4e57bd 3638 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3639 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3640 /* Complete PM interrupt masking here doesn't race with the rps work
3641 * item again unmasking PM interrupts because that is using a different
3642 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3643 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3644
59cdb63d 3645 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3646 dev_priv->rps.pm_iir = 0;
59cdb63d 3647 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3648
4848405c 3649 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3650}
3651
44fc7d5c 3652static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3653{
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655
3656 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3657 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3658
44fc7d5c
DV		 3659 gen6_disable_rps_interrupts(dev);
3660}
3661
3662static void valleyview_disable_rps(struct drm_device *dev)
3663{
3664 struct drm_i915_private *dev_priv = dev->dev_private;
3665
3666 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3667
44fc7d5c 3668 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3669
3670 if (dev_priv->vlv_pctx) {
3671 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3672 dev_priv->vlv_pctx = NULL;
3673 }
d20d4f0c
JB		 3674}
3675
dc39fff7
BW		 3676static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3677{
3678 if (IS_GEN6(dev))
3679 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3680
3681 if (IS_HASWELL(dev))
3682 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3683
3684 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3685 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3686 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3687 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3688}
3689
2b4e57bd
ED		 3690int intel_enable_rc6(const struct drm_device *dev)
3691{
eb4926e4
DL		 3692 /* No RC6 before Ironlake */
3693 if (INTEL_INFO(dev)->gen < 5)
3694 return 0;
3695
456470eb 3696 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3697 if (i915_enable_rc6 >= 0)
3698 return i915_enable_rc6;
3699
6567d748
CW		 3700 /* Disable RC6 on Ironlake */
3701 if (INTEL_INFO(dev)->gen == 5)
3702 return 0;
2b4e57bd 3703
dc39fff7 3704 if (IS_HASWELL(dev))
4a637c2c 3705 return INTEL_RC6_ENABLE;
2b4e57bd 3706
456470eb 3707 /* snb/ivb have more than one rc6 state. */
dc39fff7 3708 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3709 return INTEL_RC6_ENABLE;
456470eb 3710
2b4e57bd
ED		 3711 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3712}
3713
44fc7d5c
DV		 3714static void gen6_enable_rps_interrupts(struct drm_device *dev)
3715{
3716 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3717 u32 enabled_intrs;
44fc7d5c
DV		 3718
3719 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3720 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3721 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3722 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3723 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3724
fd547d25 3725 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3726 enabled_intrs = GEN6_PM_RPS_EVENTS;
3727
3728 /* IVB and SNB hard hangs on looping batchbuffer
3729 * if GEN6_PM_UP_EI_EXPIRED is masked.
3730 */
3731 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3732 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3733
3734 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3735}
3736
6edee7f3
BW		 3737static void gen8_enable_rps(struct drm_device *dev)
3738{
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_ring_buffer *ring;
3741 uint32_t rc6_mask = 0, rp_state_cap;
3742 int unused;
3743
3744 /* 1a: Software RC state - RC0 */
3745 I915_WRITE(GEN6_RC_STATE, 0);
3746
3747 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3748 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3749 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3750
3751 /* 2a: Disable RC states. */
3752 I915_WRITE(GEN6_RC_CONTROL, 0);
3753
3754 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3755
3756 /* 2b: Program RC6 thresholds.*/
3757 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3758 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3759 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3760 for_each_ring(ring, dev_priv, unused)
3761 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3762 I915_WRITE(GEN6_RC_SLEEP, 0);
3763 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3764
3765 /* 3: Enable RC6 */
3766 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3767 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3768 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3769 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3770 GEN6_RC_CTL_EI_MODE(1) |
3771 rc6_mask);
3772
3773 /* 4 Program defaults and thresholds for RPS*/
3774 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3775 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3776 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3777 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3778
3779 /* Docs recommend 900MHz, and 300 MHz respectively */
3780 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3781 dev_priv->rps.max_delay << 24 |
3782 dev_priv->rps.min_delay << 16);
3783
3784 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3785 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3786 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3787 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3788
3789 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3790
3791 /* 5: Enable RPS */
3792 I915_WRITE(GEN6_RP_CONTROL,
3793 GEN6_RP_MEDIA_TURBO |
3794 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3795 GEN6_RP_MEDIA_IS_GFX |
3796 GEN6_RP_ENABLE |
3797 GEN6_RP_UP_BUSY_AVG |
3798 GEN6_RP_DOWN_IDLE_AVG);
3799
3800 /* 6: Ring frequency + overclocking (our driver does this later */
3801
3802 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3803
3804 gen6_enable_rps_interrupts(dev);
3805
c8d9a590 3806 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3807}
3808
79f5b2c7 3809static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3810{
79f5b2c7 3811 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3812 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3813 u32 rp_state_cap;
3814 u32 gt_perf_status;
31643d54 3815 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3816 u32 gtfifodbg;
2b4e57bd 3817 int rc6_mode;
42c0526c 3818 int i, ret;
2b4e57bd 3819
4fc688ce 3820 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3821
2b4e57bd
ED		 3822 /* Here begins a magic sequence of register writes to enable
3823 * auto-downclocking.
3824 *
3825 * Perhaps there might be some value in exposing these to
3826 * userspace...
3827 */
3828 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3829
3830 /* Clear the DBG now so we don't confuse earlier errors */
3831 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3832 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3833 I915_WRITE(GTFIFODBG, gtfifodbg);
3834 }
3835
c8d9a590 3836 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3837
7b9e0ae6
CW		 3838 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3839 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3840
31c77388
BW		 3841 /* In units of 50MHz */
3842 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3843 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3844 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3845 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3846 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3847 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3848
2b4e57bd
ED		 3849 /* disable the counters and set deterministic thresholds */
3850 I915_WRITE(GEN6_RC_CONTROL, 0);
3851
3852 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3853 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3854 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3855 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3856 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3857
b4519513
CW		 3858 for_each_ring(ring, dev_priv, i)
3859 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3860
3861 I915_WRITE(GEN6_RC_SLEEP, 0);
3862 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3863 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3864 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3865 else
3866 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3867 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3868 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3869
5a7dc92a 3870 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3871 rc6_mode = intel_enable_rc6(dev_priv->dev);
3872 if (rc6_mode & INTEL_RC6_ENABLE)
3873 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3874
5a7dc92a
ED		 3875 /* We don't use those on Haswell */
3876 if (!IS_HASWELL(dev)) {
3877 if (rc6_mode & INTEL_RC6p_ENABLE)
3878 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3879
5a7dc92a
ED		 3880 if (rc6_mode & INTEL_RC6pp_ENABLE)
3881 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3882 }
2b4e57bd 3883
dc39fff7 3884 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3885
3886 I915_WRITE(GEN6_RC_CONTROL,
3887 rc6_mask |
3888 GEN6_RC_CTL_EI_MODE(1) |
3889 GEN6_RC_CTL_HW_ENABLE);
3890
dd75fdc8
CW		 3891 /* Power down if completely idle for over 50ms */
3892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3893 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3894
42c0526c 3895 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3896 if (!ret) {
42c0526c
BW		 3897 pcu_mbox = 0;
3898 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3899 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3900 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3901 (dev_priv->rps.max_delay & 0xff) * 50,
3902 (pcu_mbox & 0xff) * 50);
31c77388 3903 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3904 }
3905 } else {
3906 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3907 }
3908
dd75fdc8
CW		 3909 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3910 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3911
44fc7d5c 3912 gen6_enable_rps_interrupts(dev);
2b4e57bd 3913
31643d54
BW		 3914 rc6vids = 0;
3915 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3916 if (IS_GEN6(dev) && ret) {
3917 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3918 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3919 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3920 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3921 rc6vids &= 0xffff00;
3922 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3923 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3924 if (ret)
3925 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3926 }
3927
c8d9a590 3928 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3929}
3930
c67a470b 3931void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3932{
79f5b2c7 3933 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3934 int min_freq = 15;
3ebecd07
CW		 3935 unsigned int gpu_freq;
3936 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3937 int scaling_factor = 180;
eda79642 3938 struct cpufreq_policy *policy;
2b4e57bd 3939
4fc688ce 3940 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3941
eda79642
BW		 3942 policy = cpufreq_cpu_get(0);
3943 if (policy) {
3944 max_ia_freq = policy->cpuinfo.max_freq;
3945 cpufreq_cpu_put(policy);
3946 } else {
3947 /*
3948 * Default to measured freq if none found, PCU will ensure we
3949 * don't go over
3950 */
2b4e57bd 3951 max_ia_freq = tsc_khz;
eda79642 3952 }
2b4e57bd
ED		 3953
3954 /* Convert from kHz to MHz */
3955 max_ia_freq /= 1000;
3956
153b4b95 3957 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3958 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3959 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3960
2b4e57bd
ED		 3961 /*
3962 * For each potential GPU frequency, load a ring frequency we'd like
3963 * to use for memory access. We do this by specifying the IA frequency
3964 * the PCU should use as a reference to determine the ring frequency.
3965 */
c6a828d3 3966 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3967 gpu_freq--) {
c6a828d3 3968 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3969 unsigned int ia_freq = 0, ring_freq = 0;
3970
46c764d4
BW		 3971 if (INTEL_INFO(dev)->gen >= 8) {
3972 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3973 ring_freq = max(min_ring_freq, gpu_freq);
3974 } else if (IS_HASWELL(dev)) {
f6aca45c 3975 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3976 ring_freq = max(min_ring_freq, ring_freq);
3977 /* leave ia_freq as the default, chosen by cpufreq */
3978 } else {
3979 /* On older processors, there is no separate ring
3980 * clock domain, so in order to boost the bandwidth
3981 * of the ring, we need to upclock the CPU (ia_freq).
3982 *
3983 * For GPU frequencies less than 750MHz,
3984 * just use the lowest ring freq.
3985 */
3986 if (gpu_freq < min_freq)
3987 ia_freq = 800;
3988 else
3989 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3990 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3991 }
2b4e57bd 3992
42c0526c
BW		 3993 sandybridge_pcode_write(dev_priv,
3994 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3995 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3996 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3997 gpu_freq);
2b4e57bd 3998 }
2b4e57bd
ED		 3999}
4000
0a073b84
JB		 4001int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4002{
4003 u32 val, rp0;
4004
64936258 4005 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4006
4007 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4008 /* Clamp to max */
4009 rp0 = min_t(u32, rp0, 0xea);
4010
4011 return rp0;
4012}
4013
4014static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4015{
4016 u32 val, rpe;
4017
64936258 4018 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4019 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4020 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4021 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4022
4023 return rpe;
4024}
4025
4026int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4027{
64936258 4028 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4029}
4030
c9cddffc
JB		 4031static void valleyview_setup_pctx(struct drm_device *dev)
4032{
4033 struct drm_i915_private *dev_priv = dev->dev_private;
4034 struct drm_i915_gem_object *pctx;
4035 unsigned long pctx_paddr;
4036 u32 pcbr;
4037 int pctx_size = 24*1024;
4038
4039 pcbr = I915_READ(VLV_PCBR);
4040 if (pcbr) {
4041 /* BIOS set it up already, grab the pre-alloc'd space */
4042 int pcbr_offset;
4043
4044 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4045 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4046 pcbr_offset,
190d6cd5 4047 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4048 pctx_size);
4049 goto out;
4050 }
4051
4052 /*
4053 * From the Gunit register HAS:
4054 * The Gfx driver is expected to program this register and ensure
4055 * proper allocation within Gfx stolen memory. For example, this
4056 * register should be programmed such than the PCBR range does not
4057 * overlap with other ranges, such as the frame buffer, protected
4058 * memory, or any other relevant ranges.
4059 */
4060 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4061 if (!pctx) {
4062 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4063 return;
4064 }
4065
4066 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4067 I915_WRITE(VLV_PCBR, pctx_paddr);
4068
4069out:
4070 dev_priv->vlv_pctx = pctx;
4071}
4072
0a073b84
JB		 4073static void valleyview_enable_rps(struct drm_device *dev)
4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 struct intel_ring_buffer *ring;
a2b23fe0 4077 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4078 int i;
4079
4080 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4081
4082 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4083 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4084 gtfifodbg);
0a073b84
JB		 4085 I915_WRITE(GTFIFODBG, gtfifodbg);
4086 }
4087
c9cddffc
JB		 4088 valleyview_setup_pctx(dev);
4089
c8d9a590
D		 4090 /* If VLV, Forcewake all wells, else re-direct to regular path */
4091 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4092
4093 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4094 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4095 I915_WRITE(GEN6_RP_UP_EI, 66000);
4096 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4097
4098 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4099
4100 I915_WRITE(GEN6_RP_CONTROL,
4101 GEN6_RP_MEDIA_TURBO |
4102 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4103 GEN6_RP_MEDIA_IS_GFX |
4104 GEN6_RP_ENABLE |
4105 GEN6_RP_UP_BUSY_AVG |
4106 GEN6_RP_DOWN_IDLE_CONT);
4107
4108 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4109 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4110 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4111
4112 for_each_ring(ring, dev_priv, i)
4113 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4114
2f0aa304 4115 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4116
4117 /* allows RC6 residency counter to work */
49798eb2
JB		 4118 I915_WRITE(VLV_COUNTER_CONTROL,
4119 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4120 VLV_MEDIA_RC6_COUNT_EN |
4121 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 4122 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4123 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4124
4125 intel_print_rc6_info(dev, rc6_mode);
4126
a2b23fe0 4127 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4128
64936258 4129 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4130
4131 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4132 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4133
0a073b84 4134 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 4135 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 4136 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 4137 dev_priv->rps.cur_delay);
0a073b84
JB		 4138
4139 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4140 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 4141 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 4142 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 4143 dev_priv->rps.max_delay);
0a073b84 4144
73008b98
VS		 4145 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4146 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 4147 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4148 dev_priv->rps.rpe_delay);
0a073b84 4149
73008b98
VS		 4150 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4151 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 4152 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 4153 dev_priv->rps.min_delay);
0a073b84 4154
73008b98 4155 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 4156 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4157 dev_priv->rps.rpe_delay);
0a073b84 4158
73008b98 4159 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 4160
44fc7d5c 4161 gen6_enable_rps_interrupts(dev);
0a073b84 4162
c8d9a590 4163 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4164}
4165
930ebb46 4166void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4167{
4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169
3e373948
DV		 4170 if (dev_priv->ips.renderctx) {
4171 i915_gem_object_unpin(dev_priv->ips.renderctx);
4172 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4173 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4174 }
4175
3e373948
DV		 4176 if (dev_priv->ips.pwrctx) {
4177 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4178 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4179 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4180 }
4181}
4182
930ebb46 4183static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4184{
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186
4187 if (I915_READ(PWRCTXA)) {
4188 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4189 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4190 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4191 50);
4192
4193 I915_WRITE(PWRCTXA, 0);
4194 POSTING_READ(PWRCTXA);
4195
4196 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4197 POSTING_READ(RSTDBYCTL);
4198 }
2b4e57bd
ED		 4199}
4200
4201static int ironlake_setup_rc6(struct drm_device *dev)
4202{
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204
3e373948
DV		 4205 if (dev_priv->ips.renderctx == NULL)
4206 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4207 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4208 return -ENOMEM;
4209
3e373948
DV		 4210 if (dev_priv->ips.pwrctx == NULL)
4211 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4212 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4213 ironlake_teardown_rc6(dev);
4214 return -ENOMEM;
4215 }
4216
4217 return 0;
4218}
4219
930ebb46 4220static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4221{
4222 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4223 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4224 bool was_interruptible;
2b4e57bd
ED		 4225 int ret;
4226
4227 /* rc6 disabled by default due to repeated reports of hanging during
4228 * boot and resume.
4229 */
4230 if (!intel_enable_rc6(dev))
4231 return;
4232
79f5b2c7
DV		 4233 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4234
2b4e57bd 4235 ret = ironlake_setup_rc6(dev);
79f5b2c7 4236 if (ret)
2b4e57bd 4237 return;
2b4e57bd 4238
3e960501
CW		 4239 was_interruptible = dev_priv->mm.interruptible;
4240 dev_priv->mm.interruptible = false;
4241
2b4e57bd
ED		 4242 /*
4243 * GPU can automatically power down the render unit if given a page
4244 * to save state.
4245 */
6d90c952 4246 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4247 if (ret) {
4248 ironlake_teardown_rc6(dev);
3e960501 4249 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4250 return;
4251 }
4252
6d90c952
DV		 4253 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4254 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4255 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4256 MI_MM_SPACE_GTT |
4257 MI_SAVE_EXT_STATE_EN |
4258 MI_RESTORE_EXT_STATE_EN |
4259 MI_RESTORE_INHIBIT);
4260 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4261 intel_ring_emit(ring, MI_NOOP);
4262 intel_ring_emit(ring, MI_FLUSH);
4263 intel_ring_advance(ring);
2b4e57bd
ED		 4264
4265 /*
4266 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4267 * does an implicit flush, combined with MI_FLUSH above, it should be
4268 * safe to assume that renderctx is valid
4269 */
3e960501
CW		 4270 ret = intel_ring_idle(ring);
4271 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4272 if (ret) {
def27a58 4273 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4274 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4275 return;
4276 }
4277
f343c5f6 4278 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4279 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 4280
4281 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 4282}
4283
dde18883
ED		 4284static unsigned long intel_pxfreq(u32 vidfreq)
4285{
4286 unsigned long freq;
4287 int div = (vidfreq & 0x3f0000) >> 16;
4288 int post = (vidfreq & 0x3000) >> 12;
4289 int pre = (vidfreq & 0x7);
4290
4291 if (!pre)
4292 return 0;
4293
4294 freq = ((div * 133333) / ((1<<post) * pre));
4295
4296 return freq;
4297}
4298
eb48eb00
DV		 4299static const struct cparams {
4300 u16 i;
4301 u16 t;
4302 u16 m;
4303 u16 c;
4304} cparams[] = {
4305 { 1, 1333, 301, 28664 },
4306 { 1, 1066, 294, 24460 },
4307 { 1, 800, 294, 25192 },
4308 { 0, 1333, 276, 27605 },
4309 { 0, 1066, 276, 27605 },
4310 { 0, 800, 231, 23784 },
4311};
4312
f531dcb2 4313static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4314{
4315 u64 total_count, diff, ret;
4316 u32 count1, count2, count3, m = 0, c = 0;
4317 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4318 int i;
4319
02d71956
DV		 4320 assert_spin_locked(&mchdev_lock);
4321
20e4d407 4322 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4323
4324 /* Prevent division-by-zero if we are asking too fast.
4325 * Also, we don't get interesting results if we are polling
4326 * faster than once in 10ms, so just return the saved value
4327 * in such cases.
4328 */
4329 if (diff1 <= 10)
20e4d407 4330 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4331
4332 count1 = I915_READ(DMIEC);
4333 count2 = I915_READ(DDREC);
4334 count3 = I915_READ(CSIEC);
4335
4336 total_count = count1 + count2 + count3;
4337
4338 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4339 if (total_count < dev_priv->ips.last_count1) {
4340 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4341 diff += total_count;
4342 } else {
20e4d407 4343 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4344 }
4345
4346 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4347 if (cparams[i].i == dev_priv->ips.c_m &&
4348 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4349 m = cparams[i].m;
4350 c = cparams[i].c;
4351 break;
4352 }
4353 }
4354
4355 diff = div_u64(diff, diff1);
4356 ret = ((m * diff) + c);
4357 ret = div_u64(ret, 10);
4358
20e4d407
DV		 4359 dev_priv->ips.last_count1 = total_count;
4360 dev_priv->ips.last_time1 = now;
eb48eb00 4361
20e4d407 4362 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4363
4364 return ret;
4365}
4366
f531dcb2
CW		 4367unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4368{
4369 unsigned long val;
4370
4371 if (dev_priv->info->gen != 5)
4372 return 0;
4373
4374 spin_lock_irq(&mchdev_lock);
4375
4376 val = __i915_chipset_val(dev_priv);
4377
4378 spin_unlock_irq(&mchdev_lock);
4379
4380 return val;
4381}
4382
eb48eb00
DV		 4383unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4384{
4385 unsigned long m, x, b;
4386 u32 tsfs;
4387
4388 tsfs = I915_READ(TSFS);
4389
4390 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4391 x = I915_READ8(TR1);
4392
4393 b = tsfs & TSFS_INTR_MASK;
4394
4395 return ((m * x) / 127) - b;
4396}
4397
4398static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4399{
4400 static const struct v_table {
4401 u16 vd; /* in .1 mil */
4402 u16 vm; /* in .1 mil */
4403 } v_table[] = {
4404 { 0, 0, },
4405 { 375, 0, },
4406 { 500, 0, },
4407 { 625, 0, },
4408 { 750, 0, },
4409 { 875, 0, },
4410 { 1000, 0, },
4411 { 1125, 0, },
4412 { 4125, 3000, },
4413 { 4125, 3000, },
4414 { 4125, 3000, },
4415 { 4125, 3000, },
4416 { 4125, 3000, },
4417 { 4125, 3000, },
4418 { 4125, 3000, },
4419 { 4125, 3000, },
4420 { 4125, 3000, },
4421 { 4125, 3000, },
4422 { 4125, 3000, },
4423 { 4125, 3000, },
4424 { 4125, 3000, },
4425 { 4125, 3000, },
4426 { 4125, 3000, },
4427 { 4125, 3000, },
4428 { 4125, 3000, },
4429 { 4125, 3000, },
4430 { 4125, 3000, },
4431 { 4125, 3000, },
4432 { 4125, 3000, },
4433 { 4125, 3000, },
4434 { 4125, 3000, },
4435 { 4125, 3000, },
4436 { 4250, 3125, },
4437 { 4375, 3250, },
4438 { 4500, 3375, },
4439 { 4625, 3500, },
4440 { 4750, 3625, },
4441 { 4875, 3750, },
4442 { 5000, 3875, },
4443 { 5125, 4000, },
4444 { 5250, 4125, },
4445 { 5375, 4250, },
4446 { 5500, 4375, },
4447 { 5625, 4500, },
4448 { 5750, 4625, },
4449 { 5875, 4750, },
4450 { 6000, 4875, },
4451 { 6125, 5000, },
4452 { 6250, 5125, },
4453 { 6375, 5250, },
4454 { 6500, 5375, },
4455 { 6625, 5500, },
4456 { 6750, 5625, },
4457 { 6875, 5750, },
4458 { 7000, 5875, },
4459 { 7125, 6000, },
4460 { 7250, 6125, },
4461 { 7375, 6250, },
4462 { 7500, 6375, },
4463 { 7625, 6500, },
4464 { 7750, 6625, },
4465 { 7875, 6750, },
4466 { 8000, 6875, },
4467 { 8125, 7000, },
4468 { 8250, 7125, },
4469 { 8375, 7250, },
4470 { 8500, 7375, },
4471 { 8625, 7500, },
4472 { 8750, 7625, },
4473 { 8875, 7750, },
4474 { 9000, 7875, },
4475 { 9125, 8000, },
4476 { 9250, 8125, },
4477 { 9375, 8250, },
4478 { 9500, 8375, },
4479 { 9625, 8500, },
4480 { 9750, 8625, },
4481 { 9875, 8750, },
4482 { 10000, 8875, },
4483 { 10125, 9000, },
4484 { 10250, 9125, },
4485 { 10375, 9250, },
4486 { 10500, 9375, },
4487 { 10625, 9500, },
4488 { 10750, 9625, },
4489 { 10875, 9750, },
4490 { 11000, 9875, },
4491 { 11125, 10000, },
4492 { 11250, 10125, },
4493 { 11375, 10250, },
4494 { 11500, 10375, },
4495 { 11625, 10500, },
4496 { 11750, 10625, },
4497 { 11875, 10750, },
4498 { 12000, 10875, },
4499 { 12125, 11000, },
4500 { 12250, 11125, },
4501 { 12375, 11250, },
4502 { 12500, 11375, },
4503 { 12625, 11500, },
4504 { 12750, 11625, },
4505 { 12875, 11750, },
4506 { 13000, 11875, },
4507 { 13125, 12000, },
4508 { 13250, 12125, },
4509 { 13375, 12250, },
4510 { 13500, 12375, },
4511 { 13625, 12500, },
4512 { 13750, 12625, },
4513 { 13875, 12750, },
4514 { 14000, 12875, },
4515 { 14125, 13000, },
4516 { 14250, 13125, },
4517 { 14375, 13250, },
4518 { 14500, 13375, },
4519 { 14625, 13500, },
4520 { 14750, 13625, },
4521 { 14875, 13750, },
4522 { 15000, 13875, },
4523 { 15125, 14000, },
4524 { 15250, 14125, },
4525 { 15375, 14250, },
4526 { 15500, 14375, },
4527 { 15625, 14500, },
4528 { 15750, 14625, },
4529 { 15875, 14750, },
4530 { 16000, 14875, },
4531 { 16125, 15000, },
4532 };
4533 if (dev_priv->info->is_mobile)
4534 return v_table[pxvid].vm;
4535 else
4536 return v_table[pxvid].vd;
4537}
4538
02d71956 4539static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4540{
4541 struct timespec now, diff1;
4542 u64 diff;
4543 unsigned long diffms;
4544 u32 count;
4545
02d71956 4546 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4547
4548 getrawmonotonic(&now);
20e4d407 4549 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4550
4551 /* Don't divide by 0 */
4552 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4553 if (!diffms)
4554 return;
4555
4556 count = I915_READ(GFXEC);
4557
20e4d407
DV		 4558 if (count < dev_priv->ips.last_count2) {
4559 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4560 diff += count;
4561 } else {
20e4d407 4562 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4563 }
4564
20e4d407
DV		 4565 dev_priv->ips.last_count2 = count;
4566 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4567
4568 /* More magic constants... */
4569 diff = diff * 1181;
4570 diff = div_u64(diff, diffms * 10);
20e4d407 4571 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4572}
4573
02d71956
DV		 4574void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4575{
4576 if (dev_priv->info->gen != 5)
4577 return;
4578
9270388e 4579 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4580
4581 __i915_update_gfx_val(dev_priv);
4582
9270388e 4583 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4584}
4585
f531dcb2 4586static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4587{
4588 unsigned long t, corr, state1, corr2, state2;
4589 u32 pxvid, ext_v;
4590
02d71956
DV		 4591 assert_spin_locked(&mchdev_lock);
4592
c6a828d3 4593 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4594 pxvid = (pxvid >> 24) & 0x7f;
4595 ext_v = pvid_to_extvid(dev_priv, pxvid);
4596
4597 state1 = ext_v;
4598
4599 t = i915_mch_val(dev_priv);
4600
4601 /* Revel in the empirically derived constants */
4602
4603 /* Correction factor in 1/100000 units */
4604 if (t > 80)
4605 corr = ((t * 2349) + 135940);
4606 else if (t >= 50)
4607 corr = ((t * 964) + 29317);
4608 else /* < 50 */
4609 corr = ((t * 301) + 1004);
4610
4611 corr = corr * ((150142 * state1) / 10000 - 78642);
4612 corr /= 100000;
20e4d407 4613 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4614
4615 state2 = (corr2 * state1) / 10000;
4616 state2 /= 100; /* convert to mW */
4617
02d71956 4618 __i915_update_gfx_val(dev_priv);
eb48eb00 4619
20e4d407 4620 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4621}
4622
f531dcb2
CW		 4623unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4624{
4625 unsigned long val;
4626
4627 if (dev_priv->info->gen != 5)
4628 return 0;
4629
4630 spin_lock_irq(&mchdev_lock);
4631
4632 val = __i915_gfx_val(dev_priv);
4633
4634 spin_unlock_irq(&mchdev_lock);
4635
4636 return val;
4637}
4638
eb48eb00
DV		 4639/**
4640 * i915_read_mch_val - return value for IPS use
4641 *
4642 * Calculate and return a value for the IPS driver to use when deciding whether
4643 * we have thermal and power headroom to increase CPU or GPU power budget.
4644 */
4645unsigned long i915_read_mch_val(void)
4646{
4647 struct drm_i915_private *dev_priv;
4648 unsigned long chipset_val, graphics_val, ret = 0;
4649
9270388e 4650 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4651 if (!i915_mch_dev)
4652 goto out_unlock;
4653 dev_priv = i915_mch_dev;
4654
f531dcb2
CW		 4655 chipset_val = __i915_chipset_val(dev_priv);
4656 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4657
4658 ret = chipset_val + graphics_val;
4659
4660out_unlock:
9270388e 4661 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4662
4663 return ret;
4664}
4665EXPORT_SYMBOL_GPL(i915_read_mch_val);
4666
4667/**
4668 * i915_gpu_raise - raise GPU frequency limit
4669 *
4670 * Raise the limit; IPS indicates we have thermal headroom.
4671 */
4672bool i915_gpu_raise(void)
4673{
4674 struct drm_i915_private *dev_priv;
4675 bool ret = true;
4676
9270388e 4677 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4678 if (!i915_mch_dev) {
4679 ret = false;
4680 goto out_unlock;
4681 }
4682 dev_priv = i915_mch_dev;
4683
20e4d407
DV		 4684 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4685 dev_priv->ips.max_delay--;
eb48eb00
DV		 4686
4687out_unlock:
9270388e 4688 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4689
4690 return ret;
4691}
4692EXPORT_SYMBOL_GPL(i915_gpu_raise);
4693
4694/**
4695 * i915_gpu_lower - lower GPU frequency limit
4696 *
4697 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4698 * frequency maximum.
4699 */
4700bool i915_gpu_lower(void)
4701{
4702 struct drm_i915_private *dev_priv;
4703 bool ret = true;
4704
9270388e 4705 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4706 if (!i915_mch_dev) {
4707 ret = false;
4708 goto out_unlock;
4709 }
4710 dev_priv = i915_mch_dev;
4711
20e4d407
DV		 4712 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4713 dev_priv->ips.max_delay++;
eb48eb00
DV		 4714
4715out_unlock:
9270388e 4716 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4717
4718 return ret;
4719}
4720EXPORT_SYMBOL_GPL(i915_gpu_lower);
4721
4722/**
4723 * i915_gpu_busy - indicate GPU business to IPS
4724 *
4725 * Tell the IPS driver whether or not the GPU is busy.
4726 */
4727bool i915_gpu_busy(void)
4728{
4729 struct drm_i915_private *dev_priv;
f047e395 4730 struct intel_ring_buffer *ring;
eb48eb00 4731 bool ret = false;
f047e395 4732 int i;
eb48eb00 4733
9270388e 4734 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4735 if (!i915_mch_dev)
4736 goto out_unlock;
4737 dev_priv = i915_mch_dev;
4738
f047e395
CW		 4739 for_each_ring(ring, dev_priv, i)
4740 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4741
4742out_unlock:
9270388e 4743 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4744
4745 return ret;
4746}
4747EXPORT_SYMBOL_GPL(i915_gpu_busy);
4748
4749/**
4750 * i915_gpu_turbo_disable - disable graphics turbo
4751 *
4752 * Disable graphics turbo by resetting the max frequency and setting the
4753 * current frequency to the default.
4754 */
4755bool i915_gpu_turbo_disable(void)
4756{
4757 struct drm_i915_private *dev_priv;
4758 bool ret = true;
4759
9270388e 4760 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4761 if (!i915_mch_dev) {
4762 ret = false;
4763 goto out_unlock;
4764 }
4765 dev_priv = i915_mch_dev;
4766
20e4d407 4767 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4768
20e4d407 4769 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4770 ret = false;
4771
4772out_unlock:
9270388e 4773 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4774
4775 return ret;
4776}
4777EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4778
4779/**
4780 * Tells the intel_ips driver that the i915 driver is now loaded, if
4781 * IPS got loaded first.
4782 *
4783 * This awkward dance is so that neither module has to depend on the
4784 * other in order for IPS to do the appropriate communication of
4785 * GPU turbo limits to i915.
4786 */
4787static void
4788ips_ping_for_i915_load(void)
4789{
4790 void (*link)(void);
4791
4792 link = symbol_get(ips_link_to_i915_driver);
4793 if (link) {
4794 link();
4795 symbol_put(ips_link_to_i915_driver);
4796 }
4797}
4798
4799void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4800{
02d71956
DV		 4801 /* We only register the i915 ips part with intel-ips once everything is
4802 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4803 spin_lock_irq(&mchdev_lock);
eb48eb00 4804 i915_mch_dev = dev_priv;
9270388e 4805 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4806
4807 ips_ping_for_i915_load();
4808}
4809
4810void intel_gpu_ips_teardown(void)
4811{
9270388e 4812 spin_lock_irq(&mchdev_lock);
eb48eb00 4813 i915_mch_dev = NULL;
9270388e 4814 spin_unlock_irq(&mchdev_lock);
eb48eb00 4815}
8090c6b9 4816static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4817{
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 u32 lcfuse;
4820 u8 pxw[16];
4821 int i;
4822
4823 /* Disable to program */
4824 I915_WRITE(ECR, 0);
4825 POSTING_READ(ECR);
4826
4827 /* Program energy weights for various events */
4828 I915_WRITE(SDEW, 0x15040d00);
4829 I915_WRITE(CSIEW0, 0x007f0000);
4830 I915_WRITE(CSIEW1, 0x1e220004);
4831 I915_WRITE(CSIEW2, 0x04000004);
4832
4833 for (i = 0; i < 5; i++)
4834 I915_WRITE(PEW + (i * 4), 0);
4835 for (i = 0; i < 3; i++)
4836 I915_WRITE(DEW + (i * 4), 0);
4837
4838 /* Program P-state weights to account for frequency power adjustment */
4839 for (i = 0; i < 16; i++) {
4840 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4841 unsigned long freq = intel_pxfreq(pxvidfreq);
4842 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4843 PXVFREQ_PX_SHIFT;
4844 unsigned long val;
4845
4846 val = vid * vid;
4847 val *= (freq / 1000);
4848 val *= 255;
4849 val /= (127*127*900);
4850 if (val > 0xff)
4851 DRM_ERROR("bad pxval: %ld\n", val);
4852 pxw[i] = val;
4853 }
4854 /* Render standby states get 0 weight */
4855 pxw[14] = 0;
4856 pxw[15] = 0;
4857
4858 for (i = 0; i < 4; i++) {
4859 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4860 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4861 I915_WRITE(PXW + (i * 4), val);
4862 }
4863
4864 /* Adjust magic regs to magic values (more experimental results) */
4865 I915_WRITE(OGW0, 0);
4866 I915_WRITE(OGW1, 0);
4867 I915_WRITE(EG0, 0x00007f00);
4868 I915_WRITE(EG1, 0x0000000e);
4869 I915_WRITE(EG2, 0x000e0000);
4870 I915_WRITE(EG3, 0x68000300);
4871 I915_WRITE(EG4, 0x42000000);
4872 I915_WRITE(EG5, 0x00140031);
4873 I915_WRITE(EG6, 0);
4874 I915_WRITE(EG7, 0);
4875
4876 for (i = 0; i < 8; i++)
4877 I915_WRITE(PXWL + (i * 4), 0);
4878
4879 /* Enable PMON + select events */
4880 I915_WRITE(ECR, 0x80000019);
4881
4882 lcfuse = I915_READ(LCFUSE02);
4883
20e4d407 4884 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4885}
4886
8090c6b9
DV		 4887void intel_disable_gt_powersave(struct drm_device *dev)
4888{
1a01ab3b
JB		 4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890
fd0c0642
DV		 4891 /* Interrupts should be disabled already to avoid re-arming. */
4892 WARN_ON(dev->irq_enabled);
4893
930ebb46 4894 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4895 ironlake_disable_drps(dev);
930ebb46 4896 ironlake_disable_rc6(dev);
0a073b84 4897 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4898 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4899 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4900 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4901 if (IS_VALLEYVIEW(dev))
4902 valleyview_disable_rps(dev);
4903 else
4904 gen6_disable_rps(dev);
c0951f0c 4905 dev_priv->rps.enabled = false;
4fc688ce 4906 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4907 }
8090c6b9
DV		 4908}
4909
1a01ab3b
JB		 4910static void intel_gen6_powersave_work(struct work_struct *work)
4911{
4912 struct drm_i915_private *dev_priv =
4913 container_of(work, struct drm_i915_private,
4914 rps.delayed_resume_work.work);
4915 struct drm_device *dev = dev_priv->dev;
4916
4fc688ce 4917 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4918
4919 if (IS_VALLEYVIEW(dev)) {
4920 valleyview_enable_rps(dev);
6edee7f3
BW		 4921 } else if (IS_BROADWELL(dev)) {
4922 gen8_enable_rps(dev);
4923 gen6_update_ring_freq(dev);
0a073b84
JB		 4924 } else {
4925 gen6_enable_rps(dev);
4926 gen6_update_ring_freq(dev);
4927 }
c0951f0c 4928 dev_priv->rps.enabled = true;
4fc688ce 4929 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4930}
4931
8090c6b9
DV		 4932void intel_enable_gt_powersave(struct drm_device *dev)
4933{
1a01ab3b
JB		 4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935
8090c6b9
DV		 4936 if (IS_IRONLAKE_M(dev)) {
4937 ironlake_enable_drps(dev);
4938 ironlake_enable_rc6(dev);
4939 intel_init_emon(dev);
0a073b84 4940 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4941 /*
4942 * PCU communication is slow and this doesn't need to be
4943 * done at any specific time, so do this out of our fast path
4944 * to make resume and init faster.
4945 */
4946 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4947 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4948 }
4949}
4950
3107bd48
DV		 4951static void ibx_init_clock_gating(struct drm_device *dev)
4952{
4953 struct drm_i915_private *dev_priv = dev->dev_private;
4954
4955 /*
4956 * On Ibex Peak and Cougar Point, we need to disable clock
4957 * gating for the panel power sequencer or it will fail to
4958 * start up when no ports are active.
4959 */
4960 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4961}
4962
0e088b8f
VS		 4963static void g4x_disable_trickle_feed(struct drm_device *dev)
4964{
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 int pipe;
4967
4968 for_each_pipe(pipe) {
4969 I915_WRITE(DSPCNTR(pipe),
4970 I915_READ(DSPCNTR(pipe)) |
4971 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4972 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4973 }
4974}
4975
1fa61106 4976static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4977{
4978 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4979 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4980
f1e8fa56
DL		 4981 /*
4982 * Required for FBC
4983 * WaFbcDisableDpfcClockGating:ilk
4984 */
4d47e4f5
DL		 4985 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4986 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4987 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4988
4989 I915_WRITE(PCH_3DCGDIS0,
4990 MARIUNIT_CLOCK_GATE_DISABLE |
4991 SVSMUNIT_CLOCK_GATE_DISABLE);
4992 I915_WRITE(PCH_3DCGDIS1,
4993 VFMUNIT_CLOCK_GATE_DISABLE);
4994
6f1d69b0
ED		 4995 /*
4996 * According to the spec the following bits should be set in
4997 * order to enable memory self-refresh
4998 * The bit 22/21 of 0x42004
4999 * The bit 5 of 0x42020
5000 * The bit 15 of 0x45000
5001 */
5002 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5003 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5004 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5005 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5006 I915_WRITE(DISP_ARB_CTL,
5007 (I915_READ(DISP_ARB_CTL) |
5008 DISP_FBC_WM_DIS));
5009 I915_WRITE(WM3_LP_ILK, 0);
5010 I915_WRITE(WM2_LP_ILK, 0);
5011 I915_WRITE(WM1_LP_ILK, 0);
5012
5013 /*
5014 * Based on the document from hardware guys the following bits
5015 * should be set unconditionally in order to enable FBC.
5016 * The bit 22 of 0x42000
5017 * The bit 22 of 0x42004
5018 * The bit 7,8,9 of 0x42020.
5019 */
5020 if (IS_IRONLAKE_M(dev)) {
4bb35334 5021 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5022 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5023 I915_READ(ILK_DISPLAY_CHICKEN1) |
5024 ILK_FBCQ_DIS);
5025 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5026 I915_READ(ILK_DISPLAY_CHICKEN2) |
5027 ILK_DPARB_GATE);
6f1d69b0
ED		 5028 }
5029
4d47e4f5
DL		 5030 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5031
6f1d69b0
ED		 5032 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5033 I915_READ(ILK_DISPLAY_CHICKEN2) |
5034 ILK_ELPIN_409_SELECT);
5035 I915_WRITE(_3D_CHICKEN2,
5036 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5037 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5038
ecdb4eb7 5039 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5040 I915_WRITE(CACHE_MODE_0,
5041 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5042
0e088b8f 5043 g4x_disable_trickle_feed(dev);
bdad2b2f 5044
3107bd48
DV		 5045 ibx_init_clock_gating(dev);
5046}
5047
5048static void cpt_init_clock_gating(struct drm_device *dev)
5049{
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 int pipe;
3f704fa2 5052 uint32_t val;
3107bd48
DV		 5053
5054 /*
5055 * On Ibex Peak and Cougar Point, we need to disable clock
5056 * gating for the panel power sequencer or it will fail to
5057 * start up when no ports are active.
5058 */
cd664078
JB		 5059 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5060 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5061 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5062 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5063 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5064 /* The below fixes the weird display corruption, a few pixels shifted
5065 * downward, on (only) LVDS of some HP laptops with IVY.
5066 */
3f704fa2 5067 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5068 val = I915_READ(TRANS_CHICKEN2(pipe));
5069 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5070 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5071 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5072 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5073 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5074 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5075 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5076 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5077 }
3107bd48
DV		 5078 /* WADP0ClockGatingDisable */
5079 for_each_pipe(pipe) {
5080 I915_WRITE(TRANS_CHICKEN1(pipe),
5081 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5082 }
6f1d69b0
ED		 5083}
5084
1d7aaa0c
DV		 5085static void gen6_check_mch_setup(struct drm_device *dev)
5086{
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5088 uint32_t tmp;
5089
5090 tmp = I915_READ(MCH_SSKPD);
5091 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5092 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5093 DRM_INFO("This can cause pipe underruns and display issues.\n");
5094 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5095 }
5096}
5097
1fa61106 5098static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5099{
5100 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5101 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5102
231e54f6 5103 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5104
5105 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5106 I915_READ(ILK_DISPLAY_CHICKEN2) |
5107 ILK_ELPIN_409_SELECT);
5108
ecdb4eb7 5109 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5110 I915_WRITE(_3D_CHICKEN,
5111 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5112
ecdb4eb7 5113 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5114 if (IS_SNB_GT1(dev))
5115 I915_WRITE(GEN6_GT_MODE,
5116 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5117
6f1d69b0
ED		 5118 I915_WRITE(WM3_LP_ILK, 0);
5119 I915_WRITE(WM2_LP_ILK, 0);
5120 I915_WRITE(WM1_LP_ILK, 0);
5121
6f1d69b0 5122 I915_WRITE(CACHE_MODE_0,
50743298 5123 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5124
5125 I915_WRITE(GEN6_UCGCTL1,
5126 I915_READ(GEN6_UCGCTL1) |
5127 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5128 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5129
5130 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5131 * gating disable must be set. Failure to set it results in
5132 * flickering pixels due to Z write ordering failures after
5133 * some amount of runtime in the Mesa "fire" demo, and Unigine
5134 * Sanctuary and Tropics, and apparently anything else with
5135 * alpha test or pixel discard.
5136 *
5137 * According to the spec, bit 11 (RCCUNIT) must also be set,
5138 * but we didn't debug actual testcases to find it out.
0f846f81 5139 *
ecdb4eb7
DL		 5140 * Also apply WaDisableVDSUnitClockGating:snb and
5141 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 5142 */
5143 I915_WRITE(GEN6_UCGCTL2,
0f846f81 5144 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 5145 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5146 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5147
5148 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 5149 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5150 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 5151
5152 /*
5153 * According to the spec the following bits should be
5154 * set in order to enable memory self-refresh and fbc:
5155 * The bit21 and bit22 of 0x42000
5156 * The bit21 and bit22 of 0x42004
5157 * The bit5 and bit7 of 0x42020
5158 * The bit14 of 0x70180
5159 * The bit14 of 0x71180
4bb35334
DL		 5160 *
5161 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5162 */
5163 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5164 I915_READ(ILK_DISPLAY_CHICKEN1) |
5165 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5166 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5167 I915_READ(ILK_DISPLAY_CHICKEN2) |
5168 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5169 I915_WRITE(ILK_DSPCLK_GATE_D,
5170 I915_READ(ILK_DSPCLK_GATE_D) |
5171 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5172 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5173
0e088b8f 5174 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 5175
5176 /* The default value should be 0x200 according to docs, but the two
5177 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5178 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5179 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 5180
5181 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5182
5183 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5184}
5185
5186static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5187{
5188 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5189
5190 reg &= ~GEN7_FF_SCHED_MASK;
5191 reg |= GEN7_FF_TS_SCHED_HW;
5192 reg |= GEN7_FF_VS_SCHED_HW;
5193 reg |= GEN7_FF_DS_SCHED_HW;
5194
41c0b3a8
BW		 5195 if (IS_HASWELL(dev_priv->dev))
5196 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5197
6f1d69b0
ED		 5198 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5199}
5200
17a303ec
PZ		 5201static void lpt_init_clock_gating(struct drm_device *dev)
5202{
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204
5205 /*
5206 * TODO: this bit should only be enabled when really needed, then
5207 * disabled when not needed anymore in order to save power.
5208 */
5209 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5210 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5211 I915_READ(SOUTH_DSPCLK_GATE_D) |
5212 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5213
5214 /* WADPOClockGatingDisable:hsw */
5215 I915_WRITE(_TRANSA_CHICKEN1,
5216 I915_READ(_TRANSA_CHICKEN1) |
5217 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5218}
5219
7d708ee4
ID		 5220static void lpt_suspend_hw(struct drm_device *dev)
5221{
5222 struct drm_i915_private *dev_priv = dev->dev_private;
5223
5224 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5225 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5226
5227 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5228 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5229 }
5230}
5231
1020a5c2
BW		 5232static void gen8_init_clock_gating(struct drm_device *dev)
5233{
5234 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 5235 enum pipe i;
1020a5c2
BW		 5236
5237 I915_WRITE(WM3_LP_ILK, 0);
5238 I915_WRITE(WM2_LP_ILK, 0);
5239 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5240
5241 /* FIXME(BDW): Check all the w/a, some might only apply to
5242 * pre-production hw. */
5243
fd392b60
BW		 5244 WARN(!i915_preliminary_hw_support,
5245 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5246 I915_WRITE(HALF_SLICE_CHICKEN3,
5247 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5248 I915_WRITE(HALF_SLICE_CHICKEN3,
5249 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5250 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5251
7f88da0c
BW		 5252 I915_WRITE(_3D_CHICKEN3,
5253 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5254
a75f3628
BW		 5255 I915_WRITE(COMMON_SLICE_CHICKEN2,
5256 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5257
4c2e7a5f
BW		 5258 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5259 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5260
50ed5fbd
BW		 5261 /* WaSwitchSolVfFArbitrationPriority */
5262 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce
BW		 5263
5264 /* WaPsrDPAMaskVBlankInSRD */
5265 I915_WRITE(CHICKEN_PAR1_1,
5266 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5267
5268 /* WaPsrDPRSUnmaskVBlankInSRD */
5269 for_each_pipe(i) {
5270 I915_WRITE(CHICKEN_PIPESL_1(i),
5271 I915_READ(CHICKEN_PIPESL_1(i) |
5272 DPRS_MASK_VBLANK_SRD));
5273 }
1020a5c2
BW		 5274}
5275
cad2a2d7
ED		 5276static void haswell_init_clock_gating(struct drm_device *dev)
5277{
5278 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5279
5280 I915_WRITE(WM3_LP_ILK, 0);
5281 I915_WRITE(WM2_LP_ILK, 0);
5282 I915_WRITE(WM1_LP_ILK, 0);
5283
5284 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5285 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5286 */
5287 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5288
ecdb4eb7 5289 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5290 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5291 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5292
ecdb4eb7 5293 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5294 I915_WRITE(GEN7_L3CNTLREG1,
5295 GEN7_WA_FOR_GEN7_L3_CONTROL);
5296 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5297 GEN7_WA_L3_CHICKEN_MODE);
5298
f3fc4884
FJ		 5299 /* L3 caching of data atomics doesn't work -- disable it. */
5300 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5301 I915_WRITE(HSW_ROW_CHICKEN3,
5302 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5303
ecdb4eb7 5304 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5305 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5306 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5307 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5308
ecdb4eb7 5309 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5310 gen7_setup_fixed_func_scheduler(dev_priv);
5311
ecdb4eb7 5312 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5313 I915_WRITE(CACHE_MODE_1,
5314 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5315
ecdb4eb7 5316 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5317 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5318
90a88643
PZ		 5319 /* WaRsPkgCStateDisplayPMReq:hsw */
5320 I915_WRITE(CHICKEN_PAR1_1,
5321 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5322
17a303ec 5323 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5324}
5325
1fa61106 5326static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5329 uint32_t snpcr;
6f1d69b0 5330
6f1d69b0
ED		 5331 I915_WRITE(WM3_LP_ILK, 0);
5332 I915_WRITE(WM2_LP_ILK, 0);
5333 I915_WRITE(WM1_LP_ILK, 0);
5334
231e54f6 5335 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5336
ecdb4eb7 5337 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5338 I915_WRITE(_3D_CHICKEN3,
5339 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5340
ecdb4eb7 5341 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5342 I915_WRITE(IVB_CHICKEN3,
5343 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5344 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5345
ecdb4eb7 5346 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5347 if (IS_IVB_GT1(dev))
5348 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5349 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5350 else
5351 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5352 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5353
ecdb4eb7 5354 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5355 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5356 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5357
ecdb4eb7 5358 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5359 I915_WRITE(GEN7_L3CNTLREG1,
5360 GEN7_WA_FOR_GEN7_L3_CONTROL);
5361 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5362 GEN7_WA_L3_CHICKEN_MODE);
5363 if (IS_IVB_GT1(dev))
5364 I915_WRITE(GEN7_ROW_CHICKEN2,
5365 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5366 else
5367 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5368 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5369
6f1d69b0 5370
ecdb4eb7 5371 /* WaForceL3Serialization:ivb */
61939d97
JB		 5372 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5373 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5374
0f846f81
JB		 5375 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5376 * gating disable must be set. Failure to set it results in
5377 * flickering pixels due to Z write ordering failures after
5378 * some amount of runtime in the Mesa "fire" demo, and Unigine
5379 * Sanctuary and Tropics, and apparently anything else with
5380 * alpha test or pixel discard.
5381 *
5382 * According to the spec, bit 11 (RCCUNIT) must also be set,
5383 * but we didn't debug actual testcases to find it out.
5384 *
5385 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5386 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5387 */
5388 I915_WRITE(GEN6_UCGCTL2,
5389 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5390 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5391
ecdb4eb7 5392 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5393 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5394 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5395 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5396
0e088b8f 5397 g4x_disable_trickle_feed(dev);
6f1d69b0 5398
ecdb4eb7 5399 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5400 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5401
ecdb4eb7 5402 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5403 I915_WRITE(CACHE_MODE_1,
5404 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5405
5406 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5407 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5408 snpcr |= GEN6_MBC_SNPCR_MED;
5409 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5410
ab5c608b
BW		 5411 if (!HAS_PCH_NOP(dev))
5412 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5413
5414 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5415}
5416
1fa61106 5417static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5418{
5419 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5420 u32 val;
5421
5422 mutex_lock(&dev_priv->rps.hw_lock);
5423 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5424 mutex_unlock(&dev_priv->rps.hw_lock);
5425 switch ((val >> 6) & 3) {
5426 case 0:
85b1d7b3
JB		 5427 dev_priv->mem_freq = 800;
5428 break;
f64a28a7 5429 case 1:
85b1d7b3
JB		 5430 dev_priv->mem_freq = 1066;
5431 break;
f64a28a7 5432 case 2:
85b1d7b3
JB		 5433 dev_priv->mem_freq = 1333;
5434 break;
f64a28a7 5435 case 3:
2325991e 5436 dev_priv->mem_freq = 1333;
f64a28a7 5437 break;
85b1d7b3
JB		 5438 }
5439 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5440
d7fe0cc0 5441 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5442
ecdb4eb7 5443 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5444 I915_WRITE(_3D_CHICKEN3,
5445 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5446
ecdb4eb7 5447 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5448 I915_WRITE(IVB_CHICKEN3,
5449 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5450 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5451
ecdb4eb7 5452 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5453 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5454 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5455 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5456
ecdb4eb7 5457 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5458 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5459 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5460
ecdb4eb7 5461 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5462 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5463 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5464
ecdb4eb7 5465 /* WaForceL3Serialization:vlv */
61939d97
JB		 5466 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5467 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5468
ecdb4eb7 5469 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5470 I915_WRITE(GEN7_ROW_CHICKEN2,
5471 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5472
ecdb4eb7 5473 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5474 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5475 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5476 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5477
0f846f81
JB		 5478 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5479 * gating disable must be set. Failure to set it results in
5480 * flickering pixels due to Z write ordering failures after
5481 * some amount of runtime in the Mesa "fire" demo, and Unigine
5482 * Sanctuary and Tropics, and apparently anything else with
5483 * alpha test or pixel discard.
5484 *
5485 * According to the spec, bit 11 (RCCUNIT) must also be set,
5486 * but we didn't debug actual testcases to find it out.
5487 *
5488 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5489 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5490 *
ecdb4eb7
DL		 5491 * Also apply WaDisableVDSUnitClockGating:vlv and
5492 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5493 */
5494 I915_WRITE(GEN6_UCGCTL2,
5495 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5496 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5497 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5498 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5499 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5500
e3f33d46
JB		 5501 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5502
e0d8d59b 5503 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5504
6b26c86d
DV		 5505 I915_WRITE(CACHE_MODE_1,
5506 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5507
2d809570 5508 /*
ecdb4eb7 5509 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5510 * Disable clock gating on th GCFG unit to prevent a delay
5511 * in the reporting of vblank events.
5512 */
4e8c84a5
JB		 5513 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5514
5515 /* Conservative clock gating settings for now */
5516 I915_WRITE(0x9400, 0xffffffff);
5517 I915_WRITE(0x9404, 0xffffffff);
5518 I915_WRITE(0x9408, 0xffffffff);
5519 I915_WRITE(0x940c, 0xffffffff);
5520 I915_WRITE(0x9410, 0xffffffff);
5521 I915_WRITE(0x9414, 0xffffffff);
5522 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5523}
5524
1fa61106 5525static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5526{
5527 struct drm_i915_private *dev_priv = dev->dev_private;
5528 uint32_t dspclk_gate;
5529
5530 I915_WRITE(RENCLK_GATE_D1, 0);
5531 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5532 GS_UNIT_CLOCK_GATE_DISABLE |
5533 CL_UNIT_CLOCK_GATE_DISABLE);
5534 I915_WRITE(RAMCLK_GATE_D, 0);
5535 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5536 OVRUNIT_CLOCK_GATE_DISABLE |
5537 OVCUNIT_CLOCK_GATE_DISABLE;
5538 if (IS_GM45(dev))
5539 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5540 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5541
5542 /* WaDisableRenderCachePipelinedFlush */
5543 I915_WRITE(CACHE_MODE_0,
5544 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5545
0e088b8f 5546 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5547}
5548
1fa61106 5549static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5554 I915_WRITE(RENCLK_GATE_D2, 0);
5555 I915_WRITE(DSPCLK_GATE_D, 0);
5556 I915_WRITE(RAMCLK_GATE_D, 0);
5557 I915_WRITE16(DEUC, 0);
20f94967
VS		 5558 I915_WRITE(MI_ARB_STATE,
5559 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5560}
5561
1fa61106 5562static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5563{
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565
5566 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5567 I965_RCC_CLOCK_GATE_DISABLE |
5568 I965_RCPB_CLOCK_GATE_DISABLE |
5569 I965_ISC_CLOCK_GATE_DISABLE |
5570 I965_FBC_CLOCK_GATE_DISABLE);
5571 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5572 I915_WRITE(MI_ARB_STATE,
5573 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5574}
5575
1fa61106 5576static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5577{
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 u32 dstate = I915_READ(D_STATE);
5580
5581 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5582 DSTATE_DOT_CLOCK_GATING;
5583 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5584
5585 if (IS_PINEVIEW(dev))
5586 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5587
5588 /* IIR "flip pending" means done if this bit is set */
5589 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5590}
5591
1fa61106 5592static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5593{
5594 struct drm_i915_private *dev_priv = dev->dev_private;
5595
5596 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5597}
5598
1fa61106 5599static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5600{
5601 struct drm_i915_private *dev_priv = dev->dev_private;
5602
5603 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5604}
5605
6f1d69b0
ED		 5606void intel_init_clock_gating(struct drm_device *dev)
5607{
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609
5610 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5611}
5612
7d708ee4
ID		 5613void intel_suspend_hw(struct drm_device *dev)
5614{
5615 if (HAS_PCH_LPT(dev))
5616 lpt_suspend_hw(dev);
5617}
5618
c1ca727f
ID		 5619#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5620 for (i = 0; \
5621 i < (power_domains)->power_well_count && \
5622 ((power_well) = &(power_domains)->power_wells[i]); \
5623 i++) \
5624 if ((power_well)->domains & (domain_mask))
5625
5626#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5627 for (i = (power_domains)->power_well_count - 1; \
5628 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5629 i--) \
5630 if ((power_well)->domains & (domain_mask))
5631
15d199ea
PZ		 5632/**
5633 * We should only use the power well if we explicitly asked the hardware to
5634 * enable it, so check if it's enabled and also check if we've requested it to
5635 * be enabled.
5636 */
c1ca727f
ID		 5637static bool hsw_power_well_enabled(struct drm_device *dev,
5638 struct i915_power_well *power_well)
5639{
5640 struct drm_i915_private *dev_priv = dev->dev_private;
5641
5642 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5643 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5644}
5645
ddf9c536
ID		 5646bool intel_display_power_enabled_sw(struct drm_device *dev,
5647 enum intel_display_power_domain domain)
5648{
5649 struct drm_i915_private *dev_priv = dev->dev_private;
5650 struct i915_power_domains *power_domains;
5651
5652 power_domains = &dev_priv->power_domains;
5653
5654 return power_domains->domain_use_count[domain];
5655}
5656
b97186f0
PZ		 5657bool intel_display_power_enabled(struct drm_device *dev,
5658 enum intel_display_power_domain domain)
15d199ea
PZ		 5659{
5660 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5661 struct i915_power_domains *power_domains;
5662 struct i915_power_well *power_well;
5663 bool is_enabled;
5664 int i;
15d199ea 5665
c1ca727f
ID		 5666 power_domains = &dev_priv->power_domains;
5667
5668 is_enabled = true;
5669
5670 mutex_lock(&power_domains->lock);
5671 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5672 if (power_well->always_on)
5673 continue;
5674
c1ca727f
ID		 5675 if (!power_well->is_enabled(dev, power_well)) {
5676 is_enabled = false;
5677 break;
5678 }
5679 }
5680 mutex_unlock(&power_domains->lock);
5681
5682 return is_enabled;
15d199ea
PZ		 5683}
5684
d5e8fdc8
PZ		 5685static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5686{
5687 struct drm_device *dev = dev_priv->dev;
5688 unsigned long irqflags;
5689
f9dcb0df
PZ		 5690 /*
5691 * After we re-enable the power well, if we touch VGA register 0x3d5
5692 * we'll get unclaimed register interrupts. This stops after we write
5693 * anything to the VGA MSR register. The vgacon module uses this
5694 * register all the time, so if we unbind our driver and, as a
5695 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5696 * console_unlock(). So make here we touch the VGA MSR register, making
5697 * sure vgacon can keep working normally without triggering interrupts
5698 * and error messages.
5699 */
5700 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5701 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5702 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5703
d5e8fdc8
PZ		 5704 if (IS_BROADWELL(dev)) {
5705 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5706 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5707 dev_priv->de_irq_mask[PIPE_B]);
5708 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5709 ~dev_priv->de_irq_mask[PIPE_B] |
5710 GEN8_PIPE_VBLANK);
5711 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5712 dev_priv->de_irq_mask[PIPE_C]);
5713 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5714 ~dev_priv->de_irq_mask[PIPE_C] |
5715 GEN8_PIPE_VBLANK);
5716 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5717 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5718 }
5719}
5720
5721static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5722{
5723 struct drm_device *dev = dev_priv->dev;
5724 enum pipe p;
5725 unsigned long irqflags;
5726
5727 /*
5728 * After this, the registers on the pipes that are part of the power
5729 * well will become zero, so we have to adjust our counters according to
5730 * that.
5731 *
5732 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5733 */
5734 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5735 for_each_pipe(p)
5736 if (p != PIPE_A)
5737 dev->vblank[p].last = 0;
5738 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5739}
5740
c1ca727f
ID		 5741static void hsw_set_power_well(struct drm_device *dev,
5742 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5743{
5744 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5745 bool is_enabled, enable_requested;
5746 uint32_t tmp;
d0d3e513 5747
d62292c8
PZ		 5748 WARN_ON(dev_priv->pc8.enabled);
5749
fa42e23c 5750 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5751 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5752 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5753
fa42e23c
PZ		 5754 if (enable) {
5755 if (!enable_requested)
6aedd1f5
PZ		 5756 I915_WRITE(HSW_PWR_WELL_DRIVER,
5757 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5758
fa42e23c
PZ		 5759 if (!is_enabled) {
5760 DRM_DEBUG_KMS("Enabling power well\n");
5761 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5762 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5763 DRM_ERROR("Timeout enabling power well\n");
5764 }
596cc11e 5765
d5e8fdc8 5766 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5767 } else {
5768 if (enable_requested) {
5769 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5770 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5771 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5772
d5e8fdc8 5773 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5774 }
5775 }
fa42e23c 5776}
d0d3e513 5777
b4ed4484
ID		 5778static void __intel_power_well_get(struct drm_device *dev,
5779 struct i915_power_well *power_well)
2d66aef5 5780{
d62292c8
PZ		 5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782
5783 if (!power_well->count++ && power_well->set) {
5784 hsw_disable_package_c8(dev_priv);
c1ca727f 5785 power_well->set(dev, power_well, true);
d62292c8 5786 }
2d66aef5
VS		 5787}
5788
b4ed4484
ID		 5789static void __intel_power_well_put(struct drm_device *dev,
5790 struct i915_power_well *power_well)
2d66aef5 5791{
d62292c8
PZ		 5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793
2d66aef5 5794 WARN_ON(!power_well->count);
c1ca727f 5795
d62292c8
PZ		 5796 if (!--power_well->count && power_well->set &&
5797 i915_disable_power_well) {
c1ca727f 5798 power_well->set(dev, power_well, false);
d62292c8
PZ		 5799 hsw_enable_package_c8(dev_priv);
5800 }
2d66aef5
VS		 5801}
5802
6765625e
VS		 5803void intel_display_power_get(struct drm_device *dev,
5804 enum intel_display_power_domain domain)
5805{
5806 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5807 struct i915_power_domains *power_domains;
c1ca727f
ID		 5808 struct i915_power_well *power_well;
5809 int i;
6765625e 5810
83c00f55
ID		 5811 power_domains = &dev_priv->power_domains;
5812
5813 mutex_lock(&power_domains->lock);
1da51581 5814
c1ca727f
ID		 5815 for_each_power_well(i, power_well, BIT(domain), power_domains)
5816 __intel_power_well_get(dev, power_well);
1da51581 5817
ddf9c536
ID		 5818 power_domains->domain_use_count[domain]++;
5819
83c00f55 5820 mutex_unlock(&power_domains->lock);
6765625e
VS		 5821}
5822
5823void intel_display_power_put(struct drm_device *dev,
5824 enum intel_display_power_domain domain)
5825{
5826 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5827 struct i915_power_domains *power_domains;
c1ca727f
ID		 5828 struct i915_power_well *power_well;
5829 int i;
6765625e 5830
83c00f55
ID		 5831 power_domains = &dev_priv->power_domains;
5832
5833 mutex_lock(&power_domains->lock);
1da51581 5834
1da51581
ID		 5835 WARN_ON(!power_domains->domain_use_count[domain]);
5836 power_domains->domain_use_count[domain]--;
ddf9c536
ID		 5837
5838 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5839 __intel_power_well_put(dev, power_well);
1da51581 5840
83c00f55 5841 mutex_unlock(&power_domains->lock);
6765625e
VS		 5842}
5843
83c00f55 5844static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5845
5846/* Display audio driver power well request */
5847void i915_request_power_well(void)
5848{
b4ed4484
ID		 5849 struct drm_i915_private *dev_priv;
5850
a38911a3
WX		 5851 if (WARN_ON(!hsw_pwr))
5852 return;
5853
b4ed4484
ID		 5854 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5855 power_domains);
fbeeaa23 5856 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5857}
5858EXPORT_SYMBOL_GPL(i915_request_power_well);
5859
5860/* Display audio driver power well release */
5861void i915_release_power_well(void)
5862{
b4ed4484
ID		 5863 struct drm_i915_private *dev_priv;
5864
a38911a3
WX		 5865 if (WARN_ON(!hsw_pwr))
5866 return;
5867
b4ed4484
ID		 5868 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5869 power_domains);
fbeeaa23 5870 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5871}
5872EXPORT_SYMBOL_GPL(i915_release_power_well);
5873
1c2256df
ID		 5874static struct i915_power_well i9xx_always_on_power_well[] = {
5875 {
5876 .name = "always-on",
5877 .always_on = 1,
5878 .domains = POWER_DOMAIN_MASK,
5879 },
5880};
5881
c1ca727f 5882static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5883 {
5884 .name = "always-on",
5885 .always_on = 1,
5886 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5887 },
c1ca727f
ID		 5888 {
5889 .name = "display",
5890 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5891 .is_enabled = hsw_power_well_enabled,
5892 .set = hsw_set_power_well,
5893 },
5894};
5895
5896static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5897 {
5898 .name = "always-on",
5899 .always_on = 1,
5900 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5901 },
c1ca727f
ID		 5902 {
5903 .name = "display",
5904 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5905 .is_enabled = hsw_power_well_enabled,
5906 .set = hsw_set_power_well,
5907 },
5908};
5909
5910#define set_power_wells(power_domains, __power_wells) ({ \
5911 (power_domains)->power_wells = (__power_wells); \
5912 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5913})
5914
ddb642fb 5915int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5916{
5917 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5918 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5919
83c00f55 5920 mutex_init(&power_domains->lock);
a38911a3 5921
c1ca727f
ID		 5922 /*
5923 * The enabling order will be from lower to higher indexed wells,
5924 * the disabling order is reversed.
5925 */
5926 if (IS_HASWELL(dev)) {
5927 set_power_wells(power_domains, hsw_power_wells);
5928 hsw_pwr = power_domains;
5929 } else if (IS_BROADWELL(dev)) {
5930 set_power_wells(power_domains, bdw_power_wells);
5931 hsw_pwr = power_domains;
5932 } else {
1c2256df 5933 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5934 }
a38911a3
WX		 5935
5936 return 0;
5937}
5938
ddb642fb 5939void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5940{
5941 hsw_pwr = NULL;
5942}
5943
ddb642fb 5944static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5945{
5946 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5947 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5948 struct i915_power_well *power_well;
c1ca727f 5949 int i;
9cdb826c 5950
83c00f55 5951 mutex_lock(&power_domains->lock);
c1ca727f
ID		 5952 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5953 if (power_well->set)
5954 power_well->set(dev, power_well, power_well->count > 0);
5955 }
83c00f55 5956 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5957}
5958
fa42e23c
PZ		 5959/*
5960 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5961 * when not needed anymore. We have 4 registers that can request the power well
5962 * to be enabled, and it will only be disabled if none of the registers is
5963 * requesting it to be enabled.
d0d3e513 5964 */
ddb642fb 5965void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5966{
5967 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5968
fa42e23c 5969 /* For now, we need the power well to be always enabled. */
baa70707 5970 intel_display_set_init_power(dev, true);
ddb642fb 5971 intel_power_domains_resume(dev);
d0d3e513 5972
f7243ac9
ID		 5973 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5974 return;
5975
fa42e23c
PZ		 5976 /* We're taking over the BIOS, so clear any requests made by it since
5977 * the driver is in charge now. */
6aedd1f5 5978 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5979 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5980}
5981
c67a470b
PZ		 5982/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5983void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5984{
5985 hsw_disable_package_c8(dev_priv);
5986}
5987
5988void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5989{
5990 hsw_enable_package_c8(dev_priv);
5991}
5992
8a187455
PZ		 5993void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5994{
5995 struct drm_device *dev = dev_priv->dev;
5996 struct device *device = &dev->pdev->dev;
5997
5998 if (!HAS_RUNTIME_PM(dev))
5999 return;
6000
6001 pm_runtime_get_sync(device);
6002 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6003}
6004
6005void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6006{
6007 struct drm_device *dev = dev_priv->dev;
6008 struct device *device = &dev->pdev->dev;
6009
6010 if (!HAS_RUNTIME_PM(dev))
6011 return;
6012
6013 pm_runtime_mark_last_busy(device);
6014 pm_runtime_put_autosuspend(device);
6015}
6016
6017void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6018{
6019 struct drm_device *dev = dev_priv->dev;
6020 struct device *device = &dev->pdev->dev;
6021
6022 dev_priv->pm.suspended = false;
6023
6024 if (!HAS_RUNTIME_PM(dev))
6025 return;
6026
6027 pm_runtime_set_active(device);
6028
6029 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6030 pm_runtime_mark_last_busy(device);
6031 pm_runtime_use_autosuspend(device);
6032}
6033
6034void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6035{
6036 struct drm_device *dev = dev_priv->dev;
6037 struct device *device = &dev->pdev->dev;
6038
6039 if (!HAS_RUNTIME_PM(dev))
6040 return;
6041
6042 /* Make sure we're not suspended first. */
6043 pm_runtime_get_sync(device);
6044 pm_runtime_disable(device);
6045}
6046
1fa61106
ED		 6047/* Set up chip specific power management-related functions */
6048void intel_init_pm(struct drm_device *dev)
6049{
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051
6052 if (I915_HAS_FBC(dev)) {
40045465 6053 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6054 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6055 dev_priv->display.enable_fbc = gen7_enable_fbc;
6056 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6057 } else if (INTEL_INFO(dev)->gen >= 5) {
6058 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6059 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6060 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6061 } else if (IS_GM45(dev)) {
6062 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6063 dev_priv->display.enable_fbc = g4x_enable_fbc;
6064 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6065 } else {
1fa61106
ED		 6066 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6067 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6068 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6069 }
1fa61106
ED		 6070 }
6071
c921aba8
DV		 6072 /* For cxsr */
6073 if (IS_PINEVIEW(dev))
6074 i915_pineview_get_mem_freq(dev);
6075 else if (IS_GEN5(dev))
6076 i915_ironlake_get_mem_freq(dev);
6077
1fa61106
ED		 6078 /* For FIFO watermark updates */
6079 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 6080 intel_setup_wm_latency(dev);
6081
1fa61106 6082 if (IS_GEN5(dev)) {
53615a5e
VS		 6083 if (dev_priv->wm.pri_latency[1] &&
6084 dev_priv->wm.spr_latency[1] &&
6085 dev_priv->wm.cur_latency[1])
1fa61106
ED		 6086 dev_priv->display.update_wm = ironlake_update_wm;
6087 else {
6088 DRM_DEBUG_KMS("Failed to get proper latency. "
6089 "Disable CxSR\n");
6090 dev_priv->display.update_wm = NULL;
6091 }
6092 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6093 } else if (IS_GEN6(dev)) {
53615a5e
VS		 6094 if (dev_priv->wm.pri_latency[0] &&
6095 dev_priv->wm.spr_latency[0] &&
6096 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 6097 dev_priv->display.update_wm = sandybridge_update_wm;
6098 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6099 } else {
6100 DRM_DEBUG_KMS("Failed to read display plane latency. "
6101 "Disable CxSR\n");
6102 dev_priv->display.update_wm = NULL;
6103 }
6104 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6105 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 6106 if (dev_priv->wm.pri_latency[0] &&
6107 dev_priv->wm.spr_latency[0] &&
6108 dev_priv->wm.cur_latency[0]) {
c43d0188 6109 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 6110 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6111 } else {
6112 DRM_DEBUG_KMS("Failed to read display plane latency. "
6113 "Disable CxSR\n");
6114 dev_priv->display.update_wm = NULL;
6115 }
6116 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 6117 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 6118 if (dev_priv->wm.pri_latency[0] &&
6119 dev_priv->wm.spr_latency[0] &&
6120 dev_priv->wm.cur_latency[0]) {
1011d8c4 6121 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 6122 dev_priv->display.update_sprite_wm =
6123 haswell_update_sprite_wm;
6b8a5eeb
ED		 6124 } else {
6125 DRM_DEBUG_KMS("Failed to read display plane latency. "
6126 "Disable CxSR\n");
6127 dev_priv->display.update_wm = NULL;
6128 }
cad2a2d7 6129 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 6130 } else if (INTEL_INFO(dev)->gen == 8) {
6131 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6132 } else
6133 dev_priv->display.update_wm = NULL;
6134 } else if (IS_VALLEYVIEW(dev)) {
6135 dev_priv->display.update_wm = valleyview_update_wm;
6136 dev_priv->display.init_clock_gating =
6137 valleyview_init_clock_gating;
1fa61106
ED		 6138 } else if (IS_PINEVIEW(dev)) {
6139 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6140 dev_priv->is_ddr3,
6141 dev_priv->fsb_freq,
6142 dev_priv->mem_freq)) {
6143 DRM_INFO("failed to find known CxSR latency "
6144 "(found ddr%s fsb freq %d, mem freq %d), "
6145 "disabling CxSR\n",
6146 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6147 dev_priv->fsb_freq, dev_priv->mem_freq);
6148 /* Disable CxSR and never update its watermark again */
6149 pineview_disable_cxsr(dev);
6150 dev_priv->display.update_wm = NULL;
6151 } else
6152 dev_priv->display.update_wm = pineview_update_wm;
6153 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6154 } else if (IS_G4X(dev)) {
6155 dev_priv->display.update_wm = g4x_update_wm;
6156 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6157 } else if (IS_GEN4(dev)) {
6158 dev_priv->display.update_wm = i965_update_wm;
6159 if (IS_CRESTLINE(dev))
6160 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6161 else if (IS_BROADWATER(dev))
6162 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6163 } else if (IS_GEN3(dev)) {
6164 dev_priv->display.update_wm = i9xx_update_wm;
6165 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6166 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6167 } else if (IS_I865G(dev)) {
6168 dev_priv->display.update_wm = i830_update_wm;
6169 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6170 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6171 } else if (IS_I85X(dev)) {
6172 dev_priv->display.update_wm = i9xx_update_wm;
6173 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6174 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6175 } else {
6176 dev_priv->display.update_wm = i830_update_wm;
6177 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6178 if (IS_845G(dev))
6179 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6180 else
6181 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6182 }
6183}
6184
42c0526c
BW		 6185int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6186{
4fc688ce 6187 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6188
6189 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6190 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6191 return -EAGAIN;
6192 }
6193
6194 I915_WRITE(GEN6_PCODE_DATA, *val);
6195 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6196
6197 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6198 500)) {
6199 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6200 return -ETIMEDOUT;
6201 }
6202
6203 *val = I915_READ(GEN6_PCODE_DATA);
6204 I915_WRITE(GEN6_PCODE_DATA, 0);
6205
6206 return 0;
6207}
6208
6209int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6210{
4fc688ce 6211 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6212
6213 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6214 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6215 return -EAGAIN;
6216 }
6217
6218 I915_WRITE(GEN6_PCODE_DATA, val);
6219 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6220
6221 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6222 500)) {
6223 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6224 return -ETIMEDOUT;
6225 }
6226
6227 I915_WRITE(GEN6_PCODE_DATA, 0);
6228
6229 return 0;
6230}
a0e4e199 6231
2ec3815f 6232int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6233{
07ab118b 6234 int div;
855ba3be 6235
07ab118b 6236 /* 4 x czclk */
2ec3815f 6237 switch (dev_priv->mem_freq) {
855ba3be 6238 case 800:
07ab118b 6239 div = 10;
855ba3be
JB		 6240 break;
6241 case 1066:
07ab118b 6242 div = 12;
855ba3be
JB		 6243 break;
6244 case 1333:
07ab118b 6245 div = 16;
855ba3be
JB		 6246 break;
6247 default:
6248 return -1;
6249 }
6250
2ec3815f 6251 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6252}
6253
2ec3815f 6254int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6255{
07ab118b 6256 int mul;
855ba3be 6257
07ab118b 6258 /* 4 x czclk */
2ec3815f 6259 switch (dev_priv->mem_freq) {
855ba3be 6260 case 800:
07ab118b 6261 mul = 10;
855ba3be
JB		 6262 break;
6263 case 1066:
07ab118b 6264 mul = 12;
855ba3be
JB		 6265 break;
6266 case 1333:
07ab118b 6267 mul = 16;
855ba3be
JB		 6268 break;
6269 default:
6270 return -1;
6271 }
6272
2ec3815f 6273 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6274}
6275
907b28c5
CW		 6276void intel_pm_init(struct drm_device *dev)
6277{
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279
6280 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6281 intel_gen6_powersave_work);
6282}
ubuntu-bionic-kernel mirror