]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/skl+: Remove minimum block allocation from crtc state.
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
b033bb6d 59static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 60{
32608ca2
ID		 61 struct drm_i915_private *dev_priv = dev->dev_private;
62
b033bb6d 63 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 64 I915_WRITE(CHICKEN_PAR1_1,
65 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
66
b033bb6d
MK		 67 I915_WRITE(GEN8_CONFIG0,
68 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 69
70 /* WaEnableChickenDCPR:skl,bxt,kbl */
71 I915_WRITE(GEN8_CHICKEN_DCPR_1,
72 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 73
74 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 75 /* WaFbcWakeMemOn:skl,bxt,kbl */
76 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
77 DISP_FBC_WM_DIS |
78 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 79
80 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
81 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
82 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 83}
84
85static void bxt_init_clock_gating(struct drm_device *dev)
86{
fac5e23e 87 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 88
89 gen9_init_clock_gating(dev);
90
a7546159
NH		 91 /* WaDisableSDEUnitClockGating:bxt */
92 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
93 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
94
32608ca2
ID		 95 /*
96 * FIXME:
868434c5 97 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 98 */
32608ca2 99 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 100 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 101
102 /*
103 * Wa: Backlight PWM may stop in the asserted state, causing backlight
104 * to stay fully on.
105 */
106 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
107 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
108 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 109}
110
c921aba8
DV		 111static void i915_pineview_get_mem_freq(struct drm_device *dev)
112{
fac5e23e 113 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 114 u32 tmp;
115
116 tmp = I915_READ(CLKCFG);
117
118 switch (tmp & CLKCFG_FSB_MASK) {
119 case CLKCFG_FSB_533:
120 dev_priv->fsb_freq = 533; /* 133*4 */
121 break;
122 case CLKCFG_FSB_800:
123 dev_priv->fsb_freq = 800; /* 200*4 */
124 break;
125 case CLKCFG_FSB_667:
126 dev_priv->fsb_freq = 667; /* 167*4 */
127 break;
128 case CLKCFG_FSB_400:
129 dev_priv->fsb_freq = 400; /* 100*4 */
130 break;
131 }
132
133 switch (tmp & CLKCFG_MEM_MASK) {
134 case CLKCFG_MEM_533:
135 dev_priv->mem_freq = 533;
136 break;
137 case CLKCFG_MEM_667:
138 dev_priv->mem_freq = 667;
139 break;
140 case CLKCFG_MEM_800:
141 dev_priv->mem_freq = 800;
142 break;
143 }
144
145 /* detect pineview DDR3 setting */
146 tmp = I915_READ(CSHRDDR3CTL);
147 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
148}
149
150static void i915_ironlake_get_mem_freq(struct drm_device *dev)
151{
fac5e23e 152 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 153 u16 ddrpll, csipll;
154
155 ddrpll = I915_READ16(DDRMPLL1);
156 csipll = I915_READ16(CSIPLL0);
157
158 switch (ddrpll & 0xff) {
159 case 0xc:
160 dev_priv->mem_freq = 800;
161 break;
162 case 0x10:
163 dev_priv->mem_freq = 1066;
164 break;
165 case 0x14:
166 dev_priv->mem_freq = 1333;
167 break;
168 case 0x18:
169 dev_priv->mem_freq = 1600;
170 break;
171 default:
172 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
173 ddrpll & 0xff);
174 dev_priv->mem_freq = 0;
175 break;
176 }
177
20e4d407 178 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 179
180 switch (csipll & 0x3ff) {
181 case 0x00c:
182 dev_priv->fsb_freq = 3200;
183 break;
184 case 0x00e:
185 dev_priv->fsb_freq = 3733;
186 break;
187 case 0x010:
188 dev_priv->fsb_freq = 4266;
189 break;
190 case 0x012:
191 dev_priv->fsb_freq = 4800;
192 break;
193 case 0x014:
194 dev_priv->fsb_freq = 5333;
195 break;
196 case 0x016:
197 dev_priv->fsb_freq = 5866;
198 break;
199 case 0x018:
200 dev_priv->fsb_freq = 6400;
201 break;
202 default:
203 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
204 csipll & 0x3ff);
205 dev_priv->fsb_freq = 0;
206 break;
207 }
208
209 if (dev_priv->fsb_freq == 3200) {
20e4d407 210 dev_priv->ips.c_m = 0;
c921aba8 211 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 212 dev_priv->ips.c_m = 1;
c921aba8 213 } else {
20e4d407 214 dev_priv->ips.c_m = 2;
c921aba8
DV		 215 }
216}
217
b445e3b0
ED		 218static const struct cxsr_latency cxsr_latency_table[] = {
219 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
220 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
221 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
222 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
223 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
224
225 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
226 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
227 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
228 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
229 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
230
231 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
232 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
233 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
234 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
235 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
236
237 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
238 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
239 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
240 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
241 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
242
243 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
244 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
245 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
246 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
247 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
248
249 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
250 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
251 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
252 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
253 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
254};
255
44a655ca
TU		 256static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
257 bool is_ddr3,
b445e3b0
ED		 258 int fsb,
259 int mem)
260{
261 const struct cxsr_latency *latency;
262 int i;
263
264 if (fsb == 0 || mem == 0)
265 return NULL;
266
267 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
268 latency = &cxsr_latency_table[i];
269 if (is_desktop == latency->is_desktop &&
270 is_ddr3 == latency->is_ddr3 &&
271 fsb == latency->fsb_freq && mem == latency->mem_freq)
272 return latency;
273 }
274
275 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
276
277 return NULL;
278}
279
fc1ac8de
VS		 280static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
281{
282 u32 val;
283
284 mutex_lock(&dev_priv->rps.hw_lock);
285
286 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
287 if (enable)
288 val &= ~FORCE_DDR_HIGH_FREQ;
289 else
290 val |= FORCE_DDR_HIGH_FREQ;
291 val &= ~FORCE_DDR_LOW_FREQ;
292 val |= FORCE_DDR_FREQ_REQ_ACK;
293 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
294
295 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
296 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
297 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
298
299 mutex_unlock(&dev_priv->rps.hw_lock);
300}
301
cfb41411
VS		 302static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
303{
304 u32 val;
305
306 mutex_lock(&dev_priv->rps.hw_lock);
307
308 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
309 if (enable)
310 val |= DSP_MAXFIFO_PM5_ENABLE;
311 else
312 val &= ~DSP_MAXFIFO_PM5_ENABLE;
313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
314
315 mutex_unlock(&dev_priv->rps.hw_lock);
316}
317
f4998963
VS		 318#define FW_WM(value, plane) \
319 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
320
5209b1f4 321void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 322{
91c8a326 323 struct drm_device *dev = &dev_priv->drm;
5209b1f4 324 u32 val;
b445e3b0 325
920a14b2 326 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 327 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 328 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 329 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 330 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 331 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 332 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 333 } else if (IS_PINEVIEW(dev)) {
334 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
335 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
336 I915_WRITE(DSPFW3, val);
a7a6c498 337 POSTING_READ(DSPFW3);
50a0bc90 338 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 339 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
340 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
341 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 342 POSTING_READ(FW_BLC_SELF);
50a0bc90 343 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 344 /*
345 * FIXME can't find a bit like this for 915G, and
346 * and yet it does have the related watermark in
347 * FW_BLC_SELF. What's going on?
348 */
5209b1f4
ID		 349 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
350 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
351 I915_WRITE(INSTPM, val);
a7a6c498 352 POSTING_READ(INSTPM);
5209b1f4
ID		 353 } else {
354 return;
355 }
b445e3b0 356
5209b1f4
ID		 357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
b445e3b0
ED		 359}
360
fc1ac8de 361
b445e3b0
ED		 362/*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
5aef6003 376static const int pessimal_latency_ns = 5000;
b445e3b0 377
b5004720
VS		 378#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383{
fac5e23e 384 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431}
432
1fa61106 433static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 434{
fac5e23e 435 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447}
448
feb56b93 449static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 450{
fac5e23e 451 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
1fa61106 466static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 467{
fac5e23e 468 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480}
481
b445e3b0
ED		 482/* Pineview has different values for various configs */
483static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 524};
b445e3b0 525static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 526 .fifo_size = I965_CURSOR_FIFO,
527 .max_wm = I965_CURSOR_MAX_WM,
528 .default_wm = I965_CURSOR_DFT_WM,
529 .guard_size = 2,
530 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 533 .fifo_size = I945_FIFO_SIZE,
534 .max_wm = I915_MAX_WM,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 538};
539static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 540 .fifo_size = I915_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 545};
9d539105 546static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 547 .fifo_size = I855GM_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 552};
9d539105
VS		 553static const struct intel_watermark_params i830_bc_wm_info = {
554 .fifo_size = I855GM_FIFO_SIZE,
555 .max_wm = I915_MAX_WM/2,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I830_FIFO_LINE_SIZE,
559};
feb56b93 560static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 561 .fifo_size = I830_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 566};
567
b445e3b0
ED		 568/**
569 * intel_calculate_wm - calculate watermark level
570 * @clock_in_khz: pixel clock
571 * @wm: chip FIFO params
ac484963 572 * @cpp: bytes per pixel
b445e3b0
ED		 573 * @latency_ns: memory latency for the platform
574 *
575 * Calculate the watermark level (the level at which the display plane will
576 * start fetching from memory again). Each chip has a different display
577 * FIFO size and allocation, so the caller needs to figure that out and pass
578 * in the correct intel_watermark_params structure.
579 *
580 * As the pixel clock runs, the FIFO will be drained at a rate that depends
581 * on the pixel size. When it reaches the watermark level, it'll start
582 * fetching FIFO line sized based chunks from memory until the FIFO fills
583 * past the watermark point. If the FIFO drains completely, a FIFO underrun
584 * will occur, and a display engine hang could result.
585 */
586static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
587 const struct intel_watermark_params *wm,
ac484963 588 int fifo_size, int cpp,
b445e3b0
ED		 589 unsigned long latency_ns)
590{
591 long entries_required, wm_size;
592
593 /*
594 * Note: we need to make sure we don't overflow for various clock &
595 * latency values.
596 * clocks go from a few thousand to several hundred thousand.
597 * latency is usually a few thousand
598 */
ac484963 599 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 600 1000;
601 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
602
603 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
604
605 wm_size = fifo_size - (entries_required + wm->guard_size);
606
607 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
608
609 /* Don't promote wm_size to unsigned... */
610 if (wm_size > (long)wm->max_wm)
611 wm_size = wm->max_wm;
612 if (wm_size <= 0)
613 wm_size = wm->default_wm;
d6feb196
VS		 614
615 /*
616 * Bspec seems to indicate that the value shouldn't be lower than
617 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
618 * Lets go for 8 which is the burst size since certain platforms
619 * already use a hardcoded 8 (which is what the spec says should be
620 * done).
621 */
622 if (wm_size <= 8)
623 wm_size = 8;
624
b445e3b0
ED		 625 return wm_size;
626}
627
628static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
629{
630 struct drm_crtc *crtc, *enabled = NULL;
631
70e1e0ec 632 for_each_crtc(dev, crtc) {
3490ea5d 633 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 634 if (enabled)
635 return NULL;
636 enabled = crtc;
637 }
638 }
639
640 return enabled;
641}
642
46ba614c 643static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 644{
46ba614c 645 struct drm_device *dev = unused_crtc->dev;
fac5e23e 646 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 647 struct drm_crtc *crtc;
648 const struct cxsr_latency *latency;
649 u32 reg;
650 unsigned long wm;
651
50a0bc90
TU		 652 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
653 dev_priv->is_ddr3,
654 dev_priv->fsb_freq,
655 dev_priv->mem_freq);
b445e3b0
ED		 656 if (!latency) {
657 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 658 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 659 return;
660 }
661
662 crtc = single_enabled_crtc(dev);
663 if (crtc) {
7c5f93b0 664 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 665 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 666 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 667
668 /* Display SR */
669 wm = intel_calculate_wm(clock, &pineview_display_wm,
670 pineview_display_wm.fifo_size,
ac484963 671 cpp, latency->display_sr);
b445e3b0
ED		 672 reg = I915_READ(DSPFW1);
673 reg &= ~DSPFW_SR_MASK;
f4998963 674 reg |= FW_WM(wm, SR);
b445e3b0
ED		 675 I915_WRITE(DSPFW1, reg);
676 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
677
678 /* cursor SR */
679 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
680 pineview_display_wm.fifo_size,
ac484963 681 cpp, latency->cursor_sr);
b445e3b0
ED		 682 reg = I915_READ(DSPFW3);
683 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 684 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 685 I915_WRITE(DSPFW3, reg);
686
687 /* Display HPLL off SR */
688 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
689 pineview_display_hplloff_wm.fifo_size,
ac484963 690 cpp, latency->display_hpll_disable);
b445e3b0
ED		 691 reg = I915_READ(DSPFW3);
692 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 693 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 694 I915_WRITE(DSPFW3, reg);
695
696 /* cursor HPLL off SR */
697 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
698 pineview_display_hplloff_wm.fifo_size,
ac484963 699 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 700 reg = I915_READ(DSPFW3);
701 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 702 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 703 I915_WRITE(DSPFW3, reg);
704 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
705
5209b1f4 706 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 707 } else {
5209b1f4 708 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 709 }
710}
711
712static bool g4x_compute_wm0(struct drm_device *dev,
713 int plane,
714 const struct intel_watermark_params *display,
715 int display_latency_ns,
716 const struct intel_watermark_params *cursor,
717 int cursor_latency_ns,
718 int *plane_wm,
719 int *cursor_wm)
720{
721 struct drm_crtc *crtc;
4fe8590a 722 const struct drm_display_mode *adjusted_mode;
ac484963 723 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 724 int line_time_us, line_count;
725 int entries, tlb_miss;
726
727 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 728 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 729 *cursor_wm = cursor->guard_size;
730 *plane_wm = display->guard_size;
731 return false;
732 }
733
6e3c9717 734 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 735 clock = adjusted_mode->crtc_clock;
fec8cba3 736 htotal = adjusted_mode->crtc_htotal;
6e3c9717 737 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 738 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 739
740 /* Use the small buffer method to calculate plane watermark */
ac484963 741 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 742 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
743 if (tlb_miss > 0)
744 entries += tlb_miss;
745 entries = DIV_ROUND_UP(entries, display->cacheline_size);
746 *plane_wm = entries + display->guard_size;
747 if (*plane_wm > (int)display->max_wm)
748 *plane_wm = display->max_wm;
749
750 /* Use the large buffer method to calculate cursor watermark */
922044c9 751 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 752 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 753 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 754 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
755 if (tlb_miss > 0)
756 entries += tlb_miss;
757 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
758 *cursor_wm = entries + cursor->guard_size;
759 if (*cursor_wm > (int)cursor->max_wm)
760 *cursor_wm = (int)cursor->max_wm;
761
762 return true;
763}
764
765/*
766 * Check the wm result.
767 *
768 * If any calculated watermark values is larger than the maximum value that
769 * can be programmed into the associated watermark register, that watermark
770 * must be disabled.
771 */
772static bool g4x_check_srwm(struct drm_device *dev,
773 int display_wm, int cursor_wm,
774 const struct intel_watermark_params *display,
775 const struct intel_watermark_params *cursor)
776{
777 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
778 display_wm, cursor_wm);
779
780 if (display_wm > display->max_wm) {
ae9400ca 781 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 782 display_wm, display->max_wm);
783 return false;
784 }
785
786 if (cursor_wm > cursor->max_wm) {
ae9400ca 787 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 788 cursor_wm, cursor->max_wm);
789 return false;
790 }
791
792 if (!(display_wm || cursor_wm)) {
793 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
794 return false;
795 }
796
797 return true;
798}
799
800static bool g4x_compute_srwm(struct drm_device *dev,
801 int plane,
802 int latency_ns,
803 const struct intel_watermark_params *display,
804 const struct intel_watermark_params *cursor,
805 int *display_wm, int *cursor_wm)
806{
807 struct drm_crtc *crtc;
4fe8590a 808 const struct drm_display_mode *adjusted_mode;
ac484963 809 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 810 unsigned long line_time_us;
811 int line_count, line_size;
812 int small, large;
813 int entries;
814
815 if (!latency_ns) {
816 *display_wm = *cursor_wm = 0;
817 return false;
818 }
819
820 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 821 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 822 clock = adjusted_mode->crtc_clock;
fec8cba3 823 htotal = adjusted_mode->crtc_htotal;
6e3c9717 824 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 825 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 826
922044c9 827 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 828 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 829 line_size = hdisplay * cpp;
b445e3b0
ED		 830
831 /* Use the minimum of the small and large buffer method for primary */
ac484963 832 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 833 large = line_count * line_size;
834
835 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
836 *display_wm = entries + display->guard_size;
837
838 /* calculate the self-refresh watermark for display cursor */
ac484963 839 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 840 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
841 *cursor_wm = entries + cursor->guard_size;
842
843 return g4x_check_srwm(dev,
844 *display_wm, *cursor_wm,
845 display, cursor);
846}
847
15665979
VS		 848#define FW_WM_VLV(value, plane) \
849 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
850
0018fda1
VS		 851static void vlv_write_wm_values(struct intel_crtc *crtc,
852 const struct vlv_wm_values *wm)
853{
854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
855 enum pipe pipe = crtc->pipe;
856
857 I915_WRITE(VLV_DDL(pipe),
858 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
859 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
860 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
861 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
862
ae80152d 863 I915_WRITE(DSPFW1,
15665979
VS		 864 FW_WM(wm->sr.plane, SR) |
865 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
866 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
867 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 868 I915_WRITE(DSPFW2,
15665979
VS		 869 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
870 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
871 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 872 I915_WRITE(DSPFW3,
15665979 873 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 874
875 if (IS_CHERRYVIEW(dev_priv)) {
876 I915_WRITE(DSPFW7_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
878 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 879 I915_WRITE(DSPFW8_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
881 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 882 I915_WRITE(DSPFW9_CHV,
15665979
VS		 883 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
884 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 885 I915_WRITE(DSPHOWM,
15665979
VS		 886 FW_WM(wm->sr.plane >> 9, SR_HI) |
887 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
888 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
889 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
891 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
892 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
894 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
895 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 896 } else {
897 I915_WRITE(DSPFW7,
15665979
VS		 898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
899 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 900 I915_WRITE(DSPHOWM,
15665979
VS		 901 FW_WM(wm->sr.plane >> 9, SR_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
903 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
904 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
906 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
907 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 908 }
909
2cb389b7
VS		 910 /* zero (unused) WM1 watermarks */
911 I915_WRITE(DSPFW4, 0);
912 I915_WRITE(DSPFW5, 0);
913 I915_WRITE(DSPFW6, 0);
914 I915_WRITE(DSPHOWM1, 0);
915
ae80152d 916 POSTING_READ(DSPFW1);
0018fda1
VS		 917}
918
15665979
VS		 919#undef FW_WM_VLV
920
6eb1a681
VS		 921enum vlv_wm_level {
922 VLV_WM_LEVEL_PM2,
923 VLV_WM_LEVEL_PM5,
924 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 925};
926
262cd2e1
VS		 927/* latency must be in 0.1us units. */
928static unsigned int vlv_wm_method2(unsigned int pixel_rate,
929 unsigned int pipe_htotal,
930 unsigned int horiz_pixels,
ac484963 931 unsigned int cpp,
262cd2e1
VS		 932 unsigned int latency)
933{
934 unsigned int ret;
935
936 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 937 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 938 ret = DIV_ROUND_UP(ret, 64);
939
940 return ret;
941}
942
943static void vlv_setup_wm_latency(struct drm_device *dev)
944{
fac5e23e 945 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 946
947 /* all latencies in usec */
948 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
949
58590c14
VS		 950 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
951
262cd2e1
VS		 952 if (IS_CHERRYVIEW(dev_priv)) {
953 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
954 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 955
956 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 957 }
958}
959
960static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
961 struct intel_crtc *crtc,
962 const struct intel_plane_state *state,
963 int level)
964{
965 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 966 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 967
968 if (dev_priv->wm.pri_latency[level] == 0)
969 return USHRT_MAX;
970
936e71e3 971 if (!state->base.visible)
262cd2e1
VS		 972 return 0;
973
ac484963 974 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 975 clock = crtc->config->base.adjusted_mode.crtc_clock;
976 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
977 width = crtc->config->pipe_src_w;
978 if (WARN_ON(htotal == 0))
979 htotal = 1;
980
981 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
982 /*
983 * FIXME the formula gives values that are
984 * too big for the cursor FIFO, and hence we
985 * would never be able to use cursors. For
986 * now just hardcode the watermark.
987 */
988 wm = 63;
989 } else {
ac484963 990 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 991 dev_priv->wm.pri_latency[level] * 10);
992 }
993
994 return min_t(int, wm, USHRT_MAX);
995}
996
54f1b6e1
VS		 997static void vlv_compute_fifo(struct intel_crtc *crtc)
998{
999 struct drm_device *dev = crtc->base.dev;
1000 struct vlv_wm_state *wm_state = &crtc->wm_state;
1001 struct intel_plane *plane;
1002 unsigned int total_rate = 0;
1003 const int fifo_size = 512 - 1;
1004 int fifo_extra, fifo_left = fifo_size;
1005
1006 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1007 struct intel_plane_state *state =
1008 to_intel_plane_state(plane->base.state);
1009
1010 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1011 continue;
1012
936e71e3 1013 if (state->base.visible) {
54f1b6e1
VS		 1014 wm_state->num_active_planes++;
1015 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1016 }
1017 }
1018
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 struct intel_plane_state *state =
1021 to_intel_plane_state(plane->base.state);
1022 unsigned int rate;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1025 plane->wm.fifo_size = 63;
1026 continue;
1027 }
1028
936e71e3 1029 if (!state->base.visible) {
54f1b6e1
VS		 1030 plane->wm.fifo_size = 0;
1031 continue;
1032 }
1033
1034 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1035 plane->wm.fifo_size = fifo_size * rate / total_rate;
1036 fifo_left -= plane->wm.fifo_size;
1037 }
1038
1039 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1040
1041 /* spread the remainder evenly */
1042 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043 int plane_extra;
1044
1045 if (fifo_left == 0)
1046 break;
1047
1048 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1049 continue;
1050
1051 /* give it all to the first plane if none are active */
1052 if (plane->wm.fifo_size == 0 &&
1053 wm_state->num_active_planes)
1054 continue;
1055
1056 plane_extra = min(fifo_extra, fifo_left);
1057 plane->wm.fifo_size += plane_extra;
1058 fifo_left -= plane_extra;
1059 }
1060
1061 WARN_ON(fifo_left != 0);
1062}
1063
262cd2e1
VS		 1064static void vlv_invert_wms(struct intel_crtc *crtc)
1065{
1066 struct vlv_wm_state *wm_state = &crtc->wm_state;
1067 int level;
1068
1069 for (level = 0; level < wm_state->num_levels; level++) {
1070 struct drm_device *dev = crtc->base.dev;
1071 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 struct intel_plane *plane;
1073
1074 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1075 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1076
1077 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1078 switch (plane->base.type) {
1079 int sprite;
1080 case DRM_PLANE_TYPE_CURSOR:
1081 wm_state->wm[level].cursor = plane->wm.fifo_size -
1082 wm_state->wm[level].cursor;
1083 break;
1084 case DRM_PLANE_TYPE_PRIMARY:
1085 wm_state->wm[level].primary = plane->wm.fifo_size -
1086 wm_state->wm[level].primary;
1087 break;
1088 case DRM_PLANE_TYPE_OVERLAY:
1089 sprite = plane->plane;
1090 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1091 wm_state->wm[level].sprite[sprite];
1092 break;
1093 }
1094 }
1095 }
1096}
1097
26e1fe4f 1098static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1099{
1100 struct drm_device *dev = crtc->base.dev;
1101 struct vlv_wm_state *wm_state = &crtc->wm_state;
1102 struct intel_plane *plane;
1103 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1104 int level;
1105
1106 memset(wm_state, 0, sizeof(*wm_state));
1107
852eb00d 1108 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1109 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1110
1111 wm_state->num_active_planes = 0;
262cd2e1 1112
54f1b6e1 1113 vlv_compute_fifo(crtc);
262cd2e1
VS		 1114
1115 if (wm_state->num_active_planes != 1)
1116 wm_state->cxsr = false;
1117
1118 if (wm_state->cxsr) {
1119 for (level = 0; level < wm_state->num_levels; level++) {
1120 wm_state->sr[level].plane = sr_fifo_size;
1121 wm_state->sr[level].cursor = 63;
1122 }
1123 }
1124
1125 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1126 struct intel_plane_state *state =
1127 to_intel_plane_state(plane->base.state);
1128
936e71e3 1129 if (!state->base.visible)
262cd2e1
VS		 1130 continue;
1131
1132 /* normal watermarks */
1133 for (level = 0; level < wm_state->num_levels; level++) {
1134 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1135 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1136
1137 /* hack */
1138 if (WARN_ON(level == 0 && wm > max_wm))
1139 wm = max_wm;
1140
1141 if (wm > plane->wm.fifo_size)
1142 break;
1143
1144 switch (plane->base.type) {
1145 int sprite;
1146 case DRM_PLANE_TYPE_CURSOR:
1147 wm_state->wm[level].cursor = wm;
1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 wm_state->wm[level].primary = wm;
1151 break;
1152 case DRM_PLANE_TYPE_OVERLAY:
1153 sprite = plane->plane;
1154 wm_state->wm[level].sprite[sprite] = wm;
1155 break;
1156 }
1157 }
1158
1159 wm_state->num_levels = level;
1160
1161 if (!wm_state->cxsr)
1162 continue;
1163
1164 /* maxfifo watermarks */
1165 switch (plane->base.type) {
1166 int sprite, level;
1167 case DRM_PLANE_TYPE_CURSOR:
1168 for (level = 0; level < wm_state->num_levels; level++)
1169 wm_state->sr[level].cursor =
5a37ed0a 1170 wm_state->wm[level].cursor;
262cd2e1
VS		 1171 break;
1172 case DRM_PLANE_TYPE_PRIMARY:
1173 for (level = 0; level < wm_state->num_levels; level++)
1174 wm_state->sr[level].plane =
1175 min(wm_state->sr[level].plane,
1176 wm_state->wm[level].primary);
1177 break;
1178 case DRM_PLANE_TYPE_OVERLAY:
1179 sprite = plane->plane;
1180 for (level = 0; level < wm_state->num_levels; level++)
1181 wm_state->sr[level].plane =
1182 min(wm_state->sr[level].plane,
1183 wm_state->wm[level].sprite[sprite]);
1184 break;
1185 }
1186 }
1187
1188 /* clear any (partially) filled invalid levels */
58590c14 1189 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1190 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1191 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1192 }
1193
1194 vlv_invert_wms(crtc);
1195}
1196
54f1b6e1
VS		 1197#define VLV_FIFO(plane, value) \
1198 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1199
1200static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1201{
1202 struct drm_device *dev = crtc->base.dev;
1203 struct drm_i915_private *dev_priv = to_i915(dev);
1204 struct intel_plane *plane;
1205 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1206
1207 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1208 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1209 WARN_ON(plane->wm.fifo_size != 63);
1210 continue;
1211 }
1212
1213 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1214 sprite0_start = plane->wm.fifo_size;
1215 else if (plane->plane == 0)
1216 sprite1_start = sprite0_start + plane->wm.fifo_size;
1217 else
1218 fifo_size = sprite1_start + plane->wm.fifo_size;
1219 }
1220
1221 WARN_ON(fifo_size != 512 - 1);
1222
1223 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1224 pipe_name(crtc->pipe), sprite0_start,
1225 sprite1_start, fifo_size);
1226
1227 switch (crtc->pipe) {
1228 uint32_t dsparb, dsparb2, dsparb3;
1229 case PIPE_A:
1230 dsparb = I915_READ(DSPARB);
1231 dsparb2 = I915_READ(DSPARB2);
1232
1233 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1234 VLV_FIFO(SPRITEB, 0xff));
1235 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1236 VLV_FIFO(SPRITEB, sprite1_start));
1237
1238 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1239 VLV_FIFO(SPRITEB_HI, 0x1));
1240 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1241 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1242
1243 I915_WRITE(DSPARB, dsparb);
1244 I915_WRITE(DSPARB2, dsparb2);
1245 break;
1246 case PIPE_B:
1247 dsparb = I915_READ(DSPARB);
1248 dsparb2 = I915_READ(DSPARB2);
1249
1250 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1251 VLV_FIFO(SPRITED, 0xff));
1252 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1253 VLV_FIFO(SPRITED, sprite1_start));
1254
1255 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1256 VLV_FIFO(SPRITED_HI, 0xff));
1257 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1258 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1259
1260 I915_WRITE(DSPARB, dsparb);
1261 I915_WRITE(DSPARB2, dsparb2);
1262 break;
1263 case PIPE_C:
1264 dsparb3 = I915_READ(DSPARB3);
1265 dsparb2 = I915_READ(DSPARB2);
1266
1267 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1268 VLV_FIFO(SPRITEF, 0xff));
1269 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1270 VLV_FIFO(SPRITEF, sprite1_start));
1271
1272 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1273 VLV_FIFO(SPRITEF_HI, 0xff));
1274 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1275 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1276
1277 I915_WRITE(DSPARB3, dsparb3);
1278 I915_WRITE(DSPARB2, dsparb2);
1279 break;
1280 default:
1281 break;
1282 }
1283}
1284
1285#undef VLV_FIFO
1286
262cd2e1
VS		 1287static void vlv_merge_wm(struct drm_device *dev,
1288 struct vlv_wm_values *wm)
1289{
1290 struct intel_crtc *crtc;
1291 int num_active_crtcs = 0;
1292
58590c14 1293 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1294 wm->cxsr = true;
1295
1296 for_each_intel_crtc(dev, crtc) {
1297 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1298
1299 if (!crtc->active)
1300 continue;
1301
1302 if (!wm_state->cxsr)
1303 wm->cxsr = false;
1304
1305 num_active_crtcs++;
1306 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1307 }
1308
1309 if (num_active_crtcs != 1)
1310 wm->cxsr = false;
1311
6f9c784b
VS		 1312 if (num_active_crtcs > 1)
1313 wm->level = VLV_WM_LEVEL_PM2;
1314
262cd2e1
VS		 1315 for_each_intel_crtc(dev, crtc) {
1316 struct vlv_wm_state *wm_state = &crtc->wm_state;
1317 enum pipe pipe = crtc->pipe;
1318
1319 if (!crtc->active)
1320 continue;
1321
1322 wm->pipe[pipe] = wm_state->wm[wm->level];
1323 if (wm->cxsr)
1324 wm->sr = wm_state->sr[wm->level];
1325
1326 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1329 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1330 }
1331}
1332
1333static void vlv_update_wm(struct drm_crtc *crtc)
1334{
1335 struct drm_device *dev = crtc->dev;
fac5e23e 1336 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1338 enum pipe pipe = intel_crtc->pipe;
1339 struct vlv_wm_values wm = {};
1340
26e1fe4f 1341 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1342 vlv_merge_wm(dev, &wm);
1343
54f1b6e1
VS		 1344 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1345 /* FIXME should be part of crtc atomic commit */
1346 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1347 return;
54f1b6e1 1348 }
262cd2e1
VS		 1349
1350 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1351 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1352 chv_set_memory_dvfs(dev_priv, false);
1353
1354 if (wm.level < VLV_WM_LEVEL_PM5 &&
1355 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1356 chv_set_memory_pm5(dev_priv, false);
1357
852eb00d 1358 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1359 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1360
54f1b6e1
VS		 1361 /* FIXME should be part of crtc atomic commit */
1362 vlv_pipe_set_fifo_size(intel_crtc);
1363
262cd2e1
VS		 1364 vlv_write_wm_values(intel_crtc, &wm);
1365
1366 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1367 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1368 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1369 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1370 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1371
852eb00d 1372 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1373 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1374
1375 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1376 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1377 chv_set_memory_pm5(dev_priv, true);
1378
1379 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1380 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1381 chv_set_memory_dvfs(dev_priv, true);
1382
1383 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1384}
1385
ae80152d
VS		 1386#define single_plane_enabled(mask) is_power_of_2(mask)
1387
46ba614c 1388static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1389{
46ba614c 1390 struct drm_device *dev = crtc->dev;
b445e3b0 1391 static const int sr_latency_ns = 12000;
fac5e23e 1392 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1393 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1394 int plane_sr, cursor_sr;
1395 unsigned int enabled = 0;
9858425c 1396 bool cxsr_enabled;
b445e3b0 1397
51cea1f4 1398 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1399 &g4x_wm_info, pessimal_latency_ns,
1400 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1401 &planea_wm, &cursora_wm))
51cea1f4 1402 enabled |= 1 << PIPE_A;
b445e3b0 1403
51cea1f4 1404 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1405 &g4x_wm_info, pessimal_latency_ns,
1406 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1407 &planeb_wm, &cursorb_wm))
51cea1f4 1408 enabled |= 1 << PIPE_B;
b445e3b0 1409
b445e3b0
ED		 1410 if (single_plane_enabled(enabled) &&
1411 g4x_compute_srwm(dev, ffs(enabled) - 1,
1412 sr_latency_ns,
1413 &g4x_wm_info,
1414 &g4x_cursor_wm_info,
52bd02d8 1415 &plane_sr, &cursor_sr)) {
9858425c 1416 cxsr_enabled = true;
52bd02d8 1417 } else {
9858425c 1418 cxsr_enabled = false;
5209b1f4 1419 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1420 plane_sr = cursor_sr = 0;
1421 }
b445e3b0 1422
a5043453
VS		 1423 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1424 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1425 planea_wm, cursora_wm,
1426 planeb_wm, cursorb_wm,
1427 plane_sr, cursor_sr);
1428
1429 I915_WRITE(DSPFW1,
f4998963
VS		 1430 FW_WM(plane_sr, SR) |
1431 FW_WM(cursorb_wm, CURSORB) |
1432 FW_WM(planeb_wm, PLANEB) |
1433 FW_WM(planea_wm, PLANEA));
b445e3b0 1434 I915_WRITE(DSPFW2,
8c919b28 1435 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1436 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1437 /* HPLL off in SR has some issues on G4x... disable it */
1438 I915_WRITE(DSPFW3,
8c919b28 1439 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1440 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1441
1442 if (cxsr_enabled)
1443 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1444}
1445
46ba614c 1446static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1447{
46ba614c 1448 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1449 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1450 struct drm_crtc *crtc;
1451 int srwm = 1;
1452 int cursor_sr = 16;
9858425c 1453 bool cxsr_enabled;
b445e3b0
ED		 1454
1455 /* Calc sr entries for one plane configs */
1456 crtc = single_enabled_crtc(dev);
1457 if (crtc) {
1458 /* self-refresh has much higher latency */
1459 static const int sr_latency_ns = 12000;
124abe07 1460 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1461 int clock = adjusted_mode->crtc_clock;
fec8cba3 1462 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1463 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1464 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1465 unsigned long line_time_us;
1466 int entries;
1467
922044c9 1468 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1469
1470 /* Use ns/us then divide to preserve precision */
1471 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1472 cpp * hdisplay;
b445e3b0
ED		 1473 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1474 srwm = I965_FIFO_SIZE - entries;
1475 if (srwm < 0)
1476 srwm = 1;
1477 srwm &= 0x1ff;
1478 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1479 entries, srwm);
1480
1481 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1482 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1483 entries = DIV_ROUND_UP(entries,
1484 i965_cursor_wm_info.cacheline_size);
1485 cursor_sr = i965_cursor_wm_info.fifo_size -
1486 (entries + i965_cursor_wm_info.guard_size);
1487
1488 if (cursor_sr > i965_cursor_wm_info.max_wm)
1489 cursor_sr = i965_cursor_wm_info.max_wm;
1490
1491 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1492 "cursor %d\n", srwm, cursor_sr);
1493
9858425c 1494 cxsr_enabled = true;
b445e3b0 1495 } else {
9858425c 1496 cxsr_enabled = false;
b445e3b0 1497 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1498 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1499 }
1500
1501 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1502 srwm);
1503
1504 /* 965 has limitations... */
f4998963
VS		 1505 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1506 FW_WM(8, CURSORB) |
1507 FW_WM(8, PLANEB) |
1508 FW_WM(8, PLANEA));
1509 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1510 FW_WM(8, PLANEC_OLD));
b445e3b0 1511 /* update cursor SR watermark */
f4998963 1512 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1513
1514 if (cxsr_enabled)
1515 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1516}
1517
f4998963
VS		 1518#undef FW_WM
1519
46ba614c 1520static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1521{
46ba614c 1522 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1523 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1524 const struct intel_watermark_params *wm_info;
1525 uint32_t fwater_lo;
1526 uint32_t fwater_hi;
1527 int cwm, srwm = 1;
1528 int fifo_size;
1529 int planea_wm, planeb_wm;
1530 struct drm_crtc *crtc, *enabled = NULL;
1531
1532 if (IS_I945GM(dev))
1533 wm_info = &i945_wm_info;
5db94019 1534 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1535 wm_info = &i915_wm_info;
1536 else
9d539105 1537 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1538
1539 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1541 if (intel_crtc_active(crtc)) {
241bfc38 1542 const struct drm_display_mode *adjusted_mode;
ac484963 1543 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1544 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1545 cpp = 4;
1546
6e3c9717 1547 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1548 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1549 wm_info, fifo_size, cpp,
5aef6003 1550 pessimal_latency_ns);
b445e3b0 1551 enabled = crtc;
9d539105 1552 } else {
b445e3b0 1553 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1554 if (planea_wm > (long)wm_info->max_wm)
1555 planea_wm = wm_info->max_wm;
1556 }
1557
5db94019 1558 if (IS_GEN2(dev_priv))
9d539105 1559 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1560
1561 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1562 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1563 if (intel_crtc_active(crtc)) {
241bfc38 1564 const struct drm_display_mode *adjusted_mode;
ac484963 1565 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1566 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1567 cpp = 4;
1568
6e3c9717 1569 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1570 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1571 wm_info, fifo_size, cpp,
5aef6003 1572 pessimal_latency_ns);
b445e3b0
ED		 1573 if (enabled == NULL)
1574 enabled = crtc;
1575 else
1576 enabled = NULL;
9d539105 1577 } else {
b445e3b0 1578 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1579 if (planeb_wm > (long)wm_info->max_wm)
1580 planeb_wm = wm_info->max_wm;
1581 }
b445e3b0
ED		 1582
1583 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1584
50a0bc90 1585 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1586 struct drm_i915_gem_object *obj;
2ab1bc9d 1587
59bea882 1588 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1589
1590 /* self-refresh seems busted with untiled */
3e510a8e 1591 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1592 enabled = NULL;
1593 }
1594
b445e3b0
ED		 1595 /*
1596 * Overlay gets an aggressive default since video jitter is bad.
1597 */
1598 cwm = 2;
1599
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1601 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1602
1603 /* Calc sr entries for one plane configs */
1604 if (HAS_FW_BLC(dev) && enabled) {
1605 /* self-refresh has much higher latency */
1606 static const int sr_latency_ns = 6000;
124abe07 1607 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1608 int clock = adjusted_mode->crtc_clock;
fec8cba3 1609 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1610 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1611 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1612 unsigned long line_time_us;
1613 int entries;
1614
50a0bc90 1615 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056
VS		 1616 cpp = 4;
1617
922044c9 1618 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1619
1620 /* Use ns/us then divide to preserve precision */
1621 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1622 cpp * hdisplay;
b445e3b0
ED		 1623 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1624 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1625 srwm = wm_info->fifo_size - entries;
1626 if (srwm < 0)
1627 srwm = 1;
1628
50a0bc90 1629 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF,
1631 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1632 else
b445e3b0
ED		 1633 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1634 }
1635
1636 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1637 planea_wm, planeb_wm, cwm, srwm);
1638
1639 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1640 fwater_hi = (cwm & 0x1f);
1641
1642 /* Set request length to 8 cachelines per fetch */
1643 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1644 fwater_hi = fwater_hi | (1 << 8);
1645
1646 I915_WRITE(FW_BLC, fwater_lo);
1647 I915_WRITE(FW_BLC2, fwater_hi);
1648
5209b1f4
ID		 1649 if (enabled)
1650 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1651}
1652
feb56b93 1653static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1654{
46ba614c 1655 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1656 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1657 struct drm_crtc *crtc;
241bfc38 1658 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1659 uint32_t fwater_lo;
1660 int planea_wm;
1661
1662 crtc = single_enabled_crtc(dev);
1663 if (crtc == NULL)
1664 return;
1665
6e3c9717 1666 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1667 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1668 &i845_wm_info,
b445e3b0 1669 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1670 4, pessimal_latency_ns);
b445e3b0
ED		 1671 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1672 fwater_lo |= (3<<8) | planea_wm;
1673
1674 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1675
1676 I915_WRITE(FW_BLC, fwater_lo);
1677}
1678
8cfb3407 1679uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1680{
fd4daa9c 1681 uint32_t pixel_rate;
801bcfff 1682
8cfb3407 1683 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1684
1685 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1686 * adjust the pixel_rate here. */
1687
8cfb3407 1688 if (pipe_config->pch_pfit.enabled) {
801bcfff 1689 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1690 uint32_t pfit_size = pipe_config->pch_pfit.size;
1691
1692 pipe_w = pipe_config->pipe_src_w;
1693 pipe_h = pipe_config->pipe_src_h;
801bcfff 1694
801bcfff
PZ		 1695 pfit_w = (pfit_size >> 16) & 0xFFFF;
1696 pfit_h = pfit_size & 0xFFFF;
1697 if (pipe_w < pfit_w)
1698 pipe_w = pfit_w;
1699 if (pipe_h < pfit_h)
1700 pipe_h = pfit_h;
1701
15126882
MR		 1702 if (WARN_ON(!pfit_w || !pfit_h))
1703 return pixel_rate;
1704
801bcfff
PZ		 1705 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1706 pfit_w * pfit_h);
1707 }
1708
1709 return pixel_rate;
1710}
1711
37126462 1712/* latency must be in 0.1us units. */
ac484963 1713static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1714{
1715 uint64_t ret;
1716
3312ba65
VS		 1717 if (WARN(latency == 0, "Latency value missing\n"))
1718 return UINT_MAX;
1719
ac484963 1720 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1721 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1722
1723 return ret;
1724}
1725
37126462 1726/* latency must be in 0.1us units. */
23297044 1727static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1728 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1729 uint32_t latency)
1730{
1731 uint32_t ret;
1732
3312ba65
VS		 1733 if (WARN(latency == 0, "Latency value missing\n"))
1734 return UINT_MAX;
15126882
MR		 1735 if (WARN_ON(!pipe_htotal))
1736 return UINT_MAX;
3312ba65 1737
801bcfff 1738 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1739 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1740 ret = DIV_ROUND_UP(ret, 64) + 2;
1741 return ret;
1742}
1743
23297044 1744static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1745 uint8_t cpp)
cca32e9a 1746{
15126882
MR		 1747 /*
1748 * Neither of these should be possible since this function shouldn't be
1749 * called if the CRTC is off or the plane is invisible. But let's be
1750 * extra paranoid to avoid a potential divide-by-zero if we screw up
1751 * elsewhere in the driver.
1752 */
ac484963 1753 if (WARN_ON(!cpp))
15126882
MR		 1754 return 0;
1755 if (WARN_ON(!horiz_pixels))
1756 return 0;
1757
ac484963 1758 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1759}
1760
820c1980 1761struct ilk_wm_maximums {
cca32e9a
PZ		 1762 uint16_t pri;
1763 uint16_t spr;
1764 uint16_t cur;
1765 uint16_t fbc;
1766};
1767
37126462
VS		 1768/*
1769 * For both WM_PIPE and WM_LP.
1770 * mem_value must be in 0.1us units.
1771 */
7221fc33 1772static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1773 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1774 uint32_t mem_value,
1775 bool is_lp)
801bcfff 1776{
ac484963
VS		 1777 int cpp = pstate->base.fb ?
1778 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1779 uint32_t method1, method2;
1780
936e71e3 1781 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1782 return 0;
1783
ac484963 1784 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1785
1786 if (!is_lp)
1787 return method1;
1788
7221fc33
MR		 1789 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1790 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1791 drm_rect_width(&pstate->base.dst),
ac484963 1792 cpp, mem_value);
cca32e9a
PZ		 1793
1794 return min(method1, method2);
801bcfff
PZ		 1795}
1796
37126462
VS		 1797/*
1798 * For both WM_PIPE and WM_LP.
1799 * mem_value must be in 0.1us units.
1800 */
7221fc33 1801static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1802 const struct intel_plane_state *pstate,
801bcfff
PZ		 1803 uint32_t mem_value)
1804{
ac484963
VS		 1805 int cpp = pstate->base.fb ?
1806 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1807 uint32_t method1, method2;
1808
936e71e3 1809 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1810 return 0;
1811
ac484963 1812 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1813 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1815 drm_rect_width(&pstate->base.dst),
ac484963 1816 cpp, mem_value);
801bcfff
PZ		 1817 return min(method1, method2);
1818}
1819
37126462
VS		 1820/*
1821 * For both WM_PIPE and WM_LP.
1822 * mem_value must be in 0.1us units.
1823 */
7221fc33 1824static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1825 const struct intel_plane_state *pstate,
801bcfff
PZ		 1826 uint32_t mem_value)
1827{
b2435692
MR		 1828 /*
1829 * We treat the cursor plane as always-on for the purposes of watermark
1830 * calculation. Until we have two-stage watermark programming merged,
1831 * this is necessary to avoid flickering.
1832 */
1833 int cpp = 4;
936e71e3 1834 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1835
b2435692 1836 if (!cstate->base.active)
801bcfff
PZ		 1837 return 0;
1838
7221fc33
MR		 1839 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1840 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1841 width, cpp, mem_value);
801bcfff
PZ		 1842}
1843
cca32e9a 1844/* Only for WM_LP. */
7221fc33 1845static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1846 const struct intel_plane_state *pstate,
1fda9882 1847 uint32_t pri_val)
cca32e9a 1848{
ac484963
VS		 1849 int cpp = pstate->base.fb ?
1850 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1851
936e71e3 1852 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1853 return 0;
1854
936e71e3 1855 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1856}
1857
158ae64f
VS		 1858static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1859{
416f4727
VS		 1860 if (INTEL_INFO(dev)->gen >= 8)
1861 return 3072;
1862 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1863 return 768;
1864 else
1865 return 512;
1866}
1867
4e975081
VS		 1868static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1869 int level, bool is_sprite)
1870{
1871 if (INTEL_INFO(dev)->gen >= 8)
1872 /* BDW primary/sprite plane watermarks */
1873 return level == 0 ? 255 : 2047;
1874 else if (INTEL_INFO(dev)->gen >= 7)
1875 /* IVB/HSW primary/sprite plane watermarks */
1876 return level == 0 ? 127 : 1023;
1877 else if (!is_sprite)
1878 /* ILK/SNB primary plane watermarks */
1879 return level == 0 ? 127 : 511;
1880 else
1881 /* ILK/SNB sprite plane watermarks */
1882 return level == 0 ? 63 : 255;
1883}
1884
1885static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1886 int level)
1887{
1888 if (INTEL_INFO(dev)->gen >= 7)
1889 return level == 0 ? 63 : 255;
1890 else
1891 return level == 0 ? 31 : 63;
1892}
1893
1894static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1895{
1896 if (INTEL_INFO(dev)->gen >= 8)
1897 return 31;
1898 else
1899 return 15;
1900}
1901
158ae64f
VS		 1902/* Calculate the maximum primary/sprite plane watermark */
1903static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1904 int level,
240264f4 1905 const struct intel_wm_config *config,
158ae64f
VS		 1906 enum intel_ddb_partitioning ddb_partitioning,
1907 bool is_sprite)
1908{
1909 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1910
1911 /* if sprites aren't enabled, sprites get nothing */
240264f4 1912 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1913 return 0;
1914
1915 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1916 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1917 fifo_size /= INTEL_INFO(dev)->num_pipes;
1918
1919 /*
1920 * For some reason the non self refresh
1921 * FIFO size is only half of the self
1922 * refresh FIFO size on ILK/SNB.
1923 */
1924 if (INTEL_INFO(dev)->gen <= 6)
1925 fifo_size /= 2;
1926 }
1927
240264f4 1928 if (config->sprites_enabled) {
158ae64f
VS		 1929 /* level 0 is always calculated with 1:1 split */
1930 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1931 if (is_sprite)
1932 fifo_size *= 5;
1933 fifo_size /= 6;
1934 } else {
1935 fifo_size /= 2;
1936 }
1937 }
1938
1939 /* clamp to max that the registers can hold */
4e975081 1940 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1941}
1942
1943/* Calculate the maximum cursor plane watermark */
1944static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1945 int level,
1946 const struct intel_wm_config *config)
158ae64f
VS		 1947{
1948 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1949 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1950 return 64;
1951
1952 /* otherwise just report max that registers can hold */
4e975081 1953 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1954}
1955
d34ff9c6 1956static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1957 int level,
1958 const struct intel_wm_config *config,
1959 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1960 struct ilk_wm_maximums *max)
158ae64f 1961{
240264f4
VS		 1962 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1963 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1964 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1965 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1966}
1967
a3cb4048
VS		 1968static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1969 int level,
1970 struct ilk_wm_maximums *max)
1971{
1972 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1973 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1974 max->cur = ilk_cursor_wm_reg_max(dev, level);
1975 max->fbc = ilk_fbc_wm_reg_max(dev);
1976}
1977
d9395655 1978static bool ilk_validate_wm_level(int level,
820c1980 1979 const struct ilk_wm_maximums *max,
d9395655 1980 struct intel_wm_level *result)
a9786a11
VS		 1981{
1982 bool ret;
1983
1984 /* already determined to be invalid? */
1985 if (!result->enable)
1986 return false;
1987
1988 result->enable = result->pri_val <= max->pri &&
1989 result->spr_val <= max->spr &&
1990 result->cur_val <= max->cur;
1991
1992 ret = result->enable;
1993
1994 /*
1995 * HACK until we can pre-compute everything,
1996 * and thus fail gracefully if LP0 watermarks
1997 * are exceeded...
1998 */
1999 if (level == 0 && !result->enable) {
2000 if (result->pri_val > max->pri)
2001 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2002 level, result->pri_val, max->pri);
2003 if (result->spr_val > max->spr)
2004 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2005 level, result->spr_val, max->spr);
2006 if (result->cur_val > max->cur)
2007 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2008 level, result->cur_val, max->cur);
2009
2010 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2011 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2012 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2013 result->enable = true;
2014 }
2015
a9786a11
VS		 2016 return ret;
2017}
2018
d34ff9c6 2019static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2020 const struct intel_crtc *intel_crtc,
6f5ddd17 2021 int level,
7221fc33 2022 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2023 struct intel_plane_state *pristate,
2024 struct intel_plane_state *sprstate,
2025 struct intel_plane_state *curstate,
1fd527cc 2026 struct intel_wm_level *result)
6f5ddd17
VS		 2027{
2028 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2029 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2030 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2031
2032 /* WM1+ latency values stored in 0.5us units */
2033 if (level > 0) {
2034 pri_latency *= 5;
2035 spr_latency *= 5;
2036 cur_latency *= 5;
2037 }
2038
e3bddded
ML		 2039 if (pristate) {
2040 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2041 pri_latency, level);
2042 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2043 }
2044
2045 if (sprstate)
2046 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2047
2048 if (curstate)
2049 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2050
6f5ddd17
VS		 2051 result->enable = true;
2052}
2053
801bcfff 2054static uint32_t
532f7a7f 2055hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2056{
532f7a7f
VS		 2057 const struct intel_atomic_state *intel_state =
2058 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2059 const struct drm_display_mode *adjusted_mode =
2060 &cstate->base.adjusted_mode;
85a02deb 2061 u32 linetime, ips_linetime;
1f8eeabf 2062
ee91a159
MR		 2063 if (!cstate->base.active)
2064 return 0;
2065 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2066 return 0;
532f7a7f 2067 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2068 return 0;
1011d8c4 2069
1f8eeabf
ED		 2070 /* The WM are computed with base on how long it takes to fill a single
2071 * row at the given clock rate, multiplied by 8.
2072 * */
124abe07
VS		 2073 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2074 adjusted_mode->crtc_clock);
2075 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2076 intel_state->cdclk);
1f8eeabf 2077
801bcfff
PZ		 2078 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2079 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2080}
2081
2af30a5c 2082static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2083{
fac5e23e 2084 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2085
5db94019 2086 if (IS_GEN9(dev_priv)) {
2af30a5c 2087 uint32_t val;
4f947386 2088 int ret, i;
5db94019 2089 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2090
2091 /* read the first set of memory latencies[0:3] */
2092 val = 0; /* data0 to be programmed to 0 for first set */
2093 mutex_lock(&dev_priv->rps.hw_lock);
2094 ret = sandybridge_pcode_read(dev_priv,
2095 GEN9_PCODE_READ_MEM_LATENCY,
2096 &val);
2097 mutex_unlock(&dev_priv->rps.hw_lock);
2098
2099 if (ret) {
2100 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2101 return;
2102 }
2103
2104 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2105 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2106 GEN9_MEM_LATENCY_LEVEL_MASK;
2107 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2108 GEN9_MEM_LATENCY_LEVEL_MASK;
2109 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2110 GEN9_MEM_LATENCY_LEVEL_MASK;
2111
2112 /* read the second set of memory latencies[4:7] */
2113 val = 1; /* data0 to be programmed to 1 for second set */
2114 mutex_lock(&dev_priv->rps.hw_lock);
2115 ret = sandybridge_pcode_read(dev_priv,
2116 GEN9_PCODE_READ_MEM_LATENCY,
2117 &val);
2118 mutex_unlock(&dev_priv->rps.hw_lock);
2119 if (ret) {
2120 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2121 return;
2122 }
2123
2124 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2125 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2126 GEN9_MEM_LATENCY_LEVEL_MASK;
2127 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2128 GEN9_MEM_LATENCY_LEVEL_MASK;
2129 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2130 GEN9_MEM_LATENCY_LEVEL_MASK;
2131
0727e40a
PZ		 2132 /*
2133 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2134 * need to be disabled. We make sure to sanitize the values out
2135 * of the punit to satisfy this requirement.
2136 */
2137 for (level = 1; level <= max_level; level++) {
2138 if (wm[level] == 0) {
2139 for (i = level + 1; i <= max_level; i++)
2140 wm[i] = 0;
2141 break;
2142 }
2143 }
2144
367294be 2145 /*
6f97235b
DL		 2146 * WaWmMemoryReadLatency:skl
2147 *
367294be 2148 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2149 * to add 2us to the various latency levels we retrieve from the
2150 * punit when level 0 response data us 0us.
367294be 2151 */
0727e40a
PZ		 2152 if (wm[0] == 0) {
2153 wm[0] += 2;
2154 for (level = 1; level <= max_level; level++) {
2155 if (wm[level] == 0)
2156 break;
367294be 2157 wm[level] += 2;
4f947386 2158 }
0727e40a
PZ		 2159 }
2160
8652744b 2161 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2162 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2163
2164 wm[0] = (sskpd >> 56) & 0xFF;
2165 if (wm[0] == 0)
2166 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2167 wm[1] = (sskpd >> 4) & 0xFF;
2168 wm[2] = (sskpd >> 12) & 0xFF;
2169 wm[3] = (sskpd >> 20) & 0x1FF;
2170 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2171 } else if (INTEL_INFO(dev)->gen >= 6) {
2172 uint32_t sskpd = I915_READ(MCH_SSKPD);
2173
2174 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2175 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2176 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2177 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2178 } else if (INTEL_INFO(dev)->gen >= 5) {
2179 uint32_t mltr = I915_READ(MLTR_ILK);
2180
2181 /* ILK primary LP0 latency is 700 ns */
2182 wm[0] = 7;
2183 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2184 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2185 }
2186}
2187
5db94019
TU		 2188static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2189 uint16_t wm[5])
53615a5e
VS		 2190{
2191 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2192 if (IS_GEN5(dev_priv))
53615a5e
VS		 2193 wm[0] = 13;
2194}
2195
fd6b8f43
TU		 2196static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2197 uint16_t wm[5])
53615a5e
VS		 2198{
2199 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2200 if (IS_GEN5(dev_priv))
53615a5e
VS		 2201 wm[0] = 13;
2202
2203 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2204 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2205 wm[3] *= 2;
2206}
2207
5db94019 2208int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2209{
26ec971e 2210 /* how many WM levels are we expecting */
8652744b 2211 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2212 return 7;
8652744b 2213 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2214 return 4;
8652744b 2215 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2216 return 3;
26ec971e 2217 else
ad0d6dc4
VS		 2218 return 2;
2219}
7526ed79 2220
5db94019 2221static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2222 const char *name,
2af30a5c 2223 const uint16_t wm[8])
ad0d6dc4 2224{
5db94019 2225 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2226
2227 for (level = 0; level <= max_level; level++) {
2228 unsigned int latency = wm[level];
2229
2230 if (latency == 0) {
2231 DRM_ERROR("%s WM%d latency not provided\n",
2232 name, level);
2233 continue;
2234 }
2235
2af30a5c
PB		 2236 /*
2237 * - latencies are in us on gen9.
2238 * - before then, WM1+ latency values are in 0.5us units
2239 */
5db94019 2240 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2241 latency *= 10;
2242 else if (level > 0)
26ec971e
VS		 2243 latency *= 5;
2244
2245 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2246 name, level, wm[level],
2247 latency / 10, latency % 10);
2248 }
2249}
2250
e95a2f75
VS		 2251static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2252 uint16_t wm[5], uint16_t min)
2253{
5db94019 2254 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2255
2256 if (wm[0] >= min)
2257 return false;
2258
2259 wm[0] = max(wm[0], min);
2260 for (level = 1; level <= max_level; level++)
2261 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2262
2263 return true;
2264}
2265
2266static void snb_wm_latency_quirk(struct drm_device *dev)
2267{
fac5e23e 2268 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2269 bool changed;
2270
2271 /*
2272 * The BIOS provided WM memory latency values are often
2273 * inadequate for high resolution displays. Adjust them.
2274 */
2275 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2276 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2277 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2278
2279 if (!changed)
2280 return;
2281
2282 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2283 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2284 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2285 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2286}
2287
fa50ad61 2288static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2289{
fac5e23e 2290 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2291
2292 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2293
2294 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2295 sizeof(dev_priv->wm.pri_latency));
2296 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2297 sizeof(dev_priv->wm.pri_latency));
2298
5db94019 2299 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2300 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2301
5db94019
TU		 2302 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2303 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2304 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2305
5db94019 2306 if (IS_GEN6(dev_priv))
e95a2f75 2307 snb_wm_latency_quirk(dev);
53615a5e
VS		 2308}
2309
2af30a5c
PB		 2310static void skl_setup_wm_latency(struct drm_device *dev)
2311{
fac5e23e 2312 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2313
2314 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2315 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2316}
2317
ed4a6a7c
MR		 2318static bool ilk_validate_pipe_wm(struct drm_device *dev,
2319 struct intel_pipe_wm *pipe_wm)
2320{
2321 /* LP0 watermark maximums depend on this pipe alone */
2322 const struct intel_wm_config config = {
2323 .num_pipes_active = 1,
2324 .sprites_enabled = pipe_wm->sprites_enabled,
2325 .sprites_scaled = pipe_wm->sprites_scaled,
2326 };
2327 struct ilk_wm_maximums max;
2328
2329 /* LP0 watermarks always use 1/2 DDB partitioning */
2330 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2331
2332 /* At least LP0 must be valid */
2333 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2334 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2335 return false;
2336 }
2337
2338 return true;
2339}
2340
0b2ae6d7 2341/* Compute new watermarks for the pipe */
e3bddded 2342static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2343{
e3bddded
ML		 2344 struct drm_atomic_state *state = cstate->base.state;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2346 struct intel_pipe_wm *pipe_wm;
e3bddded 2347 struct drm_device *dev = state->dev;
fac5e23e 2348 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2349 struct intel_plane *intel_plane;
86c8bbbe 2350 struct intel_plane_state *pristate = NULL;
43d59eda 2351 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2352 struct intel_plane_state *curstate = NULL;
5db94019 2353 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2354 struct ilk_wm_maximums max;
0b2ae6d7 2355
e8f1f02e 2356 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2357
43d59eda 2358 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2359 struct intel_plane_state *ps;
2360
2361 ps = intel_atomic_get_existing_plane_state(state,
2362 intel_plane);
2363 if (!ps)
2364 continue;
86c8bbbe
MR		 2365
2366 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2367 pristate = ps;
86c8bbbe 2368 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2369 sprstate = ps;
86c8bbbe 2370 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2371 curstate = ps;
43d59eda
MR		 2372 }
2373
ed4a6a7c 2374 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2375 if (sprstate) {
936e71e3
VS		 2376 pipe_wm->sprites_enabled = sprstate->base.visible;
2377 pipe_wm->sprites_scaled = sprstate->base.visible &&
2378 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2379 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2380 }
2381
d81f04c5
ML		 2382 usable_level = max_level;
2383
7b39a0b7 2384 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2385 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2386 usable_level = 1;
7b39a0b7
VS		 2387
2388 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2389 if (pipe_wm->sprites_scaled)
d81f04c5 2390 usable_level = 0;
7b39a0b7 2391
86c8bbbe 2392 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2393 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2394
2395 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2396 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2397
8652744b 2398 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2399 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2400
ed4a6a7c 2401 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2402 return -EINVAL;
a3cb4048
VS		 2403
2404 ilk_compute_wm_reg_maximums(dev, 1, &max);
2405
2406 for (level = 1; level <= max_level; level++) {
71f0a626 2407 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2408
86c8bbbe 2409 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2410 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2411
2412 /*
2413 * Disable any watermark level that exceeds the
2414 * register maximums since such watermarks are
2415 * always invalid.
2416 */
71f0a626
ML		 2417 if (level > usable_level)
2418 continue;
2419
2420 if (ilk_validate_wm_level(level, &max, wm))
2421 pipe_wm->wm[level] = *wm;
2422 else
d81f04c5 2423 usable_level = level;
a3cb4048
VS		 2424 }
2425
86c8bbbe 2426 return 0;
0b2ae6d7
VS		 2427}
2428
ed4a6a7c
MR		 2429/*
2430 * Build a set of 'intermediate' watermark values that satisfy both the old
2431 * state and the new state. These can be programmed to the hardware
2432 * immediately.
2433 */
2434static int ilk_compute_intermediate_wm(struct drm_device *dev,
2435 struct intel_crtc *intel_crtc,
2436 struct intel_crtc_state *newstate)
2437{
e8f1f02e 2438 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2439 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2440 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2441
2442 /*
2443 * Start with the final, target watermarks, then combine with the
2444 * currently active watermarks to get values that are safe both before
2445 * and after the vblank.
2446 */
e8f1f02e 2447 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2448 a->pipe_enabled |= b->pipe_enabled;
2449 a->sprites_enabled |= b->sprites_enabled;
2450 a->sprites_scaled |= b->sprites_scaled;
2451
2452 for (level = 0; level <= max_level; level++) {
2453 struct intel_wm_level *a_wm = &a->wm[level];
2454 const struct intel_wm_level *b_wm = &b->wm[level];
2455
2456 a_wm->enable &= b_wm->enable;
2457 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2458 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2459 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2460 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2461 }
2462
2463 /*
2464 * We need to make sure that these merged watermark values are
2465 * actually a valid configuration themselves. If they're not,
2466 * there's no safe way to transition from the old state to
2467 * the new state, so we need to fail the atomic transaction.
2468 */
2469 if (!ilk_validate_pipe_wm(dev, a))
2470 return -EINVAL;
2471
2472 /*
2473 * If our intermediate WM are identical to the final WM, then we can
2474 * omit the post-vblank programming; only update if it's different.
2475 */
e8f1f02e 2476 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2477 newstate->wm.need_postvbl_update = false;
2478
2479 return 0;
2480}
2481
0b2ae6d7
VS		 2482/*
2483 * Merge the watermarks from all active pipes for a specific level.
2484 */
2485static void ilk_merge_wm_level(struct drm_device *dev,
2486 int level,
2487 struct intel_wm_level *ret_wm)
2488{
2489 const struct intel_crtc *intel_crtc;
2490
d52fea5b
VS		 2491 ret_wm->enable = true;
2492
d3fcc808 2493 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2494 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2495 const struct intel_wm_level *wm = &active->wm[level];
2496
2497 if (!active->pipe_enabled)
2498 continue;
0b2ae6d7 2499
d52fea5b
VS		 2500 /*
2501 * The watermark values may have been used in the past,
2502 * so we must maintain them in the registers for some
2503 * time even if the level is now disabled.
2504 */
0b2ae6d7 2505 if (!wm->enable)
d52fea5b 2506 ret_wm->enable = false;
0b2ae6d7
VS		 2507
2508 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2509 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2510 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2511 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2512 }
0b2ae6d7
VS		 2513}
2514
2515/*
2516 * Merge all low power watermarks for all active pipes.
2517 */
2518static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2519 const struct intel_wm_config *config,
820c1980 2520 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2521 struct intel_pipe_wm *merged)
2522{
fac5e23e 2523 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2524 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2525 int last_enabled_level = max_level;
0b2ae6d7 2526
0ba22e26 2527 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2528 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2529 config->num_pipes_active > 1)
1204d5ba 2530 last_enabled_level = 0;
0ba22e26 2531
6c8b6c28
VS		 2532 /* ILK: FBC WM must be disabled always */
2533 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2534
2535 /* merge each WM1+ level */
2536 for (level = 1; level <= max_level; level++) {
2537 struct intel_wm_level *wm = &merged->wm[level];
2538
2539 ilk_merge_wm_level(dev, level, wm);
2540
d52fea5b
VS		 2541 if (level > last_enabled_level)
2542 wm->enable = false;
2543 else if (!ilk_validate_wm_level(level, max, wm))
2544 /* make sure all following levels get disabled */
2545 last_enabled_level = level - 1;
0b2ae6d7
VS		 2546
2547 /*
2548 * The spec says it is preferred to disable
2549 * FBC WMs instead of disabling a WM level.
2550 */
2551 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2552 if (wm->enable)
2553 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2554 wm->fbc_val = 0;
2555 }
2556 }
6c8b6c28
VS		 2557
2558 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2559 /*
2560 * FIXME this is racy. FBC might get enabled later.
2561 * What we should check here is whether FBC can be
2562 * enabled sometime later.
2563 */
5db94019 2564 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2565 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2566 for (level = 2; level <= max_level; level++) {
2567 struct intel_wm_level *wm = &merged->wm[level];
2568
2569 wm->enable = false;
2570 }
2571 }
0b2ae6d7
VS		 2572}
2573
b380ca3c
VS		 2574static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2575{
2576 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2577 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2578}
2579
a68d68ee
VS		 2580/* The value we need to program into the WM_LPx latency field */
2581static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2582{
fac5e23e 2583 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2584
8652744b 2585 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2586 return 2 * level;
2587 else
2588 return dev_priv->wm.pri_latency[level];
2589}
2590
820c1980 2591static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2592 const struct intel_pipe_wm *merged,
609cedef 2593 enum intel_ddb_partitioning partitioning,
820c1980 2594 struct ilk_wm_values *results)
801bcfff 2595{
0b2ae6d7
VS		 2596 struct intel_crtc *intel_crtc;
2597 int level, wm_lp;
cca32e9a 2598
0362c781 2599 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2600 results->partitioning = partitioning;
cca32e9a 2601
0b2ae6d7 2602 /* LP1+ register values */
cca32e9a 2603 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2604 const struct intel_wm_level *r;
801bcfff 2605
b380ca3c 2606 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2607
0362c781 2608 r = &merged->wm[level];
cca32e9a 2609
d52fea5b
VS		 2610 /*
2611 * Maintain the watermark values even if the level is
2612 * disabled. Doing otherwise could cause underruns.
2613 */
2614 results->wm_lp[wm_lp - 1] =
a68d68ee 2615 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2616 (r->pri_val << WM1_LP_SR_SHIFT) |
2617 r->cur_val;
2618
d52fea5b
VS		 2619 if (r->enable)
2620 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2621
416f4727
VS		 2622 if (INTEL_INFO(dev)->gen >= 8)
2623 results->wm_lp[wm_lp - 1] |=
2624 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2625 else
2626 results->wm_lp[wm_lp - 1] |=
2627 r->fbc_val << WM1_LP_FBC_SHIFT;
2628
d52fea5b
VS		 2629 /*
2630 * Always set WM1S_LP_EN when spr_val != 0, even if the
2631 * level is disabled. Doing otherwise could cause underruns.
2632 */
6cef2b8a
VS		 2633 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2634 WARN_ON(wm_lp != 1);
2635 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2636 } else
2637 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2638 }
801bcfff 2639
0b2ae6d7 2640 /* LP0 register values */
d3fcc808 2641 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2642 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2643 const struct intel_wm_level *r =
2644 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2645
2646 if (WARN_ON(!r->enable))
2647 continue;
2648
ed4a6a7c 2649 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2650
0b2ae6d7
VS		 2651 results->wm_pipe[pipe] =
2652 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2653 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2654 r->cur_val;
801bcfff
PZ		 2655 }
2656}
2657
861f3389
PZ		 2658/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2659 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2660static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2661 struct intel_pipe_wm *r1,
2662 struct intel_pipe_wm *r2)
861f3389 2663{
5db94019 2664 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2665 int level1 = 0, level2 = 0;
861f3389 2666
198a1e9b
VS		 2667 for (level = 1; level <= max_level; level++) {
2668 if (r1->wm[level].enable)
2669 level1 = level;
2670 if (r2->wm[level].enable)
2671 level2 = level;
861f3389
PZ		 2672 }
2673
198a1e9b
VS		 2674 if (level1 == level2) {
2675 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2676 return r2;
2677 else
2678 return r1;
198a1e9b 2679 } else if (level1 > level2) {
861f3389
PZ		 2680 return r1;
2681 } else {
2682 return r2;
2683 }
2684}
2685
49a687c4
VS		 2686/* dirty bits used to track which watermarks need changes */
2687#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2688#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2689#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2690#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2691#define WM_DIRTY_FBC (1 << 24)
2692#define WM_DIRTY_DDB (1 << 25)
2693
055e393f 2694static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2695 const struct ilk_wm_values *old,
2696 const struct ilk_wm_values *new)
49a687c4
VS		 2697{
2698 unsigned int dirty = 0;
2699 enum pipe pipe;
2700 int wm_lp;
2701
055e393f 2702 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2703 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2704 dirty |= WM_DIRTY_LINETIME(pipe);
2705 /* Must disable LP1+ watermarks too */
2706 dirty |= WM_DIRTY_LP_ALL;
2707 }
2708
2709 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2710 dirty |= WM_DIRTY_PIPE(pipe);
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714 }
2715
2716 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2717 dirty |= WM_DIRTY_FBC;
2718 /* Must disable LP1+ watermarks too */
2719 dirty |= WM_DIRTY_LP_ALL;
2720 }
2721
2722 if (old->partitioning != new->partitioning) {
2723 dirty |= WM_DIRTY_DDB;
2724 /* Must disable LP1+ watermarks too */
2725 dirty |= WM_DIRTY_LP_ALL;
2726 }
2727
2728 /* LP1+ watermarks already deemed dirty, no need to continue */
2729 if (dirty & WM_DIRTY_LP_ALL)
2730 return dirty;
2731
2732 /* Find the lowest numbered LP1+ watermark in need of an update... */
2733 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2734 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2735 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2736 break;
2737 }
2738
2739 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2740 for (; wm_lp <= 3; wm_lp++)
2741 dirty |= WM_DIRTY_LP(wm_lp);
2742
2743 return dirty;
2744}
2745
8553c18e
VS		 2746static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2747 unsigned int dirty)
801bcfff 2748{
820c1980 2749 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2750 bool changed = false;
801bcfff 2751
facd619b
VS		 2752 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2753 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2755 changed = true;
facd619b
VS		 2756 }
2757 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2758 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2760 changed = true;
facd619b
VS		 2761 }
2762 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2763 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2765 changed = true;
facd619b 2766 }
801bcfff 2767
facd619b
VS		 2768 /*
2769 * Don't touch WM1S_LP_EN here.
2770 * Doing so could cause underruns.
2771 */
6cef2b8a 2772
8553c18e
VS		 2773 return changed;
2774}
2775
2776/*
2777 * The spec says we shouldn't write when we don't need, because every write
2778 * causes WMs to be re-evaluated, expending some power.
2779 */
820c1980
ID		 2780static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2781 struct ilk_wm_values *results)
8553c18e 2782{
91c8a326 2783 struct drm_device *dev = &dev_priv->drm;
820c1980 2784 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2785 unsigned int dirty;
2786 uint32_t val;
2787
055e393f 2788 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2789 if (!dirty)
2790 return;
2791
2792 _ilk_disable_lp_wm(dev_priv, dirty);
2793
49a687c4 2794 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2795 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2796 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2797 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2798 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2802 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2803 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2804 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2805 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2807
49a687c4 2808 if (dirty & WM_DIRTY_DDB) {
8652744b 2809 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2810 val = I915_READ(WM_MISC);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~WM_MISC_DATA_PARTITION_5_6;
2813 else
2814 val |= WM_MISC_DATA_PARTITION_5_6;
2815 I915_WRITE(WM_MISC, val);
2816 } else {
2817 val = I915_READ(DISP_ARB_CTL2);
2818 if (results->partitioning == INTEL_DDB_PART_1_2)
2819 val &= ~DISP_DATA_PARTITION_5_6;
2820 else
2821 val |= DISP_DATA_PARTITION_5_6;
2822 I915_WRITE(DISP_ARB_CTL2, val);
2823 }
1011d8c4
PZ		 2824 }
2825
49a687c4 2826 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2827 val = I915_READ(DISP_ARB_CTL);
2828 if (results->enable_fbc_wm)
2829 val &= ~DISP_FBC_WM_DIS;
2830 else
2831 val |= DISP_FBC_WM_DIS;
2832 I915_WRITE(DISP_ARB_CTL, val);
2833 }
2834
954911eb
ID		 2835 if (dirty & WM_DIRTY_LP(1) &&
2836 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2837 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2838
2839 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2840 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2841 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2842 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2843 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2844 }
801bcfff 2845
facd619b 2846 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2847 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2848 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2849 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2850 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2851 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2852
2853 dev_priv->wm.hw = *results;
801bcfff
PZ		 2854}
2855
ed4a6a7c 2856bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2857{
fac5e23e 2858 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2859
2860 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2861}
2862
656d1b89 2863#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2864
024c9045
MR		 2865/*
2866 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2867 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868 * other universal planes are in indices 1..n. Note that this may leave unused
2869 * indices between the top "sprite" plane and the cursor.
2870 */
2871static int
2872skl_wm_plane_id(const struct intel_plane *plane)
2873{
2874 switch (plane->base.type) {
2875 case DRM_PLANE_TYPE_PRIMARY:
2876 return 0;
2877 case DRM_PLANE_TYPE_CURSOR:
2878 return PLANE_CURSOR;
2879 case DRM_PLANE_TYPE_OVERLAY:
2880 return plane->plane + 1;
2881 default:
2882 MISSING_CASE(plane->base.type);
2883 return plane->plane;
2884 }
2885}
2886
ee3d532f
PZ		 2887/*
2888 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2889 * so assume we'll always need it in order to avoid underruns.
2890 */
2891static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2892{
2893 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2894
2895 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2896 IS_KABYLAKE(dev_priv))
2897 return true;
2898
2899 return false;
2900}
2901
56feca91
PZ		 2902static bool
2903intel_has_sagv(struct drm_i915_private *dev_priv)
2904{
6e3100ec
PZ		 2905 if (IS_KABYLAKE(dev_priv))
2906 return true;
2907
2908 if (IS_SKYLAKE(dev_priv) &&
2909 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2910 return true;
2911
2912 return false;
56feca91
PZ		 2913}
2914
656d1b89
L		 2915/*
2916 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2917 * depending on power and performance requirements. The display engine access
2918 * to system memory is blocked during the adjustment time. Because of the
2919 * blocking time, having this enabled can cause full system hangs and/or pipe
2920 * underruns if we don't meet all of the following requirements:
2921 *
2922 * - <= 1 pipe enabled
2923 * - All planes can enable watermarks for latencies >= SAGV engine block time
2924 * - We're not using an interlaced display configuration
2925 */
2926int
16dcdc4e 2927intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2928{
2929 int ret;
2930
56feca91
PZ		 2931 if (!intel_has_sagv(dev_priv))
2932 return 0;
2933
2934 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2935 return 0;
2936
2937 DRM_DEBUG_KMS("Enabling the SAGV\n");
2938 mutex_lock(&dev_priv->rps.hw_lock);
2939
2940 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2941 GEN9_SAGV_ENABLE);
2942
2943 /* We don't need to wait for the SAGV when enabling */
2944 mutex_unlock(&dev_priv->rps.hw_lock);
2945
2946 /*
2947 * Some skl systems, pre-release machines in particular,
2948 * don't actually have an SAGV.
2949 */
6e3100ec 2950 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2951 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2952 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2953 return 0;
2954 } else if (ret < 0) {
2955 DRM_ERROR("Failed to enable the SAGV\n");
2956 return ret;
2957 }
2958
16dcdc4e 2959 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2960 return 0;
2961}
2962
2963static int
16dcdc4e 2964intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2965{
2966 int ret;
2967 uint32_t temp = GEN9_SAGV_DISABLE;
2968
2969 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2970 &temp);
2971 if (ret)
2972 return ret;
2973 else
2974 return temp & GEN9_SAGV_IS_DISABLED;
2975}
2976
2977int
16dcdc4e 2978intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2979{
2980 int ret, result;
2981
56feca91
PZ		 2982 if (!intel_has_sagv(dev_priv))
2983 return 0;
2984
2985 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2986 return 0;
2987
2988 DRM_DEBUG_KMS("Disabling the SAGV\n");
2989 mutex_lock(&dev_priv->rps.hw_lock);
2990
2991 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2992 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2993 mutex_unlock(&dev_priv->rps.hw_lock);
2994
2995 if (ret == -ETIMEDOUT) {
2996 DRM_ERROR("Request to disable SAGV timed out\n");
2997 return -ETIMEDOUT;
2998 }
2999
3000 /*
3001 * Some skl systems, pre-release machines in particular,
3002 * don't actually have an SAGV.
3003 */
6e3100ec 3004 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3005 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3006 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3007 return 0;
3008 } else if (result < 0) {
3009 DRM_ERROR("Failed to disable the SAGV\n");
3010 return result;
3011 }
3012
16dcdc4e 3013 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3014 return 0;
3015}
3016
16dcdc4e 3017bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3018{
3019 struct drm_device *dev = state->dev;
3020 struct drm_i915_private *dev_priv = to_i915(dev);
3021 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3022 struct intel_crtc *crtc;
3023 struct intel_plane *plane;
d8c0fafc 3024 struct intel_crtc_state *cstate;
3025 struct skl_plane_wm *wm;
656d1b89 3026 enum pipe pipe;
d8c0fafc 3027 int level, latency;
656d1b89 3028
56feca91
PZ		 3029 if (!intel_has_sagv(dev_priv))
3030 return false;
3031
656d1b89
L		 3032 /*
3033 * SKL workaround: bspec recommends we disable the SAGV when we have
3034 * more then one pipe enabled
3035 *
3036 * If there are no active CRTCs, no additional checks need be performed
3037 */
3038 if (hweight32(intel_state->active_crtcs) == 0)
3039 return true;
3040 else if (hweight32(intel_state->active_crtcs) > 1)
3041 return false;
3042
3043 /* Since we're now guaranteed to only have one active CRTC... */
3044 pipe = ffs(intel_state->active_crtcs) - 1;
ee3d532f 3045 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d8c0fafc 3046 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3047
c89cadd5 3048 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3049 return false;
3050
ee3d532f 3051 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3052 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3053
656d1b89 3054 /* Skip this plane if it's not enabled */
d8c0fafc 3055 if (!wm->wm[0].plane_en)
656d1b89
L		 3056 continue;
3057
3058 /* Find the highest enabled wm level for this plane */
5db94019 3059 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3060 !wm->wm[level].plane_en; --level)
656d1b89
L		 3061 { }
3062
ee3d532f
PZ		 3063 latency = dev_priv->wm.skl_latency[level];
3064
3065 if (skl_needs_memory_bw_wa(intel_state) &&
3066 plane->base.state->fb->modifier[0] ==
3067 I915_FORMAT_MOD_X_TILED)
3068 latency += 15;
3069
656d1b89
L		 3070 /*
3071 * If any of the planes on this pipe don't enable wm levels
3072 * that incur memory latencies higher then 30µs we can't enable
3073 * the SAGV
3074 */
ee3d532f 3075 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3076 return false;
3077 }
3078
3079 return true;
3080}
3081
b9cec075
DL		 3082static void
3083skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3084 const struct intel_crtc_state *cstate,
c107acfe
MR		 3085 struct skl_ddb_entry *alloc, /* out */
3086 int *num_active /* out */)
b9cec075 3087{
c107acfe
MR		 3088 struct drm_atomic_state *state = cstate->base.state;
3089 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3090 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3091 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3092 unsigned int pipe_size, ddb_size;
3093 int nth_active_pipe;
c107acfe 3094
a6d3460e 3095 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3096 alloc->start = 0;
3097 alloc->end = 0;
a6d3460e 3098 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3099 return;
3100 }
3101
a6d3460e
MR		 3102 if (intel_state->active_pipe_changes)
3103 *num_active = hweight32(intel_state->active_crtcs);
3104 else
3105 *num_active = hweight32(dev_priv->active_crtcs);
3106
6f3fff60
D		 3107 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3108 WARN_ON(ddb_size == 0);
b9cec075
DL		 3109
3110 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3111
c107acfe 3112 /*
a6d3460e
MR		 3113 * If the state doesn't change the active CRTC's, then there's
3114 * no need to recalculate; the existing pipe allocation limits
3115 * should remain unchanged. Note that we're safe from racing
3116 * commits since any racing commit that changes the active CRTC
3117 * list would need to grab _all_ crtc locks, including the one
3118 * we currently hold.
c107acfe 3119 */
a6d3460e 3120 if (!intel_state->active_pipe_changes) {
ce0ba283 3121 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3122 return;
c107acfe 3123 }
a6d3460e
MR		 3124
3125 nth_active_pipe = hweight32(intel_state->active_crtcs &
3126 (drm_crtc_mask(for_crtc) - 1));
3127 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3128 alloc->start = nth_active_pipe * ddb_size / *num_active;
3129 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3130}
3131
c107acfe 3132static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3133{
c107acfe 3134 if (num_active == 1)
b9cec075
DL		 3135 return 32;
3136
3137 return 8;
3138}
3139
a269c583
DL		 3140static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3141{
3142 entry->start = reg & 0x3ff;
3143 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3144 if (entry->end)
3145 entry->end += 1;
a269c583
DL		 3146}
3147
08db6652
DL		 3148void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3149 struct skl_ddb_allocation *ddb /* out */)
a269c583 3150{
a269c583
DL		 3151 enum pipe pipe;
3152 int plane;
3153 u32 val;
3154
b10f1b20
ML		 3155 memset(ddb, 0, sizeof(*ddb));
3156
a269c583 3157 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3158 enum intel_display_power_domain power_domain;
3159
3160 power_domain = POWER_DOMAIN_PIPE(pipe);
3161 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3162 continue;
3163
8b364b41 3164 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3165 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3166 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3167 val);
3168 }
3169
3170 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3171 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3172 val);
4d800030
ID		 3173
3174 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3175 }
3176}
3177
9c2f7a9d
KM		 3178/*
3179 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3180 * The bspec defines downscale amount as:
3181 *
3182 * """
3183 * Horizontal down scale amount = maximum[1, Horizontal source size /
3184 * Horizontal destination size]
3185 * Vertical down scale amount = maximum[1, Vertical source size /
3186 * Vertical destination size]
3187 * Total down scale amount = Horizontal down scale amount *
3188 * Vertical down scale amount
3189 * """
3190 *
3191 * Return value is provided in 16.16 fixed point form to retain fractional part.
3192 * Caller should take care of dividing & rounding off the value.
3193 */
3194static uint32_t
3195skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3196{
3197 uint32_t downscale_h, downscale_w;
3198 uint32_t src_w, src_h, dst_w, dst_h;
3199
936e71e3 3200 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3201 return DRM_PLANE_HELPER_NO_SCALING;
3202
3203 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3204 src_w = drm_rect_width(&pstate->base.src);
3205 src_h = drm_rect_height(&pstate->base.src);
3206 dst_w = drm_rect_width(&pstate->base.dst);
3207 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3208 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3209 swap(dst_w, dst_h);
3210
3211 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3213
3214 /* Provide result in 16.16 fixed point */
3215 return (uint64_t)downscale_w * downscale_h >> 16;
3216}
3217
b9cec075 3218static unsigned int
024c9045
MR		 3219skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3220 const struct drm_plane_state *pstate,
3221 int y)
b9cec075 3222{
a280f7dd 3223 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3224 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3225 uint32_t down_scale_amount, data_rate;
a280f7dd 3226 uint32_t width = 0, height = 0;
a1de91e5
MR		 3227 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3228
936e71e3 3229 if (!intel_pstate->base.visible)
a1de91e5
MR		 3230 return 0;
3231 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3232 return 0;
3233 if (y && format != DRM_FORMAT_NV12)
3234 return 0;
a280f7dd 3235
936e71e3
VS		 3236 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3237 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3238
bd2ef25d 3239 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3240 swap(width, height);
2cd601c6
CK		 3241
3242 /* for planar format */
a1de91e5 3243 if (format == DRM_FORMAT_NV12) {
2cd601c6 3244 if (y) /* y-plane data rate */
8d19d7d9 3245 data_rate = width * height *
a1de91e5 3246 drm_format_plane_cpp(format, 0);
2cd601c6 3247 else /* uv-plane data rate */
8d19d7d9 3248 data_rate = (width / 2) * (height / 2) *
a1de91e5 3249 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3250 } else {
3251 /* for packed formats */
3252 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3253 }
3254
8d19d7d9
KM		 3255 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3256
3257 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3258}
3259
3260/*
3261 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3262 * a 8192x4096@32bpp framebuffer:
3263 * 3 * 4096 * 8192 * 4 < 2^32
3264 */
3265static unsigned int
1e6ee542
ML		 3266skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3267 unsigned *plane_data_rate,
3268 unsigned *plane_y_data_rate)
b9cec075 3269{
9c74d826
MR		 3270 struct drm_crtc_state *cstate = &intel_cstate->base;
3271 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3272 struct drm_plane *plane;
024c9045 3273 const struct intel_plane *intel_plane;
c8fe32c1 3274 const struct drm_plane_state *pstate;
a1de91e5 3275 unsigned int rate, total_data_rate = 0;
9c74d826 3276 int id;
a6d3460e
MR		 3277
3278 if (WARN_ON(!state))
3279 return 0;
b9cec075 3280
a1de91e5 3281 /* Calculate and cache data rate for each plane */
c8fe32c1 3282 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3283 id = skl_wm_plane_id(to_intel_plane(plane));
3284 intel_plane = to_intel_plane(plane);
3285
a6d3460e
MR		 3286 /* packed/uv */
3287 rate = skl_plane_relative_data_rate(intel_cstate,
3288 pstate, 0);
1e6ee542
ML		 3289 plane_data_rate[id] = rate;
3290
3291 total_data_rate += rate;
a6d3460e
MR		 3292
3293 /* y-plane */
3294 rate = skl_plane_relative_data_rate(intel_cstate,
3295 pstate, 1);
1e6ee542 3296 plane_y_data_rate[id] = rate;
024c9045 3297
1e6ee542 3298 total_data_rate += rate;
b9cec075
DL		 3299 }
3300
3301 return total_data_rate;
3302}
3303
cbcfd14b
KM		 3304static uint16_t
3305skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3306 const int y)
3307{
3308 struct drm_framebuffer *fb = pstate->fb;
3309 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3310 uint32_t src_w, src_h;
3311 uint32_t min_scanlines = 8;
3312 uint8_t plane_bpp;
3313
3314 if (WARN_ON(!fb))
3315 return 0;
3316
3317 /* For packed formats, no y-plane, return 0 */
3318 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3319 return 0;
3320
3321 /* For Non Y-tile return 8-blocks */
3322 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3323 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3324 return 8;
3325
936e71e3
VS		 3326 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3327 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3328
bd2ef25d 3329 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3330 swap(src_w, src_h);
3331
3332 /* Halve UV plane width and height for NV12 */
3333 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3334 src_w /= 2;
3335 src_h /= 2;
3336 }
3337
3338 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3339 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3340 else
3341 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3342
bd2ef25d 3343 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3344 switch (plane_bpp) {
3345 case 1:
3346 min_scanlines = 32;
3347 break;
3348 case 2:
3349 min_scanlines = 16;
3350 break;
3351 case 4:
3352 min_scanlines = 8;
3353 break;
3354 case 8:
3355 min_scanlines = 4;
3356 break;
3357 default:
3358 WARN(1, "Unsupported pixel depth %u for rotation",
3359 plane_bpp);
3360 min_scanlines = 32;
3361 }
3362 }
3363
3364 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3365}
3366
c107acfe 3367static int
024c9045 3368skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3369 struct skl_ddb_allocation *ddb /* out */)
3370{
c107acfe 3371 struct drm_atomic_state *state = cstate->base.state;
024c9045 3372 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3373 struct drm_device *dev = crtc->dev;
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3375 struct intel_plane *intel_plane;
c107acfe 3376 struct drm_plane *plane;
c8fe32c1 3377 const struct drm_plane_state *pstate;
b9cec075 3378 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3379 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
b9cec075 3380 uint16_t alloc_size, start, cursor_blocks;
fefdd810
ML		 3381 uint16_t minimum[I915_MAX_PLANES] = {};
3382 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3383 unsigned int total_data_rate;
c107acfe
MR		 3384 int num_active;
3385 int id, i;
1e6ee542
ML		 3386 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3387 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3388
5a920b85
PZ		 3389 /* Clear the partitioning for disabled planes. */
3390 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3391 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3392
a6d3460e
MR		 3393 if (WARN_ON(!state))
3394 return 0;
3395
c107acfe 3396 if (!cstate->base.active) {
ce0ba283 3397 alloc->start = alloc->end = 0;
c107acfe
MR		 3398 return 0;
3399 }
3400
a6d3460e 3401 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3402 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3403 if (alloc_size == 0) {
3404 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3405 return 0;
b9cec075
DL		 3406 }
3407
c107acfe 3408 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3409 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3410 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3411
3412 alloc_size -= cursor_blocks;
b9cec075 3413
80958155 3414 /* 1. Allocate the mininum required blocks for each active plane */
c8fe32c1 3415 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
a6d3460e
MR		 3416 intel_plane = to_intel_plane(plane);
3417 id = skl_wm_plane_id(intel_plane);
c107acfe 3418
fefdd810 3419 if (!pstate->visible)
a6d3460e 3420 continue;
fefdd810
ML		 3421
3422 if (plane->type == DRM_PLANE_TYPE_CURSOR)
a6d3460e 3423 continue;
a6d3460e 3424
cbcfd14b
KM		 3425 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3426 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3427 }
80958155 3428
c107acfe
MR		 3429 for (i = 0; i < PLANE_CURSOR; i++) {
3430 alloc_size -= minimum[i];
3431 alloc_size -= y_minimum[i];
80958155
DL		 3432 }
3433
b9cec075 3434 /*
80958155
DL		 3435 * 2. Distribute the remaining space in proportion to the amount of
3436 * data each plane needs to fetch from memory.
b9cec075
DL		 3437 *
3438 * FIXME: we may not allocate every single block here.
3439 */
1e6ee542
ML		 3440 total_data_rate = skl_get_total_relative_data_rate(cstate,
3441 plane_data_rate,
3442 plane_y_data_rate);
a1de91e5 3443 if (total_data_rate == 0)
c107acfe 3444 return 0;
b9cec075 3445
34bb56af 3446 start = alloc->start;
1e6ee542 3447 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3448 unsigned int data_rate, y_data_rate;
3449 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3450
1e6ee542 3451 data_rate = plane_data_rate[id];
b9cec075
DL		 3452
3453 /*
2cd601c6 3454 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3455 * promote the expression to 64 bits to avoid overflowing, the
3456 * result is < available as data_rate / total_data_rate < 1
3457 */
024c9045 3458 plane_blocks = minimum[id];
80958155
DL		 3459 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3460 total_data_rate);
b9cec075 3461
c107acfe
MR		 3462 /* Leave disabled planes at (0,0) */
3463 if (data_rate) {
3464 ddb->plane[pipe][id].start = start;
3465 ddb->plane[pipe][id].end = start + plane_blocks;
3466 }
b9cec075
DL		 3467
3468 start += plane_blocks;
2cd601c6
CK		 3469
3470 /*
3471 * allocation for y_plane part of planar format:
3472 */
1e6ee542 3473 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3474
3475 y_plane_blocks = y_minimum[id];
3476 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3477 total_data_rate);
2cd601c6 3478
c107acfe
MR		 3479 if (y_data_rate) {
3480 ddb->y_plane[pipe][id].start = start;
3481 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3482 }
a1de91e5
MR		 3483
3484 start += y_plane_blocks;
b9cec075
DL		 3485 }
3486
c107acfe 3487 return 0;
b9cec075
DL		 3488}
3489
2d41c0b5
PB		 3490/*
3491 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3492 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3493 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3494 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3495*/
ac484963 3496static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3497{
3498 uint32_t wm_intermediate_val, ret;
3499
3500 if (latency == 0)
3501 return UINT_MAX;
3502
ac484963 3503 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3504 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3505
3506 return ret;
3507}
3508
3509static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3510 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3511{
d4c2aa60 3512 uint32_t ret;
d4c2aa60 3513 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3514
3515 if (latency == 0)
3516 return UINT_MAX;
3517
2d41c0b5
PB		 3518 wm_intermediate_val = latency * pixel_rate;
3519 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3520 plane_blocks_per_line;
2d41c0b5
PB		 3521
3522 return ret;
3523}
3524
9c2f7a9d
KM		 3525static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3526 struct intel_plane_state *pstate)
3527{
3528 uint64_t adjusted_pixel_rate;
3529 uint64_t downscale_amount;
3530 uint64_t pixel_rate;
3531
3532 /* Shouldn't reach here on disabled planes... */
936e71e3 3533 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3534 return 0;
3535
3536 /*
3537 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3538 * with additional adjustments for plane-specific scaling.
3539 */
cfd7e3a2 3540 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3541 downscale_amount = skl_plane_downscale_amount(pstate);
3542
3543 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3544 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3545
3546 return pixel_rate;
3547}
3548
55994c2c
MR		 3549static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3550 struct intel_crtc_state *cstate,
3551 struct intel_plane_state *intel_pstate,
3552 uint16_t ddb_allocation,
3553 int level,
3554 uint16_t *out_blocks, /* out */
3555 uint8_t *out_lines, /* out */
3556 bool *enabled /* out */)
2d41c0b5 3557{
33815fa5
MR		 3558 struct drm_plane_state *pstate = &intel_pstate->base;
3559 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3560 uint32_t latency = dev_priv->wm.skl_latency[level];
3561 uint32_t method1, method2;
3562 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3563 uint32_t res_blocks, res_lines;
3564 uint32_t selected_result;
ac484963 3565 uint8_t cpp;
a280f7dd 3566 uint32_t width = 0, height = 0;
9c2f7a9d 3567 uint32_t plane_pixel_rate;
75676ed4 3568 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3569 struct intel_atomic_state *state =
3570 to_intel_atomic_state(cstate->base.state);
3571 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3572
936e71e3 3573 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3574 *enabled = false;
3575 return 0;
3576 }
2d41c0b5 3577
ee3d532f
PZ		 3578 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3579 latency += 15;
3580
936e71e3
VS		 3581 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3582 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3583
bd2ef25d 3584 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3585 swap(width, height);
3586
ac484963 3587 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3588 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3589
61d0a04d 3590 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3591 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3592 drm_format_plane_cpp(fb->pixel_format, 1) :
3593 drm_format_plane_cpp(fb->pixel_format, 0);
3594
3595 switch (cpp) {
3596 case 1:
3597 y_min_scanlines = 16;
3598 break;
3599 case 2:
3600 y_min_scanlines = 8;
3601 break;
1186fa85
PZ		 3602 case 4:
3603 y_min_scanlines = 4;
3604 break;
86a462bc
PZ		 3605 default:
3606 MISSING_CASE(cpp);
3607 return -EINVAL;
1186fa85
PZ		 3608 }
3609 } else {
3610 y_min_scanlines = 4;
3611 }
3612
7a1a8aed
PZ		 3613 plane_bytes_per_line = width * cpp;
3614 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3615 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3616 plane_blocks_per_line =
3617 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3618 plane_blocks_per_line /= y_min_scanlines;
3619 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3620 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3621 + 1;
3622 } else {
3623 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3624 }
3625
9c2f7a9d
KM		 3626 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3627 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3628 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3629 latency,
7a1a8aed 3630 plane_blocks_per_line);
2d41c0b5 3631
75676ed4 3632 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
ee3d532f
PZ		 3633 if (apply_memory_bw_wa)
3634 y_tile_minimum *= 2;
75676ed4 3635
024c9045
MR		 3636 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3637 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3638 selected_result = max(method2, y_tile_minimum);
3639 } else {
f1db3eaf
PZ		 3640 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3641 (plane_bytes_per_line / 512 < 1))
3642 selected_result = method2;
3643 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3644 selected_result = min(method1, method2);
3645 else
3646 selected_result = method1;
3647 }
2d41c0b5 3648
d4c2aa60
TU		 3649 res_blocks = selected_result + 1;
3650 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3651
0fda6568 3652 if (level >= 1 && level <= 7) {
024c9045 3653 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3654 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3655 res_blocks += y_tile_minimum;
1186fa85 3656 res_lines += y_min_scanlines;
75676ed4 3657 } else {
0fda6568 3658 res_blocks++;
75676ed4 3659 }
0fda6568 3660 }
e6d66171 3661
55994c2c
MR		 3662 if (res_blocks >= ddb_allocation || res_lines > 31) {
3663 *enabled = false;
6b6bada7
MR		 3664
3665 /*
3666 * If there are no valid level 0 watermarks, then we can't
3667 * support this display configuration.
3668 */
3669 if (level) {
3670 return 0;
3671 } else {
3672 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3673 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3674 to_intel_crtc(cstate->base.crtc)->pipe,
3675 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3676 res_blocks, ddb_allocation, res_lines);
3677
3678 return -EINVAL;
3679 }
55994c2c 3680 }
e6d66171
DL		 3681
3682 *out_blocks = res_blocks;
3683 *out_lines = res_lines;
55994c2c 3684 *enabled = true;
2d41c0b5 3685
55994c2c 3686 return 0;
2d41c0b5
PB		 3687}
3688
f4a96752
MR		 3689static int
3690skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3691 struct skl_ddb_allocation *ddb,
3692 struct intel_crtc_state *cstate,
a62163e9 3693 struct intel_plane *intel_plane,
f4a96752
MR		 3694 int level,
3695 struct skl_wm_level *result)
2d41c0b5 3696{
f4a96752 3697 struct drm_atomic_state *state = cstate->base.state;
024c9045 3698 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3699 struct drm_plane *plane = &intel_plane->base;
3700 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3701 uint16_t ddb_blocks;
024c9045 3702 enum pipe pipe = intel_crtc->pipe;
55994c2c 3703 int ret;
a62163e9
L		 3704 int i = skl_wm_plane_id(intel_plane);
3705
3706 if (state)
3707 intel_pstate =
3708 intel_atomic_get_existing_plane_state(state,
3709 intel_plane);
024c9045 3710
f4a96752 3711 /*
a62163e9
L		 3712 * Note: If we start supporting multiple pending atomic commits against
3713 * the same planes/CRTC's in the future, plane->state will no longer be
3714 * the correct pre-state to use for the calculations here and we'll
3715 * need to change where we get the 'unchanged' plane data from.
3716 *
3717 * For now this is fine because we only allow one queued commit against
3718 * a CRTC. Even if the plane isn't modified by this transaction and we
3719 * don't have a plane lock, we still have the CRTC's lock, so we know
3720 * that no other transactions are racing with us to update it.
f4a96752 3721 */
a62163e9
L		 3722 if (!intel_pstate)
3723 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3724
a62163e9 3725 WARN_ON(!intel_pstate->base.fb);
f4a96752 3726
a62163e9 3727 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3728
a62163e9
L		 3729 ret = skl_compute_plane_wm(dev_priv,
3730 cstate,
3731 intel_pstate,
3732 ddb_blocks,
3733 level,
3734 &result->plane_res_b,
3735 &result->plane_res_l,
3736 &result->plane_en);
3737 if (ret)
3738 return ret;
f4a96752
MR		 3739
3740 return 0;
2d41c0b5
PB		 3741}
3742
407b50f3 3743static uint32_t
024c9045 3744skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3745{
30d1b5fe
PZ		 3746 uint32_t pixel_rate;
3747
024c9045 3748 if (!cstate->base.active)
407b50f3
DL		 3749 return 0;
3750
30d1b5fe
PZ		 3751 pixel_rate = ilk_pipe_pixel_rate(cstate);
3752
3753 if (WARN_ON(pixel_rate == 0))
661abfc0 3754 return 0;
407b50f3 3755
024c9045 3756 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3757 pixel_rate);
407b50f3
DL		 3758}
3759
024c9045 3760static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3761 struct skl_wm_level *trans_wm /* out */)
407b50f3 3762{
024c9045 3763 if (!cstate->base.active)
407b50f3 3764 return;
9414f563
DL		 3765
3766 /* Until we know more, just disable transition WMs */
a62163e9 3767 trans_wm->plane_en = false;
407b50f3
DL		 3768}
3769
55994c2c
MR		 3770static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3771 struct skl_ddb_allocation *ddb,
3772 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3773{
024c9045 3774 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3775 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3776 struct intel_plane *intel_plane;
3777 struct skl_plane_wm *wm;
5db94019 3778 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3779 int ret;
2d41c0b5 3780
a62163e9
L		 3781 /*
3782 * We'll only calculate watermarks for planes that are actually
3783 * enabled, so make sure all other planes are set as disabled.
3784 */
3785 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3786
3787 for_each_intel_plane_mask(&dev_priv->drm,
3788 intel_plane,
3789 cstate->base.plane_mask) {
3790 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3791
3792 for (level = 0; level <= max_level; level++) {
3793 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3794 intel_plane, level,
3795 &wm->wm[level]);
3796 if (ret)
3797 return ret;
3798 }
3799 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3800 }
024c9045 3801 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3802
55994c2c 3803 return 0;
2d41c0b5
PB		 3804}
3805
f0f59a00
VS		 3806static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3807 i915_reg_t reg,
16160e3d
DL		 3808 const struct skl_ddb_entry *entry)
3809{
3810 if (entry->end)
3811 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3812 else
3813 I915_WRITE(reg, 0);
3814}
3815
d8c0fafc 3816static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3817 i915_reg_t reg,
3818 const struct skl_wm_level *level)
3819{
3820 uint32_t val = 0;
3821
3822 if (level->plane_en) {
3823 val |= PLANE_WM_EN;
3824 val |= level->plane_res_b;
3825 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3826 }
3827
3828 I915_WRITE(reg, val);
3829}
3830
62e0fb88 3831void skl_write_plane_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3832 const struct skl_plane_wm *wm,
3833 const struct skl_ddb_allocation *ddb,
62e0fb88
L		 3834 int plane)
3835{
3836 struct drm_crtc *crtc = &intel_crtc->base;
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3839 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3840 enum pipe pipe = intel_crtc->pipe;
3841
3842 for (level = 0; level <= max_level; level++) {
d8c0fafc 3843 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3844 &wm->wm[level]);
62e0fb88 3845 }
d8c0fafc 3846 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3847 &wm->trans_wm);
27082493
L		 3848
3849 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3850 &ddb->plane[pipe][plane]);
27082493 3851 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3852 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3853}
3854
3855void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3856 const struct skl_plane_wm *wm,
3857 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3858{
3859 struct drm_crtc *crtc = &intel_crtc->base;
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3862 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3863 enum pipe pipe = intel_crtc->pipe;
3864
3865 for (level = 0; level <= max_level; level++) {
d8c0fafc 3866 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3867 &wm->wm[level]);
62e0fb88 3868 }
d8c0fafc 3869 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3870
27082493 3871 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3872 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3873}
3874
45ece230 3875bool skl_wm_level_equals(const struct skl_wm_level *l1,
3876 const struct skl_wm_level *l2)
3877{
3878 if (l1->plane_en != l2->plane_en)
3879 return false;
3880
3881 /* If both planes aren't enabled, the rest shouldn't matter */
3882 if (!l1->plane_en)
3883 return true;
3884
3885 return (l1->plane_res_l == l2->plane_res_l &&
3886 l1->plane_res_b == l2->plane_res_b);
3887}
3888
27082493
L		 3889static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3890 const struct skl_ddb_entry *b)
0e8fb7ba 3891{
27082493 3892 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3893}
3894
27082493 3895bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3896 struct intel_crtc *intel_crtc)
0e8fb7ba 3897{
ce0ba283
L		 3898 struct drm_crtc *other_crtc;
3899 struct drm_crtc_state *other_cstate;
3900 struct intel_crtc *other_intel_crtc;
3901 const struct skl_ddb_entry *ddb =
3902 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3903 int i;
0e8fb7ba 3904
ce0ba283
L		 3905 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3906 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3907
ce0ba283 3908 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3909 continue;
3910
ce0ba283 3911 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3912 return true;
0e8fb7ba
DL		 3913 }
3914
27082493 3915 return false;
0e8fb7ba
DL		 3916}
3917
55994c2c
MR		 3918static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3919 struct skl_ddb_allocation *ddb, /* out */
3920 struct skl_pipe_wm *pipe_wm, /* out */
3921 bool *changed /* out */)
2d41c0b5 3922{
f4a96752
MR		 3923 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3924 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3925 int ret;
2d41c0b5 3926
55994c2c
MR		 3927 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3928 if (ret)
3929 return ret;
2d41c0b5 3930
4e0963c7 3931 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3932 *changed = false;
3933 else
3934 *changed = true;
2d41c0b5 3935
55994c2c 3936 return 0;
2d41c0b5
PB		 3937}
3938
9b613022
MR		 3939static uint32_t
3940pipes_modified(struct drm_atomic_state *state)
3941{
3942 struct drm_crtc *crtc;
3943 struct drm_crtc_state *cstate;
3944 uint32_t i, ret = 0;
3945
3946 for_each_crtc_in_state(state, crtc, cstate, i)
3947 ret |= drm_crtc_mask(crtc);
3948
3949 return ret;
3950}
3951
bb7791bd 3952static int
7f60e200
PZ		 3953skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3954{
3955 struct drm_atomic_state *state = cstate->base.state;
3956 struct drm_device *dev = state->dev;
3957 struct drm_crtc *crtc = cstate->base.crtc;
3958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3959 struct drm_i915_private *dev_priv = to_i915(dev);
3960 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3961 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3962 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3963 struct drm_plane_state *plane_state;
3964 struct drm_plane *plane;
3965 enum pipe pipe = intel_crtc->pipe;
3966 int id;
3967
3968 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3969
220b0965 3970 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 3971 id = skl_wm_plane_id(to_intel_plane(plane));
3972
3973 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3974 &new_ddb->plane[pipe][id]) &&
3975 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3976 &new_ddb->y_plane[pipe][id]))
3977 continue;
3978
3979 plane_state = drm_atomic_get_plane_state(state, plane);
3980 if (IS_ERR(plane_state))
3981 return PTR_ERR(plane_state);
3982 }
3983
3984 return 0;
3985}
3986
98d39494
MR		 3987static int
3988skl_compute_ddb(struct drm_atomic_state *state)
3989{
3990 struct drm_device *dev = state->dev;
3991 struct drm_i915_private *dev_priv = to_i915(dev);
3992 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3993 struct intel_crtc *intel_crtc;
734fa01f 3994 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3995 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3996 int ret;
3997
3998 /*
3999 * If this is our first atomic update following hardware readout,
4000 * we can't trust the DDB that the BIOS programmed for us. Let's
4001 * pretend that all pipes switched active status so that we'll
4002 * ensure a full DDB recompute.
4003 */
1b54a880
MR		 4004 if (dev_priv->wm.distrust_bios_wm) {
4005 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4006 state->acquire_ctx);
4007 if (ret)
4008 return ret;
4009
98d39494
MR		 4010 intel_state->active_pipe_changes = ~0;
4011
1b54a880
MR		 4012 /*
4013 * We usually only initialize intel_state->active_crtcs if we
4014 * we're doing a modeset; make sure this field is always
4015 * initialized during the sanitization process that happens
4016 * on the first commit too.
4017 */
4018 if (!intel_state->modeset)
4019 intel_state->active_crtcs = dev_priv->active_crtcs;
4020 }
4021
98d39494
MR		 4022 /*
4023 * If the modeset changes which CRTC's are active, we need to
4024 * recompute the DDB allocation for *all* active pipes, even
4025 * those that weren't otherwise being modified in any way by this
4026 * atomic commit. Due to the shrinking of the per-pipe allocations
4027 * when new active CRTC's are added, it's possible for a pipe that
4028 * we were already using and aren't changing at all here to suddenly
4029 * become invalid if its DDB needs exceeds its new allocation.
4030 *
4031 * Note that if we wind up doing a full DDB recompute, we can't let
4032 * any other display updates race with this transaction, so we need
4033 * to grab the lock on *all* CRTC's.
4034 */
734fa01f 4035 if (intel_state->active_pipe_changes) {
98d39494 4036 realloc_pipes = ~0;
734fa01f
MR		 4037 intel_state->wm_results.dirty_pipes = ~0;
4038 }
98d39494 4039
5a920b85
PZ		 4040 /*
4041 * We're not recomputing for the pipes not included in the commit, so
4042 * make sure we start with the current state.
4043 */
4044 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4045
98d39494
MR		 4046 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4047 struct intel_crtc_state *cstate;
4048
4049 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4050 if (IS_ERR(cstate))
4051 return PTR_ERR(cstate);
4052
734fa01f 4053 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4054 if (ret)
4055 return ret;
05a76d3d 4056
7f60e200 4057 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4058 if (ret)
4059 return ret;
98d39494
MR		 4060 }
4061
4062 return 0;
4063}
4064
2722efb9
MR		 4065static void
4066skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4067 struct skl_wm_values *src,
4068 enum pipe pipe)
4069{
2722efb9
MR		 4070 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4071 sizeof(dst->ddb.y_plane[pipe]));
4072 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4073 sizeof(dst->ddb.plane[pipe]));
4074}
4075
413fc530 4076static void
4077skl_print_wm_changes(const struct drm_atomic_state *state)
4078{
4079 const struct drm_device *dev = state->dev;
4080 const struct drm_i915_private *dev_priv = to_i915(dev);
4081 const struct intel_atomic_state *intel_state =
4082 to_intel_atomic_state(state);
4083 const struct drm_crtc *crtc;
4084 const struct drm_crtc_state *cstate;
413fc530 4085 const struct intel_plane *intel_plane;
413fc530 4086 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4087 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4088 int id;
7570498e 4089 int i;
413fc530 4090
4091 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4092 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4093 enum pipe pipe = intel_crtc->pipe;
413fc530 4094
7570498e 4095 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4096 const struct skl_ddb_entry *old, *new;
4097
413fc530 4098 id = skl_wm_plane_id(intel_plane);
4099 old = &old_ddb->plane[pipe][id];
4100 new = &new_ddb->plane[pipe][id];
4101
413fc530 4102 if (skl_ddb_entry_equal(old, new))
4103 continue;
4104
7570498e
ML		 4105 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4106 intel_plane->base.base.id,
4107 intel_plane->base.name,
4108 old->start, old->end,
4109 new->start, new->end);
413fc530 4110 }
4111 }
4112}
4113
98d39494
MR		 4114static int
4115skl_compute_wm(struct drm_atomic_state *state)
4116{
4117 struct drm_crtc *crtc;
4118 struct drm_crtc_state *cstate;
734fa01f
MR		 4119 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4120 struct skl_wm_values *results = &intel_state->wm_results;
4121 struct skl_pipe_wm *pipe_wm;
98d39494 4122 bool changed = false;
734fa01f 4123 int ret, i;
98d39494
MR		 4124
4125 /*
4126 * If this transaction isn't actually touching any CRTC's, don't
4127 * bother with watermark calculation. Note that if we pass this
4128 * test, we're guaranteed to hold at least one CRTC state mutex,
4129 * which means we can safely use values like dev_priv->active_crtcs
4130 * since any racing commits that want to update them would need to
4131 * hold _all_ CRTC state mutexes.
4132 */
4133 for_each_crtc_in_state(state, crtc, cstate, i)
4134 changed = true;
4135 if (!changed)
4136 return 0;
4137
734fa01f
MR		 4138 /* Clear all dirty flags */
4139 results->dirty_pipes = 0;
4140
98d39494
MR		 4141 ret = skl_compute_ddb(state);
4142 if (ret)
4143 return ret;
4144
734fa01f
MR		 4145 /*
4146 * Calculate WM's for all pipes that are part of this transaction.
4147 * Note that the DDB allocation above may have added more CRTC's that
4148 * weren't otherwise being modified (and set bits in dirty_pipes) if
4149 * pipe allocations had to change.
4150 *
4151 * FIXME: Now that we're doing this in the atomic check phase, we
4152 * should allow skl_update_pipe_wm() to return failure in cases where
4153 * no suitable watermark values can be found.
4154 */
4155 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4156 struct intel_crtc_state *intel_cstate =
4157 to_intel_crtc_state(cstate);
4158
4159 pipe_wm = &intel_cstate->wm.skl.optimal;
4160 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4161 &changed);
4162 if (ret)
4163 return ret;
4164
4165 if (changed)
4166 results->dirty_pipes |= drm_crtc_mask(crtc);
4167
4168 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4169 /* This pipe's WM's did not change */
4170 continue;
4171
4172 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4173 }
4174
413fc530 4175 skl_print_wm_changes(state);
4176
98d39494
MR		 4177 return 0;
4178}
4179
2d41c0b5
PB		 4180static void skl_update_wm(struct drm_crtc *crtc)
4181{
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183 struct drm_device *dev = crtc->dev;
fac5e23e 4184 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4185 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4186 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4187 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4188 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4189 enum pipe pipe = intel_crtc->pipe;
adda50b8 4190
734fa01f 4191 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4192 return;
4193
734fa01f
MR		 4194 intel_crtc->wm.active.skl = *pipe_wm;
4195
4196 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4197
2722efb9 4198 /*
27082493
L		 4199 * If this pipe isn't active already, we're going to be enabling it
4200 * very soon. Since it's safe to update a pipe's ddb allocation while
4201 * the pipe's shut off, just do so here. Already active pipes will have
4202 * their watermarks updated once we update their planes.
2722efb9 4203 */
27082493
L		 4204 if (crtc->state->active_changed) {
4205 int plane;
4206
2c4b49a0 4207 for_each_universal_plane(dev_priv, pipe, plane)
d8c0fafc 4208 skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4209 &results->ddb, plane);
27082493 4210
d8c0fafc 4211 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4212 &results->ddb);
27082493
L		 4213 }
4214
4215 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4216
ce0ba283
L		 4217 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4218
734fa01f 4219 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4220}
4221
d890565c
VS		 4222static void ilk_compute_wm_config(struct drm_device *dev,
4223 struct intel_wm_config *config)
4224{
4225 struct intel_crtc *crtc;
4226
4227 /* Compute the currently _active_ config */
4228 for_each_intel_crtc(dev, crtc) {
4229 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4230
4231 if (!wm->pipe_enabled)
4232 continue;
4233
4234 config->sprites_enabled |= wm->sprites_enabled;
4235 config->sprites_scaled |= wm->sprites_scaled;
4236 config->num_pipes_active++;
4237 }
4238}
4239
ed4a6a7c 4240static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4241{
91c8a326 4242 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4243 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4244 struct ilk_wm_maximums max;
d890565c 4245 struct intel_wm_config config = {};
820c1980 4246 struct ilk_wm_values results = {};
77c122bc 4247 enum intel_ddb_partitioning partitioning;
261a27d1 4248
d890565c
VS		 4249 ilk_compute_wm_config(dev, &config);
4250
4251 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4252 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4253
4254 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4255 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4256 config.num_pipes_active == 1 && config.sprites_enabled) {
4257 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4258 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4259
820c1980 4260 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4261 } else {
198a1e9b 4262 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4263 }
4264
198a1e9b 4265 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4266 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4267
820c1980 4268 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4269
820c1980 4270 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4271}
4272
ed4a6a7c 4273static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4274{
ed4a6a7c
MR		 4275 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4276 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4277
ed4a6a7c 4278 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4279 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4280 ilk_program_watermarks(dev_priv);
4281 mutex_unlock(&dev_priv->wm.wm_mutex);
4282}
bf220452 4283
ed4a6a7c
MR		 4284static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4285{
4286 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4287 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4288
ed4a6a7c
MR		 4289 mutex_lock(&dev_priv->wm.wm_mutex);
4290 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4291 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4292 ilk_program_watermarks(dev_priv);
4293 }
4294 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4295}
4296
d8c0fafc 4297static inline void skl_wm_level_from_reg_val(uint32_t val,
4298 struct skl_wm_level *level)
3078999f 4299{
d8c0fafc 4300 level->plane_en = val & PLANE_WM_EN;
4301 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4302 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4303 PLANE_WM_LINES_MASK;
3078999f
PB		 4304}
4305
bf9d99ad 4306void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4307 struct skl_pipe_wm *out)
3078999f
PB		 4308{
4309 struct drm_device *dev = crtc->dev;
fac5e23e 4310 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4312 struct intel_plane *intel_plane;
d8c0fafc 4313 struct skl_plane_wm *wm;
3078999f 4314 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4315 int level, id, max_level;
4316 uint32_t val;
3078999f 4317
5db94019 4318 max_level = ilk_wm_max_level(dev_priv);
3078999f 4319
d8c0fafc 4320 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4321 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4322 wm = &out->planes[id];
3078999f 4323
d8c0fafc 4324 for (level = 0; level <= max_level; level++) {
4325 if (id != PLANE_CURSOR)
4326 val = I915_READ(PLANE_WM(pipe, id, level));
4327 else
4328 val = I915_READ(CUR_WM(pipe, level));
3078999f 4329
d8c0fafc 4330 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4331 }
3078999f 4332
d8c0fafc 4333 if (id != PLANE_CURSOR)
4334 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4335 else
4336 val = I915_READ(CUR_WM_TRANS(pipe));
4337
4338 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4339 }
4340
d8c0fafc 4341 if (!intel_crtc->active)
4342 return;
4e0963c7 4343
bf9d99ad 4344 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4345}
4346
4347void skl_wm_get_hw_state(struct drm_device *dev)
4348{
fac5e23e 4349 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4350 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4351 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4352 struct drm_crtc *crtc;
bf9d99ad 4353 struct intel_crtc *intel_crtc;
4354 struct intel_crtc_state *cstate;
3078999f 4355
a269c583 4356 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4357 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4358 intel_crtc = to_intel_crtc(crtc);
4359 cstate = to_intel_crtc_state(crtc->state);
4360
4361 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4362
4363 if (intel_crtc->active) {
4364 hw->dirty_pipes |= drm_crtc_mask(crtc);
4365 intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
4366 }
4367 }
a1de91e5 4368
279e99d7
MR		 4369 if (dev_priv->active_crtcs) {
4370 /* Fully recompute DDB on first atomic commit */
4371 dev_priv->wm.distrust_bios_wm = true;
4372 } else {
4373 /* Easy/common case; just sanitize DDB now if everything off */
4374 memset(ddb, 0, sizeof(*ddb));
4375 }
3078999f
PB		 4376}
4377
243e6a44
VS		 4378static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4379{
4380 struct drm_device *dev = crtc->dev;
fac5e23e 4381 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4382 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4384 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4385 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4386 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4387 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4388 [PIPE_A] = WM0_PIPEA_ILK,
4389 [PIPE_B] = WM0_PIPEB_ILK,
4390 [PIPE_C] = WM0_PIPEC_IVB,
4391 };
4392
4393 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4394 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4395 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4396
15606534
VS		 4397 memset(active, 0, sizeof(*active));
4398
3ef00284 4399 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4400
4401 if (active->pipe_enabled) {
243e6a44
VS		 4402 u32 tmp = hw->wm_pipe[pipe];
4403
4404 /*
4405 * For active pipes LP0 watermark is marked as
4406 * enabled, and LP1+ watermaks as disabled since
4407 * we can't really reverse compute them in case
4408 * multiple pipes are active.
4409 */
4410 active->wm[0].enable = true;
4411 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4412 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4413 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4414 active->linetime = hw->wm_linetime[pipe];
4415 } else {
5db94019 4416 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4417
4418 /*
4419 * For inactive pipes, all watermark levels
4420 * should be marked as enabled but zeroed,
4421 * which is what we'd compute them to.
4422 */
4423 for (level = 0; level <= max_level; level++)
4424 active->wm[level].enable = true;
4425 }
4e0963c7
MR		 4426
4427 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4428}
4429
6eb1a681
VS		 4430#define _FW_WM(value, plane) \
4431 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4432#define _FW_WM_VLV(value, plane) \
4433 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4434
4435static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4436 struct vlv_wm_values *wm)
4437{
4438 enum pipe pipe;
4439 uint32_t tmp;
4440
4441 for_each_pipe(dev_priv, pipe) {
4442 tmp = I915_READ(VLV_DDL(pipe));
4443
4444 wm->ddl[pipe].primary =
4445 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4446 wm->ddl[pipe].cursor =
4447 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4448 wm->ddl[pipe].sprite[0] =
4449 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4450 wm->ddl[pipe].sprite[1] =
4451 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4452 }
4453
4454 tmp = I915_READ(DSPFW1);
4455 wm->sr.plane = _FW_WM(tmp, SR);
4456 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4457 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4458 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4459
4460 tmp = I915_READ(DSPFW2);
4461 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4462 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4463 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4464
4465 tmp = I915_READ(DSPFW3);
4466 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4467
4468 if (IS_CHERRYVIEW(dev_priv)) {
4469 tmp = I915_READ(DSPFW7_CHV);
4470 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4471 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4472
4473 tmp = I915_READ(DSPFW8_CHV);
4474 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4475 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4476
4477 tmp = I915_READ(DSPFW9_CHV);
4478 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4479 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4480
4481 tmp = I915_READ(DSPHOWM);
4482 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4483 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4484 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4485 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4486 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4487 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4488 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4489 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4490 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4491 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4492 } else {
4493 tmp = I915_READ(DSPFW7);
4494 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4495 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4496
4497 tmp = I915_READ(DSPHOWM);
4498 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4499 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4500 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4501 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4502 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4503 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4504 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4505 }
4506}
4507
4508#undef _FW_WM
4509#undef _FW_WM_VLV
4510
4511void vlv_wm_get_hw_state(struct drm_device *dev)
4512{
4513 struct drm_i915_private *dev_priv = to_i915(dev);
4514 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4515 struct intel_plane *plane;
4516 enum pipe pipe;
4517 u32 val;
4518
4519 vlv_read_wm_values(dev_priv, wm);
4520
4521 for_each_intel_plane(dev, plane) {
4522 switch (plane->base.type) {
4523 int sprite;
4524 case DRM_PLANE_TYPE_CURSOR:
4525 plane->wm.fifo_size = 63;
4526 break;
4527 case DRM_PLANE_TYPE_PRIMARY:
4528 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4529 break;
4530 case DRM_PLANE_TYPE_OVERLAY:
4531 sprite = plane->plane;
4532 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4533 break;
4534 }
4535 }
4536
4537 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4538 wm->level = VLV_WM_LEVEL_PM2;
4539
4540 if (IS_CHERRYVIEW(dev_priv)) {
4541 mutex_lock(&dev_priv->rps.hw_lock);
4542
4543 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4544 if (val & DSP_MAXFIFO_PM5_ENABLE)
4545 wm->level = VLV_WM_LEVEL_PM5;
4546
58590c14
VS		 4547 /*
4548 * If DDR DVFS is disabled in the BIOS, Punit
4549 * will never ack the request. So if that happens
4550 * assume we don't have to enable/disable DDR DVFS
4551 * dynamically. To test that just set the REQ_ACK
4552 * bit to poke the Punit, but don't change the
4553 * HIGH/LOW bits so that we don't actually change
4554 * the current state.
4555 */
6eb1a681 4556 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4557 val |= FORCE_DDR_FREQ_REQ_ACK;
4558 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4559
4560 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4561 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4562 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4563 "assuming DDR DVFS is disabled\n");
4564 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4565 } else {
4566 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4567 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4568 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4569 }
6eb1a681
VS		 4570
4571 mutex_unlock(&dev_priv->rps.hw_lock);
4572 }
4573
4574 for_each_pipe(dev_priv, pipe)
4575 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4576 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4577 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4578
4579 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4580 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4581}
4582
243e6a44
VS		 4583void ilk_wm_get_hw_state(struct drm_device *dev)
4584{
fac5e23e 4585 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4586 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4587 struct drm_crtc *crtc;
4588
70e1e0ec 4589 for_each_crtc(dev, crtc)
243e6a44
VS		 4590 ilk_pipe_wm_get_hw_state(crtc);
4591
4592 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4593 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4594 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4595
4596 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4597 if (INTEL_INFO(dev)->gen >= 7) {
4598 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4599 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4600 }
243e6a44 4601
8652744b 4602 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4603 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4604 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4605 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4606 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4607 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4608
4609 hw->enable_fbc_wm =
4610 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4611}
4612
b445e3b0
ED		 4613/**
4614 * intel_update_watermarks - update FIFO watermark values based on current modes
4615 *
4616 * Calculate watermark values for the various WM regs based on current mode
4617 * and plane configuration.
4618 *
4619 * There are several cases to deal with here:
4620 * - normal (i.e. non-self-refresh)
4621 * - self-refresh (SR) mode
4622 * - lines are large relative to FIFO size (buffer can hold up to 2)
4623 * - lines are small relative to FIFO size (buffer can hold more than 2
4624 * lines), so need to account for TLB latency
4625 *
4626 * The normal calculation is:
4627 * watermark = dotclock * bytes per pixel * latency
4628 * where latency is platform & configuration dependent (we assume pessimal
4629 * values here).
4630 *
4631 * The SR calculation is:
4632 * watermark = (trunc(latency/line time)+1) * surface width *
4633 * bytes per pixel
4634 * where
4635 * line time = htotal / dotclock
4636 * surface width = hdisplay for normal plane and 64 for cursor
4637 * and latency is assumed to be high, as above.
4638 *
4639 * The final value programmed to the register should always be rounded up,
4640 * and include an extra 2 entries to account for clock crossings.
4641 *
4642 * We don't use the sprite, so we can ignore that. And on Crestline we have
4643 * to set the non-SR watermarks to 8.
4644 */
46ba614c 4645void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4646{
fac5e23e 4647 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4648
4649 if (dev_priv->display.update_wm)
46ba614c 4650 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4651}
4652
e2828914 4653/*
9270388e 4654 * Lock protecting IPS related data structures
9270388e
DV		 4655 */
4656DEFINE_SPINLOCK(mchdev_lock);
4657
4658/* Global for IPS driver to get at the current i915 device. Protected by
4659 * mchdev_lock. */
4660static struct drm_i915_private *i915_mch_dev;
4661
91d14251 4662bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4663{
2b4e57bd
ED		 4664 u16 rgvswctl;
4665
9270388e
DV		 4666 assert_spin_locked(&mchdev_lock);
4667
2b4e57bd
ED		 4668 rgvswctl = I915_READ16(MEMSWCTL);
4669 if (rgvswctl & MEMCTL_CMD_STS) {
4670 DRM_DEBUG("gpu busy, RCS change rejected\n");
4671 return false; /* still busy with another command */
4672 }
4673
4674 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4675 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4676 I915_WRITE16(MEMSWCTL, rgvswctl);
4677 POSTING_READ16(MEMSWCTL);
4678
4679 rgvswctl |= MEMCTL_CMD_STS;
4680 I915_WRITE16(MEMSWCTL, rgvswctl);
4681
4682 return true;
4683}
4684
91d14251 4685static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4686{
84f1b20f 4687 u32 rgvmodectl;
2b4e57bd
ED		 4688 u8 fmax, fmin, fstart, vstart;
4689
9270388e
DV		 4690 spin_lock_irq(&mchdev_lock);
4691
84f1b20f
TU		 4692 rgvmodectl = I915_READ(MEMMODECTL);
4693
2b4e57bd
ED		 4694 /* Enable temp reporting */
4695 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4696 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4697
4698 /* 100ms RC evaluation intervals */
4699 I915_WRITE(RCUPEI, 100000);
4700 I915_WRITE(RCDNEI, 100000);
4701
4702 /* Set max/min thresholds to 90ms and 80ms respectively */
4703 I915_WRITE(RCBMAXAVG, 90000);
4704 I915_WRITE(RCBMINAVG, 80000);
4705
4706 I915_WRITE(MEMIHYST, 1);
4707
4708 /* Set up min, max, and cur for interrupt handling */
4709 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4710 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4711 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4712 MEMMODE_FSTART_SHIFT;
4713
616847e7 4714 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4715 PXVFREQ_PX_SHIFT;
4716
20e4d407
DV		 4717 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4718 dev_priv->ips.fstart = fstart;
2b4e57bd 4719
20e4d407
DV		 4720 dev_priv->ips.max_delay = fstart;
4721 dev_priv->ips.min_delay = fmin;
4722 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4723
4724 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4725 fmax, fmin, fstart);
4726
4727 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4728
4729 /*
4730 * Interrupts will be enabled in ironlake_irq_postinstall
4731 */
4732
4733 I915_WRITE(VIDSTART, vstart);
4734 POSTING_READ(VIDSTART);
4735
4736 rgvmodectl |= MEMMODE_SWMODE_EN;
4737 I915_WRITE(MEMMODECTL, rgvmodectl);
4738
9270388e 4739 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4740 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4741 mdelay(1);
2b4e57bd 4742
91d14251 4743 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4744
7d81c3e0
VS		 4745 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4746 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4747 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4748 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4749 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4750
4751 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4752}
4753
91d14251 4754static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4755{
9270388e
DV		 4756 u16 rgvswctl;
4757
4758 spin_lock_irq(&mchdev_lock);
4759
4760 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4761
4762 /* Ack interrupts, disable EFC interrupt */
4763 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4764 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4765 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4766 I915_WRITE(DEIIR, DE_PCU_EVENT);
4767 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4768
4769 /* Go back to the starting frequency */
91d14251 4770 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4771 mdelay(1);
2b4e57bd
ED		 4772 rgvswctl |= MEMCTL_CMD_STS;
4773 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4774 mdelay(1);
2b4e57bd 4775
9270388e 4776 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4777}
4778
acbe9475
DV		 4779/* There's a funny hw issue where the hw returns all 0 when reading from
4780 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4781 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4782 * all limits and the gpu stuck at whatever frequency it is at atm).
4783 */
74ef1173 4784static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4785{
7b9e0ae6 4786 u32 limits;
2b4e57bd 4787
20b46e59
DV		 4788 /* Only set the down limit when we've reached the lowest level to avoid
4789 * getting more interrupts, otherwise leave this clear. This prevents a
4790 * race in the hw when coming out of rc6: There's a tiny window where
4791 * the hw runs at the minimal clock before selecting the desired
4792 * frequency, if the down threshold expires in that window we will not
4793 * receive a down interrupt. */
2d1fe073 4794 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4795 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4796 if (val <= dev_priv->rps.min_freq_softlimit)
4797 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4798 } else {
4799 limits = dev_priv->rps.max_freq_softlimit << 24;
4800 if (val <= dev_priv->rps.min_freq_softlimit)
4801 limits |= dev_priv->rps.min_freq_softlimit << 16;
4802 }
20b46e59
DV		 4803
4804 return limits;
4805}
4806
dd75fdc8
CW		 4807static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4808{
4809 int new_power;
8a586437
AG		 4810 u32 threshold_up = 0, threshold_down = 0; /* in % */
4811 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4812
4813 new_power = dev_priv->rps.power;
4814 switch (dev_priv->rps.power) {
4815 case LOW_POWER:
a72b5623
CW		 4816 if (val > dev_priv->rps.efficient_freq + 1 &&
4817 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4818 new_power = BETWEEN;
4819 break;
4820
4821 case BETWEEN:
a72b5623
CW		 4822 if (val <= dev_priv->rps.efficient_freq &&
4823 val < dev_priv->rps.cur_freq)
dd75fdc8 4824 new_power = LOW_POWER;
a72b5623
CW		 4825 else if (val >= dev_priv->rps.rp0_freq &&
4826 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4827 new_power = HIGH_POWER;
4828 break;
4829
4830 case HIGH_POWER:
a72b5623
CW		 4831 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4832 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4833 new_power = BETWEEN;
4834 break;
4835 }
4836 /* Max/min bins are special */
aed242ff 4837 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4838 new_power = LOW_POWER;
aed242ff 4839 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4840 new_power = HIGH_POWER;
4841 if (new_power == dev_priv->rps.power)
4842 return;
4843
4844 /* Note the units here are not exactly 1us, but 1280ns. */
4845 switch (new_power) {
4846 case LOW_POWER:
4847 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4848 ei_up = 16000;
4849 threshold_up = 95;
dd75fdc8
CW		 4850
4851 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4852 ei_down = 32000;
4853 threshold_down = 85;
dd75fdc8
CW		 4854 break;
4855
4856 case BETWEEN:
4857 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4858 ei_up = 13000;
4859 threshold_up = 90;
dd75fdc8
CW		 4860
4861 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4862 ei_down = 32000;
4863 threshold_down = 75;
dd75fdc8
CW		 4864 break;
4865
4866 case HIGH_POWER:
4867 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4868 ei_up = 10000;
4869 threshold_up = 85;
dd75fdc8
CW		 4870
4871 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4872 ei_down = 32000;
4873 threshold_down = 60;
dd75fdc8
CW		 4874 break;
4875 }
4876
8a586437 4877 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4878 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4879 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4880 GT_INTERVAL_FROM_US(dev_priv,
4881 ei_up * threshold_up / 100));
8a586437
AG		 4882
4883 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4884 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4885 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4886 GT_INTERVAL_FROM_US(dev_priv,
4887 ei_down * threshold_down / 100));
4888
4889 I915_WRITE(GEN6_RP_CONTROL,
4890 GEN6_RP_MEDIA_TURBO |
4891 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4892 GEN6_RP_MEDIA_IS_GFX |
4893 GEN6_RP_ENABLE |
4894 GEN6_RP_UP_BUSY_AVG |
4895 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4896
dd75fdc8 4897 dev_priv->rps.power = new_power;
8fb55197
CW		 4898 dev_priv->rps.up_threshold = threshold_up;
4899 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4900 dev_priv->rps.last_adj = 0;
4901}
4902
2876ce73
CW		 4903static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4904{
4905 u32 mask = 0;
4906
4907 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4908 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4909 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4910 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4911
7b3c29f6
CW		 4912 mask &= dev_priv->pm_rps_events;
4913
59d02a1f 4914 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4915}
4916
b8a5ff8d
JM		 4917/* gen6_set_rps is called to update the frequency request, but should also be
4918 * called when the range (min_delay and max_delay) is modified so that we can
4919 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4920static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4921{
23eafea6 4922 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4923 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4924 return;
4925
4fc688ce 4926 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4927 WARN_ON(val > dev_priv->rps.max_freq);
4928 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4929
eb64cad1
CW		 4930 /* min/max delay may still have been modified so be sure to
4931 * write the limits value.
4932 */
4933 if (val != dev_priv->rps.cur_freq) {
4934 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4935
dc97997a 4936 if (IS_GEN9(dev_priv))
5704195c
AG		 4937 I915_WRITE(GEN6_RPNSWREQ,
4938 GEN9_FREQUENCY(val));
dc97997a 4939 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4940 I915_WRITE(GEN6_RPNSWREQ,
4941 HSW_FREQUENCY(val));
4942 else
4943 I915_WRITE(GEN6_RPNSWREQ,
4944 GEN6_FREQUENCY(val) |
4945 GEN6_OFFSET(0) |
4946 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4947 }
7b9e0ae6 4948
7b9e0ae6
CW		 4949 /* Make sure we continue to get interrupts
4950 * until we hit the minimum or maximum frequencies.
4951 */
74ef1173 4952 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4953 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4954
d5570a72
BW		 4955 POSTING_READ(GEN6_RPNSWREQ);
4956
b39fb297 4957 dev_priv->rps.cur_freq = val;
0f94592e 4958 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4959}
4960
dc97997a 4961static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4962{
ffe02b40 4963 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4964 WARN_ON(val > dev_priv->rps.max_freq);
4965 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4966
dc97997a 4967 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4968 "Odd GPU freq value\n"))
4969 val &= ~1;
4970
cd25dd5b
D		 4971 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4972
8fb55197 4973 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4974 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4975 if (!IS_CHERRYVIEW(dev_priv))
4976 gen6_set_rps_thresholds(dev_priv, val);
4977 }
ffe02b40 4978
ffe02b40
VS		 4979 dev_priv->rps.cur_freq = val;
4980 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4981}
4982
a7f6e231 4983/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4984 *
4985 * * If Gfx is Idle, then
a7f6e231
D		 4986 * 1. Forcewake Media well.
4987 * 2. Request idle freq.
4988 * 3. Release Forcewake of Media well.
76c3552f
D		 4989*/
4990static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4991{
aed242ff 4992 u32 val = dev_priv->rps.idle_freq;
5549d25f 4993
aed242ff 4994 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4995 return;
4996
a7f6e231
D		 4997 /* Wake up the media well, as that takes a lot less
4998 * power than the Render well. */
4999 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5000 valleyview_set_rps(dev_priv, val);
a7f6e231 5001 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5002}
5003
43cf3bf0
CW		 5004void gen6_rps_busy(struct drm_i915_private *dev_priv)
5005{
5006 mutex_lock(&dev_priv->rps.hw_lock);
5007 if (dev_priv->rps.enabled) {
5008 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5009 gen6_rps_reset_ei(dev_priv);
5010 I915_WRITE(GEN6_PMINTRMSK,
5011 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5012
c33d247d
CW		 5013 gen6_enable_rps_interrupts(dev_priv);
5014
2b83c4c4
MW		 5015 /* Ensure we start at the user's desired frequency */
5016 intel_set_rps(dev_priv,
5017 clamp(dev_priv->rps.cur_freq,
5018 dev_priv->rps.min_freq_softlimit,
5019 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5020 }
5021 mutex_unlock(&dev_priv->rps.hw_lock);
5022}
5023
b29c19b6
CW		 5024void gen6_rps_idle(struct drm_i915_private *dev_priv)
5025{
c33d247d
CW		 5026 /* Flush our bottom-half so that it does not race with us
5027 * setting the idle frequency and so that it is bounded by
5028 * our rpm wakeref. And then disable the interrupts to stop any
5029 * futher RPS reclocking whilst we are asleep.
5030 */
5031 gen6_disable_rps_interrupts(dev_priv);
5032
b29c19b6 5033 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5034 if (dev_priv->rps.enabled) {
dc97997a 5035 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5036 vlv_set_rps_idle(dev_priv);
7526ed79 5037 else
dc97997a 5038 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5039 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5040 I915_WRITE(GEN6_PMINTRMSK,
5041 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5042 }
8d3afd7d 5043 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5044
8d3afd7d 5045 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5046 while (!list_empty(&dev_priv->rps.clients))
5047 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5048 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5049}
5050
1854d5ca 5051void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5052 struct intel_rps_client *rps,
5053 unsigned long submitted)
b29c19b6 5054{
8d3afd7d
CW		 5055 /* This is intentionally racy! We peek at the state here, then
5056 * validate inside the RPS worker.
5057 */
67d97da3 5058 if (!(dev_priv->gt.awake &&
8d3afd7d 5059 dev_priv->rps.enabled &&
29ecd78d 5060 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5061 return;
43cf3bf0 5062
e61b9958
CW		 5063 /* Force a RPS boost (and don't count it against the client) if
5064 * the GPU is severely congested.
5065 */
d0bc54f2 5066 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5067 rps = NULL;
5068
8d3afd7d
CW		 5069 spin_lock(&dev_priv->rps.client_lock);
5070 if (rps == NULL || list_empty(&rps->link)) {
5071 spin_lock_irq(&dev_priv->irq_lock);
5072 if (dev_priv->rps.interrupts_enabled) {
5073 dev_priv->rps.client_boost = true;
c33d247d 5074 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5075 }
5076 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5077
2e1b8730
CW		 5078 if (rps != NULL) {
5079 list_add(&rps->link, &dev_priv->rps.clients);
5080 rps->boosts++;
1854d5ca
CW		 5081 } else
5082 dev_priv->rps.boosts++;
c0951f0c 5083 }
8d3afd7d 5084 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5085}
5086
dc97997a 5087void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5088{
dc97997a
CW		 5089 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5090 valleyview_set_rps(dev_priv, val);
ffe02b40 5091 else
dc97997a 5092 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5093}
5094
dc97997a 5095static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5096{
20e49366 5097 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5098 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5099}
5100
dc97997a 5101static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5102{
2030d684
AG		 5103 I915_WRITE(GEN6_RP_CONTROL, 0);
5104}
5105
dc97997a 5106static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5107{
d20d4f0c 5108 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5109 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5110 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5111}
5112
dc97997a 5113static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5114{
38807746
D		 5115 I915_WRITE(GEN6_RC_CONTROL, 0);
5116}
5117
dc97997a 5118static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5119{
98a2e5f9
D		 5120 /* we're doing forcewake before Disabling RC6,
5121 * This what the BIOS expects when going into suspend */
59bad947 5122 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5123
44fc7d5c 5124 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5125
59bad947 5126 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5127}
5128
dc97997a 5129static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5130{
dc97997a 5131 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5132 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5133 mode = GEN6_RC_CTL_RC6_ENABLE;
5134 else
5135 mode = 0;
5136 }
dc97997a 5137 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5138 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5139 "RC6 %s RC6p %s RC6pp %s\n",
5140 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5141 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5142 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5143
5144 else
b99d49cc
ID		 5145 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5146 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5147}
5148
dc97997a 5149static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5150{
72e96d64 5151 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5152 bool enable_rc6 = true;
5153 unsigned long rc6_ctx_base;
fc619841
ID		 5154 u32 rc_ctl;
5155 int rc_sw_target;
5156
5157 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5158 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5159 RC_SW_TARGET_STATE_SHIFT;
5160 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5161 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5162 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5163 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5164 rc_sw_target);
274008e8
SAK		 5165
5166 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5167 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5168 enable_rc6 = false;
5169 }
5170
5171 /*
5172 * The exact context size is not known for BXT, so assume a page size
5173 * for this check.
5174 */
5175 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5176 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5177 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5178 ggtt->stolen_reserved_size))) {
b99d49cc 5179 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5180 enable_rc6 = false;
5181 }
5182
5183 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5184 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5185 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5186 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5187 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5188 enable_rc6 = false;
5189 }
5190
fc619841
ID		 5191 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5192 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5193 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5194 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5195 enable_rc6 = false;
5196 }
5197
5198 if (!I915_READ(GEN6_GFXPAUSE)) {
5199 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5200 enable_rc6 = false;
5201 }
5202
5203 if (!I915_READ(GEN8_MISC_CTRL0)) {
5204 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5205 enable_rc6 = false;
5206 }
5207
5208 return enable_rc6;
5209}
5210
dc97997a 5211int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5212{
e7d66d89 5213 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5214 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5215 return 0;
5216
274008e8
SAK		 5217 if (!enable_rc6)
5218 return 0;
5219
dc97997a 5220 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5221 DRM_INFO("RC6 disabled by BIOS\n");
5222 return 0;
5223 }
5224
456470eb 5225 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5226 if (enable_rc6 >= 0) {
5227 int mask;
5228
dc97997a 5229 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5230 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5231 INTEL_RC6pp_ENABLE;
5232 else
5233 mask = INTEL_RC6_ENABLE;
5234
5235 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5236 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5237 "(requested %d, valid %d)\n",
5238 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5239
5240 return enable_rc6 & mask;
5241 }
2b4e57bd 5242
dc97997a 5243 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5244 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5245
5246 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5247}
5248
dc97997a 5249static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5250{
5251 /* All of these values are in units of 50MHz */
773ea9a8 5252
93ee2920 5253 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5254 if (IS_BROXTON(dev_priv)) {
773ea9a8 5255 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5256 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5257 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5258 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5259 } else {
773ea9a8 5260 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5261 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5262 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5263 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5264 }
3280e8b0 5265 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5266 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5267
93ee2920 5268 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5269 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5270 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5271 u32 ddcc_status = 0;
5272
5273 if (sandybridge_pcode_read(dev_priv,
5274 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5275 &ddcc_status) == 0)
93ee2920 5276 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5277 clamp_t(u8,
5278 ((ddcc_status >> 8) & 0xff),
5279 dev_priv->rps.min_freq,
5280 dev_priv->rps.max_freq);
93ee2920
TR		 5281 }
5282
dc97997a 5283 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5284 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5285 * the natural hardware unit for SKL
5286 */
c5e0688c
AG		 5287 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5288 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5289 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5290 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5291 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5292 }
3280e8b0
BW		 5293}
5294
3a45b05c
CW		 5295static void reset_rps(struct drm_i915_private *dev_priv,
5296 void (*set)(struct drm_i915_private *, u8))
5297{
5298 u8 freq = dev_priv->rps.cur_freq;
5299
5300 /* force a reset */
5301 dev_priv->rps.power = -1;
5302 dev_priv->rps.cur_freq = -1;
5303
5304 set(dev_priv, freq);
5305}
5306
b6fef0ef 5307/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5308static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5309{
b6fef0ef
JB		 5310 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5311
23eafea6 5312 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5313 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5314 /*
5315 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5316 * clear out the Control register just to avoid inconsitency
5317 * with debugfs interface, which will show Turbo as enabled
5318 * only and that is not expected by the User after adding the
5319 * WaGsvDisableTurbo. Apart from this there is no problem even
5320 * if the Turbo is left enabled in the Control register, as the
5321 * Up/Down interrupts would remain masked.
5322 */
dc97997a 5323 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5324 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5325 return;
5326 }
5327
0beb059a
AG		 5328 /* Program defaults and thresholds for RPS*/
5329 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5330 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5331
5332 /* 1 second timeout*/
5333 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5334 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5335
b6fef0ef 5336 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5337
0beb059a
AG		 5338 /* Leaning on the below call to gen6_set_rps to program/setup the
5339 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5340 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5341 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5342
5343 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5344}
5345
dc97997a 5346static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5347{
e2f80391 5348 struct intel_engine_cs *engine;
3b3f1650 5349 enum intel_engine_id id;
20e49366 5350 uint32_t rc6_mask = 0;
20e49366
ZW		 5351
5352 /* 1a: Software RC state - RC0 */
5353 I915_WRITE(GEN6_RC_STATE, 0);
5354
5355 /* 1b: Get forcewake during program sequence. Although the driver
5356 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5358
5359 /* 2a: Disable RC states. */
5360 I915_WRITE(GEN6_RC_CONTROL, 0);
5361
5362 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5363
5364 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5365 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5366 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5367 else
5368 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5369 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5370 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5371 for_each_engine(engine, dev_priv, id)
e2f80391 5372 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5373
1a3d1898 5374 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5375 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5376
20e49366 5377 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5378
38c23527
ZW		 5379 /* 2c: Program Coarse Power Gating Policies. */
5380 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5381 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5382
20e49366 5383 /* 3a: Enable RC6 */
dc97997a 5384 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5385 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5386 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5387 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5388 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5389 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5390 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5391 GEN7_RC_CTL_TO_MODE |
5392 rc6_mask);
3e7732a0
SAK		 5393 } else {
5394 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5395 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5396 GEN6_RC_CTL_EI_MODE(1) |
5397 rc6_mask);
3e7732a0 5398 }
20e49366 5399
cb07bae0
SK		 5400 /*
5401 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5402 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5403 */
dc97997a 5404 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5405 I915_WRITE(GEN9_PG_ENABLE, 0);
5406 else
5407 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5408 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5409
59bad947 5410 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5411}
5412
dc97997a 5413static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5414{
e2f80391 5415 struct intel_engine_cs *engine;
3b3f1650 5416 enum intel_engine_id id;
93ee2920 5417 uint32_t rc6_mask = 0;
6edee7f3
BW		 5418
5419 /* 1a: Software RC state - RC0 */
5420 I915_WRITE(GEN6_RC_STATE, 0);
5421
5422 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5423 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5424 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5425
5426 /* 2a: Disable RC states. */
5427 I915_WRITE(GEN6_RC_CONTROL, 0);
5428
6edee7f3
BW		 5429 /* 2b: Program RC6 thresholds.*/
5430 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5431 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5432 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5433 for_each_engine(engine, dev_priv, id)
e2f80391 5434 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5435 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5436 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5437 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5438 else
5439 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5440
5441 /* 3: Enable RC6 */
dc97997a 5442 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5443 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5444 intel_print_rc6_info(dev_priv, rc6_mask);
5445 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5446 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5447 GEN7_RC_CTL_TO_MODE |
5448 rc6_mask);
5449 else
5450 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5451 GEN6_RC_CTL_EI_MODE(1) |
5452 rc6_mask);
6edee7f3
BW		 5453
5454 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5455 I915_WRITE(GEN6_RPNSWREQ,
5456 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5457 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5458 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5459 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5460 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5461
5462 /* Docs recommend 900MHz, and 300 MHz respectively */
5463 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5464 dev_priv->rps.max_freq_softlimit << 24 |
5465 dev_priv->rps.min_freq_softlimit << 16);
5466
5467 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5468 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5469 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5470 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5471
5472 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5473
5474 /* 5: Enable RPS */
7526ed79
DV		 5475 I915_WRITE(GEN6_RP_CONTROL,
5476 GEN6_RP_MEDIA_TURBO |
5477 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5478 GEN6_RP_MEDIA_IS_GFX |
5479 GEN6_RP_ENABLE |
5480 GEN6_RP_UP_BUSY_AVG |
5481 GEN6_RP_DOWN_IDLE_AVG);
5482
5483 /* 6: Ring frequency + overclocking (our driver does this later */
5484
3a45b05c 5485 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5486
59bad947 5487 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5488}
5489
dc97997a 5490static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5491{
e2f80391 5492 struct intel_engine_cs *engine;
3b3f1650 5493 enum intel_engine_id id;
99ac9612 5494 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5495 u32 gtfifodbg;
2b4e57bd 5496 int rc6_mode;
b4ac5afc 5497 int ret;
2b4e57bd 5498
4fc688ce 5499 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5500
2b4e57bd
ED		 5501 /* Here begins a magic sequence of register writes to enable
5502 * auto-downclocking.
5503 *
5504 * Perhaps there might be some value in exposing these to
5505 * userspace...
5506 */
5507 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5508
5509 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5510 gtfifodbg = I915_READ(GTFIFODBG);
5511 if (gtfifodbg) {
2b4e57bd
ED		 5512 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5513 I915_WRITE(GTFIFODBG, gtfifodbg);
5514 }
5515
59bad947 5516 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5517
5518 /* disable the counters and set deterministic thresholds */
5519 I915_WRITE(GEN6_RC_CONTROL, 0);
5520
5521 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5522 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5523 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5524 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5525 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5526
3b3f1650 5527 for_each_engine(engine, dev_priv, id)
e2f80391 5528 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5529
5530 I915_WRITE(GEN6_RC_SLEEP, 0);
5531 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5532 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5533 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5534 else
5535 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5536 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5537 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5538
5a7dc92a 5539 /* Check if we are enabling RC6 */
dc97997a 5540 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5541 if (rc6_mode & INTEL_RC6_ENABLE)
5542 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5543
5a7dc92a 5544 /* We don't use those on Haswell */
dc97997a 5545 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5546 if (rc6_mode & INTEL_RC6p_ENABLE)
5547 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5548
5a7dc92a
ED		 5549 if (rc6_mode & INTEL_RC6pp_ENABLE)
5550 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5551 }
2b4e57bd 5552
dc97997a 5553 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5554
5555 I915_WRITE(GEN6_RC_CONTROL,
5556 rc6_mask |
5557 GEN6_RC_CTL_EI_MODE(1) |
5558 GEN6_RC_CTL_HW_ENABLE);
5559
dd75fdc8
CW		 5560 /* Power down if completely idle for over 50ms */
5561 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5562 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5563
3a45b05c 5564 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5565
31643d54
BW		 5566 rc6vids = 0;
5567 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5568 if (IS_GEN6(dev_priv) && ret) {
31643d54 5569 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5570 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5571 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5572 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5573 rc6vids &= 0xffff00;
5574 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5575 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5576 if (ret)
5577 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5578 }
5579
59bad947 5580 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5581}
5582
fb7404e8 5583static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5584{
5585 int min_freq = 15;
3ebecd07
CW		 5586 unsigned int gpu_freq;
5587 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5588 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5589 int scaling_factor = 180;
eda79642 5590 struct cpufreq_policy *policy;
2b4e57bd 5591
4fc688ce 5592 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5593
eda79642
BW		 5594 policy = cpufreq_cpu_get(0);
5595 if (policy) {
5596 max_ia_freq = policy->cpuinfo.max_freq;
5597 cpufreq_cpu_put(policy);
5598 } else {
5599 /*
5600 * Default to measured freq if none found, PCU will ensure we
5601 * don't go over
5602 */
2b4e57bd 5603 max_ia_freq = tsc_khz;
eda79642 5604 }
2b4e57bd
ED		 5605
5606 /* Convert from kHz to MHz */
5607 max_ia_freq /= 1000;
5608
153b4b95 5609 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5610 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5611 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5612
dc97997a 5613 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5614 /* Convert GT frequency to 50 HZ units */
5615 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5616 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5617 } else {
5618 min_gpu_freq = dev_priv->rps.min_freq;
5619 max_gpu_freq = dev_priv->rps.max_freq;
5620 }
5621
2b4e57bd
ED		 5622 /*
5623 * For each potential GPU frequency, load a ring frequency we'd like
5624 * to use for memory access. We do this by specifying the IA frequency
5625 * the PCU should use as a reference to determine the ring frequency.
5626 */
4c8c7743
AG		 5627 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5628 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5629 unsigned int ia_freq = 0, ring_freq = 0;
5630
dc97997a 5631 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5632 /*
5633 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5634 * No floor required for ring frequency on SKL.
5635 */
5636 ring_freq = gpu_freq;
dc97997a 5637 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5638 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5639 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5640 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5641 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5642 ring_freq = max(min_ring_freq, ring_freq);
5643 /* leave ia_freq as the default, chosen by cpufreq */
5644 } else {
5645 /* On older processors, there is no separate ring
5646 * clock domain, so in order to boost the bandwidth
5647 * of the ring, we need to upclock the CPU (ia_freq).
5648 *
5649 * For GPU frequencies less than 750MHz,
5650 * just use the lowest ring freq.
5651 */
5652 if (gpu_freq < min_freq)
5653 ia_freq = 800;
5654 else
5655 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5656 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5657 }
2b4e57bd 5658
42c0526c
BW		 5659 sandybridge_pcode_write(dev_priv,
5660 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5661 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5662 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5663 gpu_freq);
2b4e57bd 5664 }
2b4e57bd
ED		 5665}
5666
03af2045 5667static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5668{
5669 u32 val, rp0;
5670
5b5929cb 5671 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5672
43b67998 5673 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5674 case 8:
5675 /* (2 * 4) config */
5676 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5677 break;
5678 case 12:
5679 /* (2 * 6) config */
5680 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5681 break;
5682 case 16:
5683 /* (2 * 8) config */
5684 default:
5685 /* Setting (2 * 8) Min RP0 for any other combination */
5686 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5687 break;
095acd5f 5688 }
5b5929cb
JN		 5689
5690 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5691
2b6b3a09
D		 5692 return rp0;
5693}
5694
5695static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5696{
5697 u32 val, rpe;
5698
5699 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5700 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5701
5702 return rpe;
5703}
5704
7707df4a
D		 5705static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5706{
5707 u32 val, rp1;
5708
5b5929cb
JN		 5709 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5710 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5711
7707df4a
D		 5712 return rp1;
5713}
5714
f8f2b001
D		 5715static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5716{
5717 u32 val, rp1;
5718
5719 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5720
5721 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5722
5723 return rp1;
5724}
5725
03af2045 5726static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5727{
5728 u32 val, rp0;
5729
64936258 5730 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5731
5732 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5733 /* Clamp to max */
5734 rp0 = min_t(u32, rp0, 0xea);
5735
5736 return rp0;
5737}
5738
5739static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5740{
5741 u32 val, rpe;
5742
64936258 5743 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5744 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5745 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5746 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5747
5748 return rpe;
5749}
5750
03af2045 5751static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5752{
36146035
ID		 5753 u32 val;
5754
5755 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5756 /*
5757 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5758 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5759 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5760 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5761 * to make sure it matches what Punit accepts.
5762 */
5763 return max_t(u32, val, 0xc0);
0a073b84
JB		 5764}
5765
ae48434c
ID		 5766/* Check that the pctx buffer wasn't move under us. */
5767static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5768{
5769 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5770
5771 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5772 dev_priv->vlv_pctx->stolen->start);
5773}
5774
38807746
D		 5775
5776/* Check that the pcbr address is not empty. */
5777static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5778{
5779 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5780
5781 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5782}
5783
dc97997a 5784static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5785{
62106b4f 5786 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5787 unsigned long pctx_paddr, paddr;
38807746
D		 5788 u32 pcbr;
5789 int pctx_size = 32*1024;
5790
38807746
D		 5791 pcbr = I915_READ(VLV_PCBR);
5792 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5793 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5794 paddr = (dev_priv->mm.stolen_base +
62106b4f 5795 (ggtt->stolen_size - pctx_size));
38807746
D		 5796
5797 pctx_paddr = (paddr & (~4095));
5798 I915_WRITE(VLV_PCBR, pctx_paddr);
5799 }
ce611ef8
VS		 5800
5801 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5802}
5803
dc97997a 5804static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5805{
c9cddffc
JB		 5806 struct drm_i915_gem_object *pctx;
5807 unsigned long pctx_paddr;
5808 u32 pcbr;
5809 int pctx_size = 24*1024;
5810
5811 pcbr = I915_READ(VLV_PCBR);
5812 if (pcbr) {
5813 /* BIOS set it up already, grab the pre-alloc'd space */
5814 int pcbr_offset;
5815
5816 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5817 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5818 pcbr_offset,
190d6cd5 5819 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5820 pctx_size);
5821 goto out;
5822 }
5823
ce611ef8
VS		 5824 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5825
c9cddffc
JB		 5826 /*
5827 * From the Gunit register HAS:
5828 * The Gfx driver is expected to program this register and ensure
5829 * proper allocation within Gfx stolen memory. For example, this
5830 * register should be programmed such than the PCBR range does not
5831 * overlap with other ranges, such as the frame buffer, protected
5832 * memory, or any other relevant ranges.
5833 */
91c8a326 5834 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5835 if (!pctx) {
5836 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5837 goto out;
c9cddffc
JB		 5838 }
5839
5840 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5841 I915_WRITE(VLV_PCBR, pctx_paddr);
5842
5843out:
ce611ef8 5844 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5845 dev_priv->vlv_pctx = pctx;
5846}
5847
dc97997a 5848static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5849{
ae48434c
ID		 5850 if (WARN_ON(!dev_priv->vlv_pctx))
5851 return;
5852
f0cd5182 5853 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5854 dev_priv->vlv_pctx = NULL;
5855}
5856
c30fec65
VS		 5857static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5858{
5859 dev_priv->rps.gpll_ref_freq =
5860 vlv_get_cck_clock(dev_priv, "GPLL ref",
5861 CCK_GPLL_CLOCK_CONTROL,
5862 dev_priv->czclk_freq);
5863
5864 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5865 dev_priv->rps.gpll_ref_freq);
5866}
5867
dc97997a 5868static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5869{
2bb25c17 5870 u32 val;
4e80519e 5871
dc97997a 5872 valleyview_setup_pctx(dev_priv);
4e80519e 5873
c30fec65
VS		 5874 vlv_init_gpll_ref_freq(dev_priv);
5875
2bb25c17
VS		 5876 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5877 switch ((val >> 6) & 3) {
5878 case 0:
5879 case 1:
5880 dev_priv->mem_freq = 800;
5881 break;
5882 case 2:
5883 dev_priv->mem_freq = 1066;
5884 break;
5885 case 3:
5886 dev_priv->mem_freq = 1333;
5887 break;
5888 }
80b83b62 5889 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5890
4e80519e
ID		 5891 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5892 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5893 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5894 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5895 dev_priv->rps.max_freq);
5896
5897 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5898 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5899 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5900 dev_priv->rps.efficient_freq);
5901
f8f2b001
D		 5902 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5903 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5904 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5905 dev_priv->rps.rp1_freq);
5906
4e80519e
ID		 5907 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5908 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5909 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5910 dev_priv->rps.min_freq);
4e80519e
ID		 5911}
5912
dc97997a 5913static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5914{
2bb25c17 5915 u32 val;
2b6b3a09 5916
dc97997a 5917 cherryview_setup_pctx(dev_priv);
2b6b3a09 5918
c30fec65
VS		 5919 vlv_init_gpll_ref_freq(dev_priv);
5920
a580516d 5921 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5922 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5923 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5924
2bb25c17 5925 switch ((val >> 2) & 0x7) {
2bb25c17 5926 case 3:
2bb25c17
VS		 5927 dev_priv->mem_freq = 2000;
5928 break;
bfa7df01 5929 default:
2bb25c17
VS		 5930 dev_priv->mem_freq = 1600;
5931 break;
5932 }
80b83b62 5933 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5934
2b6b3a09
D		 5935 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5936 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5937 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5938 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5939 dev_priv->rps.max_freq);
5940
5941 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5942 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5943 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5944 dev_priv->rps.efficient_freq);
5945
7707df4a
D		 5946 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5947 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5948 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5949 dev_priv->rps.rp1_freq);
5950
5b7c91b7
D		 5951 /* PUnit validated range is only [RPe, RP0] */
5952 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5953 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5954 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5955 dev_priv->rps.min_freq);
5956
1c14762d
VS		 5957 WARN_ONCE((dev_priv->rps.max_freq |
5958 dev_priv->rps.efficient_freq |
5959 dev_priv->rps.rp1_freq |
5960 dev_priv->rps.min_freq) & 1,
5961 "Odd GPU freq values\n");
38807746
D		 5962}
5963
dc97997a 5964static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5965{
dc97997a 5966 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5967}
5968
dc97997a 5969static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5970{
e2f80391 5971 struct intel_engine_cs *engine;
3b3f1650 5972 enum intel_engine_id id;
2b6b3a09 5973 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5974
5975 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5976
297b32ec
VS		 5977 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5978 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5979 if (gtfifodbg) {
5980 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5981 gtfifodbg);
5982 I915_WRITE(GTFIFODBG, gtfifodbg);
5983 }
5984
5985 cherryview_check_pctx(dev_priv);
5986
5987 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5988 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5989 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5990
160614a2
VS		 5991 /* Disable RC states. */
5992 I915_WRITE(GEN6_RC_CONTROL, 0);
5993
38807746
D		 5994 /* 2a: Program RC6 thresholds.*/
5995 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5996 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5997 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5998
3b3f1650 5999 for_each_engine(engine, dev_priv, id)
e2f80391 6000 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6001 I915_WRITE(GEN6_RC_SLEEP, 0);
6002
f4f71c7d
D		 6003 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6004 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6005
6006 /* allows RC6 residency counter to work */
6007 I915_WRITE(VLV_COUNTER_CONTROL,
6008 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6009 VLV_MEDIA_RC6_COUNT_EN |
6010 VLV_RENDER_RC6_COUNT_EN));
6011
6012 /* For now we assume BIOS is allocating and populating the PCBR */
6013 pcbr = I915_READ(VLV_PCBR);
6014
38807746 6015 /* 3: Enable RC6 */
dc97997a
CW		 6016 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6017 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6018 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6019
6020 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6021
2b6b3a09 6022 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6023 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6024 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6025 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6026 I915_WRITE(GEN6_RP_UP_EI, 66000);
6027 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6028
6029 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6030
6031 /* 5: Enable RPS */
6032 I915_WRITE(GEN6_RP_CONTROL,
6033 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6034 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6035 GEN6_RP_ENABLE |
6036 GEN6_RP_UP_BUSY_AVG |
6037 GEN6_RP_DOWN_IDLE_AVG);
6038
3ef62342
D		 6039 /* Setting Fixed Bias */
6040 val = VLV_OVERRIDE_EN |
6041 VLV_SOC_TDP_EN |
6042 CHV_BIAS_CPU_50_SOC_50;
6043 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6044
2b6b3a09
D		 6045 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6046
8d40c3ae
VS		 6047 /* RPS code assumes GPLL is used */
6048 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6049
742f491d 6050 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6051 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6052
3a45b05c 6053 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6054
59bad947 6055 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6056}
6057
dc97997a 6058static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6059{
e2f80391 6060 struct intel_engine_cs *engine;
3b3f1650 6061 enum intel_engine_id id;
2a5913a8 6062 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6063
6064 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6065
ae48434c
ID		 6066 valleyview_check_pctx(dev_priv);
6067
297b32ec
VS		 6068 gtfifodbg = I915_READ(GTFIFODBG);
6069 if (gtfifodbg) {
f7d85c1e
JB		 6070 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6071 gtfifodbg);
0a073b84
JB		 6072 I915_WRITE(GTFIFODBG, gtfifodbg);
6073 }
6074
c8d9a590 6075 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6076 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6077
160614a2
VS		 6078 /* Disable RC states. */
6079 I915_WRITE(GEN6_RC_CONTROL, 0);
6080
cad725fe 6081 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6082 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6083 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6084 I915_WRITE(GEN6_RP_UP_EI, 66000);
6085 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6086
6087 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6088
6089 I915_WRITE(GEN6_RP_CONTROL,
6090 GEN6_RP_MEDIA_TURBO |
6091 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6092 GEN6_RP_MEDIA_IS_GFX |
6093 GEN6_RP_ENABLE |
6094 GEN6_RP_UP_BUSY_AVG |
6095 GEN6_RP_DOWN_IDLE_CONT);
6096
6097 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6098 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6099 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6100
3b3f1650 6101 for_each_engine(engine, dev_priv, id)
e2f80391 6102 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6103
2f0aa304 6104 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6105
6106 /* allows RC6 residency counter to work */
49798eb2 6107 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6108 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6109 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6110 VLV_MEDIA_RC6_COUNT_EN |
6111 VLV_RENDER_RC6_COUNT_EN));
31685c25 6112
dc97997a 6113 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6114 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6115
dc97997a 6116 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6117
a2b23fe0 6118 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6119
3ef62342
D		 6120 /* Setting Fixed Bias */
6121 val = VLV_OVERRIDE_EN |
6122 VLV_SOC_TDP_EN |
6123 VLV_BIAS_CPU_125_SOC_875;
6124 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6125
64936258 6126 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6127
8d40c3ae
VS		 6128 /* RPS code assumes GPLL is used */
6129 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6130
742f491d 6131 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6132 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6133
3a45b05c 6134 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6135
59bad947 6136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6137}
6138
dde18883
ED		 6139static unsigned long intel_pxfreq(u32 vidfreq)
6140{
6141 unsigned long freq;
6142 int div = (vidfreq & 0x3f0000) >> 16;
6143 int post = (vidfreq & 0x3000) >> 12;
6144 int pre = (vidfreq & 0x7);
6145
6146 if (!pre)
6147 return 0;
6148
6149 freq = ((div * 133333) / ((1<<post) * pre));
6150
6151 return freq;
6152}
6153
eb48eb00
DV		 6154static const struct cparams {
6155 u16 i;
6156 u16 t;
6157 u16 m;
6158 u16 c;
6159} cparams[] = {
6160 { 1, 1333, 301, 28664 },
6161 { 1, 1066, 294, 24460 },
6162 { 1, 800, 294, 25192 },
6163 { 0, 1333, 276, 27605 },
6164 { 0, 1066, 276, 27605 },
6165 { 0, 800, 231, 23784 },
6166};
6167
f531dcb2 6168static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6169{
6170 u64 total_count, diff, ret;
6171 u32 count1, count2, count3, m = 0, c = 0;
6172 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6173 int i;
6174
02d71956
DV		 6175 assert_spin_locked(&mchdev_lock);
6176
20e4d407 6177 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6178
6179 /* Prevent division-by-zero if we are asking too fast.
6180 * Also, we don't get interesting results if we are polling
6181 * faster than once in 10ms, so just return the saved value
6182 * in such cases.
6183 */
6184 if (diff1 <= 10)
20e4d407 6185 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6186
6187 count1 = I915_READ(DMIEC);
6188 count2 = I915_READ(DDREC);
6189 count3 = I915_READ(CSIEC);
6190
6191 total_count = count1 + count2 + count3;
6192
6193 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6194 if (total_count < dev_priv->ips.last_count1) {
6195 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6196 diff += total_count;
6197 } else {
20e4d407 6198 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6199 }
6200
6201 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6202 if (cparams[i].i == dev_priv->ips.c_m &&
6203 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6204 m = cparams[i].m;
6205 c = cparams[i].c;
6206 break;
6207 }
6208 }
6209
6210 diff = div_u64(diff, diff1);
6211 ret = ((m * diff) + c);
6212 ret = div_u64(ret, 10);
6213
20e4d407
DV		 6214 dev_priv->ips.last_count1 = total_count;
6215 dev_priv->ips.last_time1 = now;
eb48eb00 6216
20e4d407 6217 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6218
6219 return ret;
6220}
6221
f531dcb2
CW		 6222unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6223{
6224 unsigned long val;
6225
dc97997a 6226 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6227 return 0;
6228
6229 spin_lock_irq(&mchdev_lock);
6230
6231 val = __i915_chipset_val(dev_priv);
6232
6233 spin_unlock_irq(&mchdev_lock);
6234
6235 return val;
6236}
6237
eb48eb00
DV		 6238unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6239{
6240 unsigned long m, x, b;
6241 u32 tsfs;
6242
6243 tsfs = I915_READ(TSFS);
6244
6245 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6246 x = I915_READ8(TR1);
6247
6248 b = tsfs & TSFS_INTR_MASK;
6249
6250 return ((m * x) / 127) - b;
6251}
6252
d972d6ee
MK		 6253static int _pxvid_to_vd(u8 pxvid)
6254{
6255 if (pxvid == 0)
6256 return 0;
6257
6258 if (pxvid >= 8 && pxvid < 31)
6259 pxvid = 31;
6260
6261 return (pxvid + 2) * 125;
6262}
6263
6264static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6265{
d972d6ee
MK		 6266 const int vd = _pxvid_to_vd(pxvid);
6267 const int vm = vd - 1125;
6268
dc97997a 6269 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6270 return vm > 0 ? vm : 0;
6271
6272 return vd;
eb48eb00
DV		 6273}
6274
02d71956 6275static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6276{
5ed0bdf2 6277 u64 now, diff, diffms;
eb48eb00
DV		 6278 u32 count;
6279
02d71956 6280 assert_spin_locked(&mchdev_lock);
eb48eb00 6281
5ed0bdf2
TG		 6282 now = ktime_get_raw_ns();
6283 diffms = now - dev_priv->ips.last_time2;
6284 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6285
6286 /* Don't divide by 0 */
eb48eb00
DV		 6287 if (!diffms)
6288 return;
6289
6290 count = I915_READ(GFXEC);
6291
20e4d407
DV		 6292 if (count < dev_priv->ips.last_count2) {
6293 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6294 diff += count;
6295 } else {
20e4d407 6296 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6297 }
6298
20e4d407
DV		 6299 dev_priv->ips.last_count2 = count;
6300 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6301
6302 /* More magic constants... */
6303 diff = diff * 1181;
6304 diff = div_u64(diff, diffms * 10);
20e4d407 6305 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6306}
6307
02d71956
DV		 6308void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6309{
dc97997a 6310 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6311 return;
6312
9270388e 6313 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6314
6315 __i915_update_gfx_val(dev_priv);
6316
9270388e 6317 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6318}
6319
f531dcb2 6320static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6321{
6322 unsigned long t, corr, state1, corr2, state2;
6323 u32 pxvid, ext_v;
6324
02d71956
DV		 6325 assert_spin_locked(&mchdev_lock);
6326
616847e7 6327 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6328 pxvid = (pxvid >> 24) & 0x7f;
6329 ext_v = pvid_to_extvid(dev_priv, pxvid);
6330
6331 state1 = ext_v;
6332
6333 t = i915_mch_val(dev_priv);
6334
6335 /* Revel in the empirically derived constants */
6336
6337 /* Correction factor in 1/100000 units */
6338 if (t > 80)
6339 corr = ((t * 2349) + 135940);
6340 else if (t >= 50)
6341 corr = ((t * 964) + 29317);
6342 else /* < 50 */
6343 corr = ((t * 301) + 1004);
6344
6345 corr = corr * ((150142 * state1) / 10000 - 78642);
6346 corr /= 100000;
20e4d407 6347 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6348
6349 state2 = (corr2 * state1) / 10000;
6350 state2 /= 100; /* convert to mW */
6351
02d71956 6352 __i915_update_gfx_val(dev_priv);
eb48eb00 6353
20e4d407 6354 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6355}
6356
f531dcb2
CW		 6357unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6358{
6359 unsigned long val;
6360
dc97997a 6361 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6362 return 0;
6363
6364 spin_lock_irq(&mchdev_lock);
6365
6366 val = __i915_gfx_val(dev_priv);
6367
6368 spin_unlock_irq(&mchdev_lock);
6369
6370 return val;
6371}
6372
eb48eb00
DV		 6373/**
6374 * i915_read_mch_val - return value for IPS use
6375 *
6376 * Calculate and return a value for the IPS driver to use when deciding whether
6377 * we have thermal and power headroom to increase CPU or GPU power budget.
6378 */
6379unsigned long i915_read_mch_val(void)
6380{
6381 struct drm_i915_private *dev_priv;
6382 unsigned long chipset_val, graphics_val, ret = 0;
6383
9270388e 6384 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6385 if (!i915_mch_dev)
6386 goto out_unlock;
6387 dev_priv = i915_mch_dev;
6388
f531dcb2
CW		 6389 chipset_val = __i915_chipset_val(dev_priv);
6390 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6391
6392 ret = chipset_val + graphics_val;
6393
6394out_unlock:
9270388e 6395 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6396
6397 return ret;
6398}
6399EXPORT_SYMBOL_GPL(i915_read_mch_val);
6400
6401/**
6402 * i915_gpu_raise - raise GPU frequency limit
6403 *
6404 * Raise the limit; IPS indicates we have thermal headroom.
6405 */
6406bool i915_gpu_raise(void)
6407{
6408 struct drm_i915_private *dev_priv;
6409 bool ret = true;
6410
9270388e 6411 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6412 if (!i915_mch_dev) {
6413 ret = false;
6414 goto out_unlock;
6415 }
6416 dev_priv = i915_mch_dev;
6417
20e4d407
DV		 6418 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6419 dev_priv->ips.max_delay--;
eb48eb00
DV		 6420
6421out_unlock:
9270388e 6422 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6423
6424 return ret;
6425}
6426EXPORT_SYMBOL_GPL(i915_gpu_raise);
6427
6428/**
6429 * i915_gpu_lower - lower GPU frequency limit
6430 *
6431 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6432 * frequency maximum.
6433 */
6434bool i915_gpu_lower(void)
6435{
6436 struct drm_i915_private *dev_priv;
6437 bool ret = true;
6438
9270388e 6439 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6440 if (!i915_mch_dev) {
6441 ret = false;
6442 goto out_unlock;
6443 }
6444 dev_priv = i915_mch_dev;
6445
20e4d407
DV		 6446 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6447 dev_priv->ips.max_delay++;
eb48eb00
DV		 6448
6449out_unlock:
9270388e 6450 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6451
6452 return ret;
6453}
6454EXPORT_SYMBOL_GPL(i915_gpu_lower);
6455
6456/**
6457 * i915_gpu_busy - indicate GPU business to IPS
6458 *
6459 * Tell the IPS driver whether or not the GPU is busy.
6460 */
6461bool i915_gpu_busy(void)
6462{
eb48eb00
DV		 6463 bool ret = false;
6464
9270388e 6465 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6466 if (i915_mch_dev)
6467 ret = i915_mch_dev->gt.awake;
9270388e 6468 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6469
6470 return ret;
6471}
6472EXPORT_SYMBOL_GPL(i915_gpu_busy);
6473
6474/**
6475 * i915_gpu_turbo_disable - disable graphics turbo
6476 *
6477 * Disable graphics turbo by resetting the max frequency and setting the
6478 * current frequency to the default.
6479 */
6480bool i915_gpu_turbo_disable(void)
6481{
6482 struct drm_i915_private *dev_priv;
6483 bool ret = true;
6484
9270388e 6485 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6486 if (!i915_mch_dev) {
6487 ret = false;
6488 goto out_unlock;
6489 }
6490 dev_priv = i915_mch_dev;
6491
20e4d407 6492 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6493
91d14251 6494 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6495 ret = false;
6496
6497out_unlock:
9270388e 6498 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6499
6500 return ret;
6501}
6502EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6503
6504/**
6505 * Tells the intel_ips driver that the i915 driver is now loaded, if
6506 * IPS got loaded first.
6507 *
6508 * This awkward dance is so that neither module has to depend on the
6509 * other in order for IPS to do the appropriate communication of
6510 * GPU turbo limits to i915.
6511 */
6512static void
6513ips_ping_for_i915_load(void)
6514{
6515 void (*link)(void);
6516
6517 link = symbol_get(ips_link_to_i915_driver);
6518 if (link) {
6519 link();
6520 symbol_put(ips_link_to_i915_driver);
6521 }
6522}
6523
6524void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6525{
02d71956
DV		 6526 /* We only register the i915 ips part with intel-ips once everything is
6527 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6528 spin_lock_irq(&mchdev_lock);
eb48eb00 6529 i915_mch_dev = dev_priv;
9270388e 6530 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6531
6532 ips_ping_for_i915_load();
6533}
6534
6535void intel_gpu_ips_teardown(void)
6536{
9270388e 6537 spin_lock_irq(&mchdev_lock);
eb48eb00 6538 i915_mch_dev = NULL;
9270388e 6539 spin_unlock_irq(&mchdev_lock);
eb48eb00 6540}
76c3552f 6541
dc97997a 6542static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6543{
dde18883
ED		 6544 u32 lcfuse;
6545 u8 pxw[16];
6546 int i;
6547
6548 /* Disable to program */
6549 I915_WRITE(ECR, 0);
6550 POSTING_READ(ECR);
6551
6552 /* Program energy weights for various events */
6553 I915_WRITE(SDEW, 0x15040d00);
6554 I915_WRITE(CSIEW0, 0x007f0000);
6555 I915_WRITE(CSIEW1, 0x1e220004);
6556 I915_WRITE(CSIEW2, 0x04000004);
6557
6558 for (i = 0; i < 5; i++)
616847e7 6559 I915_WRITE(PEW(i), 0);
dde18883 6560 for (i = 0; i < 3; i++)
616847e7 6561 I915_WRITE(DEW(i), 0);
dde18883
ED		 6562
6563 /* Program P-state weights to account for frequency power adjustment */
6564 for (i = 0; i < 16; i++) {
616847e7 6565 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6566 unsigned long freq = intel_pxfreq(pxvidfreq);
6567 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6568 PXVFREQ_PX_SHIFT;
6569 unsigned long val;
6570
6571 val = vid * vid;
6572 val *= (freq / 1000);
6573 val *= 255;
6574 val /= (127*127*900);
6575 if (val > 0xff)
6576 DRM_ERROR("bad pxval: %ld\n", val);
6577 pxw[i] = val;
6578 }
6579 /* Render standby states get 0 weight */
6580 pxw[14] = 0;
6581 pxw[15] = 0;
6582
6583 for (i = 0; i < 4; i++) {
6584 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6585 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6586 I915_WRITE(PXW(i), val);
dde18883
ED		 6587 }
6588
6589 /* Adjust magic regs to magic values (more experimental results) */
6590 I915_WRITE(OGW0, 0);
6591 I915_WRITE(OGW1, 0);
6592 I915_WRITE(EG0, 0x00007f00);
6593 I915_WRITE(EG1, 0x0000000e);
6594 I915_WRITE(EG2, 0x000e0000);
6595 I915_WRITE(EG3, 0x68000300);
6596 I915_WRITE(EG4, 0x42000000);
6597 I915_WRITE(EG5, 0x00140031);
6598 I915_WRITE(EG6, 0);
6599 I915_WRITE(EG7, 0);
6600
6601 for (i = 0; i < 8; i++)
616847e7 6602 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6603
6604 /* Enable PMON + select events */
6605 I915_WRITE(ECR, 0x80000019);
6606
6607 lcfuse = I915_READ(LCFUSE02);
6608
20e4d407 6609 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6610}
6611
dc97997a 6612void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6613{
b268c699
ID		 6614 /*
6615 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6616 * requirement.
6617 */
6618 if (!i915.enable_rc6) {
6619 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6620 intel_runtime_pm_get(dev_priv);
6621 }
e6069ca8 6622
b5163dbb 6623 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6624 mutex_lock(&dev_priv->rps.hw_lock);
6625
6626 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6627 if (IS_CHERRYVIEW(dev_priv))
6628 cherryview_init_gt_powersave(dev_priv);
6629 else if (IS_VALLEYVIEW(dev_priv))
6630 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6631 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6632 gen6_init_rps_frequencies(dev_priv);
6633
6634 /* Derive initial user preferences/limits from the hardware limits */
6635 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6636 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6637
6638 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6639 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6640
6641 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6642 dev_priv->rps.min_freq_softlimit =
6643 max_t(int,
6644 dev_priv->rps.efficient_freq,
6645 intel_freq_opcode(dev_priv, 450));
6646
99ac9612
CW		 6647 /* After setting max-softlimit, find the overclock max freq */
6648 if (IS_GEN6(dev_priv) ||
6649 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6650 u32 params = 0;
6651
6652 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6653 if (params & BIT(31)) { /* OC supported */
6654 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6655 (dev_priv->rps.max_freq & 0xff) * 50,
6656 (params & 0xff) * 50);
6657 dev_priv->rps.max_freq = params & 0xff;
6658 }
6659 }
6660
29ecd78d
CW		 6661 /* Finally allow us to boost to max by default */
6662 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6663
773ea9a8 6664 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6665 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6666
6667 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6668}
6669
dc97997a 6670void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6671{
8dac1e1f 6672 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6673 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6674
6675 if (!i915.enable_rc6)
6676 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6677}
6678
54b4f68f
CW		 6679/**
6680 * intel_suspend_gt_powersave - suspend PM work and helper threads
6681 * @dev_priv: i915 device
6682 *
6683 * We don't want to disable RC6 or other features here, we just want
6684 * to make sure any work we've queued has finished and won't bother
6685 * us while we're suspended.
6686 */
6687void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6688{
6689 if (INTEL_GEN(dev_priv) < 6)
6690 return;
6691
6692 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6693 intel_runtime_pm_put(dev_priv);
6694
6695 /* gen6_rps_idle() will be called later to disable interrupts */
6696}
6697
b7137e0c
CW		 6698void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6699{
6700 dev_priv->rps.enabled = true; /* force disabling */
6701 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6702
6703 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6704}
6705
dc97997a 6706void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6707{
b7137e0c
CW		 6708 if (!READ_ONCE(dev_priv->rps.enabled))
6709 return;
e494837a 6710
b7137e0c 6711 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6712
b7137e0c
CW		 6713 if (INTEL_GEN(dev_priv) >= 9) {
6714 gen9_disable_rc6(dev_priv);
6715 gen9_disable_rps(dev_priv);
6716 } else if (IS_CHERRYVIEW(dev_priv)) {
6717 cherryview_disable_rps(dev_priv);
6718 } else if (IS_VALLEYVIEW(dev_priv)) {
6719 valleyview_disable_rps(dev_priv);
6720 } else if (INTEL_GEN(dev_priv) >= 6) {
6721 gen6_disable_rps(dev_priv);
6722 } else if (IS_IRONLAKE_M(dev_priv)) {
6723 ironlake_disable_drps(dev_priv);
930ebb46 6724 }
b7137e0c
CW		 6725
6726 dev_priv->rps.enabled = false;
6727 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6728}
6729
b7137e0c 6730void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6731{
54b4f68f
CW		 6732 /* We shouldn't be disabling as we submit, so this should be less
6733 * racy than it appears!
6734 */
b7137e0c
CW		 6735 if (READ_ONCE(dev_priv->rps.enabled))
6736 return;
1a01ab3b 6737
b7137e0c
CW		 6738 /* Powersaving is controlled by the host when inside a VM */
6739 if (intel_vgpu_active(dev_priv))
6740 return;
0a073b84 6741
b7137e0c 6742 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6743
6744 if (IS_CHERRYVIEW(dev_priv)) {
6745 cherryview_enable_rps(dev_priv);
6746 } else if (IS_VALLEYVIEW(dev_priv)) {
6747 valleyview_enable_rps(dev_priv);
b7137e0c 6748 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6749 gen9_enable_rc6(dev_priv);
6750 gen9_enable_rps(dev_priv);
6751 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6752 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6753 } else if (IS_BROADWELL(dev_priv)) {
6754 gen8_enable_rps(dev_priv);
fb7404e8 6755 gen6_update_ring_freq(dev_priv);
b7137e0c 6756 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6757 gen6_enable_rps(dev_priv);
fb7404e8 6758 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6759 } else if (IS_IRONLAKE_M(dev_priv)) {
6760 ironlake_enable_drps(dev_priv);
6761 intel_init_emon(dev_priv);
0a073b84 6762 }
aed242ff
CW		 6763
6764 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6765 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6766
6767 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6768 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6769
54b4f68f 6770 dev_priv->rps.enabled = true;
b7137e0c
CW		 6771 mutex_unlock(&dev_priv->rps.hw_lock);
6772}
3cc134e3 6773
54b4f68f
CW		 6774static void __intel_autoenable_gt_powersave(struct work_struct *work)
6775{
6776 struct drm_i915_private *dev_priv =
6777 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6778 struct intel_engine_cs *rcs;
6779 struct drm_i915_gem_request *req;
6780
6781 if (READ_ONCE(dev_priv->rps.enabled))
6782 goto out;
6783
3b3f1650 6784 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6785 if (rcs->last_context)
6786 goto out;
6787
6788 if (!rcs->init_context)
6789 goto out;
6790
6791 mutex_lock(&dev_priv->drm.struct_mutex);
6792
6793 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6794 if (IS_ERR(req))
6795 goto unlock;
6796
6797 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6798 rcs->init_context(req);
6799
6800 /* Mark the device busy, calling intel_enable_gt_powersave() */
6801 i915_add_request_no_flush(req);
6802
6803unlock:
6804 mutex_unlock(&dev_priv->drm.struct_mutex);
6805out:
6806 intel_runtime_pm_put(dev_priv);
6807}
6808
6809void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6810{
6811 if (READ_ONCE(dev_priv->rps.enabled))
6812 return;
6813
6814 if (IS_IRONLAKE_M(dev_priv)) {
6815 ironlake_enable_drps(dev_priv);
54b4f68f 6816 intel_init_emon(dev_priv);
54b4f68f
CW		 6817 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6818 /*
6819 * PCU communication is slow and this doesn't need to be
6820 * done at any specific time, so do this out of our fast path
6821 * to make resume and init faster.
6822 *
6823 * We depend on the HW RC6 power context save/restore
6824 * mechanism when entering D3 through runtime PM suspend. So
6825 * disable RPM until RPS/RC6 is properly setup. We can only
6826 * get here via the driver load/system resume/runtime resume
6827 * paths, so the _noresume version is enough (and in case of
6828 * runtime resume it's necessary).
6829 */
6830 if (queue_delayed_work(dev_priv->wq,
6831 &dev_priv->rps.autoenable_work,
6832 round_jiffies_up_relative(HZ)))
6833 intel_runtime_pm_get_noresume(dev_priv);
6834 }
6835}
6836
3107bd48
DV		 6837static void ibx_init_clock_gating(struct drm_device *dev)
6838{
fac5e23e 6839 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6840
6841 /*
6842 * On Ibex Peak and Cougar Point, we need to disable clock
6843 * gating for the panel power sequencer or it will fail to
6844 * start up when no ports are active.
6845 */
6846 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6847}
6848
0e088b8f
VS		 6849static void g4x_disable_trickle_feed(struct drm_device *dev)
6850{
fac5e23e 6851 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6852 enum pipe pipe;
0e088b8f 6853
055e393f 6854 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6855 I915_WRITE(DSPCNTR(pipe),
6856 I915_READ(DSPCNTR(pipe)) |
6857 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6858
6859 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6860 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6861 }
6862}
6863
017636cc
VS		 6864static void ilk_init_lp_watermarks(struct drm_device *dev)
6865{
fac5e23e 6866 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6867
6868 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6869 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6870 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6871
6872 /*
6873 * Don't touch WM1S_LP_EN here.
6874 * Doing so could cause underruns.
6875 */
6876}
6877
1fa61106 6878static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6879{
fac5e23e 6880 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6881 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6882
f1e8fa56
DL		 6883 /*
6884 * Required for FBC
6885 * WaFbcDisableDpfcClockGating:ilk
6886 */
4d47e4f5
DL		 6887 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6888 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6889 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6890
6891 I915_WRITE(PCH_3DCGDIS0,
6892 MARIUNIT_CLOCK_GATE_DISABLE |
6893 SVSMUNIT_CLOCK_GATE_DISABLE);
6894 I915_WRITE(PCH_3DCGDIS1,
6895 VFMUNIT_CLOCK_GATE_DISABLE);
6896
6f1d69b0
ED		 6897 /*
6898 * According to the spec the following bits should be set in
6899 * order to enable memory self-refresh
6900 * The bit 22/21 of 0x42004
6901 * The bit 5 of 0x42020
6902 * The bit 15 of 0x45000
6903 */
6904 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6905 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6906 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6907 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6908 I915_WRITE(DISP_ARB_CTL,
6909 (I915_READ(DISP_ARB_CTL) |
6910 DISP_FBC_WM_DIS));
017636cc
VS		 6911
6912 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6913
6914 /*
6915 * Based on the document from hardware guys the following bits
6916 * should be set unconditionally in order to enable FBC.
6917 * The bit 22 of 0x42000
6918 * The bit 22 of 0x42004
6919 * The bit 7,8,9 of 0x42020.
6920 */
50a0bc90 6921 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6922 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6923 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6924 I915_READ(ILK_DISPLAY_CHICKEN1) |
6925 ILK_FBCQ_DIS);
6926 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6927 I915_READ(ILK_DISPLAY_CHICKEN2) |
6928 ILK_DPARB_GATE);
6f1d69b0
ED		 6929 }
6930
4d47e4f5
DL		 6931 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6932
6f1d69b0
ED		 6933 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6934 I915_READ(ILK_DISPLAY_CHICKEN2) |
6935 ILK_ELPIN_409_SELECT);
6936 I915_WRITE(_3D_CHICKEN2,
6937 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6938 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6939
ecdb4eb7 6940 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6941 I915_WRITE(CACHE_MODE_0,
6942 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6943
4e04632e
AG		 6944 /* WaDisable_RenderCache_OperationalFlush:ilk */
6945 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6946
0e088b8f 6947 g4x_disable_trickle_feed(dev);
bdad2b2f 6948
3107bd48
DV		 6949 ibx_init_clock_gating(dev);
6950}
6951
6952static void cpt_init_clock_gating(struct drm_device *dev)
6953{
fac5e23e 6954 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6955 int pipe;
3f704fa2 6956 uint32_t val;
3107bd48
DV		 6957
6958 /*
6959 * On Ibex Peak and Cougar Point, we need to disable clock
6960 * gating for the panel power sequencer or it will fail to
6961 * start up when no ports are active.
6962 */
cd664078
JB		 6963 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6964 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6965 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6966 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6967 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6968 /* The below fixes the weird display corruption, a few pixels shifted
6969 * downward, on (only) LVDS of some HP laptops with IVY.
6970 */
055e393f 6971 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6972 val = I915_READ(TRANS_CHICKEN2(pipe));
6973 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6974 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6975 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6976 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6977 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6978 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6979 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6980 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6981 }
3107bd48 6982 /* WADP0ClockGatingDisable */
055e393f 6983 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6984 I915_WRITE(TRANS_CHICKEN1(pipe),
6985 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6986 }
6f1d69b0
ED		 6987}
6988
1d7aaa0c
DV		 6989static void gen6_check_mch_setup(struct drm_device *dev)
6990{
fac5e23e 6991 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6992 uint32_t tmp;
6993
6994 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6995 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6996 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6997 tmp);
1d7aaa0c
DV		 6998}
6999
1fa61106 7000static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7001{
fac5e23e 7002 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7003 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7004
231e54f6 7005 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7006
7007 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7008 I915_READ(ILK_DISPLAY_CHICKEN2) |
7009 ILK_ELPIN_409_SELECT);
7010
ecdb4eb7 7011 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7012 I915_WRITE(_3D_CHICKEN,
7013 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7014
4e04632e
AG		 7015 /* WaDisable_RenderCache_OperationalFlush:snb */
7016 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7017
8d85d272
VS		 7018 /*
7019 * BSpec recoomends 8x4 when MSAA is used,
7020 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7021 *
7022 * Note that PS/WM thread counts depend on the WIZ hashing
7023 * disable bit, which we don't touch here, but it's good
7024 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7025 */
7026 I915_WRITE(GEN6_GT_MODE,
98533251 7027 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7028
017636cc 7029 ilk_init_lp_watermarks(dev);
6f1d69b0 7030
6f1d69b0 7031 I915_WRITE(CACHE_MODE_0,
50743298 7032 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7033
7034 I915_WRITE(GEN6_UCGCTL1,
7035 I915_READ(GEN6_UCGCTL1) |
7036 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7037 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7038
7039 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7040 * gating disable must be set. Failure to set it results in
7041 * flickering pixels due to Z write ordering failures after
7042 * some amount of runtime in the Mesa "fire" demo, and Unigine
7043 * Sanctuary and Tropics, and apparently anything else with
7044 * alpha test or pixel discard.
7045 *
7046 * According to the spec, bit 11 (RCCUNIT) must also be set,
7047 * but we didn't debug actual testcases to find it out.
0f846f81 7048 *
ef59318c
VS		 7049 * WaDisableRCCUnitClockGating:snb
7050 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7051 */
7052 I915_WRITE(GEN6_UCGCTL2,
7053 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7054 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7055
5eb146dd 7056 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7057 I915_WRITE(_3D_CHICKEN3,
7058 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7059
e927ecde
VS		 7060 /*
7061 * Bspec says:
7062 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7063 * 3DSTATE_SF number of SF output attributes is more than 16."
7064 */
7065 I915_WRITE(_3D_CHICKEN3,
7066 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7067
6f1d69b0
ED		 7068 /*
7069 * According to the spec the following bits should be
7070 * set in order to enable memory self-refresh and fbc:
7071 * The bit21 and bit22 of 0x42000
7072 * The bit21 and bit22 of 0x42004
7073 * The bit5 and bit7 of 0x42020
7074 * The bit14 of 0x70180
7075 * The bit14 of 0x71180
4bb35334
DL		 7076 *
7077 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7078 */
7079 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7080 I915_READ(ILK_DISPLAY_CHICKEN1) |
7081 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7082 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7083 I915_READ(ILK_DISPLAY_CHICKEN2) |
7084 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7085 I915_WRITE(ILK_DSPCLK_GATE_D,
7086 I915_READ(ILK_DSPCLK_GATE_D) |
7087 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7088 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7089
0e088b8f 7090 g4x_disable_trickle_feed(dev);
f8f2ac9a 7091
3107bd48 7092 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7093
7094 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7095}
7096
7097static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7098{
7099 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7100
3aad9059 7101 /*
46680e0a 7102 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7103 *
7104 * This actually overrides the dispatch
7105 * mode for all thread types.
7106 */
6f1d69b0
ED		 7107 reg &= ~GEN7_FF_SCHED_MASK;
7108 reg |= GEN7_FF_TS_SCHED_HW;
7109 reg |= GEN7_FF_VS_SCHED_HW;
7110 reg |= GEN7_FF_DS_SCHED_HW;
7111
7112 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7113}
7114
17a303ec
PZ		 7115static void lpt_init_clock_gating(struct drm_device *dev)
7116{
fac5e23e 7117 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7118
7119 /*
7120 * TODO: this bit should only be enabled when really needed, then
7121 * disabled when not needed anymore in order to save power.
7122 */
4f8036a2 7123 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7124 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7125 I915_READ(SOUTH_DSPCLK_GATE_D) |
7126 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7127
7128 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7129 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7130 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7131 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7132}
7133
7d708ee4
ID		 7134static void lpt_suspend_hw(struct drm_device *dev)
7135{
fac5e23e 7136 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7137
4f8036a2 7138 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7139 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7140
7141 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7142 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7143 }
7144}
7145
450174fe
ID		 7146static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7147 int general_prio_credits,
7148 int high_prio_credits)
7149{
7150 u32 misccpctl;
7151
7152 /* WaTempDisableDOPClkGating:bdw */
7153 misccpctl = I915_READ(GEN7_MISCCPCTL);
7154 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7155
7156 I915_WRITE(GEN8_L3SQCREG1,
7157 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7158 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7159
7160 /*
7161 * Wait at least 100 clocks before re-enabling clock gating.
7162 * See the definition of L3SQCREG1 in BSpec.
7163 */
7164 POSTING_READ(GEN8_L3SQCREG1);
7165 udelay(1);
7166 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7167}
7168
9498dba7
MK		 7169static void kabylake_init_clock_gating(struct drm_device *dev)
7170{
9146f308 7171 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7172
b033bb6d 7173 gen9_init_clock_gating(dev);
9498dba7
MK		 7174
7175 /* WaDisableSDEUnitClockGating:kbl */
7176 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7177 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7178 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7179
7180 /* WaDisableGamClockGating:kbl */
7181 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7182 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7183 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7184
7185 /* WaFbcNukeOnHostModify:kbl */
7186 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7187 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7188}
7189
dc00b6a0
DV		 7190static void skylake_init_clock_gating(struct drm_device *dev)
7191{
c584e2d3 7192 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7193
b033bb6d 7194 gen9_init_clock_gating(dev);
44fff99f
MK		 7195
7196 /* WAC6entrylatency:skl */
7197 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7198 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7199
7200 /* WaFbcNukeOnHostModify:skl */
7201 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7202 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7203}
7204
47c2bd97 7205static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7206{
fac5e23e 7207 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7208 enum pipe pipe;
1020a5c2 7209
7ad0dbab 7210 ilk_init_lp_watermarks(dev);
50ed5fbd 7211
ab57fff1 7212 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7213 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7214
ab57fff1 7215 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7216 I915_WRITE(CHICKEN_PAR1_1,
7217 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7218
ab57fff1 7219 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7220 for_each_pipe(dev_priv, pipe) {
07d27e20 7221 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7222 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7223 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7224 }
63801f21 7225
ab57fff1
BW		 7226 /* WaVSRefCountFullforceMissDisable:bdw */
7227 /* WaDSRefCountFullforceMissDisable:bdw */
7228 I915_WRITE(GEN7_FF_THREAD_MODE,
7229 I915_READ(GEN7_FF_THREAD_MODE) &
7230 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7231
295e8bb7
VS		 7232 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7233 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7234
7235 /* WaDisableSDEUnitClockGating:bdw */
7236 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7237 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7238
450174fe
ID		 7239 /* WaProgramL3SqcReg1Default:bdw */
7240 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7241
6d50b065
VS		 7242 /*
7243 * WaGttCachingOffByDefault:bdw
7244 * GTT cache may not work with big pages, so if those
7245 * are ever enabled GTT cache may need to be disabled.
7246 */
7247 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7248
17e0adf0
MK		 7249 /* WaKVMNotificationOnConfigChange:bdw */
7250 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7251 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7252
89d6b2b8 7253 lpt_init_clock_gating(dev);
1020a5c2
BW		 7254}
7255
cad2a2d7
ED		 7256static void haswell_init_clock_gating(struct drm_device *dev)
7257{
fac5e23e 7258 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7259
017636cc 7260 ilk_init_lp_watermarks(dev);
cad2a2d7 7261
f3fc4884
FJ		 7262 /* L3 caching of data atomics doesn't work -- disable it. */
7263 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7264 I915_WRITE(HSW_ROW_CHICKEN3,
7265 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7266
ecdb4eb7 7267 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7268 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7269 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7270 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7271
e36ea7ff
VS		 7272 /* WaVSRefCountFullforceMissDisable:hsw */
7273 I915_WRITE(GEN7_FF_THREAD_MODE,
7274 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7275
4e04632e
AG		 7276 /* WaDisable_RenderCache_OperationalFlush:hsw */
7277 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7278
fe27c606
CW		 7279 /* enable HiZ Raw Stall Optimization */
7280 I915_WRITE(CACHE_MODE_0_GEN7,
7281 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7282
ecdb4eb7 7283 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7284 I915_WRITE(CACHE_MODE_1,
7285 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7286
a12c4967
VS		 7287 /*
7288 * BSpec recommends 8x4 when MSAA is used,
7289 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7290 *
7291 * Note that PS/WM thread counts depend on the WIZ hashing
7292 * disable bit, which we don't touch here, but it's good
7293 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7294 */
7295 I915_WRITE(GEN7_GT_MODE,
98533251 7296 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7297
94411593
KG		 7298 /* WaSampleCChickenBitEnable:hsw */
7299 I915_WRITE(HALF_SLICE_CHICKEN3,
7300 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7301
ecdb4eb7 7302 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7303 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7304
90a88643
PZ		 7305 /* WaRsPkgCStateDisplayPMReq:hsw */
7306 I915_WRITE(CHICKEN_PAR1_1,
7307 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7308
17a303ec 7309 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7310}
7311
1fa61106 7312static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7313{
fac5e23e 7314 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7315 uint32_t snpcr;
6f1d69b0 7316
017636cc 7317 ilk_init_lp_watermarks(dev);
6f1d69b0 7318
231e54f6 7319 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7320
ecdb4eb7 7321 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7322 I915_WRITE(_3D_CHICKEN3,
7323 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7324
ecdb4eb7 7325 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7326 I915_WRITE(IVB_CHICKEN3,
7327 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7328 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7329
ecdb4eb7 7330 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7331 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7332 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7333 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7334
4e04632e
AG		 7335 /* WaDisable_RenderCache_OperationalFlush:ivb */
7336 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7337
ecdb4eb7 7338 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7339 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7340 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7341
ecdb4eb7 7342 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7343 I915_WRITE(GEN7_L3CNTLREG1,
7344 GEN7_WA_FOR_GEN7_L3_CONTROL);
7345 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7346 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7347 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7348 I915_WRITE(GEN7_ROW_CHICKEN2,
7349 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7350 else {
7351 /* must write both registers */
7352 I915_WRITE(GEN7_ROW_CHICKEN2,
7353 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7354 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7355 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7356 }
6f1d69b0 7357
ecdb4eb7 7358 /* WaForceL3Serialization:ivb */
61939d97
JB		 7359 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7360 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7361
1b80a19a 7362 /*
0f846f81 7363 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7364 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7365 */
7366 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7367 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7368
ecdb4eb7 7369 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7370 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7371 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7372 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7373
0e088b8f 7374 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7375
7376 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7377
22721343
CW		 7378 if (0) { /* causes HiZ corruption on ivb:gt1 */
7379 /* enable HiZ Raw Stall Optimization */
7380 I915_WRITE(CACHE_MODE_0_GEN7,
7381 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7382 }
116f2b6d 7383
ecdb4eb7 7384 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7385 I915_WRITE(CACHE_MODE_1,
7386 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7387
a607c1a4
VS		 7388 /*
7389 * BSpec recommends 8x4 when MSAA is used,
7390 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7391 *
7392 * Note that PS/WM thread counts depend on the WIZ hashing
7393 * disable bit, which we don't touch here, but it's good
7394 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7395 */
7396 I915_WRITE(GEN7_GT_MODE,
98533251 7397 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7398
20848223
BW		 7399 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7400 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7401 snpcr |= GEN6_MBC_SNPCR_MED;
7402 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7403
6e266956 7404 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7405 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7406
7407 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7408}
7409
1fa61106 7410static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7411{
fac5e23e 7412 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7413
ecdb4eb7 7414 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7415 I915_WRITE(_3D_CHICKEN3,
7416 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7417
ecdb4eb7 7418 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7419 I915_WRITE(IVB_CHICKEN3,
7420 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7421 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7422
fad7d36e 7423 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7424 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7425 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7426 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7427 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7428
4e04632e
AG		 7429 /* WaDisable_RenderCache_OperationalFlush:vlv */
7430 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7431
ecdb4eb7 7432 /* WaForceL3Serialization:vlv */
61939d97
JB		 7433 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7434 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7435
ecdb4eb7 7436 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7437 I915_WRITE(GEN7_ROW_CHICKEN2,
7438 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7439
ecdb4eb7 7440 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7441 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7442 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7443 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7444
46680e0a
VS		 7445 gen7_setup_fixed_func_scheduler(dev_priv);
7446
3c0edaeb 7447 /*
0f846f81 7448 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7449 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7450 */
7451 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7452 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7453
c98f5062
AG		 7454 /* WaDisableL3Bank2xClockGate:vlv
7455 * Disabling L3 clock gating- MMIO 940c[25] = 1
7456 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7457 I915_WRITE(GEN7_UCGCTL4,
7458 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7459
afd58e79
VS		 7460 /*
7461 * BSpec says this must be set, even though
7462 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7463 */
6b26c86d
DV		 7464 I915_WRITE(CACHE_MODE_1,
7465 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7466
da2518f9
VS		 7467 /*
7468 * BSpec recommends 8x4 when MSAA is used,
7469 * however in practice 16x4 seems fastest.
7470 *
7471 * Note that PS/WM thread counts depend on the WIZ hashing
7472 * disable bit, which we don't touch here, but it's good
7473 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7474 */
7475 I915_WRITE(GEN7_GT_MODE,
7476 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7477
031994ee
VS		 7478 /*
7479 * WaIncreaseL3CreditsForVLVB0:vlv
7480 * This is the hardware default actually.
7481 */
7482 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7483
2d809570 7484 /*
ecdb4eb7 7485 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7486 * Disable clock gating on th GCFG unit to prevent a delay
7487 * in the reporting of vblank events.
7488 */
7a0d1eed 7489 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7490}
7491
a4565da8
VS		 7492static void cherryview_init_clock_gating(struct drm_device *dev)
7493{
fac5e23e 7494 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7495
232ce337
VS		 7496 /* WaVSRefCountFullforceMissDisable:chv */
7497 /* WaDSRefCountFullforceMissDisable:chv */
7498 I915_WRITE(GEN7_FF_THREAD_MODE,
7499 I915_READ(GEN7_FF_THREAD_MODE) &
7500 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7501
7502 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7503 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7504 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7505
7506 /* WaDisableCSUnitClockGating:chv */
7507 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7508 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7509
7510 /* WaDisableSDEUnitClockGating:chv */
7511 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7512 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7513
450174fe
ID		 7514 /*
7515 * WaProgramL3SqcReg1Default:chv
7516 * See gfxspecs/Related Documents/Performance Guide/
7517 * LSQC Setting Recommendations.
7518 */
7519 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7520
6d50b065
VS		 7521 /*
7522 * GTT cache may not work with big pages, so if those
7523 * are ever enabled GTT cache may need to be disabled.
7524 */
7525 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7526}
7527
1fa61106 7528static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7529{
fac5e23e 7530 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7531 uint32_t dspclk_gate;
7532
7533 I915_WRITE(RENCLK_GATE_D1, 0);
7534 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7535 GS_UNIT_CLOCK_GATE_DISABLE |
7536 CL_UNIT_CLOCK_GATE_DISABLE);
7537 I915_WRITE(RAMCLK_GATE_D, 0);
7538 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7539 OVRUNIT_CLOCK_GATE_DISABLE |
7540 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7541 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7542 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7543 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7544
7545 /* WaDisableRenderCachePipelinedFlush */
7546 I915_WRITE(CACHE_MODE_0,
7547 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7548
4e04632e
AG		 7549 /* WaDisable_RenderCache_OperationalFlush:g4x */
7550 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7551
0e088b8f 7552 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7553}
7554
1fa61106 7555static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7556{
fac5e23e 7557 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7558
7559 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7560 I915_WRITE(RENCLK_GATE_D2, 0);
7561 I915_WRITE(DSPCLK_GATE_D, 0);
7562 I915_WRITE(RAMCLK_GATE_D, 0);
7563 I915_WRITE16(DEUC, 0);
20f94967
VS		 7564 I915_WRITE(MI_ARB_STATE,
7565 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7566
7567 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7568 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7569}
7570
1fa61106 7571static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7572{
fac5e23e 7573 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7574
7575 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7576 I965_RCC_CLOCK_GATE_DISABLE |
7577 I965_RCPB_CLOCK_GATE_DISABLE |
7578 I965_ISC_CLOCK_GATE_DISABLE |
7579 I965_FBC_CLOCK_GATE_DISABLE);
7580 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7581 I915_WRITE(MI_ARB_STATE,
7582 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7583
7584 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7585 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7586}
7587
1fa61106 7588static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7589{
fac5e23e 7590 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7591 u32 dstate = I915_READ(D_STATE);
7592
7593 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7594 DSTATE_DOT_CLOCK_GATING;
7595 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7596
7597 if (IS_PINEVIEW(dev))
7598 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7599
7600 /* IIR "flip pending" means done if this bit is set */
7601 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7602
7603 /* interrupts should cause a wake up from C3 */
3299254f 7604 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7605
7606 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7607 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7608
7609 I915_WRITE(MI_ARB_STATE,
7610 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7611}
7612
1fa61106 7613static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7614{
fac5e23e 7615 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7616
7617 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7618
7619 /* interrupts should cause a wake up from C3 */
7620 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7621 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7622
7623 I915_WRITE(MEM_MODE,
7624 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7625}
7626
1fa61106 7627static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7628{
fac5e23e 7629 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7630
7631 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7632
7633 I915_WRITE(MEM_MODE,
7634 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7635 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7636}
7637
6f1d69b0
ED		 7638void intel_init_clock_gating(struct drm_device *dev)
7639{
fac5e23e 7640 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7641
bb400da9 7642 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7643}
7644
7d708ee4
ID		 7645void intel_suspend_hw(struct drm_device *dev)
7646{
6e266956 7647 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7648 lpt_suspend_hw(dev);
7649}
7650
bb400da9
ID		 7651static void nop_init_clock_gating(struct drm_device *dev)
7652{
7653 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7654}
7655
7656/**
7657 * intel_init_clock_gating_hooks - setup the clock gating hooks
7658 * @dev_priv: device private
7659 *
7660 * Setup the hooks that configure which clocks of a given platform can be
7661 * gated and also apply various GT and display specific workarounds for these
7662 * platforms. Note that some GT specific workarounds are applied separately
7663 * when GPU contexts or batchbuffers start their execution.
7664 */
7665void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7666{
7667 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7668 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7669 else if (IS_KABYLAKE(dev_priv))
9498dba7 7670 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7671 else if (IS_BROXTON(dev_priv))
7672 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7673 else if (IS_BROADWELL(dev_priv))
7674 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7675 else if (IS_CHERRYVIEW(dev_priv))
7676 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7677 else if (IS_HASWELL(dev_priv))
7678 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7679 else if (IS_IVYBRIDGE(dev_priv))
7680 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7681 else if (IS_VALLEYVIEW(dev_priv))
7682 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7683 else if (IS_GEN6(dev_priv))
7684 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7685 else if (IS_GEN5(dev_priv))
7686 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7687 else if (IS_G4X(dev_priv))
7688 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7689 else if (IS_CRESTLINE(dev_priv))
7690 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7691 else if (IS_BROADWATER(dev_priv))
7692 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7693 else if (IS_GEN3(dev_priv))
7694 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7695 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7696 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7697 else if (IS_GEN2(dev_priv))
7698 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7699 else {
7700 MISSING_CASE(INTEL_DEVID(dev_priv));
7701 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7702 }
7703}
7704
1fa61106
ED		 7705/* Set up chip specific power management-related functions */
7706void intel_init_pm(struct drm_device *dev)
7707{
fac5e23e 7708 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7709
7ff0ebcc 7710 intel_fbc_init(dev_priv);
1fa61106 7711
c921aba8
DV		 7712 /* For cxsr */
7713 if (IS_PINEVIEW(dev))
7714 i915_pineview_get_mem_freq(dev);
5db94019 7715 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7716 i915_ironlake_get_mem_freq(dev);
7717
1fa61106 7718 /* For FIFO watermark updates */
f5ed50cb 7719 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7720 skl_setup_wm_latency(dev);
2d41c0b5 7721 dev_priv->display.update_wm = skl_update_wm;
98d39494 7722 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7723 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7724 ilk_setup_wm_latency(dev);
53615a5e 7725
5db94019 7726 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7727 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7728 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7729 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7730 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7731 dev_priv->display.compute_intermediate_wm =
7732 ilk_compute_intermediate_wm;
7733 dev_priv->display.initial_watermarks =
7734 ilk_initial_watermarks;
7735 dev_priv->display.optimize_watermarks =
7736 ilk_optimize_watermarks;
bd602544
VS		 7737 } else {
7738 DRM_DEBUG_KMS("Failed to read display plane latency. "
7739 "Disable CxSR\n");
7740 }
920a14b2 7741 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7742 vlv_setup_wm_latency(dev);
262cd2e1 7743 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7744 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7745 vlv_setup_wm_latency(dev);
26e1fe4f 7746 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7747 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7748 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7749 dev_priv->is_ddr3,
7750 dev_priv->fsb_freq,
7751 dev_priv->mem_freq)) {
7752 DRM_INFO("failed to find known CxSR latency "
7753 "(found ddr%s fsb freq %d, mem freq %d), "
7754 "disabling CxSR\n",
7755 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7756 dev_priv->fsb_freq, dev_priv->mem_freq);
7757 /* Disable CxSR and never update its watermark again */
5209b1f4 7758 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7759 dev_priv->display.update_wm = NULL;
7760 } else
7761 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7762 } else if (IS_G4X(dev_priv)) {
1fa61106 7763 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7764 } else if (IS_GEN4(dev_priv)) {
1fa61106 7765 dev_priv->display.update_wm = i965_update_wm;
5db94019 7766 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7767 dev_priv->display.update_wm = i9xx_update_wm;
7768 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7769 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7770 if (INTEL_INFO(dev)->num_pipes == 1) {
7771 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7772 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7773 } else {
7774 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7775 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7776 }
feb56b93
DV		 7777 } else {
7778 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7779 }
7780}
7781
87660502
L		 7782static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7783{
7784 uint32_t flags =
7785 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7786
7787 switch (flags) {
7788 case GEN6_PCODE_SUCCESS:
7789 return 0;
7790 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7791 case GEN6_PCODE_ILLEGAL_CMD:
7792 return -ENXIO;
7793 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7794 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7795 return -EOVERFLOW;
7796 case GEN6_PCODE_TIMEOUT:
7797 return -ETIMEDOUT;
7798 default:
7799 MISSING_CASE(flags)
7800 return 0;
7801 }
7802}
7803
7804static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7805{
7806 uint32_t flags =
7807 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7808
7809 switch (flags) {
7810 case GEN6_PCODE_SUCCESS:
7811 return 0;
7812 case GEN6_PCODE_ILLEGAL_CMD:
7813 return -ENXIO;
7814 case GEN7_PCODE_TIMEOUT:
7815 return -ETIMEDOUT;
7816 case GEN7_PCODE_ILLEGAL_DATA:
7817 return -EINVAL;
7818 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7819 return -EOVERFLOW;
7820 default:
7821 MISSING_CASE(flags);
7822 return 0;
7823 }
7824}
7825
151a49d0 7826int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7827{
87660502
L		 7828 int status;
7829
4fc688ce 7830 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7831
3f5582dd
CW		 7832 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7833 * use te fw I915_READ variants to reduce the amount of work
7834 * required when reading/writing.
7835 */
7836
7837 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7838 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7839 return -EAGAIN;
7840 }
7841
3f5582dd
CW		 7842 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7843 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7844 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7845
3f5582dd
CW		 7846 if (intel_wait_for_register_fw(dev_priv,
7847 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7848 500)) {
42c0526c
BW		 7849 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7850 return -ETIMEDOUT;
7851 }
7852
3f5582dd
CW		 7853 *val = I915_READ_FW(GEN6_PCODE_DATA);
7854 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7855
87660502
L		 7856 if (INTEL_GEN(dev_priv) > 6)
7857 status = gen7_check_mailbox_status(dev_priv);
7858 else
7859 status = gen6_check_mailbox_status(dev_priv);
7860
7861 if (status) {
7862 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7863 status);
7864 return status;
7865 }
7866
42c0526c
BW		 7867 return 0;
7868}
7869
3f5582dd 7870int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7871 u32 mbox, u32 val)
42c0526c 7872{
87660502
L		 7873 int status;
7874
4fc688ce 7875 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7876
3f5582dd
CW		 7877 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7878 * use te fw I915_READ variants to reduce the amount of work
7879 * required when reading/writing.
7880 */
7881
7882 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7883 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7884 return -EAGAIN;
7885 }
7886
3f5582dd
CW		 7887 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7888 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7889
3f5582dd
CW		 7890 if (intel_wait_for_register_fw(dev_priv,
7891 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7892 500)) {
42c0526c
BW		 7893 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7894 return -ETIMEDOUT;
7895 }
7896
3f5582dd 7897 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7898
87660502
L		 7899 if (INTEL_GEN(dev_priv) > 6)
7900 status = gen7_check_mailbox_status(dev_priv);
7901 else
7902 status = gen6_check_mailbox_status(dev_priv);
7903
7904 if (status) {
7905 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7906 status);
7907 return status;
7908 }
7909
42c0526c
BW		 7910 return 0;
7911}
a0e4e199 7912
dd06f88c
VS		 7913static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7914{
c30fec65
VS		 7915 /*
7916 * N = val - 0xb7
7917 * Slow = Fast = GPLL ref * N
7918 */
7919 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7920}
7921
b55dd647 7922static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7923{
c30fec65 7924 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7925}
7926
b55dd647 7927static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7928{
c30fec65
VS		 7929 /*
7930 * N = val / 2
7931 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7932 */
7933 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7934}
7935
b55dd647 7936static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7937{
1c14762d 7938 /* CHV needs even values */
c30fec65 7939 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7940}
7941
616bc820 7942int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7943{
2d1fe073 7944 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7945 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7946 GEN9_FREQ_SCALER);
2d1fe073 7947 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7948 return chv_gpu_freq(dev_priv, val);
2d1fe073 7949 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7950 return byt_gpu_freq(dev_priv, val);
7951 else
7952 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7953}
7954
616bc820
VS		 7955int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7956{
2d1fe073 7957 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7958 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7959 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7960 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7961 return chv_freq_opcode(dev_priv, val);
2d1fe073 7962 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7963 return byt_freq_opcode(dev_priv, val);
7964 else
500a3d2e 7965 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7966}
22b1b2f8 7967
6ad790c0
CW		 7968struct request_boost {
7969 struct work_struct work;
eed29a5b 7970 struct drm_i915_gem_request *req;
6ad790c0
CW		 7971};
7972
7973static void __intel_rps_boost_work(struct work_struct *work)
7974{
7975 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7976 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7977
f69a02c9 7978 if (!i915_gem_request_completed(req))
c033666a 7979 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7980
e8a261ea 7981 i915_gem_request_put(req);
6ad790c0
CW		 7982 kfree(boost);
7983}
7984
91d14251 7985void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7986{
7987 struct request_boost *boost;
7988
91d14251 7989 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7990 return;
7991
f69a02c9 7992 if (i915_gem_request_completed(req))
e61b9958
CW		 7993 return;
7994
6ad790c0
CW		 7995 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7996 if (boost == NULL)
7997 return;
7998
e8a261ea 7999 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8000
8001 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8002 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8003}
8004
f742a552 8005void intel_pm_setup(struct drm_device *dev)
907b28c5 8006{
fac5e23e 8007 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8008
f742a552 8009 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8010 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8011
54b4f68f
CW		 8012 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8013 __intel_autoenable_gt_powersave);
1854d5ca 8014 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8015
33688d95 8016 dev_priv->pm.suspended = false;
1f814dac 8017 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8018}
Ubuntu Jammy Linux kernel mirror