]>
Commit | Line | Data |
---|---|---|
0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
e2bbc343 RV |
59 | static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) |
60 | { | |
fac5e23e | 61 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 RV |
62 | uint32_t val; |
63 | ||
64 | val = I915_READ(VLV_PSRSTAT(pipe)) & | |
65 | VLV_EDP_PSR_CURR_STATE_MASK; | |
66 | return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
67 | (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); | |
68 | } | |
69 | ||
d2419ffc VS |
70 | static void vlv_psr_setup_vsc(struct intel_dp *intel_dp, |
71 | const struct intel_crtc_state *crtc_state) | |
e2bbc343 | 72 | { |
d2419ffc VS |
73 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
74 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
e2bbc343 RV |
75 | uint32_t val; |
76 | ||
77 | /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ | |
d2419ffc | 78 | val = I915_READ(VLV_VSCSDP(crtc->pipe)); |
e2bbc343 RV |
79 | val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; |
80 | val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; | |
d2419ffc | 81 | I915_WRITE(VLV_VSCSDP(crtc->pipe), val); |
e2bbc343 RV |
82 | } |
83 | ||
2ce4df87 RV |
84 | static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, |
85 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 86 | { |
97da2ef4 | 87 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
d2419ffc VS |
88 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
89 | struct edp_vsc_psr psr_vsc; | |
474d1ec4 | 90 | |
2ce4df87 RV |
91 | if (dev_priv->psr.psr2_support) { |
92 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ | |
93 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
94 | psr_vsc.sdp_header.HB0 = 0; | |
95 | psr_vsc.sdp_header.HB1 = 0x7; | |
96 | if (dev_priv->psr.colorimetry_support && | |
97 | dev_priv->psr.y_cord_support) { | |
98 | psr_vsc.sdp_header.HB2 = 0x5; | |
99 | psr_vsc.sdp_header.HB3 = 0x13; | |
100 | } else if (dev_priv->psr.y_cord_support) { | |
101 | psr_vsc.sdp_header.HB2 = 0x4; | |
102 | psr_vsc.sdp_header.HB3 = 0xe; | |
103 | } else { | |
104 | psr_vsc.sdp_header.HB2 = 0x3; | |
105 | psr_vsc.sdp_header.HB3 = 0xc; | |
106 | } | |
97da2ef4 | 107 | } else { |
2ce4df87 RV |
108 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
109 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
110 | psr_vsc.sdp_header.HB0 = 0; | |
111 | psr_vsc.sdp_header.HB1 = 0x7; | |
112 | psr_vsc.sdp_header.HB2 = 0x2; | |
113 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
114 | } |
115 | ||
1d776538 VS |
116 | intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state, |
117 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); | |
474d1ec4 SJ |
118 | } |
119 | ||
e2bbc343 RV |
120 | static void vlv_psr_enable_sink(struct intel_dp *intel_dp) |
121 | { | |
122 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
670b90d2 | 123 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
e2bbc343 RV |
124 | } |
125 | ||
f0f59a00 VS |
126 | static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, |
127 | enum port port) | |
1f38089c VS |
128 | { |
129 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
130 | return DP_AUX_CH_CTL(port); | |
131 | else | |
132 | return EDP_PSR_AUX_CTL; | |
133 | } | |
134 | ||
f0f59a00 VS |
135 | static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, |
136 | enum port port, int index) | |
1f38089c VS |
137 | { |
138 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
139 | return DP_AUX_CH_DATA(port, index); | |
140 | else | |
141 | return EDP_PSR_AUX_DATA(index); | |
142 | } | |
143 | ||
e2bbc343 | 144 | static void hsw_psr_enable_sink(struct intel_dp *intel_dp) |
0bc12bcb RV |
145 | { |
146 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
147 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 149 | uint32_t aux_clock_divider; |
f0f59a00 | 150 | i915_reg_t aux_ctl_reg; |
0bc12bcb RV |
151 | static const uint8_t aux_msg[] = { |
152 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
153 | [1] = DP_SET_POWER >> 8, | |
154 | [2] = DP_SET_POWER & 0xff, | |
155 | [3] = 1 - 1, | |
156 | [4] = DP_SET_POWER_D0, | |
157 | }; | |
8f4f2797 | 158 | enum port port = dig_port->base.port; |
d4dcbdce | 159 | u32 aux_ctl; |
0bc12bcb RV |
160 | int i; |
161 | ||
162 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
163 | ||
164 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); | |
165 | ||
474d1ec4 SJ |
166 | /* Enable AUX frame sync at sink */ |
167 | if (dev_priv->psr.aux_frame_sync) | |
168 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
169 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
170 | DP_AUX_FRAME_SYNC_ENABLE); | |
340c93c0 NV |
171 | /* Enable ALPM at sink for psr2 */ |
172 | if (dev_priv->psr.psr2_support && dev_priv->psr.alpm) | |
173 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
174 | DP_RECEIVER_ALPM_CONFIG, | |
175 | DP_ALPM_ENABLE); | |
6f32ea7e DV |
176 | if (dev_priv->psr.link_standby) |
177 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
178 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
179 | else | |
180 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, | |
181 | DP_PSR_ENABLE); | |
182 | ||
1f38089c | 183 | aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port); |
e3d99845 | 184 | |
0bc12bcb RV |
185 | /* Setup AUX registers */ |
186 | for (i = 0; i < sizeof(aux_msg); i += 4) | |
1f38089c | 187 | I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), |
0bc12bcb RV |
188 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
189 | ||
d4dcbdce DV |
190 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg), |
191 | aux_clock_divider); | |
192 | I915_WRITE(aux_ctl_reg, aux_ctl); | |
0bc12bcb RV |
193 | } |
194 | ||
d2419ffc VS |
195 | static void vlv_psr_enable_source(struct intel_dp *intel_dp, |
196 | const struct intel_crtc_state *crtc_state) | |
e2bbc343 RV |
197 | { |
198 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d2419ffc VS |
199 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
200 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
e2bbc343 | 201 | |
0d0c2794 | 202 | /* Transition from PSR_state 0 (disabled) to PSR_state 1 (inactive) */ |
d2419ffc | 203 | I915_WRITE(VLV_PSRCTL(crtc->pipe), |
e2bbc343 RV |
204 | VLV_EDP_PSR_MODE_SW_TIMER | |
205 | VLV_EDP_PSR_SRC_TRANSMITTER_STATE | | |
206 | VLV_EDP_PSR_ENABLE); | |
207 | } | |
208 | ||
995d3047 RV |
209 | static void vlv_psr_activate(struct intel_dp *intel_dp) |
210 | { | |
211 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
212 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 213 | struct drm_i915_private *dev_priv = to_i915(dev); |
995d3047 RV |
214 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
215 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
216 | ||
0d0c2794 RV |
217 | /* |
218 | * Let's do the transition from PSR_state 1 (inactive) to | |
219 | * PSR_state 2 (transition to active - static frame transmission). | |
220 | * Then Hardware is responsible for the transition to | |
221 | * PSR_state 3 (active - no Remote Frame Buffer (RFB) update). | |
995d3047 RV |
222 | */ |
223 | I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | | |
224 | VLV_EDP_PSR_ACTIVE_ENTRY); | |
225 | } | |
226 | ||
ed63d24b | 227 | static void hsw_activate_psr1(struct intel_dp *intel_dp) |
0bc12bcb RV |
228 | { |
229 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
230 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 231 | struct drm_i915_private *dev_priv = to_i915(dev); |
474d1ec4 | 232 | |
0bc12bcb | 233 | uint32_t max_sleep_time = 0x1f; |
40918e0b RV |
234 | /* |
235 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
236 | * Let's use 6 as the minimum to cover all known cases including | |
237 | * the off-by-one issue that HW has in some cases. Also there are | |
238 | * cases where sink should be able to train | |
239 | * with the 5 or 6 idle patterns. | |
d44b4dcb | 240 | */ |
40918e0b | 241 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
50db1390 DV |
242 | uint32_t val = EDP_PSR_ENABLE; |
243 | ||
244 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
245 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
7370c68d | 246 | |
772c2a51 | 247 | if (IS_HASWELL(dev_priv)) |
7370c68d | 248 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0bc12bcb | 249 | |
60e5ffe3 RV |
250 | if (dev_priv->psr.link_standby) |
251 | val |= EDP_PSR_LINK_STANDBY; | |
252 | ||
50db1390 DV |
253 | if (dev_priv->vbt.psr.tp1_wakeup_time > 5) |
254 | val |= EDP_PSR_TP1_TIME_2500us; | |
255 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) | |
256 | val |= EDP_PSR_TP1_TIME_500us; | |
257 | else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) | |
258 | val |= EDP_PSR_TP1_TIME_100us; | |
259 | else | |
260 | val |= EDP_PSR_TP1_TIME_0us; | |
261 | ||
262 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
263 | val |= EDP_PSR_TP2_TP3_TIME_2500us; | |
264 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
265 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
266 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
267 | val |= EDP_PSR_TP2_TP3_TIME_100us; | |
268 | else | |
269 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
270 | ||
271 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
272 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
273 | val |= EDP_PSR_TP1_TP3_SEL; | |
274 | else | |
275 | val |= EDP_PSR_TP1_TP2_SEL; | |
276 | ||
912d6412 | 277 | val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; |
50db1390 | 278 | I915_WRITE(EDP_PSR_CTL, val); |
3fcb0ca1 | 279 | } |
50db1390 | 280 | |
ed63d24b | 281 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 NV |
282 | { |
283 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
284 | struct drm_device *dev = dig_port->base.base.dev; | |
285 | struct drm_i915_private *dev_priv = to_i915(dev); | |
286 | /* | |
287 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
288 | * Let's use 6 as the minimum to cover all known cases including | |
289 | * the off-by-one issue that HW has in some cases. Also there are | |
290 | * cases where sink should be able to train | |
291 | * with the 5 or 6 idle patterns. | |
292 | */ | |
293 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
294 | uint32_t val; | |
977da084 | 295 | uint8_t sink_latency; |
3fcb0ca1 NV |
296 | |
297 | val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
50db1390 DV |
298 | |
299 | /* FIXME: selective update is probably totally broken because it doesn't | |
300 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
301 | * good enough. */ | |
6433226b | 302 | val |= EDP_PSR2_ENABLE | |
977da084 | 303 | EDP_SU_TRACK_ENABLE; |
304 | ||
305 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
306 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, | |
307 | &sink_latency) == 1) { | |
308 | sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
309 | } else { | |
310 | sink_latency = 0; | |
311 | } | |
312 | val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1); | |
50db1390 DV |
313 | |
314 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) | |
315 | val |= EDP_PSR2_TP2_TIME_2500; | |
316 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) | |
317 | val |= EDP_PSR2_TP2_TIME_500; | |
318 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) | |
319 | val |= EDP_PSR2_TP2_TIME_100; | |
320 | else | |
321 | val |= EDP_PSR2_TP2_TIME_50; | |
474d1ec4 | 322 | |
50db1390 | 323 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
324 | } |
325 | ||
ed63d24b | 326 | static void hsw_psr_activate(struct intel_dp *intel_dp) |
3fcb0ca1 NV |
327 | { |
328 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
329 | struct drm_device *dev = dig_port->base.base.dev; | |
330 | struct drm_i915_private *dev_priv = to_i915(dev); | |
331 | ||
ed63d24b RV |
332 | /* On HSW+ after we enable PSR on source it will activate it |
333 | * as soon as it match configure idle_frame count. So | |
334 | * we just actually enable it here on activation time. | |
335 | */ | |
336 | ||
3fcb0ca1 NV |
337 | /* psr1 and psr2 are mutually exclusive.*/ |
338 | if (dev_priv->psr.psr2_support) | |
ed63d24b | 339 | hsw_activate_psr2(intel_dp); |
3fcb0ca1 | 340 | else |
ed63d24b | 341 | hsw_activate_psr1(intel_dp); |
3fcb0ca1 NV |
342 | } |
343 | ||
4d90f2d5 VS |
344 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
345 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
346 | { |
347 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
4d90f2d5 | 348 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
dfd2e9ab | 349 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 350 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 351 | int psr_setup_time; |
0bc12bcb | 352 | |
4371d896 | 353 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
354 | return; |
355 | ||
356 | if (!i915_modparams.enable_psr) { | |
357 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
358 | return; | |
359 | } | |
0bc12bcb | 360 | |
dc9b5a0c RV |
361 | /* |
362 | * HSW spec explicitly says PSR is tied to port A. | |
363 | * BDW+ platforms with DDI implementation of PSR have different | |
364 | * PSR registers per transcoder and we only implement transcoder EDP | |
365 | * ones. Since by Display design transcoder EDP is tied to port A | |
366 | * we can safely escape based on the port A. | |
367 | */ | |
8f4f2797 | 368 | if (HAS_DDI(dev_priv) && dig_port->base.port != PORT_A) { |
dc9b5a0c | 369 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 370 | return; |
0bc12bcb RV |
371 | } |
372 | ||
920a14b2 | 373 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
65f61b42 RV |
374 | !dev_priv->psr.link_standby) { |
375 | DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n"); | |
4d90f2d5 | 376 | return; |
65f61b42 RV |
377 | } |
378 | ||
772c2a51 | 379 | if (IS_HASWELL(dev_priv) && |
4d90f2d5 | 380 | I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & |
c8e68b7e | 381 | S3D_ENABLE) { |
0bc12bcb | 382 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
4d90f2d5 | 383 | return; |
0bc12bcb RV |
384 | } |
385 | ||
772c2a51 | 386 | if (IS_HASWELL(dev_priv) && |
dfd2e9ab | 387 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb | 388 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
4d90f2d5 | 389 | return; |
0bc12bcb RV |
390 | } |
391 | ||
dfd2e9ab VS |
392 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
393 | if (psr_setup_time < 0) { | |
394 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
395 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 396 | return; |
dfd2e9ab VS |
397 | } |
398 | ||
399 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
400 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
401 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
402 | psr_setup_time); | |
4d90f2d5 VS |
403 | return; |
404 | } | |
405 | ||
406 | /* | |
407 | * FIXME psr2_support is messed up. It's both computed | |
408 | * dynamically during PSR enable, and extracted from sink | |
409 | * caps during eDP detection. | |
410 | */ | |
411 | if (!dev_priv->psr.psr2_support) { | |
412 | crtc_state->has_psr = true; | |
413 | return; | |
dfd2e9ab VS |
414 | } |
415 | ||
acf45d11 | 416 | /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ |
4d90f2d5 VS |
417 | if (adjusted_mode->crtc_hdisplay > 3200 || |
418 | adjusted_mode->crtc_vdisplay > 2000) { | |
419 | DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n"); | |
420 | return; | |
acf45d11 | 421 | } |
18b9bf3e NV |
422 | |
423 | /* | |
424 | * FIXME:enable psr2 only for y-cordinate psr2 panels | |
425 | * After gtc implementation , remove this restriction. | |
426 | */ | |
4d90f2d5 | 427 | if (!dev_priv->psr.y_cord_support) { |
18b9bf3e | 428 | DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n"); |
4d90f2d5 | 429 | return; |
18b9bf3e | 430 | } |
acf45d11 | 431 | |
4d90f2d5 VS |
432 | crtc_state->has_psr = true; |
433 | crtc_state->has_psr2 = true; | |
0bc12bcb RV |
434 | } |
435 | ||
e2bbc343 | 436 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
437 | { |
438 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
439 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 440 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 441 | |
3fcb0ca1 NV |
442 | if (dev_priv->psr.psr2_support) |
443 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
444 | else | |
445 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb RV |
446 | WARN_ON(dev_priv->psr.active); |
447 | lockdep_assert_held(&dev_priv->psr.lock); | |
448 | ||
e3702ac9 | 449 | dev_priv->psr.activate(intel_dp); |
0bc12bcb RV |
450 | dev_priv->psr.active = true; |
451 | } | |
452 | ||
4d1fa22f RV |
453 | static void hsw_psr_enable_source(struct intel_dp *intel_dp, |
454 | const struct intel_crtc_state *crtc_state) | |
455 | { | |
456 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
457 | struct drm_device *dev = dig_port->base.base.dev; | |
458 | struct drm_i915_private *dev_priv = to_i915(dev); | |
459 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
460 | u32 chicken; | |
461 | ||
462 | if (dev_priv->psr.psr2_support) { | |
463 | chicken = PSR2_VSC_ENABLE_PROG_HEADER; | |
464 | if (dev_priv->psr.y_cord_support) | |
465 | chicken |= PSR2_ADD_VERTICAL_LINE_COUNT; | |
466 | I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); | |
467 | ||
468 | I915_WRITE(EDP_PSR_DEBUG_CTL, | |
469 | EDP_PSR_DEBUG_MASK_MEMUP | | |
470 | EDP_PSR_DEBUG_MASK_HPD | | |
471 | EDP_PSR_DEBUG_MASK_LPSP | | |
472 | EDP_PSR_DEBUG_MASK_MAX_SLEEP | | |
473 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
474 | } else { | |
475 | /* | |
476 | * Per Spec: Avoid continuous PSR exit by masking MEMUP | |
477 | * and HPD. also mask LPSP to avoid dependency on other | |
478 | * drivers that might block runtime_pm besides | |
479 | * preventing other hw tracking issues now we can rely | |
480 | * on frontbuffer tracking. | |
481 | */ | |
482 | I915_WRITE(EDP_PSR_DEBUG_CTL, | |
483 | EDP_PSR_DEBUG_MASK_MEMUP | | |
484 | EDP_PSR_DEBUG_MASK_HPD | | |
485 | EDP_PSR_DEBUG_MASK_LPSP); | |
486 | } | |
487 | } | |
488 | ||
b2b89f55 RV |
489 | /** |
490 | * intel_psr_enable - Enable PSR | |
491 | * @intel_dp: Intel DP | |
d2419ffc | 492 | * @crtc_state: new CRTC state |
b2b89f55 RV |
493 | * |
494 | * This function can only be called after the pipe is fully trained and enabled. | |
495 | */ | |
d2419ffc VS |
496 | void intel_psr_enable(struct intel_dp *intel_dp, |
497 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
498 | { |
499 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
500 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 501 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 502 | |
4d90f2d5 | 503 | if (!crtc_state->has_psr) |
0bc12bcb | 504 | return; |
0bc12bcb | 505 | |
da83ef85 | 506 | WARN_ON(dev_priv->drrs.dp); |
0bc12bcb RV |
507 | mutex_lock(&dev_priv->psr.lock); |
508 | if (dev_priv->psr.enabled) { | |
509 | DRM_DEBUG_KMS("PSR already in use\n"); | |
510 | goto unlock; | |
511 | } | |
512 | ||
4d90f2d5 | 513 | dev_priv->psr.psr2_support = crtc_state->has_psr2; |
0bc12bcb RV |
514 | dev_priv->psr.busy_frontbuffer_bits = 0; |
515 | ||
2a5db87f | 516 | dev_priv->psr.setup_vsc(intel_dp, crtc_state); |
49ad316f | 517 | dev_priv->psr.enable_sink(intel_dp); |
d0d5e0d7 | 518 | dev_priv->psr.enable_source(intel_dp, crtc_state); |
29d1efe0 RV |
519 | dev_priv->psr.enabled = intel_dp; |
520 | ||
521 | if (INTEL_GEN(dev_priv) >= 9) { | |
522 | intel_psr_activate(intel_dp); | |
523 | } else { | |
524 | /* | |
525 | * FIXME: Activation should happen immediately since this | |
526 | * function is just called after pipe is fully trained and | |
527 | * enabled. | |
528 | * However on some platforms we face issues when first | |
529 | * activation follows a modeset so quickly. | |
530 | * - On VLV/CHV we get bank screen on first activation | |
531 | * - On HSW/BDW we get a recoverable frozen screen until | |
532 | * next exit-activate sequence. | |
533 | */ | |
d0ac896a RV |
534 | schedule_delayed_work(&dev_priv->psr.work, |
535 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
29d1efe0 | 536 | } |
d0ac896a | 537 | |
0bc12bcb RV |
538 | unlock: |
539 | mutex_unlock(&dev_priv->psr.lock); | |
540 | } | |
541 | ||
d2419ffc VS |
542 | static void vlv_psr_disable(struct intel_dp *intel_dp, |
543 | const struct intel_crtc_state *old_crtc_state) | |
0bc12bcb RV |
544 | { |
545 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
546 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 547 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2419ffc | 548 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
e2bbc343 | 549 | uint32_t val; |
0bc12bcb | 550 | |
e2bbc343 | 551 | if (dev_priv->psr.active) { |
0d0c2794 | 552 | /* Put VLV PSR back to PSR_state 0 (disabled). */ |
eb0241c1 | 553 | if (intel_wait_for_register(dev_priv, |
d2419ffc | 554 | VLV_PSRSTAT(crtc->pipe), |
eb0241c1 CW |
555 | VLV_EDP_PSR_IN_TRANS, |
556 | 0, | |
557 | 1)) | |
e2bbc343 RV |
558 | WARN(1, "PSR transition took longer than expected\n"); |
559 | ||
d2419ffc | 560 | val = I915_READ(VLV_PSRCTL(crtc->pipe)); |
e2bbc343 RV |
561 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; |
562 | val &= ~VLV_EDP_PSR_ENABLE; | |
563 | val &= ~VLV_EDP_PSR_MODE_MASK; | |
d2419ffc | 564 | I915_WRITE(VLV_PSRCTL(crtc->pipe), val); |
e2bbc343 RV |
565 | |
566 | dev_priv->psr.active = false; | |
567 | } else { | |
d2419ffc | 568 | WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe)); |
0bc12bcb | 569 | } |
e2bbc343 RV |
570 | } |
571 | ||
d2419ffc VS |
572 | static void hsw_psr_disable(struct intel_dp *intel_dp, |
573 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
574 | { |
575 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
576 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 577 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
578 | |
579 | if (dev_priv->psr.active) { | |
14c6547d | 580 | i915_reg_t psr_status; |
77affa31 CW |
581 | u32 psr_status_mask; |
582 | ||
f40c484b NV |
583 | if (dev_priv->psr.aux_frame_sync) |
584 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
585 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
586 | 0); | |
587 | ||
3fcb0ca1 | 588 | if (dev_priv->psr.psr2_support) { |
14c6547d | 589 | psr_status = EDP_PSR2_STATUS_CTL; |
77affa31 CW |
590 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
591 | ||
14c6547d DP |
592 | I915_WRITE(EDP_PSR2_CTL, |
593 | I915_READ(EDP_PSR2_CTL) & | |
77affa31 CW |
594 | ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); |
595 | ||
3fcb0ca1 | 596 | } else { |
14c6547d | 597 | psr_status = EDP_PSR_STATUS_CTL; |
77affa31 CW |
598 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
599 | ||
14c6547d DP |
600 | I915_WRITE(EDP_PSR_CTL, |
601 | I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); | |
3fcb0ca1 | 602 | } |
77affa31 CW |
603 | |
604 | /* Wait till PSR is idle */ | |
605 | if (intel_wait_for_register(dev_priv, | |
14c6547d | 606 | psr_status, psr_status_mask, 0, |
77affa31 CW |
607 | 2000)) |
608 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
609 | ||
0bc12bcb RV |
610 | dev_priv->psr.active = false; |
611 | } else { | |
3fcb0ca1 NV |
612 | if (dev_priv->psr.psr2_support) |
613 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
614 | else | |
615 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb | 616 | } |
e2bbc343 RV |
617 | } |
618 | ||
619 | /** | |
620 | * intel_psr_disable - Disable PSR | |
621 | * @intel_dp: Intel DP | |
d2419ffc | 622 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
623 | * |
624 | * This function needs to be called before disabling pipe. | |
625 | */ | |
d2419ffc VS |
626 | void intel_psr_disable(struct intel_dp *intel_dp, |
627 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
628 | { |
629 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
630 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 631 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 | 632 | |
4d90f2d5 | 633 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
634 | return; |
635 | ||
e2bbc343 RV |
636 | mutex_lock(&dev_priv->psr.lock); |
637 | if (!dev_priv->psr.enabled) { | |
638 | mutex_unlock(&dev_priv->psr.lock); | |
639 | return; | |
640 | } | |
641 | ||
424644c2 | 642 | dev_priv->psr.disable_source(intel_dp, old_crtc_state); |
0bc12bcb | 643 | |
b6e4d534 RV |
644 | /* Disable PSR on Sink */ |
645 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
646 | ||
0bc12bcb RV |
647 | dev_priv->psr.enabled = NULL; |
648 | mutex_unlock(&dev_priv->psr.lock); | |
649 | ||
650 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
651 | } | |
652 | ||
653 | static void intel_psr_work(struct work_struct *work) | |
654 | { | |
655 | struct drm_i915_private *dev_priv = | |
656 | container_of(work, typeof(*dev_priv), psr.work.work); | |
657 | struct intel_dp *intel_dp = dev_priv->psr.enabled; | |
995d3047 RV |
658 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; |
659 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
0bc12bcb RV |
660 | |
661 | /* We have to make sure PSR is ready for re-enable | |
662 | * otherwise it keeps disabled until next full enable/disable cycle. | |
663 | * PSR might take some time to get fully disabled | |
664 | * and be ready for re-enable. | |
665 | */ | |
2d1fe073 | 666 | if (HAS_DDI(dev_priv)) { |
3fcb0ca1 NV |
667 | if (dev_priv->psr.psr2_support) { |
668 | if (intel_wait_for_register(dev_priv, | |
669 | EDP_PSR2_STATUS_CTL, | |
670 | EDP_PSR2_STATUS_STATE_MASK, | |
671 | 0, | |
672 | 50)) { | |
673 | DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n"); | |
674 | return; | |
675 | } | |
676 | } else { | |
677 | if (intel_wait_for_register(dev_priv, | |
678 | EDP_PSR_STATUS_CTL, | |
679 | EDP_PSR_STATUS_STATE_MASK, | |
680 | 0, | |
681 | 50)) { | |
682 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
683 | return; | |
684 | } | |
995d3047 RV |
685 | } |
686 | } else { | |
12bb6319 CW |
687 | if (intel_wait_for_register(dev_priv, |
688 | VLV_PSRSTAT(pipe), | |
689 | VLV_EDP_PSR_IN_TRANS, | |
690 | 0, | |
691 | 1)) { | |
995d3047 RV |
692 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); |
693 | return; | |
694 | } | |
0bc12bcb | 695 | } |
0bc12bcb RV |
696 | mutex_lock(&dev_priv->psr.lock); |
697 | intel_dp = dev_priv->psr.enabled; | |
698 | ||
699 | if (!intel_dp) | |
700 | goto unlock; | |
701 | ||
702 | /* | |
703 | * The delayed work can race with an invalidate hence we need to | |
704 | * recheck. Since psr_flush first clears this and then reschedules we | |
705 | * won't ever miss a flush when bailing out here. | |
706 | */ | |
707 | if (dev_priv->psr.busy_frontbuffer_bits) | |
708 | goto unlock; | |
709 | ||
e2bbc343 | 710 | intel_psr_activate(intel_dp); |
0bc12bcb RV |
711 | unlock: |
712 | mutex_unlock(&dev_priv->psr.lock); | |
713 | } | |
714 | ||
5748b6a1 | 715 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
0bc12bcb | 716 | { |
995d3047 RV |
717 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
718 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
719 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
720 | u32 val; | |
0bc12bcb | 721 | |
995d3047 RV |
722 | if (!dev_priv->psr.active) |
723 | return; | |
724 | ||
5748b6a1 | 725 | if (HAS_DDI(dev_priv)) { |
f40c484b NV |
726 | if (dev_priv->psr.aux_frame_sync) |
727 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
728 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, | |
729 | 0); | |
3fcb0ca1 NV |
730 | if (dev_priv->psr.psr2_support) { |
731 | val = I915_READ(EDP_PSR2_CTL); | |
732 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
733 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
734 | } else { | |
735 | val = I915_READ(EDP_PSR_CTL); | |
736 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
737 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
738 | } | |
995d3047 RV |
739 | } else { |
740 | val = I915_READ(VLV_PSRCTL(pipe)); | |
741 | ||
0d0c2794 RV |
742 | /* |
743 | * Here we do the transition drirectly from | |
744 | * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to | |
745 | * PSR_state 5 (exit). | |
746 | * PSR State 4 (active with single frame update) can be skipped. | |
747 | * On PSR_state 5 (exit) Hardware is responsible to transition | |
748 | * back to PSR_state 1 (inactive). | |
749 | * Now we are at Same state after vlv_psr_enable_source. | |
995d3047 RV |
750 | */ |
751 | val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; | |
752 | I915_WRITE(VLV_PSRCTL(pipe), val); | |
753 | ||
0d0c2794 RV |
754 | /* |
755 | * Send AUX wake up - Spec says after transitioning to PSR | |
995d3047 RV |
756 | * active we have to send AUX wake up by writing 01h in DPCD |
757 | * 600h of sink device. | |
758 | * XXX: This might slow down the transition, but without this | |
759 | * HW doesn't complete the transition to PSR_state 1 and we | |
760 | * never get the screen updated. | |
761 | */ | |
762 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, | |
763 | DP_SET_POWER_D0); | |
0bc12bcb RV |
764 | } |
765 | ||
995d3047 | 766 | dev_priv->psr.active = false; |
0bc12bcb RV |
767 | } |
768 | ||
c7240c3b RV |
769 | /** |
770 | * intel_psr_single_frame_update - Single Frame Update | |
5748b6a1 | 771 | * @dev_priv: i915 device |
20c8838b | 772 | * @frontbuffer_bits: frontbuffer plane tracking bits |
c7240c3b RV |
773 | * |
774 | * Some platforms support a single frame update feature that is used to | |
775 | * send and update only one frame on Remote Frame Buffer. | |
776 | * So far it is only implemented for Valleyview and Cherryview because | |
777 | * hardware requires this to be done before a page flip. | |
778 | */ | |
5748b6a1 | 779 | void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, |
20c8838b | 780 | unsigned frontbuffer_bits) |
c7240c3b | 781 | { |
c7240c3b RV |
782 | struct drm_crtc *crtc; |
783 | enum pipe pipe; | |
784 | u32 val; | |
785 | ||
4371d896 | 786 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
787 | return; |
788 | ||
c7240c3b RV |
789 | /* |
790 | * Single frame update is already supported on BDW+ but it requires | |
791 | * many W/A and it isn't really needed. | |
792 | */ | |
5748b6a1 | 793 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
c7240c3b RV |
794 | return; |
795 | ||
796 | mutex_lock(&dev_priv->psr.lock); | |
797 | if (!dev_priv->psr.enabled) { | |
798 | mutex_unlock(&dev_priv->psr.lock); | |
799 | return; | |
800 | } | |
801 | ||
802 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
803 | pipe = to_intel_crtc(crtc)->pipe; | |
c7240c3b | 804 | |
20c8838b DV |
805 | if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) { |
806 | val = I915_READ(VLV_PSRCTL(pipe)); | |
c7240c3b | 807 | |
20c8838b DV |
808 | /* |
809 | * We need to set this bit before writing registers for a flip. | |
810 | * This bit will be self-clear when it gets to the PSR active state. | |
811 | */ | |
812 | I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); | |
813 | } | |
c7240c3b RV |
814 | mutex_unlock(&dev_priv->psr.lock); |
815 | } | |
816 | ||
b2b89f55 RV |
817 | /** |
818 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 819 | * @dev_priv: i915 device |
b2b89f55 RV |
820 | * @frontbuffer_bits: frontbuffer plane tracking bits |
821 | * | |
822 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
823 | * with the software frontbuffer tracking. This function gets called every | |
824 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
825 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
826 | * | |
827 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
828 | */ | |
5748b6a1 | 829 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
20c8838b | 830 | unsigned frontbuffer_bits) |
0bc12bcb | 831 | { |
0bc12bcb RV |
832 | struct drm_crtc *crtc; |
833 | enum pipe pipe; | |
834 | ||
4371d896 | 835 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
836 | return; |
837 | ||
0bc12bcb RV |
838 | mutex_lock(&dev_priv->psr.lock); |
839 | if (!dev_priv->psr.enabled) { | |
840 | mutex_unlock(&dev_priv->psr.lock); | |
841 | return; | |
842 | } | |
843 | ||
844 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
845 | pipe = to_intel_crtc(crtc)->pipe; | |
846 | ||
0bc12bcb | 847 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 848 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
849 | |
850 | if (frontbuffer_bits) | |
5748b6a1 | 851 | intel_psr_exit(dev_priv); |
ec76d629 | 852 | |
0bc12bcb RV |
853 | mutex_unlock(&dev_priv->psr.lock); |
854 | } | |
855 | ||
b2b89f55 RV |
856 | /** |
857 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 858 | * @dev_priv: i915 device |
b2b89f55 | 859 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 860 | * @origin: which operation caused the flush |
b2b89f55 RV |
861 | * |
862 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
863 | * with the software frontbuffer tracking. This function gets called every | |
864 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
865 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
866 | * | |
867 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
868 | */ | |
5748b6a1 | 869 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 870 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 871 | { |
0bc12bcb RV |
872 | struct drm_crtc *crtc; |
873 | enum pipe pipe; | |
874 | ||
4371d896 | 875 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
876 | return; |
877 | ||
0bc12bcb RV |
878 | mutex_lock(&dev_priv->psr.lock); |
879 | if (!dev_priv->psr.enabled) { | |
880 | mutex_unlock(&dev_priv->psr.lock); | |
881 | return; | |
882 | } | |
883 | ||
884 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
885 | pipe = to_intel_crtc(crtc)->pipe; | |
ec76d629 DV |
886 | |
887 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
888 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
889 | ||
921ec285 RV |
890 | /* By definition flush = invalidate + flush */ |
891 | if (frontbuffer_bits) | |
5748b6a1 | 892 | intel_psr_exit(dev_priv); |
995d3047 | 893 | |
0bc12bcb | 894 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
d0ac896a RV |
895 | if (!work_busy(&dev_priv->psr.work.work)) |
896 | schedule_delayed_work(&dev_priv->psr.work, | |
20bb97fe | 897 | msecs_to_jiffies(100)); |
0bc12bcb RV |
898 | mutex_unlock(&dev_priv->psr.lock); |
899 | } | |
900 | ||
b2b89f55 RV |
901 | /** |
902 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 903 | * @dev_priv: i915 device private |
b2b89f55 RV |
904 | * |
905 | * This function is called only once at driver load to initialize basic | |
906 | * PSR stuff. | |
907 | */ | |
c39055b0 | 908 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 909 | { |
0f328da6 RV |
910 | if (!HAS_PSR(dev_priv)) |
911 | return; | |
912 | ||
443a389f VS |
913 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
914 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
915 | ||
2ee7dc49 | 916 | /* Per platform default: all disabled. */ |
4f044a88 MW |
917 | if (i915_modparams.enable_psr == -1) |
918 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 919 | |
65f61b42 | 920 | /* Set link_standby x link_off defaults */ |
8652744b | 921 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
922 | /* HSW and BDW require workarounds that we don't implement. */ |
923 | dev_priv->psr.link_standby = false; | |
920a14b2 | 924 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
60e5ffe3 RV |
925 | /* On VLV and CHV only standby mode is supported. */ |
926 | dev_priv->psr.link_standby = true; | |
927 | else | |
928 | /* For new platforms let's respect VBT back again */ | |
929 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
930 | ||
65f61b42 | 931 | /* Override link_standby x link_off defaults */ |
4f044a88 | 932 | if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) { |
65f61b42 RV |
933 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); |
934 | dev_priv->psr.link_standby = true; | |
935 | } | |
4f044a88 | 936 | if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) { |
65f61b42 RV |
937 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); |
938 | dev_priv->psr.link_standby = false; | |
939 | } | |
940 | ||
0bc12bcb RV |
941 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |
942 | mutex_init(&dev_priv->psr.lock); | |
424644c2 RV |
943 | |
944 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
d0d5e0d7 | 945 | dev_priv->psr.enable_source = vlv_psr_enable_source; |
424644c2 | 946 | dev_priv->psr.disable_source = vlv_psr_disable; |
49ad316f | 947 | dev_priv->psr.enable_sink = vlv_psr_enable_sink; |
e3702ac9 | 948 | dev_priv->psr.activate = vlv_psr_activate; |
2a5db87f | 949 | dev_priv->psr.setup_vsc = vlv_psr_setup_vsc; |
424644c2 | 950 | } else { |
d0d5e0d7 | 951 | dev_priv->psr.enable_source = hsw_psr_enable_source; |
424644c2 | 952 | dev_priv->psr.disable_source = hsw_psr_disable; |
49ad316f | 953 | dev_priv->psr.enable_sink = hsw_psr_enable_sink; |
e3702ac9 | 954 | dev_priv->psr.activate = hsw_psr_activate; |
2a5db87f | 955 | dev_priv->psr.setup_vsc = hsw_psr_setup_vsc; |
424644c2 | 956 | } |
0bc12bcb | 957 | } |