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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
b891d5e4 DP |
59 | static inline enum intel_display_power_domain |
60 | psr_aux_domain(struct intel_dp *intel_dp) | |
61 | { | |
62 | /* CNL HW requires corresponding AUX IOs to be powered up for PSR. | |
63 | * However, for non-A AUX ports the corresponding non-EDP transcoders | |
64 | * would have already enabled power well 2 and DC_OFF. This means we can | |
65 | * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a | |
66 | * specific AUX_IO reference without powering up any extra wells. | |
67 | * Note that PSR is enabled only on Port A even though this function | |
68 | * returns the correct domain for other ports too. | |
69 | */ | |
70 | return intel_dp->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : | |
71 | intel_dp->aux_power_domain; | |
72 | } | |
73 | ||
74 | static void psr_aux_io_power_get(struct intel_dp *intel_dp) | |
75 | { | |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
77 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
78 | ||
79 | if (INTEL_GEN(dev_priv) < 10) | |
80 | return; | |
81 | ||
82 | intel_display_power_get(dev_priv, psr_aux_domain(intel_dp)); | |
83 | } | |
84 | ||
85 | static void psr_aux_io_power_put(struct intel_dp *intel_dp) | |
86 | { | |
87 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
88 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
89 | ||
90 | if (INTEL_GEN(dev_priv) < 10) | |
91 | return; | |
92 | ||
93 | intel_display_power_put(dev_priv, psr_aux_domain(intel_dp)); | |
94 | } | |
95 | ||
54fd3149 DP |
96 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug) |
97 | { | |
98 | u32 debug_mask, mask; | |
99 | ||
54fd3149 DP |
100 | mask = EDP_PSR_ERROR(TRANSCODER_EDP); |
101 | debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) | | |
102 | EDP_PSR_PRE_ENTRY(TRANSCODER_EDP); | |
103 | ||
104 | if (INTEL_GEN(dev_priv) >= 8) { | |
105 | mask |= EDP_PSR_ERROR(TRANSCODER_A) | | |
106 | EDP_PSR_ERROR(TRANSCODER_B) | | |
107 | EDP_PSR_ERROR(TRANSCODER_C); | |
108 | ||
109 | debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) | | |
110 | EDP_PSR_PRE_ENTRY(TRANSCODER_A) | | |
111 | EDP_PSR_POST_EXIT(TRANSCODER_B) | | |
112 | EDP_PSR_PRE_ENTRY(TRANSCODER_B) | | |
113 | EDP_PSR_POST_EXIT(TRANSCODER_C) | | |
114 | EDP_PSR_PRE_ENTRY(TRANSCODER_C); | |
115 | } | |
116 | ||
117 | if (debug) | |
118 | mask |= debug_mask; | |
119 | ||
120 | WRITE_ONCE(dev_priv->psr.debug, debug); | |
121 | I915_WRITE(EDP_PSR_IMR, ~mask); | |
122 | } | |
123 | ||
bc18b4df JRS |
124 | static void psr_event_print(u32 val, bool psr2_enabled) |
125 | { | |
126 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
127 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
128 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
129 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
130 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
131 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
132 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
133 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
134 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
135 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
136 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
137 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
138 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
139 | if (val & PSR_EVENT_MEMORY_UP) | |
140 | DRM_DEBUG_KMS("\tMemory up\n"); | |
141 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
142 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
143 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
144 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
145 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
146 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
147 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
148 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
149 | if (val & PSR_EVENT_HDCP_ENABLE) | |
150 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
151 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
152 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
153 | if (val & PSR_EVENT_VBI_ENABLE) | |
154 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
155 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
156 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
157 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
158 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
159 | } | |
160 | ||
54fd3149 DP |
161 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
162 | { | |
163 | u32 transcoders = BIT(TRANSCODER_EDP); | |
164 | enum transcoder cpu_transcoder; | |
3f983e54 | 165 | ktime_t time_ns = ktime_get(); |
54fd3149 DP |
166 | |
167 | if (INTEL_GEN(dev_priv) >= 8) | |
168 | transcoders |= BIT(TRANSCODER_A) | | |
169 | BIT(TRANSCODER_B) | | |
170 | BIT(TRANSCODER_C); | |
171 | ||
172 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
173 | /* FIXME: Exit PSR and link train manually when this happens. */ | |
174 | if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) | |
175 | DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n", | |
176 | transcoder_name(cpu_transcoder)); | |
177 | ||
3f983e54 DP |
178 | if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) { |
179 | dev_priv->psr.last_entry_attempt = time_ns; | |
54fd3149 DP |
180 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", |
181 | transcoder_name(cpu_transcoder)); | |
3f983e54 | 182 | } |
54fd3149 | 183 | |
3f983e54 DP |
184 | if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) { |
185 | dev_priv->psr.last_exit = time_ns; | |
54fd3149 DP |
186 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", |
187 | transcoder_name(cpu_transcoder)); | |
bc18b4df JRS |
188 | |
189 | if (INTEL_GEN(dev_priv) >= 9) { | |
190 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
191 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
192 | ||
193 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); | |
194 | psr_event_print(val, psr2_enabled); | |
195 | } | |
3f983e54 | 196 | } |
54fd3149 DP |
197 | } |
198 | } | |
199 | ||
aee3bac0 | 200 | static bool intel_dp_get_y_coord_required(struct intel_dp *intel_dp) |
77fe36ff DP |
201 | { |
202 | uint8_t psr_caps = 0; | |
203 | ||
204 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) | |
205 | return false; | |
206 | return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
207 | } | |
208 | ||
209 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) | |
210 | { | |
211 | uint8_t dprx = 0; | |
212 | ||
213 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
214 | &dprx) != 1) | |
215 | return false; | |
216 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
217 | } | |
218 | ||
219 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) | |
220 | { | |
221 | uint8_t alpm_caps = 0; | |
222 | ||
223 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
224 | &alpm_caps) != 1) | |
225 | return false; | |
226 | return alpm_caps & DP_ALPM_CAP; | |
227 | } | |
228 | ||
26e5378d JRS |
229 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
230 | { | |
231 | u8 val = 0; | |
232 | ||
233 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
234 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
235 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
236 | else | |
237 | DRM_ERROR("Unable to get sink synchronization latency\n"); | |
238 | return val; | |
239 | } | |
240 | ||
77fe36ff DP |
241 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
242 | { | |
243 | struct drm_i915_private *dev_priv = | |
244 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
245 | ||
246 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, | |
247 | sizeof(intel_dp->psr_dpcd)); | |
248 | ||
8cf6da7e DP |
249 | if (!intel_dp->psr_dpcd[0]) |
250 | return; | |
251 | ||
252 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", | |
253 | intel_dp->psr_dpcd[0]); | |
254 | dev_priv->psr.sink_support = true; | |
77fe36ff DP |
255 | |
256 | if (INTEL_GEN(dev_priv) >= 9 && | |
aee3bac0 JRS |
257 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
258 | /* | |
259 | * All panels that supports PSR version 03h (PSR2 + | |
260 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
261 | * only sure that it is going to be used when required by the | |
262 | * panel. This way panel is capable to do selective update | |
263 | * without a aux frame sync. | |
264 | * | |
265 | * To support PSR version 02h and PSR version 03h without | |
266 | * Y-coordinate requirement panels we would need to enable | |
267 | * GTC first. | |
268 | */ | |
95f28d2e JRS |
269 | dev_priv->psr.sink_psr2_support = |
270 | intel_dp_get_y_coord_required(intel_dp); | |
8cf6da7e DP |
271 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
272 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 273 | |
95f28d2e | 274 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
275 | dev_priv->psr.colorimetry_support = |
276 | intel_dp_get_colorimetry_status(intel_dp); | |
277 | dev_priv->psr.alpm = | |
278 | intel_dp_get_alpm_status(intel_dp); | |
26e5378d JRS |
279 | dev_priv->psr.sink_sync_latency = |
280 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff DP |
281 | } |
282 | } | |
283 | } | |
284 | ||
2ce4df87 RV |
285 | static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, |
286 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 287 | { |
97da2ef4 | 288 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
d2419ffc VS |
289 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
290 | struct edp_vsc_psr psr_vsc; | |
474d1ec4 | 291 | |
95f28d2e | 292 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
293 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
294 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
295 | psr_vsc.sdp_header.HB0 = 0; | |
296 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 297 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
298 | psr_vsc.sdp_header.HB2 = 0x5; |
299 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 300 | } else { |
2ce4df87 RV |
301 | psr_vsc.sdp_header.HB2 = 0x4; |
302 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 303 | } |
97da2ef4 | 304 | } else { |
2ce4df87 RV |
305 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
306 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
307 | psr_vsc.sdp_header.HB0 = 0; | |
308 | psr_vsc.sdp_header.HB1 = 0x7; | |
309 | psr_vsc.sdp_header.HB2 = 0x2; | |
310 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
311 | } |
312 | ||
1d776538 VS |
313 | intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state, |
314 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); | |
474d1ec4 SJ |
315 | } |
316 | ||
b90eed08 | 317 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb RV |
318 | { |
319 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d544e918 DP |
320 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
321 | u32 aux_clock_divider, aux_ctl; | |
322 | int i; | |
0bc12bcb RV |
323 | static const uint8_t aux_msg[] = { |
324 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
325 | [1] = DP_SET_POWER >> 8, | |
326 | [2] = DP_SET_POWER & 0xff, | |
327 | [3] = 1 - 1, | |
328 | [4] = DP_SET_POWER_D0, | |
329 | }; | |
d544e918 DP |
330 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
331 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
332 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
333 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
334 | |
335 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 336 | for (i = 0; i < sizeof(aux_msg); i += 4) |
d544e918 | 337 | I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), |
b90eed08 DP |
338 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
339 | ||
d544e918 DP |
340 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
341 | ||
342 | /* Start with bits set for DDI_AUX_CTL register */ | |
b90eed08 DP |
343 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg), |
344 | aux_clock_divider); | |
d544e918 DP |
345 | |
346 | /* Select only valid bits for SRD_AUX_CTL */ | |
347 | aux_ctl &= psr_aux_mask; | |
348 | I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); | |
b90eed08 DP |
349 | } |
350 | ||
351 | static void hsw_psr_enable_sink(struct intel_dp *intel_dp) | |
352 | { | |
353 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
354 | struct drm_device *dev = dig_port->base.base.dev; | |
355 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4df4925b | 356 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 357 | |
340c93c0 | 358 | /* Enable ALPM at sink for psr2 */ |
95f28d2e | 359 | if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm) |
340c93c0 NV |
360 | drm_dp_dpcd_writeb(&intel_dp->aux, |
361 | DP_RECEIVER_ALPM_CONFIG, | |
362 | DP_ALPM_ENABLE); | |
4df4925b JRS |
363 | |
364 | if (dev_priv->psr.psr2_enabled) | |
365 | dpcd_val |= DP_PSR_ENABLE_PSR2; | |
6f32ea7e | 366 | if (dev_priv->psr.link_standby) |
4df4925b JRS |
367 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; |
368 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); | |
6f32ea7e | 369 | |
d544e918 | 370 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
371 | } |
372 | ||
ed63d24b | 373 | static void hsw_activate_psr1(struct intel_dp *intel_dp) |
0bc12bcb RV |
374 | { |
375 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
376 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 377 | struct drm_i915_private *dev_priv = to_i915(dev); |
474d1ec4 | 378 | |
0bc12bcb | 379 | uint32_t max_sleep_time = 0x1f; |
40918e0b RV |
380 | /* |
381 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
382 | * Let's use 6 as the minimum to cover all known cases including | |
383 | * the off-by-one issue that HW has in some cases. Also there are | |
384 | * cases where sink should be able to train | |
385 | * with the 5 or 6 idle patterns. | |
d44b4dcb | 386 | */ |
40918e0b | 387 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
50db1390 DV |
388 | uint32_t val = EDP_PSR_ENABLE; |
389 | ||
390 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; | |
391 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; | |
7370c68d | 392 | |
772c2a51 | 393 | if (IS_HASWELL(dev_priv)) |
7370c68d | 394 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0bc12bcb | 395 | |
60e5ffe3 RV |
396 | if (dev_priv->psr.link_standby) |
397 | val |= EDP_PSR_LINK_STANDBY; | |
398 | ||
77312ae8 VN |
399 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
400 | val |= EDP_PSR_TP1_TIME_0us; | |
401 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) | |
50db1390 | 402 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
403 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
404 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 405 | else |
77312ae8 | 406 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 407 | |
77312ae8 VN |
408 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
409 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
410 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
50db1390 | 411 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
412 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
413 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 414 | else |
77312ae8 | 415 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
416 | |
417 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
418 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
419 | val |= EDP_PSR_TP1_TP3_SEL; | |
420 | else | |
421 | val |= EDP_PSR_TP1_TP2_SEL; | |
422 | ||
912d6412 | 423 | val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; |
50db1390 | 424 | I915_WRITE(EDP_PSR_CTL, val); |
3fcb0ca1 | 425 | } |
50db1390 | 426 | |
ed63d24b | 427 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 NV |
428 | { |
429 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
430 | struct drm_device *dev = dig_port->base.base.dev; | |
431 | struct drm_i915_private *dev_priv = to_i915(dev); | |
432 | /* | |
433 | * Let's respect VBT in case VBT asks a higher idle_frame value. | |
434 | * Let's use 6 as the minimum to cover all known cases including | |
435 | * the off-by-one issue that HW has in some cases. Also there are | |
436 | * cases where sink should be able to train | |
437 | * with the 5 or 6 idle patterns. | |
438 | */ | |
439 | uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); | |
26e5378d | 440 | u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; |
50db1390 DV |
441 | |
442 | /* FIXME: selective update is probably totally broken because it doesn't | |
443 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
444 | * good enough. */ | |
5e87325f | 445 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
446 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
447 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 448 | |
26e5378d | 449 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 450 | |
77312ae8 VN |
451 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && |
452 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) | |
453 | val |= EDP_PSR2_TP2_TIME_50us; | |
454 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
455 | val |= EDP_PSR2_TP2_TIME_100us; | |
456 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) | |
457 | val |= EDP_PSR2_TP2_TIME_500us; | |
50db1390 | 458 | else |
77312ae8 | 459 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 460 | |
50db1390 | 461 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
462 | } |
463 | ||
ed63d24b | 464 | static void hsw_psr_activate(struct intel_dp *intel_dp) |
3fcb0ca1 NV |
465 | { |
466 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
467 | struct drm_device *dev = dig_port->base.base.dev; | |
468 | struct drm_i915_private *dev_priv = to_i915(dev); | |
469 | ||
ed63d24b RV |
470 | /* On HSW+ after we enable PSR on source it will activate it |
471 | * as soon as it match configure idle_frame count. So | |
472 | * we just actually enable it here on activation time. | |
473 | */ | |
474 | ||
3fcb0ca1 | 475 | /* psr1 and psr2 are mutually exclusive.*/ |
95f28d2e | 476 | if (dev_priv->psr.psr2_enabled) |
ed63d24b | 477 | hsw_activate_psr2(intel_dp); |
3fcb0ca1 | 478 | else |
ed63d24b | 479 | hsw_activate_psr1(intel_dp); |
3fcb0ca1 NV |
480 | } |
481 | ||
c4932d79 RV |
482 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
483 | struct intel_crtc_state *crtc_state) | |
484 | { | |
485 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
486 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
c90c275c DP |
487 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
488 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
489 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 RV |
490 | |
491 | /* | |
492 | * FIXME psr2_support is messed up. It's both computed | |
493 | * dynamically during PSR enable, and extracted from sink | |
494 | * caps during eDP detection. | |
495 | */ | |
95f28d2e | 496 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
497 | return false; |
498 | ||
c90c275c DP |
499 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
500 | psr_max_h = 4096; | |
501 | psr_max_v = 2304; | |
502 | } else if (IS_GEN9(dev_priv)) { | |
503 | psr_max_h = 3640; | |
504 | psr_max_v = 2304; | |
505 | } | |
506 | ||
507 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
508 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
509 | crtc_hdisplay, crtc_vdisplay, | |
510 | psr_max_h, psr_max_v); | |
c4932d79 RV |
511 | return false; |
512 | } | |
513 | ||
c4932d79 RV |
514 | return true; |
515 | } | |
516 | ||
4d90f2d5 VS |
517 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
518 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
519 | { |
520 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
4d90f2d5 | 521 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
dfd2e9ab | 522 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 523 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 524 | int psr_setup_time; |
0bc12bcb | 525 | |
4371d896 | 526 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
527 | return; |
528 | ||
529 | if (!i915_modparams.enable_psr) { | |
530 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
531 | return; | |
532 | } | |
0bc12bcb | 533 | |
dc9b5a0c RV |
534 | /* |
535 | * HSW spec explicitly says PSR is tied to port A. | |
536 | * BDW+ platforms with DDI implementation of PSR have different | |
537 | * PSR registers per transcoder and we only implement transcoder EDP | |
538 | * ones. Since by Display design transcoder EDP is tied to port A | |
539 | * we can safely escape based on the port A. | |
540 | */ | |
ce3508fd | 541 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 542 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 543 | return; |
0bc12bcb RV |
544 | } |
545 | ||
772c2a51 | 546 | if (IS_HASWELL(dev_priv) && |
4d90f2d5 | 547 | I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & |
c8e68b7e | 548 | S3D_ENABLE) { |
0bc12bcb | 549 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
4d90f2d5 | 550 | return; |
0bc12bcb RV |
551 | } |
552 | ||
772c2a51 | 553 | if (IS_HASWELL(dev_priv) && |
dfd2e9ab | 554 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb | 555 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
4d90f2d5 | 556 | return; |
0bc12bcb RV |
557 | } |
558 | ||
dfd2e9ab VS |
559 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
560 | if (psr_setup_time < 0) { | |
561 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
562 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 563 | return; |
dfd2e9ab VS |
564 | } |
565 | ||
566 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
567 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
568 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
569 | psr_setup_time); | |
4d90f2d5 VS |
570 | return; |
571 | } | |
572 | ||
06d058e1 DP |
573 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { |
574 | DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n"); | |
575 | return; | |
576 | } | |
577 | ||
4d90f2d5 | 578 | crtc_state->has_psr = true; |
c4932d79 RV |
579 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
580 | DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); | |
0bc12bcb RV |
581 | } |
582 | ||
e2bbc343 | 583 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
584 | { |
585 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
586 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 587 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 588 | |
95f28d2e | 589 | if (dev_priv->psr.psr2_enabled) |
3fcb0ca1 NV |
590 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
591 | else | |
592 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb RV |
593 | WARN_ON(dev_priv->psr.active); |
594 | lockdep_assert_held(&dev_priv->psr.lock); | |
595 | ||
e3702ac9 | 596 | dev_priv->psr.activate(intel_dp); |
0bc12bcb RV |
597 | dev_priv->psr.active = true; |
598 | } | |
599 | ||
4d1fa22f RV |
600 | static void hsw_psr_enable_source(struct intel_dp *intel_dp, |
601 | const struct intel_crtc_state *crtc_state) | |
602 | { | |
603 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
604 | struct drm_device *dev = dig_port->base.base.dev; | |
605 | struct drm_i915_private *dev_priv = to_i915(dev); | |
606 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
4d1fa22f | 607 | |
b891d5e4 DP |
608 | psr_aux_io_power_get(intel_dp); |
609 | ||
d544e918 DP |
610 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
611 | * use hardcoded values PSR AUX transactions | |
612 | */ | |
613 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
614 | hsw_psr_setup_aux(intel_dp); | |
615 | ||
95f28d2e | 616 | if (dev_priv->psr.psr2_enabled) { |
5e87325f JRS |
617 | u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); |
618 | ||
619 | if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) | |
620 | chicken |= (PSR2_VSC_ENABLE_PROG_HEADER | |
621 | | PSR2_ADD_VERTICAL_LINE_COUNT); | |
622 | ||
623 | else | |
624 | chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL; | |
4d1fa22f RV |
625 | I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); |
626 | ||
861023e0 | 627 | I915_WRITE(EDP_PSR_DEBUG, |
4d1fa22f RV |
628 | EDP_PSR_DEBUG_MASK_MEMUP | |
629 | EDP_PSR_DEBUG_MASK_HPD | | |
630 | EDP_PSR_DEBUG_MASK_LPSP | | |
631 | EDP_PSR_DEBUG_MASK_MAX_SLEEP | | |
632 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
633 | } else { | |
634 | /* | |
635 | * Per Spec: Avoid continuous PSR exit by masking MEMUP | |
636 | * and HPD. also mask LPSP to avoid dependency on other | |
637 | * drivers that might block runtime_pm besides | |
638 | * preventing other hw tracking issues now we can rely | |
639 | * on frontbuffer tracking. | |
640 | */ | |
861023e0 | 641 | I915_WRITE(EDP_PSR_DEBUG, |
4d1fa22f RV |
642 | EDP_PSR_DEBUG_MASK_MEMUP | |
643 | EDP_PSR_DEBUG_MASK_HPD | | |
75cbec03 RS |
644 | EDP_PSR_DEBUG_MASK_LPSP | |
645 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
4d1fa22f RV |
646 | } |
647 | } | |
648 | ||
b2b89f55 RV |
649 | /** |
650 | * intel_psr_enable - Enable PSR | |
651 | * @intel_dp: Intel DP | |
d2419ffc | 652 | * @crtc_state: new CRTC state |
b2b89f55 RV |
653 | * |
654 | * This function can only be called after the pipe is fully trained and enabled. | |
655 | */ | |
d2419ffc VS |
656 | void intel_psr_enable(struct intel_dp *intel_dp, |
657 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
658 | { |
659 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
660 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 661 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 662 | |
4d90f2d5 | 663 | if (!crtc_state->has_psr) |
0bc12bcb | 664 | return; |
0bc12bcb | 665 | |
c9ef291a DP |
666 | if (WARN_ON(!CAN_PSR(dev_priv))) |
667 | return; | |
668 | ||
da83ef85 | 669 | WARN_ON(dev_priv->drrs.dp); |
0bc12bcb RV |
670 | mutex_lock(&dev_priv->psr.lock); |
671 | if (dev_priv->psr.enabled) { | |
672 | DRM_DEBUG_KMS("PSR already in use\n"); | |
673 | goto unlock; | |
674 | } | |
675 | ||
95f28d2e | 676 | dev_priv->psr.psr2_enabled = crtc_state->has_psr2; |
0bc12bcb RV |
677 | dev_priv->psr.busy_frontbuffer_bits = 0; |
678 | ||
2a5db87f | 679 | dev_priv->psr.setup_vsc(intel_dp, crtc_state); |
49ad316f | 680 | dev_priv->psr.enable_sink(intel_dp); |
d0d5e0d7 | 681 | dev_priv->psr.enable_source(intel_dp, crtc_state); |
29d1efe0 RV |
682 | dev_priv->psr.enabled = intel_dp; |
683 | ||
684 | if (INTEL_GEN(dev_priv) >= 9) { | |
685 | intel_psr_activate(intel_dp); | |
686 | } else { | |
687 | /* | |
688 | * FIXME: Activation should happen immediately since this | |
689 | * function is just called after pipe is fully trained and | |
690 | * enabled. | |
691 | * However on some platforms we face issues when first | |
692 | * activation follows a modeset so quickly. | |
29d1efe0 RV |
693 | * - On HSW/BDW we get a recoverable frozen screen until |
694 | * next exit-activate sequence. | |
695 | */ | |
d0ac896a RV |
696 | schedule_delayed_work(&dev_priv->psr.work, |
697 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
29d1efe0 | 698 | } |
d0ac896a | 699 | |
0bc12bcb RV |
700 | unlock: |
701 | mutex_unlock(&dev_priv->psr.lock); | |
702 | } | |
703 | ||
d2419ffc VS |
704 | static void hsw_psr_disable(struct intel_dp *intel_dp, |
705 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
706 | { |
707 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
708 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 709 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
710 | |
711 | if (dev_priv->psr.active) { | |
14c6547d | 712 | i915_reg_t psr_status; |
77affa31 CW |
713 | u32 psr_status_mask; |
714 | ||
95f28d2e | 715 | if (dev_priv->psr.psr2_enabled) { |
861023e0 | 716 | psr_status = EDP_PSR2_STATUS; |
77affa31 CW |
717 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
718 | ||
14c6547d DP |
719 | I915_WRITE(EDP_PSR2_CTL, |
720 | I915_READ(EDP_PSR2_CTL) & | |
77affa31 CW |
721 | ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); |
722 | ||
3fcb0ca1 | 723 | } else { |
861023e0 | 724 | psr_status = EDP_PSR_STATUS; |
77affa31 CW |
725 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
726 | ||
14c6547d DP |
727 | I915_WRITE(EDP_PSR_CTL, |
728 | I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); | |
3fcb0ca1 | 729 | } |
77affa31 CW |
730 | |
731 | /* Wait till PSR is idle */ | |
732 | if (intel_wait_for_register(dev_priv, | |
14c6547d | 733 | psr_status, psr_status_mask, 0, |
77affa31 CW |
734 | 2000)) |
735 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
736 | ||
0bc12bcb RV |
737 | dev_priv->psr.active = false; |
738 | } else { | |
95f28d2e | 739 | if (dev_priv->psr.psr2_enabled) |
3fcb0ca1 NV |
740 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
741 | else | |
742 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb | 743 | } |
b891d5e4 DP |
744 | |
745 | psr_aux_io_power_put(intel_dp); | |
e2bbc343 RV |
746 | } |
747 | ||
748 | /** | |
749 | * intel_psr_disable - Disable PSR | |
750 | * @intel_dp: Intel DP | |
d2419ffc | 751 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
752 | * |
753 | * This function needs to be called before disabling pipe. | |
754 | */ | |
d2419ffc VS |
755 | void intel_psr_disable(struct intel_dp *intel_dp, |
756 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
757 | { |
758 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
759 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 760 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 | 761 | |
4d90f2d5 | 762 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
763 | return; |
764 | ||
c9ef291a DP |
765 | if (WARN_ON(!CAN_PSR(dev_priv))) |
766 | return; | |
767 | ||
e2bbc343 RV |
768 | mutex_lock(&dev_priv->psr.lock); |
769 | if (!dev_priv->psr.enabled) { | |
770 | mutex_unlock(&dev_priv->psr.lock); | |
771 | return; | |
772 | } | |
773 | ||
424644c2 | 774 | dev_priv->psr.disable_source(intel_dp, old_crtc_state); |
0bc12bcb | 775 | |
b6e4d534 RV |
776 | /* Disable PSR on Sink */ |
777 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
778 | ||
0bc12bcb RV |
779 | dev_priv->psr.enabled = NULL; |
780 | mutex_unlock(&dev_priv->psr.lock); | |
781 | ||
782 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
783 | } | |
784 | ||
daeb725e | 785 | static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) |
0bc12bcb | 786 | { |
daeb725e CW |
787 | struct intel_dp *intel_dp; |
788 | i915_reg_t reg; | |
789 | u32 mask; | |
790 | int err; | |
791 | ||
792 | intel_dp = dev_priv->psr.enabled; | |
793 | if (!intel_dp) | |
794 | return false; | |
0bc12bcb | 795 | |
ce3508fd DP |
796 | if (dev_priv->psr.psr2_enabled) { |
797 | reg = EDP_PSR2_STATUS; | |
798 | mask = EDP_PSR2_STATUS_STATE_MASK; | |
995d3047 | 799 | } else { |
ce3508fd DP |
800 | reg = EDP_PSR_STATUS; |
801 | mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 802 | } |
daeb725e CW |
803 | |
804 | mutex_unlock(&dev_priv->psr.lock); | |
805 | ||
806 | err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); | |
807 | if (err) | |
808 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
809 | ||
810 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 811 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
812 | return err == 0 && dev_priv->psr.enabled; |
813 | } | |
0bc12bcb | 814 | |
daeb725e CW |
815 | static void intel_psr_work(struct work_struct *work) |
816 | { | |
817 | struct drm_i915_private *dev_priv = | |
818 | container_of(work, typeof(*dev_priv), psr.work.work); | |
819 | ||
820 | mutex_lock(&dev_priv->psr.lock); | |
821 | ||
822 | /* | |
823 | * We have to make sure PSR is ready for re-enable | |
824 | * otherwise it keeps disabled until next full enable/disable cycle. | |
825 | * PSR might take some time to get fully disabled | |
826 | * and be ready for re-enable. | |
827 | */ | |
828 | if (!psr_wait_for_idle(dev_priv)) | |
0bc12bcb RV |
829 | goto unlock; |
830 | ||
831 | /* | |
832 | * The delayed work can race with an invalidate hence we need to | |
833 | * recheck. Since psr_flush first clears this and then reschedules we | |
834 | * won't ever miss a flush when bailing out here. | |
835 | */ | |
836 | if (dev_priv->psr.busy_frontbuffer_bits) | |
837 | goto unlock; | |
838 | ||
daeb725e | 839 | intel_psr_activate(dev_priv->psr.enabled); |
0bc12bcb RV |
840 | unlock: |
841 | mutex_unlock(&dev_priv->psr.lock); | |
842 | } | |
843 | ||
5748b6a1 | 844 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
0bc12bcb | 845 | { |
995d3047 | 846 | u32 val; |
0bc12bcb | 847 | |
995d3047 RV |
848 | if (!dev_priv->psr.active) |
849 | return; | |
850 | ||
ce3508fd DP |
851 | if (dev_priv->psr.psr2_enabled) { |
852 | val = I915_READ(EDP_PSR2_CTL); | |
853 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
854 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
995d3047 | 855 | } else { |
ce3508fd DP |
856 | val = I915_READ(EDP_PSR_CTL); |
857 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
858 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
0bc12bcb | 859 | } |
995d3047 | 860 | dev_priv->psr.active = false; |
0bc12bcb RV |
861 | } |
862 | ||
b2b89f55 RV |
863 | /** |
864 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 865 | * @dev_priv: i915 device |
b2b89f55 | 866 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 867 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
868 | * |
869 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
870 | * with the software frontbuffer tracking. This function gets called every | |
871 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
872 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
873 | * | |
874 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
875 | */ | |
5748b6a1 | 876 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 877 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 878 | { |
0bc12bcb RV |
879 | struct drm_crtc *crtc; |
880 | enum pipe pipe; | |
881 | ||
4371d896 | 882 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
883 | return; |
884 | ||
ce3508fd | 885 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
886 | return; |
887 | ||
0bc12bcb RV |
888 | mutex_lock(&dev_priv->psr.lock); |
889 | if (!dev_priv->psr.enabled) { | |
890 | mutex_unlock(&dev_priv->psr.lock); | |
891 | return; | |
892 | } | |
893 | ||
894 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
895 | pipe = to_intel_crtc(crtc)->pipe; | |
896 | ||
0bc12bcb | 897 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 898 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
899 | |
900 | if (frontbuffer_bits) | |
5748b6a1 | 901 | intel_psr_exit(dev_priv); |
ec76d629 | 902 | |
0bc12bcb RV |
903 | mutex_unlock(&dev_priv->psr.lock); |
904 | } | |
905 | ||
b2b89f55 RV |
906 | /** |
907 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 908 | * @dev_priv: i915 device |
b2b89f55 | 909 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 910 | * @origin: which operation caused the flush |
b2b89f55 RV |
911 | * |
912 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
913 | * with the software frontbuffer tracking. This function gets called every | |
914 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
915 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
916 | * | |
917 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
918 | */ | |
5748b6a1 | 919 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 920 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 921 | { |
0bc12bcb RV |
922 | struct drm_crtc *crtc; |
923 | enum pipe pipe; | |
924 | ||
4371d896 | 925 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
926 | return; |
927 | ||
ce3508fd | 928 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
929 | return; |
930 | ||
0bc12bcb RV |
931 | mutex_lock(&dev_priv->psr.lock); |
932 | if (!dev_priv->psr.enabled) { | |
933 | mutex_unlock(&dev_priv->psr.lock); | |
934 | return; | |
935 | } | |
936 | ||
937 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
938 | pipe = to_intel_crtc(crtc)->pipe; | |
ec76d629 DV |
939 | |
940 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
941 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
942 | ||
921ec285 | 943 | /* By definition flush = invalidate + flush */ |
caa1fd66 | 944 | if (frontbuffer_bits) { |
ce3508fd | 945 | if (dev_priv->psr.psr2_enabled) { |
caa1fd66 RV |
946 | intel_psr_exit(dev_priv); |
947 | } else { | |
948 | /* | |
949 | * Display WA #0884: all | |
950 | * This documented WA for bxt can be safely applied | |
951 | * broadly so we can force HW tracking to exit PSR | |
952 | * instead of disabling and re-enabling. | |
a8ada068 | 953 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, |
caa1fd66 RV |
954 | * but it makes more sense write to the current active |
955 | * pipe. | |
956 | */ | |
a8ada068 | 957 | I915_WRITE(CURSURFLIVE(pipe), 0); |
caa1fd66 RV |
958 | } |
959 | } | |
995d3047 | 960 | |
0bc12bcb | 961 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
d0ac896a RV |
962 | if (!work_busy(&dev_priv->psr.work.work)) |
963 | schedule_delayed_work(&dev_priv->psr.work, | |
20bb97fe | 964 | msecs_to_jiffies(100)); |
0bc12bcb RV |
965 | mutex_unlock(&dev_priv->psr.lock); |
966 | } | |
967 | ||
b2b89f55 RV |
968 | /** |
969 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 970 | * @dev_priv: i915 device private |
b2b89f55 RV |
971 | * |
972 | * This function is called only once at driver load to initialize basic | |
973 | * PSR stuff. | |
974 | */ | |
c39055b0 | 975 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 976 | { |
0f328da6 RV |
977 | if (!HAS_PSR(dev_priv)) |
978 | return; | |
979 | ||
443a389f VS |
980 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
981 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
982 | ||
c9ef291a DP |
983 | if (!dev_priv->psr.sink_support) |
984 | return; | |
985 | ||
2bdd045e DP |
986 | if (i915_modparams.enable_psr == -1) { |
987 | i915_modparams.enable_psr = dev_priv->vbt.psr.enable; | |
988 | ||
989 | /* Per platform default: all disabled. */ | |
4f044a88 | 990 | i915_modparams.enable_psr = 0; |
2bdd045e | 991 | } |
d94d6e87 | 992 | |
65f61b42 | 993 | /* Set link_standby x link_off defaults */ |
8652744b | 994 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
995 | /* HSW and BDW require workarounds that we don't implement. */ |
996 | dev_priv->psr.link_standby = false; | |
60e5ffe3 RV |
997 | else |
998 | /* For new platforms let's respect VBT back again */ | |
999 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
1000 | ||
65f61b42 | 1001 | /* Override link_standby x link_off defaults */ |
4f044a88 | 1002 | if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) { |
65f61b42 RV |
1003 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); |
1004 | dev_priv->psr.link_standby = true; | |
1005 | } | |
4f044a88 | 1006 | if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) { |
65f61b42 RV |
1007 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); |
1008 | dev_priv->psr.link_standby = false; | |
1009 | } | |
1010 | ||
0bc12bcb RV |
1011 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); |
1012 | mutex_init(&dev_priv->psr.lock); | |
424644c2 | 1013 | |
ce3508fd DP |
1014 | dev_priv->psr.enable_source = hsw_psr_enable_source; |
1015 | dev_priv->psr.disable_source = hsw_psr_disable; | |
1016 | dev_priv->psr.enable_sink = hsw_psr_enable_sink; | |
1017 | dev_priv->psr.activate = hsw_psr_activate; | |
1018 | dev_priv->psr.setup_vsc = hsw_psr_setup_vsc; | |
1019 | ||
0bc12bcb | 1020 | } |