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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
c44301fc ML |
59 | static bool psr_global_enabled(u32 debug) |
60 | { | |
61 | switch (debug & I915_PSR_DEBUG_MODE_MASK) { | |
62 | case I915_PSR_DEBUG_DEFAULT: | |
63 | return i915_modparams.enable_psr; | |
64 | case I915_PSR_DEBUG_DISABLE: | |
65 | return false; | |
66 | default: | |
67 | return true; | |
68 | } | |
69 | } | |
70 | ||
2ac45bdd ML |
71 | static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, |
72 | const struct intel_crtc_state *crtc_state) | |
73 | { | |
598c6cfe DP |
74 | /* Disable PSR2 by default for all platforms */ |
75 | if (i915_modparams.enable_psr == -1) | |
76 | return false; | |
77 | ||
2ac45bdd ML |
78 | switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { |
79 | case I915_PSR_DEBUG_FORCE_PSR1: | |
80 | return false; | |
81 | default: | |
82 | return crtc_state->has_psr2; | |
83 | } | |
84 | } | |
85 | ||
1aeb1b5f | 86 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) |
54fd3149 DP |
87 | { |
88 | u32 debug_mask, mask; | |
89 | ||
54fd3149 DP |
90 | mask = EDP_PSR_ERROR(TRANSCODER_EDP); |
91 | debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) | | |
92 | EDP_PSR_PRE_ENTRY(TRANSCODER_EDP); | |
93 | ||
94 | if (INTEL_GEN(dev_priv) >= 8) { | |
95 | mask |= EDP_PSR_ERROR(TRANSCODER_A) | | |
96 | EDP_PSR_ERROR(TRANSCODER_B) | | |
97 | EDP_PSR_ERROR(TRANSCODER_C); | |
98 | ||
99 | debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) | | |
100 | EDP_PSR_PRE_ENTRY(TRANSCODER_A) | | |
101 | EDP_PSR_POST_EXIT(TRANSCODER_B) | | |
102 | EDP_PSR_PRE_ENTRY(TRANSCODER_B) | | |
103 | EDP_PSR_POST_EXIT(TRANSCODER_C) | | |
104 | EDP_PSR_PRE_ENTRY(TRANSCODER_C); | |
105 | } | |
106 | ||
1aeb1b5f | 107 | if (debug & I915_PSR_DEBUG_IRQ) |
54fd3149 DP |
108 | mask |= debug_mask; |
109 | ||
54fd3149 DP |
110 | I915_WRITE(EDP_PSR_IMR, ~mask); |
111 | } | |
112 | ||
bc18b4df JRS |
113 | static void psr_event_print(u32 val, bool psr2_enabled) |
114 | { | |
115 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
116 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
117 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
118 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
119 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
120 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
121 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
122 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
123 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
124 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
125 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
126 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
127 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
128 | if (val & PSR_EVENT_MEMORY_UP) | |
129 | DRM_DEBUG_KMS("\tMemory up\n"); | |
130 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
131 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
132 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
133 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
134 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
135 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
136 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
137 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
138 | if (val & PSR_EVENT_HDCP_ENABLE) | |
139 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
140 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
141 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
142 | if (val & PSR_EVENT_VBI_ENABLE) | |
143 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
144 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
145 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
146 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
147 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
148 | } | |
149 | ||
54fd3149 DP |
150 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
151 | { | |
152 | u32 transcoders = BIT(TRANSCODER_EDP); | |
153 | enum transcoder cpu_transcoder; | |
3f983e54 | 154 | ktime_t time_ns = ktime_get(); |
54fd3149 DP |
155 | |
156 | if (INTEL_GEN(dev_priv) >= 8) | |
157 | transcoders |= BIT(TRANSCODER_A) | | |
158 | BIT(TRANSCODER_B) | | |
159 | BIT(TRANSCODER_C); | |
160 | ||
161 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
162 | /* FIXME: Exit PSR and link train manually when this happens. */ | |
163 | if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) | |
164 | DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n", | |
165 | transcoder_name(cpu_transcoder)); | |
166 | ||
3f983e54 DP |
167 | if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) { |
168 | dev_priv->psr.last_entry_attempt = time_ns; | |
54fd3149 DP |
169 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", |
170 | transcoder_name(cpu_transcoder)); | |
3f983e54 | 171 | } |
54fd3149 | 172 | |
3f983e54 DP |
173 | if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) { |
174 | dev_priv->psr.last_exit = time_ns; | |
54fd3149 DP |
175 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", |
176 | transcoder_name(cpu_transcoder)); | |
bc18b4df JRS |
177 | |
178 | if (INTEL_GEN(dev_priv) >= 9) { | |
179 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
180 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
181 | ||
182 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); | |
183 | psr_event_print(val, psr2_enabled); | |
184 | } | |
3f983e54 | 185 | } |
54fd3149 DP |
186 | } |
187 | } | |
188 | ||
77fe36ff DP |
189 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
190 | { | |
191 | uint8_t dprx = 0; | |
192 | ||
193 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
194 | &dprx) != 1) | |
195 | return false; | |
196 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
197 | } | |
198 | ||
199 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) | |
200 | { | |
201 | uint8_t alpm_caps = 0; | |
202 | ||
203 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
204 | &alpm_caps) != 1) | |
205 | return false; | |
206 | return alpm_caps & DP_ALPM_CAP; | |
207 | } | |
208 | ||
26e5378d JRS |
209 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
210 | { | |
264ff016 | 211 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
212 | |
213 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
214 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
215 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
216 | else | |
264ff016 | 217 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
218 | return val; |
219 | } | |
220 | ||
77fe36ff DP |
221 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
222 | { | |
223 | struct drm_i915_private *dev_priv = | |
224 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
225 | ||
226 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, | |
227 | sizeof(intel_dp->psr_dpcd)); | |
228 | ||
8cf6da7e DP |
229 | if (!intel_dp->psr_dpcd[0]) |
230 | return; | |
8cf6da7e DP |
231 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
232 | intel_dp->psr_dpcd[0]); | |
84bb2916 DP |
233 | |
234 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { | |
235 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
236 | return; | |
237 | } | |
8cf6da7e | 238 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
239 | dev_priv->psr.sink_sync_latency = |
240 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff | 241 | |
c44301fc ML |
242 | WARN_ON(dev_priv->psr.dp); |
243 | dev_priv->psr.dp = intel_dp; | |
244 | ||
77fe36ff | 245 | if (INTEL_GEN(dev_priv) >= 9 && |
aee3bac0 | 246 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
247 | bool y_req = intel_dp->psr_dpcd[1] & |
248 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
249 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
250 | ||
aee3bac0 JRS |
251 | /* |
252 | * All panels that supports PSR version 03h (PSR2 + | |
253 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
254 | * only sure that it is going to be used when required by the | |
255 | * panel. This way panel is capable to do selective update | |
256 | * without a aux frame sync. | |
257 | * | |
258 | * To support PSR version 02h and PSR version 03h without | |
259 | * Y-coordinate requirement panels we would need to enable | |
260 | * GTC first. | |
261 | */ | |
97c9de66 | 262 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
263 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
264 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 265 | |
95f28d2e | 266 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
267 | dev_priv->psr.colorimetry_support = |
268 | intel_dp_get_colorimetry_status(intel_dp); | |
77fe36ff DP |
269 | } |
270 | } | |
271 | } | |
272 | ||
cf5d862d RV |
273 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
274 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 275 | { |
97da2ef4 | 276 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1895759e | 277 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d2419ffc | 278 | struct edp_vsc_psr psr_vsc; |
474d1ec4 | 279 | |
95f28d2e | 280 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
281 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
282 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
283 | psr_vsc.sdp_header.HB0 = 0; | |
284 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 285 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
286 | psr_vsc.sdp_header.HB2 = 0x5; |
287 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 288 | } else { |
2ce4df87 RV |
289 | psr_vsc.sdp_header.HB2 = 0x4; |
290 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 291 | } |
97da2ef4 | 292 | } else { |
2ce4df87 RV |
293 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
294 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
295 | psr_vsc.sdp_header.HB0 = 0; | |
296 | psr_vsc.sdp_header.HB1 = 0x7; | |
297 | psr_vsc.sdp_header.HB2 = 0x2; | |
298 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
299 | } |
300 | ||
790ea70c VS |
301 | intel_dig_port->write_infoframe(&intel_dig_port->base, |
302 | crtc_state, | |
1d776538 | 303 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); |
474d1ec4 SJ |
304 | } |
305 | ||
b90eed08 | 306 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb | 307 | { |
1895759e | 308 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
d544e918 DP |
309 | u32 aux_clock_divider, aux_ctl; |
310 | int i; | |
0bc12bcb RV |
311 | static const uint8_t aux_msg[] = { |
312 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
313 | [1] = DP_SET_POWER >> 8, | |
314 | [2] = DP_SET_POWER & 0xff, | |
315 | [3] = 1 - 1, | |
316 | [4] = DP_SET_POWER_D0, | |
317 | }; | |
d544e918 DP |
318 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
319 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
320 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
321 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
322 | |
323 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 324 | for (i = 0; i < sizeof(aux_msg); i += 4) |
d544e918 | 325 | I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), |
b90eed08 DP |
326 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
327 | ||
d544e918 DP |
328 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
329 | ||
330 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 331 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 332 | aux_clock_divider); |
d544e918 DP |
333 | |
334 | /* Select only valid bits for SRD_AUX_CTL */ | |
335 | aux_ctl &= psr_aux_mask; | |
336 | I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); | |
b90eed08 DP |
337 | } |
338 | ||
cf5d862d | 339 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 | 340 | { |
1895759e | 341 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4df4925b | 342 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 343 | |
340c93c0 | 344 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
345 | if (dev_priv->psr.psr2_enabled) { |
346 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
347 | DP_ALPM_ENABLE); | |
4df4925b | 348 | dpcd_val |= DP_PSR_ENABLE_PSR2; |
97c9de66 DP |
349 | } |
350 | ||
6f32ea7e | 351 | if (dev_priv->psr.link_standby) |
4df4925b | 352 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; |
00c8f194 JRS |
353 | if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) |
354 | dpcd_val |= DP_PSR_CRC_VERIFICATION; | |
4df4925b | 355 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); |
6f32ea7e | 356 | |
d544e918 | 357 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
358 | } |
359 | ||
ed63d24b | 360 | static void hsw_activate_psr1(struct intel_dp *intel_dp) |
0bc12bcb | 361 | { |
1895759e | 362 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
363 | u32 max_sleep_time = 0x1f; |
364 | u32 val = EDP_PSR_ENABLE; | |
474d1ec4 | 365 | |
a3db1428 DP |
366 | /* Let's use 6 as the minimum to cover all known cases including the |
367 | * off-by-one issue that HW has in some cases. | |
d44b4dcb | 368 | */ |
a3db1428 | 369 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
50db1390 | 370 | |
a3db1428 DP |
371 | /* sink_sync_latency of 8 means source has to wait for more than 8 |
372 | * frames, we'll go with 9 frames for now | |
373 | */ | |
374 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
50db1390 | 375 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; |
7370c68d | 376 | |
a3db1428 | 377 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; |
772c2a51 | 378 | if (IS_HASWELL(dev_priv)) |
7370c68d | 379 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0bc12bcb | 380 | |
60e5ffe3 RV |
381 | if (dev_priv->psr.link_standby) |
382 | val |= EDP_PSR_LINK_STANDBY; | |
383 | ||
77312ae8 VN |
384 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
385 | val |= EDP_PSR_TP1_TIME_0us; | |
386 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) | |
50db1390 | 387 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
388 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
389 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 390 | else |
77312ae8 | 391 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 392 | |
77312ae8 VN |
393 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
394 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
395 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
50db1390 | 396 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
397 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
398 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 399 | else |
77312ae8 | 400 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
401 | |
402 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
403 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
404 | val |= EDP_PSR_TP1_TP3_SEL; | |
405 | else | |
406 | val |= EDP_PSR_TP1_TP2_SEL; | |
407 | ||
00c8f194 JRS |
408 | if (INTEL_GEN(dev_priv) >= 8) |
409 | val |= EDP_PSR_CRC_ENABLE; | |
410 | ||
912d6412 | 411 | val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; |
50db1390 | 412 | I915_WRITE(EDP_PSR_CTL, val); |
3fcb0ca1 | 413 | } |
50db1390 | 414 | |
ed63d24b | 415 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 | 416 | { |
1895759e | 417 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
a3db1428 DP |
418 | u32 val; |
419 | ||
420 | /* Let's use 6 as the minimum to cover all known cases including the | |
421 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 422 | */ |
a3db1428 DP |
423 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
424 | ||
425 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
426 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 DV |
427 | |
428 | /* FIXME: selective update is probably totally broken because it doesn't | |
429 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
430 | * good enough. */ | |
5e87325f | 431 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
432 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
433 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 434 | |
26e5378d | 435 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 436 | |
77312ae8 VN |
437 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && |
438 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) | |
439 | val |= EDP_PSR2_TP2_TIME_50us; | |
440 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
441 | val |= EDP_PSR2_TP2_TIME_100us; | |
442 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) | |
443 | val |= EDP_PSR2_TP2_TIME_500us; | |
50db1390 | 444 | else |
77312ae8 | 445 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 446 | |
50db1390 | 447 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
448 | } |
449 | ||
c4932d79 RV |
450 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
451 | struct intel_crtc_state *crtc_state) | |
452 | { | |
1895759e | 453 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
c90c275c DP |
454 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
455 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
456 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 RV |
457 | |
458 | /* | |
459 | * FIXME psr2_support is messed up. It's both computed | |
460 | * dynamically during PSR enable, and extracted from sink | |
461 | * caps during eDP detection. | |
462 | */ | |
95f28d2e | 463 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
464 | return false; |
465 | ||
c90c275c DP |
466 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
467 | psr_max_h = 4096; | |
468 | psr_max_v = 2304; | |
469 | } else if (IS_GEN9(dev_priv)) { | |
470 | psr_max_h = 3640; | |
471 | psr_max_v = 2304; | |
472 | } | |
473 | ||
474 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
475 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
476 | crtc_hdisplay, crtc_vdisplay, | |
477 | psr_max_h, psr_max_v); | |
c4932d79 RV |
478 | return false; |
479 | } | |
480 | ||
c4932d79 RV |
481 | return true; |
482 | } | |
483 | ||
4d90f2d5 VS |
484 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
485 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
486 | { |
487 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1895759e | 488 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
dfd2e9ab | 489 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 490 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 491 | int psr_setup_time; |
0bc12bcb | 492 | |
4371d896 | 493 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
494 | return; |
495 | ||
c44301fc | 496 | if (intel_dp != dev_priv->psr.dp) |
4d90f2d5 | 497 | return; |
0bc12bcb | 498 | |
dc9b5a0c RV |
499 | /* |
500 | * HSW spec explicitly says PSR is tied to port A. | |
501 | * BDW+ platforms with DDI implementation of PSR have different | |
502 | * PSR registers per transcoder and we only implement transcoder EDP | |
503 | * ones. Since by Display design transcoder EDP is tied to port A | |
504 | * we can safely escape based on the port A. | |
505 | */ | |
ce3508fd | 506 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 507 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 508 | return; |
0bc12bcb RV |
509 | } |
510 | ||
772c2a51 | 511 | if (IS_HASWELL(dev_priv) && |
4d90f2d5 | 512 | I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & |
c8e68b7e | 513 | S3D_ENABLE) { |
0bc12bcb | 514 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
4d90f2d5 | 515 | return; |
0bc12bcb RV |
516 | } |
517 | ||
772c2a51 | 518 | if (IS_HASWELL(dev_priv) && |
dfd2e9ab | 519 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb | 520 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
4d90f2d5 | 521 | return; |
0bc12bcb RV |
522 | } |
523 | ||
dfd2e9ab VS |
524 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
525 | if (psr_setup_time < 0) { | |
526 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
527 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 528 | return; |
dfd2e9ab VS |
529 | } |
530 | ||
531 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
532 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
533 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
534 | psr_setup_time); | |
4d90f2d5 VS |
535 | return; |
536 | } | |
537 | ||
4d90f2d5 | 538 | crtc_state->has_psr = true; |
c4932d79 | 539 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
0bc12bcb RV |
540 | } |
541 | ||
e2bbc343 | 542 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb | 543 | { |
1895759e | 544 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 545 | |
bcc233b2 | 546 | if (INTEL_GEN(dev_priv) >= 9) |
3fcb0ca1 | 547 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
bcc233b2 | 548 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); |
0bc12bcb RV |
549 | WARN_ON(dev_priv->psr.active); |
550 | lockdep_assert_held(&dev_priv->psr.lock); | |
551 | ||
cf5d862d RV |
552 | /* psr1 and psr2 are mutually exclusive.*/ |
553 | if (dev_priv->psr.psr2_enabled) | |
554 | hsw_activate_psr2(intel_dp); | |
555 | else | |
556 | hsw_activate_psr1(intel_dp); | |
557 | ||
0bc12bcb RV |
558 | dev_priv->psr.active = true; |
559 | } | |
560 | ||
cf5d862d RV |
561 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
562 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f | 563 | { |
1895759e | 564 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
4d1fa22f | 565 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
fc6ff9dc | 566 | u32 mask; |
4d1fa22f | 567 | |
d544e918 DP |
568 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
569 | * use hardcoded values PSR AUX transactions | |
570 | */ | |
571 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
572 | hsw_psr_setup_aux(intel_dp); | |
573 | ||
95f28d2e | 574 | if (dev_priv->psr.psr2_enabled) { |
5e87325f JRS |
575 | u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); |
576 | ||
9e783375 | 577 | if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) |
5e87325f JRS |
578 | chicken |= (PSR2_VSC_ENABLE_PROG_HEADER |
579 | | PSR2_ADD_VERTICAL_LINE_COUNT); | |
580 | ||
581 | else | |
582 | chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL; | |
4d1fa22f | 583 | I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); |
4d1fa22f | 584 | } |
bf80928f JRS |
585 | |
586 | /* | |
587 | * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also | |
588 | * mask LPSP to avoid dependency on other drivers that might block | |
589 | * runtime_pm besides preventing other hw tracking issues now we | |
590 | * can rely on frontbuffer tracking. | |
591 | */ | |
fc6ff9dc JRS |
592 | mask = EDP_PSR_DEBUG_MASK_MEMUP | |
593 | EDP_PSR_DEBUG_MASK_HPD | | |
594 | EDP_PSR_DEBUG_MASK_LPSP | | |
595 | EDP_PSR_DEBUG_MASK_MAX_SLEEP; | |
596 | ||
597 | if (INTEL_GEN(dev_priv) < 11) | |
598 | mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; | |
599 | ||
600 | I915_WRITE(EDP_PSR_DEBUG, mask); | |
4d1fa22f RV |
601 | } |
602 | ||
c44301fc ML |
603 | static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, |
604 | const struct intel_crtc_state *crtc_state) | |
605 | { | |
606 | struct intel_dp *intel_dp = dev_priv->psr.dp; | |
607 | ||
608 | if (dev_priv->psr.enabled) | |
609 | return; | |
610 | ||
611 | DRM_DEBUG_KMS("Enabling PSR%s\n", | |
612 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
613 | intel_psr_setup_vsc(intel_dp, crtc_state); | |
614 | intel_psr_enable_sink(intel_dp); | |
615 | intel_psr_enable_source(intel_dp, crtc_state); | |
616 | dev_priv->psr.enabled = true; | |
617 | ||
618 | intel_psr_activate(intel_dp); | |
619 | } | |
620 | ||
b2b89f55 RV |
621 | /** |
622 | * intel_psr_enable - Enable PSR | |
623 | * @intel_dp: Intel DP | |
d2419ffc | 624 | * @crtc_state: new CRTC state |
b2b89f55 RV |
625 | * |
626 | * This function can only be called after the pipe is fully trained and enabled. | |
627 | */ | |
d2419ffc VS |
628 | void intel_psr_enable(struct intel_dp *intel_dp, |
629 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb | 630 | { |
1895759e | 631 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
0bc12bcb | 632 | |
4d90f2d5 | 633 | if (!crtc_state->has_psr) |
0bc12bcb | 634 | return; |
0bc12bcb | 635 | |
c9ef291a DP |
636 | if (WARN_ON(!CAN_PSR(dev_priv))) |
637 | return; | |
638 | ||
da83ef85 | 639 | WARN_ON(dev_priv->drrs.dp); |
c44301fc | 640 | |
0bc12bcb | 641 | mutex_lock(&dev_priv->psr.lock); |
c44301fc | 642 | if (dev_priv->psr.prepared) { |
0bc12bcb RV |
643 | DRM_DEBUG_KMS("PSR already in use\n"); |
644 | goto unlock; | |
645 | } | |
646 | ||
2ac45bdd | 647 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); |
0bc12bcb | 648 | dev_priv->psr.busy_frontbuffer_bits = 0; |
c44301fc | 649 | dev_priv->psr.prepared = true; |
0bc12bcb | 650 | |
c44301fc ML |
651 | if (psr_global_enabled(dev_priv->psr.debug)) |
652 | intel_psr_enable_locked(dev_priv, crtc_state); | |
653 | else | |
654 | DRM_DEBUG_KMS("PSR disabled by flag\n"); | |
d0ac896a | 655 | |
0bc12bcb RV |
656 | unlock: |
657 | mutex_unlock(&dev_priv->psr.lock); | |
658 | } | |
659 | ||
26f9ec9a JRS |
660 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
661 | { | |
662 | u32 val; | |
663 | ||
b2fc2252 JRS |
664 | if (!dev_priv->psr.active) { |
665 | if (INTEL_GEN(dev_priv) >= 9) | |
666 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); | |
667 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
26f9ec9a | 668 | return; |
b2fc2252 | 669 | } |
26f9ec9a JRS |
670 | |
671 | if (dev_priv->psr.psr2_enabled) { | |
672 | val = I915_READ(EDP_PSR2_CTL); | |
673 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
674 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
675 | } else { | |
676 | val = I915_READ(EDP_PSR_CTL); | |
677 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
678 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
679 | } | |
680 | dev_priv->psr.active = false; | |
681 | } | |
682 | ||
2ee936e3 | 683 | static void intel_psr_disable_locked(struct intel_dp *intel_dp) |
e2bbc343 | 684 | { |
1895759e | 685 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
b2fc2252 JRS |
686 | i915_reg_t psr_status; |
687 | u32 psr_status_mask; | |
0bc12bcb | 688 | |
2ee936e3 JRS |
689 | lockdep_assert_held(&dev_priv->psr.lock); |
690 | ||
691 | if (!dev_priv->psr.enabled) | |
692 | return; | |
693 | ||
694 | DRM_DEBUG_KMS("Disabling PSR%s\n", | |
695 | dev_priv->psr.psr2_enabled ? "2" : "1"); | |
696 | ||
b2fc2252 | 697 | intel_psr_exit(dev_priv); |
77affa31 | 698 | |
b2fc2252 JRS |
699 | if (dev_priv->psr.psr2_enabled) { |
700 | psr_status = EDP_PSR2_STATUS; | |
701 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; | |
0bc12bcb | 702 | } else { |
b2fc2252 JRS |
703 | psr_status = EDP_PSR_STATUS; |
704 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 705 | } |
b2fc2252 JRS |
706 | |
707 | /* Wait till PSR is idle */ | |
708 | if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0, | |
709 | 2000)) | |
710 | DRM_ERROR("Timed out waiting PSR idle state\n"); | |
cc3054ff JRS |
711 | |
712 | /* Disable PSR on Sink */ | |
713 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
714 | ||
c44301fc | 715 | dev_priv->psr.enabled = false; |
cc3054ff JRS |
716 | } |
717 | ||
e2bbc343 RV |
718 | /** |
719 | * intel_psr_disable - Disable PSR | |
720 | * @intel_dp: Intel DP | |
d2419ffc | 721 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
722 | * |
723 | * This function needs to be called before disabling pipe. | |
724 | */ | |
d2419ffc VS |
725 | void intel_psr_disable(struct intel_dp *intel_dp, |
726 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 | 727 | { |
1895759e | 728 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
e2bbc343 | 729 | |
4d90f2d5 | 730 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
731 | return; |
732 | ||
c9ef291a DP |
733 | if (WARN_ON(!CAN_PSR(dev_priv))) |
734 | return; | |
735 | ||
e2bbc343 | 736 | mutex_lock(&dev_priv->psr.lock); |
c44301fc ML |
737 | if (!dev_priv->psr.prepared) { |
738 | mutex_unlock(&dev_priv->psr.lock); | |
739 | return; | |
740 | } | |
741 | ||
cc3054ff | 742 | intel_psr_disable_locked(intel_dp); |
c44301fc ML |
743 | |
744 | dev_priv->psr.prepared = false; | |
0bc12bcb | 745 | mutex_unlock(&dev_priv->psr.lock); |
98fa2aec | 746 | cancel_work_sync(&dev_priv->psr.work); |
0bc12bcb RV |
747 | } |
748 | ||
65df9c79 DP |
749 | /** |
750 | * intel_psr_wait_for_idle - wait for PSR1 to idle | |
751 | * @new_crtc_state: new CRTC state | |
752 | * @out_value: PSR status in case of failure | |
753 | * | |
754 | * This function is expected to be called from pipe_update_start() where it is | |
755 | * not expected to race with PSR enable or disable. | |
756 | * | |
757 | * Returns: 0 on success or -ETIMEOUT if PSR status does not idle. | |
758 | */ | |
63ec132d DP |
759 | int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, |
760 | u32 *out_value) | |
c43dbcbb | 761 | { |
c3d43361 TV |
762 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc); |
763 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
c43dbcbb | 764 | |
c44301fc | 765 | if (!dev_priv->psr.enabled || !new_crtc_state->has_psr) |
c3d43361 TV |
766 | return 0; |
767 | ||
fd255f6e DP |
768 | /* FIXME: Update this for PSR2 if we need to wait for idle */ |
769 | if (READ_ONCE(dev_priv->psr.psr2_enabled)) | |
770 | return 0; | |
c43dbcbb TV |
771 | |
772 | /* | |
65df9c79 DP |
773 | * From bspec: Panel Self Refresh (BDW+) |
774 | * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of | |
775 | * exit training time + 1.5 ms of aux channel handshake. 50 ms is | |
776 | * defensive enough to cover everything. | |
c43dbcbb | 777 | */ |
63ec132d | 778 | |
fd255f6e DP |
779 | return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS, |
780 | EDP_PSR_STATUS_STATE_MASK, | |
63ec132d DP |
781 | EDP_PSR_STATUS_STATE_IDLE, 2, 50, |
782 | out_value); | |
c43dbcbb TV |
783 | } |
784 | ||
785 | static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) | |
0bc12bcb | 786 | { |
daeb725e CW |
787 | i915_reg_t reg; |
788 | u32 mask; | |
789 | int err; | |
790 | ||
c44301fc | 791 | if (!dev_priv->psr.enabled) |
daeb725e | 792 | return false; |
0bc12bcb | 793 | |
ce3508fd DP |
794 | if (dev_priv->psr.psr2_enabled) { |
795 | reg = EDP_PSR2_STATUS; | |
796 | mask = EDP_PSR2_STATUS_STATE_MASK; | |
995d3047 | 797 | } else { |
ce3508fd DP |
798 | reg = EDP_PSR_STATUS; |
799 | mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 800 | } |
daeb725e CW |
801 | |
802 | mutex_unlock(&dev_priv->psr.lock); | |
803 | ||
804 | err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); | |
805 | if (err) | |
806 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
807 | ||
808 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 809 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
810 | return err == 0 && dev_priv->psr.enabled; |
811 | } | |
0bc12bcb | 812 | |
2ac45bdd ML |
813 | static bool switching_psr(struct drm_i915_private *dev_priv, |
814 | struct intel_crtc_state *crtc_state, | |
815 | u32 mode) | |
816 | { | |
817 | /* Can't switch psr state anyway if PSR2 is not supported. */ | |
818 | if (!crtc_state || !crtc_state->has_psr2) | |
819 | return false; | |
820 | ||
821 | if (dev_priv->psr.psr2_enabled && mode == I915_PSR_DEBUG_FORCE_PSR1) | |
822 | return true; | |
823 | ||
824 | if (!dev_priv->psr.psr2_enabled && mode != I915_PSR_DEBUG_FORCE_PSR1) | |
825 | return true; | |
826 | ||
827 | return false; | |
828 | } | |
829 | ||
c44301fc ML |
830 | int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv, |
831 | struct drm_modeset_acquire_ctx *ctx, | |
832 | u64 val) | |
833 | { | |
834 | struct drm_device *dev = &dev_priv->drm; | |
835 | struct drm_connector_state *conn_state; | |
2ac45bdd | 836 | struct intel_crtc_state *crtc_state = NULL; |
9d3f8d2f | 837 | struct drm_crtc_commit *commit; |
c44301fc ML |
838 | struct drm_crtc *crtc; |
839 | struct intel_dp *dp; | |
840 | int ret; | |
841 | bool enable; | |
2ac45bdd | 842 | u32 mode = val & I915_PSR_DEBUG_MODE_MASK; |
c44301fc ML |
843 | |
844 | if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || | |
2ac45bdd | 845 | mode > I915_PSR_DEBUG_FORCE_PSR1) { |
c44301fc ML |
846 | DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); |
847 | return -EINVAL; | |
848 | } | |
849 | ||
850 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, ctx); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
854 | /* dev_priv->psr.dp should be set once and then never touched again. */ | |
855 | dp = READ_ONCE(dev_priv->psr.dp); | |
856 | conn_state = dp->attached_connector->base.state; | |
857 | crtc = conn_state->crtc; | |
858 | if (crtc) { | |
859 | ret = drm_modeset_lock(&crtc->mutex, ctx); | |
860 | if (ret) | |
861 | return ret; | |
862 | ||
2ac45bdd | 863 | crtc_state = to_intel_crtc_state(crtc->state); |
9d3f8d2f CW |
864 | commit = crtc_state->base.commit; |
865 | } else { | |
866 | commit = conn_state->commit; | |
867 | } | |
868 | if (commit) { | |
869 | ret = wait_for_completion_interruptible(&commit->hw_done); | |
870 | if (ret) | |
871 | return ret; | |
872 | } | |
c44301fc ML |
873 | |
874 | ret = mutex_lock_interruptible(&dev_priv->psr.lock); | |
875 | if (ret) | |
876 | return ret; | |
877 | ||
878 | enable = psr_global_enabled(val); | |
879 | ||
2ac45bdd | 880 | if (!enable || switching_psr(dev_priv, crtc_state, mode)) |
c44301fc ML |
881 | intel_psr_disable_locked(dev_priv->psr.dp); |
882 | ||
883 | dev_priv->psr.debug = val; | |
2ac45bdd ML |
884 | if (crtc) |
885 | dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); | |
886 | ||
1aeb1b5f | 887 | intel_psr_irq_control(dev_priv, dev_priv->psr.debug); |
c44301fc ML |
888 | |
889 | if (dev_priv->psr.prepared && enable) | |
2ac45bdd | 890 | intel_psr_enable_locked(dev_priv, crtc_state); |
c44301fc ML |
891 | |
892 | mutex_unlock(&dev_priv->psr.lock); | |
893 | return ret; | |
894 | } | |
895 | ||
daeb725e CW |
896 | static void intel_psr_work(struct work_struct *work) |
897 | { | |
898 | struct drm_i915_private *dev_priv = | |
5422b37c | 899 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
900 | |
901 | mutex_lock(&dev_priv->psr.lock); | |
902 | ||
5422b37c RV |
903 | if (!dev_priv->psr.enabled) |
904 | goto unlock; | |
905 | ||
daeb725e CW |
906 | /* |
907 | * We have to make sure PSR is ready for re-enable | |
908 | * otherwise it keeps disabled until next full enable/disable cycle. | |
909 | * PSR might take some time to get fully disabled | |
910 | * and be ready for re-enable. | |
911 | */ | |
c43dbcbb | 912 | if (!__psr_wait_for_idle_locked(dev_priv)) |
0bc12bcb RV |
913 | goto unlock; |
914 | ||
915 | /* | |
916 | * The delayed work can race with an invalidate hence we need to | |
917 | * recheck. Since psr_flush first clears this and then reschedules we | |
918 | * won't ever miss a flush when bailing out here. | |
919 | */ | |
c12e0643 | 920 | if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active) |
0bc12bcb RV |
921 | goto unlock; |
922 | ||
c44301fc | 923 | intel_psr_activate(dev_priv->psr.dp); |
0bc12bcb RV |
924 | unlock: |
925 | mutex_unlock(&dev_priv->psr.lock); | |
926 | } | |
927 | ||
b2b89f55 RV |
928 | /** |
929 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 930 | * @dev_priv: i915 device |
b2b89f55 | 931 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 932 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
933 | * |
934 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
935 | * with the software frontbuffer tracking. This function gets called every | |
936 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
937 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
938 | * | |
939 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
940 | */ | |
5748b6a1 | 941 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 942 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 943 | { |
0bc12bcb RV |
944 | struct drm_crtc *crtc; |
945 | enum pipe pipe; | |
946 | ||
4371d896 | 947 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
948 | return; |
949 | ||
ce3508fd | 950 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
951 | return; |
952 | ||
0bc12bcb RV |
953 | mutex_lock(&dev_priv->psr.lock); |
954 | if (!dev_priv->psr.enabled) { | |
955 | mutex_unlock(&dev_priv->psr.lock); | |
956 | return; | |
957 | } | |
958 | ||
c44301fc | 959 | crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc; |
0bc12bcb RV |
960 | pipe = to_intel_crtc(crtc)->pipe; |
961 | ||
0bc12bcb | 962 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 963 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
964 | |
965 | if (frontbuffer_bits) | |
5748b6a1 | 966 | intel_psr_exit(dev_priv); |
ec76d629 | 967 | |
0bc12bcb RV |
968 | mutex_unlock(&dev_priv->psr.lock); |
969 | } | |
970 | ||
b2b89f55 RV |
971 | /** |
972 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 973 | * @dev_priv: i915 device |
b2b89f55 | 974 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 975 | * @origin: which operation caused the flush |
b2b89f55 RV |
976 | * |
977 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
978 | * with the software frontbuffer tracking. This function gets called every | |
979 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
980 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
981 | * | |
982 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
983 | */ | |
5748b6a1 | 984 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 985 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 986 | { |
0bc12bcb RV |
987 | struct drm_crtc *crtc; |
988 | enum pipe pipe; | |
989 | ||
4371d896 | 990 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
991 | return; |
992 | ||
ce3508fd | 993 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
994 | return; |
995 | ||
0bc12bcb RV |
996 | mutex_lock(&dev_priv->psr.lock); |
997 | if (!dev_priv->psr.enabled) { | |
998 | mutex_unlock(&dev_priv->psr.lock); | |
999 | return; | |
1000 | } | |
1001 | ||
c44301fc | 1002 | crtc = dp_to_dig_port(dev_priv->psr.dp)->base.base.crtc; |
0bc12bcb | 1003 | pipe = to_intel_crtc(crtc)->pipe; |
ec76d629 DV |
1004 | |
1005 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
1006 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
1007 | ||
921ec285 | 1008 | /* By definition flush = invalidate + flush */ |
caa1fd66 | 1009 | if (frontbuffer_bits) { |
66231d14 JRS |
1010 | /* |
1011 | * Display WA #0884: all | |
1012 | * This documented WA for bxt can be safely applied | |
1013 | * broadly so we can force HW tracking to exit PSR | |
1014 | * instead of disabling and re-enabling. | |
1015 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, | |
1016 | * but it makes more sense write to the current active | |
1017 | * pipe. | |
1018 | */ | |
1019 | I915_WRITE(CURSURFLIVE(pipe), 0); | |
caa1fd66 | 1020 | } |
995d3047 | 1021 | |
0bc12bcb | 1022 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 1023 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
1024 | mutex_unlock(&dev_priv->psr.lock); |
1025 | } | |
1026 | ||
b2b89f55 RV |
1027 | /** |
1028 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 1029 | * @dev_priv: i915 device private |
b2b89f55 RV |
1030 | * |
1031 | * This function is called only once at driver load to initialize basic | |
1032 | * PSR stuff. | |
1033 | */ | |
c39055b0 | 1034 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 1035 | { |
0f328da6 RV |
1036 | if (!HAS_PSR(dev_priv)) |
1037 | return; | |
1038 | ||
443a389f VS |
1039 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
1040 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
1041 | ||
c9ef291a DP |
1042 | if (!dev_priv->psr.sink_support) |
1043 | return; | |
1044 | ||
598c6cfe DP |
1045 | if (i915_modparams.enable_psr == -1) |
1046 | if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) | |
1047 | i915_modparams.enable_psr = 0; | |
d94d6e87 | 1048 | |
65f61b42 | 1049 | /* Set link_standby x link_off defaults */ |
8652744b | 1050 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
1051 | /* HSW and BDW require workarounds that we don't implement. */ |
1052 | dev_priv->psr.link_standby = false; | |
60e5ffe3 RV |
1053 | else |
1054 | /* For new platforms let's respect VBT back again */ | |
1055 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
1056 | ||
5422b37c | 1057 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
0bc12bcb RV |
1058 | mutex_init(&dev_priv->psr.lock); |
1059 | } | |
cc3054ff JRS |
1060 | |
1061 | void intel_psr_short_pulse(struct intel_dp *intel_dp) | |
1062 | { | |
1895759e | 1063 | struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); |
cc3054ff JRS |
1064 | struct i915_psr *psr = &dev_priv->psr; |
1065 | u8 val; | |
93bf76ed | 1066 | const u8 errors = DP_PSR_RFB_STORAGE_ERROR | |
00c8f194 JRS |
1067 | DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | |
1068 | DP_PSR_LINK_CRC_ERROR; | |
cc3054ff JRS |
1069 | |
1070 | if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp)) | |
1071 | return; | |
1072 | ||
1073 | mutex_lock(&psr->lock); | |
1074 | ||
c44301fc | 1075 | if (!psr->enabled || psr->dp != intel_dp) |
cc3054ff JRS |
1076 | goto exit; |
1077 | ||
1078 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) != 1) { | |
1079 | DRM_ERROR("PSR_STATUS dpcd read failed\n"); | |
1080 | goto exit; | |
1081 | } | |
1082 | ||
1083 | if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) { | |
1084 | DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); | |
1085 | intel_psr_disable_locked(intel_dp); | |
1086 | } | |
1087 | ||
93bf76ed JRS |
1088 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) { |
1089 | DRM_ERROR("PSR_ERROR_STATUS dpcd read failed\n"); | |
1090 | goto exit; | |
1091 | } | |
1092 | ||
1093 | if (val & DP_PSR_RFB_STORAGE_ERROR) | |
1094 | DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); | |
1095 | if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) | |
1096 | DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); | |
00c8f194 JRS |
1097 | if (val & DP_PSR_LINK_CRC_ERROR) |
1098 | DRM_ERROR("PSR Link CRC error, disabling PSR\n"); | |
93bf76ed JRS |
1099 | |
1100 | if (val & ~errors) | |
1101 | DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", | |
1102 | val & ~errors); | |
1103 | if (val & errors) | |
1104 | intel_psr_disable_locked(intel_dp); | |
1105 | /* clear status register */ | |
1106 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); | |
cc3054ff JRS |
1107 | exit: |
1108 | mutex_unlock(&psr->lock); | |
1109 | } |