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0bc12bcb RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
b2b89f55 RV |
24 | /** |
25 | * DOC: Panel Self Refresh (PSR/SRD) | |
26 | * | |
27 | * Since Haswell Display controller supports Panel Self-Refresh on display | |
28 | * panels witch have a remote frame buffer (RFB) implemented according to PSR | |
29 | * spec in eDP1.3. PSR feature allows the display to go to lower standby states | |
30 | * when system is idle but display is on as it eliminates display refresh | |
31 | * request to DDR memory completely as long as the frame buffer for that | |
32 | * display is unchanged. | |
33 | * | |
34 | * Panel Self Refresh must be supported by both Hardware (source) and | |
35 | * Panel (sink). | |
36 | * | |
37 | * PSR saves power by caching the framebuffer in the panel RFB, which allows us | |
38 | * to power down the link and memory controller. For DSI panels the same idea | |
39 | * is called "manual mode". | |
40 | * | |
41 | * The implementation uses the hardware-based PSR support which automatically | |
42 | * enters/exits self-refresh mode. The hardware takes care of sending the | |
43 | * required DP aux message and could even retrain the link (that part isn't | |
44 | * enabled yet though). The hardware also keeps track of any frontbuffer | |
45 | * changes to know when to exit self-refresh mode again. Unfortunately that | |
46 | * part doesn't work too well, hence why the i915 PSR support uses the | |
47 | * software frontbuffer tracking to make sure it doesn't miss a screen | |
48 | * update. For this integration intel_psr_invalidate() and intel_psr_flush() | |
49 | * get called by the frontbuffer tracking code. Note that because of locking | |
50 | * issues the self-refresh re-enable code is done from a work queue, which | |
51 | * must be correctly synchronized/cancelled when shutting down the pipe." | |
52 | */ | |
53 | ||
0bc12bcb RV |
54 | #include <drm/drmP.h> |
55 | ||
56 | #include "intel_drv.h" | |
57 | #include "i915_drv.h" | |
58 | ||
54fd3149 DP |
59 | void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug) |
60 | { | |
61 | u32 debug_mask, mask; | |
62 | ||
54fd3149 DP |
63 | mask = EDP_PSR_ERROR(TRANSCODER_EDP); |
64 | debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) | | |
65 | EDP_PSR_PRE_ENTRY(TRANSCODER_EDP); | |
66 | ||
67 | if (INTEL_GEN(dev_priv) >= 8) { | |
68 | mask |= EDP_PSR_ERROR(TRANSCODER_A) | | |
69 | EDP_PSR_ERROR(TRANSCODER_B) | | |
70 | EDP_PSR_ERROR(TRANSCODER_C); | |
71 | ||
72 | debug_mask |= EDP_PSR_POST_EXIT(TRANSCODER_A) | | |
73 | EDP_PSR_PRE_ENTRY(TRANSCODER_A) | | |
74 | EDP_PSR_POST_EXIT(TRANSCODER_B) | | |
75 | EDP_PSR_PRE_ENTRY(TRANSCODER_B) | | |
76 | EDP_PSR_POST_EXIT(TRANSCODER_C) | | |
77 | EDP_PSR_PRE_ENTRY(TRANSCODER_C); | |
78 | } | |
79 | ||
80 | if (debug) | |
81 | mask |= debug_mask; | |
82 | ||
83 | WRITE_ONCE(dev_priv->psr.debug, debug); | |
84 | I915_WRITE(EDP_PSR_IMR, ~mask); | |
85 | } | |
86 | ||
bc18b4df JRS |
87 | static void psr_event_print(u32 val, bool psr2_enabled) |
88 | { | |
89 | DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val); | |
90 | if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) | |
91 | DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n"); | |
92 | if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) | |
93 | DRM_DEBUG_KMS("\tPSR2 disabled\n"); | |
94 | if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) | |
95 | DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n"); | |
96 | if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) | |
97 | DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n"); | |
98 | if (val & PSR_EVENT_GRAPHICS_RESET) | |
99 | DRM_DEBUG_KMS("\tGraphics reset\n"); | |
100 | if (val & PSR_EVENT_PCH_INTERRUPT) | |
101 | DRM_DEBUG_KMS("\tPCH interrupt\n"); | |
102 | if (val & PSR_EVENT_MEMORY_UP) | |
103 | DRM_DEBUG_KMS("\tMemory up\n"); | |
104 | if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) | |
105 | DRM_DEBUG_KMS("\tFront buffer modification\n"); | |
106 | if (val & PSR_EVENT_WD_TIMER_EXPIRE) | |
107 | DRM_DEBUG_KMS("\tPSR watchdog timer expired\n"); | |
108 | if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) | |
109 | DRM_DEBUG_KMS("\tPIPE registers updated\n"); | |
110 | if (val & PSR_EVENT_REGISTER_UPDATE) | |
111 | DRM_DEBUG_KMS("\tRegister updated\n"); | |
112 | if (val & PSR_EVENT_HDCP_ENABLE) | |
113 | DRM_DEBUG_KMS("\tHDCP enabled\n"); | |
114 | if (val & PSR_EVENT_KVMR_SESSION_ENABLE) | |
115 | DRM_DEBUG_KMS("\tKVMR session enabled\n"); | |
116 | if (val & PSR_EVENT_VBI_ENABLE) | |
117 | DRM_DEBUG_KMS("\tVBI enabled\n"); | |
118 | if (val & PSR_EVENT_LPSP_MODE_EXIT) | |
119 | DRM_DEBUG_KMS("\tLPSP mode exited\n"); | |
120 | if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) | |
121 | DRM_DEBUG_KMS("\tPSR disabled\n"); | |
122 | } | |
123 | ||
54fd3149 DP |
124 | void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) |
125 | { | |
126 | u32 transcoders = BIT(TRANSCODER_EDP); | |
127 | enum transcoder cpu_transcoder; | |
3f983e54 | 128 | ktime_t time_ns = ktime_get(); |
54fd3149 DP |
129 | |
130 | if (INTEL_GEN(dev_priv) >= 8) | |
131 | transcoders |= BIT(TRANSCODER_A) | | |
132 | BIT(TRANSCODER_B) | | |
133 | BIT(TRANSCODER_C); | |
134 | ||
135 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { | |
136 | /* FIXME: Exit PSR and link train manually when this happens. */ | |
137 | if (psr_iir & EDP_PSR_ERROR(cpu_transcoder)) | |
138 | DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n", | |
139 | transcoder_name(cpu_transcoder)); | |
140 | ||
3f983e54 DP |
141 | if (psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) { |
142 | dev_priv->psr.last_entry_attempt = time_ns; | |
54fd3149 DP |
143 | DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", |
144 | transcoder_name(cpu_transcoder)); | |
3f983e54 | 145 | } |
54fd3149 | 146 | |
3f983e54 DP |
147 | if (psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) { |
148 | dev_priv->psr.last_exit = time_ns; | |
54fd3149 DP |
149 | DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", |
150 | transcoder_name(cpu_transcoder)); | |
bc18b4df JRS |
151 | |
152 | if (INTEL_GEN(dev_priv) >= 9) { | |
153 | u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); | |
154 | bool psr2_enabled = dev_priv->psr.psr2_enabled; | |
155 | ||
156 | I915_WRITE(PSR_EVENT(cpu_transcoder), val); | |
157 | psr_event_print(val, psr2_enabled); | |
158 | } | |
3f983e54 | 159 | } |
54fd3149 DP |
160 | } |
161 | } | |
162 | ||
77fe36ff DP |
163 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
164 | { | |
165 | uint8_t dprx = 0; | |
166 | ||
167 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, | |
168 | &dprx) != 1) | |
169 | return false; | |
170 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
171 | } | |
172 | ||
173 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) | |
174 | { | |
175 | uint8_t alpm_caps = 0; | |
176 | ||
177 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, | |
178 | &alpm_caps) != 1) | |
179 | return false; | |
180 | return alpm_caps & DP_ALPM_CAP; | |
181 | } | |
182 | ||
26e5378d JRS |
183 | static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) |
184 | { | |
264ff016 | 185 | u8 val = 8; /* assume the worst if we can't read the value */ |
26e5378d JRS |
186 | |
187 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
188 | DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) | |
189 | val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; | |
190 | else | |
264ff016 | 191 | DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n"); |
26e5378d JRS |
192 | return val; |
193 | } | |
194 | ||
77fe36ff DP |
195 | void intel_psr_init_dpcd(struct intel_dp *intel_dp) |
196 | { | |
197 | struct drm_i915_private *dev_priv = | |
198 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
199 | ||
200 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, | |
201 | sizeof(intel_dp->psr_dpcd)); | |
202 | ||
8cf6da7e DP |
203 | if (!intel_dp->psr_dpcd[0]) |
204 | return; | |
8cf6da7e DP |
205 | DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", |
206 | intel_dp->psr_dpcd[0]); | |
84bb2916 DP |
207 | |
208 | if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { | |
209 | DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); | |
210 | return; | |
211 | } | |
8cf6da7e | 212 | dev_priv->psr.sink_support = true; |
a3db1428 DP |
213 | dev_priv->psr.sink_sync_latency = |
214 | intel_dp_get_sink_sync_latency(intel_dp); | |
77fe36ff DP |
215 | |
216 | if (INTEL_GEN(dev_priv) >= 9 && | |
aee3bac0 | 217 | (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { |
97c9de66 DP |
218 | bool y_req = intel_dp->psr_dpcd[1] & |
219 | DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
220 | bool alpm = intel_dp_get_alpm_status(intel_dp); | |
221 | ||
aee3bac0 JRS |
222 | /* |
223 | * All panels that supports PSR version 03h (PSR2 + | |
224 | * Y-coordinate) can handle Y-coordinates in VSC but we are | |
225 | * only sure that it is going to be used when required by the | |
226 | * panel. This way panel is capable to do selective update | |
227 | * without a aux frame sync. | |
228 | * | |
229 | * To support PSR version 02h and PSR version 03h without | |
230 | * Y-coordinate requirement panels we would need to enable | |
231 | * GTC first. | |
232 | */ | |
97c9de66 | 233 | dev_priv->psr.sink_psr2_support = y_req && alpm; |
8cf6da7e DP |
234 | DRM_DEBUG_KMS("PSR2 %ssupported\n", |
235 | dev_priv->psr.sink_psr2_support ? "" : "not "); | |
77fe36ff | 236 | |
95f28d2e | 237 | if (dev_priv->psr.sink_psr2_support) { |
77fe36ff DP |
238 | dev_priv->psr.colorimetry_support = |
239 | intel_dp_get_colorimetry_status(intel_dp); | |
77fe36ff DP |
240 | } |
241 | } | |
242 | } | |
243 | ||
cf5d862d RV |
244 | static void intel_psr_setup_vsc(struct intel_dp *intel_dp, |
245 | const struct intel_crtc_state *crtc_state) | |
474d1ec4 | 246 | { |
97da2ef4 | 247 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
d2419ffc VS |
248 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
249 | struct edp_vsc_psr psr_vsc; | |
474d1ec4 | 250 | |
95f28d2e | 251 | if (dev_priv->psr.psr2_enabled) { |
2ce4df87 RV |
252 | /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ |
253 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
254 | psr_vsc.sdp_header.HB0 = 0; | |
255 | psr_vsc.sdp_header.HB1 = 0x7; | |
aee3bac0 | 256 | if (dev_priv->psr.colorimetry_support) { |
2ce4df87 RV |
257 | psr_vsc.sdp_header.HB2 = 0x5; |
258 | psr_vsc.sdp_header.HB3 = 0x13; | |
aee3bac0 | 259 | } else { |
2ce4df87 RV |
260 | psr_vsc.sdp_header.HB2 = 0x4; |
261 | psr_vsc.sdp_header.HB3 = 0xe; | |
2ce4df87 | 262 | } |
97da2ef4 | 263 | } else { |
2ce4df87 RV |
264 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
265 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
266 | psr_vsc.sdp_header.HB0 = 0; | |
267 | psr_vsc.sdp_header.HB1 = 0x7; | |
268 | psr_vsc.sdp_header.HB2 = 0x2; | |
269 | psr_vsc.sdp_header.HB3 = 0x8; | |
97da2ef4 NV |
270 | } |
271 | ||
1d776538 VS |
272 | intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state, |
273 | DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); | |
474d1ec4 SJ |
274 | } |
275 | ||
b90eed08 | 276 | static void hsw_psr_setup_aux(struct intel_dp *intel_dp) |
0bc12bcb RV |
277 | { |
278 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d544e918 DP |
279 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
280 | u32 aux_clock_divider, aux_ctl; | |
281 | int i; | |
0bc12bcb RV |
282 | static const uint8_t aux_msg[] = { |
283 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
284 | [1] = DP_SET_POWER >> 8, | |
285 | [2] = DP_SET_POWER & 0xff, | |
286 | [3] = 1 - 1, | |
287 | [4] = DP_SET_POWER_D0, | |
288 | }; | |
d544e918 DP |
289 | u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK | |
290 | EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | | |
291 | EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | | |
292 | EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; | |
0bc12bcb RV |
293 | |
294 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
b90eed08 | 295 | for (i = 0; i < sizeof(aux_msg); i += 4) |
d544e918 | 296 | I915_WRITE(EDP_PSR_AUX_DATA(i >> 2), |
b90eed08 DP |
297 | intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); |
298 | ||
d544e918 DP |
299 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
300 | ||
301 | /* Start with bits set for DDI_AUX_CTL register */ | |
8a29c778 | 302 | aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), |
b90eed08 | 303 | aux_clock_divider); |
d544e918 DP |
304 | |
305 | /* Select only valid bits for SRD_AUX_CTL */ | |
306 | aux_ctl &= psr_aux_mask; | |
307 | I915_WRITE(EDP_PSR_AUX_CTL, aux_ctl); | |
b90eed08 DP |
308 | } |
309 | ||
cf5d862d | 310 | static void intel_psr_enable_sink(struct intel_dp *intel_dp) |
b90eed08 DP |
311 | { |
312 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
313 | struct drm_device *dev = dig_port->base.base.dev; | |
314 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4df4925b | 315 | u8 dpcd_val = DP_PSR_ENABLE; |
b90eed08 | 316 | |
340c93c0 | 317 | /* Enable ALPM at sink for psr2 */ |
97c9de66 DP |
318 | if (dev_priv->psr.psr2_enabled) { |
319 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, | |
320 | DP_ALPM_ENABLE); | |
4df4925b | 321 | dpcd_val |= DP_PSR_ENABLE_PSR2; |
97c9de66 DP |
322 | } |
323 | ||
6f32ea7e | 324 | if (dev_priv->psr.link_standby) |
4df4925b JRS |
325 | dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; |
326 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); | |
6f32ea7e | 327 | |
d544e918 | 328 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); |
0bc12bcb RV |
329 | } |
330 | ||
ed63d24b | 331 | static void hsw_activate_psr1(struct intel_dp *intel_dp) |
0bc12bcb RV |
332 | { |
333 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
334 | struct drm_device *dev = dig_port->base.base.dev; | |
fac5e23e | 335 | struct drm_i915_private *dev_priv = to_i915(dev); |
a3db1428 DP |
336 | u32 max_sleep_time = 0x1f; |
337 | u32 val = EDP_PSR_ENABLE; | |
474d1ec4 | 338 | |
a3db1428 DP |
339 | /* Let's use 6 as the minimum to cover all known cases including the |
340 | * off-by-one issue that HW has in some cases. | |
d44b4dcb | 341 | */ |
a3db1428 | 342 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
50db1390 | 343 | |
a3db1428 DP |
344 | /* sink_sync_latency of 8 means source has to wait for more than 8 |
345 | * frames, we'll go with 9 frames for now | |
346 | */ | |
347 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
50db1390 | 348 | val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; |
7370c68d | 349 | |
a3db1428 | 350 | val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; |
772c2a51 | 351 | if (IS_HASWELL(dev_priv)) |
7370c68d | 352 | val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0bc12bcb | 353 | |
60e5ffe3 RV |
354 | if (dev_priv->psr.link_standby) |
355 | val |= EDP_PSR_LINK_STANDBY; | |
356 | ||
77312ae8 VN |
357 | if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) |
358 | val |= EDP_PSR_TP1_TIME_0us; | |
359 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100) | |
50db1390 | 360 | val |= EDP_PSR_TP1_TIME_100us; |
77312ae8 VN |
361 | else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500) |
362 | val |= EDP_PSR_TP1_TIME_500us; | |
50db1390 | 363 | else |
77312ae8 | 364 | val |= EDP_PSR_TP1_TIME_2500us; |
50db1390 | 365 | |
77312ae8 VN |
366 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0) |
367 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
368 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
50db1390 | 369 | val |= EDP_PSR_TP2_TP3_TIME_100us; |
77312ae8 VN |
370 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) |
371 | val |= EDP_PSR_TP2_TP3_TIME_500us; | |
50db1390 | 372 | else |
77312ae8 | 373 | val |= EDP_PSR_TP2_TP3_TIME_2500us; |
50db1390 DV |
374 | |
375 | if (intel_dp_source_supports_hbr2(intel_dp) && | |
376 | drm_dp_tps3_supported(intel_dp->dpcd)) | |
377 | val |= EDP_PSR_TP1_TP3_SEL; | |
378 | else | |
379 | val |= EDP_PSR_TP1_TP2_SEL; | |
380 | ||
912d6412 | 381 | val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; |
50db1390 | 382 | I915_WRITE(EDP_PSR_CTL, val); |
3fcb0ca1 | 383 | } |
50db1390 | 384 | |
ed63d24b | 385 | static void hsw_activate_psr2(struct intel_dp *intel_dp) |
3fcb0ca1 NV |
386 | { |
387 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
388 | struct drm_device *dev = dig_port->base.base.dev; | |
389 | struct drm_i915_private *dev_priv = to_i915(dev); | |
a3db1428 DP |
390 | u32 val; |
391 | ||
392 | /* Let's use 6 as the minimum to cover all known cases including the | |
393 | * off-by-one issue that HW has in some cases. | |
3fcb0ca1 | 394 | */ |
a3db1428 DP |
395 | int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); |
396 | ||
397 | idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); | |
398 | val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; | |
50db1390 DV |
399 | |
400 | /* FIXME: selective update is probably totally broken because it doesn't | |
401 | * mesh at all with our frontbuffer tracking. And the hw alone isn't | |
402 | * good enough. */ | |
5e87325f | 403 | val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; |
2a34b005 JRS |
404 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
405 | val |= EDP_Y_COORDINATE_ENABLE; | |
977da084 | 406 | |
26e5378d | 407 | val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); |
50db1390 | 408 | |
77312ae8 VN |
409 | if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && |
410 | dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) | |
411 | val |= EDP_PSR2_TP2_TIME_50us; | |
412 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100) | |
413 | val |= EDP_PSR2_TP2_TIME_100us; | |
414 | else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500) | |
415 | val |= EDP_PSR2_TP2_TIME_500us; | |
50db1390 | 416 | else |
77312ae8 | 417 | val |= EDP_PSR2_TP2_TIME_2500us; |
474d1ec4 | 418 | |
50db1390 | 419 | I915_WRITE(EDP_PSR2_CTL, val); |
0bc12bcb RV |
420 | } |
421 | ||
c4932d79 RV |
422 | static bool intel_psr2_config_valid(struct intel_dp *intel_dp, |
423 | struct intel_crtc_state *crtc_state) | |
424 | { | |
425 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
426 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
c90c275c DP |
427 | int crtc_hdisplay = crtc_state->base.adjusted_mode.crtc_hdisplay; |
428 | int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; | |
429 | int psr_max_h = 0, psr_max_v = 0; | |
c4932d79 RV |
430 | |
431 | /* | |
432 | * FIXME psr2_support is messed up. It's both computed | |
433 | * dynamically during PSR enable, and extracted from sink | |
434 | * caps during eDP detection. | |
435 | */ | |
95f28d2e | 436 | if (!dev_priv->psr.sink_psr2_support) |
c4932d79 RV |
437 | return false; |
438 | ||
c90c275c DP |
439 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
440 | psr_max_h = 4096; | |
441 | psr_max_v = 2304; | |
442 | } else if (IS_GEN9(dev_priv)) { | |
443 | psr_max_h = 3640; | |
444 | psr_max_v = 2304; | |
445 | } | |
446 | ||
447 | if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { | |
448 | DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", | |
449 | crtc_hdisplay, crtc_vdisplay, | |
450 | psr_max_h, psr_max_v); | |
c4932d79 RV |
451 | return false; |
452 | } | |
453 | ||
c4932d79 RV |
454 | return true; |
455 | } | |
456 | ||
4d90f2d5 VS |
457 | void intel_psr_compute_config(struct intel_dp *intel_dp, |
458 | struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
459 | { |
460 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
4d90f2d5 | 461 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
dfd2e9ab | 462 | const struct drm_display_mode *adjusted_mode = |
4d90f2d5 | 463 | &crtc_state->base.adjusted_mode; |
dfd2e9ab | 464 | int psr_setup_time; |
0bc12bcb | 465 | |
4371d896 | 466 | if (!CAN_PSR(dev_priv)) |
4d90f2d5 VS |
467 | return; |
468 | ||
469 | if (!i915_modparams.enable_psr) { | |
470 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
471 | return; | |
472 | } | |
0bc12bcb | 473 | |
dc9b5a0c RV |
474 | /* |
475 | * HSW spec explicitly says PSR is tied to port A. | |
476 | * BDW+ platforms with DDI implementation of PSR have different | |
477 | * PSR registers per transcoder and we only implement transcoder EDP | |
478 | * ones. Since by Display design transcoder EDP is tied to port A | |
479 | * we can safely escape based on the port A. | |
480 | */ | |
ce3508fd | 481 | if (dig_port->base.port != PORT_A) { |
dc9b5a0c | 482 | DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); |
4d90f2d5 | 483 | return; |
0bc12bcb RV |
484 | } |
485 | ||
772c2a51 | 486 | if (IS_HASWELL(dev_priv) && |
4d90f2d5 | 487 | I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & |
c8e68b7e | 488 | S3D_ENABLE) { |
0bc12bcb | 489 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
4d90f2d5 | 490 | return; |
0bc12bcb RV |
491 | } |
492 | ||
772c2a51 | 493 | if (IS_HASWELL(dev_priv) && |
dfd2e9ab | 494 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
0bc12bcb | 495 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
4d90f2d5 | 496 | return; |
0bc12bcb RV |
497 | } |
498 | ||
dfd2e9ab VS |
499 | psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); |
500 | if (psr_setup_time < 0) { | |
501 | DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", | |
502 | intel_dp->psr_dpcd[1]); | |
4d90f2d5 | 503 | return; |
dfd2e9ab VS |
504 | } |
505 | ||
506 | if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > | |
507 | adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { | |
508 | DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", | |
509 | psr_setup_time); | |
4d90f2d5 VS |
510 | return; |
511 | } | |
512 | ||
4d90f2d5 | 513 | crtc_state->has_psr = true; |
c4932d79 RV |
514 | crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); |
515 | DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); | |
0bc12bcb RV |
516 | } |
517 | ||
e2bbc343 | 518 | static void intel_psr_activate(struct intel_dp *intel_dp) |
0bc12bcb RV |
519 | { |
520 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
521 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 522 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 523 | |
95f28d2e | 524 | if (dev_priv->psr.psr2_enabled) |
3fcb0ca1 NV |
525 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
526 | else | |
527 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb RV |
528 | WARN_ON(dev_priv->psr.active); |
529 | lockdep_assert_held(&dev_priv->psr.lock); | |
530 | ||
cf5d862d RV |
531 | /* psr1 and psr2 are mutually exclusive.*/ |
532 | if (dev_priv->psr.psr2_enabled) | |
533 | hsw_activate_psr2(intel_dp); | |
534 | else | |
535 | hsw_activate_psr1(intel_dp); | |
536 | ||
0bc12bcb RV |
537 | dev_priv->psr.active = true; |
538 | } | |
539 | ||
cf5d862d RV |
540 | static void intel_psr_enable_source(struct intel_dp *intel_dp, |
541 | const struct intel_crtc_state *crtc_state) | |
4d1fa22f RV |
542 | { |
543 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
544 | struct drm_device *dev = dig_port->base.base.dev; | |
545 | struct drm_i915_private *dev_priv = to_i915(dev); | |
546 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
4d1fa22f | 547 | |
d544e918 DP |
548 | /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+ |
549 | * use hardcoded values PSR AUX transactions | |
550 | */ | |
551 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
552 | hsw_psr_setup_aux(intel_dp); | |
553 | ||
95f28d2e | 554 | if (dev_priv->psr.psr2_enabled) { |
5e87325f JRS |
555 | u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); |
556 | ||
557 | if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv)) | |
558 | chicken |= (PSR2_VSC_ENABLE_PROG_HEADER | |
559 | | PSR2_ADD_VERTICAL_LINE_COUNT); | |
560 | ||
561 | else | |
562 | chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL; | |
4d1fa22f RV |
563 | I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); |
564 | ||
861023e0 | 565 | I915_WRITE(EDP_PSR_DEBUG, |
4d1fa22f RV |
566 | EDP_PSR_DEBUG_MASK_MEMUP | |
567 | EDP_PSR_DEBUG_MASK_HPD | | |
568 | EDP_PSR_DEBUG_MASK_LPSP | | |
569 | EDP_PSR_DEBUG_MASK_MAX_SLEEP | | |
570 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
571 | } else { | |
572 | /* | |
573 | * Per Spec: Avoid continuous PSR exit by masking MEMUP | |
574 | * and HPD. also mask LPSP to avoid dependency on other | |
575 | * drivers that might block runtime_pm besides | |
576 | * preventing other hw tracking issues now we can rely | |
577 | * on frontbuffer tracking. | |
578 | */ | |
861023e0 | 579 | I915_WRITE(EDP_PSR_DEBUG, |
4d1fa22f RV |
580 | EDP_PSR_DEBUG_MASK_MEMUP | |
581 | EDP_PSR_DEBUG_MASK_HPD | | |
75cbec03 RS |
582 | EDP_PSR_DEBUG_MASK_LPSP | |
583 | EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); | |
4d1fa22f RV |
584 | } |
585 | } | |
586 | ||
b2b89f55 RV |
587 | /** |
588 | * intel_psr_enable - Enable PSR | |
589 | * @intel_dp: Intel DP | |
d2419ffc | 590 | * @crtc_state: new CRTC state |
b2b89f55 RV |
591 | * |
592 | * This function can only be called after the pipe is fully trained and enabled. | |
593 | */ | |
d2419ffc VS |
594 | void intel_psr_enable(struct intel_dp *intel_dp, |
595 | const struct intel_crtc_state *crtc_state) | |
0bc12bcb RV |
596 | { |
597 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
598 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 599 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb | 600 | |
4d90f2d5 | 601 | if (!crtc_state->has_psr) |
0bc12bcb | 602 | return; |
0bc12bcb | 603 | |
c9ef291a DP |
604 | if (WARN_ON(!CAN_PSR(dev_priv))) |
605 | return; | |
606 | ||
da83ef85 | 607 | WARN_ON(dev_priv->drrs.dp); |
0bc12bcb RV |
608 | mutex_lock(&dev_priv->psr.lock); |
609 | if (dev_priv->psr.enabled) { | |
610 | DRM_DEBUG_KMS("PSR already in use\n"); | |
611 | goto unlock; | |
612 | } | |
613 | ||
95f28d2e | 614 | dev_priv->psr.psr2_enabled = crtc_state->has_psr2; |
0bc12bcb RV |
615 | dev_priv->psr.busy_frontbuffer_bits = 0; |
616 | ||
cf5d862d RV |
617 | intel_psr_setup_vsc(intel_dp, crtc_state); |
618 | intel_psr_enable_sink(intel_dp); | |
619 | intel_psr_enable_source(intel_dp, crtc_state); | |
29d1efe0 RV |
620 | dev_priv->psr.enabled = intel_dp; |
621 | ||
5422b37c | 622 | intel_psr_activate(intel_dp); |
d0ac896a | 623 | |
0bc12bcb RV |
624 | unlock: |
625 | mutex_unlock(&dev_priv->psr.lock); | |
626 | } | |
627 | ||
cf5d862d RV |
628 | static void |
629 | intel_psr_disable_source(struct intel_dp *intel_dp, | |
630 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
631 | { |
632 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
633 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 634 | struct drm_i915_private *dev_priv = to_i915(dev); |
0bc12bcb RV |
635 | |
636 | if (dev_priv->psr.active) { | |
14c6547d | 637 | i915_reg_t psr_status; |
77affa31 CW |
638 | u32 psr_status_mask; |
639 | ||
95f28d2e | 640 | if (dev_priv->psr.psr2_enabled) { |
861023e0 | 641 | psr_status = EDP_PSR2_STATUS; |
77affa31 CW |
642 | psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; |
643 | ||
14c6547d DP |
644 | I915_WRITE(EDP_PSR2_CTL, |
645 | I915_READ(EDP_PSR2_CTL) & | |
77affa31 CW |
646 | ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); |
647 | ||
3fcb0ca1 | 648 | } else { |
861023e0 | 649 | psr_status = EDP_PSR_STATUS; |
77affa31 CW |
650 | psr_status_mask = EDP_PSR_STATUS_STATE_MASK; |
651 | ||
14c6547d DP |
652 | I915_WRITE(EDP_PSR_CTL, |
653 | I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); | |
3fcb0ca1 | 654 | } |
77affa31 CW |
655 | |
656 | /* Wait till PSR is idle */ | |
657 | if (intel_wait_for_register(dev_priv, | |
14c6547d | 658 | psr_status, psr_status_mask, 0, |
77affa31 CW |
659 | 2000)) |
660 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
661 | ||
0bc12bcb RV |
662 | dev_priv->psr.active = false; |
663 | } else { | |
95f28d2e | 664 | if (dev_priv->psr.psr2_enabled) |
3fcb0ca1 NV |
665 | WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); |
666 | else | |
667 | WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); | |
0bc12bcb | 668 | } |
e2bbc343 RV |
669 | } |
670 | ||
671 | /** | |
672 | * intel_psr_disable - Disable PSR | |
673 | * @intel_dp: Intel DP | |
d2419ffc | 674 | * @old_crtc_state: old CRTC state |
e2bbc343 RV |
675 | * |
676 | * This function needs to be called before disabling pipe. | |
677 | */ | |
d2419ffc VS |
678 | void intel_psr_disable(struct intel_dp *intel_dp, |
679 | const struct intel_crtc_state *old_crtc_state) | |
e2bbc343 RV |
680 | { |
681 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
682 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 683 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2bbc343 | 684 | |
4d90f2d5 | 685 | if (!old_crtc_state->has_psr) |
0f328da6 RV |
686 | return; |
687 | ||
c9ef291a DP |
688 | if (WARN_ON(!CAN_PSR(dev_priv))) |
689 | return; | |
690 | ||
e2bbc343 RV |
691 | mutex_lock(&dev_priv->psr.lock); |
692 | if (!dev_priv->psr.enabled) { | |
693 | mutex_unlock(&dev_priv->psr.lock); | |
694 | return; | |
695 | } | |
696 | ||
cf5d862d | 697 | intel_psr_disable_source(intel_dp, old_crtc_state); |
0bc12bcb | 698 | |
b6e4d534 RV |
699 | /* Disable PSR on Sink */ |
700 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); | |
701 | ||
0bc12bcb RV |
702 | dev_priv->psr.enabled = NULL; |
703 | mutex_unlock(&dev_priv->psr.lock); | |
98fa2aec | 704 | cancel_work_sync(&dev_priv->psr.work); |
0bc12bcb RV |
705 | } |
706 | ||
daeb725e | 707 | static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) |
0bc12bcb | 708 | { |
daeb725e CW |
709 | struct intel_dp *intel_dp; |
710 | i915_reg_t reg; | |
711 | u32 mask; | |
712 | int err; | |
713 | ||
714 | intel_dp = dev_priv->psr.enabled; | |
715 | if (!intel_dp) | |
716 | return false; | |
0bc12bcb | 717 | |
ce3508fd DP |
718 | if (dev_priv->psr.psr2_enabled) { |
719 | reg = EDP_PSR2_STATUS; | |
720 | mask = EDP_PSR2_STATUS_STATE_MASK; | |
995d3047 | 721 | } else { |
ce3508fd DP |
722 | reg = EDP_PSR_STATUS; |
723 | mask = EDP_PSR_STATUS_STATE_MASK; | |
0bc12bcb | 724 | } |
daeb725e CW |
725 | |
726 | mutex_unlock(&dev_priv->psr.lock); | |
727 | ||
728 | err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); | |
729 | if (err) | |
730 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
731 | ||
732 | /* After the unlocked wait, verify that PSR is still wanted! */ | |
0bc12bcb | 733 | mutex_lock(&dev_priv->psr.lock); |
daeb725e CW |
734 | return err == 0 && dev_priv->psr.enabled; |
735 | } | |
0bc12bcb | 736 | |
daeb725e CW |
737 | static void intel_psr_work(struct work_struct *work) |
738 | { | |
739 | struct drm_i915_private *dev_priv = | |
5422b37c | 740 | container_of(work, typeof(*dev_priv), psr.work); |
daeb725e CW |
741 | |
742 | mutex_lock(&dev_priv->psr.lock); | |
743 | ||
5422b37c RV |
744 | if (!dev_priv->psr.enabled) |
745 | goto unlock; | |
746 | ||
daeb725e CW |
747 | /* |
748 | * We have to make sure PSR is ready for re-enable | |
749 | * otherwise it keeps disabled until next full enable/disable cycle. | |
750 | * PSR might take some time to get fully disabled | |
751 | * and be ready for re-enable. | |
752 | */ | |
753 | if (!psr_wait_for_idle(dev_priv)) | |
0bc12bcb RV |
754 | goto unlock; |
755 | ||
756 | /* | |
757 | * The delayed work can race with an invalidate hence we need to | |
758 | * recheck. Since psr_flush first clears this and then reschedules we | |
759 | * won't ever miss a flush when bailing out here. | |
760 | */ | |
761 | if (dev_priv->psr.busy_frontbuffer_bits) | |
762 | goto unlock; | |
763 | ||
daeb725e | 764 | intel_psr_activate(dev_priv->psr.enabled); |
0bc12bcb RV |
765 | unlock: |
766 | mutex_unlock(&dev_priv->psr.lock); | |
767 | } | |
768 | ||
5748b6a1 | 769 | static void intel_psr_exit(struct drm_i915_private *dev_priv) |
0bc12bcb | 770 | { |
995d3047 | 771 | u32 val; |
0bc12bcb | 772 | |
995d3047 RV |
773 | if (!dev_priv->psr.active) |
774 | return; | |
775 | ||
ce3508fd DP |
776 | if (dev_priv->psr.psr2_enabled) { |
777 | val = I915_READ(EDP_PSR2_CTL); | |
778 | WARN_ON(!(val & EDP_PSR2_ENABLE)); | |
779 | I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); | |
995d3047 | 780 | } else { |
ce3508fd DP |
781 | val = I915_READ(EDP_PSR_CTL); |
782 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
783 | I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); | |
0bc12bcb | 784 | } |
995d3047 | 785 | dev_priv->psr.active = false; |
0bc12bcb RV |
786 | } |
787 | ||
b2b89f55 RV |
788 | /** |
789 | * intel_psr_invalidate - Invalidade PSR | |
5748b6a1 | 790 | * @dev_priv: i915 device |
b2b89f55 | 791 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5baf63cc | 792 | * @origin: which operation caused the invalidate |
b2b89f55 RV |
793 | * |
794 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
795 | * with the software frontbuffer tracking. This function gets called every | |
796 | * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be | |
797 | * disabled if the frontbuffer mask contains a buffer relevant to PSR. | |
798 | * | |
799 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." | |
800 | */ | |
5748b6a1 | 801 | void intel_psr_invalidate(struct drm_i915_private *dev_priv, |
5baf63cc | 802 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 803 | { |
0bc12bcb RV |
804 | struct drm_crtc *crtc; |
805 | enum pipe pipe; | |
806 | ||
4371d896 | 807 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
808 | return; |
809 | ||
ce3508fd | 810 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
811 | return; |
812 | ||
0bc12bcb RV |
813 | mutex_lock(&dev_priv->psr.lock); |
814 | if (!dev_priv->psr.enabled) { | |
815 | mutex_unlock(&dev_priv->psr.lock); | |
816 | return; | |
817 | } | |
818 | ||
819 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
820 | pipe = to_intel_crtc(crtc)->pipe; | |
821 | ||
0bc12bcb | 822 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
0bc12bcb | 823 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; |
ec76d629 DV |
824 | |
825 | if (frontbuffer_bits) | |
5748b6a1 | 826 | intel_psr_exit(dev_priv); |
ec76d629 | 827 | |
0bc12bcb RV |
828 | mutex_unlock(&dev_priv->psr.lock); |
829 | } | |
830 | ||
b2b89f55 RV |
831 | /** |
832 | * intel_psr_flush - Flush PSR | |
5748b6a1 | 833 | * @dev_priv: i915 device |
b2b89f55 | 834 | * @frontbuffer_bits: frontbuffer plane tracking bits |
169de131 | 835 | * @origin: which operation caused the flush |
b2b89f55 RV |
836 | * |
837 | * Since the hardware frontbuffer tracking has gaps we need to integrate | |
838 | * with the software frontbuffer tracking. This function gets called every | |
839 | * time frontbuffer rendering has completed and flushed out to memory. PSR | |
840 | * can be enabled again if no other frontbuffer relevant to PSR is dirty. | |
841 | * | |
842 | * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. | |
843 | */ | |
5748b6a1 | 844 | void intel_psr_flush(struct drm_i915_private *dev_priv, |
169de131 | 845 | unsigned frontbuffer_bits, enum fb_op_origin origin) |
0bc12bcb | 846 | { |
0bc12bcb RV |
847 | struct drm_crtc *crtc; |
848 | enum pipe pipe; | |
849 | ||
4371d896 | 850 | if (!CAN_PSR(dev_priv)) |
0f328da6 RV |
851 | return; |
852 | ||
ce3508fd | 853 | if (origin == ORIGIN_FLIP) |
5baf63cc RV |
854 | return; |
855 | ||
0bc12bcb RV |
856 | mutex_lock(&dev_priv->psr.lock); |
857 | if (!dev_priv->psr.enabled) { | |
858 | mutex_unlock(&dev_priv->psr.lock); | |
859 | return; | |
860 | } | |
861 | ||
862 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
863 | pipe = to_intel_crtc(crtc)->pipe; | |
ec76d629 DV |
864 | |
865 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
0bc12bcb RV |
866 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; |
867 | ||
921ec285 | 868 | /* By definition flush = invalidate + flush */ |
caa1fd66 | 869 | if (frontbuffer_bits) { |
ce3508fd | 870 | if (dev_priv->psr.psr2_enabled) { |
caa1fd66 RV |
871 | intel_psr_exit(dev_priv); |
872 | } else { | |
873 | /* | |
874 | * Display WA #0884: all | |
875 | * This documented WA for bxt can be safely applied | |
876 | * broadly so we can force HW tracking to exit PSR | |
877 | * instead of disabling and re-enabling. | |
a8ada068 | 878 | * Workaround tells us to write 0 to CUR_SURFLIVE_A, |
caa1fd66 RV |
879 | * but it makes more sense write to the current active |
880 | * pipe. | |
881 | */ | |
a8ada068 | 882 | I915_WRITE(CURSURFLIVE(pipe), 0); |
caa1fd66 RV |
883 | } |
884 | } | |
995d3047 | 885 | |
0bc12bcb | 886 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) |
5422b37c | 887 | schedule_work(&dev_priv->psr.work); |
0bc12bcb RV |
888 | mutex_unlock(&dev_priv->psr.lock); |
889 | } | |
890 | ||
b2b89f55 RV |
891 | /** |
892 | * intel_psr_init - Init basic PSR work and mutex. | |
93de056b | 893 | * @dev_priv: i915 device private |
b2b89f55 RV |
894 | * |
895 | * This function is called only once at driver load to initialize basic | |
896 | * PSR stuff. | |
897 | */ | |
c39055b0 | 898 | void intel_psr_init(struct drm_i915_private *dev_priv) |
0bc12bcb | 899 | { |
0f328da6 RV |
900 | if (!HAS_PSR(dev_priv)) |
901 | return; | |
902 | ||
443a389f VS |
903 | dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? |
904 | HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; | |
905 | ||
c9ef291a DP |
906 | if (!dev_priv->psr.sink_support) |
907 | return; | |
908 | ||
2bdd045e DP |
909 | if (i915_modparams.enable_psr == -1) { |
910 | i915_modparams.enable_psr = dev_priv->vbt.psr.enable; | |
911 | ||
912 | /* Per platform default: all disabled. */ | |
4f044a88 | 913 | i915_modparams.enable_psr = 0; |
2bdd045e | 914 | } |
d94d6e87 | 915 | |
65f61b42 | 916 | /* Set link_standby x link_off defaults */ |
8652744b | 917 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
60e5ffe3 RV |
918 | /* HSW and BDW require workarounds that we don't implement. */ |
919 | dev_priv->psr.link_standby = false; | |
60e5ffe3 RV |
920 | else |
921 | /* For new platforms let's respect VBT back again */ | |
922 | dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; | |
923 | ||
65f61b42 | 924 | /* Override link_standby x link_off defaults */ |
4f044a88 | 925 | if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) { |
65f61b42 RV |
926 | DRM_DEBUG_KMS("PSR: Forcing link standby\n"); |
927 | dev_priv->psr.link_standby = true; | |
928 | } | |
4f044a88 | 929 | if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) { |
65f61b42 RV |
930 | DRM_DEBUG_KMS("PSR: Forcing main link off\n"); |
931 | dev_priv->psr.link_standby = false; | |
932 | } | |
933 | ||
5422b37c | 934 | INIT_WORK(&dev_priv->psr.work, intel_psr_work); |
0bc12bcb RV |
935 | mutex_init(&dev_priv->psr.lock); |
936 | } |