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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
18393f63 | 52 | |
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
4f54741e DG |
55 | int space = head - tail; |
56 | if (space <= 0) | |
1cf0ba14 | 57 | space += size; |
4f54741e | 58 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
59 | } |
60 | ||
ebd0fd4b DG |
61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
62 | { | |
63 | if (ringbuf->last_retired_head != -1) { | |
64 | ringbuf->head = ringbuf->last_retired_head; | |
65 | ringbuf->last_retired_head = -1; | |
66 | } | |
67 | ||
68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
69 | ringbuf->tail, ringbuf->size); | |
70 | } | |
71 | ||
82e104cc | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 73 | { |
ebd0fd4b DG |
74 | intel_ring_update_space(ringbuf); |
75 | return ringbuf->space; | |
1cf0ba14 CW |
76 | } |
77 | ||
82e104cc | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
82 | } | |
09246732 | 83 | |
6258fbe2 | 84 | static void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 85 | { |
93b0a4e0 OM |
86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
87 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 88 | if (intel_ring_stopped(ring)) |
09246732 | 89 | return; |
93b0a4e0 | 90 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
91 | } |
92 | ||
b72f3acb | 93 | static int |
a84c3ae1 | 94 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
95 | u32 invalidate_domains, |
96 | u32 flush_domains) | |
97 | { | |
a84c3ae1 | 98 | struct intel_engine_cs *ring = req->ring; |
46f0f8d1 CW |
99 | u32 cmd; |
100 | int ret; | |
101 | ||
102 | cmd = MI_FLUSH; | |
31b14c9f | 103 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
104 | cmd |= MI_NO_WRITE_FLUSH; |
105 | ||
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | ||
5fb9de1a | 109 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
110 | if (ret) |
111 | return ret; | |
112 | ||
113 | intel_ring_emit(ring, cmd); | |
114 | intel_ring_emit(ring, MI_NOOP); | |
115 | intel_ring_advance(ring); | |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
120 | static int | |
a84c3ae1 | 121 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
122 | u32 invalidate_domains, |
123 | u32 flush_domains) | |
62fdfeaf | 124 | { |
a84c3ae1 | 125 | struct intel_engine_cs *ring = req->ring; |
78501eac | 126 | struct drm_device *dev = ring->dev; |
6f392d54 | 127 | u32 cmd; |
b72f3acb | 128 | int ret; |
6f392d54 | 129 | |
36d527de CW |
130 | /* |
131 | * read/write caches: | |
132 | * | |
133 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
134 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
135 | * also flushed at 2d versus 3d pipeline switches. | |
136 | * | |
137 | * read-only caches: | |
138 | * | |
139 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
140 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
141 | * | |
142 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
143 | * | |
144 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
145 | * invalidated when MI_EXE_FLUSH is set. | |
146 | * | |
147 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
148 | * invalidated with every MI_FLUSH. | |
149 | * | |
150 | * TLBs: | |
151 | * | |
152 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
153 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
154 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
155 | * are flushed at any MI_FLUSH. | |
156 | */ | |
157 | ||
158 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 159 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 160 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
161 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
162 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 163 | |
36d527de CW |
164 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
165 | (IS_G4X(dev) || IS_GEN5(dev))) | |
166 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 167 | |
5fb9de1a | 168 | ret = intel_ring_begin(req, 2); |
36d527de CW |
169 | if (ret) |
170 | return ret; | |
b72f3acb | 171 | |
36d527de CW |
172 | intel_ring_emit(ring, cmd); |
173 | intel_ring_emit(ring, MI_NOOP); | |
174 | intel_ring_advance(ring); | |
b72f3acb CW |
175 | |
176 | return 0; | |
8187a2b7 ZN |
177 | } |
178 | ||
8d315287 JB |
179 | /** |
180 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
181 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
182 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
183 | * | |
184 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
185 | * produced by non-pipelined state commands), software needs to first | |
186 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
187 | * 0. | |
188 | * | |
189 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
190 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
191 | * | |
192 | * And the workaround for these two requires this workaround first: | |
193 | * | |
194 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
195 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
196 | * flushes. | |
197 | * | |
198 | * And this last workaround is tricky because of the requirements on | |
199 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
200 | * volume 2 part 1: | |
201 | * | |
202 | * "1 of the following must also be set: | |
203 | * - Render Target Cache Flush Enable ([12] of DW1) | |
204 | * - Depth Cache Flush Enable ([0] of DW1) | |
205 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
206 | * - Depth Stall ([13] of DW1) | |
207 | * - Post-Sync Operation ([13] of DW1) | |
208 | * - Notify Enable ([8] of DW1)" | |
209 | * | |
210 | * The cache flushes require the workaround flush that triggered this | |
211 | * one, so we can't use it. Depth stall would trigger the same. | |
212 | * Post-sync nonzero is what triggered this second workaround, so we | |
213 | * can't use that one either. Notify enable is IRQs, which aren't | |
214 | * really our business. That leaves only stall at scoreboard. | |
215 | */ | |
216 | static int | |
f2cf1fcc | 217 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 218 | { |
f2cf1fcc | 219 | struct intel_engine_cs *ring = req->ring; |
18393f63 | 220 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
221 | int ret; |
222 | ||
5fb9de1a | 223 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
224 | if (ret) |
225 | return ret; | |
226 | ||
227 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
228 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
229 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
230 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
231 | intel_ring_emit(ring, 0); /* low dword */ | |
232 | intel_ring_emit(ring, 0); /* high dword */ | |
233 | intel_ring_emit(ring, MI_NOOP); | |
234 | intel_ring_advance(ring); | |
235 | ||
5fb9de1a | 236 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
237 | if (ret) |
238 | return ret; | |
239 | ||
240 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
241 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
242 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
243 | intel_ring_emit(ring, 0); | |
244 | intel_ring_emit(ring, 0); | |
245 | intel_ring_emit(ring, MI_NOOP); | |
246 | intel_ring_advance(ring); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | static int | |
a84c3ae1 JH |
252 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
253 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 254 | { |
a84c3ae1 | 255 | struct intel_engine_cs *ring = req->ring; |
8d315287 | 256 | u32 flags = 0; |
18393f63 | 257 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
258 | int ret; |
259 | ||
b3111509 | 260 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 261 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
262 | if (ret) |
263 | return ret; | |
264 | ||
8d315287 JB |
265 | /* Just flush everything. Experiments have shown that reducing the |
266 | * number of bits based on the write domains has little performance | |
267 | * impact. | |
268 | */ | |
7d54a904 CW |
269 | if (flush_domains) { |
270 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
271 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
272 | /* | |
273 | * Ensure that any following seqno writes only happen | |
274 | * when the render cache is indeed flushed. | |
275 | */ | |
97f209bc | 276 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
277 | } |
278 | if (invalidate_domains) { | |
279 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
282 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
283 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
284 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
285 | /* | |
286 | * TLB invalidate requires a post-sync write. | |
287 | */ | |
3ac78313 | 288 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 289 | } |
8d315287 | 290 | |
5fb9de1a | 291 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
292 | if (ret) |
293 | return ret; | |
294 | ||
6c6cf5aa | 295 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
296 | intel_ring_emit(ring, flags); |
297 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 298 | intel_ring_emit(ring, 0); |
8d315287 JB |
299 | intel_ring_advance(ring); |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
f3987631 | 304 | static int |
f2cf1fcc | 305 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 306 | { |
f2cf1fcc | 307 | struct intel_engine_cs *ring = req->ring; |
f3987631 PZ |
308 | int ret; |
309 | ||
5fb9de1a | 310 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
311 | if (ret) |
312 | return ret; | |
313 | ||
314 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
315 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
316 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
317 | intel_ring_emit(ring, 0); | |
318 | intel_ring_emit(ring, 0); | |
319 | intel_ring_advance(ring); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
4772eaeb | 324 | static int |
a84c3ae1 | 325 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
326 | u32 invalidate_domains, u32 flush_domains) |
327 | { | |
a84c3ae1 | 328 | struct intel_engine_cs *ring = req->ring; |
4772eaeb | 329 | u32 flags = 0; |
18393f63 | 330 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
331 | int ret; |
332 | ||
f3987631 PZ |
333 | /* |
334 | * Ensure that any following seqno writes only happen when the render | |
335 | * cache is indeed flushed. | |
336 | * | |
337 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
338 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
339 | * don't try to be clever and just set it unconditionally. | |
340 | */ | |
341 | flags |= PIPE_CONTROL_CS_STALL; | |
342 | ||
4772eaeb PZ |
343 | /* Just flush everything. Experiments have shown that reducing the |
344 | * number of bits based on the write domains has little performance | |
345 | * impact. | |
346 | */ | |
347 | if (flush_domains) { | |
348 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
349 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
40a24488 | 350 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
351 | } |
352 | if (invalidate_domains) { | |
353 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
354 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
355 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
356 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
357 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
358 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 359 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
360 | /* |
361 | * TLB invalidate requires a post-sync write. | |
362 | */ | |
363 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 364 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 365 | |
add284a3 CW |
366 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
367 | ||
f3987631 PZ |
368 | /* Workaround: we must issue a pipe_control with CS-stall bit |
369 | * set before a pipe_control command that has the state cache | |
370 | * invalidate bit set. */ | |
f2cf1fcc | 371 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
372 | } |
373 | ||
5fb9de1a | 374 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
375 | if (ret) |
376 | return ret; | |
377 | ||
378 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
379 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 380 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
381 | intel_ring_emit(ring, 0); |
382 | intel_ring_advance(ring); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
884ceace | 387 | static int |
f2cf1fcc | 388 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
389 | u32 flags, u32 scratch_addr) |
390 | { | |
f2cf1fcc | 391 | struct intel_engine_cs *ring = req->ring; |
884ceace KG |
392 | int ret; |
393 | ||
5fb9de1a | 394 | ret = intel_ring_begin(req, 6); |
884ceace KG |
395 | if (ret) |
396 | return ret; | |
397 | ||
398 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
399 | intel_ring_emit(ring, flags); | |
400 | intel_ring_emit(ring, scratch_addr); | |
401 | intel_ring_emit(ring, 0); | |
402 | intel_ring_emit(ring, 0); | |
403 | intel_ring_emit(ring, 0); | |
404 | intel_ring_advance(ring); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
a5f3d68e | 409 | static int |
a84c3ae1 | 410 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
411 | u32 invalidate_domains, u32 flush_domains) |
412 | { | |
413 | u32 flags = 0; | |
f2cf1fcc | 414 | u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 415 | int ret; |
a5f3d68e BW |
416 | |
417 | flags |= PIPE_CONTROL_CS_STALL; | |
418 | ||
419 | if (flush_domains) { | |
420 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
421 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
40a24488 | 422 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
423 | } |
424 | if (invalidate_domains) { | |
425 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
426 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
427 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
428 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
429 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
430 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
431 | flags |= PIPE_CONTROL_QW_WRITE; | |
432 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
433 | |
434 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 435 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
436 | PIPE_CONTROL_CS_STALL | |
437 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
438 | 0); | |
439 | if (ret) | |
440 | return ret; | |
a5f3d68e BW |
441 | } |
442 | ||
f2cf1fcc | 443 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
444 | } |
445 | ||
a4872ba6 | 446 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 447 | u32 value) |
d46eefa2 | 448 | { |
4640c4ff | 449 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 450 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
451 | } |
452 | ||
a4872ba6 | 453 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 454 | { |
4640c4ff | 455 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 456 | u64 acthd; |
8187a2b7 | 457 | |
50877445 CW |
458 | if (INTEL_INFO(ring->dev)->gen >= 8) |
459 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
460 | RING_ACTHD_UDW(ring->mmio_base)); | |
461 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
462 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
463 | else | |
464 | acthd = I915_READ(ACTHD); | |
465 | ||
466 | return acthd; | |
8187a2b7 ZN |
467 | } |
468 | ||
a4872ba6 | 469 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
470 | { |
471 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
472 | u32 addr; | |
473 | ||
474 | addr = dev_priv->status_page_dmah->busaddr; | |
475 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
476 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
477 | I915_WRITE(HWS_PGA, addr); | |
478 | } | |
479 | ||
af75f269 DL |
480 | static void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
481 | { | |
482 | struct drm_device *dev = ring->dev; | |
483 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
f0f59a00 | 484 | i915_reg_t mmio; |
af75f269 DL |
485 | |
486 | /* The ring status page addresses are no longer next to the rest of | |
487 | * the ring registers as of gen7. | |
488 | */ | |
489 | if (IS_GEN7(dev)) { | |
490 | switch (ring->id) { | |
491 | case RCS: | |
492 | mmio = RENDER_HWS_PGA_GEN7; | |
493 | break; | |
494 | case BCS: | |
495 | mmio = BLT_HWS_PGA_GEN7; | |
496 | break; | |
497 | /* | |
498 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
499 | * gcc switch check warning | |
500 | */ | |
501 | case VCS2: | |
502 | case VCS: | |
503 | mmio = BSD_HWS_PGA_GEN7; | |
504 | break; | |
505 | case VECS: | |
506 | mmio = VEBOX_HWS_PGA_GEN7; | |
507 | break; | |
508 | } | |
509 | } else if (IS_GEN6(ring->dev)) { | |
510 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
511 | } else { | |
512 | /* XXX: gen8 returns to sanity */ | |
513 | mmio = RING_HWS_PGA(ring->mmio_base); | |
514 | } | |
515 | ||
516 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
517 | POSTING_READ(mmio); | |
518 | ||
519 | /* | |
520 | * Flush the TLB for this page | |
521 | * | |
522 | * FIXME: These two bits have disappeared on gen8, so a question | |
523 | * arises: do we still need this and if so how should we go about | |
524 | * invalidating the TLB? | |
525 | */ | |
526 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
f0f59a00 | 527 | i915_reg_t reg = RING_INSTPM(ring->mmio_base); |
af75f269 DL |
528 | |
529 | /* ring should be idle before issuing a sync flush*/ | |
530 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
531 | ||
532 | I915_WRITE(reg, | |
533 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
534 | INSTPM_SYNC_FLUSH)); | |
535 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
536 | 1000)) | |
537 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
538 | ring->name); | |
539 | } | |
540 | } | |
541 | ||
a4872ba6 | 542 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 543 | { |
9991ae78 | 544 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 545 | |
9991ae78 CW |
546 | if (!IS_GEN2(ring->dev)) { |
547 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
548 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
549 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
550 | /* Sometimes we observe that the idle flag is not |
551 | * set even though the ring is empty. So double | |
552 | * check before giving up. | |
553 | */ | |
554 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
555 | return false; | |
9991ae78 CW |
556 | } |
557 | } | |
b7884eb4 | 558 | |
7f2ab699 | 559 | I915_WRITE_CTL(ring, 0); |
570ef608 | 560 | I915_WRITE_HEAD(ring, 0); |
78501eac | 561 | ring->write_tail(ring, 0); |
8187a2b7 | 562 | |
9991ae78 CW |
563 | if (!IS_GEN2(ring->dev)) { |
564 | (void)I915_READ_CTL(ring); | |
565 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
566 | } | |
a51435a3 | 567 | |
9991ae78 CW |
568 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
569 | } | |
8187a2b7 | 570 | |
a4872ba6 | 571 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
572 | { |
573 | struct drm_device *dev = ring->dev; | |
574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
575 | struct intel_ringbuffer *ringbuf = ring->buffer; |
576 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
577 | int ret = 0; |
578 | ||
59bad947 | 579 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 CW |
580 | |
581 | if (!stop_ring(ring)) { | |
582 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
583 | DRM_DEBUG_KMS("%s head not reset to zero " |
584 | "ctl %08x head %08x tail %08x start %08x\n", | |
585 | ring->name, | |
586 | I915_READ_CTL(ring), | |
587 | I915_READ_HEAD(ring), | |
588 | I915_READ_TAIL(ring), | |
589 | I915_READ_START(ring)); | |
8187a2b7 | 590 | |
9991ae78 | 591 | if (!stop_ring(ring)) { |
6fd0d56e CW |
592 | DRM_ERROR("failed to set %s head to zero " |
593 | "ctl %08x head %08x tail %08x start %08x\n", | |
594 | ring->name, | |
595 | I915_READ_CTL(ring), | |
596 | I915_READ_HEAD(ring), | |
597 | I915_READ_TAIL(ring), | |
598 | I915_READ_START(ring)); | |
9991ae78 CW |
599 | ret = -EIO; |
600 | goto out; | |
6fd0d56e | 601 | } |
8187a2b7 ZN |
602 | } |
603 | ||
9991ae78 CW |
604 | if (I915_NEED_GFX_HWS(dev)) |
605 | intel_ring_setup_status_page(ring); | |
606 | else | |
607 | ring_setup_phys_status_page(ring); | |
608 | ||
ece4a17d JK |
609 | /* Enforce ordering by reading HEAD register back */ |
610 | I915_READ_HEAD(ring); | |
611 | ||
0d8957c8 DV |
612 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
613 | * registers with the above sequence (the readback of the HEAD registers | |
614 | * also enforces ordering), otherwise the hw might lose the new ring | |
615 | * register values. */ | |
f343c5f6 | 616 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
617 | |
618 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
619 | if (I915_READ_HEAD(ring)) | |
620 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
621 | ring->name, I915_READ_HEAD(ring)); | |
622 | I915_WRITE_HEAD(ring, 0); | |
623 | (void)I915_READ_HEAD(ring); | |
624 | ||
7f2ab699 | 625 | I915_WRITE_CTL(ring, |
93b0a4e0 | 626 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 627 | | RING_VALID); |
8187a2b7 | 628 | |
8187a2b7 | 629 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 630 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 631 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 632 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 633 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
634 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
635 | ring->name, | |
636 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
637 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
638 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
639 | ret = -EIO; |
640 | goto out; | |
8187a2b7 ZN |
641 | } |
642 | ||
ebd0fd4b | 643 | ringbuf->last_retired_head = -1; |
5c6c6003 CW |
644 | ringbuf->head = I915_READ_HEAD(ring); |
645 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
ebd0fd4b | 646 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 647 | |
50f018df CW |
648 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
649 | ||
b7884eb4 | 650 | out: |
59bad947 | 651 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
652 | |
653 | return ret; | |
8187a2b7 ZN |
654 | } |
655 | ||
9b1136d5 OM |
656 | void |
657 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
658 | { | |
659 | struct drm_device *dev = ring->dev; | |
660 | ||
661 | if (ring->scratch.obj == NULL) | |
662 | return; | |
663 | ||
664 | if (INTEL_INFO(dev)->gen >= 5) { | |
665 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
666 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
667 | } | |
668 | ||
669 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
670 | ring->scratch.obj = NULL; | |
671 | } | |
672 | ||
673 | int | |
674 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 675 | { |
c6df541c CW |
676 | int ret; |
677 | ||
bfc882b4 | 678 | WARN_ON(ring->scratch.obj); |
c6df541c | 679 | |
0d1aacac CW |
680 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
681 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
682 | DRM_ERROR("Failed to allocate seqno page\n"); |
683 | ret = -ENOMEM; | |
684 | goto err; | |
685 | } | |
e4ffd173 | 686 | |
a9cc726c DV |
687 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
688 | if (ret) | |
689 | goto err_unref; | |
c6df541c | 690 | |
1ec9e26d | 691 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
692 | if (ret) |
693 | goto err_unref; | |
694 | ||
0d1aacac CW |
695 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
696 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
697 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 698 | ret = -ENOMEM; |
c6df541c | 699 | goto err_unpin; |
56b085a0 | 700 | } |
c6df541c | 701 | |
2b1086cc | 702 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 703 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
704 | return 0; |
705 | ||
706 | err_unpin: | |
d7f46fc4 | 707 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 708 | err_unref: |
0d1aacac | 709 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 710 | err: |
c6df541c CW |
711 | return ret; |
712 | } | |
713 | ||
e2be4faf | 714 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 715 | { |
7225342a | 716 | int ret, i; |
e2be4faf | 717 | struct intel_engine_cs *ring = req->ring; |
888b5995 AS |
718 | struct drm_device *dev = ring->dev; |
719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7225342a | 720 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 721 | |
02235808 | 722 | if (w->count == 0) |
7225342a | 723 | return 0; |
888b5995 | 724 | |
7225342a | 725 | ring->gpu_caches_dirty = true; |
4866d729 | 726 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
727 | if (ret) |
728 | return ret; | |
888b5995 | 729 | |
5fb9de1a | 730 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
731 | if (ret) |
732 | return ret; | |
733 | ||
22a916aa | 734 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 735 | for (i = 0; i < w->count; i++) { |
f92a9162 | 736 | intel_ring_emit_reg(ring, w->reg[i].addr); |
7225342a MK |
737 | intel_ring_emit(ring, w->reg[i].value); |
738 | } | |
22a916aa | 739 | intel_ring_emit(ring, MI_NOOP); |
7225342a MK |
740 | |
741 | intel_ring_advance(ring); | |
742 | ||
743 | ring->gpu_caches_dirty = true; | |
4866d729 | 744 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
745 | if (ret) |
746 | return ret; | |
888b5995 | 747 | |
7225342a | 748 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 749 | |
7225342a | 750 | return 0; |
86d7f238 AS |
751 | } |
752 | ||
8753181e | 753 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
754 | { |
755 | int ret; | |
756 | ||
e2be4faf | 757 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
758 | if (ret != 0) |
759 | return ret; | |
760 | ||
be01363f | 761 | ret = i915_gem_render_state_init(req); |
8f0e2b9d DV |
762 | if (ret) |
763 | DRM_ERROR("init render state: %d\n", ret); | |
764 | ||
765 | return ret; | |
766 | } | |
767 | ||
7225342a | 768 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
769 | i915_reg_t addr, |
770 | const u32 mask, const u32 val) | |
7225342a MK |
771 | { |
772 | const u32 idx = dev_priv->workarounds.count; | |
773 | ||
774 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
775 | return -ENOSPC; | |
776 | ||
777 | dev_priv->workarounds.reg[idx].addr = addr; | |
778 | dev_priv->workarounds.reg[idx].value = val; | |
779 | dev_priv->workarounds.reg[idx].mask = mask; | |
780 | ||
781 | dev_priv->workarounds.count++; | |
782 | ||
783 | return 0; | |
86d7f238 AS |
784 | } |
785 | ||
ca5a0fbd | 786 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 787 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
788 | if (r) \ |
789 | return r; \ | |
ca5a0fbd | 790 | } while (0) |
7225342a MK |
791 | |
792 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 793 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
794 | |
795 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 796 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 797 | |
98533251 | 798 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 799 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 800 | |
cf4b0de6 DL |
801 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
802 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 803 | |
cf4b0de6 | 804 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 805 | |
e9a64ada AS |
806 | static int gen8_init_workarounds(struct intel_engine_cs *ring) |
807 | { | |
68c6198b AS |
808 | struct drm_device *dev = ring->dev; |
809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
810 | ||
811 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 812 | |
717d84d6 AS |
813 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
814 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
815 | ||
d0581194 AS |
816 | /* WaDisablePartialInstShootdown:bdw,chv */ |
817 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
818 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
819 | ||
a340af58 AS |
820 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
821 | * workaround for for a possible hang in the unlikely event a TLB | |
822 | * invalidation occurs during a PSD flush. | |
823 | */ | |
824 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 825 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 826 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 827 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
828 | HDC_FORCE_NON_COHERENT); |
829 | ||
6def8fdd AS |
830 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
831 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
832 | * polygons in the same 8x4 pixel/sample area to be processed without | |
833 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
834 | * buffer." | |
835 | * | |
836 | * This optimization is off by default for BDW and CHV; turn it on. | |
837 | */ | |
838 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
839 | ||
48404636 AS |
840 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
841 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
842 | ||
7eebcde6 AS |
843 | /* |
844 | * BSpec recommends 8x4 when MSAA is used, | |
845 | * however in practice 16x4 seems fastest. | |
846 | * | |
847 | * Note that PS/WM thread counts depend on the WIZ hashing | |
848 | * disable bit, which we don't touch here, but it's good | |
849 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
850 | */ | |
851 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
852 | GEN6_WIZ_HASHING_MASK, | |
853 | GEN6_WIZ_HASHING_16x4); | |
854 | ||
e9a64ada AS |
855 | return 0; |
856 | } | |
857 | ||
00e1e623 | 858 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 | 859 | { |
e9a64ada | 860 | int ret; |
888b5995 AS |
861 | struct drm_device *dev = ring->dev; |
862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 | 863 | |
e9a64ada AS |
864 | ret = gen8_init_workarounds(ring); |
865 | if (ret) | |
866 | return ret; | |
867 | ||
101b376d | 868 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 869 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 870 | |
101b376d | 871 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
872 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
873 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 874 | |
7225342a MK |
875 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
876 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 877 | |
7225342a | 878 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
879 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
880 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 881 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 882 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 883 | |
86d7f238 AS |
884 | return 0; |
885 | } | |
886 | ||
00e1e623 VS |
887 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
888 | { | |
e9a64ada | 889 | int ret; |
00e1e623 VS |
890 | struct drm_device *dev = ring->dev; |
891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
892 | ||
e9a64ada AS |
893 | ret = gen8_init_workarounds(ring); |
894 | if (ret) | |
895 | return ret; | |
896 | ||
00e1e623 | 897 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 898 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 899 | |
d60de81d KG |
900 | /* Improve HiZ throughput on CHV. */ |
901 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
902 | ||
7225342a MK |
903 | return 0; |
904 | } | |
905 | ||
3b106531 HN |
906 | static int gen9_init_workarounds(struct intel_engine_cs *ring) |
907 | { | |
ab0dfafe HN |
908 | struct drm_device *dev = ring->dev; |
909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8ea6f892 | 910 | uint32_t tmp; |
ab0dfafe | 911 | |
9c4cbf82 MK |
912 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
913 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
914 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
915 | ||
916 | /* WaDisableKillLogic:bxt,skl */ | |
917 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
918 | ECOCHK_DIS_TLB); | |
919 | ||
b0e6f6d4 | 920 | /* WaDisablePartialInstShootdown:skl,bxt */ |
ab0dfafe HN |
921 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
922 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
923 | ||
a119a6e6 | 924 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
8424171e NH |
925 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
926 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
927 | ||
e87a005d JN |
928 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
929 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
930 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
931 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
932 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 933 | |
e87a005d JN |
934 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
935 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
936 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
937 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
938 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
939 | /* |
940 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
941 | * but we do that in per ctx batchbuffer as there is an issue | |
942 | * with this register not getting restored on ctx restore | |
943 | */ | |
183c6dac DL |
944 | } |
945 | ||
e87a005d JN |
946 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
947 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev)) | |
cac23df4 NH |
948 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
949 | GEN9_ENABLE_YV12_BUGFIX); | |
cac23df4 | 950 | |
5068368c | 951 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
27160c96 | 952 | /* WaDisablePartialResolveInVc:skl,bxt */ |
60294683 AS |
953 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
954 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 955 | |
16be17af | 956 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
e2db7071 DL |
957 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
958 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
959 | ||
5a2ae95e | 960 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
961 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
962 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
963 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
964 | PIXEL_MASK_CAMMING_DISABLE); | |
965 | ||
8ea6f892 ID |
966 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
967 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; | |
e87a005d JN |
968 | if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) || |
969 | IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) | |
8ea6f892 ID |
970 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
971 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); | |
972 | ||
8c761609 | 973 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ |
e87a005d | 974 | if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) |
8c761609 AS |
975 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
976 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 977 | |
6b6d5626 RB |
978 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
979 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); | |
980 | ||
3b106531 HN |
981 | return 0; |
982 | } | |
983 | ||
b7668791 DL |
984 | static int skl_tune_iz_hashing(struct intel_engine_cs *ring) |
985 | { | |
986 | struct drm_device *dev = ring->dev; | |
987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
988 | u8 vals[3] = { 0, 0, 0 }; | |
989 | unsigned int i; | |
990 | ||
991 | for (i = 0; i < 3; i++) { | |
992 | u8 ss; | |
993 | ||
994 | /* | |
995 | * Only consider slices where one, and only one, subslice has 7 | |
996 | * EUs | |
997 | */ | |
998 | if (hweight8(dev_priv->info.subslice_7eu[i]) != 1) | |
999 | continue; | |
1000 | ||
1001 | /* | |
1002 | * subslice_7eu[i] != 0 (because of the check above) and | |
1003 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1004 | * | |
1005 | * -> 0 <= ss <= 3; | |
1006 | */ | |
1007 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1008 | vals[i] = 3 - ss; | |
1009 | } | |
1010 | ||
1011 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1012 | return 0; | |
1013 | ||
1014 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1015 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1016 | GEN9_IZ_HASHING_MASK(2) | | |
1017 | GEN9_IZ_HASHING_MASK(1) | | |
1018 | GEN9_IZ_HASHING_MASK(0), | |
1019 | GEN9_IZ_HASHING(2, vals[2]) | | |
1020 | GEN9_IZ_HASHING(1, vals[1]) | | |
1021 | GEN9_IZ_HASHING(0, vals[0])); | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
8d205494 DL |
1026 | static int skl_init_workarounds(struct intel_engine_cs *ring) |
1027 | { | |
aa0011a8 | 1028 | int ret; |
d0bbbc4f DL |
1029 | struct drm_device *dev = ring->dev; |
1030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1031 | ||
aa0011a8 AS |
1032 | ret = gen9_init_workarounds(ring); |
1033 | if (ret) | |
1034 | return ret; | |
8d205494 | 1035 | |
e87a005d | 1036 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1037 | /* WaDisableHDCInvalidation:skl */ |
1038 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1039 | BDW_DISABLE_HDC_INVALIDATION); | |
1040 | ||
1041 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ | |
1042 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1043 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1044 | } | |
1045 | ||
1046 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1047 | * involving this register should also be added to WA batch as required. | |
1048 | */ | |
e87a005d | 1049 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1050 | /* WaDisableLSQCROPERFforOCL:skl */ |
1051 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1052 | GEN8_LQSC_RO_PERF_DIS); | |
1053 | ||
1054 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1055 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1056 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1057 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1058 | } | |
1059 | ||
d0bbbc4f | 1060 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1061 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1062 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1063 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1064 | ||
e87a005d | 1065 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
b62adbd1 NH |
1066 | /* |
1067 | *Use Force Non-Coherent whenever executing a 3D context. This | |
1068 | * is a workaround for a possible hang in the unlikely event | |
1069 | * a TLB invalidation occurs during a PSD flush. | |
1070 | */ | |
1071 | /* WaForceEnableNonCoherent:skl */ | |
1072 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1073 | HDC_FORCE_NON_COHERENT); | |
1074 | } | |
1075 | ||
e87a005d JN |
1076 | /* WaBarrierPerformanceFixDisable:skl */ |
1077 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1078 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1079 | HDC_FENCE_DEST_SLM_DISABLE | | |
1080 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1081 | ||
9bd9dfb4 | 1082 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1083 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1084 | WA_SET_BIT_MASKED( |
1085 | GEN7_HALF_SLICE_CHICKEN1, | |
1086 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1087 | |
b7668791 | 1088 | return skl_tune_iz_hashing(ring); |
7225342a MK |
1089 | } |
1090 | ||
cae0437f NH |
1091 | static int bxt_init_workarounds(struct intel_engine_cs *ring) |
1092 | { | |
aa0011a8 | 1093 | int ret; |
dfb601e6 NH |
1094 | struct drm_device *dev = ring->dev; |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1096 | ||
aa0011a8 AS |
1097 | ret = gen9_init_workarounds(ring); |
1098 | if (ret) | |
1099 | return ret; | |
cae0437f | 1100 | |
9c4cbf82 MK |
1101 | /* WaStoreMultiplePTEenable:bxt */ |
1102 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1103 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1104 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1105 | ||
1106 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1107 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1108 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1109 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1110 | } | |
1111 | ||
dfb601e6 NH |
1112 | /* WaDisableThreadStallDopClockGating:bxt */ |
1113 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1114 | STALL_DOP_GATING_DISABLE); | |
1115 | ||
983b4b9d | 1116 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1117 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1118 | WA_SET_BIT_MASKED( |
1119 | GEN7_HALF_SLICE_CHICKEN1, | |
1120 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1121 | } | |
1122 | ||
cae0437f NH |
1123 | return 0; |
1124 | } | |
1125 | ||
771b9a53 | 1126 | int init_workarounds_ring(struct intel_engine_cs *ring) |
7225342a MK |
1127 | { |
1128 | struct drm_device *dev = ring->dev; | |
1129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1130 | ||
1131 | WARN_ON(ring->id != RCS); | |
1132 | ||
1133 | dev_priv->workarounds.count = 0; | |
1134 | ||
1135 | if (IS_BROADWELL(dev)) | |
1136 | return bdw_init_workarounds(ring); | |
1137 | ||
1138 | if (IS_CHERRYVIEW(dev)) | |
1139 | return chv_init_workarounds(ring); | |
00e1e623 | 1140 | |
8d205494 DL |
1141 | if (IS_SKYLAKE(dev)) |
1142 | return skl_init_workarounds(ring); | |
cae0437f NH |
1143 | |
1144 | if (IS_BROXTON(dev)) | |
1145 | return bxt_init_workarounds(ring); | |
3b106531 | 1146 | |
00e1e623 VS |
1147 | return 0; |
1148 | } | |
1149 | ||
a4872ba6 | 1150 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 1151 | { |
78501eac | 1152 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 1153 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1154 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
1155 | if (ret) |
1156 | return ret; | |
a69ffdbf | 1157 | |
61a563a2 AG |
1158 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1159 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1160 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1161 | |
1162 | /* We need to disable the AsyncFlip performance optimisations in order | |
1163 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1164 | * programmed to '1' on all products. | |
8693a824 | 1165 | * |
2441f877 | 1166 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1167 | */ |
2441f877 | 1168 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1169 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1170 | ||
f05bb0c7 | 1171 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1172 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1173 | if (INTEL_INFO(dev)->gen == 6) |
1174 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1175 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1176 | |
01fa0302 | 1177 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1178 | if (IS_GEN7(dev)) |
1179 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1180 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1181 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1182 | |
5e13a0c5 | 1183 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1184 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1185 | * "If this bit is set, STCunit will have LRA as replacement | |
1186 | * policy. [...] This bit must be reset. LRA replacement | |
1187 | * policy is not supported." | |
1188 | */ | |
1189 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1190 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1191 | } |
1192 | ||
9cc83020 | 1193 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1194 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1195 | |
040d2baa | 1196 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 1197 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1198 | |
7225342a | 1199 | return init_workarounds_ring(ring); |
8187a2b7 ZN |
1200 | } |
1201 | ||
a4872ba6 | 1202 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 1203 | { |
b45305fc | 1204 | struct drm_device *dev = ring->dev; |
3e78998a BW |
1205 | struct drm_i915_private *dev_priv = dev->dev_private; |
1206 | ||
1207 | if (dev_priv->semaphore_obj) { | |
1208 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1209 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1210 | dev_priv->semaphore_obj = NULL; | |
1211 | } | |
b45305fc | 1212 | |
9b1136d5 | 1213 | intel_fini_pipe_control(ring); |
c6df541c CW |
1214 | } |
1215 | ||
f7169687 | 1216 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1217 | unsigned int num_dwords) |
1218 | { | |
1219 | #define MBOX_UPDATE_DWORDS 8 | |
f7169687 | 1220 | struct intel_engine_cs *signaller = signaller_req->ring; |
3e78998a BW |
1221 | struct drm_device *dev = signaller->dev; |
1222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1223 | struct intel_engine_cs *waiter; | |
1224 | int i, ret, num_rings; | |
1225 | ||
1226 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1227 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1228 | #undef MBOX_UPDATE_DWORDS | |
1229 | ||
5fb9de1a | 1230 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1231 | if (ret) |
1232 | return ret; | |
1233 | ||
1234 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 1235 | u32 seqno; |
3e78998a BW |
1236 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
1237 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
1238 | continue; | |
1239 | ||
f7169687 | 1240 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1241 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1242 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1243 | PIPE_CONTROL_QW_WRITE | | |
1244 | PIPE_CONTROL_FLUSH_ENABLE); | |
1245 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1246 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1247 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1248 | intel_ring_emit(signaller, 0); |
1249 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
1250 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1251 | intel_ring_emit(signaller, 0); | |
1252 | } | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
f7169687 | 1257 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1258 | unsigned int num_dwords) |
1259 | { | |
1260 | #define MBOX_UPDATE_DWORDS 6 | |
f7169687 | 1261 | struct intel_engine_cs *signaller = signaller_req->ring; |
3e78998a BW |
1262 | struct drm_device *dev = signaller->dev; |
1263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1264 | struct intel_engine_cs *waiter; | |
1265 | int i, ret, num_rings; | |
1266 | ||
1267 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1268 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1269 | #undef MBOX_UPDATE_DWORDS | |
1270 | ||
5fb9de1a | 1271 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1272 | if (ret) |
1273 | return ret; | |
1274 | ||
1275 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 1276 | u32 seqno; |
3e78998a BW |
1277 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
1278 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
1279 | continue; | |
1280 | ||
f7169687 | 1281 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1282 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1283 | MI_FLUSH_DW_OP_STOREDW); | |
1284 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1285 | MI_FLUSH_DW_USE_GTT); | |
1286 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1287 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1288 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
1289 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1290 | intel_ring_emit(signaller, 0); | |
1291 | } | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
f7169687 | 1296 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1297 | unsigned int num_dwords) |
1ec14ad3 | 1298 | { |
f7169687 | 1299 | struct intel_engine_cs *signaller = signaller_req->ring; |
024a43e1 BW |
1300 | struct drm_device *dev = signaller->dev; |
1301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1302 | struct intel_engine_cs *useless; |
a1444b79 | 1303 | int i, ret, num_rings; |
78325f2d | 1304 | |
a1444b79 BW |
1305 | #define MBOX_UPDATE_DWORDS 3 |
1306 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1307 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1308 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1309 | |
5fb9de1a | 1310 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1311 | if (ret) |
1312 | return ret; | |
024a43e1 | 1313 | |
78325f2d | 1314 | for_each_ring(useless, dev_priv, i) { |
f0f59a00 VS |
1315 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i]; |
1316 | ||
1317 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1318 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1319 | |
78325f2d | 1320 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1321 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1322 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1323 | } |
1324 | } | |
024a43e1 | 1325 | |
a1444b79 BW |
1326 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1327 | if (num_rings % 2 == 0) | |
1328 | intel_ring_emit(signaller, MI_NOOP); | |
1329 | ||
024a43e1 | 1330 | return 0; |
1ec14ad3 CW |
1331 | } |
1332 | ||
c8c99b0f BW |
1333 | /** |
1334 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1335 | * |
1336 | * @request - request to write to the ring | |
c8c99b0f BW |
1337 | * |
1338 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1339 | * This acts like a signal in the canonical semaphore. | |
1340 | */ | |
1ec14ad3 | 1341 | static int |
ee044a88 | 1342 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1343 | { |
ee044a88 | 1344 | struct intel_engine_cs *ring = req->ring; |
024a43e1 | 1345 | int ret; |
52ed2325 | 1346 | |
707d9cf9 | 1347 | if (ring->semaphore.signal) |
f7169687 | 1348 | ret = ring->semaphore.signal(req, 4); |
707d9cf9 | 1349 | else |
5fb9de1a | 1350 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1351 | |
1ec14ad3 CW |
1352 | if (ret) |
1353 | return ret; | |
1354 | ||
1ec14ad3 CW |
1355 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1356 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
ee044a88 | 1357 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); |
1ec14ad3 | 1358 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1359 | __intel_ring_advance(ring); |
1ec14ad3 | 1360 | |
1ec14ad3 CW |
1361 | return 0; |
1362 | } | |
1363 | ||
f72b3435 MK |
1364 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1365 | u32 seqno) | |
1366 | { | |
1367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1368 | return dev_priv->last_seqno < seqno; | |
1369 | } | |
1370 | ||
c8c99b0f BW |
1371 | /** |
1372 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1373 | * | |
1374 | * @waiter - ring that is waiting | |
1375 | * @signaller - ring which has, or will signal | |
1376 | * @seqno - seqno which the waiter will block on | |
1377 | */ | |
5ee426ca BW |
1378 | |
1379 | static int | |
599d924c | 1380 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1381 | struct intel_engine_cs *signaller, |
1382 | u32 seqno) | |
1383 | { | |
599d924c | 1384 | struct intel_engine_cs *waiter = waiter_req->ring; |
5ee426ca BW |
1385 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1386 | int ret; | |
1387 | ||
5fb9de1a | 1388 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1389 | if (ret) |
1390 | return ret; | |
1391 | ||
1392 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1393 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1394 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1395 | MI_SEMAPHORE_SAD_GTE_SDD); |
1396 | intel_ring_emit(waiter, seqno); | |
1397 | intel_ring_emit(waiter, | |
1398 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1399 | intel_ring_emit(waiter, | |
1400 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1401 | intel_ring_advance(waiter); | |
1402 | return 0; | |
1403 | } | |
1404 | ||
c8c99b0f | 1405 | static int |
599d924c | 1406 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1407 | struct intel_engine_cs *signaller, |
686cb5f9 | 1408 | u32 seqno) |
1ec14ad3 | 1409 | { |
599d924c | 1410 | struct intel_engine_cs *waiter = waiter_req->ring; |
c8c99b0f BW |
1411 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1412 | MI_SEMAPHORE_COMPARE | | |
1413 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1414 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1415 | int ret; | |
1ec14ad3 | 1416 | |
1500f7ea BW |
1417 | /* Throughout all of the GEM code, seqno passed implies our current |
1418 | * seqno is >= the last seqno executed. However for hardware the | |
1419 | * comparison is strictly greater than. | |
1420 | */ | |
1421 | seqno -= 1; | |
1422 | ||
ebc348b2 | 1423 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1424 | |
5fb9de1a | 1425 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1426 | if (ret) |
1427 | return ret; | |
1428 | ||
f72b3435 MK |
1429 | /* If seqno wrap happened, omit the wait with no-ops */ |
1430 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1431 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1432 | intel_ring_emit(waiter, seqno); |
1433 | intel_ring_emit(waiter, 0); | |
1434 | intel_ring_emit(waiter, MI_NOOP); | |
1435 | } else { | |
1436 | intel_ring_emit(waiter, MI_NOOP); | |
1437 | intel_ring_emit(waiter, MI_NOOP); | |
1438 | intel_ring_emit(waiter, MI_NOOP); | |
1439 | intel_ring_emit(waiter, MI_NOOP); | |
1440 | } | |
c8c99b0f | 1441 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1442 | |
1443 | return 0; | |
1444 | } | |
1445 | ||
c6df541c CW |
1446 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1447 | do { \ | |
fcbc34e4 KG |
1448 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1449 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1450 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1451 | intel_ring_emit(ring__, 0); \ | |
1452 | intel_ring_emit(ring__, 0); \ | |
1453 | } while (0) | |
1454 | ||
1455 | static int | |
ee044a88 | 1456 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1457 | { |
ee044a88 | 1458 | struct intel_engine_cs *ring = req->ring; |
18393f63 | 1459 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1460 | int ret; |
1461 | ||
1462 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1463 | * incoherent with writes to memory, i.e. completely fubar, | |
1464 | * so we need to use PIPE_NOTIFY instead. | |
1465 | * | |
1466 | * However, we also need to workaround the qword write | |
1467 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1468 | * memory before requesting an interrupt. | |
1469 | */ | |
5fb9de1a | 1470 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1471 | if (ret) |
1472 | return ret; | |
1473 | ||
fcbc34e4 | 1474 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1475 | PIPE_CONTROL_WRITE_FLUSH | |
1476 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1477 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
ee044a88 | 1478 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); |
c6df541c CW |
1479 | intel_ring_emit(ring, 0); |
1480 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1481 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1482 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1483 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1484 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1485 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1486 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1487 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1488 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1489 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1490 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1491 | |
fcbc34e4 | 1492 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1493 | PIPE_CONTROL_WRITE_FLUSH | |
1494 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1495 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1496 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
ee044a88 | 1497 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); |
c6df541c | 1498 | intel_ring_emit(ring, 0); |
09246732 | 1499 | __intel_ring_advance(ring); |
c6df541c | 1500 | |
c6df541c CW |
1501 | return 0; |
1502 | } | |
1503 | ||
4cd53c0c | 1504 | static u32 |
a4872ba6 | 1505 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1506 | { |
4cd53c0c DV |
1507 | /* Workaround to force correct ordering between irq and seqno writes on |
1508 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1509 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1510 | if (!lazy_coherency) { |
1511 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1512 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1513 | } | |
1514 | ||
4cd53c0c DV |
1515 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1516 | } | |
1517 | ||
8187a2b7 | 1518 | static u32 |
a4872ba6 | 1519 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1520 | { |
1ec14ad3 CW |
1521 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1522 | } | |
1523 | ||
b70ec5bf | 1524 | static void |
a4872ba6 | 1525 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1526 | { |
1527 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1528 | } | |
1529 | ||
c6df541c | 1530 | static u32 |
a4872ba6 | 1531 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1532 | { |
0d1aacac | 1533 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1534 | } |
1535 | ||
b70ec5bf | 1536 | static void |
a4872ba6 | 1537 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1538 | { |
0d1aacac | 1539 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1540 | } |
1541 | ||
e48d8634 | 1542 | static bool |
a4872ba6 | 1543 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1544 | { |
1545 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1546 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1547 | unsigned long flags; |
e48d8634 | 1548 | |
7cd512f1 | 1549 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1550 | return false; |
1551 | ||
7338aefa | 1552 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1553 | if (ring->irq_refcount++ == 0) |
480c8033 | 1554 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1555 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1556 | |
1557 | return true; | |
1558 | } | |
1559 | ||
1560 | static void | |
a4872ba6 | 1561 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1562 | { |
1563 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1564 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1565 | unsigned long flags; |
e48d8634 | 1566 | |
7338aefa | 1567 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1568 | if (--ring->irq_refcount == 0) |
480c8033 | 1569 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1570 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1571 | } |
1572 | ||
b13c2b96 | 1573 | static bool |
a4872ba6 | 1574 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1575 | { |
78501eac | 1576 | struct drm_device *dev = ring->dev; |
4640c4ff | 1577 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1578 | unsigned long flags; |
62fdfeaf | 1579 | |
7cd512f1 | 1580 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1581 | return false; |
1582 | ||
7338aefa | 1583 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1584 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1585 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1586 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1587 | POSTING_READ(IMR); | |
1588 | } | |
7338aefa | 1589 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1590 | |
1591 | return true; | |
62fdfeaf EA |
1592 | } |
1593 | ||
8187a2b7 | 1594 | static void |
a4872ba6 | 1595 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1596 | { |
78501eac | 1597 | struct drm_device *dev = ring->dev; |
4640c4ff | 1598 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1599 | unsigned long flags; |
62fdfeaf | 1600 | |
7338aefa | 1601 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1602 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1603 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1604 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1605 | POSTING_READ(IMR); | |
1606 | } | |
7338aefa | 1607 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1608 | } |
1609 | ||
c2798b19 | 1610 | static bool |
a4872ba6 | 1611 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1612 | { |
1613 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1614 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1615 | unsigned long flags; |
c2798b19 | 1616 | |
7cd512f1 | 1617 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1618 | return false; |
1619 | ||
7338aefa | 1620 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1621 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1622 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1623 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1624 | POSTING_READ16(IMR); | |
1625 | } | |
7338aefa | 1626 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1627 | |
1628 | return true; | |
1629 | } | |
1630 | ||
1631 | static void | |
a4872ba6 | 1632 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1633 | { |
1634 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1635 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1636 | unsigned long flags; |
c2798b19 | 1637 | |
7338aefa | 1638 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1639 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1640 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1641 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1642 | POSTING_READ16(IMR); | |
1643 | } | |
7338aefa | 1644 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1645 | } |
1646 | ||
b72f3acb | 1647 | static int |
a84c3ae1 | 1648 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1649 | u32 invalidate_domains, |
1650 | u32 flush_domains) | |
d1b851fc | 1651 | { |
a84c3ae1 | 1652 | struct intel_engine_cs *ring = req->ring; |
b72f3acb CW |
1653 | int ret; |
1654 | ||
5fb9de1a | 1655 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1656 | if (ret) |
1657 | return ret; | |
1658 | ||
1659 | intel_ring_emit(ring, MI_FLUSH); | |
1660 | intel_ring_emit(ring, MI_NOOP); | |
1661 | intel_ring_advance(ring); | |
1662 | return 0; | |
d1b851fc ZN |
1663 | } |
1664 | ||
3cce469c | 1665 | static int |
ee044a88 | 1666 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1667 | { |
ee044a88 | 1668 | struct intel_engine_cs *ring = req->ring; |
3cce469c CW |
1669 | int ret; |
1670 | ||
5fb9de1a | 1671 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1672 | if (ret) |
1673 | return ret; | |
6f392d54 | 1674 | |
3cce469c CW |
1675 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1676 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
ee044a88 | 1677 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); |
3cce469c | 1678 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1679 | __intel_ring_advance(ring); |
d1b851fc | 1680 | |
3cce469c | 1681 | return 0; |
d1b851fc ZN |
1682 | } |
1683 | ||
0f46832f | 1684 | static bool |
a4872ba6 | 1685 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1686 | { |
1687 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1688 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1689 | unsigned long flags; |
0f46832f | 1690 | |
7cd512f1 DV |
1691 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1692 | return false; | |
0f46832f | 1693 | |
7338aefa | 1694 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1695 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1696 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1697 | I915_WRITE_IMR(ring, |
1698 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1699 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1700 | else |
1701 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1702 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1703 | } |
7338aefa | 1704 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1705 | |
1706 | return true; | |
1707 | } | |
1708 | ||
1709 | static void | |
a4872ba6 | 1710 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1711 | { |
1712 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1713 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1714 | unsigned long flags; |
0f46832f | 1715 | |
7338aefa | 1716 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1717 | if (--ring->irq_refcount == 0) { |
040d2baa | 1718 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1719 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1720 | else |
1721 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1722 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1723 | } |
7338aefa | 1724 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1725 | } |
1726 | ||
a19d2933 | 1727 | static bool |
a4872ba6 | 1728 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1729 | { |
1730 | struct drm_device *dev = ring->dev; | |
1731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1732 | unsigned long flags; | |
1733 | ||
7cd512f1 | 1734 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1735 | return false; |
1736 | ||
59cdb63d | 1737 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1738 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1739 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1740 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1741 | } |
59cdb63d | 1742 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1743 | |
1744 | return true; | |
1745 | } | |
1746 | ||
1747 | static void | |
a4872ba6 | 1748 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1749 | { |
1750 | struct drm_device *dev = ring->dev; | |
1751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1752 | unsigned long flags; | |
1753 | ||
59cdb63d | 1754 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1755 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1756 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1757 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1758 | } |
59cdb63d | 1759 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1760 | } |
1761 | ||
abd58f01 | 1762 | static bool |
a4872ba6 | 1763 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1764 | { |
1765 | struct drm_device *dev = ring->dev; | |
1766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1767 | unsigned long flags; | |
1768 | ||
7cd512f1 | 1769 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1770 | return false; |
1771 | ||
1772 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1773 | if (ring->irq_refcount++ == 0) { | |
1774 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1775 | I915_WRITE_IMR(ring, | |
1776 | ~(ring->irq_enable_mask | | |
1777 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1778 | } else { | |
1779 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1780 | } | |
1781 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1782 | } | |
1783 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1784 | ||
1785 | return true; | |
1786 | } | |
1787 | ||
1788 | static void | |
a4872ba6 | 1789 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1790 | { |
1791 | struct drm_device *dev = ring->dev; | |
1792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1793 | unsigned long flags; | |
1794 | ||
1795 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1796 | if (--ring->irq_refcount == 0) { | |
1797 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1798 | I915_WRITE_IMR(ring, | |
1799 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1800 | } else { | |
1801 | I915_WRITE_IMR(ring, ~0); | |
1802 | } | |
1803 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1804 | } | |
1805 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1806 | } | |
1807 | ||
d1b851fc | 1808 | static int |
53fddaf7 | 1809 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1810 | u64 offset, u32 length, |
8e004efc | 1811 | unsigned dispatch_flags) |
d1b851fc | 1812 | { |
53fddaf7 | 1813 | struct intel_engine_cs *ring = req->ring; |
e1f99ce6 | 1814 | int ret; |
78501eac | 1815 | |
5fb9de1a | 1816 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1817 | if (ret) |
1818 | return ret; | |
1819 | ||
78501eac | 1820 | intel_ring_emit(ring, |
65f56876 CW |
1821 | MI_BATCH_BUFFER_START | |
1822 | MI_BATCH_GTT | | |
8e004efc JH |
1823 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1824 | 0 : MI_BATCH_NON_SECURE_I965)); | |
c4e7a414 | 1825 | intel_ring_emit(ring, offset); |
78501eac CW |
1826 | intel_ring_advance(ring); |
1827 | ||
d1b851fc ZN |
1828 | return 0; |
1829 | } | |
1830 | ||
b45305fc DV |
1831 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1832 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1833 | #define I830_TLB_ENTRIES (2) |
1834 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1835 | static int |
53fddaf7 | 1836 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1837 | u64 offset, u32 len, |
1838 | unsigned dispatch_flags) | |
62fdfeaf | 1839 | { |
53fddaf7 | 1840 | struct intel_engine_cs *ring = req->ring; |
c4d69da1 | 1841 | u32 cs_offset = ring->scratch.gtt_offset; |
c4e7a414 | 1842 | int ret; |
62fdfeaf | 1843 | |
5fb9de1a | 1844 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1845 | if (ret) |
1846 | return ret; | |
62fdfeaf | 1847 | |
c4d69da1 CW |
1848 | /* Evict the invalid PTE TLBs */ |
1849 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); | |
1850 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1851 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1852 | intel_ring_emit(ring, cs_offset); | |
1853 | intel_ring_emit(ring, 0xdeadbeef); | |
1854 | intel_ring_emit(ring, MI_NOOP); | |
1855 | intel_ring_advance(ring); | |
b45305fc | 1856 | |
8e004efc | 1857 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1858 | if (len > I830_BATCH_LIMIT) |
1859 | return -ENOSPC; | |
1860 | ||
5fb9de1a | 1861 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1862 | if (ret) |
1863 | return ret; | |
c4d69da1 CW |
1864 | |
1865 | /* Blit the batch (which has now all relocs applied) to the | |
1866 | * stable batch scratch bo area (so that the CS never | |
1867 | * stumbles over its tlb invalidation bug) ... | |
1868 | */ | |
1869 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); | |
1870 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
611a7a4f | 1871 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
b45305fc | 1872 | intel_ring_emit(ring, cs_offset); |
b45305fc DV |
1873 | intel_ring_emit(ring, 4096); |
1874 | intel_ring_emit(ring, offset); | |
c4d69da1 | 1875 | |
b45305fc | 1876 | intel_ring_emit(ring, MI_FLUSH); |
c4d69da1 CW |
1877 | intel_ring_emit(ring, MI_NOOP); |
1878 | intel_ring_advance(ring); | |
b45305fc DV |
1879 | |
1880 | /* ... and execute it. */ | |
c4d69da1 | 1881 | offset = cs_offset; |
b45305fc | 1882 | } |
e1f99ce6 | 1883 | |
5fb9de1a | 1884 | ret = intel_ring_begin(req, 4); |
c4d69da1 CW |
1885 | if (ret) |
1886 | return ret; | |
1887 | ||
1888 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
8e004efc JH |
1889 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
1890 | 0 : MI_BATCH_NON_SECURE)); | |
c4d69da1 CW |
1891 | intel_ring_emit(ring, offset + len - 8); |
1892 | intel_ring_emit(ring, MI_NOOP); | |
1893 | intel_ring_advance(ring); | |
1894 | ||
fb3256da DV |
1895 | return 0; |
1896 | } | |
1897 | ||
1898 | static int | |
53fddaf7 | 1899 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1900 | u64 offset, u32 len, |
8e004efc | 1901 | unsigned dispatch_flags) |
fb3256da | 1902 | { |
53fddaf7 | 1903 | struct intel_engine_cs *ring = req->ring; |
fb3256da DV |
1904 | int ret; |
1905 | ||
5fb9de1a | 1906 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1907 | if (ret) |
1908 | return ret; | |
1909 | ||
65f56876 | 1910 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
8e004efc JH |
1911 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
1912 | 0 : MI_BATCH_NON_SECURE)); | |
c4e7a414 | 1913 | intel_ring_advance(ring); |
62fdfeaf | 1914 | |
62fdfeaf EA |
1915 | return 0; |
1916 | } | |
1917 | ||
a4872ba6 | 1918 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1919 | { |
05394f39 | 1920 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1921 | |
8187a2b7 ZN |
1922 | obj = ring->status_page.obj; |
1923 | if (obj == NULL) | |
62fdfeaf | 1924 | return; |
62fdfeaf | 1925 | |
9da3da66 | 1926 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1927 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1928 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1929 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1930 | } |
1931 | ||
a4872ba6 | 1932 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1933 | { |
05394f39 | 1934 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1935 | |
e3efda49 | 1936 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1937 | unsigned flags; |
e3efda49 | 1938 | int ret; |
e4ffd173 | 1939 | |
e3efda49 CW |
1940 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1941 | if (obj == NULL) { | |
1942 | DRM_ERROR("Failed to allocate status page\n"); | |
1943 | return -ENOMEM; | |
1944 | } | |
62fdfeaf | 1945 | |
e3efda49 CW |
1946 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1947 | if (ret) | |
1948 | goto err_unref; | |
1949 | ||
1f767e02 CW |
1950 | flags = 0; |
1951 | if (!HAS_LLC(ring->dev)) | |
1952 | /* On g33, we cannot place HWS above 256MiB, so | |
1953 | * restrict its pinning to the low mappable arena. | |
1954 | * Though this restriction is not documented for | |
1955 | * gen4, gen5, or byt, they also behave similarly | |
1956 | * and hang if the HWS is placed at the top of the | |
1957 | * GTT. To generalise, it appears that all !llc | |
1958 | * platforms have issues with us placing the HWS | |
1959 | * above the mappable region (even though we never | |
1960 | * actualy map it). | |
1961 | */ | |
1962 | flags |= PIN_MAPPABLE; | |
1963 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1964 | if (ret) { |
1965 | err_unref: | |
1966 | drm_gem_object_unreference(&obj->base); | |
1967 | return ret; | |
1968 | } | |
1969 | ||
1970 | ring->status_page.obj = obj; | |
1971 | } | |
62fdfeaf | 1972 | |
f343c5f6 | 1973 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1974 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1975 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1976 | |
8187a2b7 ZN |
1977 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1978 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1979 | |
1980 | return 0; | |
62fdfeaf EA |
1981 | } |
1982 | ||
a4872ba6 | 1983 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1984 | { |
1985 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1986 | |
1987 | if (!dev_priv->status_page_dmah) { | |
1988 | dev_priv->status_page_dmah = | |
1989 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1990 | if (!dev_priv->status_page_dmah) | |
1991 | return -ENOMEM; | |
1992 | } | |
1993 | ||
6b8294a4 CW |
1994 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1995 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
7ba717cf | 2000 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2001 | { |
def0c5f6 CW |
2002 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
2003 | vunmap(ringbuf->virtual_start); | |
2004 | else | |
2005 | iounmap(ringbuf->virtual_start); | |
7ba717cf | 2006 | ringbuf->virtual_start = NULL; |
2919d291 | 2007 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
2008 | } |
2009 | ||
def0c5f6 CW |
2010 | static u32 *vmap_obj(struct drm_i915_gem_object *obj) |
2011 | { | |
2012 | struct sg_page_iter sg_iter; | |
2013 | struct page **pages; | |
2014 | void *addr; | |
2015 | int i; | |
2016 | ||
2017 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); | |
2018 | if (pages == NULL) | |
2019 | return NULL; | |
2020 | ||
2021 | i = 0; | |
2022 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) | |
2023 | pages[i++] = sg_page_iter_page(&sg_iter); | |
2024 | ||
2025 | addr = vmap(pages, i, 0, PAGE_KERNEL); | |
2026 | drm_free_large(pages); | |
2027 | ||
2028 | return addr; | |
2029 | } | |
2030 | ||
7ba717cf TD |
2031 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
2032 | struct intel_ringbuffer *ringbuf) | |
2033 | { | |
2034 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2035 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
2036 | int ret; | |
2037 | ||
def0c5f6 CW |
2038 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
2039 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0); | |
2040 | if (ret) | |
2041 | return ret; | |
7ba717cf | 2042 | |
def0c5f6 CW |
2043 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
2044 | if (ret) { | |
2045 | i915_gem_object_ggtt_unpin(obj); | |
2046 | return ret; | |
2047 | } | |
2048 | ||
2049 | ringbuf->virtual_start = vmap_obj(obj); | |
2050 | if (ringbuf->virtual_start == NULL) { | |
2051 | i915_gem_object_ggtt_unpin(obj); | |
2052 | return -ENOMEM; | |
2053 | } | |
2054 | } else { | |
2055 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
2056 | if (ret) | |
2057 | return ret; | |
7ba717cf | 2058 | |
def0c5f6 CW |
2059 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
2060 | if (ret) { | |
2061 | i915_gem_object_ggtt_unpin(obj); | |
2062 | return ret; | |
2063 | } | |
2064 | ||
2065 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + | |
2066 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
2067 | if (ringbuf->virtual_start == NULL) { | |
2068 | i915_gem_object_ggtt_unpin(obj); | |
2069 | return -EINVAL; | |
2070 | } | |
7ba717cf TD |
2071 | } |
2072 | ||
2073 | return 0; | |
2074 | } | |
2075 | ||
01101fa7 | 2076 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2077 | { |
2919d291 OM |
2078 | drm_gem_object_unreference(&ringbuf->obj->base); |
2079 | ringbuf->obj = NULL; | |
2080 | } | |
2081 | ||
01101fa7 CW |
2082 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2083 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2084 | { |
05394f39 | 2085 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2086 | |
ebc052e0 CW |
2087 | obj = NULL; |
2088 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2089 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2090 | if (obj == NULL) |
93b0a4e0 | 2091 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
2092 | if (obj == NULL) |
2093 | return -ENOMEM; | |
8187a2b7 | 2094 | |
24f3a8cf AG |
2095 | /* mark ring buffers as read-only from GPU side by default */ |
2096 | obj->gt_ro = 1; | |
2097 | ||
93b0a4e0 | 2098 | ringbuf->obj = obj; |
e3efda49 | 2099 | |
7ba717cf | 2100 | return 0; |
e3efda49 CW |
2101 | } |
2102 | ||
01101fa7 CW |
2103 | struct intel_ringbuffer * |
2104 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2105 | { | |
2106 | struct intel_ringbuffer *ring; | |
2107 | int ret; | |
2108 | ||
2109 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2110 | if (ring == NULL) { |
2111 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2112 | engine->name); | |
01101fa7 | 2113 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2114 | } |
01101fa7 CW |
2115 | |
2116 | ring->ring = engine; | |
608c1a52 | 2117 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2118 | |
2119 | ring->size = size; | |
2120 | /* Workaround an erratum on the i830 which causes a hang if | |
2121 | * the TAIL pointer points to within the last 2 cachelines | |
2122 | * of the buffer. | |
2123 | */ | |
2124 | ring->effective_size = size; | |
2125 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2126 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2127 | ||
2128 | ring->last_retired_head = -1; | |
2129 | intel_ring_update_space(ring); | |
2130 | ||
2131 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2132 | if (ret) { | |
608c1a52 CW |
2133 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2134 | engine->name, ret); | |
2135 | list_del(&ring->link); | |
01101fa7 CW |
2136 | kfree(ring); |
2137 | return ERR_PTR(ret); | |
2138 | } | |
2139 | ||
2140 | return ring; | |
2141 | } | |
2142 | ||
2143 | void | |
2144 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2145 | { | |
2146 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2147 | list_del(&ring->link); |
01101fa7 CW |
2148 | kfree(ring); |
2149 | } | |
2150 | ||
e3efda49 | 2151 | static int intel_init_ring_buffer(struct drm_device *dev, |
a4872ba6 | 2152 | struct intel_engine_cs *ring) |
e3efda49 | 2153 | { |
bfc882b4 | 2154 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2155 | int ret; |
2156 | ||
bfc882b4 DV |
2157 | WARN_ON(ring->buffer); |
2158 | ||
e3efda49 CW |
2159 | ring->dev = dev; |
2160 | INIT_LIST_HEAD(&ring->active_list); | |
2161 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 2162 | INIT_LIST_HEAD(&ring->execlist_queue); |
608c1a52 | 2163 | INIT_LIST_HEAD(&ring->buffers); |
06fbca71 | 2164 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
ebc348b2 | 2165 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
2166 | |
2167 | init_waitqueue_head(&ring->irq_queue); | |
2168 | ||
01101fa7 CW |
2169 | ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE); |
2170 | if (IS_ERR(ringbuf)) | |
2171 | return PTR_ERR(ringbuf); | |
2172 | ring->buffer = ringbuf; | |
2173 | ||
e3efda49 CW |
2174 | if (I915_NEED_GFX_HWS(dev)) { |
2175 | ret = init_status_page(ring); | |
2176 | if (ret) | |
8ee14975 | 2177 | goto error; |
e3efda49 CW |
2178 | } else { |
2179 | BUG_ON(ring->id != RCS); | |
2180 | ret = init_phys_status_page(ring); | |
2181 | if (ret) | |
8ee14975 | 2182 | goto error; |
e3efda49 CW |
2183 | } |
2184 | ||
bfc882b4 DV |
2185 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2186 | if (ret) { | |
2187 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
2188 | ring->name, ret); | |
2189 | intel_destroy_ringbuffer_obj(ringbuf); | |
2190 | goto error; | |
e3efda49 | 2191 | } |
62fdfeaf | 2192 | |
44e895a8 BV |
2193 | ret = i915_cmd_parser_init_ring(ring); |
2194 | if (ret) | |
8ee14975 OM |
2195 | goto error; |
2196 | ||
8ee14975 | 2197 | return 0; |
351e3db2 | 2198 | |
8ee14975 | 2199 | error: |
01101fa7 | 2200 | intel_ringbuffer_free(ringbuf); |
8ee14975 OM |
2201 | ring->buffer = NULL; |
2202 | return ret; | |
62fdfeaf EA |
2203 | } |
2204 | ||
a4872ba6 | 2205 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 2206 | { |
6402c330 | 2207 | struct drm_i915_private *dev_priv; |
33626e6a | 2208 | |
93b0a4e0 | 2209 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
2210 | return; |
2211 | ||
6402c330 | 2212 | dev_priv = to_i915(ring->dev); |
6402c330 | 2213 | |
e3efda49 | 2214 | intel_stop_ring_buffer(ring); |
de8f0a50 | 2215 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 2216 | |
01101fa7 CW |
2217 | intel_unpin_ringbuffer_obj(ring->buffer); |
2218 | intel_ringbuffer_free(ring->buffer); | |
2219 | ring->buffer = NULL; | |
78501eac | 2220 | |
8d19215b ZN |
2221 | if (ring->cleanup) |
2222 | ring->cleanup(ring); | |
2223 | ||
78501eac | 2224 | cleanup_status_page(ring); |
44e895a8 BV |
2225 | |
2226 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 2227 | i915_gem_batch_pool_fini(&ring->batch_pool); |
62fdfeaf EA |
2228 | } |
2229 | ||
595e1eeb | 2230 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
a71d8d94 | 2231 | { |
93b0a4e0 | 2232 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 2233 | struct drm_i915_gem_request *request; |
b4716185 CW |
2234 | unsigned space; |
2235 | int ret; | |
a71d8d94 | 2236 | |
ebd0fd4b DG |
2237 | if (intel_ring_space(ringbuf) >= n) |
2238 | return 0; | |
a71d8d94 | 2239 | |
79bbcc29 JH |
2240 | /* The whole point of reserving space is to not wait! */ |
2241 | WARN_ON(ringbuf->reserved_in_use); | |
2242 | ||
a71d8d94 | 2243 | list_for_each_entry(request, &ring->request_list, list) { |
b4716185 CW |
2244 | space = __intel_ring_space(request->postfix, ringbuf->tail, |
2245 | ringbuf->size); | |
2246 | if (space >= n) | |
a71d8d94 | 2247 | break; |
a71d8d94 CW |
2248 | } |
2249 | ||
595e1eeb | 2250 | if (WARN_ON(&request->list == &ring->request_list)) |
a71d8d94 CW |
2251 | return -ENOSPC; |
2252 | ||
a4b3a571 | 2253 | ret = i915_wait_request(request); |
a71d8d94 CW |
2254 | if (ret) |
2255 | return ret; | |
2256 | ||
b4716185 | 2257 | ringbuf->space = space; |
a71d8d94 CW |
2258 | return 0; |
2259 | } | |
2260 | ||
79bbcc29 | 2261 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
3e960501 CW |
2262 | { |
2263 | uint32_t __iomem *virt; | |
93b0a4e0 | 2264 | int rem = ringbuf->size - ringbuf->tail; |
3e960501 | 2265 | |
93b0a4e0 | 2266 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
2267 | rem /= 4; |
2268 | while (rem--) | |
2269 | iowrite32(MI_NOOP, virt++); | |
2270 | ||
93b0a4e0 | 2271 | ringbuf->tail = 0; |
ebd0fd4b | 2272 | intel_ring_update_space(ringbuf); |
3e960501 CW |
2273 | } |
2274 | ||
a4872ba6 | 2275 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 | 2276 | { |
a4b3a571 | 2277 | struct drm_i915_gem_request *req; |
3e960501 | 2278 | |
3e960501 CW |
2279 | /* Wait upon the last request to be completed */ |
2280 | if (list_empty(&ring->request_list)) | |
2281 | return 0; | |
2282 | ||
a4b3a571 | 2283 | req = list_entry(ring->request_list.prev, |
b4716185 CW |
2284 | struct drm_i915_gem_request, |
2285 | list); | |
2286 | ||
2287 | /* Make sure we do not trigger any retires */ | |
2288 | return __i915_wait_request(req, | |
2289 | atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter), | |
2290 | to_i915(ring->dev)->mm.interruptible, | |
2291 | NULL, NULL); | |
3e960501 CW |
2292 | } |
2293 | ||
6689cb2b | 2294 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2295 | { |
6689cb2b | 2296 | request->ringbuf = request->ring->buffer; |
9eba5d4a | 2297 | return 0; |
9d773091 CW |
2298 | } |
2299 | ||
ccd98fe4 JH |
2300 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
2301 | { | |
2302 | /* | |
2303 | * The first call merely notes the reserve request and is common for | |
2304 | * all back ends. The subsequent localised _begin() call actually | |
2305 | * ensures that the reservation is available. Without the begin, if | |
2306 | * the request creator immediately submitted the request without | |
2307 | * adding any commands to it then there might not actually be | |
2308 | * sufficient room for the submission commands. | |
2309 | */ | |
2310 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
2311 | ||
2312 | return intel_ring_begin(request, 0); | |
2313 | } | |
2314 | ||
29b1b415 JH |
2315 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
2316 | { | |
ccd98fe4 | 2317 | WARN_ON(ringbuf->reserved_size); |
29b1b415 JH |
2318 | WARN_ON(ringbuf->reserved_in_use); |
2319 | ||
2320 | ringbuf->reserved_size = size; | |
29b1b415 JH |
2321 | } |
2322 | ||
2323 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) | |
2324 | { | |
2325 | WARN_ON(ringbuf->reserved_in_use); | |
2326 | ||
2327 | ringbuf->reserved_size = 0; | |
2328 | ringbuf->reserved_in_use = false; | |
2329 | } | |
2330 | ||
2331 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) | |
2332 | { | |
2333 | WARN_ON(ringbuf->reserved_in_use); | |
2334 | ||
2335 | ringbuf->reserved_in_use = true; | |
2336 | ringbuf->reserved_tail = ringbuf->tail; | |
2337 | } | |
2338 | ||
2339 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) | |
2340 | { | |
2341 | WARN_ON(!ringbuf->reserved_in_use); | |
79bbcc29 JH |
2342 | if (ringbuf->tail > ringbuf->reserved_tail) { |
2343 | WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size, | |
2344 | "request reserved size too small: %d vs %d!\n", | |
2345 | ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size); | |
2346 | } else { | |
2347 | /* | |
2348 | * The ring was wrapped while the reserved space was in use. | |
2349 | * That means that some unknown amount of the ring tail was | |
2350 | * no-op filled and skipped. Thus simply adding the ring size | |
2351 | * to the tail and doing the above space check will not work. | |
2352 | * Rather than attempt to track how much tail was skipped, | |
2353 | * it is much simpler to say that also skipping the sanity | |
2354 | * check every once in a while is not a big issue. | |
2355 | */ | |
2356 | } | |
29b1b415 JH |
2357 | |
2358 | ringbuf->reserved_size = 0; | |
2359 | ringbuf->reserved_in_use = false; | |
2360 | } | |
2361 | ||
2362 | static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes) | |
cbcc80df | 2363 | { |
93b0a4e0 | 2364 | struct intel_ringbuffer *ringbuf = ring->buffer; |
79bbcc29 JH |
2365 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2366 | int remain_actual = ringbuf->size - ringbuf->tail; | |
2367 | int ret, total_bytes, wait_bytes = 0; | |
2368 | bool need_wrap = false; | |
29b1b415 | 2369 | |
79bbcc29 JH |
2370 | if (ringbuf->reserved_in_use) |
2371 | total_bytes = bytes; | |
2372 | else | |
2373 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 2374 | |
79bbcc29 JH |
2375 | if (unlikely(bytes > remain_usable)) { |
2376 | /* | |
2377 | * Not enough space for the basic request. So need to flush | |
2378 | * out the remainder and then wait for base + reserved. | |
2379 | */ | |
2380 | wait_bytes = remain_actual + total_bytes; | |
2381 | need_wrap = true; | |
2382 | } else { | |
2383 | if (unlikely(total_bytes > remain_usable)) { | |
2384 | /* | |
2385 | * The base request will fit but the reserved space | |
2386 | * falls off the end. So only need to to wait for the | |
2387 | * reserved size after flushing out the remainder. | |
2388 | */ | |
2389 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
2390 | need_wrap = true; | |
2391 | } else if (total_bytes > ringbuf->space) { | |
2392 | /* No wrapping required, just waiting. */ | |
2393 | wait_bytes = total_bytes; | |
29b1b415 | 2394 | } |
cbcc80df MK |
2395 | } |
2396 | ||
79bbcc29 JH |
2397 | if (wait_bytes) { |
2398 | ret = ring_wait_for_space(ring, wait_bytes); | |
cbcc80df MK |
2399 | if (unlikely(ret)) |
2400 | return ret; | |
79bbcc29 JH |
2401 | |
2402 | if (need_wrap) | |
2403 | __wrap_ring_buffer(ringbuf); | |
cbcc80df MK |
2404 | } |
2405 | ||
cbcc80df MK |
2406 | return 0; |
2407 | } | |
2408 | ||
5fb9de1a | 2409 | int intel_ring_begin(struct drm_i915_gem_request *req, |
e1f99ce6 | 2410 | int num_dwords) |
8187a2b7 | 2411 | { |
5fb9de1a JH |
2412 | struct intel_engine_cs *ring; |
2413 | struct drm_i915_private *dev_priv; | |
e1f99ce6 | 2414 | int ret; |
78501eac | 2415 | |
5fb9de1a JH |
2416 | WARN_ON(req == NULL); |
2417 | ring = req->ring; | |
2418 | dev_priv = ring->dev->dev_private; | |
2419 | ||
33196ded DV |
2420 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2421 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2422 | if (ret) |
2423 | return ret; | |
21dd3734 | 2424 | |
304d695c CW |
2425 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2426 | if (ret) | |
2427 | return ret; | |
2428 | ||
ee1b1e5e | 2429 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2430 | return 0; |
8187a2b7 | 2431 | } |
78501eac | 2432 | |
753b1ad4 | 2433 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2434 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2435 | { |
bba09b12 | 2436 | struct intel_engine_cs *ring = req->ring; |
ee1b1e5e | 2437 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2438 | int ret; |
2439 | ||
2440 | if (num_dwords == 0) | |
2441 | return 0; | |
2442 | ||
18393f63 | 2443 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2444 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2445 | if (ret) |
2446 | return ret; | |
2447 | ||
2448 | while (num_dwords--) | |
2449 | intel_ring_emit(ring, MI_NOOP); | |
2450 | ||
2451 | intel_ring_advance(ring); | |
2452 | ||
2453 | return 0; | |
2454 | } | |
2455 | ||
a4872ba6 | 2456 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2457 | { |
3b2cc8ab OM |
2458 | struct drm_device *dev = ring->dev; |
2459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2460 | |
3b2cc8ab | 2461 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2462 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2463 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2464 | if (HAS_VEBOX(dev)) |
5020150b | 2465 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2466 | } |
d97ed339 | 2467 | |
f7e98ad4 | 2468 | ring->set_seqno(ring, seqno); |
92cab734 | 2469 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2470 | } |
62fdfeaf | 2471 | |
a4872ba6 | 2472 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2473 | u32 value) |
881f47b6 | 2474 | { |
4640c4ff | 2475 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2476 | |
2477 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2478 | |
2479 | /* Disable notification that the ring is IDLE. The GT | |
2480 | * will then assume that it is busy and bring it out of rc6. | |
2481 | */ | |
0206e353 | 2482 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2483 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2484 | ||
2485 | /* Clear the context id. Here be magic! */ | |
2486 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2487 | |
12f55818 | 2488 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2489 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2490 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2491 | 50)) | |
2492 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2493 | |
12f55818 | 2494 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2495 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2496 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2497 | ||
2498 | /* Let the ring send IDLE messages to the GT again, | |
2499 | * and so let it sleep to conserve power when idle. | |
2500 | */ | |
0206e353 | 2501 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2502 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2503 | } |
2504 | ||
a84c3ae1 | 2505 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2506 | u32 invalidate, u32 flush) |
881f47b6 | 2507 | { |
a84c3ae1 | 2508 | struct intel_engine_cs *ring = req->ring; |
71a77e07 | 2509 | uint32_t cmd; |
b72f3acb CW |
2510 | int ret; |
2511 | ||
5fb9de1a | 2512 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2513 | if (ret) |
2514 | return ret; | |
2515 | ||
71a77e07 | 2516 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2517 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2518 | cmd += 1; | |
f0a1fb10 CW |
2519 | |
2520 | /* We always require a command barrier so that subsequent | |
2521 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2522 | * wrt the contents of the write cache being flushed to memory | |
2523 | * (and thus being coherent from the CPU). | |
2524 | */ | |
2525 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2526 | ||
9a289771 JB |
2527 | /* |
2528 | * Bspec vol 1c.5 - video engine command streamer: | |
2529 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2530 | * operation is complete. This bit is only valid when the | |
2531 | * Post-Sync Operation field is a value of 1h or 3h." | |
2532 | */ | |
71a77e07 | 2533 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2534 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2535 | ||
71a77e07 | 2536 | intel_ring_emit(ring, cmd); |
9a289771 | 2537 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2538 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2539 | intel_ring_emit(ring, 0); /* upper addr */ | |
2540 | intel_ring_emit(ring, 0); /* value */ | |
2541 | } else { | |
2542 | intel_ring_emit(ring, 0); | |
2543 | intel_ring_emit(ring, MI_NOOP); | |
2544 | } | |
b72f3acb CW |
2545 | intel_ring_advance(ring); |
2546 | return 0; | |
881f47b6 XH |
2547 | } |
2548 | ||
1c7a0623 | 2549 | static int |
53fddaf7 | 2550 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2551 | u64 offset, u32 len, |
8e004efc | 2552 | unsigned dispatch_flags) |
1c7a0623 | 2553 | { |
53fddaf7 | 2554 | struct intel_engine_cs *ring = req->ring; |
8e004efc JH |
2555 | bool ppgtt = USES_PPGTT(ring->dev) && |
2556 | !(dispatch_flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
2557 | int ret; |
2558 | ||
5fb9de1a | 2559 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2560 | if (ret) |
2561 | return ret; | |
2562 | ||
2563 | /* FIXME(BDW): Address space and security selectors. */ | |
919032ec AJ |
2564 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
2565 | (dispatch_flags & I915_DISPATCH_RS ? | |
2566 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
9bcb144c BW |
2567 | intel_ring_emit(ring, lower_32_bits(offset)); |
2568 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2569 | intel_ring_emit(ring, MI_NOOP); |
2570 | intel_ring_advance(ring); | |
2571 | ||
2572 | return 0; | |
2573 | } | |
2574 | ||
d7d4eedd | 2575 | static int |
53fddaf7 | 2576 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2577 | u64 offset, u32 len, |
2578 | unsigned dispatch_flags) | |
d7d4eedd | 2579 | { |
53fddaf7 | 2580 | struct intel_engine_cs *ring = req->ring; |
d7d4eedd CW |
2581 | int ret; |
2582 | ||
5fb9de1a | 2583 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2584 | if (ret) |
2585 | return ret; | |
2586 | ||
2587 | intel_ring_emit(ring, | |
77072258 | 2588 | MI_BATCH_BUFFER_START | |
8e004efc | 2589 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2590 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2591 | (dispatch_flags & I915_DISPATCH_RS ? | |
2592 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd CW |
2593 | /* bit0-7 is the length on GEN6+ */ |
2594 | intel_ring_emit(ring, offset); | |
2595 | intel_ring_advance(ring); | |
2596 | ||
2597 | return 0; | |
2598 | } | |
2599 | ||
881f47b6 | 2600 | static int |
53fddaf7 | 2601 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2602 | u64 offset, u32 len, |
8e004efc | 2603 | unsigned dispatch_flags) |
881f47b6 | 2604 | { |
53fddaf7 | 2605 | struct intel_engine_cs *ring = req->ring; |
0206e353 | 2606 | int ret; |
ab6f8e32 | 2607 | |
5fb9de1a | 2608 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2609 | if (ret) |
2610 | return ret; | |
e1f99ce6 | 2611 | |
d7d4eedd CW |
2612 | intel_ring_emit(ring, |
2613 | MI_BATCH_BUFFER_START | | |
8e004efc JH |
2614 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2615 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2616 | /* bit0-7 is the length on GEN6+ */ |
2617 | intel_ring_emit(ring, offset); | |
2618 | intel_ring_advance(ring); | |
ab6f8e32 | 2619 | |
0206e353 | 2620 | return 0; |
881f47b6 XH |
2621 | } |
2622 | ||
549f7365 CW |
2623 | /* Blitter support (SandyBridge+) */ |
2624 | ||
a84c3ae1 | 2625 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2626 | u32 invalidate, u32 flush) |
8d19215b | 2627 | { |
a84c3ae1 | 2628 | struct intel_engine_cs *ring = req->ring; |
fd3da6c9 | 2629 | struct drm_device *dev = ring->dev; |
71a77e07 | 2630 | uint32_t cmd; |
b72f3acb CW |
2631 | int ret; |
2632 | ||
5fb9de1a | 2633 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2634 | if (ret) |
2635 | return ret; | |
2636 | ||
71a77e07 | 2637 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2638 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2639 | cmd += 1; |
f0a1fb10 CW |
2640 | |
2641 | /* We always require a command barrier so that subsequent | |
2642 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2643 | * wrt the contents of the write cache being flushed to memory | |
2644 | * (and thus being coherent from the CPU). | |
2645 | */ | |
2646 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2647 | ||
9a289771 JB |
2648 | /* |
2649 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2650 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2651 | * operation is complete. This bit is only valid when the | |
2652 | * Post-Sync Operation field is a value of 1h or 3h." | |
2653 | */ | |
71a77e07 | 2654 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2655 | cmd |= MI_INVALIDATE_TLB; |
71a77e07 | 2656 | intel_ring_emit(ring, cmd); |
9a289771 | 2657 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
dbef0f15 | 2658 | if (INTEL_INFO(dev)->gen >= 8) { |
075b3bba BW |
2659 | intel_ring_emit(ring, 0); /* upper addr */ |
2660 | intel_ring_emit(ring, 0); /* value */ | |
2661 | } else { | |
2662 | intel_ring_emit(ring, 0); | |
2663 | intel_ring_emit(ring, MI_NOOP); | |
2664 | } | |
b72f3acb | 2665 | intel_ring_advance(ring); |
fd3da6c9 | 2666 | |
b72f3acb | 2667 | return 0; |
8d19215b ZN |
2668 | } |
2669 | ||
5c1143bb XH |
2670 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2671 | { | |
4640c4ff | 2672 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2673 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2674 | struct drm_i915_gem_object *obj; |
2675 | int ret; | |
5c1143bb | 2676 | |
59465b5f DV |
2677 | ring->name = "render ring"; |
2678 | ring->id = RCS; | |
2679 | ring->mmio_base = RENDER_RING_BASE; | |
2680 | ||
707d9cf9 | 2681 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2682 | if (i915_semaphore_is_enabled(dev)) { |
2683 | obj = i915_gem_alloc_object(dev, 4096); | |
2684 | if (obj == NULL) { | |
2685 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2686 | i915.semaphores = 0; | |
2687 | } else { | |
2688 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2689 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2690 | if (ret != 0) { | |
2691 | drm_gem_object_unreference(&obj->base); | |
2692 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2693 | i915.semaphores = 0; | |
2694 | } else | |
2695 | dev_priv->semaphore_obj = obj; | |
2696 | } | |
2697 | } | |
7225342a | 2698 | |
8f0e2b9d | 2699 | ring->init_context = intel_rcs_ctx_init; |
707d9cf9 BW |
2700 | ring->add_request = gen6_add_request; |
2701 | ring->flush = gen8_render_ring_flush; | |
2702 | ring->irq_get = gen8_ring_get_irq; | |
2703 | ring->irq_put = gen8_ring_put_irq; | |
2704 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2705 | ring->get_seqno = gen6_ring_get_seqno; | |
2706 | ring->set_seqno = ring_set_seqno; | |
2707 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2708 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2709 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2710 | ring->semaphore.signal = gen8_rcs_signal; |
2711 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2712 | } |
2713 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
4f91fc6d | 2714 | ring->init_context = intel_rcs_ctx_init; |
1ec14ad3 | 2715 | ring->add_request = gen6_add_request; |
4772eaeb | 2716 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2717 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2718 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2719 | ring->irq_get = gen6_ring_get_irq; |
2720 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2721 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2722 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2723 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2724 | if (i915_semaphore_is_enabled(dev)) { |
2725 | ring->semaphore.sync_to = gen6_ring_sync; | |
2726 | ring->semaphore.signal = gen6_signal; | |
2727 | /* | |
2728 | * The current semaphore is only applied on pre-gen8 | |
2729 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2730 | * platform. So the semaphore between RCS and VCS2 is | |
2731 | * initialized as INVALID. Gen8 will initialize the | |
2732 | * sema between VCS2 and RCS later. | |
2733 | */ | |
2734 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2735 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2736 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2737 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2738 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2739 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2740 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2741 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2742 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2743 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2744 | } | |
c6df541c CW |
2745 | } else if (IS_GEN5(dev)) { |
2746 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2747 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2748 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2749 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2750 | ring->irq_get = gen5_ring_get_irq; |
2751 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2752 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2753 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2754 | } else { |
8620a3a9 | 2755 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2756 | if (INTEL_INFO(dev)->gen < 4) |
2757 | ring->flush = gen2_render_ring_flush; | |
2758 | else | |
2759 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2760 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2761 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2762 | if (IS_GEN2(dev)) { |
2763 | ring->irq_get = i8xx_ring_get_irq; | |
2764 | ring->irq_put = i8xx_ring_put_irq; | |
2765 | } else { | |
2766 | ring->irq_get = i9xx_ring_get_irq; | |
2767 | ring->irq_put = i9xx_ring_put_irq; | |
2768 | } | |
e3670319 | 2769 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2770 | } |
59465b5f | 2771 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2772 | |
d7d4eedd CW |
2773 | if (IS_HASWELL(dev)) |
2774 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2775 | else if (IS_GEN8(dev)) |
2776 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2777 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2778 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2779 | else if (INTEL_INFO(dev)->gen >= 4) | |
2780 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2781 | else if (IS_I830(dev) || IS_845G(dev)) | |
2782 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2783 | else | |
2784 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
ecfe00d8 | 2785 | ring->init_hw = init_render_ring; |
59465b5f DV |
2786 | ring->cleanup = render_ring_cleanup; |
2787 | ||
b45305fc DV |
2788 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2789 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2790 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2791 | if (obj == NULL) { |
2792 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2793 | return -ENOMEM; | |
2794 | } | |
2795 | ||
be1fa129 | 2796 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2797 | if (ret != 0) { |
2798 | drm_gem_object_unreference(&obj->base); | |
2799 | DRM_ERROR("Failed to ping batch bo\n"); | |
2800 | return ret; | |
2801 | } | |
2802 | ||
0d1aacac CW |
2803 | ring->scratch.obj = obj; |
2804 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2805 | } |
2806 | ||
99be1dfe DV |
2807 | ret = intel_init_ring_buffer(dev, ring); |
2808 | if (ret) | |
2809 | return ret; | |
2810 | ||
2811 | if (INTEL_INFO(dev)->gen >= 5) { | |
2812 | ret = intel_init_pipe_control(ring); | |
2813 | if (ret) | |
2814 | return ret; | |
2815 | } | |
2816 | ||
2817 | return 0; | |
5c1143bb XH |
2818 | } |
2819 | ||
2820 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2821 | { | |
4640c4ff | 2822 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2823 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2824 | |
58fa3835 DV |
2825 | ring->name = "bsd ring"; |
2826 | ring->id = VCS; | |
2827 | ||
0fd2c201 | 2828 | ring->write_tail = ring_write_tail; |
780f18c8 | 2829 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2830 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2831 | /* gen6 bsd needs a special wa for tail updates */ |
2832 | if (IS_GEN6(dev)) | |
2833 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2834 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2835 | ring->add_request = gen6_add_request; |
2836 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2837 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2838 | if (INTEL_INFO(dev)->gen >= 8) { |
2839 | ring->irq_enable_mask = | |
2840 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2841 | ring->irq_get = gen8_ring_get_irq; | |
2842 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2843 | ring->dispatch_execbuffer = |
2844 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2845 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2846 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2847 | ring->semaphore.signal = gen8_xcs_signal; |
2848 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2849 | } |
abd58f01 BW |
2850 | } else { |
2851 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2852 | ring->irq_get = gen6_ring_get_irq; | |
2853 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2854 | ring->dispatch_execbuffer = |
2855 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2856 | if (i915_semaphore_is_enabled(dev)) { |
2857 | ring->semaphore.sync_to = gen6_ring_sync; | |
2858 | ring->semaphore.signal = gen6_signal; | |
2859 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2860 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2861 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2862 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2863 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2864 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2865 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2866 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2867 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2868 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2869 | } | |
abd58f01 | 2870 | } |
58fa3835 DV |
2871 | } else { |
2872 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2873 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2874 | ring->add_request = i9xx_add_request; |
58fa3835 | 2875 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2876 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2877 | if (IS_GEN5(dev)) { |
cc609d5d | 2878 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2879 | ring->irq_get = gen5_ring_get_irq; |
2880 | ring->irq_put = gen5_ring_put_irq; | |
2881 | } else { | |
e3670319 | 2882 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2883 | ring->irq_get = i9xx_ring_get_irq; |
2884 | ring->irq_put = i9xx_ring_put_irq; | |
2885 | } | |
fb3256da | 2886 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2887 | } |
ecfe00d8 | 2888 | ring->init_hw = init_ring_common; |
58fa3835 | 2889 | |
1ec14ad3 | 2890 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2891 | } |
549f7365 | 2892 | |
845f74a7 | 2893 | /** |
62659920 | 2894 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2895 | */ |
2896 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2897 | { | |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2899 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 | 2900 | |
f7b64236 | 2901 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2902 | ring->id = VCS2; |
2903 | ||
2904 | ring->write_tail = ring_write_tail; | |
2905 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2906 | ring->flush = gen6_bsd_ring_flush; | |
2907 | ring->add_request = gen6_add_request; | |
2908 | ring->get_seqno = gen6_ring_get_seqno; | |
2909 | ring->set_seqno = ring_set_seqno; | |
2910 | ring->irq_enable_mask = | |
2911 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2912 | ring->irq_get = gen8_ring_get_irq; | |
2913 | ring->irq_put = gen8_ring_put_irq; | |
2914 | ring->dispatch_execbuffer = | |
2915 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2916 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2917 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2918 | ring->semaphore.signal = gen8_xcs_signal; |
2919 | GEN8_RING_SEMAPHORE_INIT; | |
2920 | } | |
ecfe00d8 | 2921 | ring->init_hw = init_ring_common; |
845f74a7 ZY |
2922 | |
2923 | return intel_init_ring_buffer(dev, ring); | |
2924 | } | |
2925 | ||
549f7365 CW |
2926 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2927 | { | |
4640c4ff | 2928 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2929 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2930 | |
3535d9dd DV |
2931 | ring->name = "blitter ring"; |
2932 | ring->id = BCS; | |
2933 | ||
2934 | ring->mmio_base = BLT_RING_BASE; | |
2935 | ring->write_tail = ring_write_tail; | |
ea251324 | 2936 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2937 | ring->add_request = gen6_add_request; |
2938 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2939 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2940 | if (INTEL_INFO(dev)->gen >= 8) { |
2941 | ring->irq_enable_mask = | |
2942 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2943 | ring->irq_get = gen8_ring_get_irq; | |
2944 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2945 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2946 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2947 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2948 | ring->semaphore.signal = gen8_xcs_signal; |
2949 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2950 | } |
abd58f01 BW |
2951 | } else { |
2952 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2953 | ring->irq_get = gen6_ring_get_irq; | |
2954 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2955 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2956 | if (i915_semaphore_is_enabled(dev)) { |
2957 | ring->semaphore.signal = gen6_signal; | |
2958 | ring->semaphore.sync_to = gen6_ring_sync; | |
2959 | /* | |
2960 | * The current semaphore is only applied on pre-gen8 | |
2961 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2962 | * platform. So the semaphore between BCS and VCS2 is | |
2963 | * initialized as INVALID. Gen8 will initialize the | |
2964 | * sema between BCS and VCS2 later. | |
2965 | */ | |
2966 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2967 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2968 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2969 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2970 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2971 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2972 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2973 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2974 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2975 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2976 | } | |
abd58f01 | 2977 | } |
ecfe00d8 | 2978 | ring->init_hw = init_ring_common; |
549f7365 | 2979 | |
1ec14ad3 | 2980 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2981 | } |
a7b9761d | 2982 | |
9a8a2213 BW |
2983 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2984 | { | |
4640c4ff | 2985 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2986 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2987 | |
2988 | ring->name = "video enhancement ring"; | |
2989 | ring->id = VECS; | |
2990 | ||
2991 | ring->mmio_base = VEBOX_RING_BASE; | |
2992 | ring->write_tail = ring_write_tail; | |
2993 | ring->flush = gen6_ring_flush; | |
2994 | ring->add_request = gen6_add_request; | |
2995 | ring->get_seqno = gen6_ring_get_seqno; | |
2996 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2997 | |
2998 | if (INTEL_INFO(dev)->gen >= 8) { | |
2999 | ring->irq_enable_mask = | |
40c499f9 | 3000 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
3001 | ring->irq_get = gen8_ring_get_irq; |
3002 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 3003 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 3004 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 3005 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
3006 | ring->semaphore.signal = gen8_xcs_signal; |
3007 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 3008 | } |
abd58f01 BW |
3009 | } else { |
3010 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
3011 | ring->irq_get = hsw_vebox_get_irq; | |
3012 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 3013 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
3014 | if (i915_semaphore_is_enabled(dev)) { |
3015 | ring->semaphore.sync_to = gen6_ring_sync; | |
3016 | ring->semaphore.signal = gen6_signal; | |
3017 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3018 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3019 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3020 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3021 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3022 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3023 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3024 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3025 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3026 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
3027 | } | |
abd58f01 | 3028 | } |
ecfe00d8 | 3029 | ring->init_hw = init_ring_common; |
9a8a2213 BW |
3030 | |
3031 | return intel_init_ring_buffer(dev, ring); | |
3032 | } | |
3033 | ||
a7b9761d | 3034 | int |
4866d729 | 3035 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3036 | { |
4866d729 | 3037 | struct intel_engine_cs *ring = req->ring; |
a7b9761d CW |
3038 | int ret; |
3039 | ||
3040 | if (!ring->gpu_caches_dirty) | |
3041 | return 0; | |
3042 | ||
a84c3ae1 | 3043 | ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3044 | if (ret) |
3045 | return ret; | |
3046 | ||
a84c3ae1 | 3047 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3048 | |
3049 | ring->gpu_caches_dirty = false; | |
3050 | return 0; | |
3051 | } | |
3052 | ||
3053 | int | |
2f20055d | 3054 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3055 | { |
2f20055d | 3056 | struct intel_engine_cs *ring = req->ring; |
a7b9761d CW |
3057 | uint32_t flush_domains; |
3058 | int ret; | |
3059 | ||
3060 | flush_domains = 0; | |
3061 | if (ring->gpu_caches_dirty) | |
3062 | flush_domains = I915_GEM_GPU_DOMAINS; | |
3063 | ||
a84c3ae1 | 3064 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3065 | if (ret) |
3066 | return ret; | |
3067 | ||
a84c3ae1 | 3068 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3069 | |
3070 | ring->gpu_caches_dirty = false; | |
3071 | return 0; | |
3072 | } | |
e3efda49 CW |
3073 | |
3074 | void | |
a4872ba6 | 3075 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
3076 | { |
3077 | int ret; | |
3078 | ||
3079 | if (!intel_ring_initialized(ring)) | |
3080 | return; | |
3081 | ||
3082 | ret = intel_ring_idle(ring); | |
3083 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
3084 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
3085 | ring->name, ret); | |
3086 | ||
3087 | stop_ring(ring); | |
3088 | } |