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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
2f35afe9 | 42 | static int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b72f3acb | 61 | static int |
7c9cf4e3 | 62 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 63 | { |
73dec95e | 64 | u32 cmd, *cs; |
46f0f8d1 CW |
65 | |
66 | cmd = MI_FLUSH; | |
46f0f8d1 | 67 | |
7c9cf4e3 | 68 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
69 | cmd |= MI_READ_FLUSH; |
70 | ||
73dec95e TU |
71 | cs = intel_ring_begin(req, 2); |
72 | if (IS_ERR(cs)) | |
73 | return PTR_ERR(cs); | |
46f0f8d1 | 74 | |
73dec95e TU |
75 | *cs++ = cmd; |
76 | *cs++ = MI_NOOP; | |
77 | intel_ring_advance(req, cs); | |
46f0f8d1 CW |
78 | |
79 | return 0; | |
80 | } | |
81 | ||
82 | static int | |
7c9cf4e3 | 83 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 84 | { |
73dec95e | 85 | u32 cmd, *cs; |
6f392d54 | 86 | |
36d527de CW |
87 | /* |
88 | * read/write caches: | |
89 | * | |
90 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
91 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
92 | * also flushed at 2d versus 3d pipeline switches. | |
93 | * | |
94 | * read-only caches: | |
95 | * | |
96 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
97 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
98 | * | |
99 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
100 | * | |
101 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
102 | * invalidated when MI_EXE_FLUSH is set. | |
103 | * | |
104 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
105 | * invalidated with every MI_FLUSH. | |
106 | * | |
107 | * TLBs: | |
108 | * | |
109 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
110 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
111 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
112 | * are flushed at any MI_FLUSH. | |
113 | */ | |
114 | ||
b5321f30 | 115 | cmd = MI_FLUSH; |
7c9cf4e3 | 116 | if (mode & EMIT_INVALIDATE) { |
36d527de | 117 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
118 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
119 | cmd |= MI_INVALIDATE_ISP; | |
120 | } | |
70eac33e | 121 | |
73dec95e TU |
122 | cs = intel_ring_begin(req, 2); |
123 | if (IS_ERR(cs)) | |
124 | return PTR_ERR(cs); | |
b72f3acb | 125 | |
73dec95e TU |
126 | *cs++ = cmd; |
127 | *cs++ = MI_NOOP; | |
128 | intel_ring_advance(req, cs); | |
b72f3acb CW |
129 | |
130 | return 0; | |
8187a2b7 ZN |
131 | } |
132 | ||
8d315287 JB |
133 | /** |
134 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
135 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
136 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
137 | * | |
138 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
139 | * produced by non-pipelined state commands), software needs to first | |
140 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
141 | * 0. | |
142 | * | |
143 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
144 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
145 | * | |
146 | * And the workaround for these two requires this workaround first: | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
149 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
150 | * flushes. | |
151 | * | |
152 | * And this last workaround is tricky because of the requirements on | |
153 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
154 | * volume 2 part 1: | |
155 | * | |
156 | * "1 of the following must also be set: | |
157 | * - Render Target Cache Flush Enable ([12] of DW1) | |
158 | * - Depth Cache Flush Enable ([0] of DW1) | |
159 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
160 | * - Depth Stall ([13] of DW1) | |
161 | * - Post-Sync Operation ([13] of DW1) | |
162 | * - Notify Enable ([8] of DW1)" | |
163 | * | |
164 | * The cache flushes require the workaround flush that triggered this | |
165 | * one, so we can't use it. Depth stall would trigger the same. | |
166 | * Post-sync nonzero is what triggered this second workaround, so we | |
167 | * can't use that one either. Notify enable is IRQs, which aren't | |
168 | * really our business. That leaves only stall at scoreboard. | |
169 | */ | |
170 | static int | |
f2cf1fcc | 171 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 172 | { |
b5321f30 | 173 | u32 scratch_addr = |
bde13ebd | 174 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
175 | u32 *cs; |
176 | ||
177 | cs = intel_ring_begin(req, 6); | |
178 | if (IS_ERR(cs)) | |
179 | return PTR_ERR(cs); | |
180 | ||
181 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
182 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
183 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
184 | *cs++ = 0; /* low dword */ | |
185 | *cs++ = 0; /* high dword */ | |
186 | *cs++ = MI_NOOP; | |
187 | intel_ring_advance(req, cs); | |
188 | ||
189 | cs = intel_ring_begin(req, 6); | |
190 | if (IS_ERR(cs)) | |
191 | return PTR_ERR(cs); | |
192 | ||
193 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
194 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
195 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
196 | *cs++ = 0; | |
197 | *cs++ = 0; | |
198 | *cs++ = MI_NOOP; | |
199 | intel_ring_advance(req, cs); | |
8d315287 JB |
200 | |
201 | return 0; | |
202 | } | |
203 | ||
204 | static int | |
7c9cf4e3 | 205 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 206 | { |
b5321f30 | 207 | u32 scratch_addr = |
bde13ebd | 208 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 209 | u32 *cs, flags = 0; |
8d315287 JB |
210 | int ret; |
211 | ||
b3111509 | 212 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 213 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
214 | if (ret) |
215 | return ret; | |
216 | ||
8d315287 JB |
217 | /* Just flush everything. Experiments have shown that reducing the |
218 | * number of bits based on the write domains has little performance | |
219 | * impact. | |
220 | */ | |
7c9cf4e3 | 221 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
222 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
223 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
224 | /* | |
225 | * Ensure that any following seqno writes only happen | |
226 | * when the render cache is indeed flushed. | |
227 | */ | |
97f209bc | 228 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 229 | } |
7c9cf4e3 | 230 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
231 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
232 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
233 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
234 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
235 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
236 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
237 | /* | |
238 | * TLB invalidate requires a post-sync write. | |
239 | */ | |
3ac78313 | 240 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 241 | } |
8d315287 | 242 | |
73dec95e TU |
243 | cs = intel_ring_begin(req, 4); |
244 | if (IS_ERR(cs)) | |
245 | return PTR_ERR(cs); | |
8d315287 | 246 | |
73dec95e TU |
247 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
248 | *cs++ = flags; | |
249 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
250 | *cs++ = 0; | |
251 | intel_ring_advance(req, cs); | |
8d315287 JB |
252 | |
253 | return 0; | |
254 | } | |
255 | ||
f3987631 | 256 | static int |
f2cf1fcc | 257 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 258 | { |
73dec95e | 259 | u32 *cs; |
f3987631 | 260 | |
73dec95e TU |
261 | cs = intel_ring_begin(req, 4); |
262 | if (IS_ERR(cs)) | |
263 | return PTR_ERR(cs); | |
f3987631 | 264 | |
73dec95e TU |
265 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
266 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
267 | *cs++ = 0; | |
268 | *cs++ = 0; | |
269 | intel_ring_advance(req, cs); | |
f3987631 PZ |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
4772eaeb | 274 | static int |
7c9cf4e3 | 275 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 276 | { |
b5321f30 | 277 | u32 scratch_addr = |
bde13ebd | 278 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 279 | u32 *cs, flags = 0; |
4772eaeb | 280 | |
f3987631 PZ |
281 | /* |
282 | * Ensure that any following seqno writes only happen when the render | |
283 | * cache is indeed flushed. | |
284 | * | |
285 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
286 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
287 | * don't try to be clever and just set it unconditionally. | |
288 | */ | |
289 | flags |= PIPE_CONTROL_CS_STALL; | |
290 | ||
4772eaeb PZ |
291 | /* Just flush everything. Experiments have shown that reducing the |
292 | * number of bits based on the write domains has little performance | |
293 | * impact. | |
294 | */ | |
7c9cf4e3 | 295 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
296 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
297 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 298 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 299 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 300 | } |
7c9cf4e3 | 301 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
302 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
303 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
304 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
305 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
306 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
307 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 308 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
309 | /* |
310 | * TLB invalidate requires a post-sync write. | |
311 | */ | |
312 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 313 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 314 | |
add284a3 CW |
315 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
316 | ||
f3987631 PZ |
317 | /* Workaround: we must issue a pipe_control with CS-stall bit |
318 | * set before a pipe_control command that has the state cache | |
319 | * invalidate bit set. */ | |
f2cf1fcc | 320 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
321 | } |
322 | ||
73dec95e TU |
323 | cs = intel_ring_begin(req, 4); |
324 | if (IS_ERR(cs)) | |
325 | return PTR_ERR(cs); | |
4772eaeb | 326 | |
73dec95e TU |
327 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
328 | *cs++ = flags; | |
329 | *cs++ = scratch_addr; | |
330 | *cs++ = 0; | |
331 | intel_ring_advance(req, cs); | |
4772eaeb PZ |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
884ceace | 336 | static int |
f2cf1fcc | 337 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
338 | u32 flags, u32 scratch_addr) |
339 | { | |
73dec95e | 340 | u32 *cs; |
884ceace | 341 | |
73dec95e TU |
342 | cs = intel_ring_begin(req, 6); |
343 | if (IS_ERR(cs)) | |
344 | return PTR_ERR(cs); | |
884ceace | 345 | |
73dec95e TU |
346 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
347 | *cs++ = flags; | |
348 | *cs++ = scratch_addr; | |
349 | *cs++ = 0; | |
350 | *cs++ = 0; | |
351 | *cs++ = 0; | |
352 | intel_ring_advance(req, cs); | |
884ceace KG |
353 | |
354 | return 0; | |
355 | } | |
356 | ||
a5f3d68e | 357 | static int |
7c9cf4e3 | 358 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 359 | { |
56c0f1a7 | 360 | u32 scratch_addr = |
bde13ebd | 361 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
b5321f30 | 362 | u32 flags = 0; |
02c9f7e3 | 363 | int ret; |
a5f3d68e BW |
364 | |
365 | flags |= PIPE_CONTROL_CS_STALL; | |
366 | ||
7c9cf4e3 | 367 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
368 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
369 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 370 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 371 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 372 | } |
7c9cf4e3 | 373 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
374 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
375 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
376 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
377 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
378 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
379 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
380 | flags |= PIPE_CONTROL_QW_WRITE; | |
381 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
382 | |
383 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 384 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
385 | PIPE_CONTROL_CS_STALL | |
386 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
387 | 0); | |
388 | if (ret) | |
389 | return ret; | |
a5f3d68e BW |
390 | } |
391 | ||
f2cf1fcc | 392 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
393 | } |
394 | ||
0bc40be8 | 395 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 396 | { |
c033666a | 397 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
398 | u32 addr; |
399 | ||
400 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 401 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
402 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
403 | I915_WRITE(HWS_PGA, addr); | |
404 | } | |
405 | ||
0bc40be8 | 406 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 407 | { |
c033666a | 408 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 409 | i915_reg_t mmio; |
af75f269 DL |
410 | |
411 | /* The ring status page addresses are no longer next to the rest of | |
412 | * the ring registers as of gen7. | |
413 | */ | |
c033666a | 414 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 415 | switch (engine->id) { |
af75f269 DL |
416 | case RCS: |
417 | mmio = RENDER_HWS_PGA_GEN7; | |
418 | break; | |
419 | case BCS: | |
420 | mmio = BLT_HWS_PGA_GEN7; | |
421 | break; | |
422 | /* | |
423 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
424 | * gcc switch check warning | |
425 | */ | |
426 | case VCS2: | |
427 | case VCS: | |
428 | mmio = BSD_HWS_PGA_GEN7; | |
429 | break; | |
430 | case VECS: | |
431 | mmio = VEBOX_HWS_PGA_GEN7; | |
432 | break; | |
433 | } | |
c033666a | 434 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 435 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
436 | } else { |
437 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 438 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
439 | } |
440 | ||
57e88531 | 441 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
442 | POSTING_READ(mmio); |
443 | ||
444 | /* | |
445 | * Flush the TLB for this page | |
446 | * | |
447 | * FIXME: These two bits have disappeared on gen8, so a question | |
448 | * arises: do we still need this and if so how should we go about | |
449 | * invalidating the TLB? | |
450 | */ | |
ac657f64 | 451 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 452 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
453 | |
454 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 455 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
456 | |
457 | I915_WRITE(reg, | |
458 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
459 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
460 | if (intel_wait_for_register(dev_priv, |
461 | reg, INSTPM_SYNC_FLUSH, 0, | |
462 | 1000)) | |
af75f269 | 463 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 464 | engine->name); |
af75f269 DL |
465 | } |
466 | } | |
467 | ||
0bc40be8 | 468 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 469 | { |
c033666a | 470 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 471 | |
21a2c58a | 472 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 473 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
474 | if (intel_wait_for_register(dev_priv, |
475 | RING_MI_MODE(engine->mmio_base), | |
476 | MODE_IDLE, | |
477 | MODE_IDLE, | |
478 | 1000)) { | |
0bc40be8 TU |
479 | DRM_ERROR("%s : timed out trying to stop ring\n", |
480 | engine->name); | |
9bec9b13 CW |
481 | /* Sometimes we observe that the idle flag is not |
482 | * set even though the ring is empty. So double | |
483 | * check before giving up. | |
484 | */ | |
0bc40be8 | 485 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 486 | return false; |
9991ae78 CW |
487 | } |
488 | } | |
b7884eb4 | 489 | |
0bc40be8 TU |
490 | I915_WRITE_CTL(engine, 0); |
491 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 492 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 493 | |
21a2c58a | 494 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
495 | (void)I915_READ_CTL(engine); |
496 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 497 | } |
a51435a3 | 498 | |
0bc40be8 | 499 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 500 | } |
8187a2b7 | 501 | |
0bc40be8 | 502 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 503 | { |
c033666a | 504 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 505 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
506 | int ret = 0; |
507 | ||
59bad947 | 508 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 509 | |
0bc40be8 | 510 | if (!stop_ring(engine)) { |
9991ae78 | 511 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
512 | DRM_DEBUG_KMS("%s head not reset to zero " |
513 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
514 | engine->name, |
515 | I915_READ_CTL(engine), | |
516 | I915_READ_HEAD(engine), | |
517 | I915_READ_TAIL(engine), | |
518 | I915_READ_START(engine)); | |
8187a2b7 | 519 | |
0bc40be8 | 520 | if (!stop_ring(engine)) { |
6fd0d56e CW |
521 | DRM_ERROR("failed to set %s head to zero " |
522 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
523 | engine->name, |
524 | I915_READ_CTL(engine), | |
525 | I915_READ_HEAD(engine), | |
526 | I915_READ_TAIL(engine), | |
527 | I915_READ_START(engine)); | |
9991ae78 CW |
528 | ret = -EIO; |
529 | goto out; | |
6fd0d56e | 530 | } |
8187a2b7 ZN |
531 | } |
532 | ||
3177659a | 533 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 534 | ring_setup_phys_status_page(engine); |
3177659a CS |
535 | else |
536 | intel_ring_setup_status_page(engine); | |
9991ae78 | 537 | |
ad07dfcd | 538 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 539 | |
ece4a17d | 540 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 541 | I915_READ_HEAD(engine); |
ece4a17d | 542 | |
0d8957c8 DV |
543 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
544 | * registers with the above sequence (the readback of the HEAD registers | |
545 | * also enforces ordering), otherwise the hw might lose the new ring | |
546 | * register values. */ | |
bde13ebd | 547 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
548 | |
549 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 550 | if (I915_READ_HEAD(engine)) |
95468892 | 551 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 552 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
553 | |
554 | intel_ring_update_space(ring); | |
555 | I915_WRITE_HEAD(engine, ring->head); | |
556 | I915_WRITE_TAIL(engine, ring->tail); | |
557 | (void)I915_READ_TAIL(engine); | |
95468892 | 558 | |
62ae14b1 | 559 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 560 | |
8187a2b7 | 561 | /* If the head is still not zero, the ring is dead */ |
821ed7df CW |
562 | if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base), |
563 | RING_VALID, RING_VALID, | |
564 | 50)) { | |
e74cfed5 | 565 | DRM_ERROR("%s initialization failed " |
821ed7df | 566 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
567 | engine->name, |
568 | I915_READ_CTL(engine), | |
569 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
570 | I915_READ_HEAD(engine), ring->head, |
571 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 572 | I915_READ_START(engine), |
bde13ebd | 573 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
574 | ret = -EIO; |
575 | goto out; | |
8187a2b7 ZN |
576 | } |
577 | ||
fc0768ce | 578 | intel_engine_init_hangcheck(engine); |
50f018df | 579 | |
b7884eb4 | 580 | out: |
59bad947 | 581 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
582 | |
583 | return ret; | |
8187a2b7 ZN |
584 | } |
585 | ||
821ed7df CW |
586 | static void reset_ring_common(struct intel_engine_cs *engine, |
587 | struct drm_i915_gem_request *request) | |
588 | { | |
c0dcb203 CW |
589 | /* Try to restore the logical GPU state to match the continuation |
590 | * of the request queue. If we skip the context/PD restore, then | |
591 | * the next request may try to execute assuming that its context | |
592 | * is valid and loaded on the GPU and so may try to access invalid | |
593 | * memory, prompting repeated GPU hangs. | |
594 | * | |
595 | * If the request was guilty, we still restore the logical state | |
596 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
597 | * but skip over the hung batch. | |
598 | * | |
599 | * If the request was innocent, we try to replay the request with | |
600 | * the restored context. | |
601 | */ | |
602 | if (request) { | |
603 | struct drm_i915_private *dev_priv = request->i915; | |
604 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
605 | struct i915_hw_ppgtt *ppgtt; | |
606 | ||
607 | /* FIXME consider gen8 reset */ | |
608 | ||
609 | if (ce->state) { | |
610 | I915_WRITE(CCID, | |
611 | i915_ggtt_offset(ce->state) | | |
612 | BIT(8) /* must be set! */ | | |
613 | CCID_EXTENDED_STATE_SAVE | | |
614 | CCID_EXTENDED_STATE_RESTORE | | |
615 | CCID_EN); | |
616 | } | |
617 | ||
618 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
619 | if (ppgtt) { | |
620 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
621 | ||
622 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
623 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
624 | ||
625 | /* Wait for the PD reload to complete */ | |
626 | if (intel_wait_for_register(dev_priv, | |
627 | RING_PP_DIR_BASE(engine), | |
628 | BIT(0), 0, | |
629 | 10)) | |
630 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 631 | |
c0dcb203 CW |
632 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
633 | } | |
634 | ||
635 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
636 | if (request->fence.error == -EIO) { | |
637 | struct intel_ring *ring = request->ring; | |
638 | ||
639 | ring->head = request->postfix; | |
640 | ring->last_retired_head = -1; | |
641 | } | |
642 | } else { | |
643 | engine->legacy_active_context = NULL; | |
644 | } | |
821ed7df CW |
645 | } |
646 | ||
8753181e | 647 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
648 | { |
649 | int ret; | |
650 | ||
e2be4faf | 651 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
652 | if (ret != 0) |
653 | return ret; | |
654 | ||
4e50f082 | 655 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 656 | if (ret) |
e26e1b97 | 657 | return ret; |
8f0e2b9d | 658 | |
e26e1b97 | 659 | return 0; |
8f0e2b9d DV |
660 | } |
661 | ||
0bc40be8 | 662 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 663 | { |
c033666a | 664 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 665 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
666 | if (ret) |
667 | return ret; | |
a69ffdbf | 668 | |
61a563a2 | 669 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 670 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 671 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
672 | |
673 | /* We need to disable the AsyncFlip performance optimisations in order | |
674 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
675 | * programmed to '1' on all products. | |
8693a824 | 676 | * |
2441f877 | 677 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 678 | */ |
ac657f64 | 679 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
680 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
681 | ||
f05bb0c7 | 682 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 683 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 684 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 685 | I915_WRITE(GFX_MODE, |
aa83e30d | 686 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 687 | |
01fa0302 | 688 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 689 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 690 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 691 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 692 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 693 | |
c033666a | 694 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
695 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
696 | * "If this bit is set, STCunit will have LRA as replacement | |
697 | * policy. [...] This bit must be reset. LRA replacement | |
698 | * policy is not supported." | |
699 | */ | |
700 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 701 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
702 | } |
703 | ||
ac657f64 | 704 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 705 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 706 | |
035ea405 VS |
707 | if (INTEL_INFO(dev_priv)->gen >= 6) |
708 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 709 | |
0bc40be8 | 710 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
711 | } |
712 | ||
0bc40be8 | 713 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 714 | { |
c033666a | 715 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 716 | |
19880c4a | 717 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
718 | } |
719 | ||
73dec95e | 720 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 721 | { |
ad7bdb2b | 722 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 723 | struct intel_engine_cs *waiter; |
c3232b18 | 724 | enum intel_engine_id id; |
3e78998a | 725 | |
3b3f1650 | 726 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 727 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
728 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
729 | continue; | |
730 | ||
73dec95e TU |
731 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
732 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | | |
733 | PIPE_CONTROL_CS_STALL; | |
734 | *cs++ = lower_32_bits(gtt_offset); | |
735 | *cs++ = upper_32_bits(gtt_offset); | |
736 | *cs++ = req->global_seqno; | |
737 | *cs++ = 0; | |
738 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
739 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
740 | *cs++ = 0; | |
3e78998a BW |
741 | } |
742 | ||
73dec95e | 743 | return cs; |
3e78998a BW |
744 | } |
745 | ||
73dec95e | 746 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 747 | { |
ad7bdb2b | 748 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 749 | struct intel_engine_cs *waiter; |
c3232b18 | 750 | enum intel_engine_id id; |
3e78998a | 751 | |
3b3f1650 | 752 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 753 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
754 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
755 | continue; | |
756 | ||
73dec95e TU |
757 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
758 | *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
759 | *cs++ = upper_32_bits(gtt_offset); | |
760 | *cs++ = req->global_seqno; | |
761 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
762 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
763 | *cs++ = 0; | |
3e78998a BW |
764 | } |
765 | ||
73dec95e | 766 | return cs; |
3e78998a BW |
767 | } |
768 | ||
73dec95e | 769 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 770 | { |
ad7bdb2b | 771 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 772 | struct intel_engine_cs *engine; |
3b3f1650 | 773 | enum intel_engine_id id; |
caddfe71 | 774 | int num_rings = 0; |
024a43e1 | 775 | |
3b3f1650 | 776 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
777 | i915_reg_t mbox_reg; |
778 | ||
779 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
780 | continue; | |
f0f59a00 | 781 | |
318f89ca | 782 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 783 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
784 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
785 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
786 | *cs++ = req->global_seqno; | |
caddfe71 | 787 | num_rings++; |
78325f2d BW |
788 | } |
789 | } | |
caddfe71 | 790 | if (num_rings & 1) |
73dec95e | 791 | *cs++ = MI_NOOP; |
024a43e1 | 792 | |
73dec95e | 793 | return cs; |
1ec14ad3 CW |
794 | } |
795 | ||
b0411e7d CW |
796 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
797 | { | |
798 | struct drm_i915_private *dev_priv = request->i915; | |
799 | ||
d55ac5bf CW |
800 | i915_gem_request_submit(request); |
801 | ||
caddfe71 | 802 | I915_WRITE_TAIL(request->engine, request->tail); |
b0411e7d CW |
803 | } |
804 | ||
73dec95e | 805 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 806 | { |
73dec95e TU |
807 | *cs++ = MI_STORE_DWORD_INDEX; |
808 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
809 | *cs++ = req->global_seqno; | |
810 | *cs++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 811 | |
73dec95e | 812 | req->tail = intel_ring_offset(req, cs); |
1ec14ad3 CW |
813 | } |
814 | ||
98f29e8d CW |
815 | static const int i9xx_emit_breadcrumb_sz = 4; |
816 | ||
b0411e7d | 817 | /** |
9b81d556 | 818 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
819 | * |
820 | * @request - request to write to the ring | |
821 | * | |
822 | * Update the mailbox registers in the *other* rings with the current seqno. | |
823 | * This acts like a signal in the canonical semaphore. | |
824 | */ | |
73dec95e | 825 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
b0411e7d | 826 | { |
caddfe71 | 827 | return i9xx_emit_breadcrumb(req, |
73dec95e | 828 | req->engine->semaphore.signal(req, cs)); |
b0411e7d CW |
829 | } |
830 | ||
caddfe71 | 831 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
73dec95e | 832 | u32 *cs) |
a58c01aa CW |
833 | { |
834 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 835 | |
caddfe71 | 836 | if (engine->semaphore.signal) |
73dec95e TU |
837 | cs = engine->semaphore.signal(req, cs); |
838 | ||
839 | *cs++ = GFX_OP_PIPE_CONTROL(6); | |
840 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
841 | PIPE_CONTROL_QW_WRITE; | |
842 | *cs++ = intel_hws_seqno_address(engine); | |
843 | *cs++ = 0; | |
844 | *cs++ = req->global_seqno; | |
a58c01aa | 845 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
846 | *cs++ = 0; |
847 | *cs++ = MI_USER_INTERRUPT; | |
848 | *cs++ = MI_NOOP; | |
a58c01aa | 849 | |
73dec95e | 850 | req->tail = intel_ring_offset(req, cs); |
a58c01aa CW |
851 | } |
852 | ||
98f29e8d CW |
853 | static const int gen8_render_emit_breadcrumb_sz = 8; |
854 | ||
c8c99b0f BW |
855 | /** |
856 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
857 | * | |
858 | * @waiter - ring that is waiting | |
859 | * @signaller - ring which has, or will signal | |
860 | * @seqno - seqno which the waiter will block on | |
861 | */ | |
5ee426ca BW |
862 | |
863 | static int | |
ad7bdb2b CW |
864 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
865 | struct drm_i915_gem_request *signal) | |
5ee426ca | 866 | { |
ad7bdb2b CW |
867 | struct drm_i915_private *dev_priv = req->i915; |
868 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 869 | struct i915_hw_ppgtt *ppgtt; |
73dec95e | 870 | u32 *cs; |
5ee426ca | 871 | |
73dec95e TU |
872 | cs = intel_ring_begin(req, 4); |
873 | if (IS_ERR(cs)) | |
874 | return PTR_ERR(cs); | |
5ee426ca | 875 | |
73dec95e TU |
876 | *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | |
877 | MI_SEMAPHORE_SAD_GTE_SDD; | |
878 | *cs++ = signal->global_seqno; | |
879 | *cs++ = lower_32_bits(offset); | |
880 | *cs++ = upper_32_bits(offset); | |
881 | intel_ring_advance(req, cs); | |
6ef48d7f CW |
882 | |
883 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
884 | * pagetables and we must reload them before executing the batch. | |
885 | * We do this on the i915_switch_context() following the wait and | |
886 | * before the dispatch. | |
887 | */ | |
ad7bdb2b CW |
888 | ppgtt = req->ctx->ppgtt; |
889 | if (ppgtt && req->engine->id != RCS) | |
890 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
891 | return 0; |
892 | } | |
893 | ||
c8c99b0f | 894 | static int |
ad7bdb2b CW |
895 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
896 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 897 | { |
c8c99b0f BW |
898 | u32 dw1 = MI_SEMAPHORE_MBOX | |
899 | MI_SEMAPHORE_COMPARE | | |
900 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 901 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
73dec95e | 902 | u32 *cs; |
1ec14ad3 | 903 | |
ebc348b2 | 904 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 905 | |
73dec95e TU |
906 | cs = intel_ring_begin(req, 4); |
907 | if (IS_ERR(cs)) | |
908 | return PTR_ERR(cs); | |
1ec14ad3 | 909 | |
73dec95e | 910 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
911 | /* Throughout all of the GEM code, seqno passed implies our current |
912 | * seqno is >= the last seqno executed. However for hardware the | |
913 | * comparison is strictly greater than. | |
914 | */ | |
73dec95e TU |
915 | *cs++ = signal->global_seqno - 1; |
916 | *cs++ = 0; | |
917 | *cs++ = MI_NOOP; | |
918 | intel_ring_advance(req, cs); | |
1ec14ad3 CW |
919 | |
920 | return 0; | |
921 | } | |
922 | ||
f8973c21 | 923 | static void |
38a0f2db | 924 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 925 | { |
f8973c21 CW |
926 | /* MI_STORE are internally buffered by the GPU and not flushed |
927 | * either by MI_FLUSH or SyncFlush or any other combination of | |
928 | * MI commands. | |
c6df541c | 929 | * |
f8973c21 CW |
930 | * "Only the submission of the store operation is guaranteed. |
931 | * The write result will be complete (coherent) some time later | |
932 | * (this is practically a finite period but there is no guaranteed | |
933 | * latency)." | |
934 | * | |
935 | * Empirically, we observe that we need a delay of at least 75us to | |
936 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 937 | */ |
f8973c21 | 938 | usleep_range(125, 250); |
c6df541c CW |
939 | } |
940 | ||
c04e0f3b CW |
941 | static void |
942 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 943 | { |
c033666a | 944 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 945 | |
4cd53c0c DV |
946 | /* Workaround to force correct ordering between irq and seqno writes on |
947 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
948 | * ACTHD) before reading the status page. |
949 | * | |
950 | * Note that this effectively stalls the read by the time it takes to | |
951 | * do a memory transaction, which more or less ensures that the write | |
952 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
953 | * Alternatively we could delay the interrupt from the CS ring to give | |
954 | * the write time to land, but that would incur a delay after every | |
955 | * batch i.e. much more frequent than a delay when waiting for the | |
956 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
957 | * |
958 | * Also note that to prevent whole machine hangs on gen7, we have to | |
959 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 960 | */ |
bcbdb6d0 | 961 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 962 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 963 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
964 | } |
965 | ||
31bb59cc CW |
966 | static void |
967 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 968 | { |
31bb59cc | 969 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
970 | } |
971 | ||
972 | static void | |
31bb59cc | 973 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 974 | { |
31bb59cc | 975 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
976 | } |
977 | ||
31bb59cc CW |
978 | static void |
979 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 980 | { |
c033666a | 981 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 982 | |
31bb59cc CW |
983 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
984 | I915_WRITE(IMR, dev_priv->irq_mask); | |
985 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
986 | } |
987 | ||
8187a2b7 | 988 | static void |
31bb59cc | 989 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 990 | { |
c033666a | 991 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 992 | |
31bb59cc CW |
993 | dev_priv->irq_mask |= engine->irq_enable_mask; |
994 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
995 | } |
996 | ||
31bb59cc CW |
997 | static void |
998 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 999 | { |
c033666a | 1000 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1001 | |
31bb59cc CW |
1002 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1003 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1004 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1005 | } |
1006 | ||
1007 | static void | |
31bb59cc | 1008 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1009 | { |
c033666a | 1010 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1011 | |
31bb59cc CW |
1012 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1013 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1014 | } |
1015 | ||
b72f3acb | 1016 | static int |
7c9cf4e3 | 1017 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1018 | { |
73dec95e | 1019 | u32 *cs; |
b72f3acb | 1020 | |
73dec95e TU |
1021 | cs = intel_ring_begin(req, 2); |
1022 | if (IS_ERR(cs)) | |
1023 | return PTR_ERR(cs); | |
b72f3acb | 1024 | |
73dec95e TU |
1025 | *cs++ = MI_FLUSH; |
1026 | *cs++ = MI_NOOP; | |
1027 | intel_ring_advance(req, cs); | |
b72f3acb | 1028 | return 0; |
d1b851fc ZN |
1029 | } |
1030 | ||
31bb59cc CW |
1031 | static void |
1032 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1033 | { |
c033666a | 1034 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1035 | |
61ff75ac CW |
1036 | I915_WRITE_IMR(engine, |
1037 | ~(engine->irq_enable_mask | | |
1038 | engine->irq_keep_mask)); | |
31bb59cc | 1039 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1040 | } |
1041 | ||
1042 | static void | |
31bb59cc | 1043 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1044 | { |
c033666a | 1045 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1046 | |
61ff75ac | 1047 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1048 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1049 | } |
1050 | ||
31bb59cc CW |
1051 | static void |
1052 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1053 | { |
c033666a | 1054 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1055 | |
31bb59cc | 1056 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1057 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1058 | } |
1059 | ||
1060 | static void | |
31bb59cc | 1061 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1062 | { |
c033666a | 1063 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1064 | |
31bb59cc | 1065 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1066 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1067 | } |
1068 | ||
31bb59cc CW |
1069 | static void |
1070 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1071 | { |
c033666a | 1072 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1073 | |
61ff75ac CW |
1074 | I915_WRITE_IMR(engine, |
1075 | ~(engine->irq_enable_mask | | |
1076 | engine->irq_keep_mask)); | |
31bb59cc | 1077 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1078 | } |
1079 | ||
1080 | static void | |
31bb59cc | 1081 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1082 | { |
c033666a | 1083 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1084 | |
61ff75ac | 1085 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1086 | } |
1087 | ||
d1b851fc | 1088 | static int |
803688ba CW |
1089 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1090 | u64 offset, u32 length, | |
1091 | unsigned int dispatch_flags) | |
d1b851fc | 1092 | { |
73dec95e | 1093 | u32 *cs; |
78501eac | 1094 | |
73dec95e TU |
1095 | cs = intel_ring_begin(req, 2); |
1096 | if (IS_ERR(cs)) | |
1097 | return PTR_ERR(cs); | |
e1f99ce6 | 1098 | |
73dec95e TU |
1099 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1100 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1101 | *cs++ = offset; | |
1102 | intel_ring_advance(req, cs); | |
78501eac | 1103 | |
d1b851fc ZN |
1104 | return 0; |
1105 | } | |
1106 | ||
b45305fc DV |
1107 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1108 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1109 | #define I830_TLB_ENTRIES (2) |
1110 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1111 | static int |
803688ba CW |
1112 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1113 | u64 offset, u32 len, | |
1114 | unsigned int dispatch_flags) | |
62fdfeaf | 1115 | { |
73dec95e | 1116 | u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); |
62fdfeaf | 1117 | |
73dec95e TU |
1118 | cs = intel_ring_begin(req, 6); |
1119 | if (IS_ERR(cs)) | |
1120 | return PTR_ERR(cs); | |
62fdfeaf | 1121 | |
c4d69da1 | 1122 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1123 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1124 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1125 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1126 | *cs++ = cs_offset; | |
1127 | *cs++ = 0xdeadbeef; | |
1128 | *cs++ = MI_NOOP; | |
1129 | intel_ring_advance(req, cs); | |
b45305fc | 1130 | |
8e004efc | 1131 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1132 | if (len > I830_BATCH_LIMIT) |
1133 | return -ENOSPC; | |
1134 | ||
73dec95e TU |
1135 | cs = intel_ring_begin(req, 6 + 2); |
1136 | if (IS_ERR(cs)) | |
1137 | return PTR_ERR(cs); | |
c4d69da1 CW |
1138 | |
1139 | /* Blit the batch (which has now all relocs applied) to the | |
1140 | * stable batch scratch bo area (so that the CS never | |
1141 | * stumbles over its tlb invalidation bug) ... | |
1142 | */ | |
73dec95e TU |
1143 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1144 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1145 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1146 | *cs++ = cs_offset; | |
1147 | *cs++ = 4096; | |
1148 | *cs++ = offset; | |
1149 | ||
1150 | *cs++ = MI_FLUSH; | |
1151 | *cs++ = MI_NOOP; | |
1152 | intel_ring_advance(req, cs); | |
b45305fc DV |
1153 | |
1154 | /* ... and execute it. */ | |
c4d69da1 | 1155 | offset = cs_offset; |
b45305fc | 1156 | } |
e1f99ce6 | 1157 | |
73dec95e TU |
1158 | cs = intel_ring_begin(req, 2); |
1159 | if (IS_ERR(cs)) | |
1160 | return PTR_ERR(cs); | |
c4d69da1 | 1161 | |
73dec95e TU |
1162 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1163 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1164 | MI_BATCH_NON_SECURE); | |
1165 | intel_ring_advance(req, cs); | |
c4d69da1 | 1166 | |
fb3256da DV |
1167 | return 0; |
1168 | } | |
1169 | ||
1170 | static int | |
803688ba CW |
1171 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1172 | u64 offset, u32 len, | |
1173 | unsigned int dispatch_flags) | |
fb3256da | 1174 | { |
73dec95e | 1175 | u32 *cs; |
fb3256da | 1176 | |
73dec95e TU |
1177 | cs = intel_ring_begin(req, 2); |
1178 | if (IS_ERR(cs)) | |
1179 | return PTR_ERR(cs); | |
fb3256da | 1180 | |
73dec95e TU |
1181 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1182 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1183 | MI_BATCH_NON_SECURE); | |
1184 | intel_ring_advance(req, cs); | |
62fdfeaf | 1185 | |
62fdfeaf EA |
1186 | return 0; |
1187 | } | |
1188 | ||
0bc40be8 | 1189 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1190 | { |
c033666a | 1191 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1192 | |
1193 | if (!dev_priv->status_page_dmah) | |
1194 | return; | |
1195 | ||
91c8a326 | 1196 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1197 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1198 | } |
1199 | ||
0bc40be8 | 1200 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1201 | { |
57e88531 | 1202 | struct i915_vma *vma; |
f8a7fde4 | 1203 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1204 | |
57e88531 CW |
1205 | vma = fetch_and_zero(&engine->status_page.vma); |
1206 | if (!vma) | |
62fdfeaf | 1207 | return; |
62fdfeaf | 1208 | |
f8a7fde4 CW |
1209 | obj = vma->obj; |
1210 | ||
57e88531 | 1211 | i915_vma_unpin(vma); |
f8a7fde4 CW |
1212 | i915_vma_close(vma); |
1213 | ||
1214 | i915_gem_object_unpin_map(obj); | |
1215 | __i915_gem_object_release_unless_active(obj); | |
62fdfeaf EA |
1216 | } |
1217 | ||
0bc40be8 | 1218 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1219 | { |
57e88531 CW |
1220 | struct drm_i915_gem_object *obj; |
1221 | struct i915_vma *vma; | |
1222 | unsigned int flags; | |
920cf419 | 1223 | void *vaddr; |
57e88531 | 1224 | int ret; |
e4ffd173 | 1225 | |
f51455d4 | 1226 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); |
57e88531 CW |
1227 | if (IS_ERR(obj)) { |
1228 | DRM_ERROR("Failed to allocate status page\n"); | |
1229 | return PTR_ERR(obj); | |
1230 | } | |
62fdfeaf | 1231 | |
57e88531 CW |
1232 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1233 | if (ret) | |
1234 | goto err; | |
e3efda49 | 1235 | |
a01cb37a | 1236 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
57e88531 CW |
1237 | if (IS_ERR(vma)) { |
1238 | ret = PTR_ERR(vma); | |
1239 | goto err; | |
e3efda49 | 1240 | } |
62fdfeaf | 1241 | |
57e88531 CW |
1242 | flags = PIN_GLOBAL; |
1243 | if (!HAS_LLC(engine->i915)) | |
1244 | /* On g33, we cannot place HWS above 256MiB, so | |
1245 | * restrict its pinning to the low mappable arena. | |
1246 | * Though this restriction is not documented for | |
1247 | * gen4, gen5, or byt, they also behave similarly | |
1248 | * and hang if the HWS is placed at the top of the | |
1249 | * GTT. To generalise, it appears that all !llc | |
1250 | * platforms have issues with us placing the HWS | |
1251 | * above the mappable region (even though we never | |
1252 | * actualy map it). | |
1253 | */ | |
1254 | flags |= PIN_MAPPABLE; | |
1255 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1256 | if (ret) | |
1257 | goto err; | |
62fdfeaf | 1258 | |
920cf419 CW |
1259 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); |
1260 | if (IS_ERR(vaddr)) { | |
1261 | ret = PTR_ERR(vaddr); | |
1262 | goto err_unpin; | |
1263 | } | |
1264 | ||
57e88531 | 1265 | engine->status_page.vma = vma; |
bde13ebd | 1266 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
f51455d4 | 1267 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); |
62fdfeaf | 1268 | |
bde13ebd CW |
1269 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1270 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1271 | return 0; |
57e88531 | 1272 | |
920cf419 CW |
1273 | err_unpin: |
1274 | i915_vma_unpin(vma); | |
57e88531 CW |
1275 | err: |
1276 | i915_gem_object_put(obj); | |
1277 | return ret; | |
62fdfeaf EA |
1278 | } |
1279 | ||
0bc40be8 | 1280 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1281 | { |
c033666a | 1282 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1283 | |
57e88531 CW |
1284 | dev_priv->status_page_dmah = |
1285 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1286 | if (!dev_priv->status_page_dmah) | |
1287 | return -ENOMEM; | |
6b8294a4 | 1288 | |
0bc40be8 TU |
1289 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1290 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1291 | |
1292 | return 0; | |
1293 | } | |
1294 | ||
d3ef1af6 | 1295 | int intel_ring_pin(struct intel_ring *ring, unsigned int offset_bias) |
7ba717cf | 1296 | { |
d3ef1af6 | 1297 | unsigned int flags; |
9d80841e | 1298 | enum i915_map_type map; |
57e88531 | 1299 | struct i915_vma *vma = ring->vma; |
8305216f | 1300 | void *addr; |
7ba717cf TD |
1301 | int ret; |
1302 | ||
57e88531 | 1303 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1304 | |
9d80841e CW |
1305 | map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC; |
1306 | ||
d3ef1af6 DCS |
1307 | flags = PIN_GLOBAL; |
1308 | if (offset_bias) | |
1309 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1310 | if (vma->obj->stolen) |
57e88531 | 1311 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1312 | |
57e88531 | 1313 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1314 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1315 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1316 | else | |
1317 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1318 | if (unlikely(ret)) | |
def0c5f6 | 1319 | return ret; |
57e88531 | 1320 | } |
7ba717cf | 1321 | |
57e88531 CW |
1322 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1323 | if (unlikely(ret)) | |
1324 | return ret; | |
def0c5f6 | 1325 | |
9d80841e | 1326 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1327 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1328 | else | |
9d80841e | 1329 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1330 | if (IS_ERR(addr)) |
1331 | goto err; | |
7ba717cf | 1332 | |
32c04f16 | 1333 | ring->vaddr = addr; |
7ba717cf | 1334 | return 0; |
d2cad535 | 1335 | |
57e88531 CW |
1336 | err: |
1337 | i915_vma_unpin(vma); | |
1338 | return PTR_ERR(addr); | |
7ba717cf TD |
1339 | } |
1340 | ||
aad29fbb CW |
1341 | void intel_ring_unpin(struct intel_ring *ring) |
1342 | { | |
1343 | GEM_BUG_ON(!ring->vma); | |
1344 | GEM_BUG_ON(!ring->vaddr); | |
1345 | ||
9d80841e | 1346 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1347 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1348 | else |
1349 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1350 | ring->vaddr = NULL; |
1351 | ||
57e88531 | 1352 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1353 | } |
1354 | ||
57e88531 CW |
1355 | static struct i915_vma * |
1356 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1357 | { |
05394f39 | 1358 | struct drm_i915_gem_object *obj; |
57e88531 | 1359 | struct i915_vma *vma; |
62fdfeaf | 1360 | |
187685cb | 1361 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1362 | if (!obj) |
12d79d78 | 1363 | obj = i915_gem_object_create(dev_priv, size); |
57e88531 CW |
1364 | if (IS_ERR(obj)) |
1365 | return ERR_CAST(obj); | |
8187a2b7 | 1366 | |
24f3a8cf AG |
1367 | /* mark ring buffers as read-only from GPU side by default */ |
1368 | obj->gt_ro = 1; | |
1369 | ||
a01cb37a | 1370 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1371 | if (IS_ERR(vma)) |
1372 | goto err; | |
1373 | ||
1374 | return vma; | |
e3efda49 | 1375 | |
57e88531 CW |
1376 | err: |
1377 | i915_gem_object_put(obj); | |
1378 | return vma; | |
e3efda49 CW |
1379 | } |
1380 | ||
7e37f889 CW |
1381 | struct intel_ring * |
1382 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1383 | { |
7e37f889 | 1384 | struct intel_ring *ring; |
57e88531 | 1385 | struct i915_vma *vma; |
01101fa7 | 1386 | |
8f942018 | 1387 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1388 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1389 | |
01101fa7 | 1390 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1391 | if (!ring) |
01101fa7 CW |
1392 | return ERR_PTR(-ENOMEM); |
1393 | ||
4a570db5 | 1394 | ring->engine = engine; |
01101fa7 | 1395 | |
675d9ad7 CW |
1396 | INIT_LIST_HEAD(&ring->request_list); |
1397 | ||
01101fa7 CW |
1398 | ring->size = size; |
1399 | /* Workaround an erratum on the i830 which causes a hang if | |
1400 | * the TAIL pointer points to within the last 2 cachelines | |
1401 | * of the buffer. | |
1402 | */ | |
1403 | ring->effective_size = size; | |
2a307c2e | 1404 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1405 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1406 | ||
1407 | ring->last_retired_head = -1; | |
1408 | intel_ring_update_space(ring); | |
1409 | ||
57e88531 CW |
1410 | vma = intel_ring_create_vma(engine->i915, size); |
1411 | if (IS_ERR(vma)) { | |
01101fa7 | 1412 | kfree(ring); |
57e88531 | 1413 | return ERR_CAST(vma); |
01101fa7 | 1414 | } |
57e88531 | 1415 | ring->vma = vma; |
01101fa7 CW |
1416 | |
1417 | return ring; | |
1418 | } | |
1419 | ||
1420 | void | |
7e37f889 | 1421 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1422 | { |
f8a7fde4 CW |
1423 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1424 | ||
1425 | i915_vma_close(ring->vma); | |
1426 | __i915_gem_object_release_unless_active(obj); | |
1427 | ||
01101fa7 CW |
1428 | kfree(ring); |
1429 | } | |
1430 | ||
72b72ae4 | 1431 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1432 | { |
1433 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1434 | int ret; | |
1435 | ||
1436 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
1437 | * We only want to do this on the first bind so that we do not stall | |
1438 | * on an active context (which by nature is already on the GPU). | |
1439 | */ | |
1440 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
1441 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
1442 | if (ret) | |
1443 | return ret; | |
1444 | } | |
1445 | ||
72b72ae4 | 1446 | return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | PIN_HIGH); |
e8a9c58f CW |
1447 | } |
1448 | ||
1449 | static int intel_ring_context_pin(struct intel_engine_cs *engine, | |
1450 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1451 | { |
1452 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1453 | int ret; | |
1454 | ||
91c8a326 | 1455 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
1456 | |
1457 | if (ce->pin_count++) | |
1458 | return 0; | |
1459 | ||
1460 | if (ce->state) { | |
72b72ae4 | 1461 | ret = context_pin(ctx); |
e8a9c58f | 1462 | if (ret) |
0cb26a8e CW |
1463 | goto error; |
1464 | } | |
1465 | ||
c7c3c07d CW |
1466 | /* The kernel context is only used as a placeholder for flushing the |
1467 | * active context. It is never used for submitting user rendering and | |
1468 | * as such never requires the golden render context, and so we can skip | |
1469 | * emitting it when we switch to the kernel context. This is required | |
1470 | * as during eviction we cannot allocate and pin the renderstate in | |
1471 | * order to initialise the context. | |
1472 | */ | |
984ff29f | 1473 | if (i915_gem_context_is_kernel(ctx)) |
c7c3c07d CW |
1474 | ce->initialised = true; |
1475 | ||
9a6feaf0 | 1476 | i915_gem_context_get(ctx); |
0cb26a8e CW |
1477 | return 0; |
1478 | ||
1479 | error: | |
1480 | ce->pin_count = 0; | |
1481 | return ret; | |
1482 | } | |
1483 | ||
e8a9c58f CW |
1484 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1485 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1486 | { |
1487 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1488 | ||
91c8a326 | 1489 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1490 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1491 | |
1492 | if (--ce->pin_count) | |
1493 | return; | |
1494 | ||
1495 | if (ce->state) | |
bf3783e5 | 1496 | i915_vma_unpin(ce->state); |
0cb26a8e | 1497 | |
9a6feaf0 | 1498 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1499 | } |
1500 | ||
acd27845 | 1501 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1502 | { |
acd27845 | 1503 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 1504 | struct intel_ring *ring; |
e3efda49 CW |
1505 | int ret; |
1506 | ||
0bc40be8 | 1507 | WARN_ON(engine->buffer); |
bfc882b4 | 1508 | |
019bf277 TU |
1509 | intel_engine_setup_common(engine); |
1510 | ||
019bf277 | 1511 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
1512 | if (ret) |
1513 | goto error; | |
e3efda49 | 1514 | |
32c04f16 CW |
1515 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1516 | if (IS_ERR(ring)) { | |
1517 | ret = PTR_ERR(ring); | |
b0366a54 DG |
1518 | goto error; |
1519 | } | |
01101fa7 | 1520 | |
3177659a CS |
1521 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
1522 | WARN_ON(engine->id != RCS); | |
1523 | ret = init_phys_status_page(engine); | |
e3efda49 | 1524 | if (ret) |
8ee14975 | 1525 | goto error; |
e3efda49 | 1526 | } else { |
3177659a | 1527 | ret = init_status_page(engine); |
e3efda49 | 1528 | if (ret) |
8ee14975 | 1529 | goto error; |
e3efda49 CW |
1530 | } |
1531 | ||
d3ef1af6 | 1532 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
f51455d4 | 1533 | ret = intel_ring_pin(ring, I915_GTT_PAGE_SIZE); |
bfc882b4 | 1534 | if (ret) { |
57e88531 | 1535 | intel_ring_free(ring); |
bfc882b4 | 1536 | goto error; |
e3efda49 | 1537 | } |
57e88531 | 1538 | engine->buffer = ring; |
62fdfeaf | 1539 | |
8ee14975 | 1540 | return 0; |
351e3db2 | 1541 | |
8ee14975 | 1542 | error: |
7e37f889 | 1543 | intel_engine_cleanup(engine); |
8ee14975 | 1544 | return ret; |
62fdfeaf EA |
1545 | } |
1546 | ||
7e37f889 | 1547 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1548 | { |
6402c330 | 1549 | struct drm_i915_private *dev_priv; |
33626e6a | 1550 | |
c033666a | 1551 | dev_priv = engine->i915; |
6402c330 | 1552 | |
0bc40be8 | 1553 | if (engine->buffer) { |
21a2c58a CW |
1554 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1555 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1556 | |
aad29fbb | 1557 | intel_ring_unpin(engine->buffer); |
7e37f889 | 1558 | intel_ring_free(engine->buffer); |
0bc40be8 | 1559 | engine->buffer = NULL; |
b0366a54 | 1560 | } |
78501eac | 1561 | |
0bc40be8 TU |
1562 | if (engine->cleanup) |
1563 | engine->cleanup(engine); | |
8d19215b | 1564 | |
3177659a | 1565 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
0bc40be8 TU |
1566 | WARN_ON(engine->id != RCS); |
1567 | cleanup_phys_status_page(engine); | |
3177659a CS |
1568 | } else { |
1569 | cleanup_status_page(engine); | |
7d3fdfff | 1570 | } |
44e895a8 | 1571 | |
96a945aa | 1572 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1573 | |
c033666a | 1574 | engine->i915 = NULL; |
3b3f1650 AG |
1575 | dev_priv->engine[engine->id] = NULL; |
1576 | kfree(engine); | |
62fdfeaf EA |
1577 | } |
1578 | ||
821ed7df CW |
1579 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1580 | { | |
1581 | struct intel_engine_cs *engine; | |
3b3f1650 | 1582 | enum intel_engine_id id; |
821ed7df | 1583 | |
3b3f1650 | 1584 | for_each_engine(engine, dev_priv, id) { |
821ed7df CW |
1585 | engine->buffer->head = engine->buffer->tail; |
1586 | engine->buffer->last_retired_head = -1; | |
1587 | } | |
1588 | } | |
1589 | ||
f73e7399 | 1590 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 1591 | { |
73dec95e | 1592 | u32 *cs; |
6310346e | 1593 | |
e8a9c58f CW |
1594 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1595 | ||
6310346e CW |
1596 | /* Flush enough space to reduce the likelihood of waiting after |
1597 | * we start building the request - in which case we will just | |
1598 | * have to repeat work. | |
1599 | */ | |
a0442461 | 1600 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1601 | |
e8a9c58f | 1602 | GEM_BUG_ON(!request->engine->buffer); |
1dae2dfb | 1603 | request->ring = request->engine->buffer; |
6310346e | 1604 | |
73dec95e TU |
1605 | cs = intel_ring_begin(request, 0); |
1606 | if (IS_ERR(cs)) | |
1607 | return PTR_ERR(cs); | |
6310346e | 1608 | |
a0442461 | 1609 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1610 | return 0; |
9d773091 CW |
1611 | } |
1612 | ||
987046ad CW |
1613 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
1614 | { | |
7e37f889 | 1615 | struct intel_ring *ring = req->ring; |
987046ad | 1616 | struct drm_i915_gem_request *target; |
e95433c7 CW |
1617 | long timeout; |
1618 | ||
1619 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
987046ad | 1620 | |
1dae2dfb CW |
1621 | intel_ring_update_space(ring); |
1622 | if (ring->space >= bytes) | |
987046ad CW |
1623 | return 0; |
1624 | ||
1625 | /* | |
1626 | * Space is reserved in the ringbuffer for finalising the request, | |
1627 | * as that cannot be allowed to fail. During request finalisation, | |
1628 | * reserved_space is set to 0 to stop the overallocation and the | |
1629 | * assumption is that then we never need to wait (which has the | |
1630 | * risk of failing with EINTR). | |
1631 | * | |
1632 | * See also i915_gem_request_alloc() and i915_add_request(). | |
1633 | */ | |
0251a963 | 1634 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 1635 | |
675d9ad7 | 1636 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
1637 | unsigned space; |
1638 | ||
987046ad | 1639 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
1640 | space = __intel_ring_space(target->postfix, ring->tail, |
1641 | ring->size); | |
987046ad CW |
1642 | if (space >= bytes) |
1643 | break; | |
79bbcc29 | 1644 | } |
29b1b415 | 1645 | |
675d9ad7 | 1646 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1647 | return -ENOSPC; |
1648 | ||
e95433c7 CW |
1649 | timeout = i915_wait_request(target, |
1650 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
1651 | MAX_SCHEDULE_TIMEOUT); | |
1652 | if (timeout < 0) | |
1653 | return timeout; | |
7da844c5 | 1654 | |
7da844c5 CW |
1655 | i915_gem_request_retire_upto(target); |
1656 | ||
1657 | intel_ring_update_space(ring); | |
1658 | GEM_BUG_ON(ring->space < bytes); | |
1659 | return 0; | |
29b1b415 JH |
1660 | } |
1661 | ||
73dec95e | 1662 | u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 1663 | { |
7e37f889 | 1664 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
1665 | int remain_actual = ring->size - ring->tail; |
1666 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
1667 | int bytes = num_dwords * sizeof(u32); |
1668 | int total_bytes, wait_bytes; | |
79bbcc29 | 1669 | bool need_wrap = false; |
73dec95e | 1670 | u32 *cs; |
29b1b415 | 1671 | |
0251a963 | 1672 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 1673 | |
79bbcc29 JH |
1674 | if (unlikely(bytes > remain_usable)) { |
1675 | /* | |
1676 | * Not enough space for the basic request. So need to flush | |
1677 | * out the remainder and then wait for base + reserved. | |
1678 | */ | |
1679 | wait_bytes = remain_actual + total_bytes; | |
1680 | need_wrap = true; | |
987046ad CW |
1681 | } else if (unlikely(total_bytes > remain_usable)) { |
1682 | /* | |
1683 | * The base request will fit but the reserved space | |
1684 | * falls off the end. So we don't need an immediate wrap | |
1685 | * and only need to effectively wait for the reserved | |
1686 | * size space from the start of ringbuffer. | |
1687 | */ | |
0251a963 | 1688 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 1689 | } else { |
987046ad CW |
1690 | /* No wrapping required, just waiting. */ |
1691 | wait_bytes = total_bytes; | |
cbcc80df MK |
1692 | } |
1693 | ||
1dae2dfb | 1694 | if (wait_bytes > ring->space) { |
987046ad | 1695 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df | 1696 | if (unlikely(ret)) |
73dec95e | 1697 | return ERR_PTR(ret); |
cbcc80df MK |
1698 | } |
1699 | ||
987046ad | 1700 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
1701 | GEM_BUG_ON(remain_actual > ring->space); |
1702 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 1703 | |
987046ad | 1704 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
1705 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
1706 | ring->tail = 0; | |
1707 | ring->space -= remain_actual; | |
987046ad | 1708 | } |
304d695c | 1709 | |
73dec95e TU |
1710 | GEM_BUG_ON(ring->tail > ring->size - bytes); |
1711 | cs = ring->vaddr + ring->tail; | |
1712 | ring->tail += bytes; | |
1dae2dfb CW |
1713 | ring->space -= bytes; |
1714 | GEM_BUG_ON(ring->space < 0); | |
73dec95e TU |
1715 | |
1716 | return cs; | |
8187a2b7 | 1717 | } |
78501eac | 1718 | |
753b1ad4 | 1719 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 1720 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 1721 | { |
b5321f30 | 1722 | int num_dwords = |
73dec95e TU |
1723 | (req->ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
1724 | u32 *cs; | |
753b1ad4 VS |
1725 | |
1726 | if (num_dwords == 0) | |
1727 | return 0; | |
1728 | ||
18393f63 | 1729 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
73dec95e TU |
1730 | cs = intel_ring_begin(req, num_dwords); |
1731 | if (IS_ERR(cs)) | |
1732 | return PTR_ERR(cs); | |
753b1ad4 VS |
1733 | |
1734 | while (num_dwords--) | |
73dec95e | 1735 | *cs++ = MI_NOOP; |
753b1ad4 | 1736 | |
73dec95e | 1737 | intel_ring_advance(req, cs); |
753b1ad4 VS |
1738 | |
1739 | return 0; | |
1740 | } | |
1741 | ||
c5efa1ad | 1742 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 1743 | { |
c5efa1ad | 1744 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1745 | |
76f8421f CW |
1746 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1747 | ||
881f47b6 | 1748 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1749 | |
1750 | /* Disable notification that the ring is IDLE. The GT | |
1751 | * will then assume that it is busy and bring it out of rc6. | |
1752 | */ | |
76f8421f CW |
1753 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1754 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1755 | |
1756 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1757 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1758 | |
12f55818 | 1759 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
1760 | if (intel_wait_for_register_fw(dev_priv, |
1761 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1762 | GEN6_BSD_SLEEP_INDICATOR, | |
1763 | 0, | |
1764 | 50)) | |
12f55818 | 1765 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1766 | |
12f55818 | 1767 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1768 | i9xx_submit_request(request); |
12f55818 CW |
1769 | |
1770 | /* Let the ring send IDLE messages to the GT again, | |
1771 | * and so let it sleep to conserve power when idle. | |
1772 | */ | |
76f8421f CW |
1773 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1774 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1775 | ||
1776 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1777 | } |
1778 | ||
7c9cf4e3 | 1779 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 1780 | { |
73dec95e | 1781 | u32 cmd, *cs; |
b72f3acb | 1782 | |
73dec95e TU |
1783 | cs = intel_ring_begin(req, 4); |
1784 | if (IS_ERR(cs)) | |
1785 | return PTR_ERR(cs); | |
b72f3acb | 1786 | |
71a77e07 | 1787 | cmd = MI_FLUSH_DW; |
c033666a | 1788 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1789 | cmd += 1; |
f0a1fb10 CW |
1790 | |
1791 | /* We always require a command barrier so that subsequent | |
1792 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1793 | * wrt the contents of the write cache being flushed to memory | |
1794 | * (and thus being coherent from the CPU). | |
1795 | */ | |
1796 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1797 | ||
9a289771 JB |
1798 | /* |
1799 | * Bspec vol 1c.5 - video engine command streamer: | |
1800 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1801 | * operation is complete. This bit is only valid when the | |
1802 | * Post-Sync Operation field is a value of 1h or 3h." | |
1803 | */ | |
7c9cf4e3 | 1804 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1805 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1806 | ||
73dec95e TU |
1807 | *cs++ = cmd; |
1808 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1809 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1810 | *cs++ = 0; /* upper addr */ |
1811 | *cs++ = 0; /* value */ | |
075b3bba | 1812 | } else { |
73dec95e TU |
1813 | *cs++ = 0; |
1814 | *cs++ = MI_NOOP; | |
075b3bba | 1815 | } |
73dec95e | 1816 | intel_ring_advance(req, cs); |
b72f3acb | 1817 | return 0; |
881f47b6 XH |
1818 | } |
1819 | ||
1c7a0623 | 1820 | static int |
803688ba CW |
1821 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
1822 | u64 offset, u32 len, | |
1823 | unsigned int dispatch_flags) | |
1c7a0623 | 1824 | { |
b5321f30 | 1825 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 1826 | !(dispatch_flags & I915_DISPATCH_SECURE); |
73dec95e | 1827 | u32 *cs; |
1c7a0623 | 1828 | |
73dec95e TU |
1829 | cs = intel_ring_begin(req, 4); |
1830 | if (IS_ERR(cs)) | |
1831 | return PTR_ERR(cs); | |
1c7a0623 BW |
1832 | |
1833 | /* FIXME(BDW): Address space and security selectors. */ | |
73dec95e TU |
1834 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & |
1835 | I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
1836 | *cs++ = lower_32_bits(offset); | |
1837 | *cs++ = upper_32_bits(offset); | |
1838 | *cs++ = MI_NOOP; | |
1839 | intel_ring_advance(req, cs); | |
1c7a0623 BW |
1840 | |
1841 | return 0; | |
1842 | } | |
1843 | ||
d7d4eedd | 1844 | static int |
803688ba CW |
1845 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
1846 | u64 offset, u32 len, | |
1847 | unsigned int dispatch_flags) | |
d7d4eedd | 1848 | { |
73dec95e | 1849 | u32 *cs; |
d7d4eedd | 1850 | |
73dec95e TU |
1851 | cs = intel_ring_begin(req, 2); |
1852 | if (IS_ERR(cs)) | |
1853 | return PTR_ERR(cs); | |
d7d4eedd | 1854 | |
73dec95e TU |
1855 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1856 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1857 | (dispatch_flags & I915_DISPATCH_RS ? | |
1858 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1859 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1860 | *cs++ = offset; |
1861 | intel_ring_advance(req, cs); | |
d7d4eedd CW |
1862 | |
1863 | return 0; | |
1864 | } | |
1865 | ||
881f47b6 | 1866 | static int |
803688ba CW |
1867 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
1868 | u64 offset, u32 len, | |
1869 | unsigned int dispatch_flags) | |
881f47b6 | 1870 | { |
73dec95e | 1871 | u32 *cs; |
ab6f8e32 | 1872 | |
73dec95e TU |
1873 | cs = intel_ring_begin(req, 2); |
1874 | if (IS_ERR(cs)) | |
1875 | return PTR_ERR(cs); | |
e1f99ce6 | 1876 | |
73dec95e TU |
1877 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1878 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1879 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1880 | *cs++ = offset; |
1881 | intel_ring_advance(req, cs); | |
ab6f8e32 | 1882 | |
0206e353 | 1883 | return 0; |
881f47b6 XH |
1884 | } |
1885 | ||
549f7365 CW |
1886 | /* Blitter support (SandyBridge+) */ |
1887 | ||
7c9cf4e3 | 1888 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 1889 | { |
73dec95e | 1890 | u32 cmd, *cs; |
b72f3acb | 1891 | |
73dec95e TU |
1892 | cs = intel_ring_begin(req, 4); |
1893 | if (IS_ERR(cs)) | |
1894 | return PTR_ERR(cs); | |
b72f3acb | 1895 | |
71a77e07 | 1896 | cmd = MI_FLUSH_DW; |
c033666a | 1897 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1898 | cmd += 1; |
f0a1fb10 CW |
1899 | |
1900 | /* We always require a command barrier so that subsequent | |
1901 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1902 | * wrt the contents of the write cache being flushed to memory | |
1903 | * (and thus being coherent from the CPU). | |
1904 | */ | |
1905 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1906 | ||
9a289771 JB |
1907 | /* |
1908 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1909 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1910 | * operation is complete. This bit is only valid when the | |
1911 | * Post-Sync Operation field is a value of 1h or 3h." | |
1912 | */ | |
7c9cf4e3 | 1913 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1914 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1915 | *cs++ = cmd; |
1916 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1917 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1918 | *cs++ = 0; /* upper addr */ |
1919 | *cs++ = 0; /* value */ | |
075b3bba | 1920 | } else { |
73dec95e TU |
1921 | *cs++ = 0; |
1922 | *cs++ = MI_NOOP; | |
075b3bba | 1923 | } |
73dec95e | 1924 | intel_ring_advance(req, cs); |
fd3da6c9 | 1925 | |
b72f3acb | 1926 | return 0; |
8d19215b ZN |
1927 | } |
1928 | ||
d9a64610 TU |
1929 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1930 | struct intel_engine_cs *engine) | |
1931 | { | |
db3d4019 | 1932 | struct drm_i915_gem_object *obj; |
1b9e6650 | 1933 | int ret, i; |
db3d4019 | 1934 | |
39df9190 | 1935 | if (!i915.semaphores) |
db3d4019 TU |
1936 | return; |
1937 | ||
51d545d0 CW |
1938 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
1939 | struct i915_vma *vma; | |
1940 | ||
f51455d4 | 1941 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
1942 | if (IS_ERR(obj)) |
1943 | goto err; | |
db3d4019 | 1944 | |
a01cb37a | 1945 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
1946 | if (IS_ERR(vma)) |
1947 | goto err_obj; | |
1948 | ||
1949 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1950 | if (ret) | |
1951 | goto err_obj; | |
1952 | ||
1953 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1954 | if (ret) | |
1955 | goto err_obj; | |
1956 | ||
1957 | dev_priv->semaphore = vma; | |
1958 | } | |
d9a64610 TU |
1959 | |
1960 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 1961 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 1962 | |
ad7bdb2b | 1963 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 1964 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
1965 | |
1966 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 1967 | u32 ring_offset; |
1b9e6650 TU |
1968 | |
1969 | if (i != engine->id) | |
1970 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
1971 | else | |
1972 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
1973 | ||
1974 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
1975 | } | |
d9a64610 | 1976 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 1977 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 1978 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
1979 | |
1980 | /* | |
1981 | * The current semaphore is only applied on pre-gen8 | |
1982 | * platform. And there is no VCS2 ring on the pre-gen8 | |
1983 | * platform. So the semaphore between RCS and VCS2 is | |
1984 | * initialized as INVALID. Gen8 will initialize the | |
1985 | * sema between VCS2 and RCS later. | |
1986 | */ | |
318f89ca | 1987 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
1988 | static const struct { |
1989 | u32 wait_mbox; | |
1990 | i915_reg_t mbox_reg; | |
318f89ca TU |
1991 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
1992 | [RCS_HW] = { | |
1993 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
1994 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
1995 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 1996 | }, |
318f89ca TU |
1997 | [VCS_HW] = { |
1998 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
1999 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2000 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2001 | }, |
318f89ca TU |
2002 | [BCS_HW] = { |
2003 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2004 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2005 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2006 | }, |
318f89ca TU |
2007 | [VECS_HW] = { |
2008 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2009 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2010 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2011 | }, |
2012 | }; | |
2013 | u32 wait_mbox; | |
2014 | i915_reg_t mbox_reg; | |
2015 | ||
318f89ca | 2016 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2017 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2018 | mbox_reg = GEN6_NOSYNC; | |
2019 | } else { | |
318f89ca TU |
2020 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2021 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2022 | } |
2023 | ||
2024 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2025 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2026 | } | |
d9a64610 | 2027 | } |
51d545d0 CW |
2028 | |
2029 | return; | |
2030 | ||
2031 | err_obj: | |
2032 | i915_gem_object_put(obj); | |
2033 | err: | |
2034 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2035 | i915.semaphores = 0; | |
d9a64610 TU |
2036 | } |
2037 | ||
ed003078 CW |
2038 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2039 | struct intel_engine_cs *engine) | |
2040 | { | |
c78d6061 TU |
2041 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2042 | ||
ed003078 | 2043 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2044 | engine->irq_enable = gen8_irq_enable; |
2045 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2046 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2047 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2048 | engine->irq_enable = gen6_irq_enable; |
2049 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2050 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2051 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2052 | engine->irq_enable = gen5_irq_enable; |
2053 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2054 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2055 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2056 | engine->irq_enable = i9xx_irq_enable; |
2057 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2058 | } else { |
31bb59cc CW |
2059 | engine->irq_enable = i8xx_irq_enable; |
2060 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2061 | } |
2062 | } | |
2063 | ||
06a2fe22 TU |
2064 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2065 | struct intel_engine_cs *engine) | |
2066 | { | |
618e4ca7 CW |
2067 | intel_ring_init_irq(dev_priv, engine); |
2068 | intel_ring_init_semaphores(dev_priv, engine); | |
2069 | ||
1d8a1337 | 2070 | engine->init_hw = init_ring_common; |
821ed7df | 2071 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2072 | |
e8a9c58f CW |
2073 | engine->context_pin = intel_ring_context_pin; |
2074 | engine->context_unpin = intel_ring_context_unpin; | |
2075 | ||
f73e7399 CW |
2076 | engine->request_alloc = ring_request_alloc; |
2077 | ||
9b81d556 | 2078 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d CW |
2079 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
2080 | if (i915.semaphores) { | |
2081 | int num_rings; | |
2082 | ||
9b81d556 | 2083 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d CW |
2084 | |
2085 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2086 | if (INTEL_GEN(dev_priv) >= 8) { | |
2087 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2088 | } else { | |
2089 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2090 | if (num_rings & 1) | |
2091 | engine->emit_breadcrumb_sz++; | |
2092 | } | |
2093 | } | |
ddd66c51 | 2094 | engine->submit_request = i9xx_submit_request; |
6f7bef75 CW |
2095 | |
2096 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2097 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2098 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2099 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2100 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2101 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2102 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2103 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2104 | else |
803688ba | 2105 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2106 | } |
2107 | ||
8b3e2d36 | 2108 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2109 | { |
8b3e2d36 | 2110 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2111 | int ret; |
5c1143bb | 2112 | |
06a2fe22 TU |
2113 | intel_ring_default_vfuncs(dev_priv, engine); |
2114 | ||
61ff75ac CW |
2115 | if (HAS_L3_DPF(dev_priv)) |
2116 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2117 | |
c033666a | 2118 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2119 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2120 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2121 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2122 | engine->emit_flush = gen8_render_ring_flush; |
98f29e8d CW |
2123 | if (i915.semaphores) { |
2124 | int num_rings; | |
2125 | ||
e2f80391 | 2126 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d CW |
2127 | |
2128 | num_rings = | |
2129 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2130 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2131 | } | |
c033666a | 2132 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2133 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2134 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2135 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2136 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2137 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2138 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2139 | } else { |
c033666a | 2140 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2141 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2142 | else |
c7fe7d25 | 2143 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2144 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2145 | } |
707d9cf9 | 2146 | |
c033666a | 2147 | if (IS_HASWELL(dev_priv)) |
803688ba | 2148 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2149 | |
e2f80391 TU |
2150 | engine->init_hw = init_render_ring; |
2151 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2152 | |
acd27845 | 2153 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2154 | if (ret) |
2155 | return ret; | |
2156 | ||
f8973c21 | 2157 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2158 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2159 | if (ret) |
2160 | return ret; | |
2161 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2162 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2163 | if (ret) |
2164 | return ret; | |
2165 | } | |
2166 | ||
2167 | return 0; | |
5c1143bb XH |
2168 | } |
2169 | ||
8b3e2d36 | 2170 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2171 | { |
8b3e2d36 | 2172 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2173 | |
06a2fe22 TU |
2174 | intel_ring_default_vfuncs(dev_priv, engine); |
2175 | ||
c033666a | 2176 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2177 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2178 | if (IS_GEN6(dev_priv)) |
c5efa1ad | 2179 | engine->submit_request = gen6_bsd_submit_request; |
c7fe7d25 | 2180 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2181 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2182 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2183 | } else { |
e2f80391 | 2184 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2185 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2186 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2187 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2188 | else |
e2f80391 | 2189 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2190 | } |
58fa3835 | 2191 | |
acd27845 | 2192 | return intel_init_ring_buffer(engine); |
5c1143bb | 2193 | } |
549f7365 | 2194 | |
845f74a7 | 2195 | /** |
62659920 | 2196 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2197 | */ |
8b3e2d36 | 2198 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2199 | { |
8b3e2d36 | 2200 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2201 | |
2202 | intel_ring_default_vfuncs(dev_priv, engine); | |
2203 | ||
c7fe7d25 | 2204 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2205 | |
acd27845 | 2206 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2207 | } |
2208 | ||
8b3e2d36 | 2209 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2210 | { |
8b3e2d36 | 2211 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2212 | |
2213 | intel_ring_default_vfuncs(dev_priv, engine); | |
2214 | ||
c7fe7d25 | 2215 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2216 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2217 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2218 | |
acd27845 | 2219 | return intel_init_ring_buffer(engine); |
549f7365 | 2220 | } |
a7b9761d | 2221 | |
8b3e2d36 | 2222 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2223 | { |
8b3e2d36 | 2224 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2225 | |
2226 | intel_ring_default_vfuncs(dev_priv, engine); | |
2227 | ||
c7fe7d25 | 2228 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2229 | |
c78d6061 | 2230 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2231 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2232 | engine->irq_enable = hsw_vebox_irq_enable; |
2233 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2234 | } |
9a8a2213 | 2235 | |
acd27845 | 2236 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2237 | } |