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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
ebd0fd4b DG |
50 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
51 | { | |
52 | if (ringbuf->last_retired_head != -1) { | |
53 | ringbuf->head = ringbuf->last_retired_head; | |
54 | ringbuf->last_retired_head = -1; | |
55 | } | |
56 | ||
57 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
58 | ringbuf->tail, ringbuf->size); | |
59 | } | |
60 | ||
117897f4 | 61 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 62 | { |
0bc40be8 | 63 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
666796da | 64 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 65 | } |
09246732 | 66 | |
0bc40be8 | 67 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 68 | { |
0bc40be8 | 69 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 70 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 71 | if (intel_engine_stopped(engine)) |
09246732 | 72 | return; |
0bc40be8 | 73 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
74 | } |
75 | ||
b72f3acb | 76 | static int |
a84c3ae1 | 77 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
78 | u32 invalidate_domains, |
79 | u32 flush_domains) | |
80 | { | |
4a570db5 | 81 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
82 | u32 cmd; |
83 | int ret; | |
84 | ||
85 | cmd = MI_FLUSH; | |
31b14c9f | 86 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
87 | cmd |= MI_NO_WRITE_FLUSH; |
88 | ||
89 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
90 | cmd |= MI_READ_FLUSH; | |
91 | ||
5fb9de1a | 92 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
93 | if (ret) |
94 | return ret; | |
95 | ||
e2f80391 TU |
96 | intel_ring_emit(engine, cmd); |
97 | intel_ring_emit(engine, MI_NOOP); | |
98 | intel_ring_advance(engine); | |
46f0f8d1 CW |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | static int | |
a84c3ae1 | 104 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
105 | u32 invalidate_domains, |
106 | u32 flush_domains) | |
62fdfeaf | 107 | { |
4a570db5 | 108 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 109 | struct drm_device *dev = engine->dev; |
6f392d54 | 110 | u32 cmd; |
b72f3acb | 111 | int ret; |
6f392d54 | 112 | |
36d527de CW |
113 | /* |
114 | * read/write caches: | |
115 | * | |
116 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
117 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
118 | * also flushed at 2d versus 3d pipeline switches. | |
119 | * | |
120 | * read-only caches: | |
121 | * | |
122 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
123 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
124 | * | |
125 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
126 | * | |
127 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
128 | * invalidated when MI_EXE_FLUSH is set. | |
129 | * | |
130 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
131 | * invalidated with every MI_FLUSH. | |
132 | * | |
133 | * TLBs: | |
134 | * | |
135 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
136 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
137 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
138 | * are flushed at any MI_FLUSH. | |
139 | */ | |
140 | ||
141 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 142 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 143 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
144 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
145 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 146 | |
36d527de CW |
147 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
148 | (IS_G4X(dev) || IS_GEN5(dev))) | |
149 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 150 | |
5fb9de1a | 151 | ret = intel_ring_begin(req, 2); |
36d527de CW |
152 | if (ret) |
153 | return ret; | |
b72f3acb | 154 | |
e2f80391 TU |
155 | intel_ring_emit(engine, cmd); |
156 | intel_ring_emit(engine, MI_NOOP); | |
157 | intel_ring_advance(engine); | |
b72f3acb CW |
158 | |
159 | return 0; | |
8187a2b7 ZN |
160 | } |
161 | ||
8d315287 JB |
162 | /** |
163 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
164 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
165 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
166 | * | |
167 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
168 | * produced by non-pipelined state commands), software needs to first | |
169 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
170 | * 0. | |
171 | * | |
172 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
173 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
174 | * | |
175 | * And the workaround for these two requires this workaround first: | |
176 | * | |
177 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
178 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
179 | * flushes. | |
180 | * | |
181 | * And this last workaround is tricky because of the requirements on | |
182 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
183 | * volume 2 part 1: | |
184 | * | |
185 | * "1 of the following must also be set: | |
186 | * - Render Target Cache Flush Enable ([12] of DW1) | |
187 | * - Depth Cache Flush Enable ([0] of DW1) | |
188 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
189 | * - Depth Stall ([13] of DW1) | |
190 | * - Post-Sync Operation ([13] of DW1) | |
191 | * - Notify Enable ([8] of DW1)" | |
192 | * | |
193 | * The cache flushes require the workaround flush that triggered this | |
194 | * one, so we can't use it. Depth stall would trigger the same. | |
195 | * Post-sync nonzero is what triggered this second workaround, so we | |
196 | * can't use that one either. Notify enable is IRQs, which aren't | |
197 | * really our business. That leaves only stall at scoreboard. | |
198 | */ | |
199 | static int | |
f2cf1fcc | 200 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 201 | { |
4a570db5 | 202 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 203 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
204 | int ret; |
205 | ||
5fb9de1a | 206 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
207 | if (ret) |
208 | return ret; | |
209 | ||
e2f80391 TU |
210 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
211 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 212 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
213 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
214 | intel_ring_emit(engine, 0); /* low dword */ | |
215 | intel_ring_emit(engine, 0); /* high dword */ | |
216 | intel_ring_emit(engine, MI_NOOP); | |
217 | intel_ring_advance(engine); | |
8d315287 | 218 | |
5fb9de1a | 219 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
220 | if (ret) |
221 | return ret; | |
222 | ||
e2f80391 TU |
223 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
224 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
225 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
226 | intel_ring_emit(engine, 0); | |
227 | intel_ring_emit(engine, 0); | |
228 | intel_ring_emit(engine, MI_NOOP); | |
229 | intel_ring_advance(engine); | |
8d315287 JB |
230 | |
231 | return 0; | |
232 | } | |
233 | ||
234 | static int | |
a84c3ae1 JH |
235 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
236 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 237 | { |
4a570db5 | 238 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 239 | u32 flags = 0; |
e2f80391 | 240 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
241 | int ret; |
242 | ||
b3111509 | 243 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 244 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
245 | if (ret) |
246 | return ret; | |
247 | ||
8d315287 JB |
248 | /* Just flush everything. Experiments have shown that reducing the |
249 | * number of bits based on the write domains has little performance | |
250 | * impact. | |
251 | */ | |
7d54a904 CW |
252 | if (flush_domains) { |
253 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
254 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
255 | /* | |
256 | * Ensure that any following seqno writes only happen | |
257 | * when the render cache is indeed flushed. | |
258 | */ | |
97f209bc | 259 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
260 | } |
261 | if (invalidate_domains) { | |
262 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
263 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
264 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
265 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
267 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
268 | /* | |
269 | * TLB invalidate requires a post-sync write. | |
270 | */ | |
3ac78313 | 271 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 272 | } |
8d315287 | 273 | |
5fb9de1a | 274 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
275 | if (ret) |
276 | return ret; | |
277 | ||
e2f80391 TU |
278 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
279 | intel_ring_emit(engine, flags); | |
280 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
281 | intel_ring_emit(engine, 0); | |
282 | intel_ring_advance(engine); | |
8d315287 JB |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
f3987631 | 287 | static int |
f2cf1fcc | 288 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 289 | { |
4a570db5 | 290 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
291 | int ret; |
292 | ||
5fb9de1a | 293 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
294 | if (ret) |
295 | return ret; | |
296 | ||
e2f80391 TU |
297 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
298 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 299 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
300 | intel_ring_emit(engine, 0); |
301 | intel_ring_emit(engine, 0); | |
302 | intel_ring_advance(engine); | |
f3987631 PZ |
303 | |
304 | return 0; | |
305 | } | |
306 | ||
4772eaeb | 307 | static int |
a84c3ae1 | 308 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
309 | u32 invalidate_domains, u32 flush_domains) |
310 | { | |
4a570db5 | 311 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 312 | u32 flags = 0; |
e2f80391 | 313 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
314 | int ret; |
315 | ||
f3987631 PZ |
316 | /* |
317 | * Ensure that any following seqno writes only happen when the render | |
318 | * cache is indeed flushed. | |
319 | * | |
320 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
321 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
322 | * don't try to be clever and just set it unconditionally. | |
323 | */ | |
324 | flags |= PIPE_CONTROL_CS_STALL; | |
325 | ||
4772eaeb PZ |
326 | /* Just flush everything. Experiments have shown that reducing the |
327 | * number of bits based on the write domains has little performance | |
328 | * impact. | |
329 | */ | |
330 | if (flush_domains) { | |
331 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
332 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 333 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 334 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
335 | } |
336 | if (invalidate_domains) { | |
337 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
338 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
339 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
340 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
341 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
342 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 343 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
344 | /* |
345 | * TLB invalidate requires a post-sync write. | |
346 | */ | |
347 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 348 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 349 | |
add284a3 CW |
350 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
351 | ||
f3987631 PZ |
352 | /* Workaround: we must issue a pipe_control with CS-stall bit |
353 | * set before a pipe_control command that has the state cache | |
354 | * invalidate bit set. */ | |
f2cf1fcc | 355 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
356 | } |
357 | ||
5fb9de1a | 358 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
359 | if (ret) |
360 | return ret; | |
361 | ||
e2f80391 TU |
362 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
363 | intel_ring_emit(engine, flags); | |
364 | intel_ring_emit(engine, scratch_addr); | |
365 | intel_ring_emit(engine, 0); | |
366 | intel_ring_advance(engine); | |
4772eaeb PZ |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
884ceace | 371 | static int |
f2cf1fcc | 372 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
373 | u32 flags, u32 scratch_addr) |
374 | { | |
4a570db5 | 375 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
376 | int ret; |
377 | ||
5fb9de1a | 378 | ret = intel_ring_begin(req, 6); |
884ceace KG |
379 | if (ret) |
380 | return ret; | |
381 | ||
e2f80391 TU |
382 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
383 | intel_ring_emit(engine, flags); | |
384 | intel_ring_emit(engine, scratch_addr); | |
385 | intel_ring_emit(engine, 0); | |
386 | intel_ring_emit(engine, 0); | |
387 | intel_ring_emit(engine, 0); | |
388 | intel_ring_advance(engine); | |
884ceace KG |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
a5f3d68e | 393 | static int |
a84c3ae1 | 394 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
395 | u32 invalidate_domains, u32 flush_domains) |
396 | { | |
397 | u32 flags = 0; | |
4a570db5 | 398 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 399 | int ret; |
a5f3d68e BW |
400 | |
401 | flags |= PIPE_CONTROL_CS_STALL; | |
402 | ||
403 | if (flush_domains) { | |
404 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
405 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 406 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 407 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
408 | } |
409 | if (invalidate_domains) { | |
410 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
412 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
413 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
414 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
415 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
416 | flags |= PIPE_CONTROL_QW_WRITE; | |
417 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
418 | |
419 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 420 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
421 | PIPE_CONTROL_CS_STALL | |
422 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
423 | 0); | |
424 | if (ret) | |
425 | return ret; | |
a5f3d68e BW |
426 | } |
427 | ||
f2cf1fcc | 428 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
429 | } |
430 | ||
0bc40be8 | 431 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 432 | u32 value) |
d46eefa2 | 433 | { |
0bc40be8 TU |
434 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
435 | I915_WRITE_TAIL(engine, value); | |
d46eefa2 XH |
436 | } |
437 | ||
0bc40be8 | 438 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 439 | { |
0bc40be8 | 440 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
50877445 | 441 | u64 acthd; |
8187a2b7 | 442 | |
0bc40be8 TU |
443 | if (INTEL_INFO(engine->dev)->gen >= 8) |
444 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
445 | RING_ACTHD_UDW(engine->mmio_base)); | |
446 | else if (INTEL_INFO(engine->dev)->gen >= 4) | |
447 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
50877445 CW |
448 | else |
449 | acthd = I915_READ(ACTHD); | |
450 | ||
451 | return acthd; | |
8187a2b7 ZN |
452 | } |
453 | ||
0bc40be8 | 454 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 455 | { |
0bc40be8 | 456 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
035dc1e0 DV |
457 | u32 addr; |
458 | ||
459 | addr = dev_priv->status_page_dmah->busaddr; | |
0bc40be8 | 460 | if (INTEL_INFO(engine->dev)->gen >= 4) |
035dc1e0 DV |
461 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
462 | I915_WRITE(HWS_PGA, addr); | |
463 | } | |
464 | ||
0bc40be8 | 465 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 466 | { |
0bc40be8 TU |
467 | struct drm_device *dev = engine->dev; |
468 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
f0f59a00 | 469 | i915_reg_t mmio; |
af75f269 DL |
470 | |
471 | /* The ring status page addresses are no longer next to the rest of | |
472 | * the ring registers as of gen7. | |
473 | */ | |
474 | if (IS_GEN7(dev)) { | |
0bc40be8 | 475 | switch (engine->id) { |
af75f269 DL |
476 | case RCS: |
477 | mmio = RENDER_HWS_PGA_GEN7; | |
478 | break; | |
479 | case BCS: | |
480 | mmio = BLT_HWS_PGA_GEN7; | |
481 | break; | |
482 | /* | |
483 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
484 | * gcc switch check warning | |
485 | */ | |
486 | case VCS2: | |
487 | case VCS: | |
488 | mmio = BSD_HWS_PGA_GEN7; | |
489 | break; | |
490 | case VECS: | |
491 | mmio = VEBOX_HWS_PGA_GEN7; | |
492 | break; | |
493 | } | |
0bc40be8 TU |
494 | } else if (IS_GEN6(engine->dev)) { |
495 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); | |
af75f269 DL |
496 | } else { |
497 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 498 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
499 | } |
500 | ||
0bc40be8 | 501 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
502 | POSTING_READ(mmio); |
503 | ||
504 | /* | |
505 | * Flush the TLB for this page | |
506 | * | |
507 | * FIXME: These two bits have disappeared on gen8, so a question | |
508 | * arises: do we still need this and if so how should we go about | |
509 | * invalidating the TLB? | |
510 | */ | |
511 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
0bc40be8 | 512 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
513 | |
514 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 515 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
516 | |
517 | I915_WRITE(reg, | |
518 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
519 | INSTPM_SYNC_FLUSH)); | |
520 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
521 | 1000)) | |
522 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
0bc40be8 | 523 | engine->name); |
af75f269 DL |
524 | } |
525 | } | |
526 | ||
0bc40be8 | 527 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 528 | { |
0bc40be8 | 529 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
8187a2b7 | 530 | |
0bc40be8 TU |
531 | if (!IS_GEN2(engine->dev)) { |
532 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); | |
533 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
534 | DRM_ERROR("%s : timed out trying to stop ring\n", | |
535 | engine->name); | |
9bec9b13 CW |
536 | /* Sometimes we observe that the idle flag is not |
537 | * set even though the ring is empty. So double | |
538 | * check before giving up. | |
539 | */ | |
0bc40be8 | 540 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 541 | return false; |
9991ae78 CW |
542 | } |
543 | } | |
b7884eb4 | 544 | |
0bc40be8 TU |
545 | I915_WRITE_CTL(engine, 0); |
546 | I915_WRITE_HEAD(engine, 0); | |
547 | engine->write_tail(engine, 0); | |
8187a2b7 | 548 | |
0bc40be8 TU |
549 | if (!IS_GEN2(engine->dev)) { |
550 | (void)I915_READ_CTL(engine); | |
551 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 552 | } |
a51435a3 | 553 | |
0bc40be8 | 554 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 555 | } |
8187a2b7 | 556 | |
fc0768ce TE |
557 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
558 | { | |
559 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
560 | } | |
561 | ||
0bc40be8 | 562 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 563 | { |
0bc40be8 | 564 | struct drm_device *dev = engine->dev; |
9991ae78 | 565 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 566 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 567 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
568 | int ret = 0; |
569 | ||
59bad947 | 570 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 571 | |
0bc40be8 | 572 | if (!stop_ring(engine)) { |
9991ae78 | 573 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
574 | DRM_DEBUG_KMS("%s head not reset to zero " |
575 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
576 | engine->name, |
577 | I915_READ_CTL(engine), | |
578 | I915_READ_HEAD(engine), | |
579 | I915_READ_TAIL(engine), | |
580 | I915_READ_START(engine)); | |
8187a2b7 | 581 | |
0bc40be8 | 582 | if (!stop_ring(engine)) { |
6fd0d56e CW |
583 | DRM_ERROR("failed to set %s head to zero " |
584 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
585 | engine->name, |
586 | I915_READ_CTL(engine), | |
587 | I915_READ_HEAD(engine), | |
588 | I915_READ_TAIL(engine), | |
589 | I915_READ_START(engine)); | |
9991ae78 CW |
590 | ret = -EIO; |
591 | goto out; | |
6fd0d56e | 592 | } |
8187a2b7 ZN |
593 | } |
594 | ||
9991ae78 | 595 | if (I915_NEED_GFX_HWS(dev)) |
0bc40be8 | 596 | intel_ring_setup_status_page(engine); |
9991ae78 | 597 | else |
0bc40be8 | 598 | ring_setup_phys_status_page(engine); |
9991ae78 | 599 | |
ece4a17d | 600 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 601 | I915_READ_HEAD(engine); |
ece4a17d | 602 | |
0d8957c8 DV |
603 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
604 | * registers with the above sequence (the readback of the HEAD registers | |
605 | * also enforces ordering), otherwise the hw might lose the new ring | |
606 | * register values. */ | |
0bc40be8 | 607 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
608 | |
609 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 610 | if (I915_READ_HEAD(engine)) |
95468892 | 611 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
612 | engine->name, I915_READ_HEAD(engine)); |
613 | I915_WRITE_HEAD(engine, 0); | |
614 | (void)I915_READ_HEAD(engine); | |
95468892 | 615 | |
0bc40be8 | 616 | I915_WRITE_CTL(engine, |
93b0a4e0 | 617 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 618 | | RING_VALID); |
8187a2b7 | 619 | |
8187a2b7 | 620 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
621 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
622 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
623 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 624 | DRM_ERROR("%s initialization failed " |
48e48a0b | 625 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
626 | engine->name, |
627 | I915_READ_CTL(engine), | |
628 | I915_READ_CTL(engine) & RING_VALID, | |
629 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
630 | I915_READ_START(engine), | |
631 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
632 | ret = -EIO; |
633 | goto out; | |
8187a2b7 ZN |
634 | } |
635 | ||
ebd0fd4b | 636 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
637 | ringbuf->head = I915_READ_HEAD(engine); |
638 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 639 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 640 | |
fc0768ce | 641 | intel_engine_init_hangcheck(engine); |
50f018df | 642 | |
b7884eb4 | 643 | out: |
59bad947 | 644 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
645 | |
646 | return ret; | |
8187a2b7 ZN |
647 | } |
648 | ||
9b1136d5 | 649 | void |
0bc40be8 | 650 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 651 | { |
0bc40be8 | 652 | struct drm_device *dev = engine->dev; |
9b1136d5 | 653 | |
0bc40be8 | 654 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
655 | return; |
656 | ||
657 | if (INTEL_INFO(dev)->gen >= 5) { | |
0bc40be8 TU |
658 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
659 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
660 | } |
661 | ||
0bc40be8 TU |
662 | drm_gem_object_unreference(&engine->scratch.obj->base); |
663 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
664 | } |
665 | ||
666 | int | |
0bc40be8 | 667 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 668 | { |
c6df541c CW |
669 | int ret; |
670 | ||
0bc40be8 | 671 | WARN_ON(engine->scratch.obj); |
c6df541c | 672 | |
d37cd8a8 | 673 | engine->scratch.obj = i915_gem_object_create(engine->dev, 4096); |
fe3db79b | 674 | if (IS_ERR(engine->scratch.obj)) { |
c6df541c | 675 | DRM_ERROR("Failed to allocate seqno page\n"); |
fe3db79b CW |
676 | ret = PTR_ERR(engine->scratch.obj); |
677 | engine->scratch.obj = NULL; | |
c6df541c CW |
678 | goto err; |
679 | } | |
e4ffd173 | 680 | |
0bc40be8 TU |
681 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
682 | I915_CACHE_LLC); | |
a9cc726c DV |
683 | if (ret) |
684 | goto err_unref; | |
c6df541c | 685 | |
0bc40be8 | 686 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
687 | if (ret) |
688 | goto err_unref; | |
689 | ||
0bc40be8 TU |
690 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
691 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
692 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 693 | ret = -ENOMEM; |
c6df541c | 694 | goto err_unpin; |
56b085a0 | 695 | } |
c6df541c | 696 | |
2b1086cc | 697 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 698 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
699 | return 0; |
700 | ||
701 | err_unpin: | |
0bc40be8 | 702 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 703 | err_unref: |
0bc40be8 | 704 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 705 | err: |
c6df541c CW |
706 | return ret; |
707 | } | |
708 | ||
e2be4faf | 709 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 710 | { |
7225342a | 711 | int ret, i; |
4a570db5 | 712 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 713 | struct drm_device *dev = engine->dev; |
888b5995 | 714 | struct drm_i915_private *dev_priv = dev->dev_private; |
7225342a | 715 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 716 | |
02235808 | 717 | if (w->count == 0) |
7225342a | 718 | return 0; |
888b5995 | 719 | |
e2f80391 | 720 | engine->gpu_caches_dirty = true; |
4866d729 | 721 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
722 | if (ret) |
723 | return ret; | |
888b5995 | 724 | |
5fb9de1a | 725 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
726 | if (ret) |
727 | return ret; | |
728 | ||
e2f80391 | 729 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 730 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
731 | intel_ring_emit_reg(engine, w->reg[i].addr); |
732 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 733 | } |
e2f80391 | 734 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 735 | |
e2f80391 | 736 | intel_ring_advance(engine); |
7225342a | 737 | |
e2f80391 | 738 | engine->gpu_caches_dirty = true; |
4866d729 | 739 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
740 | if (ret) |
741 | return ret; | |
888b5995 | 742 | |
7225342a | 743 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 744 | |
7225342a | 745 | return 0; |
86d7f238 AS |
746 | } |
747 | ||
8753181e | 748 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
749 | { |
750 | int ret; | |
751 | ||
e2be4faf | 752 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
753 | if (ret != 0) |
754 | return ret; | |
755 | ||
be01363f | 756 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 757 | if (ret) |
e26e1b97 | 758 | return ret; |
8f0e2b9d | 759 | |
e26e1b97 | 760 | return 0; |
8f0e2b9d DV |
761 | } |
762 | ||
7225342a | 763 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
764 | i915_reg_t addr, |
765 | const u32 mask, const u32 val) | |
7225342a MK |
766 | { |
767 | const u32 idx = dev_priv->workarounds.count; | |
768 | ||
769 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
770 | return -ENOSPC; | |
771 | ||
772 | dev_priv->workarounds.reg[idx].addr = addr; | |
773 | dev_priv->workarounds.reg[idx].value = val; | |
774 | dev_priv->workarounds.reg[idx].mask = mask; | |
775 | ||
776 | dev_priv->workarounds.count++; | |
777 | ||
778 | return 0; | |
86d7f238 AS |
779 | } |
780 | ||
ca5a0fbd | 781 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 782 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
783 | if (r) \ |
784 | return r; \ | |
ca5a0fbd | 785 | } while (0) |
7225342a MK |
786 | |
787 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 788 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
789 | |
790 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 791 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 792 | |
98533251 | 793 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 794 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 795 | |
cf4b0de6 DL |
796 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
797 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 798 | |
cf4b0de6 | 799 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 800 | |
0bc40be8 TU |
801 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
802 | i915_reg_t reg) | |
33136b06 | 803 | { |
0bc40be8 | 804 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
33136b06 | 805 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 806 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
807 | |
808 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
809 | return -EINVAL; | |
810 | ||
0bc40be8 | 811 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 812 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 813 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
814 | |
815 | return 0; | |
816 | } | |
817 | ||
0bc40be8 | 818 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 819 | { |
0bc40be8 | 820 | struct drm_device *dev = engine->dev; |
68c6198b AS |
821 | struct drm_i915_private *dev_priv = dev->dev_private; |
822 | ||
823 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 824 | |
717d84d6 AS |
825 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
826 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
827 | ||
d0581194 AS |
828 | /* WaDisablePartialInstShootdown:bdw,chv */ |
829 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
830 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
831 | ||
a340af58 AS |
832 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
833 | * workaround for for a possible hang in the unlikely event a TLB | |
834 | * invalidation occurs during a PSD flush. | |
835 | */ | |
836 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 837 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 838 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 839 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
840 | HDC_FORCE_NON_COHERENT); |
841 | ||
6def8fdd AS |
842 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
843 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
844 | * polygons in the same 8x4 pixel/sample area to be processed without | |
845 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
846 | * buffer." | |
847 | * | |
848 | * This optimization is off by default for BDW and CHV; turn it on. | |
849 | */ | |
850 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
851 | ||
48404636 AS |
852 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
853 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
854 | ||
7eebcde6 AS |
855 | /* |
856 | * BSpec recommends 8x4 when MSAA is used, | |
857 | * however in practice 16x4 seems fastest. | |
858 | * | |
859 | * Note that PS/WM thread counts depend on the WIZ hashing | |
860 | * disable bit, which we don't touch here, but it's good | |
861 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
862 | */ | |
863 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
864 | GEN6_WIZ_HASHING_MASK, | |
865 | GEN6_WIZ_HASHING_16x4); | |
866 | ||
e9a64ada AS |
867 | return 0; |
868 | } | |
869 | ||
0bc40be8 | 870 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 871 | { |
e9a64ada | 872 | int ret; |
0bc40be8 | 873 | struct drm_device *dev = engine->dev; |
888b5995 | 874 | struct drm_i915_private *dev_priv = dev->dev_private; |
86d7f238 | 875 | |
0bc40be8 | 876 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
877 | if (ret) |
878 | return ret; | |
879 | ||
101b376d | 880 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 881 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 882 | |
101b376d | 883 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
884 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
885 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 886 | |
7225342a MK |
887 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
888 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 889 | |
7225342a | 890 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
891 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
892 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 893 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 894 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 895 | |
86d7f238 AS |
896 | return 0; |
897 | } | |
898 | ||
0bc40be8 | 899 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 900 | { |
e9a64ada | 901 | int ret; |
0bc40be8 | 902 | struct drm_device *dev = engine->dev; |
00e1e623 VS |
903 | struct drm_i915_private *dev_priv = dev->dev_private; |
904 | ||
0bc40be8 | 905 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
906 | if (ret) |
907 | return ret; | |
908 | ||
00e1e623 | 909 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 910 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 911 | |
d60de81d KG |
912 | /* Improve HiZ throughput on CHV. */ |
913 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
914 | ||
7225342a MK |
915 | return 0; |
916 | } | |
917 | ||
0bc40be8 | 918 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 919 | { |
0bc40be8 | 920 | struct drm_device *dev = engine->dev; |
ab0dfafe | 921 | struct drm_i915_private *dev_priv = dev->dev_private; |
8ea6f892 | 922 | uint32_t tmp; |
e0f3fa09 | 923 | int ret; |
ab0dfafe | 924 | |
9c4cbf82 MK |
925 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
926 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
927 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
928 | ||
929 | /* WaDisableKillLogic:bxt,skl */ | |
930 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
931 | ECOCHK_DIS_TLB); | |
932 | ||
950b2aae | 933 | /* WaClearFlowControlGpgpuContextSave:skl,bxt */ |
b0e6f6d4 | 934 | /* WaDisablePartialInstShootdown:skl,bxt */ |
ab0dfafe | 935 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 936 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
937 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
938 | ||
a119a6e6 | 939 | /* Syncing dependencies between camera and graphics:skl,bxt */ |
8424171e NH |
940 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
941 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
942 | ||
e87a005d JN |
943 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
944 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
945 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
946 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
947 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 948 | |
e87a005d JN |
949 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
950 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
951 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
952 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
953 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
954 | /* |
955 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
956 | * but we do that in per ctx batchbuffer as there is an issue | |
957 | * with this register not getting restored on ctx restore | |
958 | */ | |
183c6dac DL |
959 | } |
960 | ||
e87a005d | 961 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */ |
bfd8ad4e TG |
962 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt */ |
963 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, | |
964 | GEN9_ENABLE_YV12_BUGFIX | | |
965 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 966 | |
5068368c | 967 | /* Wa4x4STCOptimizationDisable:skl,bxt */ |
27160c96 | 968 | /* WaDisablePartialResolveInVc:skl,bxt */ |
60294683 AS |
969 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
970 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 971 | |
16be17af | 972 | /* WaCcsTlbPrefetchDisable:skl,bxt */ |
e2db7071 DL |
973 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
974 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
975 | ||
5a2ae95e | 976 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
977 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
978 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
979 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
980 | PIXEL_MASK_CAMMING_DISABLE); | |
981 | ||
8ea6f892 ID |
982 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt */ |
983 | tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; | |
97ea6be1 | 984 | if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) || |
e87a005d | 985 | IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) |
8ea6f892 ID |
986 | tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; |
987 | WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); | |
988 | ||
8c761609 | 989 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */ |
e87a005d | 990 | if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0)) |
8c761609 AS |
991 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
992 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 993 | |
6b6d5626 RB |
994 | /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
995 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); | |
996 | ||
6ecf56ae AS |
997 | /* WaOCLCoherentLineFlush:skl,bxt */ |
998 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | | |
999 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1000 | ||
e0f3fa09 | 1001 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
0bc40be8 | 1002 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1003 | if (ret) |
1004 | return ret; | |
1005 | ||
3669ab61 | 1006 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
0bc40be8 | 1007 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1008 | if (ret) |
1009 | return ret; | |
1010 | ||
3b106531 HN |
1011 | return 0; |
1012 | } | |
1013 | ||
0bc40be8 | 1014 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1015 | { |
0bc40be8 | 1016 | struct drm_device *dev = engine->dev; |
b7668791 DL |
1017 | struct drm_i915_private *dev_priv = dev->dev_private; |
1018 | u8 vals[3] = { 0, 0, 0 }; | |
1019 | unsigned int i; | |
1020 | ||
1021 | for (i = 0; i < 3; i++) { | |
1022 | u8 ss; | |
1023 | ||
1024 | /* | |
1025 | * Only consider slices where one, and only one, subslice has 7 | |
1026 | * EUs | |
1027 | */ | |
a4d8a0fe | 1028 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1029 | continue; |
1030 | ||
1031 | /* | |
1032 | * subslice_7eu[i] != 0 (because of the check above) and | |
1033 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1034 | * | |
1035 | * -> 0 <= ss <= 3; | |
1036 | */ | |
1037 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1038 | vals[i] = 3 - ss; | |
1039 | } | |
1040 | ||
1041 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1042 | return 0; | |
1043 | ||
1044 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1045 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1046 | GEN9_IZ_HASHING_MASK(2) | | |
1047 | GEN9_IZ_HASHING_MASK(1) | | |
1048 | GEN9_IZ_HASHING_MASK(0), | |
1049 | GEN9_IZ_HASHING(2, vals[2]) | | |
1050 | GEN9_IZ_HASHING(1, vals[1]) | | |
1051 | GEN9_IZ_HASHING(0, vals[0])); | |
1052 | ||
1053 | return 0; | |
1054 | } | |
1055 | ||
0bc40be8 | 1056 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1057 | { |
aa0011a8 | 1058 | int ret; |
0bc40be8 | 1059 | struct drm_device *dev = engine->dev; |
d0bbbc4f DL |
1060 | struct drm_i915_private *dev_priv = dev->dev_private; |
1061 | ||
0bc40be8 | 1062 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1063 | if (ret) |
1064 | return ret; | |
8d205494 | 1065 | |
a78536e7 AS |
1066 | /* |
1067 | * Actual WA is to disable percontext preemption granularity control | |
1068 | * until D0 which is the default case so this is equivalent to | |
1069 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1070 | */ | |
1071 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { | |
1072 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1073 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1074 | } | |
1075 | ||
e87a005d | 1076 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1077 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1078 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1079 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1080 | } | |
1081 | ||
1082 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1083 | * involving this register should also be added to WA batch as required. | |
1084 | */ | |
e87a005d | 1085 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1086 | /* WaDisableLSQCROPERFforOCL:skl */ |
1087 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1088 | GEN8_LQSC_RO_PERF_DIS); | |
1089 | ||
1090 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1091 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1092 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1093 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1094 | } | |
1095 | ||
d0bbbc4f | 1096 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1097 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1098 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1099 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1100 | ||
97ea6be1 MK |
1101 | /* This is tied to WaForceContextSaveRestoreNonCoherent */ |
1102 | if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) { | |
b62adbd1 NH |
1103 | /* |
1104 | *Use Force Non-Coherent whenever executing a 3D context. This | |
1105 | * is a workaround for a possible hang in the unlikely event | |
1106 | * a TLB invalidation occurs during a PSD flush. | |
1107 | */ | |
1108 | /* WaForceEnableNonCoherent:skl */ | |
1109 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1110 | HDC_FORCE_NON_COHERENT); | |
e238659d MK |
1111 | |
1112 | /* WaDisableHDCInvalidation:skl */ | |
1113 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
1114 | BDW_DISABLE_HDC_INVALIDATION); | |
b62adbd1 NH |
1115 | } |
1116 | ||
e87a005d JN |
1117 | /* WaBarrierPerformanceFixDisable:skl */ |
1118 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1119 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1120 | HDC_FENCE_DEST_SLM_DISABLE | | |
1121 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1122 | ||
9bd9dfb4 | 1123 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1124 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1125 | WA_SET_BIT_MASKED( |
1126 | GEN7_HALF_SLICE_CHICKEN1, | |
1127 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1128 | |
6107497e | 1129 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1130 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1131 | if (ret) |
1132 | return ret; | |
1133 | ||
0bc40be8 | 1134 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1135 | } |
1136 | ||
0bc40be8 | 1137 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1138 | { |
aa0011a8 | 1139 | int ret; |
0bc40be8 | 1140 | struct drm_device *dev = engine->dev; |
dfb601e6 NH |
1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
1142 | ||
0bc40be8 | 1143 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1144 | if (ret) |
1145 | return ret; | |
cae0437f | 1146 | |
9c4cbf82 MK |
1147 | /* WaStoreMultiplePTEenable:bxt */ |
1148 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1149 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1150 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1151 | ||
1152 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1153 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1154 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1155 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1156 | } | |
1157 | ||
dfb601e6 NH |
1158 | /* WaDisableThreadStallDopClockGating:bxt */ |
1159 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1160 | STALL_DOP_GATING_DISABLE); | |
1161 | ||
983b4b9d | 1162 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1163 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1164 | WA_SET_BIT_MASKED( |
1165 | GEN7_HALF_SLICE_CHICKEN1, | |
1166 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1167 | } | |
1168 | ||
2c8580e4 AS |
1169 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1170 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1171 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1172 | /* WaDisableLSQCROPERFforOCL:bxt */ |
2c8580e4 | 1173 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 | 1174 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1175 | if (ret) |
1176 | return ret; | |
a786d53a | 1177 | |
0bc40be8 | 1178 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1179 | if (ret) |
1180 | return ret; | |
2c8580e4 AS |
1181 | } |
1182 | ||
050fc465 TG |
1183 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
1184 | if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) | |
1185 | I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT); | |
1186 | ||
cae0437f NH |
1187 | return 0; |
1188 | } | |
1189 | ||
0bc40be8 | 1190 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1191 | { |
0bc40be8 | 1192 | struct drm_device *dev = engine->dev; |
7225342a MK |
1193 | struct drm_i915_private *dev_priv = dev->dev_private; |
1194 | ||
0bc40be8 | 1195 | WARN_ON(engine->id != RCS); |
7225342a MK |
1196 | |
1197 | dev_priv->workarounds.count = 0; | |
33136b06 | 1198 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a MK |
1199 | |
1200 | if (IS_BROADWELL(dev)) | |
0bc40be8 | 1201 | return bdw_init_workarounds(engine); |
7225342a MK |
1202 | |
1203 | if (IS_CHERRYVIEW(dev)) | |
0bc40be8 | 1204 | return chv_init_workarounds(engine); |
00e1e623 | 1205 | |
8d205494 | 1206 | if (IS_SKYLAKE(dev)) |
0bc40be8 | 1207 | return skl_init_workarounds(engine); |
cae0437f NH |
1208 | |
1209 | if (IS_BROXTON(dev)) | |
0bc40be8 | 1210 | return bxt_init_workarounds(engine); |
3b106531 | 1211 | |
00e1e623 VS |
1212 | return 0; |
1213 | } | |
1214 | ||
0bc40be8 | 1215 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1216 | { |
0bc40be8 | 1217 | struct drm_device *dev = engine->dev; |
1ec14ad3 | 1218 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 1219 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1220 | if (ret) |
1221 | return ret; | |
a69ffdbf | 1222 | |
61a563a2 AG |
1223 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1224 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1225 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1226 | |
1227 | /* We need to disable the AsyncFlip performance optimisations in order | |
1228 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1229 | * programmed to '1' on all products. | |
8693a824 | 1230 | * |
2441f877 | 1231 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1232 | */ |
2441f877 | 1233 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1234 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1235 | ||
f05bb0c7 | 1236 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1237 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1238 | if (INTEL_INFO(dev)->gen == 6) |
1239 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1240 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1241 | |
01fa0302 | 1242 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1243 | if (IS_GEN7(dev)) |
1244 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1245 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1246 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1247 | |
5e13a0c5 | 1248 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1249 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1250 | * "If this bit is set, STCunit will have LRA as replacement | |
1251 | * policy. [...] This bit must be reset. LRA replacement | |
1252 | * policy is not supported." | |
1253 | */ | |
1254 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1255 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1256 | } |
1257 | ||
9cc83020 | 1258 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1259 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1260 | |
040d2baa | 1261 | if (HAS_L3_DPF(dev)) |
0bc40be8 | 1262 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1263 | |
0bc40be8 | 1264 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1265 | } |
1266 | ||
0bc40be8 | 1267 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1268 | { |
0bc40be8 | 1269 | struct drm_device *dev = engine->dev; |
3e78998a BW |
1270 | struct drm_i915_private *dev_priv = dev->dev_private; |
1271 | ||
1272 | if (dev_priv->semaphore_obj) { | |
1273 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1274 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1275 | dev_priv->semaphore_obj = NULL; | |
1276 | } | |
b45305fc | 1277 | |
0bc40be8 | 1278 | intel_fini_pipe_control(engine); |
c6df541c CW |
1279 | } |
1280 | ||
f7169687 | 1281 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1282 | unsigned int num_dwords) |
1283 | { | |
1284 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1285 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1286 | struct drm_device *dev = signaller->dev; |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1288 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1289 | enum intel_engine_id id; |
1290 | int ret, num_rings; | |
3e78998a BW |
1291 | |
1292 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1293 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1294 | #undef MBOX_UPDATE_DWORDS | |
1295 | ||
5fb9de1a | 1296 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1297 | if (ret) |
1298 | return ret; | |
1299 | ||
c3232b18 | 1300 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1301 | u32 seqno; |
c3232b18 | 1302 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1303 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1304 | continue; | |
1305 | ||
f7169687 | 1306 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1307 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1308 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1309 | PIPE_CONTROL_QW_WRITE | | |
1310 | PIPE_CONTROL_FLUSH_ENABLE); | |
1311 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1312 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1313 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1314 | intel_ring_emit(signaller, 0); |
1315 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
1316 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1317 | intel_ring_emit(signaller, 0); | |
1318 | } | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
f7169687 | 1323 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1324 | unsigned int num_dwords) |
1325 | { | |
1326 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1327 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1328 | struct drm_device *dev = signaller->dev; |
1329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1330 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1331 | enum intel_engine_id id; |
1332 | int ret, num_rings; | |
3e78998a BW |
1333 | |
1334 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1335 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1336 | #undef MBOX_UPDATE_DWORDS | |
1337 | ||
5fb9de1a | 1338 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1339 | if (ret) |
1340 | return ret; | |
1341 | ||
c3232b18 | 1342 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1343 | u32 seqno; |
c3232b18 | 1344 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1345 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1346 | continue; | |
1347 | ||
f7169687 | 1348 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1349 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1350 | MI_FLUSH_DW_OP_STOREDW); | |
1351 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1352 | MI_FLUSH_DW_USE_GTT); | |
1353 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1354 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1355 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
1356 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1357 | intel_ring_emit(signaller, 0); | |
1358 | } | |
1359 | ||
1360 | return 0; | |
1361 | } | |
1362 | ||
f7169687 | 1363 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1364 | unsigned int num_dwords) |
1ec14ad3 | 1365 | { |
4a570db5 | 1366 | struct intel_engine_cs *signaller = signaller_req->engine; |
024a43e1 BW |
1367 | struct drm_device *dev = signaller->dev; |
1368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1369 | struct intel_engine_cs *useless; |
c3232b18 DG |
1370 | enum intel_engine_id id; |
1371 | int ret, num_rings; | |
78325f2d | 1372 | |
a1444b79 BW |
1373 | #define MBOX_UPDATE_DWORDS 3 |
1374 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1375 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1376 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1377 | |
5fb9de1a | 1378 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1379 | if (ret) |
1380 | return ret; | |
024a43e1 | 1381 | |
c3232b18 DG |
1382 | for_each_engine_id(useless, dev_priv, id) { |
1383 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1384 | |
1385 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1386 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1387 | |
78325f2d | 1388 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1389 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1390 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1391 | } |
1392 | } | |
024a43e1 | 1393 | |
a1444b79 BW |
1394 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1395 | if (num_rings % 2 == 0) | |
1396 | intel_ring_emit(signaller, MI_NOOP); | |
1397 | ||
024a43e1 | 1398 | return 0; |
1ec14ad3 CW |
1399 | } |
1400 | ||
c8c99b0f BW |
1401 | /** |
1402 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1403 | * |
1404 | * @request - request to write to the ring | |
c8c99b0f BW |
1405 | * |
1406 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1407 | * This acts like a signal in the canonical semaphore. | |
1408 | */ | |
1ec14ad3 | 1409 | static int |
ee044a88 | 1410 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1411 | { |
4a570db5 | 1412 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1413 | int ret; |
52ed2325 | 1414 | |
e2f80391 TU |
1415 | if (engine->semaphore.signal) |
1416 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1417 | else |
5fb9de1a | 1418 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1419 | |
1ec14ad3 CW |
1420 | if (ret) |
1421 | return ret; | |
1422 | ||
e2f80391 TU |
1423 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1424 | intel_ring_emit(engine, | |
1425 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1426 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1427 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1428 | __intel_ring_advance(engine); | |
1ec14ad3 | 1429 | |
1ec14ad3 CW |
1430 | return 0; |
1431 | } | |
1432 | ||
f72b3435 MK |
1433 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1434 | u32 seqno) | |
1435 | { | |
1436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1437 | return dev_priv->last_seqno < seqno; | |
1438 | } | |
1439 | ||
c8c99b0f BW |
1440 | /** |
1441 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1442 | * | |
1443 | * @waiter - ring that is waiting | |
1444 | * @signaller - ring which has, or will signal | |
1445 | * @seqno - seqno which the waiter will block on | |
1446 | */ | |
5ee426ca BW |
1447 | |
1448 | static int | |
599d924c | 1449 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1450 | struct intel_engine_cs *signaller, |
1451 | u32 seqno) | |
1452 | { | |
4a570db5 | 1453 | struct intel_engine_cs *waiter = waiter_req->engine; |
5ee426ca BW |
1454 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1455 | int ret; | |
1456 | ||
5fb9de1a | 1457 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1458 | if (ret) |
1459 | return ret; | |
1460 | ||
1461 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1462 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1463 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1464 | MI_SEMAPHORE_SAD_GTE_SDD); |
1465 | intel_ring_emit(waiter, seqno); | |
1466 | intel_ring_emit(waiter, | |
1467 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1468 | intel_ring_emit(waiter, | |
1469 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1470 | intel_ring_advance(waiter); | |
1471 | return 0; | |
1472 | } | |
1473 | ||
c8c99b0f | 1474 | static int |
599d924c | 1475 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1476 | struct intel_engine_cs *signaller, |
686cb5f9 | 1477 | u32 seqno) |
1ec14ad3 | 1478 | { |
4a570db5 | 1479 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1480 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1481 | MI_SEMAPHORE_COMPARE | | |
1482 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1483 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1484 | int ret; | |
1ec14ad3 | 1485 | |
1500f7ea BW |
1486 | /* Throughout all of the GEM code, seqno passed implies our current |
1487 | * seqno is >= the last seqno executed. However for hardware the | |
1488 | * comparison is strictly greater than. | |
1489 | */ | |
1490 | seqno -= 1; | |
1491 | ||
ebc348b2 | 1492 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1493 | |
5fb9de1a | 1494 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1495 | if (ret) |
1496 | return ret; | |
1497 | ||
f72b3435 MK |
1498 | /* If seqno wrap happened, omit the wait with no-ops */ |
1499 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1500 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1501 | intel_ring_emit(waiter, seqno); |
1502 | intel_ring_emit(waiter, 0); | |
1503 | intel_ring_emit(waiter, MI_NOOP); | |
1504 | } else { | |
1505 | intel_ring_emit(waiter, MI_NOOP); | |
1506 | intel_ring_emit(waiter, MI_NOOP); | |
1507 | intel_ring_emit(waiter, MI_NOOP); | |
1508 | intel_ring_emit(waiter, MI_NOOP); | |
1509 | } | |
c8c99b0f | 1510 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1511 | |
1512 | return 0; | |
1513 | } | |
1514 | ||
c6df541c CW |
1515 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1516 | do { \ | |
fcbc34e4 KG |
1517 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1518 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1519 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1520 | intel_ring_emit(ring__, 0); \ | |
1521 | intel_ring_emit(ring__, 0); \ | |
1522 | } while (0) | |
1523 | ||
1524 | static int | |
ee044a88 | 1525 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1526 | { |
4a570db5 | 1527 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1528 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1529 | int ret; |
1530 | ||
1531 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1532 | * incoherent with writes to memory, i.e. completely fubar, | |
1533 | * so we need to use PIPE_NOTIFY instead. | |
1534 | * | |
1535 | * However, we also need to workaround the qword write | |
1536 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1537 | * memory before requesting an interrupt. | |
1538 | */ | |
5fb9de1a | 1539 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1540 | if (ret) |
1541 | return ret; | |
1542 | ||
e2f80391 TU |
1543 | intel_ring_emit(engine, |
1544 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1545 | PIPE_CONTROL_WRITE_FLUSH | |
1546 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1547 | intel_ring_emit(engine, |
1548 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1549 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1550 | intel_ring_emit(engine, 0); | |
1551 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1552 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1553 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1554 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1555 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1556 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1557 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1558 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1559 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1560 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1561 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1562 | |
e2f80391 TU |
1563 | intel_ring_emit(engine, |
1564 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1565 | PIPE_CONTROL_WRITE_FLUSH | |
1566 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1567 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1568 | intel_ring_emit(engine, |
1569 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1570 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1571 | intel_ring_emit(engine, 0); | |
1572 | __intel_ring_advance(engine); | |
c6df541c | 1573 | |
c6df541c CW |
1574 | return 0; |
1575 | } | |
1576 | ||
c04e0f3b CW |
1577 | static void |
1578 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1579 | { |
bcbdb6d0 CW |
1580 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
1581 | ||
4cd53c0c DV |
1582 | /* Workaround to force correct ordering between irq and seqno writes on |
1583 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1584 | * ACTHD) before reading the status page. |
1585 | * | |
1586 | * Note that this effectively stalls the read by the time it takes to | |
1587 | * do a memory transaction, which more or less ensures that the write | |
1588 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1589 | * Alternatively we could delay the interrupt from the CS ring to give | |
1590 | * the write time to land, but that would incur a delay after every | |
1591 | * batch i.e. much more frequent than a delay when waiting for the | |
1592 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1593 | * |
1594 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1595 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1596 | */ |
bcbdb6d0 | 1597 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1598 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1599 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1600 | } |
1601 | ||
8187a2b7 | 1602 | static u32 |
c04e0f3b | 1603 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1604 | { |
0bc40be8 | 1605 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1606 | } |
1607 | ||
b70ec5bf | 1608 | static void |
0bc40be8 | 1609 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1610 | { |
0bc40be8 | 1611 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1612 | } |
1613 | ||
c6df541c | 1614 | static u32 |
c04e0f3b | 1615 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1616 | { |
0bc40be8 | 1617 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1618 | } |
1619 | ||
b70ec5bf | 1620 | static void |
0bc40be8 | 1621 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1622 | { |
0bc40be8 | 1623 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1624 | } |
1625 | ||
e48d8634 | 1626 | static bool |
0bc40be8 | 1627 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1628 | { |
0bc40be8 | 1629 | struct drm_device *dev = engine->dev; |
4640c4ff | 1630 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1631 | unsigned long flags; |
e48d8634 | 1632 | |
7cd512f1 | 1633 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1634 | return false; |
1635 | ||
7338aefa | 1636 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1637 | if (engine->irq_refcount++ == 0) |
1638 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1639 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1640 | |
1641 | return true; | |
1642 | } | |
1643 | ||
1644 | static void | |
0bc40be8 | 1645 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1646 | { |
0bc40be8 | 1647 | struct drm_device *dev = engine->dev; |
4640c4ff | 1648 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1649 | unsigned long flags; |
e48d8634 | 1650 | |
7338aefa | 1651 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1652 | if (--engine->irq_refcount == 0) |
1653 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1654 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1655 | } |
1656 | ||
b13c2b96 | 1657 | static bool |
0bc40be8 | 1658 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1659 | { |
0bc40be8 | 1660 | struct drm_device *dev = engine->dev; |
4640c4ff | 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1662 | unsigned long flags; |
62fdfeaf | 1663 | |
7cd512f1 | 1664 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1665 | return false; |
1666 | ||
7338aefa | 1667 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1668 | if (engine->irq_refcount++ == 0) { |
1669 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1670 | I915_WRITE(IMR, dev_priv->irq_mask); |
1671 | POSTING_READ(IMR); | |
1672 | } | |
7338aefa | 1673 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1674 | |
1675 | return true; | |
62fdfeaf EA |
1676 | } |
1677 | ||
8187a2b7 | 1678 | static void |
0bc40be8 | 1679 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1680 | { |
0bc40be8 | 1681 | struct drm_device *dev = engine->dev; |
4640c4ff | 1682 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1683 | unsigned long flags; |
62fdfeaf | 1684 | |
7338aefa | 1685 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1686 | if (--engine->irq_refcount == 0) { |
1687 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1688 | I915_WRITE(IMR, dev_priv->irq_mask); |
1689 | POSTING_READ(IMR); | |
1690 | } | |
7338aefa | 1691 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1692 | } |
1693 | ||
c2798b19 | 1694 | static bool |
0bc40be8 | 1695 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1696 | { |
0bc40be8 | 1697 | struct drm_device *dev = engine->dev; |
4640c4ff | 1698 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1699 | unsigned long flags; |
c2798b19 | 1700 | |
7cd512f1 | 1701 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1702 | return false; |
1703 | ||
7338aefa | 1704 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1705 | if (engine->irq_refcount++ == 0) { |
1706 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1707 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1708 | POSTING_READ16(IMR); | |
1709 | } | |
7338aefa | 1710 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1711 | |
1712 | return true; | |
1713 | } | |
1714 | ||
1715 | static void | |
0bc40be8 | 1716 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1717 | { |
0bc40be8 | 1718 | struct drm_device *dev = engine->dev; |
4640c4ff | 1719 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1720 | unsigned long flags; |
c2798b19 | 1721 | |
7338aefa | 1722 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1723 | if (--engine->irq_refcount == 0) { |
1724 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1725 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1726 | POSTING_READ16(IMR); | |
1727 | } | |
7338aefa | 1728 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1729 | } |
1730 | ||
b72f3acb | 1731 | static int |
a84c3ae1 | 1732 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1733 | u32 invalidate_domains, |
1734 | u32 flush_domains) | |
d1b851fc | 1735 | { |
4a570db5 | 1736 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1737 | int ret; |
1738 | ||
5fb9de1a | 1739 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1740 | if (ret) |
1741 | return ret; | |
1742 | ||
e2f80391 TU |
1743 | intel_ring_emit(engine, MI_FLUSH); |
1744 | intel_ring_emit(engine, MI_NOOP); | |
1745 | intel_ring_advance(engine); | |
b72f3acb | 1746 | return 0; |
d1b851fc ZN |
1747 | } |
1748 | ||
3cce469c | 1749 | static int |
ee044a88 | 1750 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1751 | { |
4a570db5 | 1752 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1753 | int ret; |
1754 | ||
5fb9de1a | 1755 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1756 | if (ret) |
1757 | return ret; | |
6f392d54 | 1758 | |
e2f80391 TU |
1759 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1760 | intel_ring_emit(engine, | |
1761 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1762 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1763 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1764 | __intel_ring_advance(engine); | |
d1b851fc | 1765 | |
3cce469c | 1766 | return 0; |
d1b851fc ZN |
1767 | } |
1768 | ||
0f46832f | 1769 | static bool |
0bc40be8 | 1770 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1771 | { |
0bc40be8 | 1772 | struct drm_device *dev = engine->dev; |
4640c4ff | 1773 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1774 | unsigned long flags; |
0f46832f | 1775 | |
7cd512f1 DV |
1776 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1777 | return false; | |
0f46832f | 1778 | |
7338aefa | 1779 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1780 | if (engine->irq_refcount++ == 0) { |
1781 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1782 | I915_WRITE_IMR(engine, | |
1783 | ~(engine->irq_enable_mask | | |
35a85ac6 | 1784 | GT_PARITY_ERROR(dev))); |
15b9f80e | 1785 | else |
0bc40be8 TU |
1786 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1787 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1788 | } |
7338aefa | 1789 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1790 | |
1791 | return true; | |
1792 | } | |
1793 | ||
1794 | static void | |
0bc40be8 | 1795 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1796 | { |
0bc40be8 | 1797 | struct drm_device *dev = engine->dev; |
4640c4ff | 1798 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1799 | unsigned long flags; |
0f46832f | 1800 | |
7338aefa | 1801 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1802 | if (--engine->irq_refcount == 0) { |
1803 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1804 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); | |
15b9f80e | 1805 | else |
0bc40be8 TU |
1806 | I915_WRITE_IMR(engine, ~0); |
1807 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1808 | } |
7338aefa | 1809 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1810 | } |
1811 | ||
a19d2933 | 1812 | static bool |
0bc40be8 | 1813 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1814 | { |
0bc40be8 | 1815 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1816 | struct drm_i915_private *dev_priv = dev->dev_private; |
1817 | unsigned long flags; | |
1818 | ||
7cd512f1 | 1819 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1820 | return false; |
1821 | ||
59cdb63d | 1822 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1823 | if (engine->irq_refcount++ == 0) { |
1824 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1825 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1826 | } |
59cdb63d | 1827 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1828 | |
1829 | return true; | |
1830 | } | |
1831 | ||
1832 | static void | |
0bc40be8 | 1833 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1834 | { |
0bc40be8 | 1835 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1836 | struct drm_i915_private *dev_priv = dev->dev_private; |
1837 | unsigned long flags; | |
1838 | ||
59cdb63d | 1839 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1840 | if (--engine->irq_refcount == 0) { |
1841 | I915_WRITE_IMR(engine, ~0); | |
1842 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1843 | } |
59cdb63d | 1844 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1845 | } |
1846 | ||
abd58f01 | 1847 | static bool |
0bc40be8 | 1848 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1849 | { |
0bc40be8 | 1850 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; |
1852 | unsigned long flags; | |
1853 | ||
7cd512f1 | 1854 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1855 | return false; |
1856 | ||
1857 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1858 | if (engine->irq_refcount++ == 0) { |
1859 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1860 | I915_WRITE_IMR(engine, | |
1861 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1862 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1863 | } else { | |
0bc40be8 | 1864 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1865 | } |
0bc40be8 | 1866 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1867 | } |
1868 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1869 | ||
1870 | return true; | |
1871 | } | |
1872 | ||
1873 | static void | |
0bc40be8 | 1874 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1875 | { |
0bc40be8 | 1876 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1877 | struct drm_i915_private *dev_priv = dev->dev_private; |
1878 | unsigned long flags; | |
1879 | ||
1880 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1881 | if (--engine->irq_refcount == 0) { |
1882 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1883 | I915_WRITE_IMR(engine, | |
abd58f01 BW |
1884 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1885 | } else { | |
0bc40be8 | 1886 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1887 | } |
0bc40be8 | 1888 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1889 | } |
1890 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1891 | } | |
1892 | ||
d1b851fc | 1893 | static int |
53fddaf7 | 1894 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1895 | u64 offset, u32 length, |
8e004efc | 1896 | unsigned dispatch_flags) |
d1b851fc | 1897 | { |
4a570db5 | 1898 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1899 | int ret; |
78501eac | 1900 | |
5fb9de1a | 1901 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1902 | if (ret) |
1903 | return ret; | |
1904 | ||
e2f80391 | 1905 | intel_ring_emit(engine, |
65f56876 CW |
1906 | MI_BATCH_BUFFER_START | |
1907 | MI_BATCH_GTT | | |
8e004efc JH |
1908 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1909 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1910 | intel_ring_emit(engine, offset); |
1911 | intel_ring_advance(engine); | |
78501eac | 1912 | |
d1b851fc ZN |
1913 | return 0; |
1914 | } | |
1915 | ||
b45305fc DV |
1916 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1917 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1918 | #define I830_TLB_ENTRIES (2) |
1919 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1920 | static int |
53fddaf7 | 1921 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1922 | u64 offset, u32 len, |
1923 | unsigned dispatch_flags) | |
62fdfeaf | 1924 | { |
4a570db5 | 1925 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1926 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1927 | int ret; |
62fdfeaf | 1928 | |
5fb9de1a | 1929 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1930 | if (ret) |
1931 | return ret; | |
62fdfeaf | 1932 | |
c4d69da1 | 1933 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1934 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1935 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1936 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1937 | intel_ring_emit(engine, cs_offset); | |
1938 | intel_ring_emit(engine, 0xdeadbeef); | |
1939 | intel_ring_emit(engine, MI_NOOP); | |
1940 | intel_ring_advance(engine); | |
b45305fc | 1941 | |
8e004efc | 1942 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1943 | if (len > I830_BATCH_LIMIT) |
1944 | return -ENOSPC; | |
1945 | ||
5fb9de1a | 1946 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1947 | if (ret) |
1948 | return ret; | |
c4d69da1 CW |
1949 | |
1950 | /* Blit the batch (which has now all relocs applied) to the | |
1951 | * stable batch scratch bo area (so that the CS never | |
1952 | * stumbles over its tlb invalidation bug) ... | |
1953 | */ | |
e2f80391 TU |
1954 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1955 | intel_ring_emit(engine, | |
1956 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
1957 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
1958 | intel_ring_emit(engine, cs_offset); | |
1959 | intel_ring_emit(engine, 4096); | |
1960 | intel_ring_emit(engine, offset); | |
1961 | ||
1962 | intel_ring_emit(engine, MI_FLUSH); | |
1963 | intel_ring_emit(engine, MI_NOOP); | |
1964 | intel_ring_advance(engine); | |
b45305fc DV |
1965 | |
1966 | /* ... and execute it. */ | |
c4d69da1 | 1967 | offset = cs_offset; |
b45305fc | 1968 | } |
e1f99ce6 | 1969 | |
9d611c03 | 1970 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1971 | if (ret) |
1972 | return ret; | |
1973 | ||
e2f80391 TU |
1974 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1975 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1976 | 0 : MI_BATCH_NON_SECURE)); | |
1977 | intel_ring_advance(engine); | |
c4d69da1 | 1978 | |
fb3256da DV |
1979 | return 0; |
1980 | } | |
1981 | ||
1982 | static int | |
53fddaf7 | 1983 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1984 | u64 offset, u32 len, |
8e004efc | 1985 | unsigned dispatch_flags) |
fb3256da | 1986 | { |
4a570db5 | 1987 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
1988 | int ret; |
1989 | ||
5fb9de1a | 1990 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1991 | if (ret) |
1992 | return ret; | |
1993 | ||
e2f80391 TU |
1994 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1995 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1996 | 0 : MI_BATCH_NON_SECURE)); | |
1997 | intel_ring_advance(engine); | |
62fdfeaf | 1998 | |
62fdfeaf EA |
1999 | return 0; |
2000 | } | |
2001 | ||
0bc40be8 | 2002 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 2003 | { |
0bc40be8 | 2004 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
7d3fdfff VS |
2005 | |
2006 | if (!dev_priv->status_page_dmah) | |
2007 | return; | |
2008 | ||
0bc40be8 TU |
2009 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
2010 | engine->status_page.page_addr = NULL; | |
7d3fdfff VS |
2011 | } |
2012 | ||
0bc40be8 | 2013 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2014 | { |
05394f39 | 2015 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2016 | |
0bc40be8 | 2017 | obj = engine->status_page.obj; |
8187a2b7 | 2018 | if (obj == NULL) |
62fdfeaf | 2019 | return; |
62fdfeaf | 2020 | |
9da3da66 | 2021 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2022 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2023 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2024 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2025 | } |
2026 | ||
0bc40be8 | 2027 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2028 | { |
0bc40be8 | 2029 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2030 | |
7d3fdfff | 2031 | if (obj == NULL) { |
1f767e02 | 2032 | unsigned flags; |
e3efda49 | 2033 | int ret; |
e4ffd173 | 2034 | |
d37cd8a8 | 2035 | obj = i915_gem_object_create(engine->dev, 4096); |
fe3db79b | 2036 | if (IS_ERR(obj)) { |
e3efda49 | 2037 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 2038 | return PTR_ERR(obj); |
e3efda49 | 2039 | } |
62fdfeaf | 2040 | |
e3efda49 CW |
2041 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2042 | if (ret) | |
2043 | goto err_unref; | |
2044 | ||
1f767e02 | 2045 | flags = 0; |
0bc40be8 | 2046 | if (!HAS_LLC(engine->dev)) |
1f767e02 CW |
2047 | /* On g33, we cannot place HWS above 256MiB, so |
2048 | * restrict its pinning to the low mappable arena. | |
2049 | * Though this restriction is not documented for | |
2050 | * gen4, gen5, or byt, they also behave similarly | |
2051 | * and hang if the HWS is placed at the top of the | |
2052 | * GTT. To generalise, it appears that all !llc | |
2053 | * platforms have issues with us placing the HWS | |
2054 | * above the mappable region (even though we never | |
2055 | * actualy map it). | |
2056 | */ | |
2057 | flags |= PIN_MAPPABLE; | |
2058 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2059 | if (ret) { |
2060 | err_unref: | |
2061 | drm_gem_object_unreference(&obj->base); | |
2062 | return ret; | |
2063 | } | |
2064 | ||
0bc40be8 | 2065 | engine->status_page.obj = obj; |
e3efda49 | 2066 | } |
62fdfeaf | 2067 | |
0bc40be8 TU |
2068 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2069 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2070 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2071 | |
8187a2b7 | 2072 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2073 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2074 | |
2075 | return 0; | |
62fdfeaf EA |
2076 | } |
2077 | ||
0bc40be8 | 2078 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2079 | { |
0bc40be8 | 2080 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
6b8294a4 CW |
2081 | |
2082 | if (!dev_priv->status_page_dmah) { | |
2083 | dev_priv->status_page_dmah = | |
0bc40be8 | 2084 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2085 | if (!dev_priv->status_page_dmah) |
2086 | return -ENOMEM; | |
2087 | } | |
2088 | ||
0bc40be8 TU |
2089 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2090 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2091 | |
2092 | return 0; | |
2093 | } | |
2094 | ||
7ba717cf | 2095 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2096 | { |
3d77e9be CW |
2097 | GEM_BUG_ON(ringbuf->vma == NULL); |
2098 | GEM_BUG_ON(ringbuf->virtual_start == NULL); | |
2099 | ||
def0c5f6 | 2100 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2101 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 | 2102 | else |
3d77e9be | 2103 | i915_vma_unpin_iomap(ringbuf->vma); |
8305216f | 2104 | ringbuf->virtual_start = NULL; |
3d77e9be | 2105 | |
2919d291 | 2106 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
3d77e9be | 2107 | ringbuf->vma = NULL; |
7ba717cf TD |
2108 | } |
2109 | ||
2110 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
2111 | struct intel_ringbuffer *ringbuf) | |
2112 | { | |
2113 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2114 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
a687a43a CW |
2115 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2116 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2117 | void *addr; |
7ba717cf TD |
2118 | int ret; |
2119 | ||
def0c5f6 | 2120 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2121 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2122 | if (ret) |
2123 | return ret; | |
7ba717cf | 2124 | |
def0c5f6 | 2125 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2126 | if (ret) |
2127 | goto err_unpin; | |
def0c5f6 | 2128 | |
8305216f DG |
2129 | addr = i915_gem_object_pin_map(obj); |
2130 | if (IS_ERR(addr)) { | |
2131 | ret = PTR_ERR(addr); | |
d2cad535 | 2132 | goto err_unpin; |
def0c5f6 CW |
2133 | } |
2134 | } else { | |
a687a43a CW |
2135 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2136 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2137 | if (ret) |
2138 | return ret; | |
7ba717cf | 2139 | |
def0c5f6 | 2140 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2141 | if (ret) |
2142 | goto err_unpin; | |
def0c5f6 | 2143 | |
ff3dc087 DCS |
2144 | /* Access through the GTT requires the device to be awake. */ |
2145 | assert_rpm_wakelock_held(dev_priv); | |
2146 | ||
3d77e9be CW |
2147 | addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); |
2148 | if (IS_ERR(addr)) { | |
2149 | ret = PTR_ERR(addr); | |
d2cad535 | 2150 | goto err_unpin; |
def0c5f6 | 2151 | } |
7ba717cf TD |
2152 | } |
2153 | ||
8305216f | 2154 | ringbuf->virtual_start = addr; |
0eb973d3 | 2155 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2156 | return 0; |
d2cad535 CW |
2157 | |
2158 | err_unpin: | |
2159 | i915_gem_object_ggtt_unpin(obj); | |
2160 | return ret; | |
7ba717cf TD |
2161 | } |
2162 | ||
01101fa7 | 2163 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2164 | { |
2919d291 OM |
2165 | drm_gem_object_unreference(&ringbuf->obj->base); |
2166 | ringbuf->obj = NULL; | |
2167 | } | |
2168 | ||
01101fa7 CW |
2169 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2170 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2171 | { |
05394f39 | 2172 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2173 | |
ebc052e0 CW |
2174 | obj = NULL; |
2175 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2176 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2177 | if (obj == NULL) |
d37cd8a8 | 2178 | obj = i915_gem_object_create(dev, ringbuf->size); |
fe3db79b CW |
2179 | if (IS_ERR(obj)) |
2180 | return PTR_ERR(obj); | |
8187a2b7 | 2181 | |
24f3a8cf AG |
2182 | /* mark ring buffers as read-only from GPU side by default */ |
2183 | obj->gt_ro = 1; | |
2184 | ||
93b0a4e0 | 2185 | ringbuf->obj = obj; |
e3efda49 | 2186 | |
7ba717cf | 2187 | return 0; |
e3efda49 CW |
2188 | } |
2189 | ||
01101fa7 CW |
2190 | struct intel_ringbuffer * |
2191 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2192 | { | |
2193 | struct intel_ringbuffer *ring; | |
2194 | int ret; | |
2195 | ||
2196 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2197 | if (ring == NULL) { |
2198 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2199 | engine->name); | |
01101fa7 | 2200 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2201 | } |
01101fa7 | 2202 | |
4a570db5 | 2203 | ring->engine = engine; |
608c1a52 | 2204 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2205 | |
2206 | ring->size = size; | |
2207 | /* Workaround an erratum on the i830 which causes a hang if | |
2208 | * the TAIL pointer points to within the last 2 cachelines | |
2209 | * of the buffer. | |
2210 | */ | |
2211 | ring->effective_size = size; | |
2212 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2213 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2214 | ||
2215 | ring->last_retired_head = -1; | |
2216 | intel_ring_update_space(ring); | |
2217 | ||
2218 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2219 | if (ret) { | |
608c1a52 CW |
2220 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2221 | engine->name, ret); | |
2222 | list_del(&ring->link); | |
01101fa7 CW |
2223 | kfree(ring); |
2224 | return ERR_PTR(ret); | |
2225 | } | |
2226 | ||
2227 | return ring; | |
2228 | } | |
2229 | ||
2230 | void | |
2231 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2232 | { | |
2233 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2234 | list_del(&ring->link); |
01101fa7 CW |
2235 | kfree(ring); |
2236 | } | |
2237 | ||
e3efda49 | 2238 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2239 | struct intel_engine_cs *engine) |
e3efda49 | 2240 | { |
bfc882b4 | 2241 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2242 | int ret; |
2243 | ||
0bc40be8 | 2244 | WARN_ON(engine->buffer); |
bfc882b4 | 2245 | |
0bc40be8 TU |
2246 | engine->dev = dev; |
2247 | INIT_LIST_HEAD(&engine->active_list); | |
2248 | INIT_LIST_HEAD(&engine->request_list); | |
2249 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2250 | INIT_LIST_HEAD(&engine->buffers); | |
2251 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2252 | memset(engine->semaphore.sync_seqno, 0, | |
2253 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2254 | |
0bc40be8 | 2255 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2256 | |
0bc40be8 | 2257 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2258 | if (IS_ERR(ringbuf)) { |
2259 | ret = PTR_ERR(ringbuf); | |
2260 | goto error; | |
2261 | } | |
0bc40be8 | 2262 | engine->buffer = ringbuf; |
01101fa7 | 2263 | |
e3efda49 | 2264 | if (I915_NEED_GFX_HWS(dev)) { |
0bc40be8 | 2265 | ret = init_status_page(engine); |
e3efda49 | 2266 | if (ret) |
8ee14975 | 2267 | goto error; |
e3efda49 | 2268 | } else { |
0bc40be8 TU |
2269 | WARN_ON(engine->id != RCS); |
2270 | ret = init_phys_status_page(engine); | |
e3efda49 | 2271 | if (ret) |
8ee14975 | 2272 | goto error; |
e3efda49 CW |
2273 | } |
2274 | ||
bfc882b4 DV |
2275 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2276 | if (ret) { | |
2277 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2278 | engine->name, ret); |
bfc882b4 DV |
2279 | intel_destroy_ringbuffer_obj(ringbuf); |
2280 | goto error; | |
e3efda49 | 2281 | } |
62fdfeaf | 2282 | |
0bc40be8 | 2283 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2284 | if (ret) |
8ee14975 OM |
2285 | goto error; |
2286 | ||
8ee14975 | 2287 | return 0; |
351e3db2 | 2288 | |
8ee14975 | 2289 | error: |
117897f4 | 2290 | intel_cleanup_engine(engine); |
8ee14975 | 2291 | return ret; |
62fdfeaf EA |
2292 | } |
2293 | ||
117897f4 | 2294 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2295 | { |
6402c330 | 2296 | struct drm_i915_private *dev_priv; |
33626e6a | 2297 | |
117897f4 | 2298 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2299 | return; |
2300 | ||
0bc40be8 | 2301 | dev_priv = to_i915(engine->dev); |
6402c330 | 2302 | |
0bc40be8 | 2303 | if (engine->buffer) { |
117897f4 | 2304 | intel_stop_engine(engine); |
0bc40be8 | 2305 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2306 | |
0bc40be8 TU |
2307 | intel_unpin_ringbuffer_obj(engine->buffer); |
2308 | intel_ringbuffer_free(engine->buffer); | |
2309 | engine->buffer = NULL; | |
b0366a54 | 2310 | } |
78501eac | 2311 | |
0bc40be8 TU |
2312 | if (engine->cleanup) |
2313 | engine->cleanup(engine); | |
8d19215b | 2314 | |
0bc40be8 TU |
2315 | if (I915_NEED_GFX_HWS(engine->dev)) { |
2316 | cleanup_status_page(engine); | |
7d3fdfff | 2317 | } else { |
0bc40be8 TU |
2318 | WARN_ON(engine->id != RCS); |
2319 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2320 | } |
44e895a8 | 2321 | |
0bc40be8 TU |
2322 | i915_cmd_parser_fini_ring(engine); |
2323 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
2324 | engine->dev = NULL; | |
62fdfeaf EA |
2325 | } |
2326 | ||
666796da | 2327 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2328 | { |
a4b3a571 | 2329 | struct drm_i915_gem_request *req; |
3e960501 | 2330 | |
3e960501 | 2331 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2332 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2333 | return 0; |
2334 | ||
0bc40be8 TU |
2335 | req = list_entry(engine->request_list.prev, |
2336 | struct drm_i915_gem_request, | |
2337 | list); | |
b4716185 CW |
2338 | |
2339 | /* Make sure we do not trigger any retires */ | |
2340 | return __i915_wait_request(req, | |
c19ae989 | 2341 | req->i915->mm.interruptible, |
b4716185 | 2342 | NULL, NULL); |
3e960501 CW |
2343 | } |
2344 | ||
6689cb2b | 2345 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2346 | { |
6310346e CW |
2347 | int ret; |
2348 | ||
2349 | /* Flush enough space to reduce the likelihood of waiting after | |
2350 | * we start building the request - in which case we will just | |
2351 | * have to repeat work. | |
2352 | */ | |
a0442461 | 2353 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2354 | |
4a570db5 | 2355 | request->ringbuf = request->engine->buffer; |
6310346e CW |
2356 | |
2357 | ret = intel_ring_begin(request, 0); | |
2358 | if (ret) | |
2359 | return ret; | |
2360 | ||
a0442461 | 2361 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2362 | return 0; |
9d773091 CW |
2363 | } |
2364 | ||
987046ad CW |
2365 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2366 | { | |
2367 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2368 | struct intel_engine_cs *engine = req->engine; | |
2369 | struct drm_i915_gem_request *target; | |
2370 | ||
2371 | intel_ring_update_space(ringbuf); | |
2372 | if (ringbuf->space >= bytes) | |
2373 | return 0; | |
2374 | ||
2375 | /* | |
2376 | * Space is reserved in the ringbuffer for finalising the request, | |
2377 | * as that cannot be allowed to fail. During request finalisation, | |
2378 | * reserved_space is set to 0 to stop the overallocation and the | |
2379 | * assumption is that then we never need to wait (which has the | |
2380 | * risk of failing with EINTR). | |
2381 | * | |
2382 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2383 | */ | |
0251a963 | 2384 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2385 | |
2386 | list_for_each_entry(target, &engine->request_list, list) { | |
2387 | unsigned space; | |
2388 | ||
79bbcc29 | 2389 | /* |
987046ad CW |
2390 | * The request queue is per-engine, so can contain requests |
2391 | * from multiple ringbuffers. Here, we must ignore any that | |
2392 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2393 | */ |
987046ad CW |
2394 | if (target->ringbuf != ringbuf) |
2395 | continue; | |
2396 | ||
2397 | /* Would completion of this request free enough space? */ | |
2398 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2399 | ringbuf->size); | |
2400 | if (space >= bytes) | |
2401 | break; | |
79bbcc29 | 2402 | } |
29b1b415 | 2403 | |
987046ad CW |
2404 | if (WARN_ON(&target->list == &engine->request_list)) |
2405 | return -ENOSPC; | |
2406 | ||
2407 | return i915_wait_request(target); | |
29b1b415 JH |
2408 | } |
2409 | ||
987046ad | 2410 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2411 | { |
987046ad | 2412 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2413 | int remain_actual = ringbuf->size - ringbuf->tail; |
987046ad CW |
2414 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2415 | int bytes = num_dwords * sizeof(u32); | |
2416 | int total_bytes, wait_bytes; | |
79bbcc29 | 2417 | bool need_wrap = false; |
29b1b415 | 2418 | |
0251a963 | 2419 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2420 | |
79bbcc29 JH |
2421 | if (unlikely(bytes > remain_usable)) { |
2422 | /* | |
2423 | * Not enough space for the basic request. So need to flush | |
2424 | * out the remainder and then wait for base + reserved. | |
2425 | */ | |
2426 | wait_bytes = remain_actual + total_bytes; | |
2427 | need_wrap = true; | |
987046ad CW |
2428 | } else if (unlikely(total_bytes > remain_usable)) { |
2429 | /* | |
2430 | * The base request will fit but the reserved space | |
2431 | * falls off the end. So we don't need an immediate wrap | |
2432 | * and only need to effectively wait for the reserved | |
2433 | * size space from the start of ringbuffer. | |
2434 | */ | |
0251a963 | 2435 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2436 | } else { |
987046ad CW |
2437 | /* No wrapping required, just waiting. */ |
2438 | wait_bytes = total_bytes; | |
cbcc80df MK |
2439 | } |
2440 | ||
987046ad CW |
2441 | if (wait_bytes > ringbuf->space) { |
2442 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2443 | if (unlikely(ret)) |
2444 | return ret; | |
79bbcc29 | 2445 | |
987046ad | 2446 | intel_ring_update_space(ringbuf); |
cbcc80df MK |
2447 | } |
2448 | ||
987046ad CW |
2449 | if (unlikely(need_wrap)) { |
2450 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2451 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2452 | |
987046ad CW |
2453 | /* Fill the tail with MI_NOOP */ |
2454 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2455 | 0, remain_actual); | |
2456 | ringbuf->tail = 0; | |
2457 | ringbuf->space -= remain_actual; | |
2458 | } | |
304d695c | 2459 | |
987046ad CW |
2460 | ringbuf->space -= bytes; |
2461 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2462 | return 0; |
8187a2b7 | 2463 | } |
78501eac | 2464 | |
753b1ad4 | 2465 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2466 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2467 | { |
4a570db5 | 2468 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2469 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2470 | int ret; |
2471 | ||
2472 | if (num_dwords == 0) | |
2473 | return 0; | |
2474 | ||
18393f63 | 2475 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2476 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2477 | if (ret) |
2478 | return ret; | |
2479 | ||
2480 | while (num_dwords--) | |
e2f80391 | 2481 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2482 | |
e2f80391 | 2483 | intel_ring_advance(engine); |
753b1ad4 VS |
2484 | |
2485 | return 0; | |
2486 | } | |
2487 | ||
0bc40be8 | 2488 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2489 | { |
d04bce48 | 2490 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
498d2ac1 | 2491 | |
29dcb570 CW |
2492 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2493 | * so long as the semaphore value in the register/page is greater | |
2494 | * than the sync value), so whenever we reset the seqno, | |
2495 | * so long as we reset the tracking semaphore value to 0, it will | |
2496 | * always be before the next request's seqno. If we don't reset | |
2497 | * the semaphore value, then when the seqno moves backwards all | |
2498 | * future waits will complete instantly (causing rendering corruption). | |
2499 | */ | |
d04bce48 | 2500 | if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { |
0bc40be8 TU |
2501 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2502 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2503 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2504 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2505 | } |
a058d934 CW |
2506 | if (dev_priv->semaphore_obj) { |
2507 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2508 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2509 | void *semaphores = kmap(page); | |
2510 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2511 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2512 | kunmap(page); | |
2513 | } | |
29dcb570 CW |
2514 | memset(engine->semaphore.sync_seqno, 0, |
2515 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2516 | |
0bc40be8 | 2517 | engine->set_seqno(engine, seqno); |
01347126 | 2518 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2519 | |
0bc40be8 | 2520 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2521 | } |
62fdfeaf | 2522 | |
0bc40be8 | 2523 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2524 | u32 value) |
881f47b6 | 2525 | { |
0bc40be8 | 2526 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
881f47b6 XH |
2527 | |
2528 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2529 | |
2530 | /* Disable notification that the ring is IDLE. The GT | |
2531 | * will then assume that it is busy and bring it out of rc6. | |
2532 | */ | |
0206e353 | 2533 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2534 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2535 | ||
2536 | /* Clear the context id. Here be magic! */ | |
2537 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2538 | |
12f55818 | 2539 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2540 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2541 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2542 | 50)) | |
2543 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2544 | |
12f55818 | 2545 | /* Now that the ring is fully powered up, update the tail */ |
0bc40be8 TU |
2546 | I915_WRITE_TAIL(engine, value); |
2547 | POSTING_READ(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2548 | |
2549 | /* Let the ring send IDLE messages to the GT again, | |
2550 | * and so let it sleep to conserve power when idle. | |
2551 | */ | |
0206e353 | 2552 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2553 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2554 | } |
2555 | ||
a84c3ae1 | 2556 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2557 | u32 invalidate, u32 flush) |
881f47b6 | 2558 | { |
4a570db5 | 2559 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2560 | uint32_t cmd; |
b72f3acb CW |
2561 | int ret; |
2562 | ||
5fb9de1a | 2563 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2564 | if (ret) |
2565 | return ret; | |
2566 | ||
71a77e07 | 2567 | cmd = MI_FLUSH_DW; |
e2f80391 | 2568 | if (INTEL_INFO(engine->dev)->gen >= 8) |
075b3bba | 2569 | cmd += 1; |
f0a1fb10 CW |
2570 | |
2571 | /* We always require a command barrier so that subsequent | |
2572 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2573 | * wrt the contents of the write cache being flushed to memory | |
2574 | * (and thus being coherent from the CPU). | |
2575 | */ | |
2576 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2577 | ||
9a289771 JB |
2578 | /* |
2579 | * Bspec vol 1c.5 - video engine command streamer: | |
2580 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2581 | * operation is complete. This bit is only valid when the | |
2582 | * Post-Sync Operation field is a value of 1h or 3h." | |
2583 | */ | |
71a77e07 | 2584 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2585 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2586 | ||
e2f80391 TU |
2587 | intel_ring_emit(engine, cmd); |
2588 | intel_ring_emit(engine, | |
2589 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
2590 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2591 | intel_ring_emit(engine, 0); /* upper addr */ | |
2592 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2593 | } else { |
e2f80391 TU |
2594 | intel_ring_emit(engine, 0); |
2595 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2596 | } |
e2f80391 | 2597 | intel_ring_advance(engine); |
b72f3acb | 2598 | return 0; |
881f47b6 XH |
2599 | } |
2600 | ||
1c7a0623 | 2601 | static int |
53fddaf7 | 2602 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2603 | u64 offset, u32 len, |
8e004efc | 2604 | unsigned dispatch_flags) |
1c7a0623 | 2605 | { |
4a570db5 | 2606 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2607 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2608 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2609 | int ret; |
2610 | ||
5fb9de1a | 2611 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2612 | if (ret) |
2613 | return ret; | |
2614 | ||
2615 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2616 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2617 | (dispatch_flags & I915_DISPATCH_RS ? |
2618 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2619 | intel_ring_emit(engine, lower_32_bits(offset)); |
2620 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2621 | intel_ring_emit(engine, MI_NOOP); | |
2622 | intel_ring_advance(engine); | |
1c7a0623 BW |
2623 | |
2624 | return 0; | |
2625 | } | |
2626 | ||
d7d4eedd | 2627 | static int |
53fddaf7 | 2628 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2629 | u64 offset, u32 len, |
2630 | unsigned dispatch_flags) | |
d7d4eedd | 2631 | { |
4a570db5 | 2632 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2633 | int ret; |
2634 | ||
5fb9de1a | 2635 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2636 | if (ret) |
2637 | return ret; | |
2638 | ||
e2f80391 | 2639 | intel_ring_emit(engine, |
77072258 | 2640 | MI_BATCH_BUFFER_START | |
8e004efc | 2641 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2642 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2643 | (dispatch_flags & I915_DISPATCH_RS ? | |
2644 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2645 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2646 | intel_ring_emit(engine, offset); |
2647 | intel_ring_advance(engine); | |
d7d4eedd CW |
2648 | |
2649 | return 0; | |
2650 | } | |
2651 | ||
881f47b6 | 2652 | static int |
53fddaf7 | 2653 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2654 | u64 offset, u32 len, |
8e004efc | 2655 | unsigned dispatch_flags) |
881f47b6 | 2656 | { |
4a570db5 | 2657 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2658 | int ret; |
ab6f8e32 | 2659 | |
5fb9de1a | 2660 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2661 | if (ret) |
2662 | return ret; | |
e1f99ce6 | 2663 | |
e2f80391 | 2664 | intel_ring_emit(engine, |
d7d4eedd | 2665 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2666 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2667 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2668 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2669 | intel_ring_emit(engine, offset); |
2670 | intel_ring_advance(engine); | |
ab6f8e32 | 2671 | |
0206e353 | 2672 | return 0; |
881f47b6 XH |
2673 | } |
2674 | ||
549f7365 CW |
2675 | /* Blitter support (SandyBridge+) */ |
2676 | ||
a84c3ae1 | 2677 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2678 | u32 invalidate, u32 flush) |
8d19215b | 2679 | { |
4a570db5 | 2680 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2681 | struct drm_device *dev = engine->dev; |
71a77e07 | 2682 | uint32_t cmd; |
b72f3acb CW |
2683 | int ret; |
2684 | ||
5fb9de1a | 2685 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2686 | if (ret) |
2687 | return ret; | |
2688 | ||
71a77e07 | 2689 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2690 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2691 | cmd += 1; |
f0a1fb10 CW |
2692 | |
2693 | /* We always require a command barrier so that subsequent | |
2694 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2695 | * wrt the contents of the write cache being flushed to memory | |
2696 | * (and thus being coherent from the CPU). | |
2697 | */ | |
2698 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2699 | ||
9a289771 JB |
2700 | /* |
2701 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2702 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2703 | * operation is complete. This bit is only valid when the | |
2704 | * Post-Sync Operation field is a value of 1h or 3h." | |
2705 | */ | |
71a77e07 | 2706 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2707 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2708 | intel_ring_emit(engine, cmd); |
2709 | intel_ring_emit(engine, | |
2710 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
dbef0f15 | 2711 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 TU |
2712 | intel_ring_emit(engine, 0); /* upper addr */ |
2713 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2714 | } else { |
e2f80391 TU |
2715 | intel_ring_emit(engine, 0); |
2716 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2717 | } |
e2f80391 | 2718 | intel_ring_advance(engine); |
fd3da6c9 | 2719 | |
b72f3acb | 2720 | return 0; |
8d19215b ZN |
2721 | } |
2722 | ||
5c1143bb XH |
2723 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2724 | { | |
4640c4ff | 2725 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2726 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2727 | struct drm_i915_gem_object *obj; |
2728 | int ret; | |
5c1143bb | 2729 | |
e2f80391 TU |
2730 | engine->name = "render ring"; |
2731 | engine->id = RCS; | |
2732 | engine->exec_id = I915_EXEC_RENDER; | |
2733 | engine->mmio_base = RENDER_RING_BASE; | |
59465b5f | 2734 | |
707d9cf9 | 2735 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a | 2736 | if (i915_semaphore_is_enabled(dev)) { |
d37cd8a8 | 2737 | obj = i915_gem_object_create(dev, 4096); |
fe3db79b | 2738 | if (IS_ERR(obj)) { |
3e78998a BW |
2739 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); |
2740 | i915.semaphores = 0; | |
2741 | } else { | |
2742 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2743 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2744 | if (ret != 0) { | |
2745 | drm_gem_object_unreference(&obj->base); | |
2746 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2747 | i915.semaphores = 0; | |
2748 | } else | |
2749 | dev_priv->semaphore_obj = obj; | |
2750 | } | |
2751 | } | |
7225342a | 2752 | |
e2f80391 TU |
2753 | engine->init_context = intel_rcs_ctx_init; |
2754 | engine->add_request = gen6_add_request; | |
2755 | engine->flush = gen8_render_ring_flush; | |
2756 | engine->irq_get = gen8_ring_get_irq; | |
2757 | engine->irq_put = gen8_ring_put_irq; | |
2758 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2759 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2760 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2761 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2762 | if (i915_semaphore_is_enabled(dev)) { |
3e78998a | 2763 | WARN_ON(!dev_priv->semaphore_obj); |
e2f80391 TU |
2764 | engine->semaphore.sync_to = gen8_ring_sync; |
2765 | engine->semaphore.signal = gen8_rcs_signal; | |
2766 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 BW |
2767 | } |
2768 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
e2f80391 TU |
2769 | engine->init_context = intel_rcs_ctx_init; |
2770 | engine->add_request = gen6_add_request; | |
2771 | engine->flush = gen7_render_ring_flush; | |
6c6cf5aa | 2772 | if (INTEL_INFO(dev)->gen == 6) |
e2f80391 TU |
2773 | engine->flush = gen6_render_ring_flush; |
2774 | engine->irq_get = gen6_ring_get_irq; | |
2775 | engine->irq_put = gen6_ring_put_irq; | |
2776 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2777 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2778 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2779 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2780 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2781 | engine->semaphore.sync_to = gen6_ring_sync; |
2782 | engine->semaphore.signal = gen6_signal; | |
707d9cf9 BW |
2783 | /* |
2784 | * The current semaphore is only applied on pre-gen8 | |
2785 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2786 | * platform. So the semaphore between RCS and VCS2 is | |
2787 | * initialized as INVALID. Gen8 will initialize the | |
2788 | * sema between VCS2 and RCS later. | |
2789 | */ | |
e2f80391 TU |
2790 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2791 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2792 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2793 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2794 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2795 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2796 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2797 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2798 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2799 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2800 | } |
c6df541c | 2801 | } else if (IS_GEN5(dev)) { |
e2f80391 TU |
2802 | engine->add_request = pc_render_add_request; |
2803 | engine->flush = gen4_render_ring_flush; | |
2804 | engine->get_seqno = pc_render_get_seqno; | |
2805 | engine->set_seqno = pc_render_set_seqno; | |
2806 | engine->irq_get = gen5_ring_get_irq; | |
2807 | engine->irq_put = gen5_ring_put_irq; | |
2808 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | | |
cc609d5d | 2809 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 2810 | } else { |
e2f80391 | 2811 | engine->add_request = i9xx_add_request; |
46f0f8d1 | 2812 | if (INTEL_INFO(dev)->gen < 4) |
e2f80391 | 2813 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2814 | else |
e2f80391 TU |
2815 | engine->flush = gen4_render_ring_flush; |
2816 | engine->get_seqno = ring_get_seqno; | |
2817 | engine->set_seqno = ring_set_seqno; | |
c2798b19 | 2818 | if (IS_GEN2(dev)) { |
e2f80391 TU |
2819 | engine->irq_get = i8xx_ring_get_irq; |
2820 | engine->irq_put = i8xx_ring_put_irq; | |
c2798b19 | 2821 | } else { |
e2f80391 TU |
2822 | engine->irq_get = i9xx_ring_get_irq; |
2823 | engine->irq_put = i9xx_ring_put_irq; | |
c2798b19 | 2824 | } |
e2f80391 | 2825 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2826 | } |
e2f80391 | 2827 | engine->write_tail = ring_write_tail; |
707d9cf9 | 2828 | |
d7d4eedd | 2829 | if (IS_HASWELL(dev)) |
e2f80391 | 2830 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
1c7a0623 | 2831 | else if (IS_GEN8(dev)) |
e2f80391 | 2832 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
d7d4eedd | 2833 | else if (INTEL_INFO(dev)->gen >= 6) |
e2f80391 | 2834 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
fb3256da | 2835 | else if (INTEL_INFO(dev)->gen >= 4) |
e2f80391 | 2836 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
fb3256da | 2837 | else if (IS_I830(dev) || IS_845G(dev)) |
e2f80391 | 2838 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
fb3256da | 2839 | else |
e2f80391 TU |
2840 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
2841 | engine->init_hw = init_render_ring; | |
2842 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2843 | |
b45305fc DV |
2844 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2845 | if (HAS_BROKEN_CS_TLB(dev)) { | |
d37cd8a8 | 2846 | obj = i915_gem_object_create(dev, I830_WA_SIZE); |
fe3db79b | 2847 | if (IS_ERR(obj)) { |
b45305fc | 2848 | DRM_ERROR("Failed to allocate batch bo\n"); |
fe3db79b | 2849 | return PTR_ERR(obj); |
b45305fc DV |
2850 | } |
2851 | ||
be1fa129 | 2852 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2853 | if (ret != 0) { |
2854 | drm_gem_object_unreference(&obj->base); | |
2855 | DRM_ERROR("Failed to ping batch bo\n"); | |
2856 | return ret; | |
2857 | } | |
2858 | ||
e2f80391 TU |
2859 | engine->scratch.obj = obj; |
2860 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2861 | } |
2862 | ||
e2f80391 | 2863 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2864 | if (ret) |
2865 | return ret; | |
2866 | ||
2867 | if (INTEL_INFO(dev)->gen >= 5) { | |
e2f80391 | 2868 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2869 | if (ret) |
2870 | return ret; | |
2871 | } | |
2872 | ||
2873 | return 0; | |
5c1143bb XH |
2874 | } |
2875 | ||
2876 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2877 | { | |
4640c4ff | 2878 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2879 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2880 | |
e2f80391 TU |
2881 | engine->name = "bsd ring"; |
2882 | engine->id = VCS; | |
2883 | engine->exec_id = I915_EXEC_BSD; | |
58fa3835 | 2884 | |
e2f80391 | 2885 | engine->write_tail = ring_write_tail; |
780f18c8 | 2886 | if (INTEL_INFO(dev)->gen >= 6) { |
e2f80391 | 2887 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2888 | /* gen6 bsd needs a special wa for tail updates */ |
2889 | if (IS_GEN6(dev)) | |
e2f80391 TU |
2890 | engine->write_tail = gen6_bsd_ring_write_tail; |
2891 | engine->flush = gen6_bsd_ring_flush; | |
2892 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2893 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2894 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2895 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 2896 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 2897 | engine->irq_enable_mask = |
abd58f01 | 2898 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
e2f80391 TU |
2899 | engine->irq_get = gen8_ring_get_irq; |
2900 | engine->irq_put = gen8_ring_put_irq; | |
2901 | engine->dispatch_execbuffer = | |
1c7a0623 | 2902 | gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2903 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2904 | engine->semaphore.sync_to = gen8_ring_sync; |
2905 | engine->semaphore.signal = gen8_xcs_signal; | |
2906 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 2907 | } |
abd58f01 | 2908 | } else { |
e2f80391 TU |
2909 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
2910 | engine->irq_get = gen6_ring_get_irq; | |
2911 | engine->irq_put = gen6_ring_put_irq; | |
2912 | engine->dispatch_execbuffer = | |
1c7a0623 | 2913 | gen6_ring_dispatch_execbuffer; |
707d9cf9 | 2914 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2915 | engine->semaphore.sync_to = gen6_ring_sync; |
2916 | engine->semaphore.signal = gen6_signal; | |
2917 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2918 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2919 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2920 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2921 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2922 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2923 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2924 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2925 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2926 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2927 | } |
abd58f01 | 2928 | } |
58fa3835 | 2929 | } else { |
e2f80391 TU |
2930 | engine->mmio_base = BSD_RING_BASE; |
2931 | engine->flush = bsd_ring_flush; | |
2932 | engine->add_request = i9xx_add_request; | |
2933 | engine->get_seqno = ring_get_seqno; | |
2934 | engine->set_seqno = ring_set_seqno; | |
e48d8634 | 2935 | if (IS_GEN5(dev)) { |
e2f80391 TU |
2936 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
2937 | engine->irq_get = gen5_ring_get_irq; | |
2938 | engine->irq_put = gen5_ring_put_irq; | |
e48d8634 | 2939 | } else { |
e2f80391 TU |
2940 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
2941 | engine->irq_get = i9xx_ring_get_irq; | |
2942 | engine->irq_put = i9xx_ring_put_irq; | |
e48d8634 | 2943 | } |
e2f80391 | 2944 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2945 | } |
e2f80391 | 2946 | engine->init_hw = init_ring_common; |
58fa3835 | 2947 | |
e2f80391 | 2948 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 2949 | } |
549f7365 | 2950 | |
845f74a7 | 2951 | /** |
62659920 | 2952 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2953 | */ |
2954 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2955 | { | |
2956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2957 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
2958 | |
2959 | engine->name = "bsd2 ring"; | |
2960 | engine->id = VCS2; | |
2961 | engine->exec_id = I915_EXEC_BSD; | |
2962 | ||
2963 | engine->write_tail = ring_write_tail; | |
2964 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
2965 | engine->flush = gen6_bsd_ring_flush; | |
2966 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2967 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2968 | engine->get_seqno = ring_get_seqno; | |
e2f80391 TU |
2969 | engine->set_seqno = ring_set_seqno; |
2970 | engine->irq_enable_mask = | |
845f74a7 | 2971 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
e2f80391 TU |
2972 | engine->irq_get = gen8_ring_get_irq; |
2973 | engine->irq_put = gen8_ring_put_irq; | |
2974 | engine->dispatch_execbuffer = | |
845f74a7 | 2975 | gen8_ring_dispatch_execbuffer; |
3e78998a | 2976 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2977 | engine->semaphore.sync_to = gen8_ring_sync; |
2978 | engine->semaphore.signal = gen8_xcs_signal; | |
2979 | GEN8_RING_SEMAPHORE_INIT(engine); | |
3e78998a | 2980 | } |
e2f80391 | 2981 | engine->init_hw = init_ring_common; |
845f74a7 | 2982 | |
e2f80391 | 2983 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
2984 | } |
2985 | ||
549f7365 CW |
2986 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2987 | { | |
4640c4ff | 2988 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2989 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
2990 | |
2991 | engine->name = "blitter ring"; | |
2992 | engine->id = BCS; | |
2993 | engine->exec_id = I915_EXEC_BLT; | |
2994 | ||
2995 | engine->mmio_base = BLT_RING_BASE; | |
2996 | engine->write_tail = ring_write_tail; | |
2997 | engine->flush = gen6_ring_flush; | |
2998 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2999 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3000 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3001 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 3002 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 3003 | engine->irq_enable_mask = |
abd58f01 | 3004 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
e2f80391 TU |
3005 | engine->irq_get = gen8_ring_get_irq; |
3006 | engine->irq_put = gen8_ring_put_irq; | |
3007 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3008 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3009 | engine->semaphore.sync_to = gen8_ring_sync; |
3010 | engine->semaphore.signal = gen8_xcs_signal; | |
3011 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3012 | } |
abd58f01 | 3013 | } else { |
e2f80391 TU |
3014 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3015 | engine->irq_get = gen6_ring_get_irq; | |
3016 | engine->irq_put = gen6_ring_put_irq; | |
3017 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3018 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3019 | engine->semaphore.signal = gen6_signal; |
3020 | engine->semaphore.sync_to = gen6_ring_sync; | |
707d9cf9 BW |
3021 | /* |
3022 | * The current semaphore is only applied on pre-gen8 | |
3023 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3024 | * platform. So the semaphore between BCS and VCS2 is | |
3025 | * initialized as INVALID. Gen8 will initialize the | |
3026 | * sema between BCS and VCS2 later. | |
3027 | */ | |
e2f80391 TU |
3028 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3029 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3030 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3031 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3032 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3033 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3034 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3035 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3036 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3037 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3038 | } |
abd58f01 | 3039 | } |
e2f80391 | 3040 | engine->init_hw = init_ring_common; |
549f7365 | 3041 | |
e2f80391 | 3042 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3043 | } |
a7b9761d | 3044 | |
9a8a2213 BW |
3045 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3046 | { | |
4640c4ff | 3047 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3048 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3049 | |
e2f80391 TU |
3050 | engine->name = "video enhancement ring"; |
3051 | engine->id = VECS; | |
3052 | engine->exec_id = I915_EXEC_VEBOX; | |
9a8a2213 | 3053 | |
e2f80391 TU |
3054 | engine->mmio_base = VEBOX_RING_BASE; |
3055 | engine->write_tail = ring_write_tail; | |
3056 | engine->flush = gen6_ring_flush; | |
3057 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3058 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3059 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3060 | engine->set_seqno = ring_set_seqno; |
abd58f01 BW |
3061 | |
3062 | if (INTEL_INFO(dev)->gen >= 8) { | |
e2f80391 | 3063 | engine->irq_enable_mask = |
40c499f9 | 3064 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
e2f80391 TU |
3065 | engine->irq_get = gen8_ring_get_irq; |
3066 | engine->irq_put = gen8_ring_put_irq; | |
3067 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3068 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3069 | engine->semaphore.sync_to = gen8_ring_sync; |
3070 | engine->semaphore.signal = gen8_xcs_signal; | |
3071 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3072 | } |
abd58f01 | 3073 | } else { |
e2f80391 TU |
3074 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3075 | engine->irq_get = hsw_vebox_get_irq; | |
3076 | engine->irq_put = hsw_vebox_put_irq; | |
3077 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3078 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3079 | engine->semaphore.sync_to = gen6_ring_sync; |
3080 | engine->semaphore.signal = gen6_signal; | |
3081 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3082 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3083 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3084 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3085 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3086 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3087 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3088 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3089 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3090 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3091 | } |
abd58f01 | 3092 | } |
e2f80391 | 3093 | engine->init_hw = init_ring_common; |
9a8a2213 | 3094 | |
e2f80391 | 3095 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3096 | } |
3097 | ||
a7b9761d | 3098 | int |
4866d729 | 3099 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3100 | { |
4a570db5 | 3101 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3102 | int ret; |
3103 | ||
e2f80391 | 3104 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3105 | return 0; |
3106 | ||
e2f80391 | 3107 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3108 | if (ret) |
3109 | return ret; | |
3110 | ||
a84c3ae1 | 3111 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3112 | |
e2f80391 | 3113 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3114 | return 0; |
3115 | } | |
3116 | ||
3117 | int | |
2f20055d | 3118 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3119 | { |
4a570db5 | 3120 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3121 | uint32_t flush_domains; |
3122 | int ret; | |
3123 | ||
3124 | flush_domains = 0; | |
e2f80391 | 3125 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3126 | flush_domains = I915_GEM_GPU_DOMAINS; |
3127 | ||
e2f80391 | 3128 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3129 | if (ret) |
3130 | return ret; | |
3131 | ||
a84c3ae1 | 3132 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3133 | |
e2f80391 | 3134 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3135 | return 0; |
3136 | } | |
e3efda49 CW |
3137 | |
3138 | void | |
117897f4 | 3139 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3140 | { |
3141 | int ret; | |
3142 | ||
117897f4 | 3143 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3144 | return; |
3145 | ||
666796da | 3146 | ret = intel_engine_idle(engine); |
f4457ae7 | 3147 | if (ret) |
e3efda49 | 3148 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3149 | engine->name, ret); |
e3efda49 | 3150 | |
0bc40be8 | 3151 | stop_ring(engine); |
e3efda49 | 3152 | } |