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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/drmP.h> |
760285e7 | 33 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
34 | |
35 | #include "i915_drv.h" | |
36 | #include "i915_gem_render_state.h" | |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
7d3c425f | 39 | #include "intel_workarounds.h" |
62fdfeaf | 40 | |
a0442461 CW |
41 | /* Rough estimate of the typical request size, performing a flush, |
42 | * set-context and then emitting the batch. | |
43 | */ | |
44 | #define LEGACY_REQUEST_SIZE 200 | |
45 | ||
605d5b32 CW |
46 | static unsigned int __intel_ring_space(unsigned int head, |
47 | unsigned int tail, | |
48 | unsigned int size) | |
c7dca47b | 49 | { |
605d5b32 CW |
50 | /* |
51 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
52 | * same cacheline, the Head Pointer must not be greater than the Tail | |
53 | * Pointer." | |
54 | */ | |
55 | GEM_BUG_ON(!is_power_of_2(size)); | |
56 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
57 | } |
58 | ||
95aebcb2 | 59 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 60 | { |
95aebcb2 CW |
61 | unsigned int space; |
62 | ||
63 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
64 | ||
65 | ring->space = space; | |
66 | return space; | |
ebd0fd4b DG |
67 | } |
68 | ||
b72f3acb | 69 | static int |
e61e0f51 | 70 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 71 | { |
73dec95e | 72 | u32 cmd, *cs; |
46f0f8d1 CW |
73 | |
74 | cmd = MI_FLUSH; | |
46f0f8d1 | 75 | |
7c9cf4e3 | 76 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
77 | cmd |= MI_READ_FLUSH; |
78 | ||
e61e0f51 | 79 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
80 | if (IS_ERR(cs)) |
81 | return PTR_ERR(cs); | |
46f0f8d1 | 82 | |
73dec95e TU |
83 | *cs++ = cmd; |
84 | *cs++ = MI_NOOP; | |
e61e0f51 | 85 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static int | |
e61e0f51 | 91 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 92 | { |
73dec95e | 93 | u32 cmd, *cs; |
6f392d54 | 94 | |
36d527de CW |
95 | /* |
96 | * read/write caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
99 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
100 | * also flushed at 2d versus 3d pipeline switches. | |
101 | * | |
102 | * read-only caches: | |
103 | * | |
104 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
105 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
106 | * | |
107 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
108 | * | |
109 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
110 | * invalidated when MI_EXE_FLUSH is set. | |
111 | * | |
112 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
113 | * invalidated with every MI_FLUSH. | |
114 | * | |
115 | * TLBs: | |
116 | * | |
117 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
118 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
119 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
120 | * are flushed at any MI_FLUSH. | |
121 | */ | |
122 | ||
b5321f30 | 123 | cmd = MI_FLUSH; |
7c9cf4e3 | 124 | if (mode & EMIT_INVALIDATE) { |
36d527de | 125 | cmd |= MI_EXE_FLUSH; |
e61e0f51 | 126 | if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) |
b5321f30 CW |
127 | cmd |= MI_INVALIDATE_ISP; |
128 | } | |
70eac33e | 129 | |
e61e0f51 | 130 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
131 | if (IS_ERR(cs)) |
132 | return PTR_ERR(cs); | |
b72f3acb | 133 | |
73dec95e TU |
134 | *cs++ = cmd; |
135 | *cs++ = MI_NOOP; | |
e61e0f51 | 136 | intel_ring_advance(rq, cs); |
b72f3acb CW |
137 | |
138 | return 0; | |
8187a2b7 ZN |
139 | } |
140 | ||
179f4025 | 141 | /* |
8d315287 JB |
142 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
143 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
144 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
145 | * | |
146 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
147 | * produced by non-pipelined state commands), software needs to first | |
148 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
149 | * 0. | |
150 | * | |
151 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
152 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
153 | * | |
154 | * And the workaround for these two requires this workaround first: | |
155 | * | |
156 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
157 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
158 | * flushes. | |
159 | * | |
160 | * And this last workaround is tricky because of the requirements on | |
161 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
162 | * volume 2 part 1: | |
163 | * | |
164 | * "1 of the following must also be set: | |
165 | * - Render Target Cache Flush Enable ([12] of DW1) | |
166 | * - Depth Cache Flush Enable ([0] of DW1) | |
167 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
168 | * - Depth Stall ([13] of DW1) | |
169 | * - Post-Sync Operation ([13] of DW1) | |
170 | * - Notify Enable ([8] of DW1)" | |
171 | * | |
172 | * The cache flushes require the workaround flush that triggered this | |
173 | * one, so we can't use it. Depth stall would trigger the same. | |
174 | * Post-sync nonzero is what triggered this second workaround, so we | |
175 | * can't use that one either. Notify enable is IRQs, which aren't | |
176 | * really our business. That leaves only stall at scoreboard. | |
177 | */ | |
178 | static int | |
e61e0f51 | 179 | intel_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 180 | { |
b5321f30 | 181 | u32 scratch_addr = |
e61e0f51 | 182 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
183 | u32 *cs; |
184 | ||
e61e0f51 | 185 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
186 | if (IS_ERR(cs)) |
187 | return PTR_ERR(cs); | |
188 | ||
189 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
190 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
191 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
192 | *cs++ = 0; /* low dword */ | |
193 | *cs++ = 0; /* high dword */ | |
194 | *cs++ = MI_NOOP; | |
e61e0f51 | 195 | intel_ring_advance(rq, cs); |
73dec95e | 196 | |
e61e0f51 | 197 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
198 | if (IS_ERR(cs)) |
199 | return PTR_ERR(cs); | |
200 | ||
201 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
202 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
203 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
204 | *cs++ = 0; | |
205 | *cs++ = 0; | |
206 | *cs++ = MI_NOOP; | |
e61e0f51 | 207 | intel_ring_advance(rq, cs); |
8d315287 JB |
208 | |
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
e61e0f51 | 213 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 214 | { |
b5321f30 | 215 | u32 scratch_addr = |
e61e0f51 | 216 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 217 | u32 *cs, flags = 0; |
8d315287 JB |
218 | int ret; |
219 | ||
b3111509 | 220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
e61e0f51 | 221 | ret = intel_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
222 | if (ret) |
223 | return ret; | |
224 | ||
8d315287 JB |
225 | /* Just flush everything. Experiments have shown that reducing the |
226 | * number of bits based on the write domains has little performance | |
227 | * impact. | |
228 | */ | |
7c9cf4e3 | 229 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
231 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
232 | /* | |
233 | * Ensure that any following seqno writes only happen | |
234 | * when the render cache is indeed flushed. | |
235 | */ | |
97f209bc | 236 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 237 | } |
7c9cf4e3 | 238 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
239 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
240 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
244 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
245 | /* | |
246 | * TLB invalidate requires a post-sync write. | |
247 | */ | |
3ac78313 | 248 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 249 | } |
8d315287 | 250 | |
e61e0f51 | 251 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
252 | if (IS_ERR(cs)) |
253 | return PTR_ERR(cs); | |
8d315287 | 254 | |
73dec95e TU |
255 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
256 | *cs++ = flags; | |
257 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
258 | *cs++ = 0; | |
e61e0f51 | 259 | intel_ring_advance(rq, cs); |
8d315287 JB |
260 | |
261 | return 0; | |
262 | } | |
263 | ||
f3987631 | 264 | static int |
e61e0f51 | 265 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 266 | { |
73dec95e | 267 | u32 *cs; |
f3987631 | 268 | |
e61e0f51 | 269 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
270 | if (IS_ERR(cs)) |
271 | return PTR_ERR(cs); | |
f3987631 | 272 | |
73dec95e TU |
273 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
274 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
275 | *cs++ = 0; | |
276 | *cs++ = 0; | |
e61e0f51 | 277 | intel_ring_advance(rq, cs); |
f3987631 PZ |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
4772eaeb | 282 | static int |
e61e0f51 | 283 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 284 | { |
b5321f30 | 285 | u32 scratch_addr = |
e61e0f51 | 286 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 287 | u32 *cs, flags = 0; |
4772eaeb | 288 | |
f3987631 PZ |
289 | /* |
290 | * Ensure that any following seqno writes only happen when the render | |
291 | * cache is indeed flushed. | |
292 | * | |
293 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
294 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
295 | * don't try to be clever and just set it unconditionally. | |
296 | */ | |
297 | flags |= PIPE_CONTROL_CS_STALL; | |
298 | ||
4772eaeb PZ |
299 | /* Just flush everything. Experiments have shown that reducing the |
300 | * number of bits based on the write domains has little performance | |
301 | * impact. | |
302 | */ | |
7c9cf4e3 | 303 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
304 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
305 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 306 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 307 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 308 | } |
7c9cf4e3 | 309 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
310 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
311 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
312 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
313 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
314 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
315 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 316 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
317 | /* |
318 | * TLB invalidate requires a post-sync write. | |
319 | */ | |
320 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 321 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 322 | |
add284a3 CW |
323 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
324 | ||
f3987631 PZ |
325 | /* Workaround: we must issue a pipe_control with CS-stall bit |
326 | * set before a pipe_control command that has the state cache | |
327 | * invalidate bit set. */ | |
e61e0f51 | 328 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
329 | } |
330 | ||
e61e0f51 | 331 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
332 | if (IS_ERR(cs)) |
333 | return PTR_ERR(cs); | |
4772eaeb | 334 | |
73dec95e TU |
335 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
336 | *cs++ = flags; | |
337 | *cs++ = scratch_addr; | |
338 | *cs++ = 0; | |
e61e0f51 | 339 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
0bc40be8 | 344 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 345 | { |
c033666a | 346 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
347 | u32 addr; |
348 | ||
349 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 350 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
351 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
352 | I915_WRITE(HWS_PGA, addr); | |
353 | } | |
354 | ||
0bc40be8 | 355 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 356 | { |
c033666a | 357 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 358 | i915_reg_t mmio; |
af75f269 DL |
359 | |
360 | /* The ring status page addresses are no longer next to the rest of | |
361 | * the ring registers as of gen7. | |
362 | */ | |
c033666a | 363 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 364 | switch (engine->id) { |
a2d3d265 MT |
365 | /* |
366 | * No more rings exist on Gen7. Default case is only to shut up | |
367 | * gcc switch check warning. | |
368 | */ | |
369 | default: | |
370 | GEM_BUG_ON(engine->id); | |
af75f269 DL |
371 | case RCS: |
372 | mmio = RENDER_HWS_PGA_GEN7; | |
373 | break; | |
374 | case BCS: | |
375 | mmio = BLT_HWS_PGA_GEN7; | |
376 | break; | |
af75f269 DL |
377 | case VCS: |
378 | mmio = BSD_HWS_PGA_GEN7; | |
379 | break; | |
380 | case VECS: | |
381 | mmio = VEBOX_HWS_PGA_GEN7; | |
382 | break; | |
383 | } | |
c033666a | 384 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 385 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 386 | } else { |
0bc40be8 | 387 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
388 | } |
389 | ||
c5498089 VS |
390 | if (INTEL_GEN(dev_priv) >= 6) |
391 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
392 | ||
57e88531 | 393 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
394 | POSTING_READ(mmio); |
395 | ||
79e6770c | 396 | /* Flush the TLB for this page */ |
ac657f64 | 397 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 398 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
399 | |
400 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 401 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
402 | |
403 | I915_WRITE(reg, | |
404 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
405 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
406 | if (intel_wait_for_register(dev_priv, |
407 | reg, INSTPM_SYNC_FLUSH, 0, | |
408 | 1000)) | |
af75f269 | 409 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 410 | engine->name); |
af75f269 DL |
411 | } |
412 | } | |
413 | ||
0bc40be8 | 414 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 415 | { |
c033666a | 416 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 417 | |
21a2c58a | 418 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 419 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
420 | if (intel_wait_for_register(dev_priv, |
421 | RING_MI_MODE(engine->mmio_base), | |
422 | MODE_IDLE, | |
423 | MODE_IDLE, | |
424 | 1000)) { | |
0bc40be8 TU |
425 | DRM_ERROR("%s : timed out trying to stop ring\n", |
426 | engine->name); | |
9bec9b13 CW |
427 | /* Sometimes we observe that the idle flag is not |
428 | * set even though the ring is empty. So double | |
429 | * check before giving up. | |
430 | */ | |
0bc40be8 | 431 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 432 | return false; |
9991ae78 CW |
433 | } |
434 | } | |
b7884eb4 | 435 | |
11caf551 CW |
436 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
437 | ||
0bc40be8 | 438 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 439 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 440 | |
11caf551 CW |
441 | /* The ring must be empty before it is disabled */ |
442 | I915_WRITE_CTL(engine, 0); | |
443 | ||
0bc40be8 | 444 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 445 | } |
8187a2b7 | 446 | |
0bc40be8 | 447 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 448 | { |
c033666a | 449 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 450 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
451 | int ret = 0; |
452 | ||
59bad947 | 453 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 454 | |
0bc40be8 | 455 | if (!stop_ring(engine)) { |
9991ae78 | 456 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
457 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
458 | "ctl %08x head %08x tail %08x start %08x\n", | |
459 | engine->name, | |
460 | I915_READ_CTL(engine), | |
461 | I915_READ_HEAD(engine), | |
462 | I915_READ_TAIL(engine), | |
463 | I915_READ_START(engine)); | |
8187a2b7 | 464 | |
0bc40be8 | 465 | if (!stop_ring(engine)) { |
6fd0d56e CW |
466 | DRM_ERROR("failed to set %s head to zero " |
467 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
468 | engine->name, |
469 | I915_READ_CTL(engine), | |
470 | I915_READ_HEAD(engine), | |
471 | I915_READ_TAIL(engine), | |
472 | I915_READ_START(engine)); | |
9991ae78 CW |
473 | ret = -EIO; |
474 | goto out; | |
6fd0d56e | 475 | } |
8187a2b7 ZN |
476 | } |
477 | ||
3177659a | 478 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 479 | ring_setup_phys_status_page(engine); |
3177659a CS |
480 | else |
481 | intel_ring_setup_status_page(engine); | |
9991ae78 | 482 | |
ad07dfcd | 483 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 484 | |
ece4a17d | 485 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 486 | I915_READ_HEAD(engine); |
ece4a17d | 487 | |
0d8957c8 DV |
488 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
489 | * registers with the above sequence (the readback of the HEAD registers | |
490 | * also enforces ordering), otherwise the hw might lose the new ring | |
491 | * register values. */ | |
bde13ebd | 492 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
493 | |
494 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 495 | if (I915_READ_HEAD(engine)) |
8177e112 CW |
496 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
497 | engine->name, I915_READ_HEAD(engine)); | |
821ed7df CW |
498 | |
499 | intel_ring_update_space(ring); | |
500 | I915_WRITE_HEAD(engine, ring->head); | |
501 | I915_WRITE_TAIL(engine, ring->tail); | |
502 | (void)I915_READ_TAIL(engine); | |
95468892 | 503 | |
62ae14b1 | 504 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 505 | |
8187a2b7 | 506 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
507 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
508 | RING_VALID, RING_VALID, | |
509 | 50)) { | |
e74cfed5 | 510 | DRM_ERROR("%s initialization failed " |
821ed7df | 511 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
512 | engine->name, |
513 | I915_READ_CTL(engine), | |
514 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
515 | I915_READ_HEAD(engine), ring->head, |
516 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 517 | I915_READ_START(engine), |
bde13ebd | 518 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
519 | ret = -EIO; |
520 | goto out; | |
8187a2b7 ZN |
521 | } |
522 | ||
fc0768ce | 523 | intel_engine_init_hangcheck(engine); |
50f018df | 524 | |
7836cd02 CW |
525 | if (INTEL_GEN(dev_priv) > 2) |
526 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
527 | ||
b7884eb4 | 528 | out: |
59bad947 | 529 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
530 | |
531 | return ret; | |
8187a2b7 ZN |
532 | } |
533 | ||
821ed7df | 534 | static void reset_ring_common(struct intel_engine_cs *engine, |
e61e0f51 | 535 | struct i915_request *request) |
821ed7df | 536 | { |
67e64564 CW |
537 | /* |
538 | * RC6 must be prevented until the reset is complete and the engine | |
539 | * reinitialised. If it occurs in the middle of this sequence, the | |
540 | * state written to/loaded from the power context is ill-defined (e.g. | |
541 | * the PP_BASE_DIR may be lost). | |
542 | */ | |
543 | assert_forcewakes_active(engine->i915, FORCEWAKE_ALL); | |
544 | ||
545 | /* | |
546 | * Try to restore the logical GPU state to match the continuation | |
c0dcb203 CW |
547 | * of the request queue. If we skip the context/PD restore, then |
548 | * the next request may try to execute assuming that its context | |
549 | * is valid and loaded on the GPU and so may try to access invalid | |
550 | * memory, prompting repeated GPU hangs. | |
551 | * | |
552 | * If the request was guilty, we still restore the logical state | |
553 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
554 | * but skip over the hung batch. | |
555 | * | |
556 | * If the request was innocent, we try to replay the request with | |
557 | * the restored context. | |
558 | */ | |
559 | if (request) { | |
560 | struct drm_i915_private *dev_priv = request->i915; | |
561 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
562 | struct i915_hw_ppgtt *ppgtt; | |
563 | ||
c0dcb203 CW |
564 | if (ce->state) { |
565 | I915_WRITE(CCID, | |
566 | i915_ggtt_offset(ce->state) | | |
567 | BIT(8) /* must be set! */ | | |
568 | CCID_EXTENDED_STATE_SAVE | | |
569 | CCID_EXTENDED_STATE_RESTORE | | |
570 | CCID_EN); | |
571 | } | |
572 | ||
573 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
574 | if (ppgtt) { | |
575 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
576 | ||
577 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
578 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
579 | ||
580 | /* Wait for the PD reload to complete */ | |
581 | if (intel_wait_for_register(dev_priv, | |
582 | RING_PP_DIR_BASE(engine), | |
583 | BIT(0), 0, | |
584 | 10)) | |
585 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 586 | |
c0dcb203 CW |
587 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
588 | } | |
589 | ||
590 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
fe085f13 CW |
591 | if (request->fence.error == -EIO) |
592 | request->ring->head = request->postfix; | |
c0dcb203 CW |
593 | } else { |
594 | engine->legacy_active_context = NULL; | |
b1c24a61 | 595 | engine->legacy_active_ppgtt = NULL; |
c0dcb203 | 596 | } |
821ed7df CW |
597 | } |
598 | ||
e61e0f51 | 599 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
600 | { |
601 | int ret; | |
602 | ||
59b449d5 | 603 | ret = intel_ctx_workarounds_emit(rq); |
8f0e2b9d DV |
604 | if (ret != 0) |
605 | return ret; | |
606 | ||
e61e0f51 | 607 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 608 | if (ret) |
e26e1b97 | 609 | return ret; |
8f0e2b9d | 610 | |
e26e1b97 | 611 | return 0; |
8f0e2b9d DV |
612 | } |
613 | ||
0bc40be8 | 614 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 615 | { |
c033666a | 616 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 617 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
618 | if (ret) |
619 | return ret; | |
a69ffdbf | 620 | |
f4ecfbfc | 621 | intel_whitelist_workarounds_apply(engine); |
59b449d5 | 622 | |
61a563a2 | 623 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 624 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 625 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
626 | |
627 | /* We need to disable the AsyncFlip performance optimisations in order | |
628 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
629 | * programmed to '1' on all products. | |
8693a824 | 630 | * |
2441f877 | 631 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 632 | */ |
ac657f64 | 633 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
634 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
635 | ||
f05bb0c7 | 636 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 637 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 638 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 639 | I915_WRITE(GFX_MODE, |
aa83e30d | 640 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 641 | |
01fa0302 | 642 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 643 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 644 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 645 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 646 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 647 | |
c033666a | 648 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
649 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
650 | * "If this bit is set, STCunit will have LRA as replacement | |
651 | * policy. [...] This bit must be reset. LRA replacement | |
652 | * policy is not supported." | |
653 | */ | |
654 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 655 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
656 | } |
657 | ||
ac657f64 | 658 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 659 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 660 | |
c56b89f1 | 661 | if (INTEL_GEN(dev_priv) >= 6) |
035ea405 | 662 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
15b9f80e | 663 | |
59b449d5 | 664 | return 0; |
8187a2b7 ZN |
665 | } |
666 | ||
e61e0f51 | 667 | static u32 *gen6_signal(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 668 | { |
e61e0f51 | 669 | struct drm_i915_private *dev_priv = rq->i915; |
318f89ca | 670 | struct intel_engine_cs *engine; |
3b3f1650 | 671 | enum intel_engine_id id; |
caddfe71 | 672 | int num_rings = 0; |
024a43e1 | 673 | |
3b3f1650 | 674 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
675 | i915_reg_t mbox_reg; |
676 | ||
677 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
678 | continue; | |
f0f59a00 | 679 | |
e61e0f51 | 680 | mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 681 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
682 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
683 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
e61e0f51 | 684 | *cs++ = rq->global_seqno; |
caddfe71 | 685 | num_rings++; |
78325f2d BW |
686 | } |
687 | } | |
caddfe71 | 688 | if (num_rings & 1) |
73dec95e | 689 | *cs++ = MI_NOOP; |
024a43e1 | 690 | |
73dec95e | 691 | return cs; |
1ec14ad3 CW |
692 | } |
693 | ||
27a5f61b CW |
694 | static void cancel_requests(struct intel_engine_cs *engine) |
695 | { | |
e61e0f51 | 696 | struct i915_request *request; |
27a5f61b CW |
697 | unsigned long flags; |
698 | ||
699 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
700 | ||
701 | /* Mark all submitted requests as skipped. */ | |
702 | list_for_each_entry(request, &engine->timeline->requests, link) { | |
703 | GEM_BUG_ON(!request->global_seqno); | |
e61e0f51 | 704 | if (!i915_request_completed(request)) |
27a5f61b CW |
705 | dma_fence_set_error(&request->fence, -EIO); |
706 | } | |
707 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
708 | ||
709 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
710 | } | |
711 | ||
e61e0f51 | 712 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d CW |
713 | { |
714 | struct drm_i915_private *dev_priv = request->i915; | |
715 | ||
e61e0f51 | 716 | i915_request_submit(request); |
d55ac5bf | 717 | |
e6ba9992 CW |
718 | I915_WRITE_TAIL(request->engine, |
719 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
720 | } |
721 | ||
e61e0f51 | 722 | static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 723 | { |
73dec95e TU |
724 | *cs++ = MI_STORE_DWORD_INDEX; |
725 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
e61e0f51 | 726 | *cs++ = rq->global_seqno; |
73dec95e | 727 | *cs++ = MI_USER_INTERRUPT; |
1ec14ad3 | 728 | |
e61e0f51 CW |
729 | rq->tail = intel_ring_offset(rq, cs); |
730 | assert_ring_tail_valid(rq->ring, rq->tail); | |
1ec14ad3 CW |
731 | } |
732 | ||
98f29e8d CW |
733 | static const int i9xx_emit_breadcrumb_sz = 4; |
734 | ||
e61e0f51 | 735 | static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
b0411e7d | 736 | { |
e61e0f51 | 737 | return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs)); |
b0411e7d CW |
738 | } |
739 | ||
c8c99b0f | 740 | static int |
e61e0f51 | 741 | gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal) |
1ec14ad3 | 742 | { |
c8c99b0f BW |
743 | u32 dw1 = MI_SEMAPHORE_MBOX | |
744 | MI_SEMAPHORE_COMPARE | | |
745 | MI_SEMAPHORE_REGISTER; | |
e61e0f51 | 746 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id]; |
73dec95e | 747 | u32 *cs; |
1ec14ad3 | 748 | |
ebc348b2 | 749 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 750 | |
e61e0f51 | 751 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
752 | if (IS_ERR(cs)) |
753 | return PTR_ERR(cs); | |
1ec14ad3 | 754 | |
73dec95e | 755 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
756 | /* Throughout all of the GEM code, seqno passed implies our current |
757 | * seqno is >= the last seqno executed. However for hardware the | |
758 | * comparison is strictly greater than. | |
759 | */ | |
73dec95e TU |
760 | *cs++ = signal->global_seqno - 1; |
761 | *cs++ = 0; | |
762 | *cs++ = MI_NOOP; | |
e61e0f51 | 763 | intel_ring_advance(rq, cs); |
1ec14ad3 CW |
764 | |
765 | return 0; | |
766 | } | |
767 | ||
f8973c21 | 768 | static void |
38a0f2db | 769 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 770 | { |
f8973c21 CW |
771 | /* MI_STORE are internally buffered by the GPU and not flushed |
772 | * either by MI_FLUSH or SyncFlush or any other combination of | |
773 | * MI commands. | |
c6df541c | 774 | * |
f8973c21 CW |
775 | * "Only the submission of the store operation is guaranteed. |
776 | * The write result will be complete (coherent) some time later | |
777 | * (this is practically a finite period but there is no guaranteed | |
778 | * latency)." | |
779 | * | |
780 | * Empirically, we observe that we need a delay of at least 75us to | |
781 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 782 | */ |
f8973c21 | 783 | usleep_range(125, 250); |
c6df541c CW |
784 | } |
785 | ||
c04e0f3b CW |
786 | static void |
787 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 788 | { |
c033666a | 789 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 790 | |
4cd53c0c DV |
791 | /* Workaround to force correct ordering between irq and seqno writes on |
792 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
793 | * ACTHD) before reading the status page. |
794 | * | |
795 | * Note that this effectively stalls the read by the time it takes to | |
796 | * do a memory transaction, which more or less ensures that the write | |
797 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
798 | * Alternatively we could delay the interrupt from the CS ring to give | |
799 | * the write time to land, but that would incur a delay after every | |
800 | * batch i.e. much more frequent than a delay when waiting for the | |
801 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
802 | * |
803 | * Also note that to prevent whole machine hangs on gen7, we have to | |
804 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 805 | */ |
bcbdb6d0 | 806 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 807 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 808 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
809 | } |
810 | ||
31bb59cc CW |
811 | static void |
812 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 813 | { |
31bb59cc | 814 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
815 | } |
816 | ||
817 | static void | |
31bb59cc | 818 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 819 | { |
31bb59cc | 820 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
821 | } |
822 | ||
31bb59cc CW |
823 | static void |
824 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 825 | { |
c033666a | 826 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 827 | |
31bb59cc CW |
828 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
829 | I915_WRITE(IMR, dev_priv->irq_mask); | |
830 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
831 | } |
832 | ||
8187a2b7 | 833 | static void |
31bb59cc | 834 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 835 | { |
c033666a | 836 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 837 | |
31bb59cc CW |
838 | dev_priv->irq_mask |= engine->irq_enable_mask; |
839 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
840 | } |
841 | ||
31bb59cc CW |
842 | static void |
843 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 844 | { |
c033666a | 845 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 846 | |
31bb59cc CW |
847 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
848 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
849 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
850 | } |
851 | ||
852 | static void | |
31bb59cc | 853 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 854 | { |
c033666a | 855 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 856 | |
31bb59cc CW |
857 | dev_priv->irq_mask |= engine->irq_enable_mask; |
858 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
859 | } |
860 | ||
b72f3acb | 861 | static int |
e61e0f51 | 862 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 863 | { |
73dec95e | 864 | u32 *cs; |
b72f3acb | 865 | |
e61e0f51 | 866 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
867 | if (IS_ERR(cs)) |
868 | return PTR_ERR(cs); | |
b72f3acb | 869 | |
73dec95e TU |
870 | *cs++ = MI_FLUSH; |
871 | *cs++ = MI_NOOP; | |
e61e0f51 | 872 | intel_ring_advance(rq, cs); |
b72f3acb | 873 | return 0; |
d1b851fc ZN |
874 | } |
875 | ||
31bb59cc CW |
876 | static void |
877 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 878 | { |
c033666a | 879 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 880 | |
61ff75ac CW |
881 | I915_WRITE_IMR(engine, |
882 | ~(engine->irq_enable_mask | | |
883 | engine->irq_keep_mask)); | |
31bb59cc | 884 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
885 | } |
886 | ||
887 | static void | |
31bb59cc | 888 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 889 | { |
c033666a | 890 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 891 | |
61ff75ac | 892 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 893 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
894 | } |
895 | ||
31bb59cc CW |
896 | static void |
897 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 898 | { |
c033666a | 899 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 900 | |
31bb59cc | 901 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 902 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
903 | } |
904 | ||
905 | static void | |
31bb59cc | 906 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 907 | { |
c033666a | 908 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 909 | |
31bb59cc | 910 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 911 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
912 | } |
913 | ||
d1b851fc | 914 | static int |
e61e0f51 | 915 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
916 | u64 offset, u32 length, |
917 | unsigned int dispatch_flags) | |
d1b851fc | 918 | { |
73dec95e | 919 | u32 *cs; |
78501eac | 920 | |
e61e0f51 | 921 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
922 | if (IS_ERR(cs)) |
923 | return PTR_ERR(cs); | |
e1f99ce6 | 924 | |
73dec95e TU |
925 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
926 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
927 | *cs++ = offset; | |
e61e0f51 | 928 | intel_ring_advance(rq, cs); |
78501eac | 929 | |
d1b851fc ZN |
930 | return 0; |
931 | } | |
932 | ||
b45305fc DV |
933 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
934 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
935 | #define I830_TLB_ENTRIES (2) |
936 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 937 | static int |
e61e0f51 | 938 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
939 | u64 offset, u32 len, |
940 | unsigned int dispatch_flags) | |
62fdfeaf | 941 | { |
e61e0f51 | 942 | u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); |
62fdfeaf | 943 | |
e61e0f51 | 944 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
945 | if (IS_ERR(cs)) |
946 | return PTR_ERR(cs); | |
62fdfeaf | 947 | |
c4d69da1 | 948 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
949 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
950 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
951 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
952 | *cs++ = cs_offset; | |
953 | *cs++ = 0xdeadbeef; | |
954 | *cs++ = MI_NOOP; | |
e61e0f51 | 955 | intel_ring_advance(rq, cs); |
b45305fc | 956 | |
8e004efc | 957 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
958 | if (len > I830_BATCH_LIMIT) |
959 | return -ENOSPC; | |
960 | ||
e61e0f51 | 961 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
962 | if (IS_ERR(cs)) |
963 | return PTR_ERR(cs); | |
c4d69da1 CW |
964 | |
965 | /* Blit the batch (which has now all relocs applied) to the | |
966 | * stable batch scratch bo area (so that the CS never | |
967 | * stumbles over its tlb invalidation bug) ... | |
968 | */ | |
73dec95e TU |
969 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
970 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
971 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
972 | *cs++ = cs_offset; | |
973 | *cs++ = 4096; | |
974 | *cs++ = offset; | |
975 | ||
976 | *cs++ = MI_FLUSH; | |
977 | *cs++ = MI_NOOP; | |
e61e0f51 | 978 | intel_ring_advance(rq, cs); |
b45305fc DV |
979 | |
980 | /* ... and execute it. */ | |
c4d69da1 | 981 | offset = cs_offset; |
b45305fc | 982 | } |
e1f99ce6 | 983 | |
e61e0f51 | 984 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
985 | if (IS_ERR(cs)) |
986 | return PTR_ERR(cs); | |
c4d69da1 | 987 | |
73dec95e TU |
988 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
989 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
990 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 991 | intel_ring_advance(rq, cs); |
c4d69da1 | 992 | |
fb3256da DV |
993 | return 0; |
994 | } | |
995 | ||
996 | static int | |
e61e0f51 | 997 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
998 | u64 offset, u32 len, |
999 | unsigned int dispatch_flags) | |
fb3256da | 1000 | { |
73dec95e | 1001 | u32 *cs; |
fb3256da | 1002 | |
e61e0f51 | 1003 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1004 | if (IS_ERR(cs)) |
1005 | return PTR_ERR(cs); | |
fb3256da | 1006 | |
73dec95e TU |
1007 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1008 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1009 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1010 | intel_ring_advance(rq, cs); |
62fdfeaf | 1011 | |
62fdfeaf EA |
1012 | return 0; |
1013 | } | |
1014 | ||
62fdfeaf | 1015 | |
6b8294a4 | 1016 | |
d822bb18 CW |
1017 | int intel_ring_pin(struct intel_ring *ring, |
1018 | struct drm_i915_private *i915, | |
1019 | unsigned int offset_bias) | |
7ba717cf | 1020 | { |
d822bb18 | 1021 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1022 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1023 | unsigned int flags; |
8305216f | 1024 | void *addr; |
7ba717cf TD |
1025 | int ret; |
1026 | ||
57e88531 | 1027 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1028 | |
9d80841e | 1029 | |
d3ef1af6 DCS |
1030 | flags = PIN_GLOBAL; |
1031 | if (offset_bias) | |
1032 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1033 | if (vma->obj->stolen) |
57e88531 | 1034 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1035 | |
57e88531 | 1036 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1037 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1038 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1039 | else | |
1040 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1041 | if (unlikely(ret)) | |
def0c5f6 | 1042 | return ret; |
57e88531 | 1043 | } |
7ba717cf | 1044 | |
57e88531 CW |
1045 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1046 | if (unlikely(ret)) | |
1047 | return ret; | |
def0c5f6 | 1048 | |
9d80841e | 1049 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1050 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1051 | else | |
9d80841e | 1052 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1053 | if (IS_ERR(addr)) |
1054 | goto err; | |
7ba717cf | 1055 | |
3d574a6b CW |
1056 | vma->obj->pin_global++; |
1057 | ||
32c04f16 | 1058 | ring->vaddr = addr; |
7ba717cf | 1059 | return 0; |
d2cad535 | 1060 | |
57e88531 CW |
1061 | err: |
1062 | i915_vma_unpin(vma); | |
1063 | return PTR_ERR(addr); | |
7ba717cf TD |
1064 | } |
1065 | ||
e6ba9992 CW |
1066 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1067 | { | |
1068 | GEM_BUG_ON(!list_empty(&ring->request_list)); | |
1069 | ring->tail = tail; | |
1070 | ring->head = tail; | |
1071 | ring->emit = tail; | |
1072 | intel_ring_update_space(ring); | |
1073 | } | |
1074 | ||
aad29fbb CW |
1075 | void intel_ring_unpin(struct intel_ring *ring) |
1076 | { | |
1077 | GEM_BUG_ON(!ring->vma); | |
1078 | GEM_BUG_ON(!ring->vaddr); | |
1079 | ||
e6ba9992 CW |
1080 | /* Discard any unused bytes beyond that submitted to hw. */ |
1081 | intel_ring_reset(ring, ring->tail); | |
1082 | ||
9d80841e | 1083 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1084 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1085 | else |
1086 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1087 | ring->vaddr = NULL; |
1088 | ||
3d574a6b | 1089 | ring->vma->obj->pin_global--; |
57e88531 | 1090 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1091 | } |
1092 | ||
57e88531 CW |
1093 | static struct i915_vma * |
1094 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1095 | { |
05394f39 | 1096 | struct drm_i915_gem_object *obj; |
57e88531 | 1097 | struct i915_vma *vma; |
62fdfeaf | 1098 | |
187685cb | 1099 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1100 | if (!obj) |
2d6c4c84 | 1101 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1102 | if (IS_ERR(obj)) |
1103 | return ERR_CAST(obj); | |
8187a2b7 | 1104 | |
24f3a8cf AG |
1105 | /* mark ring buffers as read-only from GPU side by default */ |
1106 | obj->gt_ro = 1; | |
1107 | ||
a01cb37a | 1108 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1109 | if (IS_ERR(vma)) |
1110 | goto err; | |
1111 | ||
1112 | return vma; | |
e3efda49 | 1113 | |
57e88531 CW |
1114 | err: |
1115 | i915_gem_object_put(obj); | |
1116 | return vma; | |
e3efda49 CW |
1117 | } |
1118 | ||
7e37f889 CW |
1119 | struct intel_ring * |
1120 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1121 | { |
7e37f889 | 1122 | struct intel_ring *ring; |
57e88531 | 1123 | struct i915_vma *vma; |
01101fa7 | 1124 | |
8f942018 | 1125 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1126 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1127 | |
01101fa7 | 1128 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1129 | if (!ring) |
01101fa7 CW |
1130 | return ERR_PTR(-ENOMEM); |
1131 | ||
675d9ad7 CW |
1132 | INIT_LIST_HEAD(&ring->request_list); |
1133 | ||
01101fa7 CW |
1134 | ring->size = size; |
1135 | /* Workaround an erratum on the i830 which causes a hang if | |
1136 | * the TAIL pointer points to within the last 2 cachelines | |
1137 | * of the buffer. | |
1138 | */ | |
1139 | ring->effective_size = size; | |
2a307c2e | 1140 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1141 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1142 | ||
01101fa7 CW |
1143 | intel_ring_update_space(ring); |
1144 | ||
57e88531 CW |
1145 | vma = intel_ring_create_vma(engine->i915, size); |
1146 | if (IS_ERR(vma)) { | |
01101fa7 | 1147 | kfree(ring); |
57e88531 | 1148 | return ERR_CAST(vma); |
01101fa7 | 1149 | } |
57e88531 | 1150 | ring->vma = vma; |
01101fa7 CW |
1151 | |
1152 | return ring; | |
1153 | } | |
1154 | ||
1155 | void | |
7e37f889 | 1156 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1157 | { |
f8a7fde4 CW |
1158 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1159 | ||
1160 | i915_vma_close(ring->vma); | |
1161 | __i915_gem_object_release_unless_active(obj); | |
1162 | ||
01101fa7 CW |
1163 | kfree(ring); |
1164 | } | |
1165 | ||
72b72ae4 | 1166 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1167 | { |
1168 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1169 | int ret; | |
1170 | ||
f4e15af7 CW |
1171 | /* |
1172 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1173 | * We only want to do this on the first bind so that we do not stall |
1174 | * on an active context (which by nature is already on the GPU). | |
1175 | */ | |
1176 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
f4e15af7 | 1177 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
e8a9c58f CW |
1178 | if (ret) |
1179 | return ret; | |
1180 | } | |
1181 | ||
afeddf50 CW |
1182 | return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1183 | PIN_GLOBAL | PIN_HIGH); | |
e8a9c58f CW |
1184 | } |
1185 | ||
3204c343 CW |
1186 | static struct i915_vma * |
1187 | alloc_context_vma(struct intel_engine_cs *engine) | |
1188 | { | |
1189 | struct drm_i915_private *i915 = engine->i915; | |
1190 | struct drm_i915_gem_object *obj; | |
1191 | struct i915_vma *vma; | |
d2b4b979 | 1192 | int err; |
3204c343 | 1193 | |
63ffbcda | 1194 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1195 | if (IS_ERR(obj)) |
1196 | return ERR_CAST(obj); | |
1197 | ||
d2b4b979 CW |
1198 | if (engine->default_state) { |
1199 | void *defaults, *vaddr; | |
1200 | ||
1201 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1202 | if (IS_ERR(vaddr)) { | |
1203 | err = PTR_ERR(vaddr); | |
1204 | goto err_obj; | |
1205 | } | |
1206 | ||
1207 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1208 | I915_MAP_WB); | |
1209 | if (IS_ERR(defaults)) { | |
1210 | err = PTR_ERR(defaults); | |
1211 | goto err_map; | |
1212 | } | |
1213 | ||
1214 | memcpy(vaddr, defaults, engine->context_size); | |
1215 | ||
1216 | i915_gem_object_unpin_map(engine->default_state); | |
1217 | i915_gem_object_unpin_map(obj); | |
1218 | } | |
1219 | ||
3204c343 CW |
1220 | /* |
1221 | * Try to make the context utilize L3 as well as LLC. | |
1222 | * | |
1223 | * On VLV we don't have L3 controls in the PTEs so we | |
1224 | * shouldn't touch the cache level, especially as that | |
1225 | * would make the object snooped which might have a | |
1226 | * negative performance impact. | |
1227 | * | |
1228 | * Snooping is required on non-llc platforms in execlist | |
1229 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1230 | * get snooping anyway regardless of cache_level. | |
1231 | * | |
1232 | * This is only applicable for Ivy Bridge devices since | |
1233 | * later platforms don't have L3 control bits in the PTE. | |
1234 | */ | |
1235 | if (IS_IVYBRIDGE(i915)) { | |
1236 | /* Ignore any error, regard it as a simple optimisation */ | |
1237 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1238 | } | |
1239 | ||
1240 | vma = i915_vma_instance(obj, &i915->ggtt.base, NULL); | |
d2b4b979 CW |
1241 | if (IS_ERR(vma)) { |
1242 | err = PTR_ERR(vma); | |
1243 | goto err_obj; | |
1244 | } | |
3204c343 CW |
1245 | |
1246 | return vma; | |
d2b4b979 CW |
1247 | |
1248 | err_map: | |
1249 | i915_gem_object_unpin_map(obj); | |
1250 | err_obj: | |
1251 | i915_gem_object_put(obj); | |
1252 | return ERR_PTR(err); | |
3204c343 CW |
1253 | } |
1254 | ||
266a240b CW |
1255 | static struct intel_ring * |
1256 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1257 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1258 | { |
1259 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1260 | int ret; | |
1261 | ||
91c8a326 | 1262 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1263 | |
266a240b CW |
1264 | if (likely(ce->pin_count++)) |
1265 | goto out; | |
a533b4ba | 1266 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
0cb26a8e | 1267 | |
63ffbcda | 1268 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1269 | struct i915_vma *vma; |
1270 | ||
1271 | vma = alloc_context_vma(engine); | |
1272 | if (IS_ERR(vma)) { | |
1273 | ret = PTR_ERR(vma); | |
266a240b | 1274 | goto err; |
3204c343 CW |
1275 | } |
1276 | ||
1277 | ce->state = vma; | |
1278 | } | |
1279 | ||
0cb26a8e | 1280 | if (ce->state) { |
72b72ae4 | 1281 | ret = context_pin(ctx); |
e8a9c58f | 1282 | if (ret) |
266a240b | 1283 | goto err; |
5d4bac55 | 1284 | |
3d574a6b | 1285 | ce->state->obj->pin_global++; |
0cb26a8e CW |
1286 | } |
1287 | ||
9a6feaf0 | 1288 | i915_gem_context_get(ctx); |
0cb26a8e | 1289 | |
266a240b CW |
1290 | out: |
1291 | /* One ringbuffer to rule them all */ | |
1292 | return engine->buffer; | |
1293 | ||
1294 | err: | |
0cb26a8e | 1295 | ce->pin_count = 0; |
266a240b | 1296 | return ERR_PTR(ret); |
0cb26a8e CW |
1297 | } |
1298 | ||
e8a9c58f CW |
1299 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1300 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1301 | { |
1302 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1303 | ||
91c8a326 | 1304 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1305 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1306 | |
1307 | if (--ce->pin_count) | |
1308 | return; | |
1309 | ||
3d574a6b CW |
1310 | if (ce->state) { |
1311 | ce->state->obj->pin_global--; | |
bf3783e5 | 1312 | i915_vma_unpin(ce->state); |
3d574a6b | 1313 | } |
0cb26a8e | 1314 | |
9a6feaf0 | 1315 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1316 | } |
1317 | ||
acd27845 | 1318 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1319 | { |
32c04f16 | 1320 | struct intel_ring *ring; |
1a5788bf | 1321 | int err; |
bfc882b4 | 1322 | |
019bf277 TU |
1323 | intel_engine_setup_common(engine); |
1324 | ||
1a5788bf CW |
1325 | err = intel_engine_init_common(engine); |
1326 | if (err) | |
1327 | goto err; | |
e3efda49 | 1328 | |
d822bb18 CW |
1329 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1330 | if (IS_ERR(ring)) { | |
1a5788bf | 1331 | err = PTR_ERR(ring); |
486e93f7 | 1332 | goto err; |
d822bb18 CW |
1333 | } |
1334 | ||
d3ef1af6 | 1335 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1336 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1337 | if (err) | |
1338 | goto err_ring; | |
1339 | ||
1340 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1341 | engine->buffer = ring; |
62fdfeaf | 1342 | |
8ee14975 | 1343 | return 0; |
351e3db2 | 1344 | |
1a5788bf CW |
1345 | err_ring: |
1346 | intel_ring_free(ring); | |
1a5788bf CW |
1347 | err: |
1348 | intel_engine_cleanup_common(engine); | |
1349 | return err; | |
62fdfeaf EA |
1350 | } |
1351 | ||
7e37f889 | 1352 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1353 | { |
1a5788bf | 1354 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1355 | |
1a5788bf CW |
1356 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1357 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1358 | |
1a5788bf CW |
1359 | intel_ring_unpin(engine->buffer); |
1360 | intel_ring_free(engine->buffer); | |
78501eac | 1361 | |
0bc40be8 TU |
1362 | if (engine->cleanup) |
1363 | engine->cleanup(engine); | |
8d19215b | 1364 | |
96a945aa | 1365 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1366 | |
3b3f1650 AG |
1367 | dev_priv->engine[engine->id] = NULL; |
1368 | kfree(engine); | |
62fdfeaf EA |
1369 | } |
1370 | ||
821ed7df CW |
1371 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1372 | { | |
1373 | struct intel_engine_cs *engine; | |
3b3f1650 | 1374 | enum intel_engine_id id; |
821ed7df | 1375 | |
e6ba9992 | 1376 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1377 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1378 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1379 | } |
1380 | ||
e61e0f51 | 1381 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1382 | { |
1383 | struct drm_i915_private *i915 = rq->i915; | |
1384 | struct intel_engine_cs *engine = rq->engine; | |
1385 | enum intel_engine_id id; | |
1386 | const int num_rings = | |
1387 | /* Use an extended w/a on gen7 if signalling from other rings */ | |
1388 | (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? | |
1389 | INTEL_INFO(i915)->num_rings - 1 : | |
1390 | 0; | |
1391 | int len; | |
1392 | u32 *cs; | |
1393 | ||
1394 | flags |= MI_MM_SPACE_GTT; | |
1395 | if (IS_HASWELL(i915)) | |
1396 | /* These flags are for resource streamer on HSW+ */ | |
1397 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1398 | else | |
1399 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
1400 | ||
1401 | len = 4; | |
1402 | if (IS_GEN7(i915)) | |
1403 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); | |
1404 | ||
1405 | cs = intel_ring_begin(rq, len); | |
1406 | if (IS_ERR(cs)) | |
1407 | return PTR_ERR(cs); | |
1408 | ||
1409 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
1410 | if (IS_GEN7(i915)) { | |
1411 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; | |
1412 | if (num_rings) { | |
1413 | struct intel_engine_cs *signaller; | |
1414 | ||
1415 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1416 | for_each_engine(signaller, i915, id) { | |
1417 | if (signaller == engine) | |
1418 | continue; | |
1419 | ||
1420 | *cs++ = i915_mmio_reg_offset( | |
1421 | RING_PSMI_CTL(signaller->mmio_base)); | |
1422 | *cs++ = _MASKED_BIT_ENABLE( | |
1423 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1424 | } | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | *cs++ = MI_NOOP; | |
1429 | *cs++ = MI_SET_CONTEXT; | |
1430 | *cs++ = i915_ggtt_offset(rq->ctx->engine[RCS].state) | flags; | |
1431 | /* | |
1432 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1433 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1434 | */ | |
1435 | *cs++ = MI_NOOP; | |
1436 | ||
1437 | if (IS_GEN7(i915)) { | |
1438 | if (num_rings) { | |
1439 | struct intel_engine_cs *signaller; | |
1440 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1441 | ||
1442 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1443 | for_each_engine(signaller, i915, id) { | |
1444 | if (signaller == engine) | |
1445 | continue; | |
1446 | ||
1447 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1448 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1449 | *cs++ = _MASKED_BIT_DISABLE( | |
1450 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1451 | } | |
1452 | ||
1453 | /* Insert a delay before the next switch! */ | |
1454 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1455 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1456 | *cs++ = i915_ggtt_offset(engine->scratch); | |
1457 | *cs++ = MI_NOOP; | |
1458 | } | |
1459 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1460 | } | |
1461 | ||
1462 | intel_ring_advance(rq, cs); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
e61e0f51 | 1467 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1468 | { |
1469 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1470 | int i; | |
1471 | ||
1472 | if (!remap_info) | |
1473 | return 0; | |
1474 | ||
1475 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1476 | if (IS_ERR(cs)) | |
1477 | return PTR_ERR(cs); | |
1478 | ||
1479 | /* | |
1480 | * Note: We do not worry about the concurrent register cacheline hang | |
1481 | * here because no other code should access these registers other than | |
1482 | * at initialization time. | |
1483 | */ | |
1484 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1485 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1486 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1487 | *cs++ = remap_info[i]; | |
1488 | } | |
1489 | *cs++ = MI_NOOP; | |
1490 | intel_ring_advance(rq, cs); | |
1491 | ||
1492 | return 0; | |
1493 | } | |
1494 | ||
e61e0f51 | 1495 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1496 | { |
1497 | struct intel_engine_cs *engine = rq->engine; | |
1498 | struct i915_gem_context *to_ctx = rq->ctx; | |
1499 | struct i915_hw_ppgtt *to_mm = | |
1500 | to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
1501 | struct i915_gem_context *from_ctx = engine->legacy_active_context; | |
1502 | struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt; | |
1503 | u32 hw_flags = 0; | |
1504 | int ret, i; | |
1505 | ||
1506 | lockdep_assert_held(&rq->i915->drm.struct_mutex); | |
1507 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); | |
1508 | ||
1509 | if (to_mm != from_mm || | |
1510 | (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) { | |
1511 | trace_switch_mm(engine, to_ctx); | |
1512 | ret = to_mm->switch_mm(to_mm, rq); | |
1513 | if (ret) | |
1514 | goto err; | |
1515 | ||
1516 | to_mm->pd_dirty_rings &= ~intel_engine_flag(engine); | |
1517 | engine->legacy_active_ppgtt = to_mm; | |
1518 | hw_flags = MI_FORCE_RESTORE; | |
1519 | } | |
1520 | ||
1521 | if (to_ctx->engine[engine->id].state && | |
1522 | (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) { | |
1523 | GEM_BUG_ON(engine->id != RCS); | |
1524 | ||
1525 | /* | |
1526 | * The kernel context(s) is treated as pure scratch and is not | |
1527 | * expected to retain any state (as we sacrifice it during | |
1528 | * suspend and on resume it may be corrupted). This is ok, | |
1529 | * as nothing actually executes using the kernel context; it | |
1530 | * is purely used for flushing user contexts. | |
1531 | */ | |
1532 | if (i915_gem_context_is_kernel(to_ctx)) | |
1533 | hw_flags = MI_RESTORE_INHIBIT; | |
1534 | ||
1535 | ret = mi_set_context(rq, hw_flags); | |
1536 | if (ret) | |
1537 | goto err_mm; | |
1538 | ||
1539 | engine->legacy_active_context = to_ctx; | |
1540 | } | |
1541 | ||
1542 | if (to_ctx->remap_slice) { | |
1543 | for (i = 0; i < MAX_L3_SLICES; i++) { | |
1544 | if (!(to_ctx->remap_slice & BIT(i))) | |
1545 | continue; | |
1546 | ||
1547 | ret = remap_l3(rq, i); | |
1548 | if (ret) | |
1549 | goto err_ctx; | |
1550 | } | |
1551 | ||
1552 | to_ctx->remap_slice = 0; | |
1553 | } | |
1554 | ||
1555 | return 0; | |
1556 | ||
1557 | err_ctx: | |
1558 | engine->legacy_active_context = from_ctx; | |
1559 | err_mm: | |
1560 | engine->legacy_active_ppgtt = from_mm; | |
1561 | err: | |
1562 | return ret; | |
1563 | } | |
1564 | ||
e61e0f51 | 1565 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1566 | { |
fd138212 | 1567 | int ret; |
6310346e | 1568 | |
e8a9c58f CW |
1569 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1570 | ||
6310346e CW |
1571 | /* Flush enough space to reduce the likelihood of waiting after |
1572 | * we start building the request - in which case we will just | |
1573 | * have to repeat work. | |
1574 | */ | |
a0442461 | 1575 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1576 | |
fd138212 CW |
1577 | ret = intel_ring_wait_for_space(request->ring, request->reserved_space); |
1578 | if (ret) | |
1579 | return ret; | |
6310346e | 1580 | |
8911a31c | 1581 | ret = switch_context(request); |
3fef5cda CW |
1582 | if (ret) |
1583 | return ret; | |
1584 | ||
a0442461 | 1585 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1586 | return 0; |
9d773091 CW |
1587 | } |
1588 | ||
fd138212 | 1589 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1590 | { |
e61e0f51 | 1591 | struct i915_request *target; |
e95433c7 CW |
1592 | long timeout; |
1593 | ||
fd138212 | 1594 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1595 | |
95aebcb2 | 1596 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1597 | return 0; |
1598 | ||
36620032 | 1599 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1600 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1601 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1602 | if (bytes <= __intel_ring_space(target->postfix, |
1603 | ring->emit, ring->size)) | |
987046ad | 1604 | break; |
79bbcc29 | 1605 | } |
29b1b415 | 1606 | |
675d9ad7 | 1607 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1608 | return -ENOSPC; |
1609 | ||
e61e0f51 | 1610 | timeout = i915_request_wait(target, |
e95433c7 CW |
1611 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
1612 | MAX_SCHEDULE_TIMEOUT); | |
1613 | if (timeout < 0) | |
1614 | return timeout; | |
7da844c5 | 1615 | |
e61e0f51 | 1616 | i915_request_retire_upto(target); |
7da844c5 CW |
1617 | |
1618 | intel_ring_update_space(ring); | |
1619 | GEM_BUG_ON(ring->space < bytes); | |
1620 | return 0; | |
29b1b415 JH |
1621 | } |
1622 | ||
fd138212 CW |
1623 | int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes) |
1624 | { | |
1625 | GEM_BUG_ON(bytes > ring->effective_size); | |
1626 | if (unlikely(bytes > ring->effective_size - ring->emit)) | |
1627 | bytes += ring->size - ring->emit; | |
1628 | ||
1629 | if (unlikely(bytes > ring->space)) { | |
1630 | int ret = wait_for_space(ring, bytes); | |
1631 | if (unlikely(ret)) | |
1632 | return ret; | |
1633 | } | |
1634 | ||
1635 | GEM_BUG_ON(ring->space < bytes); | |
1636 | return 0; | |
1637 | } | |
1638 | ||
e61e0f51 | 1639 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1640 | { |
e61e0f51 | 1641 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1642 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1643 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1644 | unsigned int need_wrap = 0; | |
1645 | unsigned int total_bytes; | |
73dec95e | 1646 | u32 *cs; |
29b1b415 | 1647 | |
6492ca79 CW |
1648 | /* Packets must be qword aligned. */ |
1649 | GEM_BUG_ON(num_dwords & 1); | |
1650 | ||
e61e0f51 | 1651 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1652 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1653 | |
5e5655c3 CW |
1654 | if (unlikely(total_bytes > remain_usable)) { |
1655 | const int remain_actual = ring->size - ring->emit; | |
1656 | ||
1657 | if (bytes > remain_usable) { | |
1658 | /* | |
1659 | * Not enough space for the basic request. So need to | |
1660 | * flush out the remainder and then wait for | |
1661 | * base + reserved. | |
1662 | */ | |
1663 | total_bytes += remain_actual; | |
1664 | need_wrap = remain_actual | 1; | |
1665 | } else { | |
1666 | /* | |
1667 | * The base request will fit but the reserved space | |
1668 | * falls off the end. So we don't need an immediate | |
1669 | * wrap and only need to effectively wait for the | |
1670 | * reserved size from the start of ringbuffer. | |
1671 | */ | |
e61e0f51 | 1672 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 1673 | } |
cbcc80df MK |
1674 | } |
1675 | ||
5e5655c3 | 1676 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1677 | int ret; |
1678 | ||
1679 | /* | |
1680 | * Space is reserved in the ringbuffer for finalising the | |
1681 | * request, as that cannot be allowed to fail. During request | |
1682 | * finalisation, reserved_space is set to 0 to stop the | |
1683 | * overallocation and the assumption is that then we never need | |
1684 | * to wait (which has the risk of failing with EINTR). | |
1685 | * | |
e61e0f51 | 1686 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 1687 | */ |
e61e0f51 | 1688 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
1689 | |
1690 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 1691 | if (unlikely(ret)) |
73dec95e | 1692 | return ERR_PTR(ret); |
cbcc80df MK |
1693 | } |
1694 | ||
987046ad | 1695 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1696 | need_wrap &= ~1; |
1697 | GEM_BUG_ON(need_wrap > ring->space); | |
1698 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 1699 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 1700 | |
987046ad | 1701 | /* Fill the tail with MI_NOOP */ |
46b86332 | 1702 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 1703 | ring->space -= need_wrap; |
46b86332 | 1704 | ring->emit = 0; |
987046ad | 1705 | } |
304d695c | 1706 | |
e6ba9992 | 1707 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1708 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1709 | cs = ring->vaddr + ring->emit; |
46b86332 | 1710 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 1711 | ring->emit += bytes; |
1dae2dfb | 1712 | ring->space -= bytes; |
73dec95e TU |
1713 | |
1714 | return cs; | |
8187a2b7 | 1715 | } |
78501eac | 1716 | |
753b1ad4 | 1717 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 1718 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 1719 | { |
e61e0f51 | 1720 | int num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
73dec95e | 1721 | u32 *cs; |
753b1ad4 VS |
1722 | |
1723 | if (num_dwords == 0) | |
1724 | return 0; | |
1725 | ||
e61e0f51 CW |
1726 | num_dwords = CACHELINE_BYTES / sizeof(u32) - num_dwords; |
1727 | cs = intel_ring_begin(rq, num_dwords); | |
73dec95e TU |
1728 | if (IS_ERR(cs)) |
1729 | return PTR_ERR(cs); | |
753b1ad4 VS |
1730 | |
1731 | while (num_dwords--) | |
73dec95e | 1732 | *cs++ = MI_NOOP; |
753b1ad4 | 1733 | |
e61e0f51 | 1734 | intel_ring_advance(rq, cs); |
753b1ad4 VS |
1735 | |
1736 | return 0; | |
1737 | } | |
1738 | ||
e61e0f51 | 1739 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 1740 | { |
c5efa1ad | 1741 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1742 | |
76f8421f CW |
1743 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1744 | ||
881f47b6 | 1745 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1746 | |
1747 | /* Disable notification that the ring is IDLE. The GT | |
1748 | * will then assume that it is busy and bring it out of rc6. | |
1749 | */ | |
76f8421f CW |
1750 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1751 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1752 | |
1753 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1754 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1755 | |
12f55818 | 1756 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1757 | if (__intel_wait_for_register_fw(dev_priv, |
1758 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1759 | GEN6_BSD_SLEEP_INDICATOR, | |
1760 | 0, | |
1761 | 1000, 0, NULL)) | |
12f55818 | 1762 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1763 | |
12f55818 | 1764 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1765 | i9xx_submit_request(request); |
12f55818 CW |
1766 | |
1767 | /* Let the ring send IDLE messages to the GT again, | |
1768 | * and so let it sleep to conserve power when idle. | |
1769 | */ | |
76f8421f CW |
1770 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1771 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1772 | ||
1773 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1774 | } |
1775 | ||
e61e0f51 | 1776 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) |
881f47b6 | 1777 | { |
73dec95e | 1778 | u32 cmd, *cs; |
b72f3acb | 1779 | |
e61e0f51 | 1780 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
1781 | if (IS_ERR(cs)) |
1782 | return PTR_ERR(cs); | |
b72f3acb | 1783 | |
71a77e07 | 1784 | cmd = MI_FLUSH_DW; |
f0a1fb10 CW |
1785 | |
1786 | /* We always require a command barrier so that subsequent | |
1787 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1788 | * wrt the contents of the write cache being flushed to memory | |
1789 | * (and thus being coherent from the CPU). | |
1790 | */ | |
1791 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1792 | ||
9a289771 JB |
1793 | /* |
1794 | * Bspec vol 1c.5 - video engine command streamer: | |
1795 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1796 | * operation is complete. This bit is only valid when the | |
1797 | * Post-Sync Operation field is a value of 1h or 3h." | |
1798 | */ | |
7c9cf4e3 | 1799 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1800 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1801 | ||
73dec95e TU |
1802 | *cs++ = cmd; |
1803 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 1804 | *cs++ = 0; |
73dec95e | 1805 | *cs++ = MI_NOOP; |
e61e0f51 | 1806 | intel_ring_advance(rq, cs); |
1c7a0623 BW |
1807 | return 0; |
1808 | } | |
1809 | ||
d7d4eedd | 1810 | static int |
e61e0f51 | 1811 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1812 | u64 offset, u32 len, |
1813 | unsigned int dispatch_flags) | |
d7d4eedd | 1814 | { |
73dec95e | 1815 | u32 *cs; |
d7d4eedd | 1816 | |
e61e0f51 | 1817 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1818 | if (IS_ERR(cs)) |
1819 | return PTR_ERR(cs); | |
d7d4eedd | 1820 | |
73dec95e TU |
1821 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1822 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1823 | (dispatch_flags & I915_DISPATCH_RS ? | |
1824 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1825 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 1826 | *cs++ = offset; |
e61e0f51 | 1827 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
1828 | |
1829 | return 0; | |
1830 | } | |
1831 | ||
881f47b6 | 1832 | static int |
e61e0f51 | 1833 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1834 | u64 offset, u32 len, |
1835 | unsigned int dispatch_flags) | |
881f47b6 | 1836 | { |
73dec95e | 1837 | u32 *cs; |
ab6f8e32 | 1838 | |
e61e0f51 | 1839 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1840 | if (IS_ERR(cs)) |
1841 | return PTR_ERR(cs); | |
e1f99ce6 | 1842 | |
73dec95e TU |
1843 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1844 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1845 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 1846 | *cs++ = offset; |
e61e0f51 | 1847 | intel_ring_advance(rq, cs); |
ab6f8e32 | 1848 | |
0206e353 | 1849 | return 0; |
881f47b6 XH |
1850 | } |
1851 | ||
549f7365 CW |
1852 | /* Blitter support (SandyBridge+) */ |
1853 | ||
e61e0f51 | 1854 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 1855 | { |
73dec95e | 1856 | u32 cmd, *cs; |
b72f3acb | 1857 | |
e61e0f51 | 1858 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
1859 | if (IS_ERR(cs)) |
1860 | return PTR_ERR(cs); | |
b72f3acb | 1861 | |
71a77e07 | 1862 | cmd = MI_FLUSH_DW; |
f0a1fb10 CW |
1863 | |
1864 | /* We always require a command barrier so that subsequent | |
1865 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1866 | * wrt the contents of the write cache being flushed to memory | |
1867 | * (and thus being coherent from the CPU). | |
1868 | */ | |
1869 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1870 | ||
9a289771 JB |
1871 | /* |
1872 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1873 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1874 | * operation is complete. This bit is only valid when the | |
1875 | * Post-Sync Operation field is a value of 1h or 3h." | |
1876 | */ | |
7c9cf4e3 | 1877 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1878 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1879 | *cs++ = cmd; |
1880 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c CW |
1881 | *cs++ = 0; |
1882 | *cs++ = MI_NOOP; | |
e61e0f51 | 1883 | intel_ring_advance(rq, cs); |
fd3da6c9 | 1884 | |
b72f3acb | 1885 | return 0; |
8d19215b ZN |
1886 | } |
1887 | ||
d9a64610 TU |
1888 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1889 | struct intel_engine_cs *engine) | |
1890 | { | |
79e6770c | 1891 | int i; |
db3d4019 | 1892 | |
93c6e966 | 1893 | if (!HAS_LEGACY_SEMAPHORES(dev_priv)) |
db3d4019 TU |
1894 | return; |
1895 | ||
79e6770c CW |
1896 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); |
1897 | engine->semaphore.sync_to = gen6_ring_sync_to; | |
1898 | engine->semaphore.signal = gen6_signal; | |
51d545d0 | 1899 | |
79e6770c CW |
1900 | /* |
1901 | * The current semaphore is only applied on pre-gen8 | |
1902 | * platform. And there is no VCS2 ring on the pre-gen8 | |
1903 | * platform. So the semaphore between RCS and VCS2 is | |
1904 | * initialized as INVALID. | |
1905 | */ | |
1906 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { | |
1907 | static const struct { | |
4b8e38a9 TU |
1908 | u32 wait_mbox; |
1909 | i915_reg_t mbox_reg; | |
79e6770c CW |
1910 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
1911 | [RCS_HW] = { | |
1912 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
1913 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
1914 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
1915 | }, | |
1916 | [VCS_HW] = { | |
1917 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
1918 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
1919 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
1920 | }, | |
1921 | [BCS_HW] = { | |
1922 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
1923 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
1924 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
1925 | }, | |
1926 | [VECS_HW] = { | |
1927 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
1928 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
1929 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
1930 | }, | |
1931 | }; | |
1932 | u32 wait_mbox; | |
1933 | i915_reg_t mbox_reg; | |
4b8e38a9 | 1934 | |
79e6770c CW |
1935 | if (i == engine->hw_id) { |
1936 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
1937 | mbox_reg = GEN6_NOSYNC; | |
1938 | } else { | |
1939 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; | |
1940 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 | 1941 | } |
51d545d0 | 1942 | |
79e6770c CW |
1943 | engine->semaphore.mbox.wait[i] = wait_mbox; |
1944 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
1945 | } | |
d9a64610 TU |
1946 | } |
1947 | ||
ed003078 CW |
1948 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
1949 | struct intel_engine_cs *engine) | |
1950 | { | |
79e6770c | 1951 | if (INTEL_GEN(dev_priv) >= 6) { |
31bb59cc CW |
1952 | engine->irq_enable = gen6_irq_enable; |
1953 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
1954 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
1955 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
1956 | engine->irq_enable = gen5_irq_enable; |
1957 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 1958 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 1959 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
1960 | engine->irq_enable = i9xx_irq_enable; |
1961 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 1962 | } else { |
31bb59cc CW |
1963 | engine->irq_enable = i8xx_irq_enable; |
1964 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
1965 | } |
1966 | } | |
1967 | ||
ff44ad51 CW |
1968 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
1969 | { | |
1970 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 1971 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
1972 | |
1973 | engine->park = NULL; | |
1974 | engine->unpark = NULL; | |
ff44ad51 CW |
1975 | } |
1976 | ||
1977 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
1978 | { | |
aba5e278 | 1979 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
1980 | engine->submit_request = gen6_bsd_submit_request; |
1981 | } | |
1982 | ||
06a2fe22 TU |
1983 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
1984 | struct intel_engine_cs *engine) | |
1985 | { | |
79e6770c CW |
1986 | /* gen8+ are only supported with execlists */ |
1987 | GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); | |
1988 | ||
618e4ca7 CW |
1989 | intel_ring_init_irq(dev_priv, engine); |
1990 | intel_ring_init_semaphores(dev_priv, engine); | |
1991 | ||
1d8a1337 | 1992 | engine->init_hw = init_ring_common; |
821ed7df | 1993 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 1994 | |
e8a9c58f CW |
1995 | engine->context_pin = intel_ring_context_pin; |
1996 | engine->context_unpin = intel_ring_context_unpin; | |
1997 | ||
f73e7399 CW |
1998 | engine->request_alloc = ring_request_alloc; |
1999 | ||
9b81d556 | 2000 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d | 2001 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
93c6e966 | 2002 | if (HAS_LEGACY_SEMAPHORES(dev_priv)) { |
98f29e8d CW |
2003 | int num_rings; |
2004 | ||
9b81d556 | 2005 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d | 2006 | |
c58949f4 | 2007 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
79e6770c CW |
2008 | engine->emit_breadcrumb_sz += num_rings * 3; |
2009 | if (num_rings & 1) | |
2010 | engine->emit_breadcrumb_sz++; | |
98f29e8d | 2011 | } |
ff44ad51 CW |
2012 | |
2013 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2014 | |
79e6770c | 2015 | if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2016 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2017 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2018 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2019 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2020 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2021 | else |
803688ba | 2022 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2023 | } |
2024 | ||
8b3e2d36 | 2025 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2026 | { |
8b3e2d36 | 2027 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2028 | int ret; |
5c1143bb | 2029 | |
06a2fe22 TU |
2030 | intel_ring_default_vfuncs(dev_priv, engine); |
2031 | ||
61ff75ac CW |
2032 | if (HAS_L3_DPF(dev_priv)) |
2033 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2034 | |
fa6f071d DCS |
2035 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2036 | ||
79e6770c | 2037 | if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2038 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2039 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2040 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2041 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2042 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2043 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2044 | } else { |
c033666a | 2045 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2046 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2047 | else |
c7fe7d25 | 2048 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2049 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2050 | } |
707d9cf9 | 2051 | |
c033666a | 2052 | if (IS_HASWELL(dev_priv)) |
803688ba | 2053 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2054 | |
e2f80391 | 2055 | engine->init_hw = init_render_ring; |
59465b5f | 2056 | |
acd27845 | 2057 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2058 | if (ret) |
2059 | return ret; | |
2060 | ||
f8973c21 | 2061 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2062 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2063 | if (ret) |
2064 | return ret; | |
2065 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2066 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2067 | if (ret) |
2068 | return ret; | |
2069 | } | |
2070 | ||
2071 | return 0; | |
5c1143bb XH |
2072 | } |
2073 | ||
8b3e2d36 | 2074 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2075 | { |
8b3e2d36 | 2076 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2077 | |
06a2fe22 TU |
2078 | intel_ring_default_vfuncs(dev_priv, engine); |
2079 | ||
c033666a | 2080 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2081 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2082 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2083 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2084 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2085 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2086 | } else { |
c7fe7d25 | 2087 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2088 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2089 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2090 | else |
e2f80391 | 2091 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2092 | } |
58fa3835 | 2093 | |
acd27845 | 2094 | return intel_init_ring_buffer(engine); |
5c1143bb | 2095 | } |
549f7365 | 2096 | |
8b3e2d36 | 2097 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2098 | { |
8b3e2d36 | 2099 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2100 | |
2101 | intel_ring_default_vfuncs(dev_priv, engine); | |
2102 | ||
c7fe7d25 | 2103 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2104 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2105 | |
acd27845 | 2106 | return intel_init_ring_buffer(engine); |
549f7365 | 2107 | } |
a7b9761d | 2108 | |
8b3e2d36 | 2109 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2110 | { |
8b3e2d36 | 2111 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2112 | |
2113 | intel_ring_default_vfuncs(dev_priv, engine); | |
2114 | ||
c7fe7d25 | 2115 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2116 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2117 | engine->irq_enable = hsw_vebox_irq_enable; | |
2118 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2119 | |
acd27845 | 2120 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2121 | } |