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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
18393f63 CW |
36 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
37 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
38 | * to give some inclination as to some of the magic values used in the various | |
39 | * workarounds! | |
40 | */ | |
41 | #define CACHELINE_BYTES 64 | |
42 | ||
c7dca47b CW |
43 | static inline int ring_space(struct intel_ring_buffer *ring) |
44 | { | |
633cf8f5 | 45 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
46 | if (space < 0) |
47 | space += ring->size; | |
48 | return space; | |
49 | } | |
50 | ||
88b4aa87 | 51 | static bool intel_ring_stopped(struct intel_ring_buffer *ring) |
09246732 CW |
52 | { |
53 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
54 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
55 | } | |
09246732 | 56 | |
88b4aa87 MK |
57 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
58 | { | |
09246732 | 59 | ring->tail &= ring->size - 1; |
88b4aa87 | 60 | if (intel_ring_stopped(ring)) |
09246732 CW |
61 | return; |
62 | ring->write_tail(ring, ring->tail); | |
63 | } | |
64 | ||
b72f3acb | 65 | static int |
46f0f8d1 CW |
66 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
67 | u32 invalidate_domains, | |
68 | u32 flush_domains) | |
69 | { | |
70 | u32 cmd; | |
71 | int ret; | |
72 | ||
73 | cmd = MI_FLUSH; | |
31b14c9f | 74 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
75 | cmd |= MI_NO_WRITE_FLUSH; |
76 | ||
77 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
78 | cmd |= MI_READ_FLUSH; | |
79 | ||
80 | ret = intel_ring_begin(ring, 2); | |
81 | if (ret) | |
82 | return ret; | |
83 | ||
84 | intel_ring_emit(ring, cmd); | |
85 | intel_ring_emit(ring, MI_NOOP); | |
86 | intel_ring_advance(ring); | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | static int | |
92 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
93 | u32 invalidate_domains, | |
94 | u32 flush_domains) | |
62fdfeaf | 95 | { |
78501eac | 96 | struct drm_device *dev = ring->dev; |
6f392d54 | 97 | u32 cmd; |
b72f3acb | 98 | int ret; |
6f392d54 | 99 | |
36d527de CW |
100 | /* |
101 | * read/write caches: | |
102 | * | |
103 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
104 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
105 | * also flushed at 2d versus 3d pipeline switches. | |
106 | * | |
107 | * read-only caches: | |
108 | * | |
109 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
110 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
111 | * | |
112 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
113 | * | |
114 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
115 | * invalidated when MI_EXE_FLUSH is set. | |
116 | * | |
117 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
118 | * invalidated with every MI_FLUSH. | |
119 | * | |
120 | * TLBs: | |
121 | * | |
122 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
123 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
124 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
125 | * are flushed at any MI_FLUSH. | |
126 | */ | |
127 | ||
128 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 129 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 130 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
131 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
132 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 133 | |
36d527de CW |
134 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
135 | (IS_G4X(dev) || IS_GEN5(dev))) | |
136 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 137 | |
36d527de CW |
138 | ret = intel_ring_begin(ring, 2); |
139 | if (ret) | |
140 | return ret; | |
b72f3acb | 141 | |
36d527de CW |
142 | intel_ring_emit(ring, cmd); |
143 | intel_ring_emit(ring, MI_NOOP); | |
144 | intel_ring_advance(ring); | |
b72f3acb CW |
145 | |
146 | return 0; | |
8187a2b7 ZN |
147 | } |
148 | ||
8d315287 JB |
149 | /** |
150 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
151 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
152 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
153 | * | |
154 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
155 | * produced by non-pipelined state commands), software needs to first | |
156 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
157 | * 0. | |
158 | * | |
159 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
160 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
161 | * | |
162 | * And the workaround for these two requires this workaround first: | |
163 | * | |
164 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
165 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
166 | * flushes. | |
167 | * | |
168 | * And this last workaround is tricky because of the requirements on | |
169 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
170 | * volume 2 part 1: | |
171 | * | |
172 | * "1 of the following must also be set: | |
173 | * - Render Target Cache Flush Enable ([12] of DW1) | |
174 | * - Depth Cache Flush Enable ([0] of DW1) | |
175 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
176 | * - Depth Stall ([13] of DW1) | |
177 | * - Post-Sync Operation ([13] of DW1) | |
178 | * - Notify Enable ([8] of DW1)" | |
179 | * | |
180 | * The cache flushes require the workaround flush that triggered this | |
181 | * one, so we can't use it. Depth stall would trigger the same. | |
182 | * Post-sync nonzero is what triggered this second workaround, so we | |
183 | * can't use that one either. Notify enable is IRQs, which aren't | |
184 | * really our business. That leaves only stall at scoreboard. | |
185 | */ | |
186 | static int | |
187 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
188 | { | |
18393f63 | 189 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
190 | int ret; |
191 | ||
192 | ||
193 | ret = intel_ring_begin(ring, 6); | |
194 | if (ret) | |
195 | return ret; | |
196 | ||
197 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
198 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
199 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
200 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
201 | intel_ring_emit(ring, 0); /* low dword */ | |
202 | intel_ring_emit(ring, 0); /* high dword */ | |
203 | intel_ring_emit(ring, MI_NOOP); | |
204 | intel_ring_advance(ring); | |
205 | ||
206 | ret = intel_ring_begin(ring, 6); | |
207 | if (ret) | |
208 | return ret; | |
209 | ||
210 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
211 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
212 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
213 | intel_ring_emit(ring, 0); | |
214 | intel_ring_emit(ring, 0); | |
215 | intel_ring_emit(ring, MI_NOOP); | |
216 | intel_ring_advance(ring); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | static int | |
222 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
223 | u32 invalidate_domains, u32 flush_domains) | |
224 | { | |
225 | u32 flags = 0; | |
18393f63 | 226 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
227 | int ret; |
228 | ||
b3111509 PZ |
229 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
230 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
231 | if (ret) | |
232 | return ret; | |
233 | ||
8d315287 JB |
234 | /* Just flush everything. Experiments have shown that reducing the |
235 | * number of bits based on the write domains has little performance | |
236 | * impact. | |
237 | */ | |
7d54a904 CW |
238 | if (flush_domains) { |
239 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
240 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
241 | /* | |
242 | * Ensure that any following seqno writes only happen | |
243 | * when the render cache is indeed flushed. | |
244 | */ | |
97f209bc | 245 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
246 | } |
247 | if (invalidate_domains) { | |
248 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
249 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
250 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
251 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
252 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
253 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
254 | /* | |
255 | * TLB invalidate requires a post-sync write. | |
256 | */ | |
3ac78313 | 257 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 258 | } |
8d315287 | 259 | |
6c6cf5aa | 260 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
261 | if (ret) |
262 | return ret; | |
263 | ||
6c6cf5aa | 264 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
265 | intel_ring_emit(ring, flags); |
266 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 267 | intel_ring_emit(ring, 0); |
8d315287 JB |
268 | intel_ring_advance(ring); |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
f3987631 PZ |
273 | static int |
274 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
275 | { | |
276 | int ret; | |
277 | ||
278 | ret = intel_ring_begin(ring, 4); | |
279 | if (ret) | |
280 | return ret; | |
281 | ||
282 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
283 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
284 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
285 | intel_ring_emit(ring, 0); | |
286 | intel_ring_emit(ring, 0); | |
287 | intel_ring_advance(ring); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
fd3da6c9 RV |
292 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
293 | { | |
294 | int ret; | |
295 | ||
296 | if (!ring->fbc_dirty) | |
297 | return 0; | |
298 | ||
37c1d94f | 299 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
300 | if (ret) |
301 | return ret; | |
fd3da6c9 RV |
302 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
303 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
304 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
305 | intel_ring_emit(ring, value); | |
37c1d94f VS |
306 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
307 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
308 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
309 | intel_ring_advance(ring); |
310 | ||
311 | ring->fbc_dirty = false; | |
312 | return 0; | |
313 | } | |
314 | ||
4772eaeb PZ |
315 | static int |
316 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
317 | u32 invalidate_domains, u32 flush_domains) | |
318 | { | |
319 | u32 flags = 0; | |
18393f63 | 320 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
321 | int ret; |
322 | ||
f3987631 PZ |
323 | /* |
324 | * Ensure that any following seqno writes only happen when the render | |
325 | * cache is indeed flushed. | |
326 | * | |
327 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
328 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
329 | * don't try to be clever and just set it unconditionally. | |
330 | */ | |
331 | flags |= PIPE_CONTROL_CS_STALL; | |
332 | ||
4772eaeb PZ |
333 | /* Just flush everything. Experiments have shown that reducing the |
334 | * number of bits based on the write domains has little performance | |
335 | * impact. | |
336 | */ | |
337 | if (flush_domains) { | |
338 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
339 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
340 | } |
341 | if (invalidate_domains) { | |
342 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
343 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
344 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
345 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
346 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
347 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
348 | /* | |
349 | * TLB invalidate requires a post-sync write. | |
350 | */ | |
351 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 352 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
353 | |
354 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
355 | * set before a pipe_control command that has the state cache | |
356 | * invalidate bit set. */ | |
357 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
358 | } |
359 | ||
360 | ret = intel_ring_begin(ring, 4); | |
361 | if (ret) | |
362 | return ret; | |
363 | ||
364 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
365 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 366 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
367 | intel_ring_emit(ring, 0); |
368 | intel_ring_advance(ring); | |
369 | ||
9688ecad | 370 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
371 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
372 | ||
4772eaeb PZ |
373 | return 0; |
374 | } | |
375 | ||
a5f3d68e BW |
376 | static int |
377 | gen8_render_ring_flush(struct intel_ring_buffer *ring, | |
378 | u32 invalidate_domains, u32 flush_domains) | |
379 | { | |
380 | u32 flags = 0; | |
18393f63 | 381 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
a5f3d68e BW |
382 | int ret; |
383 | ||
384 | flags |= PIPE_CONTROL_CS_STALL; | |
385 | ||
386 | if (flush_domains) { | |
387 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
388 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
389 | } | |
390 | if (invalidate_domains) { | |
391 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
392 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
393 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
394 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
395 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
396 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
397 | flags |= PIPE_CONTROL_QW_WRITE; | |
398 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
399 | } | |
400 | ||
401 | ret = intel_ring_begin(ring, 6); | |
402 | if (ret) | |
403 | return ret; | |
404 | ||
405 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
406 | intel_ring_emit(ring, flags); | |
407 | intel_ring_emit(ring, scratch_addr); | |
408 | intel_ring_emit(ring, 0); | |
409 | intel_ring_emit(ring, 0); | |
410 | intel_ring_emit(ring, 0); | |
411 | intel_ring_advance(ring); | |
412 | ||
413 | return 0; | |
414 | ||
415 | } | |
416 | ||
78501eac | 417 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 418 | u32 value) |
d46eefa2 | 419 | { |
4640c4ff | 420 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 421 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
422 | } |
423 | ||
50877445 | 424 | u64 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 425 | { |
4640c4ff | 426 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 427 | u64 acthd; |
8187a2b7 | 428 | |
50877445 CW |
429 | if (INTEL_INFO(ring->dev)->gen >= 8) |
430 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
431 | RING_ACTHD_UDW(ring->mmio_base)); | |
432 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
433 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
434 | else | |
435 | acthd = I915_READ(ACTHD); | |
436 | ||
437 | return acthd; | |
8187a2b7 ZN |
438 | } |
439 | ||
035dc1e0 DV |
440 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
441 | { | |
442 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
443 | u32 addr; | |
444 | ||
445 | addr = dev_priv->status_page_dmah->busaddr; | |
446 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
447 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
448 | I915_WRITE(HWS_PGA, addr); | |
449 | } | |
450 | ||
9991ae78 | 451 | static bool stop_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 452 | { |
9991ae78 | 453 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 454 | |
9991ae78 CW |
455 | if (!IS_GEN2(ring->dev)) { |
456 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
457 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
458 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
459 | return false; | |
460 | } | |
461 | } | |
b7884eb4 | 462 | |
7f2ab699 | 463 | I915_WRITE_CTL(ring, 0); |
570ef608 | 464 | I915_WRITE_HEAD(ring, 0); |
78501eac | 465 | ring->write_tail(ring, 0); |
8187a2b7 | 466 | |
9991ae78 CW |
467 | if (!IS_GEN2(ring->dev)) { |
468 | (void)I915_READ_CTL(ring); | |
469 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
470 | } | |
a51435a3 | 471 | |
9991ae78 CW |
472 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
473 | } | |
8187a2b7 | 474 | |
9991ae78 CW |
475 | static int init_ring_common(struct intel_ring_buffer *ring) |
476 | { | |
477 | struct drm_device *dev = ring->dev; | |
478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
479 | struct drm_i915_gem_object *obj = ring->obj; | |
480 | int ret = 0; | |
481 | ||
482 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
483 | ||
484 | if (!stop_ring(ring)) { | |
485 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
486 | DRM_DEBUG_KMS("%s head not reset to zero " |
487 | "ctl %08x head %08x tail %08x start %08x\n", | |
488 | ring->name, | |
489 | I915_READ_CTL(ring), | |
490 | I915_READ_HEAD(ring), | |
491 | I915_READ_TAIL(ring), | |
492 | I915_READ_START(ring)); | |
8187a2b7 | 493 | |
9991ae78 | 494 | if (!stop_ring(ring)) { |
6fd0d56e CW |
495 | DRM_ERROR("failed to set %s head to zero " |
496 | "ctl %08x head %08x tail %08x start %08x\n", | |
497 | ring->name, | |
498 | I915_READ_CTL(ring), | |
499 | I915_READ_HEAD(ring), | |
500 | I915_READ_TAIL(ring), | |
501 | I915_READ_START(ring)); | |
9991ae78 CW |
502 | ret = -EIO; |
503 | goto out; | |
6fd0d56e | 504 | } |
8187a2b7 ZN |
505 | } |
506 | ||
9991ae78 CW |
507 | if (I915_NEED_GFX_HWS(dev)) |
508 | intel_ring_setup_status_page(ring); | |
509 | else | |
510 | ring_setup_phys_status_page(ring); | |
511 | ||
0d8957c8 DV |
512 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
513 | * registers with the above sequence (the readback of the HEAD registers | |
514 | * also enforces ordering), otherwise the hw might lose the new ring | |
515 | * register values. */ | |
f343c5f6 | 516 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 517 | I915_WRITE_CTL(ring, |
ae69b42a | 518 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 519 | | RING_VALID); |
8187a2b7 | 520 | |
8187a2b7 | 521 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 522 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 523 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 524 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
525 | DRM_ERROR("%s initialization failed " |
526 | "ctl %08x head %08x tail %08x start %08x\n", | |
527 | ring->name, | |
528 | I915_READ_CTL(ring), | |
529 | I915_READ_HEAD(ring), | |
530 | I915_READ_TAIL(ring), | |
531 | I915_READ_START(ring)); | |
b7884eb4 DV |
532 | ret = -EIO; |
533 | goto out; | |
8187a2b7 ZN |
534 | } |
535 | ||
78501eac CW |
536 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
537 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 538 | else { |
c7dca47b | 539 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 540 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 541 | ring->space = ring_space(ring); |
c3b20037 | 542 | ring->last_retired_head = -1; |
8187a2b7 | 543 | } |
1ec14ad3 | 544 | |
50f018df CW |
545 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
546 | ||
b7884eb4 | 547 | out: |
c8d9a590 | 548 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
549 | |
550 | return ret; | |
8187a2b7 ZN |
551 | } |
552 | ||
c6df541c CW |
553 | static int |
554 | init_pipe_control(struct intel_ring_buffer *ring) | |
555 | { | |
c6df541c CW |
556 | int ret; |
557 | ||
0d1aacac | 558 | if (ring->scratch.obj) |
c6df541c CW |
559 | return 0; |
560 | ||
0d1aacac CW |
561 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
562 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
563 | DRM_ERROR("Failed to allocate seqno page\n"); |
564 | ret = -ENOMEM; | |
565 | goto err; | |
566 | } | |
e4ffd173 | 567 | |
a9cc726c DV |
568 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
569 | if (ret) | |
570 | goto err_unref; | |
c6df541c | 571 | |
1ec9e26d | 572 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
573 | if (ret) |
574 | goto err_unref; | |
575 | ||
0d1aacac CW |
576 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
577 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
578 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 579 | ret = -ENOMEM; |
c6df541c | 580 | goto err_unpin; |
56b085a0 | 581 | } |
c6df541c | 582 | |
2b1086cc | 583 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 584 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
585 | return 0; |
586 | ||
587 | err_unpin: | |
d7f46fc4 | 588 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 589 | err_unref: |
0d1aacac | 590 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 591 | err: |
c6df541c CW |
592 | return ret; |
593 | } | |
594 | ||
78501eac | 595 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 596 | { |
78501eac | 597 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 598 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 599 | int ret = init_ring_common(ring); |
a69ffdbf | 600 | |
61a563a2 AG |
601 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
602 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 603 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
604 | |
605 | /* We need to disable the AsyncFlip performance optimisations in order | |
606 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
607 | * programmed to '1' on all products. | |
8693a824 | 608 | * |
8285222c | 609 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw |
1c8c38c5 CW |
610 | */ |
611 | if (INTEL_INFO(dev)->gen >= 6) | |
612 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
613 | ||
f05bb0c7 | 614 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 615 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
616 | if (INTEL_INFO(dev)->gen == 6) |
617 | I915_WRITE(GFX_MODE, | |
aa83e30d | 618 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 619 | |
01fa0302 | 620 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
621 | if (IS_GEN7(dev)) |
622 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 623 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 624 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 625 | |
8d315287 | 626 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
627 | ret = init_pipe_control(ring); |
628 | if (ret) | |
629 | return ret; | |
630 | } | |
631 | ||
5e13a0c5 | 632 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
633 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
634 | * "If this bit is set, STCunit will have LRA as replacement | |
635 | * policy. [...] This bit must be reset. LRA replacement | |
636 | * policy is not supported." | |
637 | */ | |
638 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 639 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
640 | } |
641 | ||
6b26c86d DV |
642 | if (INTEL_INFO(dev)->gen >= 6) |
643 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 644 | |
040d2baa | 645 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 646 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 647 | |
8187a2b7 ZN |
648 | return ret; |
649 | } | |
650 | ||
c6df541c CW |
651 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
652 | { | |
b45305fc DV |
653 | struct drm_device *dev = ring->dev; |
654 | ||
0d1aacac | 655 | if (ring->scratch.obj == NULL) |
c6df541c CW |
656 | return; |
657 | ||
0d1aacac CW |
658 | if (INTEL_INFO(dev)->gen >= 5) { |
659 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
d7f46fc4 | 660 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
0d1aacac | 661 | } |
aaf8a516 | 662 | |
0d1aacac CW |
663 | drm_gem_object_unreference(&ring->scratch.obj->base); |
664 | ring->scratch.obj = NULL; | |
c6df541c CW |
665 | } |
666 | ||
1ec14ad3 | 667 | static void |
c8c99b0f | 668 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 669 | u32 mmio_offset) |
1ec14ad3 | 670 | { |
ad776f8b BW |
671 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
672 | * of rings, it's easiest if we round up each individual update to a | |
673 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
674 | * even though the actual update only requires 3 dwords. | |
675 | */ | |
676 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 677 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 678 | intel_ring_emit(ring, mmio_offset); |
1823521d | 679 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 680 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
681 | } |
682 | ||
c8c99b0f BW |
683 | /** |
684 | * gen6_add_request - Update the semaphore mailbox registers | |
685 | * | |
686 | * @ring - ring that is adding a request | |
687 | * @seqno - return seqno stuck into the ring | |
688 | * | |
689 | * Update the mailbox registers in the *other* rings with the current seqno. | |
690 | * This acts like a signal in the canonical semaphore. | |
691 | */ | |
1ec14ad3 | 692 | static int |
9d773091 | 693 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 694 | { |
ad776f8b BW |
695 | struct drm_device *dev = ring->dev; |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
697 | struct intel_ring_buffer *useless; | |
52ed2325 | 698 | int i, ret, num_dwords = 4; |
1ec14ad3 | 699 | |
52ed2325 BW |
700 | if (i915_semaphore_is_enabled(dev)) |
701 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); | |
702 | #undef MBOX_UPDATE_DWORDS | |
703 | ||
704 | ret = intel_ring_begin(ring, num_dwords); | |
1ec14ad3 CW |
705 | if (ret) |
706 | return ret; | |
707 | ||
f0a9f74c BW |
708 | if (i915_semaphore_is_enabled(dev)) { |
709 | for_each_ring(useless, dev_priv, i) { | |
710 | u32 mbox_reg = ring->signal_mbox[i]; | |
711 | if (mbox_reg != GEN6_NOSYNC) | |
712 | update_mboxes(ring, mbox_reg); | |
713 | } | |
ad776f8b | 714 | } |
1ec14ad3 CW |
715 | |
716 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
717 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 718 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 719 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 720 | __intel_ring_advance(ring); |
1ec14ad3 | 721 | |
1ec14ad3 CW |
722 | return 0; |
723 | } | |
724 | ||
f72b3435 MK |
725 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
726 | u32 seqno) | |
727 | { | |
728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
729 | return dev_priv->last_seqno < seqno; | |
730 | } | |
731 | ||
c8c99b0f BW |
732 | /** |
733 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
734 | * | |
735 | * @waiter - ring that is waiting | |
736 | * @signaller - ring which has, or will signal | |
737 | * @seqno - seqno which the waiter will block on | |
738 | */ | |
739 | static int | |
686cb5f9 DV |
740 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
741 | struct intel_ring_buffer *signaller, | |
742 | u32 seqno) | |
1ec14ad3 CW |
743 | { |
744 | int ret; | |
c8c99b0f BW |
745 | u32 dw1 = MI_SEMAPHORE_MBOX | |
746 | MI_SEMAPHORE_COMPARE | | |
747 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 748 | |
1500f7ea BW |
749 | /* Throughout all of the GEM code, seqno passed implies our current |
750 | * seqno is >= the last seqno executed. However for hardware the | |
751 | * comparison is strictly greater than. | |
752 | */ | |
753 | seqno -= 1; | |
754 | ||
686cb5f9 DV |
755 | WARN_ON(signaller->semaphore_register[waiter->id] == |
756 | MI_SEMAPHORE_SYNC_INVALID); | |
757 | ||
c8c99b0f | 758 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
759 | if (ret) |
760 | return ret; | |
761 | ||
f72b3435 MK |
762 | /* If seqno wrap happened, omit the wait with no-ops */ |
763 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
764 | intel_ring_emit(waiter, | |
765 | dw1 | | |
766 | signaller->semaphore_register[waiter->id]); | |
767 | intel_ring_emit(waiter, seqno); | |
768 | intel_ring_emit(waiter, 0); | |
769 | intel_ring_emit(waiter, MI_NOOP); | |
770 | } else { | |
771 | intel_ring_emit(waiter, MI_NOOP); | |
772 | intel_ring_emit(waiter, MI_NOOP); | |
773 | intel_ring_emit(waiter, MI_NOOP); | |
774 | intel_ring_emit(waiter, MI_NOOP); | |
775 | } | |
c8c99b0f | 776 | intel_ring_advance(waiter); |
1ec14ad3 CW |
777 | |
778 | return 0; | |
779 | } | |
780 | ||
c6df541c CW |
781 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
782 | do { \ | |
fcbc34e4 KG |
783 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
784 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
785 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
786 | intel_ring_emit(ring__, 0); \ | |
787 | intel_ring_emit(ring__, 0); \ | |
788 | } while (0) | |
789 | ||
790 | static int | |
9d773091 | 791 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 792 | { |
18393f63 | 793 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
794 | int ret; |
795 | ||
796 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
797 | * incoherent with writes to memory, i.e. completely fubar, | |
798 | * so we need to use PIPE_NOTIFY instead. | |
799 | * | |
800 | * However, we also need to workaround the qword write | |
801 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
802 | * memory before requesting an interrupt. | |
803 | */ | |
804 | ret = intel_ring_begin(ring, 32); | |
805 | if (ret) | |
806 | return ret; | |
807 | ||
fcbc34e4 | 808 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
809 | PIPE_CONTROL_WRITE_FLUSH | |
810 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 811 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 812 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
813 | intel_ring_emit(ring, 0); |
814 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 815 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 816 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 817 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 818 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 819 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 820 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 821 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 822 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 823 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 824 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 825 | |
fcbc34e4 | 826 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
827 | PIPE_CONTROL_WRITE_FLUSH | |
828 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 829 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 830 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 831 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 832 | intel_ring_emit(ring, 0); |
09246732 | 833 | __intel_ring_advance(ring); |
c6df541c | 834 | |
c6df541c CW |
835 | return 0; |
836 | } | |
837 | ||
4cd53c0c | 838 | static u32 |
b2eadbc8 | 839 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 840 | { |
4cd53c0c DV |
841 | /* Workaround to force correct ordering between irq and seqno writes on |
842 | * ivb (and maybe also on snb) by reading from a CS register (like | |
843 | * ACTHD) before reading the status page. */ | |
50877445 CW |
844 | if (!lazy_coherency) { |
845 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
846 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
847 | } | |
848 | ||
4cd53c0c DV |
849 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
850 | } | |
851 | ||
8187a2b7 | 852 | static u32 |
b2eadbc8 | 853 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 854 | { |
1ec14ad3 CW |
855 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
856 | } | |
857 | ||
b70ec5bf MK |
858 | static void |
859 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
860 | { | |
861 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
862 | } | |
863 | ||
c6df541c | 864 | static u32 |
b2eadbc8 | 865 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 866 | { |
0d1aacac | 867 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
868 | } |
869 | ||
b70ec5bf MK |
870 | static void |
871 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
872 | { | |
0d1aacac | 873 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
874 | } |
875 | ||
e48d8634 DV |
876 | static bool |
877 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
878 | { | |
879 | struct drm_device *dev = ring->dev; | |
4640c4ff | 880 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 881 | unsigned long flags; |
e48d8634 DV |
882 | |
883 | if (!dev->irq_enabled) | |
884 | return false; | |
885 | ||
7338aefa | 886 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
887 | if (ring->irq_refcount++ == 0) |
888 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 889 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
890 | |
891 | return true; | |
892 | } | |
893 | ||
894 | static void | |
895 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
896 | { | |
897 | struct drm_device *dev = ring->dev; | |
4640c4ff | 898 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 899 | unsigned long flags; |
e48d8634 | 900 | |
7338aefa | 901 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
902 | if (--ring->irq_refcount == 0) |
903 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 904 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
905 | } |
906 | ||
b13c2b96 | 907 | static bool |
e3670319 | 908 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 909 | { |
78501eac | 910 | struct drm_device *dev = ring->dev; |
4640c4ff | 911 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 912 | unsigned long flags; |
62fdfeaf | 913 | |
b13c2b96 CW |
914 | if (!dev->irq_enabled) |
915 | return false; | |
916 | ||
7338aefa | 917 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 918 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
919 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
920 | I915_WRITE(IMR, dev_priv->irq_mask); | |
921 | POSTING_READ(IMR); | |
922 | } | |
7338aefa | 923 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
924 | |
925 | return true; | |
62fdfeaf EA |
926 | } |
927 | ||
8187a2b7 | 928 | static void |
e3670319 | 929 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 930 | { |
78501eac | 931 | struct drm_device *dev = ring->dev; |
4640c4ff | 932 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 933 | unsigned long flags; |
62fdfeaf | 934 | |
7338aefa | 935 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 936 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
937 | dev_priv->irq_mask |= ring->irq_enable_mask; |
938 | I915_WRITE(IMR, dev_priv->irq_mask); | |
939 | POSTING_READ(IMR); | |
940 | } | |
7338aefa | 941 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
942 | } |
943 | ||
c2798b19 CW |
944 | static bool |
945 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
946 | { | |
947 | struct drm_device *dev = ring->dev; | |
4640c4ff | 948 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 949 | unsigned long flags; |
c2798b19 CW |
950 | |
951 | if (!dev->irq_enabled) | |
952 | return false; | |
953 | ||
7338aefa | 954 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 955 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
956 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
957 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
958 | POSTING_READ16(IMR); | |
959 | } | |
7338aefa | 960 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
961 | |
962 | return true; | |
963 | } | |
964 | ||
965 | static void | |
966 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
967 | { | |
968 | struct drm_device *dev = ring->dev; | |
4640c4ff | 969 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 970 | unsigned long flags; |
c2798b19 | 971 | |
7338aefa | 972 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 973 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
974 | dev_priv->irq_mask |= ring->irq_enable_mask; |
975 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
976 | POSTING_READ16(IMR); | |
977 | } | |
7338aefa | 978 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
979 | } |
980 | ||
78501eac | 981 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 982 | { |
4593010b | 983 | struct drm_device *dev = ring->dev; |
4640c4ff | 984 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
985 | u32 mmio = 0; |
986 | ||
987 | /* The ring status page addresses are no longer next to the rest of | |
988 | * the ring registers as of gen7. | |
989 | */ | |
990 | if (IS_GEN7(dev)) { | |
991 | switch (ring->id) { | |
96154f2f | 992 | case RCS: |
4593010b EA |
993 | mmio = RENDER_HWS_PGA_GEN7; |
994 | break; | |
96154f2f | 995 | case BCS: |
4593010b EA |
996 | mmio = BLT_HWS_PGA_GEN7; |
997 | break; | |
96154f2f | 998 | case VCS: |
4593010b EA |
999 | mmio = BSD_HWS_PGA_GEN7; |
1000 | break; | |
4a3dd19d | 1001 | case VECS: |
9a8a2213 BW |
1002 | mmio = VEBOX_HWS_PGA_GEN7; |
1003 | break; | |
4593010b EA |
1004 | } |
1005 | } else if (IS_GEN6(ring->dev)) { | |
1006 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1007 | } else { | |
eb0d4b75 | 1008 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1009 | mmio = RING_HWS_PGA(ring->mmio_base); |
1010 | } | |
1011 | ||
78501eac CW |
1012 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1013 | POSTING_READ(mmio); | |
884020bf | 1014 | |
dc616b89 DL |
1015 | /* |
1016 | * Flush the TLB for this page | |
1017 | * | |
1018 | * FIXME: These two bits have disappeared on gen8, so a question | |
1019 | * arises: do we still need this and if so how should we go about | |
1020 | * invalidating the TLB? | |
1021 | */ | |
1022 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1023 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1024 | |
1025 | /* ring should be idle before issuing a sync flush*/ | |
1026 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1027 | ||
884020bf CW |
1028 | I915_WRITE(reg, |
1029 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1030 | INSTPM_SYNC_FLUSH)); | |
1031 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1032 | 1000)) | |
1033 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1034 | ring->name); | |
1035 | } | |
8187a2b7 ZN |
1036 | } |
1037 | ||
b72f3acb | 1038 | static int |
78501eac CW |
1039 | bsd_ring_flush(struct intel_ring_buffer *ring, |
1040 | u32 invalidate_domains, | |
1041 | u32 flush_domains) | |
d1b851fc | 1042 | { |
b72f3acb CW |
1043 | int ret; |
1044 | ||
b72f3acb CW |
1045 | ret = intel_ring_begin(ring, 2); |
1046 | if (ret) | |
1047 | return ret; | |
1048 | ||
1049 | intel_ring_emit(ring, MI_FLUSH); | |
1050 | intel_ring_emit(ring, MI_NOOP); | |
1051 | intel_ring_advance(ring); | |
1052 | return 0; | |
d1b851fc ZN |
1053 | } |
1054 | ||
3cce469c | 1055 | static int |
9d773091 | 1056 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 1057 | { |
3cce469c CW |
1058 | int ret; |
1059 | ||
1060 | ret = intel_ring_begin(ring, 4); | |
1061 | if (ret) | |
1062 | return ret; | |
6f392d54 | 1063 | |
3cce469c CW |
1064 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1065 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1066 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1067 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1068 | __intel_ring_advance(ring); |
d1b851fc | 1069 | |
3cce469c | 1070 | return 0; |
d1b851fc ZN |
1071 | } |
1072 | ||
0f46832f | 1073 | static bool |
25c06300 | 1074 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1075 | { |
1076 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1077 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1078 | unsigned long flags; |
0f46832f CW |
1079 | |
1080 | if (!dev->irq_enabled) | |
1081 | return false; | |
1082 | ||
7338aefa | 1083 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1084 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1085 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1086 | I915_WRITE_IMR(ring, |
1087 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1088 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1089 | else |
1090 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1091 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1092 | } |
7338aefa | 1093 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1094 | |
1095 | return true; | |
1096 | } | |
1097 | ||
1098 | static void | |
25c06300 | 1099 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1100 | { |
1101 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1102 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1103 | unsigned long flags; |
0f46832f | 1104 | |
7338aefa | 1105 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1106 | if (--ring->irq_refcount == 0) { |
040d2baa | 1107 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1108 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1109 | else |
1110 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1111 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1112 | } |
7338aefa | 1113 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1114 | } |
1115 | ||
a19d2933 BW |
1116 | static bool |
1117 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1118 | { | |
1119 | struct drm_device *dev = ring->dev; | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | unsigned long flags; | |
1122 | ||
1123 | if (!dev->irq_enabled) | |
1124 | return false; | |
1125 | ||
59cdb63d | 1126 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1127 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1128 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1129 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1130 | } |
59cdb63d | 1131 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1132 | |
1133 | return true; | |
1134 | } | |
1135 | ||
1136 | static void | |
1137 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1138 | { | |
1139 | struct drm_device *dev = ring->dev; | |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1141 | unsigned long flags; | |
1142 | ||
1143 | if (!dev->irq_enabled) | |
1144 | return; | |
1145 | ||
59cdb63d | 1146 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1147 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1148 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1149 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1150 | } |
59cdb63d | 1151 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1152 | } |
1153 | ||
abd58f01 BW |
1154 | static bool |
1155 | gen8_ring_get_irq(struct intel_ring_buffer *ring) | |
1156 | { | |
1157 | struct drm_device *dev = ring->dev; | |
1158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1159 | unsigned long flags; | |
1160 | ||
1161 | if (!dev->irq_enabled) | |
1162 | return false; | |
1163 | ||
1164 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1165 | if (ring->irq_refcount++ == 0) { | |
1166 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1167 | I915_WRITE_IMR(ring, | |
1168 | ~(ring->irq_enable_mask | | |
1169 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1170 | } else { | |
1171 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1172 | } | |
1173 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1174 | } | |
1175 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1176 | ||
1177 | return true; | |
1178 | } | |
1179 | ||
1180 | static void | |
1181 | gen8_ring_put_irq(struct intel_ring_buffer *ring) | |
1182 | { | |
1183 | struct drm_device *dev = ring->dev; | |
1184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1185 | unsigned long flags; | |
1186 | ||
1187 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1188 | if (--ring->irq_refcount == 0) { | |
1189 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1190 | I915_WRITE_IMR(ring, | |
1191 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1192 | } else { | |
1193 | I915_WRITE_IMR(ring, ~0); | |
1194 | } | |
1195 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1196 | } | |
1197 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1198 | } | |
1199 | ||
d1b851fc | 1200 | static int |
d7d4eedd CW |
1201 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1202 | u32 offset, u32 length, | |
1203 | unsigned flags) | |
d1b851fc | 1204 | { |
e1f99ce6 | 1205 | int ret; |
78501eac | 1206 | |
e1f99ce6 CW |
1207 | ret = intel_ring_begin(ring, 2); |
1208 | if (ret) | |
1209 | return ret; | |
1210 | ||
78501eac | 1211 | intel_ring_emit(ring, |
65f56876 CW |
1212 | MI_BATCH_BUFFER_START | |
1213 | MI_BATCH_GTT | | |
d7d4eedd | 1214 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1215 | intel_ring_emit(ring, offset); |
78501eac CW |
1216 | intel_ring_advance(ring); |
1217 | ||
d1b851fc ZN |
1218 | return 0; |
1219 | } | |
1220 | ||
b45305fc DV |
1221 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1222 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1223 | static int |
fb3256da | 1224 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1225 | u32 offset, u32 len, |
1226 | unsigned flags) | |
62fdfeaf | 1227 | { |
c4e7a414 | 1228 | int ret; |
62fdfeaf | 1229 | |
b45305fc DV |
1230 | if (flags & I915_DISPATCH_PINNED) { |
1231 | ret = intel_ring_begin(ring, 4); | |
1232 | if (ret) | |
1233 | return ret; | |
62fdfeaf | 1234 | |
b45305fc DV |
1235 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1236 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1237 | intel_ring_emit(ring, offset + len - 8); | |
1238 | intel_ring_emit(ring, MI_NOOP); | |
1239 | intel_ring_advance(ring); | |
1240 | } else { | |
0d1aacac | 1241 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1242 | |
1243 | if (len > I830_BATCH_LIMIT) | |
1244 | return -ENOSPC; | |
1245 | ||
1246 | ret = intel_ring_begin(ring, 9+3); | |
1247 | if (ret) | |
1248 | return ret; | |
1249 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1250 | * scratch bo area (so that the CS never stumbles over its tlb | |
1251 | * invalidation bug) ... */ | |
1252 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1253 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1254 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1255 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1256 | intel_ring_emit(ring, 0); | |
1257 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1258 | intel_ring_emit(ring, cs_offset); | |
1259 | intel_ring_emit(ring, 0); | |
1260 | intel_ring_emit(ring, 4096); | |
1261 | intel_ring_emit(ring, offset); | |
1262 | intel_ring_emit(ring, MI_FLUSH); | |
1263 | ||
1264 | /* ... and execute it. */ | |
1265 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1266 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1267 | intel_ring_emit(ring, cs_offset + len - 8); | |
1268 | intel_ring_advance(ring); | |
1269 | } | |
e1f99ce6 | 1270 | |
fb3256da DV |
1271 | return 0; |
1272 | } | |
1273 | ||
1274 | static int | |
1275 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1276 | u32 offset, u32 len, |
1277 | unsigned flags) | |
fb3256da DV |
1278 | { |
1279 | int ret; | |
1280 | ||
1281 | ret = intel_ring_begin(ring, 2); | |
1282 | if (ret) | |
1283 | return ret; | |
1284 | ||
65f56876 | 1285 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1286 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1287 | intel_ring_advance(ring); |
62fdfeaf | 1288 | |
62fdfeaf EA |
1289 | return 0; |
1290 | } | |
1291 | ||
78501eac | 1292 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1293 | { |
05394f39 | 1294 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1295 | |
8187a2b7 ZN |
1296 | obj = ring->status_page.obj; |
1297 | if (obj == NULL) | |
62fdfeaf | 1298 | return; |
62fdfeaf | 1299 | |
9da3da66 | 1300 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1301 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1302 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1303 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1304 | } |
1305 | ||
78501eac | 1306 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1307 | { |
78501eac | 1308 | struct drm_device *dev = ring->dev; |
05394f39 | 1309 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1310 | int ret; |
1311 | ||
62fdfeaf EA |
1312 | obj = i915_gem_alloc_object(dev, 4096); |
1313 | if (obj == NULL) { | |
1314 | DRM_ERROR("Failed to allocate status page\n"); | |
1315 | ret = -ENOMEM; | |
1316 | goto err; | |
1317 | } | |
e4ffd173 | 1318 | |
e01f6929 DV |
1319 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1320 | if (ret) | |
1321 | goto err_unref; | |
62fdfeaf | 1322 | |
9a6bbb62 | 1323 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); |
1ec9e26d | 1324 | if (ret) |
62fdfeaf | 1325 | goto err_unref; |
62fdfeaf | 1326 | |
f343c5f6 | 1327 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1328 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1329 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1330 | ret = -ENOMEM; |
62fdfeaf EA |
1331 | goto err_unpin; |
1332 | } | |
8187a2b7 ZN |
1333 | ring->status_page.obj = obj; |
1334 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1335 | |
8187a2b7 ZN |
1336 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1337 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1338 | |
1339 | return 0; | |
1340 | ||
1341 | err_unpin: | |
d7f46fc4 | 1342 | i915_gem_object_ggtt_unpin(obj); |
62fdfeaf | 1343 | err_unref: |
05394f39 | 1344 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1345 | err: |
8187a2b7 | 1346 | return ret; |
62fdfeaf EA |
1347 | } |
1348 | ||
035dc1e0 | 1349 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1350 | { |
1351 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1352 | |
1353 | if (!dev_priv->status_page_dmah) { | |
1354 | dev_priv->status_page_dmah = | |
1355 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1356 | if (!dev_priv->status_page_dmah) | |
1357 | return -ENOMEM; | |
1358 | } | |
1359 | ||
6b8294a4 CW |
1360 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1361 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1362 | ||
1363 | return 0; | |
1364 | } | |
1365 | ||
c43b5634 BW |
1366 | static int intel_init_ring_buffer(struct drm_device *dev, |
1367 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1368 | { |
05394f39 | 1369 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1370 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1371 | int ret; |
1372 | ||
8187a2b7 | 1373 | ring->dev = dev; |
23bc5982 CW |
1374 | INIT_LIST_HEAD(&ring->active_list); |
1375 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1376 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1377 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1378 | |
b259f673 | 1379 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1380 | |
8187a2b7 | 1381 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1382 | ret = init_status_page(ring); |
8187a2b7 ZN |
1383 | if (ret) |
1384 | return ret; | |
6b8294a4 CW |
1385 | } else { |
1386 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1387 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1388 | if (ret) |
1389 | return ret; | |
8187a2b7 | 1390 | } |
62fdfeaf | 1391 | |
ebc052e0 CW |
1392 | obj = NULL; |
1393 | if (!HAS_LLC(dev)) | |
1394 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1395 | if (obj == NULL) | |
1396 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1397 | if (obj == NULL) { |
1398 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1399 | ret = -ENOMEM; |
dd785e35 | 1400 | goto err_hws; |
62fdfeaf | 1401 | } |
62fdfeaf | 1402 | |
05394f39 | 1403 | ring->obj = obj; |
8187a2b7 | 1404 | |
1ec9e26d | 1405 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1406 | if (ret) |
1407 | goto err_unref; | |
62fdfeaf | 1408 | |
3eef8918 CW |
1409 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1410 | if (ret) | |
1411 | goto err_unpin; | |
1412 | ||
dd2757f8 | 1413 | ring->virtual_start = |
f343c5f6 | 1414 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1415 | ring->size); |
4225d0f2 | 1416 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1417 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1418 | ret = -EINVAL; |
dd785e35 | 1419 | goto err_unpin; |
62fdfeaf EA |
1420 | } |
1421 | ||
78501eac | 1422 | ret = ring->init(ring); |
dd785e35 CW |
1423 | if (ret) |
1424 | goto err_unmap; | |
62fdfeaf | 1425 | |
55249baa CW |
1426 | /* Workaround an erratum on the i830 which causes a hang if |
1427 | * the TAIL pointer points to within the last 2 cachelines | |
1428 | * of the buffer. | |
1429 | */ | |
1430 | ring->effective_size = ring->size; | |
27c1cbd0 | 1431 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
18393f63 | 1432 | ring->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1433 | |
351e3db2 BV |
1434 | i915_cmd_parser_init_ring(ring); |
1435 | ||
c584fe47 | 1436 | return 0; |
dd785e35 CW |
1437 | |
1438 | err_unmap: | |
4225d0f2 | 1439 | iounmap(ring->virtual_start); |
dd785e35 | 1440 | err_unpin: |
d7f46fc4 | 1441 | i915_gem_object_ggtt_unpin(obj); |
dd785e35 | 1442 | err_unref: |
05394f39 CW |
1443 | drm_gem_object_unreference(&obj->base); |
1444 | ring->obj = NULL; | |
dd785e35 | 1445 | err_hws: |
78501eac | 1446 | cleanup_status_page(ring); |
8187a2b7 | 1447 | return ret; |
62fdfeaf EA |
1448 | } |
1449 | ||
78501eac | 1450 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1451 | { |
33626e6a CW |
1452 | struct drm_i915_private *dev_priv; |
1453 | int ret; | |
1454 | ||
05394f39 | 1455 | if (ring->obj == NULL) |
62fdfeaf EA |
1456 | return; |
1457 | ||
33626e6a CW |
1458 | /* Disable the ring buffer. The ring must be idle at this point */ |
1459 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1460 | ret = intel_ring_idle(ring); |
3d57e5bd | 1461 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
29ee3991 CW |
1462 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1463 | ring->name, ret); | |
1464 | ||
33626e6a CW |
1465 | I915_WRITE_CTL(ring, 0); |
1466 | ||
4225d0f2 | 1467 | iounmap(ring->virtual_start); |
62fdfeaf | 1468 | |
d7f46fc4 | 1469 | i915_gem_object_ggtt_unpin(ring->obj); |
05394f39 CW |
1470 | drm_gem_object_unreference(&ring->obj->base); |
1471 | ring->obj = NULL; | |
3d57e5bd BW |
1472 | ring->preallocated_lazy_request = NULL; |
1473 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1474 | |
8d19215b ZN |
1475 | if (ring->cleanup) |
1476 | ring->cleanup(ring); | |
1477 | ||
78501eac | 1478 | cleanup_status_page(ring); |
62fdfeaf EA |
1479 | } |
1480 | ||
a71d8d94 CW |
1481 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
1482 | { | |
1483 | struct drm_i915_gem_request *request; | |
1f70999f | 1484 | u32 seqno = 0, tail; |
a71d8d94 CW |
1485 | int ret; |
1486 | ||
a71d8d94 CW |
1487 | if (ring->last_retired_head != -1) { |
1488 | ring->head = ring->last_retired_head; | |
1489 | ring->last_retired_head = -1; | |
1f70999f | 1490 | |
a71d8d94 CW |
1491 | ring->space = ring_space(ring); |
1492 | if (ring->space >= n) | |
1493 | return 0; | |
1494 | } | |
1495 | ||
1496 | list_for_each_entry(request, &ring->request_list, list) { | |
1497 | int space; | |
1498 | ||
1499 | if (request->tail == -1) | |
1500 | continue; | |
1501 | ||
633cf8f5 | 1502 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1503 | if (space < 0) |
1504 | space += ring->size; | |
1505 | if (space >= n) { | |
1506 | seqno = request->seqno; | |
1f70999f | 1507 | tail = request->tail; |
a71d8d94 CW |
1508 | break; |
1509 | } | |
1510 | ||
1511 | /* Consume this request in case we need more space than | |
1512 | * is available and so need to prevent a race between | |
1513 | * updating last_retired_head and direct reads of | |
1514 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1515 | */ | |
1516 | request->tail = -1; | |
1517 | } | |
1518 | ||
1519 | if (seqno == 0) | |
1520 | return -ENOSPC; | |
1521 | ||
1f70999f | 1522 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1523 | if (ret) |
1524 | return ret; | |
1525 | ||
1f70999f | 1526 | ring->head = tail; |
a71d8d94 CW |
1527 | ring->space = ring_space(ring); |
1528 | if (WARN_ON(ring->space < n)) | |
1529 | return -ENOSPC; | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
3e960501 | 1534 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1535 | { |
78501eac | 1536 | struct drm_device *dev = ring->dev; |
cae5852d | 1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1538 | unsigned long end; |
a71d8d94 | 1539 | int ret; |
c7dca47b | 1540 | |
a71d8d94 CW |
1541 | ret = intel_ring_wait_request(ring, n); |
1542 | if (ret != -ENOSPC) | |
1543 | return ret; | |
1544 | ||
09246732 CW |
1545 | /* force the tail write in case we have been skipping them */ |
1546 | __intel_ring_advance(ring); | |
1547 | ||
db53a302 | 1548 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1549 | /* With GEM the hangcheck timer should kick us out of the loop, |
1550 | * leaving it early runs the risk of corrupting GEM state (due | |
1551 | * to running on almost untested codepaths). But on resume | |
1552 | * timers don't work yet, so prevent a complete hang in that | |
1553 | * case by choosing an insanely large timeout. */ | |
1554 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1555 | |
8187a2b7 | 1556 | do { |
c7dca47b CW |
1557 | ring->head = I915_READ_HEAD(ring); |
1558 | ring->space = ring_space(ring); | |
62fdfeaf | 1559 | if (ring->space >= n) { |
db53a302 | 1560 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1561 | return 0; |
1562 | } | |
1563 | ||
fb19e2ac DV |
1564 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1565 | dev->primary->master) { | |
62fdfeaf EA |
1566 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1567 | if (master_priv->sarea_priv) | |
1568 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1569 | } | |
d1b851fc | 1570 | |
e60a0b10 | 1571 | msleep(1); |
d6b2c790 | 1572 | |
33196ded DV |
1573 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1574 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1575 | if (ret) |
1576 | return ret; | |
8187a2b7 | 1577 | } while (!time_after(jiffies, end)); |
db53a302 | 1578 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1579 | return -EBUSY; |
1580 | } | |
62fdfeaf | 1581 | |
3e960501 CW |
1582 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1583 | { | |
1584 | uint32_t __iomem *virt; | |
1585 | int rem = ring->size - ring->tail; | |
1586 | ||
1587 | if (ring->space < rem) { | |
1588 | int ret = ring_wait_for_space(ring, rem); | |
1589 | if (ret) | |
1590 | return ret; | |
1591 | } | |
1592 | ||
1593 | virt = ring->virtual_start + ring->tail; | |
1594 | rem /= 4; | |
1595 | while (rem--) | |
1596 | iowrite32(MI_NOOP, virt++); | |
1597 | ||
1598 | ring->tail = 0; | |
1599 | ring->space = ring_space(ring); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
1604 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1605 | { | |
1606 | u32 seqno; | |
1607 | int ret; | |
1608 | ||
1609 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1610 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1611 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1612 | if (ret) |
1613 | return ret; | |
1614 | } | |
1615 | ||
1616 | /* Wait upon the last request to be completed */ | |
1617 | if (list_empty(&ring->request_list)) | |
1618 | return 0; | |
1619 | ||
1620 | seqno = list_entry(ring->request_list.prev, | |
1621 | struct drm_i915_gem_request, | |
1622 | list)->seqno; | |
1623 | ||
1624 | return i915_wait_seqno(ring, seqno); | |
1625 | } | |
1626 | ||
9d773091 CW |
1627 | static int |
1628 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1629 | { | |
1823521d | 1630 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1631 | return 0; |
1632 | ||
3c0e234c CW |
1633 | if (ring->preallocated_lazy_request == NULL) { |
1634 | struct drm_i915_gem_request *request; | |
1635 | ||
1636 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1637 | if (request == NULL) | |
1638 | return -ENOMEM; | |
1639 | ||
1640 | ring->preallocated_lazy_request = request; | |
1641 | } | |
1642 | ||
1823521d | 1643 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1644 | } |
1645 | ||
304d695c CW |
1646 | static int __intel_ring_prepare(struct intel_ring_buffer *ring, |
1647 | int bytes) | |
cbcc80df MK |
1648 | { |
1649 | int ret; | |
1650 | ||
1651 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1652 | ret = intel_wrap_ring_buffer(ring); | |
1653 | if (unlikely(ret)) | |
1654 | return ret; | |
1655 | } | |
1656 | ||
1657 | if (unlikely(ring->space < bytes)) { | |
1658 | ret = ring_wait_for_space(ring, bytes); | |
1659 | if (unlikely(ret)) | |
1660 | return ret; | |
1661 | } | |
1662 | ||
cbcc80df MK |
1663 | return 0; |
1664 | } | |
1665 | ||
e1f99ce6 CW |
1666 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1667 | int num_dwords) | |
8187a2b7 | 1668 | { |
4640c4ff | 1669 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1670 | int ret; |
78501eac | 1671 | |
33196ded DV |
1672 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1673 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1674 | if (ret) |
1675 | return ret; | |
21dd3734 | 1676 | |
304d695c CW |
1677 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1678 | if (ret) | |
1679 | return ret; | |
1680 | ||
9d773091 CW |
1681 | /* Preallocate the olr before touching the ring */ |
1682 | ret = intel_ring_alloc_seqno(ring); | |
1683 | if (ret) | |
1684 | return ret; | |
1685 | ||
304d695c CW |
1686 | ring->space -= num_dwords * sizeof(uint32_t); |
1687 | return 0; | |
8187a2b7 | 1688 | } |
78501eac | 1689 | |
753b1ad4 VS |
1690 | /* Align the ring tail to a cacheline boundary */ |
1691 | int intel_ring_cacheline_align(struct intel_ring_buffer *ring) | |
1692 | { | |
18393f63 | 1693 | int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
1694 | int ret; |
1695 | ||
1696 | if (num_dwords == 0) | |
1697 | return 0; | |
1698 | ||
18393f63 | 1699 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
1700 | ret = intel_ring_begin(ring, num_dwords); |
1701 | if (ret) | |
1702 | return ret; | |
1703 | ||
1704 | while (num_dwords--) | |
1705 | intel_ring_emit(ring, MI_NOOP); | |
1706 | ||
1707 | intel_ring_advance(ring); | |
1708 | ||
1709 | return 0; | |
1710 | } | |
1711 | ||
f7e98ad4 | 1712 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1713 | { |
f7e98ad4 | 1714 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1715 | |
1823521d | 1716 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1717 | |
f7e98ad4 MK |
1718 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1719 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1720 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1721 | if (HAS_VEBOX(ring->dev)) |
1722 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1723 | } |
d97ed339 | 1724 | |
f7e98ad4 | 1725 | ring->set_seqno(ring, seqno); |
92cab734 | 1726 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1727 | } |
62fdfeaf | 1728 | |
78501eac | 1729 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1730 | u32 value) |
881f47b6 | 1731 | { |
4640c4ff | 1732 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1733 | |
1734 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1735 | |
1736 | /* Disable notification that the ring is IDLE. The GT | |
1737 | * will then assume that it is busy and bring it out of rc6. | |
1738 | */ | |
0206e353 | 1739 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1740 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1741 | ||
1742 | /* Clear the context id. Here be magic! */ | |
1743 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1744 | |
12f55818 | 1745 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1746 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1747 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1748 | 50)) | |
1749 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1750 | |
12f55818 | 1751 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1752 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1753 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1754 | ||
1755 | /* Let the ring send IDLE messages to the GT again, | |
1756 | * and so let it sleep to conserve power when idle. | |
1757 | */ | |
0206e353 | 1758 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1759 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1760 | } |
1761 | ||
ea251324 BW |
1762 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1763 | u32 invalidate, u32 flush) | |
881f47b6 | 1764 | { |
71a77e07 | 1765 | uint32_t cmd; |
b72f3acb CW |
1766 | int ret; |
1767 | ||
b72f3acb CW |
1768 | ret = intel_ring_begin(ring, 4); |
1769 | if (ret) | |
1770 | return ret; | |
1771 | ||
71a77e07 | 1772 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1773 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1774 | cmd += 1; | |
9a289771 JB |
1775 | /* |
1776 | * Bspec vol 1c.5 - video engine command streamer: | |
1777 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1778 | * operation is complete. This bit is only valid when the | |
1779 | * Post-Sync Operation field is a value of 1h or 3h." | |
1780 | */ | |
71a77e07 | 1781 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1782 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1783 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1784 | intel_ring_emit(ring, cmd); |
9a289771 | 1785 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1786 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1787 | intel_ring_emit(ring, 0); /* upper addr */ | |
1788 | intel_ring_emit(ring, 0); /* value */ | |
1789 | } else { | |
1790 | intel_ring_emit(ring, 0); | |
1791 | intel_ring_emit(ring, MI_NOOP); | |
1792 | } | |
b72f3acb CW |
1793 | intel_ring_advance(ring); |
1794 | return 0; | |
881f47b6 XH |
1795 | } |
1796 | ||
1c7a0623 BW |
1797 | static int |
1798 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1799 | u32 offset, u32 len, | |
1800 | unsigned flags) | |
1801 | { | |
28cf5415 BW |
1802 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1803 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
1804 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
1805 | int ret; |
1806 | ||
1807 | ret = intel_ring_begin(ring, 4); | |
1808 | if (ret) | |
1809 | return ret; | |
1810 | ||
1811 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 1812 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
1c7a0623 BW |
1813 | intel_ring_emit(ring, offset); |
1814 | intel_ring_emit(ring, 0); | |
1815 | intel_ring_emit(ring, MI_NOOP); | |
1816 | intel_ring_advance(ring); | |
1817 | ||
1818 | return 0; | |
1819 | } | |
1820 | ||
d7d4eedd CW |
1821 | static int |
1822 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1823 | u32 offset, u32 len, | |
1824 | unsigned flags) | |
1825 | { | |
1826 | int ret; | |
1827 | ||
1828 | ret = intel_ring_begin(ring, 2); | |
1829 | if (ret) | |
1830 | return ret; | |
1831 | ||
1832 | intel_ring_emit(ring, | |
1833 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1834 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1835 | /* bit0-7 is the length on GEN6+ */ | |
1836 | intel_ring_emit(ring, offset); | |
1837 | intel_ring_advance(ring); | |
1838 | ||
1839 | return 0; | |
1840 | } | |
1841 | ||
881f47b6 | 1842 | static int |
78501eac | 1843 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1844 | u32 offset, u32 len, |
1845 | unsigned flags) | |
881f47b6 | 1846 | { |
0206e353 | 1847 | int ret; |
ab6f8e32 | 1848 | |
0206e353 AJ |
1849 | ret = intel_ring_begin(ring, 2); |
1850 | if (ret) | |
1851 | return ret; | |
e1f99ce6 | 1852 | |
d7d4eedd CW |
1853 | intel_ring_emit(ring, |
1854 | MI_BATCH_BUFFER_START | | |
1855 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1856 | /* bit0-7 is the length on GEN6+ */ |
1857 | intel_ring_emit(ring, offset); | |
1858 | intel_ring_advance(ring); | |
ab6f8e32 | 1859 | |
0206e353 | 1860 | return 0; |
881f47b6 XH |
1861 | } |
1862 | ||
549f7365 CW |
1863 | /* Blitter support (SandyBridge+) */ |
1864 | ||
ea251324 BW |
1865 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1866 | u32 invalidate, u32 flush) | |
8d19215b | 1867 | { |
fd3da6c9 | 1868 | struct drm_device *dev = ring->dev; |
71a77e07 | 1869 | uint32_t cmd; |
b72f3acb CW |
1870 | int ret; |
1871 | ||
6a233c78 | 1872 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1873 | if (ret) |
1874 | return ret; | |
1875 | ||
71a77e07 | 1876 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1877 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1878 | cmd += 1; | |
9a289771 JB |
1879 | /* |
1880 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1881 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1882 | * operation is complete. This bit is only valid when the | |
1883 | * Post-Sync Operation field is a value of 1h or 3h." | |
1884 | */ | |
71a77e07 | 1885 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1886 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1887 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1888 | intel_ring_emit(ring, cmd); |
9a289771 | 1889 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1890 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1891 | intel_ring_emit(ring, 0); /* upper addr */ | |
1892 | intel_ring_emit(ring, 0); /* value */ | |
1893 | } else { | |
1894 | intel_ring_emit(ring, 0); | |
1895 | intel_ring_emit(ring, MI_NOOP); | |
1896 | } | |
b72f3acb | 1897 | intel_ring_advance(ring); |
fd3da6c9 | 1898 | |
9688ecad | 1899 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
1900 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
1901 | ||
b72f3acb | 1902 | return 0; |
8d19215b ZN |
1903 | } |
1904 | ||
5c1143bb XH |
1905 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1906 | { | |
4640c4ff | 1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 1908 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1909 | |
59465b5f DV |
1910 | ring->name = "render ring"; |
1911 | ring->id = RCS; | |
1912 | ring->mmio_base = RENDER_RING_BASE; | |
1913 | ||
1ec14ad3 CW |
1914 | if (INTEL_INFO(dev)->gen >= 6) { |
1915 | ring->add_request = gen6_add_request; | |
4772eaeb | 1916 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1917 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1918 | ring->flush = gen6_render_ring_flush; |
abd58f01 | 1919 | if (INTEL_INFO(dev)->gen >= 8) { |
a5f3d68e | 1920 | ring->flush = gen8_render_ring_flush; |
abd58f01 BW |
1921 | ring->irq_get = gen8_ring_get_irq; |
1922 | ring->irq_put = gen8_ring_put_irq; | |
1923 | } else { | |
1924 | ring->irq_get = gen6_ring_get_irq; | |
1925 | ring->irq_put = gen6_ring_put_irq; | |
1926 | } | |
cc609d5d | 1927 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1928 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1929 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1930 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1931 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1932 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1933 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1934 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1935 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1936 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1937 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1938 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1939 | } else if (IS_GEN5(dev)) { |
1940 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1941 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1942 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1943 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1944 | ring->irq_get = gen5_ring_get_irq; |
1945 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1946 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1947 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1948 | } else { |
8620a3a9 | 1949 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1950 | if (INTEL_INFO(dev)->gen < 4) |
1951 | ring->flush = gen2_render_ring_flush; | |
1952 | else | |
1953 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1954 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1955 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1956 | if (IS_GEN2(dev)) { |
1957 | ring->irq_get = i8xx_ring_get_irq; | |
1958 | ring->irq_put = i8xx_ring_put_irq; | |
1959 | } else { | |
1960 | ring->irq_get = i9xx_ring_get_irq; | |
1961 | ring->irq_put = i9xx_ring_put_irq; | |
1962 | } | |
e3670319 | 1963 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1964 | } |
59465b5f | 1965 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1966 | if (IS_HASWELL(dev)) |
1967 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
1968 | else if (IS_GEN8(dev)) |
1969 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 1970 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
1971 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1972 | else if (INTEL_INFO(dev)->gen >= 4) | |
1973 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1974 | else if (IS_I830(dev) || IS_845G(dev)) | |
1975 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1976 | else | |
1977 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1978 | ring->init = init_render_ring; |
1979 | ring->cleanup = render_ring_cleanup; | |
1980 | ||
b45305fc DV |
1981 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1982 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1983 | struct drm_i915_gem_object *obj; | |
1984 | int ret; | |
1985 | ||
1986 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1987 | if (obj == NULL) { | |
1988 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1989 | return -ENOMEM; | |
1990 | } | |
1991 | ||
be1fa129 | 1992 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
1993 | if (ret != 0) { |
1994 | drm_gem_object_unreference(&obj->base); | |
1995 | DRM_ERROR("Failed to ping batch bo\n"); | |
1996 | return ret; | |
1997 | } | |
1998 | ||
0d1aacac CW |
1999 | ring->scratch.obj = obj; |
2000 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2001 | } |
2002 | ||
1ec14ad3 | 2003 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2004 | } |
2005 | ||
e8616b6c CW |
2006 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2007 | { | |
4640c4ff | 2008 | struct drm_i915_private *dev_priv = dev->dev_private; |
e8616b6c | 2009 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
6b8294a4 | 2010 | int ret; |
e8616b6c | 2011 | |
59465b5f DV |
2012 | ring->name = "render ring"; |
2013 | ring->id = RCS; | |
2014 | ring->mmio_base = RENDER_RING_BASE; | |
2015 | ||
e8616b6c | 2016 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
2017 | /* non-kms not supported on gen6+ */ |
2018 | return -ENODEV; | |
e8616b6c | 2019 | } |
28f0cbf7 DV |
2020 | |
2021 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2022 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2023 | * the special gen5 functions. */ | |
2024 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2025 | if (INTEL_INFO(dev)->gen < 4) |
2026 | ring->flush = gen2_render_ring_flush; | |
2027 | else | |
2028 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2029 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2030 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2031 | if (IS_GEN2(dev)) { |
2032 | ring->irq_get = i8xx_ring_get_irq; | |
2033 | ring->irq_put = i8xx_ring_put_irq; | |
2034 | } else { | |
2035 | ring->irq_get = i9xx_ring_get_irq; | |
2036 | ring->irq_put = i9xx_ring_put_irq; | |
2037 | } | |
28f0cbf7 | 2038 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2039 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2040 | if (INTEL_INFO(dev)->gen >= 4) |
2041 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2042 | else if (IS_I830(dev) || IS_845G(dev)) | |
2043 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2044 | else | |
2045 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2046 | ring->init = init_render_ring; |
2047 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2048 | |
2049 | ring->dev = dev; | |
2050 | INIT_LIST_HEAD(&ring->active_list); | |
2051 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
2052 | |
2053 | ring->size = size; | |
2054 | ring->effective_size = ring->size; | |
17f10fdc | 2055 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
18393f63 | 2056 | ring->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2057 | |
4225d0f2 DV |
2058 | ring->virtual_start = ioremap_wc(start, size); |
2059 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
2060 | DRM_ERROR("can not ioremap virtual address for" |
2061 | " ring buffer\n"); | |
2062 | return -ENOMEM; | |
2063 | } | |
2064 | ||
6b8294a4 | 2065 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2066 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
2067 | if (ret) |
2068 | return ret; | |
2069 | } | |
2070 | ||
e8616b6c CW |
2071 | return 0; |
2072 | } | |
2073 | ||
5c1143bb XH |
2074 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2075 | { | |
4640c4ff | 2076 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 2077 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2078 | |
58fa3835 DV |
2079 | ring->name = "bsd ring"; |
2080 | ring->id = VCS; | |
2081 | ||
0fd2c201 | 2082 | ring->write_tail = ring_write_tail; |
780f18c8 | 2083 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2084 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2085 | /* gen6 bsd needs a special wa for tail updates */ |
2086 | if (IS_GEN6(dev)) | |
2087 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2088 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2089 | ring->add_request = gen6_add_request; |
2090 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2091 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2092 | if (INTEL_INFO(dev)->gen >= 8) { |
2093 | ring->irq_enable_mask = | |
2094 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2095 | ring->irq_get = gen8_ring_get_irq; | |
2096 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2097 | ring->dispatch_execbuffer = |
2098 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
2099 | } else { |
2100 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2101 | ring->irq_get = gen6_ring_get_irq; | |
2102 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2103 | ring->dispatch_execbuffer = |
2104 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2105 | } |
686cb5f9 | 2106 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2107 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2108 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2109 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 2110 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
2111 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2112 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
2113 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 2114 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
2115 | } else { |
2116 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2117 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2118 | ring->add_request = i9xx_add_request; |
58fa3835 | 2119 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2120 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2121 | if (IS_GEN5(dev)) { |
cc609d5d | 2122 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2123 | ring->irq_get = gen5_ring_get_irq; |
2124 | ring->irq_put = gen5_ring_put_irq; | |
2125 | } else { | |
e3670319 | 2126 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2127 | ring->irq_get = i9xx_ring_get_irq; |
2128 | ring->irq_put = i9xx_ring_put_irq; | |
2129 | } | |
fb3256da | 2130 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2131 | } |
2132 | ring->init = init_ring_common; | |
2133 | ||
1ec14ad3 | 2134 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2135 | } |
549f7365 CW |
2136 | |
2137 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
2138 | { | |
4640c4ff | 2139 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 2140 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 2141 | |
3535d9dd DV |
2142 | ring->name = "blitter ring"; |
2143 | ring->id = BCS; | |
2144 | ||
2145 | ring->mmio_base = BLT_RING_BASE; | |
2146 | ring->write_tail = ring_write_tail; | |
ea251324 | 2147 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2148 | ring->add_request = gen6_add_request; |
2149 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2150 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2151 | if (INTEL_INFO(dev)->gen >= 8) { |
2152 | ring->irq_enable_mask = | |
2153 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2154 | ring->irq_get = gen8_ring_get_irq; | |
2155 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2156 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2157 | } else { |
2158 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2159 | ring->irq_get = gen6_ring_get_irq; | |
2160 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2161 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2162 | } |
686cb5f9 | 2163 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2164 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2165 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2166 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 2167 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
2168 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2169 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
2170 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 2171 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 2172 | ring->init = init_ring_common; |
549f7365 | 2173 | |
1ec14ad3 | 2174 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2175 | } |
a7b9761d | 2176 | |
9a8a2213 BW |
2177 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2178 | { | |
4640c4ff | 2179 | struct drm_i915_private *dev_priv = dev->dev_private; |
9a8a2213 BW |
2180 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; |
2181 | ||
2182 | ring->name = "video enhancement ring"; | |
2183 | ring->id = VECS; | |
2184 | ||
2185 | ring->mmio_base = VEBOX_RING_BASE; | |
2186 | ring->write_tail = ring_write_tail; | |
2187 | ring->flush = gen6_ring_flush; | |
2188 | ring->add_request = gen6_add_request; | |
2189 | ring->get_seqno = gen6_ring_get_seqno; | |
2190 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2191 | |
2192 | if (INTEL_INFO(dev)->gen >= 8) { | |
2193 | ring->irq_enable_mask = | |
40c499f9 | 2194 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2195 | ring->irq_get = gen8_ring_get_irq; |
2196 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2197 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2198 | } else { |
2199 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2200 | ring->irq_get = hsw_vebox_get_irq; | |
2201 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2202 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2203 | } |
9a8a2213 BW |
2204 | ring->sync_to = gen6_ring_sync; |
2205 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2206 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2207 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2208 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2209 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
2210 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
2211 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
2212 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
2213 | ring->init = init_ring_common; | |
2214 | ||
2215 | return intel_init_ring_buffer(dev, ring); | |
2216 | } | |
2217 | ||
a7b9761d CW |
2218 | int |
2219 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2220 | { | |
2221 | int ret; | |
2222 | ||
2223 | if (!ring->gpu_caches_dirty) | |
2224 | return 0; | |
2225 | ||
2226 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2227 | if (ret) | |
2228 | return ret; | |
2229 | ||
2230 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2231 | ||
2232 | ring->gpu_caches_dirty = false; | |
2233 | return 0; | |
2234 | } | |
2235 | ||
2236 | int | |
2237 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2238 | { | |
2239 | uint32_t flush_domains; | |
2240 | int ret; | |
2241 | ||
2242 | flush_domains = 0; | |
2243 | if (ring->gpu_caches_dirty) | |
2244 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2245 | ||
2246 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2247 | if (ret) | |
2248 | return ret; | |
2249 | ||
2250 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2251 | ||
2252 | ring->gpu_caches_dirty = false; | |
2253 | return 0; | |
2254 | } |