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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
70eac33e CW |
112 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
113 | (IS_G4X(dev) || IS_GEN5(dev))) | |
114 | cmd |= MI_INVALIDATE_ISP; | |
115 | ||
62fdfeaf EA |
116 | #if WATCH_EXEC |
117 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
118 | #endif | |
e1f99ce6 CW |
119 | if (intel_ring_begin(ring, 2) == 0) { |
120 | intel_ring_emit(ring, cmd); | |
121 | intel_ring_emit(ring, MI_NOOP); | |
122 | intel_ring_advance(ring); | |
123 | } | |
62fdfeaf | 124 | } |
8187a2b7 ZN |
125 | } |
126 | ||
78501eac | 127 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 128 | u32 value) |
d46eefa2 | 129 | { |
78501eac | 130 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 131 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
132 | } |
133 | ||
78501eac | 134 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 135 | { |
78501eac CW |
136 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
137 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 138 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
139 | |
140 | return I915_READ(acthd_reg); | |
141 | } | |
142 | ||
78501eac | 143 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 144 | { |
78501eac | 145 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 146 | struct drm_i915_gem_object *obj = ring->obj; |
8187a2b7 | 147 | u32 head; |
8187a2b7 ZN |
148 | |
149 | /* Stop the ring if it's running. */ | |
7f2ab699 | 150 | I915_WRITE_CTL(ring, 0); |
570ef608 | 151 | I915_WRITE_HEAD(ring, 0); |
78501eac | 152 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
153 | |
154 | /* Initialize the ring. */ | |
05394f39 | 155 | I915_WRITE_START(ring, obj->gtt_offset); |
570ef608 | 156 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
157 | |
158 | /* G45 ring initialization fails to reset head to zero */ | |
159 | if (head != 0) { | |
6fd0d56e CW |
160 | DRM_DEBUG_KMS("%s head not reset to zero " |
161 | "ctl %08x head %08x tail %08x start %08x\n", | |
162 | ring->name, | |
163 | I915_READ_CTL(ring), | |
164 | I915_READ_HEAD(ring), | |
165 | I915_READ_TAIL(ring), | |
166 | I915_READ_START(ring)); | |
8187a2b7 | 167 | |
570ef608 | 168 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 169 | |
6fd0d56e CW |
170 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
171 | DRM_ERROR("failed to set %s head to zero " | |
172 | "ctl %08x head %08x tail %08x start %08x\n", | |
173 | ring->name, | |
174 | I915_READ_CTL(ring), | |
175 | I915_READ_HEAD(ring), | |
176 | I915_READ_TAIL(ring), | |
177 | I915_READ_START(ring)); | |
178 | } | |
8187a2b7 ZN |
179 | } |
180 | ||
7f2ab699 | 181 | I915_WRITE_CTL(ring, |
ae69b42a | 182 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
6aa56062 | 183 | | RING_REPORT_64K | RING_VALID); |
8187a2b7 | 184 | |
8187a2b7 | 185 | /* If the head is still not zero, the ring is dead */ |
176f28eb | 186 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
05394f39 | 187 | I915_READ_START(ring) != obj->gtt_offset || |
176f28eb | 188 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
e74cfed5 CW |
189 | DRM_ERROR("%s initialization failed " |
190 | "ctl %08x head %08x tail %08x start %08x\n", | |
191 | ring->name, | |
192 | I915_READ_CTL(ring), | |
193 | I915_READ_HEAD(ring), | |
194 | I915_READ_TAIL(ring), | |
195 | I915_READ_START(ring)); | |
196 | return -EIO; | |
8187a2b7 ZN |
197 | } |
198 | ||
78501eac CW |
199 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
200 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 201 | else { |
570ef608 | 202 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 203 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
204 | ring->space = ring->head - (ring->tail + 8); |
205 | if (ring->space < 0) | |
206 | ring->space += ring->size; | |
207 | } | |
1ec14ad3 | 208 | |
8187a2b7 ZN |
209 | return 0; |
210 | } | |
211 | ||
78501eac | 212 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 213 | { |
78501eac | 214 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 215 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 216 | int ret = init_ring_common(ring); |
a69ffdbf | 217 | |
a6c45cf0 | 218 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac | 219 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
a69ffdbf ZW |
220 | if (IS_GEN6(dev)) |
221 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
222 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 223 | } |
78501eac | 224 | |
8187a2b7 ZN |
225 | return ret; |
226 | } | |
227 | ||
1ec14ad3 CW |
228 | static void |
229 | update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno) | |
230 | { | |
231 | struct drm_device *dev = ring->dev; | |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | int id; | |
234 | ||
235 | /* | |
236 | * cs -> 1 = vcs, 0 = bcs | |
237 | * vcs -> 1 = bcs, 0 = cs, | |
238 | * bcs -> 1 = cs, 0 = vcs. | |
239 | */ | |
240 | id = ring - dev_priv->ring; | |
241 | id += 2 - i; | |
242 | id %= 3; | |
243 | ||
244 | intel_ring_emit(ring, | |
245 | MI_SEMAPHORE_MBOX | | |
246 | MI_SEMAPHORE_REGISTER | | |
247 | MI_SEMAPHORE_UPDATE); | |
248 | intel_ring_emit(ring, seqno); | |
249 | intel_ring_emit(ring, | |
250 | RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i); | |
251 | } | |
252 | ||
253 | static int | |
254 | gen6_add_request(struct intel_ring_buffer *ring, | |
255 | u32 *result) | |
256 | { | |
257 | u32 seqno; | |
258 | int ret; | |
259 | ||
260 | ret = intel_ring_begin(ring, 10); | |
261 | if (ret) | |
262 | return ret; | |
263 | ||
264 | seqno = i915_gem_get_seqno(ring->dev); | |
265 | update_semaphore(ring, 0, seqno); | |
266 | update_semaphore(ring, 1, seqno); | |
267 | ||
268 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
269 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
270 | intel_ring_emit(ring, seqno); | |
271 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
272 | intel_ring_advance(ring); | |
273 | ||
274 | *result = seqno; | |
275 | return 0; | |
276 | } | |
277 | ||
278 | int | |
279 | intel_ring_sync(struct intel_ring_buffer *ring, | |
280 | struct intel_ring_buffer *to, | |
281 | u32 seqno) | |
282 | { | |
283 | int ret; | |
284 | ||
285 | ret = intel_ring_begin(ring, 4); | |
286 | if (ret) | |
287 | return ret; | |
288 | ||
289 | intel_ring_emit(ring, | |
290 | MI_SEMAPHORE_MBOX | | |
291 | MI_SEMAPHORE_REGISTER | | |
292 | intel_ring_sync_index(ring, to) << 17 | | |
293 | MI_SEMAPHORE_COMPARE); | |
294 | intel_ring_emit(ring, seqno); | |
295 | intel_ring_emit(ring, 0); | |
296 | intel_ring_emit(ring, MI_NOOP); | |
297 | intel_ring_advance(ring); | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
1ec14ad3 CW |
302 | static int |
303 | render_ring_add_request(struct intel_ring_buffer *ring, | |
304 | u32 *result) | |
305 | { | |
306 | struct drm_device *dev = ring->dev; | |
307 | u32 seqno = i915_gem_get_seqno(dev); | |
308 | int ret; | |
3cce469c | 309 | |
1ec14ad3 CW |
310 | ret = intel_ring_begin(ring, 4); |
311 | if (ret) | |
312 | return ret; | |
3cce469c | 313 | |
1ec14ad3 CW |
314 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
315 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
316 | intel_ring_emit(ring, seqno); | |
317 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
3cce469c | 318 | intel_ring_advance(ring); |
1ec14ad3 | 319 | |
3cce469c CW |
320 | *result = seqno; |
321 | return 0; | |
62fdfeaf EA |
322 | } |
323 | ||
8187a2b7 | 324 | static u32 |
1ec14ad3 | 325 | ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 326 | { |
1ec14ad3 CW |
327 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
328 | } | |
329 | ||
b13c2b96 | 330 | static bool |
1ec14ad3 | 331 | render_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 332 | { |
78501eac | 333 | struct drm_device *dev = ring->dev; |
62fdfeaf | 334 | |
b13c2b96 CW |
335 | if (!dev->irq_enabled) |
336 | return false; | |
337 | ||
338 | if (atomic_inc_return(&ring->irq_refcount) == 1) { | |
1ec14ad3 CW |
339 | drm_i915_private_t *dev_priv = dev->dev_private; |
340 | unsigned long irqflags; | |
341 | ||
342 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
62fdfeaf | 343 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 344 | ironlake_enable_graphics_irq(dev_priv, |
88f23b8f | 345 | GT_USER_INTERRUPT); |
62fdfeaf EA |
346 | else |
347 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
1ec14ad3 | 348 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
62fdfeaf | 349 | } |
b13c2b96 CW |
350 | |
351 | return true; | |
62fdfeaf EA |
352 | } |
353 | ||
8187a2b7 | 354 | static void |
1ec14ad3 | 355 | render_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 356 | { |
78501eac | 357 | struct drm_device *dev = ring->dev; |
62fdfeaf | 358 | |
b13c2b96 | 359 | if (atomic_dec_and_test(&ring->irq_refcount)) { |
1ec14ad3 CW |
360 | drm_i915_private_t *dev_priv = dev->dev_private; |
361 | unsigned long irqflags; | |
362 | ||
363 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
62fdfeaf | 364 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 365 | ironlake_disable_graphics_irq(dev_priv, |
88f23b8f | 366 | GT_USER_INTERRUPT); |
62fdfeaf EA |
367 | else |
368 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
1ec14ad3 | 369 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
62fdfeaf | 370 | } |
62fdfeaf EA |
371 | } |
372 | ||
78501eac | 373 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 374 | { |
78501eac CW |
375 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
376 | u32 mmio = IS_GEN6(ring->dev) ? | |
377 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
378 | RING_HWS_PGA(ring->mmio_base); | |
379 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
380 | POSTING_READ(mmio); | |
8187a2b7 ZN |
381 | } |
382 | ||
ab6f8e32 | 383 | static void |
78501eac CW |
384 | bsd_ring_flush(struct intel_ring_buffer *ring, |
385 | u32 invalidate_domains, | |
386 | u32 flush_domains) | |
d1b851fc | 387 | { |
1ec14ad3 CW |
388 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
389 | return; | |
390 | ||
e1f99ce6 CW |
391 | if (intel_ring_begin(ring, 2) == 0) { |
392 | intel_ring_emit(ring, MI_FLUSH); | |
393 | intel_ring_emit(ring, MI_NOOP); | |
394 | intel_ring_advance(ring); | |
395 | } | |
d1b851fc ZN |
396 | } |
397 | ||
3cce469c | 398 | static int |
78501eac | 399 | ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 400 | u32 *result) |
d1b851fc ZN |
401 | { |
402 | u32 seqno; | |
3cce469c CW |
403 | int ret; |
404 | ||
405 | ret = intel_ring_begin(ring, 4); | |
406 | if (ret) | |
407 | return ret; | |
6f392d54 | 408 | |
78501eac | 409 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 410 | |
3cce469c CW |
411 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
412 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
413 | intel_ring_emit(ring, seqno); | |
414 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
415 | intel_ring_advance(ring); | |
d1b851fc ZN |
416 | |
417 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
3cce469c CW |
418 | *result = seqno; |
419 | return 0; | |
d1b851fc ZN |
420 | } |
421 | ||
b13c2b96 | 422 | static bool |
1ec14ad3 | 423 | ring_get_irq(struct intel_ring_buffer *ring, u32 flag) |
d1b851fc | 424 | { |
1ec14ad3 CW |
425 | struct drm_device *dev = ring->dev; |
426 | ||
b13c2b96 CW |
427 | if (!dev->irq_enabled) |
428 | return false; | |
429 | ||
430 | if (atomic_inc_return(&ring->irq_refcount) == 1) { | |
1ec14ad3 CW |
431 | drm_i915_private_t *dev_priv = dev->dev_private; |
432 | unsigned long irqflags; | |
433 | ||
434 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
435 | ironlake_enable_graphics_irq(dev_priv, flag); | |
436 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
437 | } | |
b13c2b96 CW |
438 | |
439 | return true; | |
d1b851fc | 440 | } |
1ec14ad3 | 441 | |
d1b851fc | 442 | static void |
1ec14ad3 | 443 | ring_put_irq(struct intel_ring_buffer *ring, u32 flag) |
d1b851fc | 444 | { |
1ec14ad3 CW |
445 | struct drm_device *dev = ring->dev; |
446 | ||
b13c2b96 | 447 | if (atomic_dec_and_test(&ring->irq_refcount)) { |
1ec14ad3 CW |
448 | drm_i915_private_t *dev_priv = dev->dev_private; |
449 | unsigned long irqflags; | |
450 | ||
451 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
452 | ironlake_disable_graphics_irq(dev_priv, flag); | |
453 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
454 | } | |
d1b851fc ZN |
455 | } |
456 | ||
b13c2b96 | 457 | static bool |
1ec14ad3 | 458 | bsd_ring_get_irq(struct intel_ring_buffer *ring) |
d1b851fc | 459 | { |
b13c2b96 | 460 | return ring_get_irq(ring, GT_BSD_USER_INTERRUPT); |
1ec14ad3 CW |
461 | } |
462 | static void | |
463 | bsd_ring_put_irq(struct intel_ring_buffer *ring) | |
464 | { | |
b13c2b96 | 465 | ring_put_irq(ring, GT_BSD_USER_INTERRUPT); |
d1b851fc ZN |
466 | } |
467 | ||
468 | static int | |
c4e7a414 | 469 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 470 | { |
e1f99ce6 | 471 | int ret; |
78501eac | 472 | |
e1f99ce6 CW |
473 | ret = intel_ring_begin(ring, 2); |
474 | if (ret) | |
475 | return ret; | |
476 | ||
78501eac | 477 | intel_ring_emit(ring, |
c4e7a414 | 478 | MI_BATCH_BUFFER_START | (2 << 6) | |
78501eac | 479 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 480 | intel_ring_emit(ring, offset); |
78501eac CW |
481 | intel_ring_advance(ring); |
482 | ||
d1b851fc ZN |
483 | return 0; |
484 | } | |
485 | ||
8187a2b7 | 486 | static int |
78501eac | 487 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 488 | u32 offset, u32 len) |
62fdfeaf | 489 | { |
78501eac | 490 | struct drm_device *dev = ring->dev; |
62fdfeaf | 491 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4e7a414 | 492 | int ret; |
62fdfeaf | 493 | |
6f392d54 | 494 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf | 495 | |
c4e7a414 CW |
496 | if (IS_I830(dev) || IS_845G(dev)) { |
497 | ret = intel_ring_begin(ring, 4); | |
498 | if (ret) | |
499 | return ret; | |
62fdfeaf | 500 | |
c4e7a414 CW |
501 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
502 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
503 | intel_ring_emit(ring, offset + len - 8); | |
504 | intel_ring_emit(ring, 0); | |
505 | } else { | |
506 | ret = intel_ring_begin(ring, 2); | |
507 | if (ret) | |
508 | return ret; | |
e1f99ce6 | 509 | |
c4e7a414 CW |
510 | if (INTEL_INFO(dev)->gen >= 4) { |
511 | intel_ring_emit(ring, | |
512 | MI_BATCH_BUFFER_START | (2 << 6) | | |
513 | MI_BATCH_NON_SECURE_I965); | |
514 | intel_ring_emit(ring, offset); | |
62fdfeaf | 515 | } else { |
c4e7a414 CW |
516 | intel_ring_emit(ring, |
517 | MI_BATCH_BUFFER_START | (2 << 6)); | |
518 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
62fdfeaf EA |
519 | } |
520 | } | |
c4e7a414 | 521 | intel_ring_advance(ring); |
62fdfeaf | 522 | |
62fdfeaf EA |
523 | return 0; |
524 | } | |
525 | ||
78501eac | 526 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 527 | { |
78501eac | 528 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 529 | struct drm_i915_gem_object *obj; |
62fdfeaf | 530 | |
8187a2b7 ZN |
531 | obj = ring->status_page.obj; |
532 | if (obj == NULL) | |
62fdfeaf | 533 | return; |
62fdfeaf | 534 | |
05394f39 | 535 | kunmap(obj->pages[0]); |
62fdfeaf | 536 | i915_gem_object_unpin(obj); |
05394f39 | 537 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 538 | ring->status_page.obj = NULL; |
62fdfeaf EA |
539 | |
540 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
541 | } |
542 | ||
78501eac | 543 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 544 | { |
78501eac | 545 | struct drm_device *dev = ring->dev; |
62fdfeaf | 546 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 547 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
548 | int ret; |
549 | ||
62fdfeaf EA |
550 | obj = i915_gem_alloc_object(dev, 4096); |
551 | if (obj == NULL) { | |
552 | DRM_ERROR("Failed to allocate status page\n"); | |
553 | ret = -ENOMEM; | |
554 | goto err; | |
555 | } | |
05394f39 | 556 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
62fdfeaf | 557 | |
75e9e915 | 558 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 559 | if (ret != 0) { |
62fdfeaf EA |
560 | goto err_unref; |
561 | } | |
562 | ||
05394f39 CW |
563 | ring->status_page.gfx_addr = obj->gtt_offset; |
564 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 565 | if (ring->status_page.page_addr == NULL) { |
62fdfeaf | 566 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
567 | goto err_unpin; |
568 | } | |
8187a2b7 ZN |
569 | ring->status_page.obj = obj; |
570 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 571 | |
78501eac | 572 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
573 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
574 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
575 | |
576 | return 0; | |
577 | ||
578 | err_unpin: | |
579 | i915_gem_object_unpin(obj); | |
580 | err_unref: | |
05394f39 | 581 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 582 | err: |
8187a2b7 | 583 | return ret; |
62fdfeaf EA |
584 | } |
585 | ||
8187a2b7 | 586 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 587 | struct intel_ring_buffer *ring) |
62fdfeaf | 588 | { |
05394f39 | 589 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
590 | int ret; |
591 | ||
8187a2b7 | 592 | ring->dev = dev; |
23bc5982 CW |
593 | INIT_LIST_HEAD(&ring->active_list); |
594 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 595 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 596 | |
8187a2b7 | 597 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 598 | ret = init_status_page(ring); |
8187a2b7 ZN |
599 | if (ret) |
600 | return ret; | |
601 | } | |
62fdfeaf | 602 | |
8187a2b7 | 603 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
604 | if (obj == NULL) { |
605 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 606 | ret = -ENOMEM; |
dd785e35 | 607 | goto err_hws; |
62fdfeaf | 608 | } |
62fdfeaf | 609 | |
05394f39 | 610 | ring->obj = obj; |
8187a2b7 | 611 | |
75e9e915 | 612 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
613 | if (ret) |
614 | goto err_unref; | |
62fdfeaf | 615 | |
8187a2b7 | 616 | ring->map.size = ring->size; |
05394f39 | 617 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
62fdfeaf EA |
618 | ring->map.type = 0; |
619 | ring->map.flags = 0; | |
620 | ring->map.mtrr = 0; | |
621 | ||
622 | drm_core_ioremap_wc(&ring->map, dev); | |
623 | if (ring->map.handle == NULL) { | |
624 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 625 | ret = -EINVAL; |
dd785e35 | 626 | goto err_unpin; |
62fdfeaf EA |
627 | } |
628 | ||
8187a2b7 | 629 | ring->virtual_start = ring->map.handle; |
78501eac | 630 | ret = ring->init(ring); |
dd785e35 CW |
631 | if (ret) |
632 | goto err_unmap; | |
62fdfeaf | 633 | |
c584fe47 | 634 | return 0; |
dd785e35 CW |
635 | |
636 | err_unmap: | |
637 | drm_core_ioremapfree(&ring->map, dev); | |
638 | err_unpin: | |
639 | i915_gem_object_unpin(obj); | |
640 | err_unref: | |
05394f39 CW |
641 | drm_gem_object_unreference(&obj->base); |
642 | ring->obj = NULL; | |
dd785e35 | 643 | err_hws: |
78501eac | 644 | cleanup_status_page(ring); |
8187a2b7 | 645 | return ret; |
62fdfeaf EA |
646 | } |
647 | ||
78501eac | 648 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 649 | { |
33626e6a CW |
650 | struct drm_i915_private *dev_priv; |
651 | int ret; | |
652 | ||
05394f39 | 653 | if (ring->obj == NULL) |
62fdfeaf EA |
654 | return; |
655 | ||
33626e6a CW |
656 | /* Disable the ring buffer. The ring must be idle at this point */ |
657 | dev_priv = ring->dev->dev_private; | |
658 | ret = intel_wait_ring_buffer(ring, ring->size - 8); | |
659 | I915_WRITE_CTL(ring, 0); | |
660 | ||
78501eac | 661 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 662 | |
05394f39 CW |
663 | i915_gem_object_unpin(ring->obj); |
664 | drm_gem_object_unreference(&ring->obj->base); | |
665 | ring->obj = NULL; | |
78501eac | 666 | |
8d19215b ZN |
667 | if (ring->cleanup) |
668 | ring->cleanup(ring); | |
669 | ||
78501eac | 670 | cleanup_status_page(ring); |
62fdfeaf EA |
671 | } |
672 | ||
78501eac | 673 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 674 | { |
8187a2b7 | 675 | unsigned int *virt; |
62fdfeaf | 676 | int rem; |
8187a2b7 | 677 | rem = ring->size - ring->tail; |
62fdfeaf | 678 | |
8187a2b7 | 679 | if (ring->space < rem) { |
78501eac | 680 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
681 | if (ret) |
682 | return ret; | |
683 | } | |
62fdfeaf | 684 | |
8187a2b7 | 685 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
686 | rem /= 8; |
687 | while (rem--) { | |
62fdfeaf | 688 | *virt++ = MI_NOOP; |
1741dd4a CW |
689 | *virt++ = MI_NOOP; |
690 | } | |
62fdfeaf | 691 | |
8187a2b7 | 692 | ring->tail = 0; |
43ed340a | 693 | ring->space = ring->head - 8; |
62fdfeaf EA |
694 | |
695 | return 0; | |
696 | } | |
697 | ||
78501eac | 698 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 699 | { |
78501eac | 700 | struct drm_device *dev = ring->dev; |
cae5852d | 701 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 702 | unsigned long end; |
6aa56062 CW |
703 | u32 head; |
704 | ||
62fdfeaf | 705 | trace_i915_ring_wait_begin (dev); |
8187a2b7 ZN |
706 | end = jiffies + 3 * HZ; |
707 | do { | |
8c0a6bfe CW |
708 | /* If the reported head position has wrapped or hasn't advanced, |
709 | * fallback to the slow and accurate path. | |
710 | */ | |
711 | head = intel_read_status_page(ring, 4); | |
712 | if (head < ring->actual_head) | |
713 | head = I915_READ_HEAD(ring); | |
714 | ring->actual_head = head; | |
715 | ring->head = head & HEAD_ADDR; | |
62fdfeaf EA |
716 | ring->space = ring->head - (ring->tail + 8); |
717 | if (ring->space < 0) | |
8187a2b7 | 718 | ring->space += ring->size; |
62fdfeaf | 719 | if (ring->space >= n) { |
78501eac | 720 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
721 | return 0; |
722 | } | |
723 | ||
724 | if (dev->primary->master) { | |
725 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
726 | if (master_priv->sarea_priv) | |
727 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
728 | } | |
d1b851fc | 729 | |
e60a0b10 | 730 | msleep(1); |
f4e0b29b CW |
731 | if (atomic_read(&dev_priv->mm.wedged)) |
732 | return -EAGAIN; | |
8187a2b7 ZN |
733 | } while (!time_after(jiffies, end)); |
734 | trace_i915_ring_wait_end (dev); | |
735 | return -EBUSY; | |
736 | } | |
62fdfeaf | 737 | |
e1f99ce6 CW |
738 | int intel_ring_begin(struct intel_ring_buffer *ring, |
739 | int num_dwords) | |
8187a2b7 | 740 | { |
be26a10b | 741 | int n = 4*num_dwords; |
e1f99ce6 | 742 | int ret; |
78501eac | 743 | |
e1f99ce6 CW |
744 | if (unlikely(ring->tail + n > ring->size)) { |
745 | ret = intel_wrap_ring_buffer(ring); | |
746 | if (unlikely(ret)) | |
747 | return ret; | |
748 | } | |
78501eac | 749 | |
e1f99ce6 CW |
750 | if (unlikely(ring->space < n)) { |
751 | ret = intel_wait_ring_buffer(ring, n); | |
752 | if (unlikely(ret)) | |
753 | return ret; | |
754 | } | |
d97ed339 CW |
755 | |
756 | ring->space -= n; | |
e1f99ce6 | 757 | return 0; |
8187a2b7 | 758 | } |
62fdfeaf | 759 | |
78501eac | 760 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 761 | { |
d97ed339 | 762 | ring->tail &= ring->size - 1; |
78501eac | 763 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 764 | } |
62fdfeaf | 765 | |
e070868e | 766 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 767 | .name = "render ring", |
9220434a | 768 | .id = RING_RENDER, |
333e9fe9 | 769 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 770 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 771 | .init = init_render_ring, |
297b0c5b | 772 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
773 | .flush = render_ring_flush, |
774 | .add_request = render_ring_add_request, | |
1ec14ad3 CW |
775 | .get_seqno = ring_get_seqno, |
776 | .irq_get = render_ring_get_irq, | |
777 | .irq_put = render_ring_put_irq, | |
78501eac | 778 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
8187a2b7 | 779 | }; |
d1b851fc ZN |
780 | |
781 | /* ring buffer for bit-stream decoder */ | |
782 | ||
e070868e | 783 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 784 | .name = "bsd ring", |
9220434a | 785 | .id = RING_BSD, |
333e9fe9 | 786 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 787 | .size = 32 * PAGE_SIZE, |
78501eac | 788 | .init = init_ring_common, |
297b0c5b | 789 | .write_tail = ring_write_tail, |
d1b851fc | 790 | .flush = bsd_ring_flush, |
549f7365 | 791 | .add_request = ring_add_request, |
1ec14ad3 CW |
792 | .get_seqno = ring_get_seqno, |
793 | .irq_get = bsd_ring_get_irq, | |
794 | .irq_put = bsd_ring_put_irq, | |
78501eac | 795 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 796 | }; |
5c1143bb | 797 | |
881f47b6 | 798 | |
78501eac | 799 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 800 | u32 value) |
881f47b6 | 801 | { |
78501eac | 802 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
803 | |
804 | /* Every tail move must follow the sequence below */ | |
805 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
806 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
807 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
808 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
809 | ||
810 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
811 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
812 | 50)) | |
813 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
814 | ||
870e86dd | 815 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
816 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
817 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
818 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
819 | } | |
820 | ||
78501eac | 821 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
822 | u32 invalidate_domains, |
823 | u32 flush_domains) | |
881f47b6 | 824 | { |
1ec14ad3 CW |
825 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
826 | return; | |
827 | ||
e1f99ce6 CW |
828 | if (intel_ring_begin(ring, 4) == 0) { |
829 | intel_ring_emit(ring, MI_FLUSH_DW); | |
830 | intel_ring_emit(ring, 0); | |
831 | intel_ring_emit(ring, 0); | |
832 | intel_ring_emit(ring, 0); | |
833 | intel_ring_advance(ring); | |
834 | } | |
881f47b6 XH |
835 | } |
836 | ||
837 | static int | |
78501eac | 838 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 839 | u32 offset, u32 len) |
881f47b6 | 840 | { |
e1f99ce6 | 841 | int ret; |
ab6f8e32 | 842 | |
e1f99ce6 CW |
843 | ret = intel_ring_begin(ring, 2); |
844 | if (ret) | |
845 | return ret; | |
846 | ||
78501eac | 847 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
ab6f8e32 | 848 | /* bit0-7 is the length on GEN6+ */ |
c4e7a414 | 849 | intel_ring_emit(ring, offset); |
78501eac | 850 | intel_ring_advance(ring); |
ab6f8e32 | 851 | |
881f47b6 XH |
852 | return 0; |
853 | } | |
854 | ||
b13c2b96 | 855 | static bool |
1ec14ad3 CW |
856 | gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring) |
857 | { | |
b13c2b96 | 858 | return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT); |
1ec14ad3 CW |
859 | } |
860 | ||
861 | static void | |
862 | gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) | |
863 | { | |
b13c2b96 | 864 | ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT); |
1ec14ad3 CW |
865 | } |
866 | ||
881f47b6 | 867 | /* ring buffer for Video Codec for Gen6+ */ |
e070868e | 868 | static const struct intel_ring_buffer gen6_bsd_ring = { |
1ec14ad3 CW |
869 | .name = "gen6 bsd ring", |
870 | .id = RING_BSD, | |
871 | .mmio_base = GEN6_BSD_RING_BASE, | |
872 | .size = 32 * PAGE_SIZE, | |
873 | .init = init_ring_common, | |
874 | .write_tail = gen6_bsd_ring_write_tail, | |
875 | .flush = gen6_ring_flush, | |
876 | .add_request = gen6_add_request, | |
877 | .get_seqno = ring_get_seqno, | |
878 | .irq_get = gen6_bsd_ring_get_irq, | |
879 | .irq_put = gen6_bsd_ring_put_irq, | |
880 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, | |
549f7365 CW |
881 | }; |
882 | ||
883 | /* Blitter support (SandyBridge+) */ | |
884 | ||
b13c2b96 | 885 | static bool |
1ec14ad3 | 886 | blt_ring_get_irq(struct intel_ring_buffer *ring) |
549f7365 | 887 | { |
b13c2b96 | 888 | return ring_get_irq(ring, GT_BLT_USER_INTERRUPT); |
549f7365 | 889 | } |
1ec14ad3 | 890 | |
549f7365 | 891 | static void |
1ec14ad3 | 892 | blt_ring_put_irq(struct intel_ring_buffer *ring) |
549f7365 | 893 | { |
b13c2b96 | 894 | ring_put_irq(ring, GT_BLT_USER_INTERRUPT); |
549f7365 CW |
895 | } |
896 | ||
8d19215b ZN |
897 | |
898 | /* Workaround for some stepping of SNB, | |
899 | * each time when BLT engine ring tail moved, | |
900 | * the first command in the ring to be parsed | |
901 | * should be MI_BATCH_BUFFER_START | |
902 | */ | |
903 | #define NEED_BLT_WORKAROUND(dev) \ | |
904 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) | |
905 | ||
906 | static inline struct drm_i915_gem_object * | |
907 | to_blt_workaround(struct intel_ring_buffer *ring) | |
908 | { | |
909 | return ring->private; | |
910 | } | |
911 | ||
912 | static int blt_ring_init(struct intel_ring_buffer *ring) | |
913 | { | |
914 | if (NEED_BLT_WORKAROUND(ring->dev)) { | |
915 | struct drm_i915_gem_object *obj; | |
27153f72 | 916 | u32 *ptr; |
8d19215b ZN |
917 | int ret; |
918 | ||
05394f39 | 919 | obj = i915_gem_alloc_object(ring->dev, 4096); |
8d19215b ZN |
920 | if (obj == NULL) |
921 | return -ENOMEM; | |
922 | ||
05394f39 | 923 | ret = i915_gem_object_pin(obj, 4096, true); |
8d19215b ZN |
924 | if (ret) { |
925 | drm_gem_object_unreference(&obj->base); | |
926 | return ret; | |
927 | } | |
928 | ||
929 | ptr = kmap(obj->pages[0]); | |
27153f72 CW |
930 | *ptr++ = MI_BATCH_BUFFER_END; |
931 | *ptr++ = MI_NOOP; | |
8d19215b ZN |
932 | kunmap(obj->pages[0]); |
933 | ||
05394f39 | 934 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
8d19215b | 935 | if (ret) { |
05394f39 | 936 | i915_gem_object_unpin(obj); |
8d19215b ZN |
937 | drm_gem_object_unreference(&obj->base); |
938 | return ret; | |
939 | } | |
940 | ||
941 | ring->private = obj; | |
942 | } | |
943 | ||
944 | return init_ring_common(ring); | |
945 | } | |
946 | ||
947 | static int blt_ring_begin(struct intel_ring_buffer *ring, | |
948 | int num_dwords) | |
949 | { | |
950 | if (ring->private) { | |
951 | int ret = intel_ring_begin(ring, num_dwords+2); | |
952 | if (ret) | |
953 | return ret; | |
954 | ||
955 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); | |
956 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); | |
957 | ||
958 | return 0; | |
959 | } else | |
960 | return intel_ring_begin(ring, 4); | |
961 | } | |
962 | ||
963 | static void blt_ring_flush(struct intel_ring_buffer *ring, | |
964 | u32 invalidate_domains, | |
965 | u32 flush_domains) | |
966 | { | |
1ec14ad3 CW |
967 | if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0) |
968 | return; | |
969 | ||
8d19215b ZN |
970 | if (blt_ring_begin(ring, 4) == 0) { |
971 | intel_ring_emit(ring, MI_FLUSH_DW); | |
972 | intel_ring_emit(ring, 0); | |
973 | intel_ring_emit(ring, 0); | |
974 | intel_ring_emit(ring, 0); | |
975 | intel_ring_advance(ring); | |
976 | } | |
977 | } | |
978 | ||
8d19215b ZN |
979 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) |
980 | { | |
981 | if (!ring->private) | |
982 | return; | |
983 | ||
984 | i915_gem_object_unpin(ring->private); | |
985 | drm_gem_object_unreference(ring->private); | |
986 | ring->private = NULL; | |
987 | } | |
988 | ||
549f7365 CW |
989 | static const struct intel_ring_buffer gen6_blt_ring = { |
990 | .name = "blt ring", | |
991 | .id = RING_BLT, | |
992 | .mmio_base = BLT_RING_BASE, | |
993 | .size = 32 * PAGE_SIZE, | |
8d19215b | 994 | .init = blt_ring_init, |
297b0c5b | 995 | .write_tail = ring_write_tail, |
8d19215b | 996 | .flush = blt_ring_flush, |
1ec14ad3 CW |
997 | .add_request = gen6_add_request, |
998 | .get_seqno = ring_get_seqno, | |
999 | .irq_get = blt_ring_get_irq, | |
1000 | .irq_put = blt_ring_put_irq, | |
78501eac | 1001 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
8d19215b | 1002 | .cleanup = blt_ring_cleanup, |
881f47b6 XH |
1003 | }; |
1004 | ||
5c1143bb XH |
1005 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1006 | { | |
1007 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1008 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1009 | |
1ec14ad3 CW |
1010 | *ring = render_ring; |
1011 | if (INTEL_INFO(dev)->gen >= 6) { | |
1012 | ring->add_request = gen6_add_request; | |
1ec14ad3 | 1013 | } |
5c1143bb XH |
1014 | |
1015 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1016 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1017 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1018 | } |
1019 | ||
1ec14ad3 | 1020 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1021 | } |
1022 | ||
1023 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
1024 | { | |
1025 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1026 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1027 | |
881f47b6 | 1028 | if (IS_GEN6(dev)) |
1ec14ad3 | 1029 | *ring = gen6_bsd_ring; |
881f47b6 | 1030 | else |
1ec14ad3 | 1031 | *ring = bsd_ring; |
5c1143bb | 1032 | |
1ec14ad3 | 1033 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1034 | } |
549f7365 CW |
1035 | |
1036 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1037 | { | |
1038 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1039 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1040 | |
1ec14ad3 | 1041 | *ring = gen6_blt_ring; |
549f7365 | 1042 | |
1ec14ad3 | 1043 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1044 | } |