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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b5321f30 | 61 | static void __intel_engine_submit(struct intel_engine_cs *engine) |
88b4aa87 | 62 | { |
7e37f889 CW |
63 | struct intel_ring *ring = engine->buffer; |
64 | ||
65 | ring->tail &= ring->size - 1; | |
66 | engine->write_tail(engine, ring->tail); | |
09246732 CW |
67 | } |
68 | ||
b72f3acb | 69 | static int |
a84c3ae1 | 70 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
71 | u32 invalidate_domains, |
72 | u32 flush_domains) | |
73 | { | |
7e37f889 | 74 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
75 | u32 cmd; |
76 | int ret; | |
77 | ||
78 | cmd = MI_FLUSH; | |
31b14c9f | 79 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
80 | cmd |= MI_NO_WRITE_FLUSH; |
81 | ||
82 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
83 | cmd |= MI_READ_FLUSH; | |
84 | ||
5fb9de1a | 85 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
86 | if (ret) |
87 | return ret; | |
88 | ||
b5321f30 CW |
89 | intel_ring_emit(ring, cmd); |
90 | intel_ring_emit(ring, MI_NOOP); | |
91 | intel_ring_advance(ring); | |
46f0f8d1 CW |
92 | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static int | |
a84c3ae1 | 97 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
98 | u32 invalidate_domains, |
99 | u32 flush_domains) | |
62fdfeaf | 100 | { |
7e37f889 | 101 | struct intel_ring *ring = req->ring; |
6f392d54 | 102 | u32 cmd; |
b72f3acb | 103 | int ret; |
6f392d54 | 104 | |
36d527de CW |
105 | /* |
106 | * read/write caches: | |
107 | * | |
108 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
109 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
110 | * also flushed at 2d versus 3d pipeline switches. | |
111 | * | |
112 | * read-only caches: | |
113 | * | |
114 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
115 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
116 | * | |
117 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
118 | * | |
119 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
120 | * invalidated when MI_EXE_FLUSH is set. | |
121 | * | |
122 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
123 | * invalidated with every MI_FLUSH. | |
124 | * | |
125 | * TLBs: | |
126 | * | |
127 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
128 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
129 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
130 | * are flushed at any MI_FLUSH. | |
131 | */ | |
132 | ||
b5321f30 CW |
133 | cmd = MI_FLUSH; |
134 | if (invalidate_domains) { | |
36d527de | 135 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
136 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
137 | cmd |= MI_INVALIDATE_ISP; | |
138 | } | |
70eac33e | 139 | |
5fb9de1a | 140 | ret = intel_ring_begin(req, 2); |
36d527de CW |
141 | if (ret) |
142 | return ret; | |
b72f3acb | 143 | |
b5321f30 CW |
144 | intel_ring_emit(ring, cmd); |
145 | intel_ring_emit(ring, MI_NOOP); | |
146 | intel_ring_advance(ring); | |
b72f3acb CW |
147 | |
148 | return 0; | |
8187a2b7 ZN |
149 | } |
150 | ||
8d315287 JB |
151 | /** |
152 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
153 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
154 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
155 | * | |
156 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
157 | * produced by non-pipelined state commands), software needs to first | |
158 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
159 | * 0. | |
160 | * | |
161 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
162 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
163 | * | |
164 | * And the workaround for these two requires this workaround first: | |
165 | * | |
166 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
167 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
168 | * flushes. | |
169 | * | |
170 | * And this last workaround is tricky because of the requirements on | |
171 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
172 | * volume 2 part 1: | |
173 | * | |
174 | * "1 of the following must also be set: | |
175 | * - Render Target Cache Flush Enable ([12] of DW1) | |
176 | * - Depth Cache Flush Enable ([0] of DW1) | |
177 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
178 | * - Depth Stall ([13] of DW1) | |
179 | * - Post-Sync Operation ([13] of DW1) | |
180 | * - Notify Enable ([8] of DW1)" | |
181 | * | |
182 | * The cache flushes require the workaround flush that triggered this | |
183 | * one, so we can't use it. Depth stall would trigger the same. | |
184 | * Post-sync nonzero is what triggered this second workaround, so we | |
185 | * can't use that one either. Notify enable is IRQs, which aren't | |
186 | * really our business. That leaves only stall at scoreboard. | |
187 | */ | |
188 | static int | |
f2cf1fcc | 189 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 190 | { |
7e37f889 | 191 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
192 | u32 scratch_addr = |
193 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 JB |
194 | int ret; |
195 | ||
5fb9de1a | 196 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
197 | if (ret) |
198 | return ret; | |
199 | ||
b5321f30 CW |
200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
201 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 202 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
204 | intel_ring_emit(ring, 0); /* low dword */ | |
205 | intel_ring_emit(ring, 0); /* high dword */ | |
206 | intel_ring_emit(ring, MI_NOOP); | |
207 | intel_ring_advance(ring); | |
8d315287 | 208 | |
5fb9de1a | 209 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
210 | if (ret) |
211 | return ret; | |
212 | ||
b5321f30 CW |
213 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
214 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
215 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
216 | intel_ring_emit(ring, 0); | |
217 | intel_ring_emit(ring, 0); | |
218 | intel_ring_emit(ring, MI_NOOP); | |
219 | intel_ring_advance(ring); | |
8d315287 JB |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static int | |
a84c3ae1 JH |
225 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
226 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 227 | { |
7e37f889 | 228 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
229 | u32 scratch_addr = |
230 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
8d315287 | 231 | u32 flags = 0; |
8d315287 JB |
232 | int ret; |
233 | ||
b3111509 | 234 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 235 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
236 | if (ret) |
237 | return ret; | |
238 | ||
8d315287 JB |
239 | /* Just flush everything. Experiments have shown that reducing the |
240 | * number of bits based on the write domains has little performance | |
241 | * impact. | |
242 | */ | |
7d54a904 CW |
243 | if (flush_domains) { |
244 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
245 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
246 | /* | |
247 | * Ensure that any following seqno writes only happen | |
248 | * when the render cache is indeed flushed. | |
249 | */ | |
97f209bc | 250 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
251 | } |
252 | if (invalidate_domains) { | |
253 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
254 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
255 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
256 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
257 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
259 | /* | |
260 | * TLB invalidate requires a post-sync write. | |
261 | */ | |
3ac78313 | 262 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 263 | } |
8d315287 | 264 | |
5fb9de1a | 265 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
266 | if (ret) |
267 | return ret; | |
268 | ||
b5321f30 CW |
269 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
270 | intel_ring_emit(ring, flags); | |
271 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
272 | intel_ring_emit(ring, 0); | |
273 | intel_ring_advance(ring); | |
8d315287 JB |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
f3987631 | 278 | static int |
f2cf1fcc | 279 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 280 | { |
7e37f889 | 281 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
282 | int ret; |
283 | ||
5fb9de1a | 284 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
285 | if (ret) |
286 | return ret; | |
287 | ||
b5321f30 CW |
288 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
289 | intel_ring_emit(ring, | |
290 | PIPE_CONTROL_CS_STALL | | |
291 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
292 | intel_ring_emit(ring, 0); | |
293 | intel_ring_emit(ring, 0); | |
294 | intel_ring_advance(ring); | |
f3987631 PZ |
295 | |
296 | return 0; | |
297 | } | |
298 | ||
4772eaeb | 299 | static int |
a84c3ae1 | 300 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
301 | u32 invalidate_domains, u32 flush_domains) |
302 | { | |
7e37f889 | 303 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
304 | u32 scratch_addr = |
305 | req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
4772eaeb | 306 | u32 flags = 0; |
4772eaeb PZ |
307 | int ret; |
308 | ||
f3987631 PZ |
309 | /* |
310 | * Ensure that any following seqno writes only happen when the render | |
311 | * cache is indeed flushed. | |
312 | * | |
313 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
314 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
315 | * don't try to be clever and just set it unconditionally. | |
316 | */ | |
317 | flags |= PIPE_CONTROL_CS_STALL; | |
318 | ||
4772eaeb PZ |
319 | /* Just flush everything. Experiments have shown that reducing the |
320 | * number of bits based on the write domains has little performance | |
321 | * impact. | |
322 | */ | |
323 | if (flush_domains) { | |
324 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
325 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 326 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 327 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
328 | } |
329 | if (invalidate_domains) { | |
330 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
331 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 336 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
337 | /* |
338 | * TLB invalidate requires a post-sync write. | |
339 | */ | |
340 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 341 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 342 | |
add284a3 CW |
343 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
344 | ||
f3987631 PZ |
345 | /* Workaround: we must issue a pipe_control with CS-stall bit |
346 | * set before a pipe_control command that has the state cache | |
347 | * invalidate bit set. */ | |
f2cf1fcc | 348 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
349 | } |
350 | ||
5fb9de1a | 351 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
352 | if (ret) |
353 | return ret; | |
354 | ||
b5321f30 CW |
355 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
356 | intel_ring_emit(ring, flags); | |
357 | intel_ring_emit(ring, scratch_addr); | |
358 | intel_ring_emit(ring, 0); | |
359 | intel_ring_advance(ring); | |
4772eaeb PZ |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
884ceace | 364 | static int |
f2cf1fcc | 365 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
366 | u32 flags, u32 scratch_addr) |
367 | { | |
7e37f889 | 368 | struct intel_ring *ring = req->ring; |
884ceace KG |
369 | int ret; |
370 | ||
5fb9de1a | 371 | ret = intel_ring_begin(req, 6); |
884ceace KG |
372 | if (ret) |
373 | return ret; | |
374 | ||
b5321f30 CW |
375 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
376 | intel_ring_emit(ring, flags); | |
377 | intel_ring_emit(ring, scratch_addr); | |
378 | intel_ring_emit(ring, 0); | |
379 | intel_ring_emit(ring, 0); | |
380 | intel_ring_emit(ring, 0); | |
381 | intel_ring_advance(ring); | |
884ceace KG |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
a5f3d68e | 386 | static int |
a84c3ae1 | 387 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
388 | u32 invalidate_domains, u32 flush_domains) |
389 | { | |
4a570db5 | 390 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
b5321f30 | 391 | u32 flags = 0; |
02c9f7e3 | 392 | int ret; |
a5f3d68e BW |
393 | |
394 | flags |= PIPE_CONTROL_CS_STALL; | |
395 | ||
396 | if (flush_domains) { | |
397 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
398 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 399 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 400 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
401 | } |
402 | if (invalidate_domains) { | |
403 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
404 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
405 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
406 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
407 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
408 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
409 | flags |= PIPE_CONTROL_QW_WRITE; | |
410 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
411 | |
412 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 413 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
414 | PIPE_CONTROL_CS_STALL | |
415 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
416 | 0); | |
417 | if (ret) | |
418 | return ret; | |
a5f3d68e BW |
419 | } |
420 | ||
f2cf1fcc | 421 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
422 | } |
423 | ||
0bc40be8 | 424 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 425 | u32 value) |
d46eefa2 | 426 | { |
c033666a | 427 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 428 | I915_WRITE_TAIL(engine, value); |
d46eefa2 XH |
429 | } |
430 | ||
7e37f889 | 431 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 432 | { |
c033666a | 433 | struct drm_i915_private *dev_priv = engine->i915; |
50877445 | 434 | u64 acthd; |
8187a2b7 | 435 | |
c033666a | 436 | if (INTEL_GEN(dev_priv) >= 8) |
0bc40be8 TU |
437 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), |
438 | RING_ACTHD_UDW(engine->mmio_base)); | |
c033666a | 439 | else if (INTEL_GEN(dev_priv) >= 4) |
0bc40be8 | 440 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); |
50877445 CW |
441 | else |
442 | acthd = I915_READ(ACTHD); | |
443 | ||
444 | return acthd; | |
8187a2b7 ZN |
445 | } |
446 | ||
0bc40be8 | 447 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 448 | { |
c033666a | 449 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
450 | u32 addr; |
451 | ||
452 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 453 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
454 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
455 | I915_WRITE(HWS_PGA, addr); | |
456 | } | |
457 | ||
0bc40be8 | 458 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 459 | { |
c033666a | 460 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 461 | i915_reg_t mmio; |
af75f269 DL |
462 | |
463 | /* The ring status page addresses are no longer next to the rest of | |
464 | * the ring registers as of gen7. | |
465 | */ | |
c033666a | 466 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 467 | switch (engine->id) { |
af75f269 DL |
468 | case RCS: |
469 | mmio = RENDER_HWS_PGA_GEN7; | |
470 | break; | |
471 | case BCS: | |
472 | mmio = BLT_HWS_PGA_GEN7; | |
473 | break; | |
474 | /* | |
475 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
476 | * gcc switch check warning | |
477 | */ | |
478 | case VCS2: | |
479 | case VCS: | |
480 | mmio = BSD_HWS_PGA_GEN7; | |
481 | break; | |
482 | case VECS: | |
483 | mmio = VEBOX_HWS_PGA_GEN7; | |
484 | break; | |
485 | } | |
c033666a | 486 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 487 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
488 | } else { |
489 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 490 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
491 | } |
492 | ||
0bc40be8 | 493 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
494 | POSTING_READ(mmio); |
495 | ||
496 | /* | |
497 | * Flush the TLB for this page | |
498 | * | |
499 | * FIXME: These two bits have disappeared on gen8, so a question | |
500 | * arises: do we still need this and if so how should we go about | |
501 | * invalidating the TLB? | |
502 | */ | |
ac657f64 | 503 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 504 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
505 | |
506 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 507 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
508 | |
509 | I915_WRITE(reg, | |
510 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
511 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
512 | if (intel_wait_for_register(dev_priv, |
513 | reg, INSTPM_SYNC_FLUSH, 0, | |
514 | 1000)) | |
af75f269 | 515 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 516 | engine->name); |
af75f269 DL |
517 | } |
518 | } | |
519 | ||
0bc40be8 | 520 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 521 | { |
c033666a | 522 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 523 | |
c033666a | 524 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 | 525 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
526 | if (intel_wait_for_register(dev_priv, |
527 | RING_MI_MODE(engine->mmio_base), | |
528 | MODE_IDLE, | |
529 | MODE_IDLE, | |
530 | 1000)) { | |
0bc40be8 TU |
531 | DRM_ERROR("%s : timed out trying to stop ring\n", |
532 | engine->name); | |
9bec9b13 CW |
533 | /* Sometimes we observe that the idle flag is not |
534 | * set even though the ring is empty. So double | |
535 | * check before giving up. | |
536 | */ | |
0bc40be8 | 537 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 538 | return false; |
9991ae78 CW |
539 | } |
540 | } | |
b7884eb4 | 541 | |
0bc40be8 TU |
542 | I915_WRITE_CTL(engine, 0); |
543 | I915_WRITE_HEAD(engine, 0); | |
544 | engine->write_tail(engine, 0); | |
8187a2b7 | 545 | |
c033666a | 546 | if (!IS_GEN2(dev_priv)) { |
0bc40be8 TU |
547 | (void)I915_READ_CTL(engine); |
548 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 549 | } |
a51435a3 | 550 | |
0bc40be8 | 551 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 552 | } |
8187a2b7 | 553 | |
0bc40be8 | 554 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 555 | { |
c033666a | 556 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 CW |
557 | struct intel_ring *ring = engine->buffer; |
558 | struct drm_i915_gem_object *obj = ring->obj; | |
9991ae78 CW |
559 | int ret = 0; |
560 | ||
59bad947 | 561 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 562 | |
0bc40be8 | 563 | if (!stop_ring(engine)) { |
9991ae78 | 564 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
565 | DRM_DEBUG_KMS("%s head not reset to zero " |
566 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
567 | engine->name, |
568 | I915_READ_CTL(engine), | |
569 | I915_READ_HEAD(engine), | |
570 | I915_READ_TAIL(engine), | |
571 | I915_READ_START(engine)); | |
8187a2b7 | 572 | |
0bc40be8 | 573 | if (!stop_ring(engine)) { |
6fd0d56e CW |
574 | DRM_ERROR("failed to set %s head to zero " |
575 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
576 | engine->name, |
577 | I915_READ_CTL(engine), | |
578 | I915_READ_HEAD(engine), | |
579 | I915_READ_TAIL(engine), | |
580 | I915_READ_START(engine)); | |
9991ae78 CW |
581 | ret = -EIO; |
582 | goto out; | |
6fd0d56e | 583 | } |
8187a2b7 ZN |
584 | } |
585 | ||
c033666a | 586 | if (I915_NEED_GFX_HWS(dev_priv)) |
0bc40be8 | 587 | intel_ring_setup_status_page(engine); |
9991ae78 | 588 | else |
0bc40be8 | 589 | ring_setup_phys_status_page(engine); |
9991ae78 | 590 | |
ece4a17d | 591 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 592 | I915_READ_HEAD(engine); |
ece4a17d | 593 | |
0d8957c8 DV |
594 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
595 | * registers with the above sequence (the readback of the HEAD registers | |
596 | * also enforces ordering), otherwise the hw might lose the new ring | |
597 | * register values. */ | |
0bc40be8 | 598 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
599 | |
600 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 601 | if (I915_READ_HEAD(engine)) |
95468892 | 602 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
603 | engine->name, I915_READ_HEAD(engine)); |
604 | I915_WRITE_HEAD(engine, 0); | |
605 | (void)I915_READ_HEAD(engine); | |
95468892 | 606 | |
0bc40be8 | 607 | I915_WRITE_CTL(engine, |
7e37f889 | 608 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 609 | | RING_VALID); |
8187a2b7 | 610 | |
8187a2b7 | 611 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
612 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
613 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
614 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 615 | DRM_ERROR("%s initialization failed " |
48e48a0b | 616 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
617 | engine->name, |
618 | I915_READ_CTL(engine), | |
619 | I915_READ_CTL(engine) & RING_VALID, | |
620 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
621 | I915_READ_START(engine), | |
622 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
623 | ret = -EIO; |
624 | goto out; | |
8187a2b7 ZN |
625 | } |
626 | ||
7e37f889 CW |
627 | ring->last_retired_head = -1; |
628 | ring->head = I915_READ_HEAD(engine); | |
629 | ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
630 | intel_ring_update_space(ring); | |
1ec14ad3 | 631 | |
fc0768ce | 632 | intel_engine_init_hangcheck(engine); |
50f018df | 633 | |
b7884eb4 | 634 | out: |
59bad947 | 635 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
636 | |
637 | return ret; | |
8187a2b7 ZN |
638 | } |
639 | ||
f8291952 | 640 | void intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 641 | { |
0bc40be8 | 642 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
643 | return; |
644 | ||
f8291952 | 645 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
f8c417cd | 646 | i915_gem_object_put(engine->scratch.obj); |
0bc40be8 | 647 | engine->scratch.obj = NULL; |
9b1136d5 OM |
648 | } |
649 | ||
7d5ea807 | 650 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size) |
c6df541c | 651 | { |
f8291952 | 652 | struct drm_i915_gem_object *obj; |
c6df541c CW |
653 | int ret; |
654 | ||
0bc40be8 | 655 | WARN_ON(engine->scratch.obj); |
c6df541c | 656 | |
91c8a326 | 657 | obj = i915_gem_object_create_stolen(&engine->i915->drm, size); |
de8fe166 | 658 | if (!obj) |
91c8a326 | 659 | obj = i915_gem_object_create(&engine->i915->drm, size); |
f8291952 CW |
660 | if (IS_ERR(obj)) { |
661 | DRM_ERROR("Failed to allocate scratch page\n"); | |
662 | ret = PTR_ERR(obj); | |
c6df541c CW |
663 | goto err; |
664 | } | |
e4ffd173 | 665 | |
f8291952 | 666 | ret = i915_gem_obj_ggtt_pin(obj, 4096, PIN_HIGH); |
a9cc726c DV |
667 | if (ret) |
668 | goto err_unref; | |
c6df541c | 669 | |
f8291952 CW |
670 | engine->scratch.obj = obj; |
671 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
2b1086cc | 672 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 673 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
674 | return 0; |
675 | ||
c6df541c | 676 | err_unref: |
f8c417cd | 677 | i915_gem_object_put(engine->scratch.obj); |
c6df541c | 678 | err: |
c6df541c CW |
679 | return ret; |
680 | } | |
681 | ||
e2be4faf | 682 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 683 | { |
7e37f889 | 684 | struct intel_ring *ring = req->ring; |
c033666a CW |
685 | struct i915_workarounds *w = &req->i915->workarounds; |
686 | int ret, i; | |
888b5995 | 687 | |
02235808 | 688 | if (w->count == 0) |
7225342a | 689 | return 0; |
888b5995 | 690 | |
b5321f30 | 691 | req->engine->gpu_caches_dirty = true; |
7e37f889 | 692 | ret = intel_engine_flush_all_caches(req); |
7225342a MK |
693 | if (ret) |
694 | return ret; | |
888b5995 | 695 | |
5fb9de1a | 696 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
697 | if (ret) |
698 | return ret; | |
699 | ||
b5321f30 | 700 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 701 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
702 | intel_ring_emit_reg(ring, w->reg[i].addr); |
703 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 704 | } |
b5321f30 | 705 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 706 | |
b5321f30 | 707 | intel_ring_advance(ring); |
7225342a | 708 | |
b5321f30 | 709 | req->engine->gpu_caches_dirty = true; |
7e37f889 | 710 | ret = intel_engine_flush_all_caches(req); |
7225342a MK |
711 | if (ret) |
712 | return ret; | |
888b5995 | 713 | |
7225342a | 714 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 715 | |
7225342a | 716 | return 0; |
86d7f238 AS |
717 | } |
718 | ||
8753181e | 719 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
720 | { |
721 | int ret; | |
722 | ||
e2be4faf | 723 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
724 | if (ret != 0) |
725 | return ret; | |
726 | ||
be01363f | 727 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 728 | if (ret) |
e26e1b97 | 729 | return ret; |
8f0e2b9d | 730 | |
e26e1b97 | 731 | return 0; |
8f0e2b9d DV |
732 | } |
733 | ||
7225342a | 734 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
735 | i915_reg_t addr, |
736 | const u32 mask, const u32 val) | |
7225342a MK |
737 | { |
738 | const u32 idx = dev_priv->workarounds.count; | |
739 | ||
740 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
741 | return -ENOSPC; | |
742 | ||
743 | dev_priv->workarounds.reg[idx].addr = addr; | |
744 | dev_priv->workarounds.reg[idx].value = val; | |
745 | dev_priv->workarounds.reg[idx].mask = mask; | |
746 | ||
747 | dev_priv->workarounds.count++; | |
748 | ||
749 | return 0; | |
86d7f238 AS |
750 | } |
751 | ||
ca5a0fbd | 752 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 753 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
754 | if (r) \ |
755 | return r; \ | |
ca5a0fbd | 756 | } while (0) |
7225342a MK |
757 | |
758 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 759 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
760 | |
761 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 762 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 763 | |
98533251 | 764 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 765 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 766 | |
cf4b0de6 DL |
767 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
768 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 769 | |
cf4b0de6 | 770 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 771 | |
0bc40be8 TU |
772 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
773 | i915_reg_t reg) | |
33136b06 | 774 | { |
c033666a | 775 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 776 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 777 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
778 | |
779 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
780 | return -EINVAL; | |
781 | ||
0bc40be8 | 782 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 783 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 784 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
785 | |
786 | return 0; | |
787 | } | |
788 | ||
0bc40be8 | 789 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 790 | { |
c033666a | 791 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
792 | |
793 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 794 | |
717d84d6 AS |
795 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
796 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
797 | ||
d0581194 AS |
798 | /* WaDisablePartialInstShootdown:bdw,chv */ |
799 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
800 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
801 | ||
a340af58 AS |
802 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
803 | * workaround for for a possible hang in the unlikely event a TLB | |
804 | * invalidation occurs during a PSD flush. | |
805 | */ | |
806 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 807 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 808 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 809 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
810 | HDC_FORCE_NON_COHERENT); |
811 | ||
6def8fdd AS |
812 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
813 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
814 | * polygons in the same 8x4 pixel/sample area to be processed without | |
815 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
816 | * buffer." | |
817 | * | |
818 | * This optimization is off by default for BDW and CHV; turn it on. | |
819 | */ | |
820 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
821 | ||
48404636 AS |
822 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
823 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
824 | ||
7eebcde6 AS |
825 | /* |
826 | * BSpec recommends 8x4 when MSAA is used, | |
827 | * however in practice 16x4 seems fastest. | |
828 | * | |
829 | * Note that PS/WM thread counts depend on the WIZ hashing | |
830 | * disable bit, which we don't touch here, but it's good | |
831 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
832 | */ | |
833 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
834 | GEN6_WIZ_HASHING_MASK, | |
835 | GEN6_WIZ_HASHING_16x4); | |
836 | ||
e9a64ada AS |
837 | return 0; |
838 | } | |
839 | ||
0bc40be8 | 840 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 841 | { |
c033666a | 842 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 843 | int ret; |
86d7f238 | 844 | |
0bc40be8 | 845 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
846 | if (ret) |
847 | return ret; | |
848 | ||
101b376d | 849 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 850 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 851 | |
101b376d | 852 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
853 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
854 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 855 | |
7225342a MK |
856 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
857 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 858 | |
7225342a | 859 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
860 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
861 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 862 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 863 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 864 | |
86d7f238 AS |
865 | return 0; |
866 | } | |
867 | ||
0bc40be8 | 868 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 869 | { |
c033666a | 870 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 871 | int ret; |
00e1e623 | 872 | |
0bc40be8 | 873 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
874 | if (ret) |
875 | return ret; | |
876 | ||
00e1e623 | 877 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 878 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 879 | |
d60de81d KG |
880 | /* Improve HiZ throughput on CHV. */ |
881 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
882 | ||
7225342a MK |
883 | return 0; |
884 | } | |
885 | ||
0bc40be8 | 886 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 887 | { |
c033666a | 888 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 889 | int ret; |
ab0dfafe | 890 | |
a8ab5ed5 TG |
891 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
892 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
893 | ||
e5f81d65 | 894 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
895 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
896 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
897 | ||
e5f81d65 | 898 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
899 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
900 | ECOCHK_DIS_TLB); | |
901 | ||
e5f81d65 MK |
902 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
903 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 904 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 905 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
906 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
907 | ||
e5f81d65 | 908 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
909 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
910 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
911 | ||
e87a005d | 912 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
c033666a CW |
913 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
914 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
915 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
916 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 917 | |
e87a005d | 918 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
919 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
920 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
921 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
922 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
923 | /* |
924 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
925 | * but we do that in per ctx batchbuffer as there is an issue | |
926 | * with this register not getting restored on ctx restore | |
927 | */ | |
183c6dac DL |
928 | } |
929 | ||
e5f81d65 MK |
930 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
931 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
932 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
933 | GEN9_ENABLE_YV12_BUGFIX | | |
934 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 935 | |
e5f81d65 MK |
936 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
937 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
938 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
939 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 940 | |
e5f81d65 | 941 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
942 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
943 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
944 | ||
5a2ae95e | 945 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
c033666a CW |
946 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || |
947 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
948 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
949 | PIXEL_MASK_CAMMING_DISABLE); | |
950 | ||
5b0e3659 MK |
951 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
952 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
953 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
954 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 955 | |
bbaefe72 MK |
956 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
957 | * both tied to WaForceContextSaveRestoreNonCoherent | |
958 | * in some hsds for skl. We keep the tie for all gen9. The | |
959 | * documentation is a bit hazy and so we want to get common behaviour, | |
960 | * even though there is no clear evidence we would need both on kbl/bxt. | |
961 | * This area has been source of system hangs so we play it safe | |
962 | * and mimic the skl regardless of what bspec says. | |
963 | * | |
964 | * Use Force Non-Coherent whenever executing a 3D context. This | |
965 | * is a workaround for a possible hang in the unlikely event | |
966 | * a TLB invalidation occurs during a PSD flush. | |
967 | */ | |
968 | ||
969 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
970 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
971 | HDC_FORCE_NON_COHERENT); | |
972 | ||
973 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
974 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
975 | BDW_DISABLE_HDC_INVALIDATION); | |
976 | ||
e5f81d65 MK |
977 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
978 | if (IS_SKYLAKE(dev_priv) || | |
979 | IS_KABYLAKE(dev_priv) || | |
980 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
981 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
982 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 983 | |
e5f81d65 | 984 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
985 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
986 | ||
e5f81d65 | 987 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
988 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
989 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
990 | ||
6bb62855 | 991 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
992 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
993 | if (ret) | |
994 | return ret; | |
995 | ||
e5f81d65 | 996 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 997 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
998 | if (ret) |
999 | return ret; | |
1000 | ||
e5f81d65 | 1001 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1002 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1003 | if (ret) |
1004 | return ret; | |
1005 | ||
3b106531 HN |
1006 | return 0; |
1007 | } | |
1008 | ||
0bc40be8 | 1009 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1010 | { |
c033666a | 1011 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
1012 | u8 vals[3] = { 0, 0, 0 }; |
1013 | unsigned int i; | |
1014 | ||
1015 | for (i = 0; i < 3; i++) { | |
1016 | u8 ss; | |
1017 | ||
1018 | /* | |
1019 | * Only consider slices where one, and only one, subslice has 7 | |
1020 | * EUs | |
1021 | */ | |
a4d8a0fe | 1022 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1023 | continue; |
1024 | ||
1025 | /* | |
1026 | * subslice_7eu[i] != 0 (because of the check above) and | |
1027 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1028 | * | |
1029 | * -> 0 <= ss <= 3; | |
1030 | */ | |
1031 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1032 | vals[i] = 3 - ss; | |
1033 | } | |
1034 | ||
1035 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1036 | return 0; | |
1037 | ||
1038 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1039 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1040 | GEN9_IZ_HASHING_MASK(2) | | |
1041 | GEN9_IZ_HASHING_MASK(1) | | |
1042 | GEN9_IZ_HASHING_MASK(0), | |
1043 | GEN9_IZ_HASHING(2, vals[2]) | | |
1044 | GEN9_IZ_HASHING(1, vals[1]) | | |
1045 | GEN9_IZ_HASHING(0, vals[0])); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
0bc40be8 | 1050 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1051 | { |
c033666a | 1052 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1053 | int ret; |
d0bbbc4f | 1054 | |
0bc40be8 | 1055 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1056 | if (ret) |
1057 | return ret; | |
8d205494 | 1058 | |
a78536e7 AS |
1059 | /* |
1060 | * Actual WA is to disable percontext preemption granularity control | |
1061 | * until D0 which is the default case so this is equivalent to | |
1062 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1063 | */ | |
c033666a | 1064 | if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { |
a78536e7 AS |
1065 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1066 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1067 | } | |
1068 | ||
71dce58c | 1069 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { |
9c4cbf82 MK |
1070 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1071 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1072 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1073 | } | |
1074 | ||
1075 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1076 | * involving this register should also be added to WA batch as required. | |
1077 | */ | |
c033666a | 1078 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1079 | /* WaDisableLSQCROPERFforOCL:skl */ |
1080 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1081 | GEN8_LQSC_RO_PERF_DIS); | |
1082 | ||
1083 | /* WaEnableGapsTsvCreditFix:skl */ | |
c033666a | 1084 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1085 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1086 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1087 | } | |
1088 | ||
d0bbbc4f | 1089 | /* WaDisablePowerCompilerClockGating:skl */ |
c033666a | 1090 | if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1091 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1092 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1093 | ||
e87a005d | 1094 | /* WaBarrierPerformanceFixDisable:skl */ |
c033666a | 1095 | if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) |
5b6fd12a VS |
1096 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1097 | HDC_FENCE_DEST_SLM_DISABLE | | |
1098 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1099 | ||
9bd9dfb4 | 1100 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
c033666a | 1101 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1102 | WA_SET_BIT_MASKED( |
1103 | GEN7_HALF_SLICE_CHICKEN1, | |
1104 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1105 | |
eee8efb0 MK |
1106 | /* WaDisableGafsUnitClkGating:skl */ |
1107 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1108 | ||
4ba9c1f7 MK |
1109 | /* WaInPlaceDecompressionHang:skl */ |
1110 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
1111 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1112 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1113 | ||
6107497e | 1114 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1115 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1116 | if (ret) |
1117 | return ret; | |
1118 | ||
0bc40be8 | 1119 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1120 | } |
1121 | ||
0bc40be8 | 1122 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1123 | { |
c033666a | 1124 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1125 | int ret; |
dfb601e6 | 1126 | |
0bc40be8 | 1127 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1128 | if (ret) |
1129 | return ret; | |
cae0437f | 1130 | |
9c4cbf82 MK |
1131 | /* WaStoreMultiplePTEenable:bxt */ |
1132 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1133 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1134 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1135 | ||
1136 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1137 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1138 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1139 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1140 | } | |
1141 | ||
dfb601e6 NH |
1142 | /* WaDisableThreadStallDopClockGating:bxt */ |
1143 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1144 | STALL_DOP_GATING_DISABLE); | |
1145 | ||
780f0aeb | 1146 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1147 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1148 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1149 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1150 | } | |
1151 | ||
983b4b9d | 1152 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1153 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1154 | WA_SET_BIT_MASKED( |
1155 | GEN7_HALF_SLICE_CHICKEN1, | |
1156 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1157 | } | |
1158 | ||
2c8580e4 AS |
1159 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1160 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1161 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1162 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1163 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1164 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1165 | if (ret) |
1166 | return ret; | |
a786d53a | 1167 | |
0bc40be8 | 1168 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1169 | if (ret) |
1170 | return ret; | |
2c8580e4 AS |
1171 | } |
1172 | ||
050fc465 | 1173 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1174 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1175 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1176 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1177 | |
ad2bdb44 MK |
1178 | /* WaInsertDummyPushConstPs:bxt */ |
1179 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1180 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1181 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1182 | ||
4ba9c1f7 MK |
1183 | /* WaInPlaceDecompressionHang:bxt */ |
1184 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1185 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1186 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1187 | ||
cae0437f NH |
1188 | return 0; |
1189 | } | |
1190 | ||
e5f81d65 MK |
1191 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1192 | { | |
e587f6cb | 1193 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1194 | int ret; |
1195 | ||
1196 | ret = gen9_init_workarounds(engine); | |
1197 | if (ret) | |
1198 | return ret; | |
1199 | ||
e587f6cb MK |
1200 | /* WaEnableGapsTsvCreditFix:kbl */ |
1201 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1202 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1203 | ||
c0b730d5 MK |
1204 | /* WaDisableDynamicCreditSharing:kbl */ |
1205 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1206 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1207 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1208 | ||
8401d42f MK |
1209 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1210 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1211 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1212 | HDC_FENCE_DEST_SLM_DISABLE); | |
1213 | ||
fe905819 MK |
1214 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1215 | * involving this register should also be added to WA batch as required. | |
1216 | */ | |
1217 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1218 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1219 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1220 | GEN8_LQSC_RO_PERF_DIS); | |
1221 | ||
ad2bdb44 MK |
1222 | /* WaInsertDummyPushConstPs:kbl */ |
1223 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1224 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1225 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1226 | ||
4de5d7cc MK |
1227 | /* WaDisableGafsUnitClkGating:kbl */ |
1228 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1229 | ||
954337aa MK |
1230 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1231 | WA_SET_BIT_MASKED( | |
1232 | GEN7_HALF_SLICE_CHICKEN1, | |
1233 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1234 | ||
4ba9c1f7 MK |
1235 | /* WaInPlaceDecompressionHang:kbl */ |
1236 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1237 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1238 | ||
fe905819 MK |
1239 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1240 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1241 | if (ret) | |
1242 | return ret; | |
1243 | ||
e5f81d65 MK |
1244 | return 0; |
1245 | } | |
1246 | ||
0bc40be8 | 1247 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1248 | { |
c033666a | 1249 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1250 | |
0bc40be8 | 1251 | WARN_ON(engine->id != RCS); |
7225342a MK |
1252 | |
1253 | dev_priv->workarounds.count = 0; | |
33136b06 | 1254 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1255 | |
c033666a | 1256 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1257 | return bdw_init_workarounds(engine); |
7225342a | 1258 | |
c033666a | 1259 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1260 | return chv_init_workarounds(engine); |
00e1e623 | 1261 | |
c033666a | 1262 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1263 | return skl_init_workarounds(engine); |
cae0437f | 1264 | |
c033666a | 1265 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1266 | return bxt_init_workarounds(engine); |
3b106531 | 1267 | |
e5f81d65 MK |
1268 | if (IS_KABYLAKE(dev_priv)) |
1269 | return kbl_init_workarounds(engine); | |
1270 | ||
00e1e623 VS |
1271 | return 0; |
1272 | } | |
1273 | ||
0bc40be8 | 1274 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1275 | { |
c033666a | 1276 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1277 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1278 | if (ret) |
1279 | return ret; | |
a69ffdbf | 1280 | |
61a563a2 | 1281 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1282 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1283 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1284 | |
1285 | /* We need to disable the AsyncFlip performance optimisations in order | |
1286 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1287 | * programmed to '1' on all products. | |
8693a824 | 1288 | * |
2441f877 | 1289 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1290 | */ |
ac657f64 | 1291 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1292 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1293 | ||
f05bb0c7 | 1294 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1295 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1296 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1297 | I915_WRITE(GFX_MODE, |
aa83e30d | 1298 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1299 | |
01fa0302 | 1300 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1301 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1302 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1303 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1304 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1305 | |
c033666a | 1306 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1307 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1308 | * "If this bit is set, STCunit will have LRA as replacement | |
1309 | * policy. [...] This bit must be reset. LRA replacement | |
1310 | * policy is not supported." | |
1311 | */ | |
1312 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1313 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1314 | } |
1315 | ||
ac657f64 | 1316 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1317 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1318 | |
035ea405 VS |
1319 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1320 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1321 | |
0bc40be8 | 1322 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1323 | } |
1324 | ||
0bc40be8 | 1325 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1326 | { |
c033666a | 1327 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a BW |
1328 | |
1329 | if (dev_priv->semaphore_obj) { | |
1330 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
f8c417cd | 1331 | i915_gem_object_put(dev_priv->semaphore_obj); |
3e78998a BW |
1332 | dev_priv->semaphore_obj = NULL; |
1333 | } | |
b45305fc | 1334 | |
0bc40be8 | 1335 | intel_fini_pipe_control(engine); |
c6df541c CW |
1336 | } |
1337 | ||
f7169687 | 1338 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1339 | unsigned int num_dwords) |
1340 | { | |
1341 | #define MBOX_UPDATE_DWORDS 8 | |
7e37f889 | 1342 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1343 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1344 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1345 | enum intel_engine_id id; |
1346 | int ret, num_rings; | |
3e78998a | 1347 | |
c033666a | 1348 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1349 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1350 | #undef MBOX_UPDATE_DWORDS | |
1351 | ||
5fb9de1a | 1352 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1353 | if (ret) |
1354 | return ret; | |
1355 | ||
c3232b18 | 1356 | for_each_engine_id(waiter, dev_priv, id) { |
b5321f30 CW |
1357 | u64 gtt_offset = |
1358 | signaller_req->engine->semaphore.signal_ggtt[id]; | |
3e78998a BW |
1359 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1360 | continue; | |
1361 | ||
1362 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
b5321f30 CW |
1363 | intel_ring_emit(signaller, |
1364 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1365 | PIPE_CONTROL_QW_WRITE | | |
1366 | PIPE_CONTROL_CS_STALL); | |
3e78998a BW |
1367 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); |
1368 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
04769652 | 1369 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
3e78998a | 1370 | intel_ring_emit(signaller, 0); |
b5321f30 CW |
1371 | intel_ring_emit(signaller, |
1372 | MI_SEMAPHORE_SIGNAL | | |
1373 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
3e78998a BW |
1374 | intel_ring_emit(signaller, 0); |
1375 | } | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
f7169687 | 1380 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1381 | unsigned int num_dwords) |
1382 | { | |
1383 | #define MBOX_UPDATE_DWORDS 6 | |
7e37f889 | 1384 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1385 | struct drm_i915_private *dev_priv = signaller_req->i915; |
3e78998a | 1386 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1387 | enum intel_engine_id id; |
1388 | int ret, num_rings; | |
3e78998a | 1389 | |
c033666a | 1390 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
3e78998a BW |
1391 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; |
1392 | #undef MBOX_UPDATE_DWORDS | |
1393 | ||
5fb9de1a | 1394 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1395 | if (ret) |
1396 | return ret; | |
1397 | ||
c3232b18 | 1398 | for_each_engine_id(waiter, dev_priv, id) { |
b5321f30 CW |
1399 | u64 gtt_offset = |
1400 | signaller_req->engine->semaphore.signal_ggtt[id]; | |
3e78998a BW |
1401 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1402 | continue; | |
1403 | ||
b5321f30 CW |
1404 | intel_ring_emit(signaller, |
1405 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); | |
1406 | intel_ring_emit(signaller, | |
1407 | lower_32_bits(gtt_offset) | | |
1408 | MI_FLUSH_DW_USE_GTT); | |
3e78998a | 1409 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); |
04769652 | 1410 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
b5321f30 CW |
1411 | intel_ring_emit(signaller, |
1412 | MI_SEMAPHORE_SIGNAL | | |
1413 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
3e78998a BW |
1414 | intel_ring_emit(signaller, 0); |
1415 | } | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
f7169687 | 1420 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1421 | unsigned int num_dwords) |
1ec14ad3 | 1422 | { |
7e37f889 | 1423 | struct intel_ring *signaller = signaller_req->ring; |
c033666a | 1424 | struct drm_i915_private *dev_priv = signaller_req->i915; |
a4872ba6 | 1425 | struct intel_engine_cs *useless; |
c3232b18 DG |
1426 | enum intel_engine_id id; |
1427 | int ret, num_rings; | |
78325f2d | 1428 | |
a1444b79 | 1429 | #define MBOX_UPDATE_DWORDS 3 |
c033666a | 1430 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); |
a1444b79 BW |
1431 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); |
1432 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1433 | |
5fb9de1a | 1434 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1435 | if (ret) |
1436 | return ret; | |
024a43e1 | 1437 | |
c3232b18 | 1438 | for_each_engine_id(useless, dev_priv, id) { |
b5321f30 CW |
1439 | i915_reg_t mbox_reg = |
1440 | signaller_req->engine->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1441 | |
1442 | if (i915_mmio_reg_valid(mbox_reg)) { | |
78325f2d | 1443 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1444 | intel_ring_emit_reg(signaller, mbox_reg); |
04769652 | 1445 | intel_ring_emit(signaller, signaller_req->fence.seqno); |
78325f2d BW |
1446 | } |
1447 | } | |
024a43e1 | 1448 | |
a1444b79 BW |
1449 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1450 | if (num_rings % 2 == 0) | |
1451 | intel_ring_emit(signaller, MI_NOOP); | |
1452 | ||
024a43e1 | 1453 | return 0; |
1ec14ad3 CW |
1454 | } |
1455 | ||
c8c99b0f BW |
1456 | /** |
1457 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1458 | * |
1459 | * @request - request to write to the ring | |
c8c99b0f BW |
1460 | * |
1461 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1462 | * This acts like a signal in the canonical semaphore. | |
1463 | */ | |
1ec14ad3 | 1464 | static int |
ee044a88 | 1465 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1466 | { |
4a570db5 | 1467 | struct intel_engine_cs *engine = req->engine; |
7e37f889 | 1468 | struct intel_ring *ring = req->ring; |
024a43e1 | 1469 | int ret; |
52ed2325 | 1470 | |
e2f80391 TU |
1471 | if (engine->semaphore.signal) |
1472 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1473 | else |
5fb9de1a | 1474 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1475 | |
1ec14ad3 CW |
1476 | if (ret) |
1477 | return ret; | |
1478 | ||
b5321f30 CW |
1479 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1480 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1481 | intel_ring_emit(ring, req->fence.seqno); | |
1482 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1483 | __intel_engine_submit(engine); | |
1ec14ad3 | 1484 | |
1ec14ad3 CW |
1485 | return 0; |
1486 | } | |
1487 | ||
a58c01aa CW |
1488 | static int |
1489 | gen8_render_add_request(struct drm_i915_gem_request *req) | |
1490 | { | |
1491 | struct intel_engine_cs *engine = req->engine; | |
7e37f889 | 1492 | struct intel_ring *ring = req->ring; |
a58c01aa CW |
1493 | int ret; |
1494 | ||
1495 | if (engine->semaphore.signal) | |
1496 | ret = engine->semaphore.signal(req, 8); | |
1497 | else | |
1498 | ret = intel_ring_begin(req, 8); | |
1499 | if (ret) | |
1500 | return ret; | |
1501 | ||
b5321f30 CW |
1502 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1503 | intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1504 | PIPE_CONTROL_CS_STALL | | |
1505 | PIPE_CONTROL_QW_WRITE)); | |
1506 | intel_ring_emit(ring, intel_hws_seqno_address(engine)); | |
1507 | intel_ring_emit(ring, 0); | |
1508 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); | |
a58c01aa | 1509 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1510 | intel_ring_emit(ring, 0); |
1511 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1512 | intel_ring_emit(ring, MI_NOOP); | |
1513 | __intel_engine_submit(engine); | |
a58c01aa CW |
1514 | |
1515 | return 0; | |
1516 | } | |
1517 | ||
c033666a | 1518 | static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv, |
f72b3435 MK |
1519 | u32 seqno) |
1520 | { | |
f72b3435 MK |
1521 | return dev_priv->last_seqno < seqno; |
1522 | } | |
1523 | ||
c8c99b0f BW |
1524 | /** |
1525 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1526 | * | |
1527 | * @waiter - ring that is waiting | |
1528 | * @signaller - ring which has, or will signal | |
1529 | * @seqno - seqno which the waiter will block on | |
1530 | */ | |
5ee426ca BW |
1531 | |
1532 | static int | |
599d924c | 1533 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1534 | struct intel_engine_cs *signaller, |
1535 | u32 seqno) | |
1536 | { | |
7e37f889 | 1537 | struct intel_ring *waiter = waiter_req->ring; |
c033666a | 1538 | struct drm_i915_private *dev_priv = waiter_req->i915; |
b5321f30 | 1539 | u64 offset = GEN8_WAIT_OFFSET(waiter_req->engine, signaller->id); |
6ef48d7f | 1540 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1541 | int ret; |
1542 | ||
5fb9de1a | 1543 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1544 | if (ret) |
1545 | return ret; | |
1546 | ||
1547 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1548 | MI_SEMAPHORE_GLOBAL_GTT | | |
1549 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1550 | intel_ring_emit(waiter, seqno); | |
c38c651b TU |
1551 | intel_ring_emit(waiter, lower_32_bits(offset)); |
1552 | intel_ring_emit(waiter, upper_32_bits(offset)); | |
5ee426ca | 1553 | intel_ring_advance(waiter); |
6ef48d7f CW |
1554 | |
1555 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1556 | * pagetables and we must reload them before executing the batch. | |
1557 | * We do this on the i915_switch_context() following the wait and | |
1558 | * before the dispatch. | |
1559 | */ | |
1560 | ppgtt = waiter_req->ctx->ppgtt; | |
1561 | if (ppgtt && waiter_req->engine->id != RCS) | |
1562 | ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine); | |
5ee426ca BW |
1563 | return 0; |
1564 | } | |
1565 | ||
c8c99b0f | 1566 | static int |
599d924c | 1567 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1568 | struct intel_engine_cs *signaller, |
686cb5f9 | 1569 | u32 seqno) |
1ec14ad3 | 1570 | { |
7e37f889 | 1571 | struct intel_ring *waiter = waiter_req->ring; |
c8c99b0f BW |
1572 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1573 | MI_SEMAPHORE_COMPARE | | |
1574 | MI_SEMAPHORE_REGISTER; | |
b5321f30 | 1575 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id]; |
ebc348b2 | 1576 | int ret; |
1ec14ad3 | 1577 | |
1500f7ea BW |
1578 | /* Throughout all of the GEM code, seqno passed implies our current |
1579 | * seqno is >= the last seqno executed. However for hardware the | |
1580 | * comparison is strictly greater than. | |
1581 | */ | |
1582 | seqno -= 1; | |
1583 | ||
ebc348b2 | 1584 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1585 | |
5fb9de1a | 1586 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1587 | if (ret) |
1588 | return ret; | |
1589 | ||
f72b3435 | 1590 | /* If seqno wrap happened, omit the wait with no-ops */ |
c033666a | 1591 | if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) { |
ebc348b2 | 1592 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1593 | intel_ring_emit(waiter, seqno); |
1594 | intel_ring_emit(waiter, 0); | |
1595 | intel_ring_emit(waiter, MI_NOOP); | |
1596 | } else { | |
1597 | intel_ring_emit(waiter, MI_NOOP); | |
1598 | intel_ring_emit(waiter, MI_NOOP); | |
1599 | intel_ring_emit(waiter, MI_NOOP); | |
1600 | intel_ring_emit(waiter, MI_NOOP); | |
1601 | } | |
c8c99b0f | 1602 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1603 | |
1604 | return 0; | |
1605 | } | |
1606 | ||
f8973c21 | 1607 | static void |
38a0f2db | 1608 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1609 | { |
f8973c21 CW |
1610 | /* MI_STORE are internally buffered by the GPU and not flushed |
1611 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1612 | * MI commands. | |
c6df541c | 1613 | * |
f8973c21 CW |
1614 | * "Only the submission of the store operation is guaranteed. |
1615 | * The write result will be complete (coherent) some time later | |
1616 | * (this is practically a finite period but there is no guaranteed | |
1617 | * latency)." | |
1618 | * | |
1619 | * Empirically, we observe that we need a delay of at least 75us to | |
1620 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1621 | */ |
f8973c21 | 1622 | usleep_range(125, 250); |
c6df541c CW |
1623 | } |
1624 | ||
c04e0f3b CW |
1625 | static void |
1626 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1627 | { |
c033666a | 1628 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1629 | |
4cd53c0c DV |
1630 | /* Workaround to force correct ordering between irq and seqno writes on |
1631 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1632 | * ACTHD) before reading the status page. |
1633 | * | |
1634 | * Note that this effectively stalls the read by the time it takes to | |
1635 | * do a memory transaction, which more or less ensures that the write | |
1636 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1637 | * Alternatively we could delay the interrupt from the CS ring to give | |
1638 | * the write time to land, but that would incur a delay after every | |
1639 | * batch i.e. much more frequent than a delay when waiting for the | |
1640 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1641 | * |
1642 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1643 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1644 | */ |
bcbdb6d0 | 1645 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1646 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1647 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1648 | } |
1649 | ||
31bb59cc CW |
1650 | static void |
1651 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1652 | { |
31bb59cc | 1653 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1654 | } |
1655 | ||
1656 | static void | |
31bb59cc | 1657 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1658 | { |
31bb59cc | 1659 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1660 | } |
1661 | ||
31bb59cc CW |
1662 | static void |
1663 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1664 | { |
c033666a | 1665 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1666 | |
31bb59cc CW |
1667 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1668 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1669 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1670 | } |
1671 | ||
8187a2b7 | 1672 | static void |
31bb59cc | 1673 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1674 | { |
c033666a | 1675 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1676 | |
31bb59cc CW |
1677 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1678 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1679 | } |
1680 | ||
31bb59cc CW |
1681 | static void |
1682 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1683 | { |
c033666a | 1684 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1685 | |
31bb59cc CW |
1686 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1687 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1688 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1689 | } |
1690 | ||
1691 | static void | |
31bb59cc | 1692 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1693 | { |
c033666a | 1694 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1695 | |
31bb59cc CW |
1696 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1697 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1698 | } |
1699 | ||
b72f3acb | 1700 | static int |
a84c3ae1 | 1701 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1702 | u32 invalidate_domains, |
1703 | u32 flush_domains) | |
d1b851fc | 1704 | { |
7e37f889 | 1705 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1706 | int ret; |
1707 | ||
5fb9de1a | 1708 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1709 | if (ret) |
1710 | return ret; | |
1711 | ||
b5321f30 CW |
1712 | intel_ring_emit(ring, MI_FLUSH); |
1713 | intel_ring_emit(ring, MI_NOOP); | |
1714 | intel_ring_advance(ring); | |
b72f3acb | 1715 | return 0; |
d1b851fc ZN |
1716 | } |
1717 | ||
3cce469c | 1718 | static int |
ee044a88 | 1719 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1720 | { |
7e37f889 | 1721 | struct intel_ring *ring = req->ring; |
3cce469c CW |
1722 | int ret; |
1723 | ||
5fb9de1a | 1724 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1725 | if (ret) |
1726 | return ret; | |
6f392d54 | 1727 | |
b5321f30 CW |
1728 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1729 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1730 | intel_ring_emit(ring, req->fence.seqno); | |
1731 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1732 | __intel_engine_submit(req->engine); | |
d1b851fc | 1733 | |
3cce469c | 1734 | return 0; |
d1b851fc ZN |
1735 | } |
1736 | ||
31bb59cc CW |
1737 | static void |
1738 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1739 | { |
c033666a | 1740 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1741 | |
61ff75ac CW |
1742 | I915_WRITE_IMR(engine, |
1743 | ~(engine->irq_enable_mask | | |
1744 | engine->irq_keep_mask)); | |
31bb59cc | 1745 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1746 | } |
1747 | ||
1748 | static void | |
31bb59cc | 1749 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1750 | { |
c033666a | 1751 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1752 | |
61ff75ac | 1753 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1754 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1755 | } |
1756 | ||
31bb59cc CW |
1757 | static void |
1758 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1759 | { |
c033666a | 1760 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1761 | |
31bb59cc CW |
1762 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1763 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1764 | } |
1765 | ||
1766 | static void | |
31bb59cc | 1767 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1768 | { |
c033666a | 1769 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1770 | |
31bb59cc CW |
1771 | I915_WRITE_IMR(engine, ~0); |
1772 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1773 | } |
1774 | ||
31bb59cc CW |
1775 | static void |
1776 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1777 | { |
c033666a | 1778 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1779 | |
61ff75ac CW |
1780 | I915_WRITE_IMR(engine, |
1781 | ~(engine->irq_enable_mask | | |
1782 | engine->irq_keep_mask)); | |
31bb59cc | 1783 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1784 | } |
1785 | ||
1786 | static void | |
31bb59cc | 1787 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1788 | { |
c033666a | 1789 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1790 | |
61ff75ac | 1791 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1792 | } |
1793 | ||
d1b851fc | 1794 | static int |
53fddaf7 | 1795 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1796 | u64 offset, u32 length, |
8e004efc | 1797 | unsigned dispatch_flags) |
d1b851fc | 1798 | { |
7e37f889 | 1799 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1800 | int ret; |
78501eac | 1801 | |
5fb9de1a | 1802 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1803 | if (ret) |
1804 | return ret; | |
1805 | ||
b5321f30 | 1806 | intel_ring_emit(ring, |
65f56876 CW |
1807 | MI_BATCH_BUFFER_START | |
1808 | MI_BATCH_GTT | | |
8e004efc JH |
1809 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1810 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1811 | intel_ring_emit(ring, offset); |
1812 | intel_ring_advance(ring); | |
78501eac | 1813 | |
d1b851fc ZN |
1814 | return 0; |
1815 | } | |
1816 | ||
b45305fc DV |
1817 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1818 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1819 | #define I830_TLB_ENTRIES (2) |
1820 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1821 | static int |
53fddaf7 | 1822 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1823 | u64 offset, u32 len, |
1824 | unsigned dispatch_flags) | |
62fdfeaf | 1825 | { |
7e37f889 | 1826 | struct intel_ring *ring = req->ring; |
b5321f30 | 1827 | u32 cs_offset = req->engine->scratch.gtt_offset; |
c4e7a414 | 1828 | int ret; |
62fdfeaf | 1829 | |
5fb9de1a | 1830 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1831 | if (ret) |
1832 | return ret; | |
62fdfeaf | 1833 | |
c4d69da1 | 1834 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1835 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1836 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1837 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1838 | intel_ring_emit(ring, cs_offset); | |
1839 | intel_ring_emit(ring, 0xdeadbeef); | |
1840 | intel_ring_emit(ring, MI_NOOP); | |
1841 | intel_ring_advance(ring); | |
b45305fc | 1842 | |
8e004efc | 1843 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1844 | if (len > I830_BATCH_LIMIT) |
1845 | return -ENOSPC; | |
1846 | ||
5fb9de1a | 1847 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1848 | if (ret) |
1849 | return ret; | |
c4d69da1 CW |
1850 | |
1851 | /* Blit the batch (which has now all relocs applied) to the | |
1852 | * stable batch scratch bo area (so that the CS never | |
1853 | * stumbles over its tlb invalidation bug) ... | |
1854 | */ | |
b5321f30 CW |
1855 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1856 | intel_ring_emit(ring, | |
e2f80391 | 1857 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1858 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1859 | intel_ring_emit(ring, cs_offset); | |
1860 | intel_ring_emit(ring, 4096); | |
1861 | intel_ring_emit(ring, offset); | |
e2f80391 | 1862 | |
b5321f30 CW |
1863 | intel_ring_emit(ring, MI_FLUSH); |
1864 | intel_ring_emit(ring, MI_NOOP); | |
1865 | intel_ring_advance(ring); | |
b45305fc DV |
1866 | |
1867 | /* ... and execute it. */ | |
c4d69da1 | 1868 | offset = cs_offset; |
b45305fc | 1869 | } |
e1f99ce6 | 1870 | |
9d611c03 | 1871 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1872 | if (ret) |
1873 | return ret; | |
1874 | ||
b5321f30 CW |
1875 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1876 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1877 | 0 : MI_BATCH_NON_SECURE)); | |
1878 | intel_ring_advance(ring); | |
c4d69da1 | 1879 | |
fb3256da DV |
1880 | return 0; |
1881 | } | |
1882 | ||
1883 | static int | |
53fddaf7 | 1884 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1885 | u64 offset, u32 len, |
8e004efc | 1886 | unsigned dispatch_flags) |
fb3256da | 1887 | { |
7e37f889 | 1888 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1889 | int ret; |
1890 | ||
5fb9de1a | 1891 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1892 | if (ret) |
1893 | return ret; | |
1894 | ||
b5321f30 CW |
1895 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1896 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1897 | 0 : MI_BATCH_NON_SECURE)); | |
1898 | intel_ring_advance(ring); | |
62fdfeaf | 1899 | |
62fdfeaf EA |
1900 | return 0; |
1901 | } | |
1902 | ||
0bc40be8 | 1903 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1904 | { |
c033666a | 1905 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1906 | |
1907 | if (!dev_priv->status_page_dmah) | |
1908 | return; | |
1909 | ||
91c8a326 | 1910 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1911 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1912 | } |
1913 | ||
0bc40be8 | 1914 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1915 | { |
05394f39 | 1916 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1917 | |
0bc40be8 | 1918 | obj = engine->status_page.obj; |
8187a2b7 | 1919 | if (obj == NULL) |
62fdfeaf | 1920 | return; |
62fdfeaf | 1921 | |
9da3da66 | 1922 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1923 | i915_gem_object_ggtt_unpin(obj); |
f8c417cd | 1924 | i915_gem_object_put(obj); |
0bc40be8 | 1925 | engine->status_page.obj = NULL; |
62fdfeaf EA |
1926 | } |
1927 | ||
0bc40be8 | 1928 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1929 | { |
0bc40be8 | 1930 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 1931 | |
7d3fdfff | 1932 | if (obj == NULL) { |
1f767e02 | 1933 | unsigned flags; |
e3efda49 | 1934 | int ret; |
e4ffd173 | 1935 | |
91c8a326 | 1936 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
fe3db79b | 1937 | if (IS_ERR(obj)) { |
e3efda49 | 1938 | DRM_ERROR("Failed to allocate status page\n"); |
fe3db79b | 1939 | return PTR_ERR(obj); |
e3efda49 | 1940 | } |
62fdfeaf | 1941 | |
e3efda49 CW |
1942 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1943 | if (ret) | |
1944 | goto err_unref; | |
1945 | ||
1f767e02 | 1946 | flags = 0; |
c033666a | 1947 | if (!HAS_LLC(engine->i915)) |
1f767e02 CW |
1948 | /* On g33, we cannot place HWS above 256MiB, so |
1949 | * restrict its pinning to the low mappable arena. | |
1950 | * Though this restriction is not documented for | |
1951 | * gen4, gen5, or byt, they also behave similarly | |
1952 | * and hang if the HWS is placed at the top of the | |
1953 | * GTT. To generalise, it appears that all !llc | |
1954 | * platforms have issues with us placing the HWS | |
1955 | * above the mappable region (even though we never | |
1956 | * actualy map it). | |
1957 | */ | |
1958 | flags |= PIN_MAPPABLE; | |
1959 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1960 | if (ret) { |
1961 | err_unref: | |
f8c417cd | 1962 | i915_gem_object_put(obj); |
e3efda49 CW |
1963 | return ret; |
1964 | } | |
1965 | ||
0bc40be8 | 1966 | engine->status_page.obj = obj; |
e3efda49 | 1967 | } |
62fdfeaf | 1968 | |
0bc40be8 TU |
1969 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
1970 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
1971 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1972 | |
8187a2b7 | 1973 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 1974 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
1975 | |
1976 | return 0; | |
62fdfeaf EA |
1977 | } |
1978 | ||
0bc40be8 | 1979 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1980 | { |
c033666a | 1981 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 CW |
1982 | |
1983 | if (!dev_priv->status_page_dmah) { | |
1984 | dev_priv->status_page_dmah = | |
91c8a326 | 1985 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
1986 | if (!dev_priv->status_page_dmah) |
1987 | return -ENOMEM; | |
1988 | } | |
1989 | ||
0bc40be8 TU |
1990 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1991 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1992 | |
1993 | return 0; | |
1994 | } | |
1995 | ||
32c04f16 | 1996 | void intel_unpin_ring(struct intel_ring *ring) |
2919d291 | 1997 | { |
32c04f16 CW |
1998 | GEM_BUG_ON(!ring->vma); |
1999 | GEM_BUG_ON(!ring->vaddr); | |
3d77e9be | 2000 | |
32c04f16 CW |
2001 | if (HAS_LLC(ring->obj->base.dev) && !ring->obj->stolen) |
2002 | i915_gem_object_unpin_map(ring->obj); | |
def0c5f6 | 2003 | else |
32c04f16 CW |
2004 | i915_vma_unpin_iomap(ring->vma); |
2005 | ring->vaddr = NULL; | |
3d77e9be | 2006 | |
32c04f16 CW |
2007 | i915_gem_object_ggtt_unpin(ring->obj); |
2008 | ring->vma = NULL; | |
7ba717cf TD |
2009 | } |
2010 | ||
7e37f889 | 2011 | int intel_pin_and_map_ring(struct drm_i915_private *dev_priv, |
32c04f16 | 2012 | struct intel_ring *ring) |
7ba717cf | 2013 | { |
32c04f16 | 2014 | struct drm_i915_gem_object *obj = ring->obj; |
a687a43a CW |
2015 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2016 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2017 | void *addr; |
7ba717cf TD |
2018 | int ret; |
2019 | ||
def0c5f6 | 2020 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2021 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2022 | if (ret) |
2023 | return ret; | |
7ba717cf | 2024 | |
def0c5f6 | 2025 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2026 | if (ret) |
2027 | goto err_unpin; | |
def0c5f6 | 2028 | |
8305216f DG |
2029 | addr = i915_gem_object_pin_map(obj); |
2030 | if (IS_ERR(addr)) { | |
2031 | ret = PTR_ERR(addr); | |
d2cad535 | 2032 | goto err_unpin; |
def0c5f6 CW |
2033 | } |
2034 | } else { | |
a687a43a CW |
2035 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2036 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2037 | if (ret) |
2038 | return ret; | |
7ba717cf | 2039 | |
def0c5f6 | 2040 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2041 | if (ret) |
2042 | goto err_unpin; | |
def0c5f6 | 2043 | |
ff3dc087 DCS |
2044 | /* Access through the GTT requires the device to be awake. */ |
2045 | assert_rpm_wakelock_held(dev_priv); | |
2046 | ||
406ea8d2 CW |
2047 | addr = (void __force *) |
2048 | i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); | |
3d77e9be CW |
2049 | if (IS_ERR(addr)) { |
2050 | ret = PTR_ERR(addr); | |
d2cad535 | 2051 | goto err_unpin; |
def0c5f6 | 2052 | } |
7ba717cf TD |
2053 | } |
2054 | ||
32c04f16 CW |
2055 | ring->vaddr = addr; |
2056 | ring->vma = i915_gem_obj_to_ggtt(obj); | |
7ba717cf | 2057 | return 0; |
d2cad535 CW |
2058 | |
2059 | err_unpin: | |
2060 | i915_gem_object_ggtt_unpin(obj); | |
2061 | return ret; | |
7ba717cf TD |
2062 | } |
2063 | ||
32c04f16 | 2064 | static void intel_destroy_ringbuffer_obj(struct intel_ring *ring) |
7ba717cf | 2065 | { |
32c04f16 CW |
2066 | i915_gem_object_put(ring->obj); |
2067 | ring->obj = NULL; | |
2919d291 OM |
2068 | } |
2069 | ||
01101fa7 | 2070 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
32c04f16 | 2071 | struct intel_ring *ring) |
62fdfeaf | 2072 | { |
05394f39 | 2073 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2074 | |
ebc052e0 CW |
2075 | obj = NULL; |
2076 | if (!HAS_LLC(dev)) | |
32c04f16 | 2077 | obj = i915_gem_object_create_stolen(dev, ring->size); |
ebc052e0 | 2078 | if (obj == NULL) |
32c04f16 | 2079 | obj = i915_gem_object_create(dev, ring->size); |
fe3db79b CW |
2080 | if (IS_ERR(obj)) |
2081 | return PTR_ERR(obj); | |
8187a2b7 | 2082 | |
24f3a8cf AG |
2083 | /* mark ring buffers as read-only from GPU side by default */ |
2084 | obj->gt_ro = 1; | |
2085 | ||
32c04f16 | 2086 | ring->obj = obj; |
e3efda49 | 2087 | |
7ba717cf | 2088 | return 0; |
e3efda49 CW |
2089 | } |
2090 | ||
7e37f889 CW |
2091 | struct intel_ring * |
2092 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 2093 | { |
7e37f889 | 2094 | struct intel_ring *ring; |
01101fa7 CW |
2095 | int ret; |
2096 | ||
2097 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2098 | if (ring == NULL) { |
2099 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2100 | engine->name); | |
01101fa7 | 2101 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2102 | } |
01101fa7 | 2103 | |
4a570db5 | 2104 | ring->engine = engine; |
608c1a52 | 2105 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2106 | |
2107 | ring->size = size; | |
2108 | /* Workaround an erratum on the i830 which causes a hang if | |
2109 | * the TAIL pointer points to within the last 2 cachelines | |
2110 | * of the buffer. | |
2111 | */ | |
2112 | ring->effective_size = size; | |
c033666a | 2113 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
2114 | ring->effective_size -= 2 * CACHELINE_BYTES; |
2115 | ||
2116 | ring->last_retired_head = -1; | |
2117 | intel_ring_update_space(ring); | |
2118 | ||
91c8a326 | 2119 | ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring); |
01101fa7 | 2120 | if (ret) { |
608c1a52 CW |
2121 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2122 | engine->name, ret); | |
2123 | list_del(&ring->link); | |
01101fa7 CW |
2124 | kfree(ring); |
2125 | return ERR_PTR(ret); | |
2126 | } | |
2127 | ||
2128 | return ring; | |
2129 | } | |
2130 | ||
2131 | void | |
7e37f889 | 2132 | intel_ring_free(struct intel_ring *ring) |
01101fa7 CW |
2133 | { |
2134 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2135 | list_del(&ring->link); |
01101fa7 CW |
2136 | kfree(ring); |
2137 | } | |
2138 | ||
0cb26a8e CW |
2139 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
2140 | struct intel_engine_cs *engine) | |
2141 | { | |
2142 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2143 | int ret; | |
2144 | ||
91c8a326 | 2145 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2146 | |
2147 | if (ce->pin_count++) | |
2148 | return 0; | |
2149 | ||
2150 | if (ce->state) { | |
2151 | ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); | |
2152 | if (ret) | |
2153 | goto error; | |
2154 | } | |
2155 | ||
c7c3c07d CW |
2156 | /* The kernel context is only used as a placeholder for flushing the |
2157 | * active context. It is never used for submitting user rendering and | |
2158 | * as such never requires the golden render context, and so we can skip | |
2159 | * emitting it when we switch to the kernel context. This is required | |
2160 | * as during eviction we cannot allocate and pin the renderstate in | |
2161 | * order to initialise the context. | |
2162 | */ | |
2163 | if (ctx == ctx->i915->kernel_context) | |
2164 | ce->initialised = true; | |
2165 | ||
9a6feaf0 | 2166 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2167 | return 0; |
2168 | ||
2169 | error: | |
2170 | ce->pin_count = 0; | |
2171 | return ret; | |
2172 | } | |
2173 | ||
2174 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2175 | struct intel_engine_cs *engine) | |
2176 | { | |
2177 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2178 | ||
91c8a326 | 2179 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2180 | |
2181 | if (--ce->pin_count) | |
2182 | return; | |
2183 | ||
2184 | if (ce->state) | |
2185 | i915_gem_object_ggtt_unpin(ce->state); | |
2186 | ||
9a6feaf0 | 2187 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2188 | } |
2189 | ||
acd27845 | 2190 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2191 | { |
acd27845 | 2192 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2193 | struct intel_ring *ring; |
e3efda49 CW |
2194 | int ret; |
2195 | ||
0bc40be8 | 2196 | WARN_ON(engine->buffer); |
bfc882b4 | 2197 | |
019bf277 TU |
2198 | intel_engine_setup_common(engine); |
2199 | ||
0bc40be8 TU |
2200 | memset(engine->semaphore.sync_seqno, 0, |
2201 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2202 | |
019bf277 | 2203 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2204 | if (ret) |
2205 | goto error; | |
e3efda49 | 2206 | |
0cb26a8e CW |
2207 | /* We may need to do things with the shrinker which |
2208 | * require us to immediately switch back to the default | |
2209 | * context. This can cause a problem as pinning the | |
2210 | * default context also requires GTT space which may not | |
2211 | * be available. To avoid this we always pin the default | |
2212 | * context. | |
2213 | */ | |
2214 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2215 | if (ret) | |
2216 | goto error; | |
2217 | ||
32c04f16 CW |
2218 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2219 | if (IS_ERR(ring)) { | |
2220 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2221 | goto error; |
2222 | } | |
32c04f16 | 2223 | engine->buffer = ring; |
01101fa7 | 2224 | |
c033666a | 2225 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2226 | ret = init_status_page(engine); |
e3efda49 | 2227 | if (ret) |
8ee14975 | 2228 | goto error; |
e3efda49 | 2229 | } else { |
0bc40be8 TU |
2230 | WARN_ON(engine->id != RCS); |
2231 | ret = init_phys_status_page(engine); | |
e3efda49 | 2232 | if (ret) |
8ee14975 | 2233 | goto error; |
e3efda49 CW |
2234 | } |
2235 | ||
32c04f16 | 2236 | ret = intel_pin_and_map_ring(dev_priv, ring); |
bfc882b4 DV |
2237 | if (ret) { |
2238 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2239 | engine->name, ret); |
32c04f16 | 2240 | intel_destroy_ringbuffer_obj(ring); |
bfc882b4 | 2241 | goto error; |
e3efda49 | 2242 | } |
62fdfeaf | 2243 | |
8ee14975 | 2244 | return 0; |
351e3db2 | 2245 | |
8ee14975 | 2246 | error: |
7e37f889 | 2247 | intel_engine_cleanup(engine); |
8ee14975 | 2248 | return ret; |
62fdfeaf EA |
2249 | } |
2250 | ||
7e37f889 | 2251 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2252 | { |
6402c330 | 2253 | struct drm_i915_private *dev_priv; |
33626e6a | 2254 | |
117897f4 | 2255 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2256 | return; |
2257 | ||
c033666a | 2258 | dev_priv = engine->i915; |
6402c330 | 2259 | |
0bc40be8 | 2260 | if (engine->buffer) { |
7e37f889 | 2261 | intel_engine_stop(engine); |
c033666a | 2262 | WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2263 | |
7e37f889 CW |
2264 | intel_unpin_ring(engine->buffer); |
2265 | intel_ring_free(engine->buffer); | |
0bc40be8 | 2266 | engine->buffer = NULL; |
b0366a54 | 2267 | } |
78501eac | 2268 | |
0bc40be8 TU |
2269 | if (engine->cleanup) |
2270 | engine->cleanup(engine); | |
8d19215b | 2271 | |
c033666a | 2272 | if (I915_NEED_GFX_HWS(dev_priv)) { |
0bc40be8 | 2273 | cleanup_status_page(engine); |
7d3fdfff | 2274 | } else { |
0bc40be8 TU |
2275 | WARN_ON(engine->id != RCS); |
2276 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2277 | } |
44e895a8 | 2278 | |
33a051a5 | 2279 | intel_engine_cleanup_cmd_parser(engine); |
0bc40be8 | 2280 | i915_gem_batch_pool_fini(&engine->batch_pool); |
688e6c72 | 2281 | intel_engine_fini_breadcrumbs(engine); |
0cb26a8e CW |
2282 | |
2283 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2284 | ||
c033666a | 2285 | engine->i915 = NULL; |
62fdfeaf EA |
2286 | } |
2287 | ||
666796da | 2288 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2289 | { |
a4b3a571 | 2290 | struct drm_i915_gem_request *req; |
3e960501 | 2291 | |
3e960501 | 2292 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2293 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2294 | return 0; |
2295 | ||
0bc40be8 TU |
2296 | req = list_entry(engine->request_list.prev, |
2297 | struct drm_i915_gem_request, | |
2298 | list); | |
b4716185 CW |
2299 | |
2300 | /* Make sure we do not trigger any retires */ | |
2301 | return __i915_wait_request(req, | |
c19ae989 | 2302 | req->i915->mm.interruptible, |
b4716185 | 2303 | NULL, NULL); |
3e960501 CW |
2304 | } |
2305 | ||
6689cb2b | 2306 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2307 | { |
6310346e CW |
2308 | int ret; |
2309 | ||
2310 | /* Flush enough space to reduce the likelihood of waiting after | |
2311 | * we start building the request - in which case we will just | |
2312 | * have to repeat work. | |
2313 | */ | |
a0442461 | 2314 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2315 | |
1dae2dfb | 2316 | request->ring = request->engine->buffer; |
6310346e CW |
2317 | |
2318 | ret = intel_ring_begin(request, 0); | |
2319 | if (ret) | |
2320 | return ret; | |
2321 | ||
a0442461 | 2322 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2323 | return 0; |
9d773091 CW |
2324 | } |
2325 | ||
987046ad CW |
2326 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2327 | { | |
7e37f889 | 2328 | struct intel_ring *ring = req->ring; |
987046ad CW |
2329 | struct intel_engine_cs *engine = req->engine; |
2330 | struct drm_i915_gem_request *target; | |
2331 | ||
1dae2dfb CW |
2332 | intel_ring_update_space(ring); |
2333 | if (ring->space >= bytes) | |
987046ad CW |
2334 | return 0; |
2335 | ||
2336 | /* | |
2337 | * Space is reserved in the ringbuffer for finalising the request, | |
2338 | * as that cannot be allowed to fail. During request finalisation, | |
2339 | * reserved_space is set to 0 to stop the overallocation and the | |
2340 | * assumption is that then we never need to wait (which has the | |
2341 | * risk of failing with EINTR). | |
2342 | * | |
2343 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2344 | */ | |
0251a963 | 2345 | GEM_BUG_ON(!req->reserved_space); |
987046ad CW |
2346 | |
2347 | list_for_each_entry(target, &engine->request_list, list) { | |
2348 | unsigned space; | |
2349 | ||
79bbcc29 | 2350 | /* |
987046ad CW |
2351 | * The request queue is per-engine, so can contain requests |
2352 | * from multiple ringbuffers. Here, we must ignore any that | |
2353 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2354 | */ |
1dae2dfb | 2355 | if (target->ring != ring) |
987046ad CW |
2356 | continue; |
2357 | ||
2358 | /* Would completion of this request free enough space? */ | |
1dae2dfb CW |
2359 | space = __intel_ring_space(target->postfix, ring->tail, |
2360 | ring->size); | |
987046ad CW |
2361 | if (space >= bytes) |
2362 | break; | |
79bbcc29 | 2363 | } |
29b1b415 | 2364 | |
987046ad CW |
2365 | if (WARN_ON(&target->list == &engine->request_list)) |
2366 | return -ENOSPC; | |
2367 | ||
2368 | return i915_wait_request(target); | |
29b1b415 JH |
2369 | } |
2370 | ||
987046ad | 2371 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2372 | { |
7e37f889 | 2373 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2374 | int remain_actual = ring->size - ring->tail; |
2375 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2376 | int bytes = num_dwords * sizeof(u32); |
2377 | int total_bytes, wait_bytes; | |
79bbcc29 | 2378 | bool need_wrap = false; |
29b1b415 | 2379 | |
0251a963 | 2380 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2381 | |
79bbcc29 JH |
2382 | if (unlikely(bytes > remain_usable)) { |
2383 | /* | |
2384 | * Not enough space for the basic request. So need to flush | |
2385 | * out the remainder and then wait for base + reserved. | |
2386 | */ | |
2387 | wait_bytes = remain_actual + total_bytes; | |
2388 | need_wrap = true; | |
987046ad CW |
2389 | } else if (unlikely(total_bytes > remain_usable)) { |
2390 | /* | |
2391 | * The base request will fit but the reserved space | |
2392 | * falls off the end. So we don't need an immediate wrap | |
2393 | * and only need to effectively wait for the reserved | |
2394 | * size space from the start of ringbuffer. | |
2395 | */ | |
0251a963 | 2396 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2397 | } else { |
987046ad CW |
2398 | /* No wrapping required, just waiting. */ |
2399 | wait_bytes = total_bytes; | |
cbcc80df MK |
2400 | } |
2401 | ||
1dae2dfb | 2402 | if (wait_bytes > ring->space) { |
987046ad | 2403 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2404 | if (unlikely(ret)) |
2405 | return ret; | |
79bbcc29 | 2406 | |
1dae2dfb CW |
2407 | intel_ring_update_space(ring); |
2408 | if (unlikely(ring->space < wait_bytes)) | |
e075a32f | 2409 | return -EAGAIN; |
cbcc80df MK |
2410 | } |
2411 | ||
987046ad | 2412 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2413 | GEM_BUG_ON(remain_actual > ring->space); |
2414 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2415 | |
987046ad | 2416 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2417 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2418 | ring->tail = 0; | |
2419 | ring->space -= remain_actual; | |
987046ad | 2420 | } |
304d695c | 2421 | |
1dae2dfb CW |
2422 | ring->space -= bytes; |
2423 | GEM_BUG_ON(ring->space < 0); | |
304d695c | 2424 | return 0; |
8187a2b7 | 2425 | } |
78501eac | 2426 | |
753b1ad4 | 2427 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2428 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2429 | { |
7e37f889 | 2430 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2431 | int num_dwords = |
2432 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2433 | int ret; |
2434 | ||
2435 | if (num_dwords == 0) | |
2436 | return 0; | |
2437 | ||
18393f63 | 2438 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2439 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2440 | if (ret) |
2441 | return ret; | |
2442 | ||
2443 | while (num_dwords--) | |
b5321f30 | 2444 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2445 | |
b5321f30 | 2446 | intel_ring_advance(ring); |
753b1ad4 VS |
2447 | |
2448 | return 0; | |
2449 | } | |
2450 | ||
7e37f889 | 2451 | void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2452 | { |
c033666a | 2453 | struct drm_i915_private *dev_priv = engine->i915; |
498d2ac1 | 2454 | |
29dcb570 CW |
2455 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2456 | * so long as the semaphore value in the register/page is greater | |
2457 | * than the sync value), so whenever we reset the seqno, | |
2458 | * so long as we reset the tracking semaphore value to 0, it will | |
2459 | * always be before the next request's seqno. If we don't reset | |
2460 | * the semaphore value, then when the seqno moves backwards all | |
2461 | * future waits will complete instantly (causing rendering corruption). | |
2462 | */ | |
7e22dbbb | 2463 | if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { |
0bc40be8 TU |
2464 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2465 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2466 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2467 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2468 | } |
a058d934 CW |
2469 | if (dev_priv->semaphore_obj) { |
2470 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2471 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2472 | void *semaphores = kmap(page); | |
2473 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2474 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2475 | kunmap(page); | |
2476 | } | |
29dcb570 CW |
2477 | memset(engine->semaphore.sync_seqno, 0, |
2478 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2479 | |
1b7744e7 CW |
2480 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
2481 | if (engine->irq_seqno_barrier) | |
2482 | engine->irq_seqno_barrier(engine); | |
01347126 | 2483 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2484 | |
0bc40be8 | 2485 | engine->hangcheck.seqno = seqno; |
688e6c72 CW |
2486 | |
2487 | /* After manually advancing the seqno, fake the interrupt in case | |
2488 | * there are any waiters for that seqno. | |
2489 | */ | |
2490 | rcu_read_lock(); | |
2491 | intel_engine_wakeup(engine); | |
2492 | rcu_read_unlock(); | |
8187a2b7 | 2493 | } |
62fdfeaf | 2494 | |
0bc40be8 | 2495 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2496 | u32 value) |
881f47b6 | 2497 | { |
c033666a | 2498 | struct drm_i915_private *dev_priv = engine->i915; |
881f47b6 | 2499 | |
76f8421f CW |
2500 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2501 | ||
881f47b6 | 2502 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2503 | |
2504 | /* Disable notification that the ring is IDLE. The GT | |
2505 | * will then assume that it is busy and bring it out of rc6. | |
2506 | */ | |
76f8421f CW |
2507 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2508 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2509 | |
2510 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2511 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2512 | |
12f55818 | 2513 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2514 | if (intel_wait_for_register_fw(dev_priv, |
2515 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2516 | GEN6_BSD_SLEEP_INDICATOR, | |
2517 | 0, | |
2518 | 50)) | |
12f55818 | 2519 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2520 | |
12f55818 | 2521 | /* Now that the ring is fully powered up, update the tail */ |
76f8421f CW |
2522 | I915_WRITE_FW(RING_TAIL(engine->mmio_base), value); |
2523 | POSTING_READ_FW(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2524 | |
2525 | /* Let the ring send IDLE messages to the GT again, | |
2526 | * and so let it sleep to conserve power when idle. | |
2527 | */ | |
76f8421f CW |
2528 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2529 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2530 | ||
2531 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2532 | } |
2533 | ||
a84c3ae1 | 2534 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2535 | u32 invalidate, u32 flush) |
881f47b6 | 2536 | { |
7e37f889 | 2537 | struct intel_ring *ring = req->ring; |
71a77e07 | 2538 | uint32_t cmd; |
b72f3acb CW |
2539 | int ret; |
2540 | ||
5fb9de1a | 2541 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2542 | if (ret) |
2543 | return ret; | |
2544 | ||
71a77e07 | 2545 | cmd = MI_FLUSH_DW; |
c033666a | 2546 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2547 | cmd += 1; |
f0a1fb10 CW |
2548 | |
2549 | /* We always require a command barrier so that subsequent | |
2550 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2551 | * wrt the contents of the write cache being flushed to memory | |
2552 | * (and thus being coherent from the CPU). | |
2553 | */ | |
2554 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2555 | ||
9a289771 JB |
2556 | /* |
2557 | * Bspec vol 1c.5 - video engine command streamer: | |
2558 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2559 | * operation is complete. This bit is only valid when the | |
2560 | * Post-Sync Operation field is a value of 1h or 3h." | |
2561 | */ | |
71a77e07 | 2562 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2563 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2564 | ||
b5321f30 CW |
2565 | intel_ring_emit(ring, cmd); |
2566 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2567 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2568 | intel_ring_emit(ring, 0); /* upper addr */ |
2569 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2570 | } else { |
b5321f30 CW |
2571 | intel_ring_emit(ring, 0); |
2572 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2573 | } |
b5321f30 | 2574 | intel_ring_advance(ring); |
b72f3acb | 2575 | return 0; |
881f47b6 XH |
2576 | } |
2577 | ||
1c7a0623 | 2578 | static int |
53fddaf7 | 2579 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2580 | u64 offset, u32 len, |
8e004efc | 2581 | unsigned dispatch_flags) |
1c7a0623 | 2582 | { |
7e37f889 | 2583 | struct intel_ring *ring = req->ring; |
b5321f30 | 2584 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2585 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2586 | int ret; |
2587 | ||
5fb9de1a | 2588 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2589 | if (ret) |
2590 | return ret; | |
2591 | ||
2592 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2593 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2594 | (dispatch_flags & I915_DISPATCH_RS ? |
2595 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2596 | intel_ring_emit(ring, lower_32_bits(offset)); |
2597 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2598 | intel_ring_emit(ring, MI_NOOP); | |
2599 | intel_ring_advance(ring); | |
1c7a0623 BW |
2600 | |
2601 | return 0; | |
2602 | } | |
2603 | ||
d7d4eedd | 2604 | static int |
53fddaf7 | 2605 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2606 | u64 offset, u32 len, |
2607 | unsigned dispatch_flags) | |
d7d4eedd | 2608 | { |
7e37f889 | 2609 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2610 | int ret; |
2611 | ||
5fb9de1a | 2612 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2613 | if (ret) |
2614 | return ret; | |
2615 | ||
b5321f30 | 2616 | intel_ring_emit(ring, |
77072258 | 2617 | MI_BATCH_BUFFER_START | |
8e004efc | 2618 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2619 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2620 | (dispatch_flags & I915_DISPATCH_RS ? | |
2621 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2622 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2623 | intel_ring_emit(ring, offset); |
2624 | intel_ring_advance(ring); | |
d7d4eedd CW |
2625 | |
2626 | return 0; | |
2627 | } | |
2628 | ||
881f47b6 | 2629 | static int |
53fddaf7 | 2630 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2631 | u64 offset, u32 len, |
8e004efc | 2632 | unsigned dispatch_flags) |
881f47b6 | 2633 | { |
7e37f889 | 2634 | struct intel_ring *ring = req->ring; |
0206e353 | 2635 | int ret; |
ab6f8e32 | 2636 | |
5fb9de1a | 2637 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2638 | if (ret) |
2639 | return ret; | |
e1f99ce6 | 2640 | |
b5321f30 | 2641 | intel_ring_emit(ring, |
d7d4eedd | 2642 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2643 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2644 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2645 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2646 | intel_ring_emit(ring, offset); |
2647 | intel_ring_advance(ring); | |
ab6f8e32 | 2648 | |
0206e353 | 2649 | return 0; |
881f47b6 XH |
2650 | } |
2651 | ||
549f7365 CW |
2652 | /* Blitter support (SandyBridge+) */ |
2653 | ||
a84c3ae1 | 2654 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2655 | u32 invalidate, u32 flush) |
8d19215b | 2656 | { |
7e37f889 | 2657 | struct intel_ring *ring = req->ring; |
71a77e07 | 2658 | uint32_t cmd; |
b72f3acb CW |
2659 | int ret; |
2660 | ||
5fb9de1a | 2661 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2662 | if (ret) |
2663 | return ret; | |
2664 | ||
71a77e07 | 2665 | cmd = MI_FLUSH_DW; |
c033666a | 2666 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2667 | cmd += 1; |
f0a1fb10 CW |
2668 | |
2669 | /* We always require a command barrier so that subsequent | |
2670 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2671 | * wrt the contents of the write cache being flushed to memory | |
2672 | * (and thus being coherent from the CPU). | |
2673 | */ | |
2674 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2675 | ||
9a289771 JB |
2676 | /* |
2677 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2678 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2679 | * operation is complete. This bit is only valid when the | |
2680 | * Post-Sync Operation field is a value of 1h or 3h." | |
2681 | */ | |
71a77e07 | 2682 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2683 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2684 | intel_ring_emit(ring, cmd); |
2685 | intel_ring_emit(ring, | |
e2f80391 | 2686 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2687 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2688 | intel_ring_emit(ring, 0); /* upper addr */ |
2689 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2690 | } else { |
b5321f30 CW |
2691 | intel_ring_emit(ring, 0); |
2692 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2693 | } |
b5321f30 | 2694 | intel_ring_advance(ring); |
fd3da6c9 | 2695 | |
b72f3acb | 2696 | return 0; |
8d19215b ZN |
2697 | } |
2698 | ||
d9a64610 TU |
2699 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2700 | struct intel_engine_cs *engine) | |
2701 | { | |
db3d4019 | 2702 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2703 | int ret, i; |
db3d4019 | 2704 | |
39df9190 | 2705 | if (!i915.semaphores) |
db3d4019 TU |
2706 | return; |
2707 | ||
2708 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { | |
91c8a326 | 2709 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
db3d4019 TU |
2710 | if (IS_ERR(obj)) { |
2711 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2712 | i915.semaphores = 0; | |
2713 | } else { | |
2714 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2715 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2716 | if (ret != 0) { | |
f8c417cd | 2717 | i915_gem_object_put(obj); |
db3d4019 TU |
2718 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); |
2719 | i915.semaphores = 0; | |
2720 | } else { | |
2721 | dev_priv->semaphore_obj = obj; | |
2722 | } | |
2723 | } | |
2724 | } | |
2725 | ||
39df9190 | 2726 | if (!i915.semaphores) |
d9a64610 TU |
2727 | return; |
2728 | ||
2729 | if (INTEL_GEN(dev_priv) >= 8) { | |
1b9e6650 TU |
2730 | u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); |
2731 | ||
d9a64610 TU |
2732 | engine->semaphore.sync_to = gen8_ring_sync; |
2733 | engine->semaphore.signal = gen8_xcs_signal; | |
1b9e6650 TU |
2734 | |
2735 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2736 | u64 ring_offset; | |
2737 | ||
2738 | if (i != engine->id) | |
2739 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2740 | else | |
2741 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2742 | ||
2743 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2744 | } | |
d9a64610 TU |
2745 | } else if (INTEL_GEN(dev_priv) >= 6) { |
2746 | engine->semaphore.sync_to = gen6_ring_sync; | |
2747 | engine->semaphore.signal = gen6_signal; | |
4b8e38a9 TU |
2748 | |
2749 | /* | |
2750 | * The current semaphore is only applied on pre-gen8 | |
2751 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2752 | * platform. So the semaphore between RCS and VCS2 is | |
2753 | * initialized as INVALID. Gen8 will initialize the | |
2754 | * sema between VCS2 and RCS later. | |
2755 | */ | |
2756 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
2757 | static const struct { | |
2758 | u32 wait_mbox; | |
2759 | i915_reg_t mbox_reg; | |
2760 | } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { | |
2761 | [RCS] = { | |
2762 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2763 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2764 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2765 | }, | |
2766 | [VCS] = { | |
2767 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2768 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2769 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2770 | }, | |
2771 | [BCS] = { | |
2772 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2773 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2774 | [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2775 | }, | |
2776 | [VECS] = { | |
2777 | [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2778 | [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2779 | [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2780 | }, | |
2781 | }; | |
2782 | u32 wait_mbox; | |
2783 | i915_reg_t mbox_reg; | |
2784 | ||
2785 | if (i == engine->id || i == VCS2) { | |
2786 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2787 | mbox_reg = GEN6_NOSYNC; | |
2788 | } else { | |
2789 | wait_mbox = sem_data[engine->id][i].wait_mbox; | |
2790 | mbox_reg = sem_data[engine->id][i].mbox_reg; | |
2791 | } | |
2792 | ||
2793 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2794 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2795 | } | |
d9a64610 TU |
2796 | } |
2797 | } | |
2798 | ||
ed003078 CW |
2799 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2800 | struct intel_engine_cs *engine) | |
2801 | { | |
c78d6061 TU |
2802 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2803 | ||
ed003078 | 2804 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2805 | engine->irq_enable = gen8_irq_enable; |
2806 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2807 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2808 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2809 | engine->irq_enable = gen6_irq_enable; |
2810 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2811 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2812 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2813 | engine->irq_enable = gen5_irq_enable; |
2814 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2815 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2816 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2817 | engine->irq_enable = i9xx_irq_enable; |
2818 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2819 | } else { |
31bb59cc CW |
2820 | engine->irq_enable = i8xx_irq_enable; |
2821 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2822 | } |
2823 | } | |
2824 | ||
06a2fe22 TU |
2825 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2826 | struct intel_engine_cs *engine) | |
2827 | { | |
1d8a1337 | 2828 | engine->init_hw = init_ring_common; |
06a2fe22 | 2829 | engine->write_tail = ring_write_tail; |
7445a2a4 | 2830 | |
6f7bef75 CW |
2831 | engine->add_request = i9xx_add_request; |
2832 | if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2833 | engine->add_request = gen6_add_request; |
6f7bef75 CW |
2834 | |
2835 | if (INTEL_GEN(dev_priv) >= 8) | |
2836 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
2837 | else if (INTEL_GEN(dev_priv) >= 6) | |
960ecaad | 2838 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
6f7bef75 | 2839 | else if (INTEL_GEN(dev_priv) >= 4) |
960ecaad | 2840 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
6f7bef75 CW |
2841 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
2842 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2843 | else | |
2844 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; | |
b9700325 | 2845 | |
ed003078 | 2846 | intel_ring_init_irq(dev_priv, engine); |
d9a64610 | 2847 | intel_ring_init_semaphores(dev_priv, engine); |
06a2fe22 TU |
2848 | } |
2849 | ||
8b3e2d36 | 2850 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2851 | { |
8b3e2d36 | 2852 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2853 | int ret; |
5c1143bb | 2854 | |
06a2fe22 TU |
2855 | intel_ring_default_vfuncs(dev_priv, engine); |
2856 | ||
61ff75ac CW |
2857 | if (HAS_L3_DPF(dev_priv)) |
2858 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2859 | |
c033666a | 2860 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2861 | engine->init_context = intel_rcs_ctx_init; |
a58c01aa | 2862 | engine->add_request = gen8_render_add_request; |
e2f80391 | 2863 | engine->flush = gen8_render_ring_flush; |
39df9190 | 2864 | if (i915.semaphores) |
e2f80391 | 2865 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2866 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2867 | engine->init_context = intel_rcs_ctx_init; |
e2f80391 | 2868 | engine->flush = gen7_render_ring_flush; |
c033666a | 2869 | if (IS_GEN6(dev_priv)) |
e2f80391 | 2870 | engine->flush = gen6_render_ring_flush; |
c033666a | 2871 | } else if (IS_GEN5(dev_priv)) { |
e2f80391 | 2872 | engine->flush = gen4_render_ring_flush; |
59465b5f | 2873 | } else { |
c033666a | 2874 | if (INTEL_GEN(dev_priv) < 4) |
e2f80391 | 2875 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2876 | else |
e2f80391 | 2877 | engine->flush = gen4_render_ring_flush; |
e2f80391 | 2878 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2879 | } |
707d9cf9 | 2880 | |
c033666a | 2881 | if (IS_HASWELL(dev_priv)) |
e2f80391 | 2882 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
6f7bef75 | 2883 | |
e2f80391 TU |
2884 | engine->init_hw = init_render_ring; |
2885 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2886 | |
acd27845 | 2887 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2888 | if (ret) |
2889 | return ret; | |
2890 | ||
f8973c21 | 2891 | if (INTEL_GEN(dev_priv) >= 6) { |
7d5ea807 CW |
2892 | ret = intel_init_pipe_control(engine, 4096); |
2893 | if (ret) | |
2894 | return ret; | |
2895 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
2896 | ret = intel_init_pipe_control(engine, I830_WA_SIZE); | |
99be1dfe DV |
2897 | if (ret) |
2898 | return ret; | |
2899 | } | |
2900 | ||
2901 | return 0; | |
5c1143bb XH |
2902 | } |
2903 | ||
8b3e2d36 | 2904 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2905 | { |
8b3e2d36 | 2906 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2907 | |
06a2fe22 TU |
2908 | intel_ring_default_vfuncs(dev_priv, engine); |
2909 | ||
c033666a | 2910 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2911 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2912 | if (IS_GEN6(dev_priv)) |
e2f80391 TU |
2913 | engine->write_tail = gen6_bsd_ring_write_tail; |
2914 | engine->flush = gen6_bsd_ring_flush; | |
c78d6061 | 2915 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2916 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2917 | } else { |
e2f80391 TU |
2918 | engine->mmio_base = BSD_RING_BASE; |
2919 | engine->flush = bsd_ring_flush; | |
8d228911 | 2920 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2921 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2922 | else |
e2f80391 | 2923 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2924 | } |
58fa3835 | 2925 | |
acd27845 | 2926 | return intel_init_ring_buffer(engine); |
5c1143bb | 2927 | } |
549f7365 | 2928 | |
845f74a7 | 2929 | /** |
62659920 | 2930 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2931 | */ |
8b3e2d36 | 2932 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2933 | { |
8b3e2d36 | 2934 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2935 | |
2936 | intel_ring_default_vfuncs(dev_priv, engine); | |
2937 | ||
e2f80391 | 2938 | engine->flush = gen6_bsd_ring_flush; |
845f74a7 | 2939 | |
acd27845 | 2940 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2941 | } |
2942 | ||
8b3e2d36 | 2943 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2944 | { |
8b3e2d36 | 2945 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2946 | |
2947 | intel_ring_default_vfuncs(dev_priv, engine); | |
2948 | ||
e2f80391 | 2949 | engine->flush = gen6_ring_flush; |
c78d6061 | 2950 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2951 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2952 | |
acd27845 | 2953 | return intel_init_ring_buffer(engine); |
549f7365 | 2954 | } |
a7b9761d | 2955 | |
8b3e2d36 | 2956 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2957 | { |
8b3e2d36 | 2958 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2959 | |
2960 | intel_ring_default_vfuncs(dev_priv, engine); | |
2961 | ||
e2f80391 | 2962 | engine->flush = gen6_ring_flush; |
abd58f01 | 2963 | |
c78d6061 | 2964 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2965 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2966 | engine->irq_enable = hsw_vebox_irq_enable; |
2967 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2968 | } |
9a8a2213 | 2969 | |
acd27845 | 2970 | return intel_init_ring_buffer(engine); |
9a8a2213 BW |
2971 | } |
2972 | ||
a7b9761d | 2973 | int |
7e37f889 | 2974 | intel_engine_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 2975 | { |
4a570db5 | 2976 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
2977 | int ret; |
2978 | ||
e2f80391 | 2979 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
2980 | return 0; |
2981 | ||
e2f80391 | 2982 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
2983 | if (ret) |
2984 | return ret; | |
2985 | ||
a84c3ae1 | 2986 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 2987 | |
e2f80391 | 2988 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
2989 | return 0; |
2990 | } | |
2991 | ||
2992 | int | |
7e37f889 | 2993 | intel_engine_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 2994 | { |
4a570db5 | 2995 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
2996 | uint32_t flush_domains; |
2997 | int ret; | |
2998 | ||
2999 | flush_domains = 0; | |
e2f80391 | 3000 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3001 | flush_domains = I915_GEM_GPU_DOMAINS; |
3002 | ||
e2f80391 | 3003 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3004 | if (ret) |
3005 | return ret; | |
3006 | ||
a84c3ae1 | 3007 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3008 | |
e2f80391 | 3009 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3010 | return 0; |
3011 | } | |
e3efda49 | 3012 | |
7e37f889 | 3013 | void intel_engine_stop(struct intel_engine_cs *engine) |
e3efda49 CW |
3014 | { |
3015 | int ret; | |
3016 | ||
117897f4 | 3017 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3018 | return; |
3019 | ||
666796da | 3020 | ret = intel_engine_idle(engine); |
f4457ae7 | 3021 | if (ret) |
e3efda49 | 3022 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3023 | engine->name, ret); |
e3efda49 | 3024 | |
0bc40be8 | 3025 | stop_ring(engine); |
e3efda49 | 3026 | } |