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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
70eac33e CW |
112 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
113 | (IS_G4X(dev) || IS_GEN5(dev))) | |
114 | cmd |= MI_INVALIDATE_ISP; | |
115 | ||
62fdfeaf EA |
116 | #if WATCH_EXEC |
117 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
118 | #endif | |
e1f99ce6 CW |
119 | if (intel_ring_begin(ring, 2) == 0) { |
120 | intel_ring_emit(ring, cmd); | |
121 | intel_ring_emit(ring, MI_NOOP); | |
122 | intel_ring_advance(ring); | |
123 | } | |
62fdfeaf | 124 | } |
8187a2b7 ZN |
125 | } |
126 | ||
78501eac | 127 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 128 | u32 value) |
d46eefa2 | 129 | { |
78501eac | 130 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 131 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
132 | } |
133 | ||
78501eac | 134 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 135 | { |
78501eac CW |
136 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
137 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 138 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
139 | |
140 | return I915_READ(acthd_reg); | |
141 | } | |
142 | ||
78501eac | 143 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 144 | { |
78501eac | 145 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 146 | struct drm_i915_gem_object *obj = ring->obj; |
8187a2b7 | 147 | u32 head; |
8187a2b7 ZN |
148 | |
149 | /* Stop the ring if it's running. */ | |
7f2ab699 | 150 | I915_WRITE_CTL(ring, 0); |
570ef608 | 151 | I915_WRITE_HEAD(ring, 0); |
78501eac | 152 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
153 | |
154 | /* Initialize the ring. */ | |
05394f39 | 155 | I915_WRITE_START(ring, obj->gtt_offset); |
570ef608 | 156 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
157 | |
158 | /* G45 ring initialization fails to reset head to zero */ | |
159 | if (head != 0) { | |
160 | DRM_ERROR("%s head not reset to zero " | |
161 | "ctl %08x head %08x tail %08x start %08x\n", | |
162 | ring->name, | |
7f2ab699 | 163 | I915_READ_CTL(ring), |
570ef608 | 164 | I915_READ_HEAD(ring), |
870e86dd | 165 | I915_READ_TAIL(ring), |
6c0e1c55 | 166 | I915_READ_START(ring)); |
8187a2b7 | 167 | |
570ef608 | 168 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
169 | |
170 | DRM_ERROR("%s head forced to zero " | |
171 | "ctl %08x head %08x tail %08x start %08x\n", | |
172 | ring->name, | |
7f2ab699 | 173 | I915_READ_CTL(ring), |
570ef608 | 174 | I915_READ_HEAD(ring), |
870e86dd | 175 | I915_READ_TAIL(ring), |
6c0e1c55 | 176 | I915_READ_START(ring)); |
8187a2b7 ZN |
177 | } |
178 | ||
7f2ab699 | 179 | I915_WRITE_CTL(ring, |
ae69b42a | 180 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
6aa56062 | 181 | | RING_REPORT_64K | RING_VALID); |
8187a2b7 | 182 | |
8187a2b7 | 183 | /* If the head is still not zero, the ring is dead */ |
176f28eb | 184 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
05394f39 | 185 | I915_READ_START(ring) != obj->gtt_offset || |
176f28eb | 186 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { |
e74cfed5 CW |
187 | DRM_ERROR("%s initialization failed " |
188 | "ctl %08x head %08x tail %08x start %08x\n", | |
189 | ring->name, | |
190 | I915_READ_CTL(ring), | |
191 | I915_READ_HEAD(ring), | |
192 | I915_READ_TAIL(ring), | |
193 | I915_READ_START(ring)); | |
194 | return -EIO; | |
8187a2b7 ZN |
195 | } |
196 | ||
78501eac CW |
197 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
198 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 199 | else { |
570ef608 | 200 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 201 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
202 | ring->space = ring->head - (ring->tail + 8); |
203 | if (ring->space < 0) | |
204 | ring->space += ring->size; | |
205 | } | |
206 | return 0; | |
207 | } | |
208 | ||
b6913e4b CW |
209 | /* |
210 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
211 | * over cache flushing. | |
212 | */ | |
213 | struct pipe_control { | |
214 | struct drm_i915_gem_object *obj; | |
215 | volatile u32 *cpu_page; | |
216 | u32 gtt_offset; | |
217 | }; | |
218 | ||
219 | static int | |
220 | init_pipe_control(struct intel_ring_buffer *ring) | |
221 | { | |
222 | struct pipe_control *pc; | |
223 | struct drm_i915_gem_object *obj; | |
224 | int ret; | |
225 | ||
226 | if (ring->private) | |
227 | return 0; | |
228 | ||
229 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
230 | if (!pc) | |
231 | return -ENOMEM; | |
232 | ||
233 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
234 | if (obj == NULL) { | |
235 | DRM_ERROR("Failed to allocate seqno page\n"); | |
236 | ret = -ENOMEM; | |
237 | goto err; | |
238 | } | |
239 | obj->agp_type = AGP_USER_CACHED_MEMORY; | |
240 | ||
241 | ret = i915_gem_object_pin(obj, 4096, true); | |
242 | if (ret) | |
243 | goto err_unref; | |
244 | ||
245 | pc->gtt_offset = obj->gtt_offset; | |
246 | pc->cpu_page = kmap(obj->pages[0]); | |
247 | if (pc->cpu_page == NULL) | |
248 | goto err_unpin; | |
249 | ||
250 | pc->obj = obj; | |
251 | ring->private = pc; | |
252 | return 0; | |
253 | ||
254 | err_unpin: | |
255 | i915_gem_object_unpin(obj); | |
256 | err_unref: | |
257 | drm_gem_object_unreference(&obj->base); | |
258 | err: | |
259 | kfree(pc); | |
260 | return ret; | |
261 | } | |
262 | ||
263 | static void | |
264 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
265 | { | |
266 | struct pipe_control *pc = ring->private; | |
267 | struct drm_i915_gem_object *obj; | |
268 | ||
269 | if (!ring->private) | |
270 | return; | |
271 | ||
272 | obj = pc->obj; | |
273 | kunmap(obj->pages[0]); | |
274 | i915_gem_object_unpin(obj); | |
275 | drm_gem_object_unreference(&obj->base); | |
276 | ||
277 | kfree(pc); | |
278 | ring->private = NULL; | |
279 | } | |
280 | ||
78501eac | 281 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 282 | { |
78501eac CW |
283 | struct drm_device *dev = ring->dev; |
284 | int ret = init_ring_common(ring); | |
a69ffdbf | 285 | |
a6c45cf0 | 286 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac CW |
287 | drm_i915_private_t *dev_priv = dev->dev_private; |
288 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; | |
a69ffdbf ZW |
289 | if (IS_GEN6(dev)) |
290 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
291 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 292 | } |
78501eac | 293 | |
b6913e4b CW |
294 | if (HAS_PIPE_CONTROL(dev)) { |
295 | ret = init_pipe_control(ring); | |
296 | if (ret) | |
297 | return ret; | |
298 | } | |
299 | ||
8187a2b7 ZN |
300 | return ret; |
301 | } | |
302 | ||
b6913e4b CW |
303 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
304 | { | |
305 | if (!ring->private) | |
306 | return; | |
307 | ||
308 | cleanup_pipe_control(ring); | |
309 | } | |
310 | ||
78501eac | 311 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
8187a2b7 | 312 | do { \ |
78501eac | 313 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 314 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
78501eac CW |
315 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
316 | intel_ring_emit(ring__, 0); \ | |
317 | intel_ring_emit(ring__, 0); \ | |
8187a2b7 | 318 | } while (0) |
62fdfeaf EA |
319 | |
320 | /** | |
321 | * Creates a new sequence number, emitting a write of it to the status page | |
322 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
323 | * | |
324 | * Must be called with struct_lock held. | |
325 | * | |
326 | * Returned sequence numbers are nonzero on success. | |
327 | */ | |
3cce469c | 328 | static int |
78501eac | 329 | render_ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 330 | u32 *result) |
62fdfeaf | 331 | { |
78501eac | 332 | struct drm_device *dev = ring->dev; |
3cce469c | 333 | u32 seqno = i915_gem_get_seqno(dev); |
b6913e4b | 334 | struct pipe_control *pc = ring->private; |
3cce469c | 335 | int ret; |
ca76482e ZW |
336 | |
337 | if (IS_GEN6(dev)) { | |
3cce469c CW |
338 | ret = intel_ring_begin(ring, 6); |
339 | if (ret) | |
340 | return ret; | |
341 | ||
342 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3); | |
343 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE | | |
344 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
345 | PIPE_CONTROL_NOTIFY); | |
b6913e4b | 346 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
3cce469c CW |
347 | intel_ring_emit(ring, seqno); |
348 | intel_ring_emit(ring, 0); | |
349 | intel_ring_emit(ring, 0); | |
ca76482e | 350 | } else if (HAS_PIPE_CONTROL(dev)) { |
b6913e4b | 351 | u32 scratch_addr = pc->gtt_offset + 128; |
62fdfeaf EA |
352 | |
353 | /* | |
354 | * Workaround qword write incoherence by flushing the | |
355 | * PIPE_NOTIFY buffers out to memory before requesting | |
356 | * an interrupt. | |
357 | */ | |
3cce469c CW |
358 | ret = intel_ring_begin(ring, 32); |
359 | if (ret) | |
360 | return ret; | |
361 | ||
362 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
363 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
b6913e4b | 364 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
3cce469c CW |
365 | intel_ring_emit(ring, seqno); |
366 | intel_ring_emit(ring, 0); | |
367 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
368 | scratch_addr += 128; /* write to separate cachelines */ | |
369 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
370 | scratch_addr += 128; | |
371 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
372 | scratch_addr += 128; | |
373 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
374 | scratch_addr += 128; | |
375 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
376 | scratch_addr += 128; | |
377 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
378 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
379 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
380 | PIPE_CONTROL_NOTIFY); | |
b6913e4b | 381 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
3cce469c CW |
382 | intel_ring_emit(ring, seqno); |
383 | intel_ring_emit(ring, 0); | |
62fdfeaf | 384 | } else { |
3cce469c CW |
385 | ret = intel_ring_begin(ring, 4); |
386 | if (ret) | |
387 | return ret; | |
62fdfeaf | 388 | |
3cce469c CW |
389 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
390 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
391 | intel_ring_emit(ring, seqno); | |
392 | ||
393 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
62fdfeaf | 394 | } |
3cce469c CW |
395 | |
396 | intel_ring_advance(ring); | |
397 | *result = seqno; | |
398 | return 0; | |
62fdfeaf EA |
399 | } |
400 | ||
8187a2b7 | 401 | static u32 |
78501eac | 402 | render_ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 403 | { |
78501eac | 404 | struct drm_device *dev = ring->dev; |
b6913e4b CW |
405 | if (HAS_PIPE_CONTROL(dev)) { |
406 | struct pipe_control *pc = ring->private; | |
407 | return pc->cpu_page[0]; | |
408 | } else | |
8187a2b7 ZN |
409 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
410 | } | |
411 | ||
412 | static void | |
78501eac | 413 | render_ring_get_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 414 | { |
78501eac | 415 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
416 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
417 | unsigned long irqflags; | |
418 | ||
419 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 420 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
421 | if (HAS_PCH_SPLIT(dev)) |
422 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
423 | else | |
424 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
425 | } | |
426 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
427 | } | |
428 | ||
8187a2b7 | 429 | static void |
78501eac | 430 | render_ring_put_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 431 | { |
78501eac | 432 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
433 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
434 | unsigned long irqflags; | |
435 | ||
436 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
437 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
438 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
439 | if (HAS_PCH_SPLIT(dev)) |
440 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
441 | else | |
442 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
443 | } | |
444 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
445 | } | |
446 | ||
78501eac | 447 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 448 | { |
78501eac CW |
449 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
450 | u32 mmio = IS_GEN6(ring->dev) ? | |
451 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
452 | RING_HWS_PGA(ring->mmio_base); | |
453 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
454 | POSTING_READ(mmio); | |
8187a2b7 ZN |
455 | } |
456 | ||
ab6f8e32 | 457 | static void |
78501eac CW |
458 | bsd_ring_flush(struct intel_ring_buffer *ring, |
459 | u32 invalidate_domains, | |
460 | u32 flush_domains) | |
d1b851fc | 461 | { |
e1f99ce6 CW |
462 | if (intel_ring_begin(ring, 2) == 0) { |
463 | intel_ring_emit(ring, MI_FLUSH); | |
464 | intel_ring_emit(ring, MI_NOOP); | |
465 | intel_ring_advance(ring); | |
466 | } | |
d1b851fc ZN |
467 | } |
468 | ||
3cce469c | 469 | static int |
78501eac | 470 | ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 471 | u32 *result) |
d1b851fc ZN |
472 | { |
473 | u32 seqno; | |
3cce469c CW |
474 | int ret; |
475 | ||
476 | ret = intel_ring_begin(ring, 4); | |
477 | if (ret) | |
478 | return ret; | |
6f392d54 | 479 | |
78501eac | 480 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 481 | |
3cce469c CW |
482 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
483 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
484 | intel_ring_emit(ring, seqno); | |
485 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
486 | intel_ring_advance(ring); | |
d1b851fc ZN |
487 | |
488 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
3cce469c CW |
489 | *result = seqno; |
490 | return 0; | |
d1b851fc ZN |
491 | } |
492 | ||
d1b851fc | 493 | static void |
78501eac | 494 | bsd_ring_get_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
495 | { |
496 | /* do nothing */ | |
497 | } | |
498 | static void | |
78501eac | 499 | bsd_ring_put_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
500 | { |
501 | /* do nothing */ | |
502 | } | |
503 | ||
504 | static u32 | |
78501eac | 505 | ring_status_page_get_seqno(struct intel_ring_buffer *ring) |
d1b851fc ZN |
506 | { |
507 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
508 | } | |
509 | ||
510 | static int | |
c4e7a414 | 511 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 512 | { |
e1f99ce6 | 513 | int ret; |
78501eac | 514 | |
e1f99ce6 CW |
515 | ret = intel_ring_begin(ring, 2); |
516 | if (ret) | |
517 | return ret; | |
518 | ||
78501eac | 519 | intel_ring_emit(ring, |
c4e7a414 | 520 | MI_BATCH_BUFFER_START | (2 << 6) | |
78501eac | 521 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 522 | intel_ring_emit(ring, offset); |
78501eac CW |
523 | intel_ring_advance(ring); |
524 | ||
d1b851fc ZN |
525 | return 0; |
526 | } | |
527 | ||
8187a2b7 | 528 | static int |
78501eac | 529 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 530 | u32 offset, u32 len) |
62fdfeaf | 531 | { |
78501eac | 532 | struct drm_device *dev = ring->dev; |
62fdfeaf | 533 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4e7a414 | 534 | int ret; |
62fdfeaf | 535 | |
6f392d54 | 536 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf | 537 | |
c4e7a414 CW |
538 | if (IS_I830(dev) || IS_845G(dev)) { |
539 | ret = intel_ring_begin(ring, 4); | |
540 | if (ret) | |
541 | return ret; | |
62fdfeaf | 542 | |
c4e7a414 CW |
543 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
544 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
545 | intel_ring_emit(ring, offset + len - 8); | |
546 | intel_ring_emit(ring, 0); | |
547 | } else { | |
548 | ret = intel_ring_begin(ring, 2); | |
549 | if (ret) | |
550 | return ret; | |
e1f99ce6 | 551 | |
c4e7a414 CW |
552 | if (INTEL_INFO(dev)->gen >= 4) { |
553 | intel_ring_emit(ring, | |
554 | MI_BATCH_BUFFER_START | (2 << 6) | | |
555 | MI_BATCH_NON_SECURE_I965); | |
556 | intel_ring_emit(ring, offset); | |
62fdfeaf | 557 | } else { |
c4e7a414 CW |
558 | intel_ring_emit(ring, |
559 | MI_BATCH_BUFFER_START | (2 << 6)); | |
560 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
62fdfeaf EA |
561 | } |
562 | } | |
c4e7a414 | 563 | intel_ring_advance(ring); |
62fdfeaf | 564 | |
62fdfeaf EA |
565 | return 0; |
566 | } | |
567 | ||
78501eac | 568 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 569 | { |
78501eac | 570 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 571 | struct drm_i915_gem_object *obj; |
62fdfeaf | 572 | |
8187a2b7 ZN |
573 | obj = ring->status_page.obj; |
574 | if (obj == NULL) | |
62fdfeaf | 575 | return; |
62fdfeaf | 576 | |
05394f39 | 577 | kunmap(obj->pages[0]); |
62fdfeaf | 578 | i915_gem_object_unpin(obj); |
05394f39 | 579 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 580 | ring->status_page.obj = NULL; |
62fdfeaf EA |
581 | |
582 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
583 | } |
584 | ||
78501eac | 585 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 586 | { |
78501eac | 587 | struct drm_device *dev = ring->dev; |
62fdfeaf | 588 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 589 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
590 | int ret; |
591 | ||
62fdfeaf EA |
592 | obj = i915_gem_alloc_object(dev, 4096); |
593 | if (obj == NULL) { | |
594 | DRM_ERROR("Failed to allocate status page\n"); | |
595 | ret = -ENOMEM; | |
596 | goto err; | |
597 | } | |
05394f39 | 598 | obj->agp_type = AGP_USER_CACHED_MEMORY; |
62fdfeaf | 599 | |
75e9e915 | 600 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 601 | if (ret != 0) { |
62fdfeaf EA |
602 | goto err_unref; |
603 | } | |
604 | ||
05394f39 CW |
605 | ring->status_page.gfx_addr = obj->gtt_offset; |
606 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 607 | if (ring->status_page.page_addr == NULL) { |
62fdfeaf | 608 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
609 | goto err_unpin; |
610 | } | |
8187a2b7 ZN |
611 | ring->status_page.obj = obj; |
612 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 613 | |
78501eac | 614 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
615 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
616 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
617 | |
618 | return 0; | |
619 | ||
620 | err_unpin: | |
621 | i915_gem_object_unpin(obj); | |
622 | err_unref: | |
05394f39 | 623 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 624 | err: |
8187a2b7 | 625 | return ret; |
62fdfeaf EA |
626 | } |
627 | ||
8187a2b7 | 628 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 629 | struct intel_ring_buffer *ring) |
62fdfeaf | 630 | { |
05394f39 | 631 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
632 | int ret; |
633 | ||
8187a2b7 | 634 | ring->dev = dev; |
23bc5982 CW |
635 | INIT_LIST_HEAD(&ring->active_list); |
636 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 637 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 638 | |
8187a2b7 | 639 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 640 | ret = init_status_page(ring); |
8187a2b7 ZN |
641 | if (ret) |
642 | return ret; | |
643 | } | |
62fdfeaf | 644 | |
8187a2b7 | 645 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
646 | if (obj == NULL) { |
647 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 648 | ret = -ENOMEM; |
dd785e35 | 649 | goto err_hws; |
62fdfeaf | 650 | } |
62fdfeaf | 651 | |
05394f39 | 652 | ring->obj = obj; |
8187a2b7 | 653 | |
75e9e915 | 654 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
655 | if (ret) |
656 | goto err_unref; | |
62fdfeaf | 657 | |
8187a2b7 | 658 | ring->map.size = ring->size; |
05394f39 | 659 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
62fdfeaf EA |
660 | ring->map.type = 0; |
661 | ring->map.flags = 0; | |
662 | ring->map.mtrr = 0; | |
663 | ||
664 | drm_core_ioremap_wc(&ring->map, dev); | |
665 | if (ring->map.handle == NULL) { | |
666 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 667 | ret = -EINVAL; |
dd785e35 | 668 | goto err_unpin; |
62fdfeaf EA |
669 | } |
670 | ||
8187a2b7 | 671 | ring->virtual_start = ring->map.handle; |
78501eac | 672 | ret = ring->init(ring); |
dd785e35 CW |
673 | if (ret) |
674 | goto err_unmap; | |
62fdfeaf | 675 | |
c584fe47 | 676 | return 0; |
dd785e35 CW |
677 | |
678 | err_unmap: | |
679 | drm_core_ioremapfree(&ring->map, dev); | |
680 | err_unpin: | |
681 | i915_gem_object_unpin(obj); | |
682 | err_unref: | |
05394f39 CW |
683 | drm_gem_object_unreference(&obj->base); |
684 | ring->obj = NULL; | |
dd785e35 | 685 | err_hws: |
78501eac | 686 | cleanup_status_page(ring); |
8187a2b7 | 687 | return ret; |
62fdfeaf EA |
688 | } |
689 | ||
78501eac | 690 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 691 | { |
33626e6a CW |
692 | struct drm_i915_private *dev_priv; |
693 | int ret; | |
694 | ||
05394f39 | 695 | if (ring->obj == NULL) |
62fdfeaf EA |
696 | return; |
697 | ||
33626e6a CW |
698 | /* Disable the ring buffer. The ring must be idle at this point */ |
699 | dev_priv = ring->dev->dev_private; | |
700 | ret = intel_wait_ring_buffer(ring, ring->size - 8); | |
701 | I915_WRITE_CTL(ring, 0); | |
702 | ||
78501eac | 703 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 704 | |
05394f39 CW |
705 | i915_gem_object_unpin(ring->obj); |
706 | drm_gem_object_unreference(&ring->obj->base); | |
707 | ring->obj = NULL; | |
78501eac | 708 | |
8d19215b ZN |
709 | if (ring->cleanup) |
710 | ring->cleanup(ring); | |
711 | ||
78501eac | 712 | cleanup_status_page(ring); |
62fdfeaf EA |
713 | } |
714 | ||
78501eac | 715 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 716 | { |
8187a2b7 | 717 | unsigned int *virt; |
62fdfeaf | 718 | int rem; |
8187a2b7 | 719 | rem = ring->size - ring->tail; |
62fdfeaf | 720 | |
8187a2b7 | 721 | if (ring->space < rem) { |
78501eac | 722 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
723 | if (ret) |
724 | return ret; | |
725 | } | |
62fdfeaf | 726 | |
8187a2b7 | 727 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
728 | rem /= 8; |
729 | while (rem--) { | |
62fdfeaf | 730 | *virt++ = MI_NOOP; |
1741dd4a CW |
731 | *virt++ = MI_NOOP; |
732 | } | |
62fdfeaf | 733 | |
8187a2b7 | 734 | ring->tail = 0; |
43ed340a | 735 | ring->space = ring->head - 8; |
62fdfeaf EA |
736 | |
737 | return 0; | |
738 | } | |
739 | ||
78501eac | 740 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 741 | { |
78501eac | 742 | struct drm_device *dev = ring->dev; |
cae5852d | 743 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 744 | unsigned long end; |
6aa56062 CW |
745 | u32 head; |
746 | ||
747 | head = intel_read_status_page(ring, 4); | |
748 | if (head) { | |
749 | ring->head = head & HEAD_ADDR; | |
750 | ring->space = ring->head - (ring->tail + 8); | |
751 | if (ring->space < 0) | |
752 | ring->space += ring->size; | |
753 | if (ring->space >= n) | |
754 | return 0; | |
755 | } | |
62fdfeaf EA |
756 | |
757 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
758 | end = jiffies + 3 * HZ; |
759 | do { | |
570ef608 | 760 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
761 | ring->space = ring->head - (ring->tail + 8); |
762 | if (ring->space < 0) | |
8187a2b7 | 763 | ring->space += ring->size; |
62fdfeaf | 764 | if (ring->space >= n) { |
78501eac | 765 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
766 | return 0; |
767 | } | |
768 | ||
769 | if (dev->primary->master) { | |
770 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
771 | if (master_priv->sarea_priv) | |
772 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
773 | } | |
d1b851fc | 774 | |
e60a0b10 | 775 | msleep(1); |
f4e0b29b CW |
776 | if (atomic_read(&dev_priv->mm.wedged)) |
777 | return -EAGAIN; | |
8187a2b7 ZN |
778 | } while (!time_after(jiffies, end)); |
779 | trace_i915_ring_wait_end (dev); | |
780 | return -EBUSY; | |
781 | } | |
62fdfeaf | 782 | |
e1f99ce6 CW |
783 | int intel_ring_begin(struct intel_ring_buffer *ring, |
784 | int num_dwords) | |
8187a2b7 | 785 | { |
be26a10b | 786 | int n = 4*num_dwords; |
e1f99ce6 | 787 | int ret; |
78501eac | 788 | |
e1f99ce6 CW |
789 | if (unlikely(ring->tail + n > ring->size)) { |
790 | ret = intel_wrap_ring_buffer(ring); | |
791 | if (unlikely(ret)) | |
792 | return ret; | |
793 | } | |
78501eac | 794 | |
e1f99ce6 CW |
795 | if (unlikely(ring->space < n)) { |
796 | ret = intel_wait_ring_buffer(ring, n); | |
797 | if (unlikely(ret)) | |
798 | return ret; | |
799 | } | |
d97ed339 CW |
800 | |
801 | ring->space -= n; | |
e1f99ce6 | 802 | return 0; |
8187a2b7 | 803 | } |
62fdfeaf | 804 | |
78501eac | 805 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 806 | { |
d97ed339 | 807 | ring->tail &= ring->size - 1; |
78501eac | 808 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 809 | } |
62fdfeaf | 810 | |
e070868e | 811 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 812 | .name = "render ring", |
9220434a | 813 | .id = RING_RENDER, |
333e9fe9 | 814 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 815 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 816 | .init = init_render_ring, |
297b0c5b | 817 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
818 | .flush = render_ring_flush, |
819 | .add_request = render_ring_add_request, | |
f787a5f5 | 820 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
821 | .user_irq_get = render_ring_get_user_irq, |
822 | .user_irq_put = render_ring_put_user_irq, | |
78501eac | 823 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
b6913e4b | 824 | .cleanup = render_ring_cleanup, |
8187a2b7 | 825 | }; |
d1b851fc ZN |
826 | |
827 | /* ring buffer for bit-stream decoder */ | |
828 | ||
e070868e | 829 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 830 | .name = "bsd ring", |
9220434a | 831 | .id = RING_BSD, |
333e9fe9 | 832 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 833 | .size = 32 * PAGE_SIZE, |
78501eac | 834 | .init = init_ring_common, |
297b0c5b | 835 | .write_tail = ring_write_tail, |
d1b851fc | 836 | .flush = bsd_ring_flush, |
549f7365 CW |
837 | .add_request = ring_add_request, |
838 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
839 | .user_irq_get = bsd_ring_get_user_irq, |
840 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 841 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 842 | }; |
5c1143bb | 843 | |
881f47b6 | 844 | |
78501eac | 845 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 846 | u32 value) |
881f47b6 | 847 | { |
78501eac | 848 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
849 | |
850 | /* Every tail move must follow the sequence below */ | |
851 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
852 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
853 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
854 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
855 | ||
856 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
857 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
858 | 50)) | |
859 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
860 | ||
870e86dd | 861 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
862 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
863 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
864 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
865 | } | |
866 | ||
78501eac | 867 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
868 | u32 invalidate_domains, |
869 | u32 flush_domains) | |
881f47b6 | 870 | { |
e1f99ce6 CW |
871 | if (intel_ring_begin(ring, 4) == 0) { |
872 | intel_ring_emit(ring, MI_FLUSH_DW); | |
873 | intel_ring_emit(ring, 0); | |
874 | intel_ring_emit(ring, 0); | |
875 | intel_ring_emit(ring, 0); | |
876 | intel_ring_advance(ring); | |
877 | } | |
881f47b6 XH |
878 | } |
879 | ||
880 | static int | |
78501eac | 881 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 882 | u32 offset, u32 len) |
881f47b6 | 883 | { |
e1f99ce6 | 884 | int ret; |
ab6f8e32 | 885 | |
e1f99ce6 CW |
886 | ret = intel_ring_begin(ring, 2); |
887 | if (ret) | |
888 | return ret; | |
889 | ||
78501eac | 890 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
ab6f8e32 | 891 | /* bit0-7 is the length on GEN6+ */ |
c4e7a414 | 892 | intel_ring_emit(ring, offset); |
78501eac | 893 | intel_ring_advance(ring); |
ab6f8e32 | 894 | |
881f47b6 XH |
895 | return 0; |
896 | } | |
897 | ||
898 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 899 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
900 | .name = "gen6 bsd ring", |
901 | .id = RING_BSD, | |
333e9fe9 | 902 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 903 | .size = 32 * PAGE_SIZE, |
78501eac | 904 | .init = init_ring_common, |
297b0c5b | 905 | .write_tail = gen6_bsd_ring_write_tail, |
549f7365 CW |
906 | .flush = gen6_ring_flush, |
907 | .add_request = ring_add_request, | |
908 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
909 | .user_irq_get = bsd_ring_get_user_irq, |
910 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 911 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
549f7365 CW |
912 | }; |
913 | ||
914 | /* Blitter support (SandyBridge+) */ | |
915 | ||
916 | static void | |
78501eac | 917 | blt_ring_get_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
918 | { |
919 | /* do nothing */ | |
920 | } | |
921 | static void | |
78501eac | 922 | blt_ring_put_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
923 | { |
924 | /* do nothing */ | |
925 | } | |
926 | ||
8d19215b ZN |
927 | |
928 | /* Workaround for some stepping of SNB, | |
929 | * each time when BLT engine ring tail moved, | |
930 | * the first command in the ring to be parsed | |
931 | * should be MI_BATCH_BUFFER_START | |
932 | */ | |
933 | #define NEED_BLT_WORKAROUND(dev) \ | |
934 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) | |
935 | ||
936 | static inline struct drm_i915_gem_object * | |
937 | to_blt_workaround(struct intel_ring_buffer *ring) | |
938 | { | |
939 | return ring->private; | |
940 | } | |
941 | ||
942 | static int blt_ring_init(struct intel_ring_buffer *ring) | |
943 | { | |
944 | if (NEED_BLT_WORKAROUND(ring->dev)) { | |
945 | struct drm_i915_gem_object *obj; | |
27153f72 | 946 | u32 *ptr; |
8d19215b ZN |
947 | int ret; |
948 | ||
05394f39 | 949 | obj = i915_gem_alloc_object(ring->dev, 4096); |
8d19215b ZN |
950 | if (obj == NULL) |
951 | return -ENOMEM; | |
952 | ||
05394f39 | 953 | ret = i915_gem_object_pin(obj, 4096, true); |
8d19215b ZN |
954 | if (ret) { |
955 | drm_gem_object_unreference(&obj->base); | |
956 | return ret; | |
957 | } | |
958 | ||
959 | ptr = kmap(obj->pages[0]); | |
27153f72 CW |
960 | *ptr++ = MI_BATCH_BUFFER_END; |
961 | *ptr++ = MI_NOOP; | |
8d19215b ZN |
962 | kunmap(obj->pages[0]); |
963 | ||
05394f39 | 964 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
8d19215b | 965 | if (ret) { |
05394f39 | 966 | i915_gem_object_unpin(obj); |
8d19215b ZN |
967 | drm_gem_object_unreference(&obj->base); |
968 | return ret; | |
969 | } | |
970 | ||
971 | ring->private = obj; | |
972 | } | |
973 | ||
974 | return init_ring_common(ring); | |
975 | } | |
976 | ||
977 | static int blt_ring_begin(struct intel_ring_buffer *ring, | |
978 | int num_dwords) | |
979 | { | |
980 | if (ring->private) { | |
981 | int ret = intel_ring_begin(ring, num_dwords+2); | |
982 | if (ret) | |
983 | return ret; | |
984 | ||
985 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); | |
986 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); | |
987 | ||
988 | return 0; | |
989 | } else | |
990 | return intel_ring_begin(ring, 4); | |
991 | } | |
992 | ||
993 | static void blt_ring_flush(struct intel_ring_buffer *ring, | |
994 | u32 invalidate_domains, | |
995 | u32 flush_domains) | |
996 | { | |
997 | if (blt_ring_begin(ring, 4) == 0) { | |
998 | intel_ring_emit(ring, MI_FLUSH_DW); | |
999 | intel_ring_emit(ring, 0); | |
1000 | intel_ring_emit(ring, 0); | |
1001 | intel_ring_emit(ring, 0); | |
1002 | intel_ring_advance(ring); | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | static int | |
1007 | blt_ring_add_request(struct intel_ring_buffer *ring, | |
1008 | u32 *result) | |
1009 | { | |
1010 | u32 seqno; | |
1011 | int ret; | |
1012 | ||
1013 | ret = blt_ring_begin(ring, 4); | |
1014 | if (ret) | |
1015 | return ret; | |
1016 | ||
1017 | seqno = i915_gem_get_seqno(ring->dev); | |
1018 | ||
1019 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
1020 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1021 | intel_ring_emit(ring, seqno); | |
1022 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1023 | intel_ring_advance(ring); | |
1024 | ||
1025 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
1026 | *result = seqno; | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) | |
1031 | { | |
1032 | if (!ring->private) | |
1033 | return; | |
1034 | ||
1035 | i915_gem_object_unpin(ring->private); | |
1036 | drm_gem_object_unreference(ring->private); | |
1037 | ring->private = NULL; | |
1038 | } | |
1039 | ||
549f7365 CW |
1040 | static const struct intel_ring_buffer gen6_blt_ring = { |
1041 | .name = "blt ring", | |
1042 | .id = RING_BLT, | |
1043 | .mmio_base = BLT_RING_BASE, | |
1044 | .size = 32 * PAGE_SIZE, | |
8d19215b | 1045 | .init = blt_ring_init, |
297b0c5b | 1046 | .write_tail = ring_write_tail, |
8d19215b ZN |
1047 | .flush = blt_ring_flush, |
1048 | .add_request = blt_ring_add_request, | |
549f7365 CW |
1049 | .get_seqno = ring_status_page_get_seqno, |
1050 | .user_irq_get = blt_ring_get_user_irq, | |
1051 | .user_irq_put = blt_ring_put_user_irq, | |
78501eac | 1052 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
8d19215b | 1053 | .cleanup = blt_ring_cleanup, |
881f47b6 XH |
1054 | }; |
1055 | ||
5c1143bb XH |
1056 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1057 | { | |
1058 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1059 | ||
1060 | dev_priv->render_ring = render_ring; | |
1061 | ||
1062 | if (!I915_NEED_GFX_HWS(dev)) { | |
1063 | dev_priv->render_ring.status_page.page_addr | |
1064 | = dev_priv->status_page_dmah->vaddr; | |
1065 | memset(dev_priv->render_ring.status_page.page_addr, | |
1066 | 0, PAGE_SIZE); | |
1067 | } | |
1068 | ||
1069 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
1070 | } | |
1071 | ||
1072 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
1073 | { | |
1074 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1075 | ||
881f47b6 XH |
1076 | if (IS_GEN6(dev)) |
1077 | dev_priv->bsd_ring = gen6_bsd_ring; | |
1078 | else | |
1079 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
1080 | |
1081 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
1082 | } | |
549f7365 CW |
1083 | |
1084 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1085 | { | |
1086 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1087 | ||
1088 | dev_priv->blt_ring = gen6_blt_ring; | |
1089 | ||
1090 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
1091 | } |