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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b72f3acb | 61 | static int |
7c9cf4e3 | 62 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 63 | { |
7e37f889 | 64 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
65 | u32 cmd; |
66 | int ret; | |
67 | ||
68 | cmd = MI_FLUSH; | |
46f0f8d1 | 69 | |
7c9cf4e3 | 70 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
71 | cmd |= MI_READ_FLUSH; |
72 | ||
5fb9de1a | 73 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
74 | if (ret) |
75 | return ret; | |
76 | ||
b5321f30 CW |
77 | intel_ring_emit(ring, cmd); |
78 | intel_ring_emit(ring, MI_NOOP); | |
79 | intel_ring_advance(ring); | |
46f0f8d1 CW |
80 | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static int | |
7c9cf4e3 | 85 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 86 | { |
7e37f889 | 87 | struct intel_ring *ring = req->ring; |
6f392d54 | 88 | u32 cmd; |
b72f3acb | 89 | int ret; |
6f392d54 | 90 | |
36d527de CW |
91 | /* |
92 | * read/write caches: | |
93 | * | |
94 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
95 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
96 | * also flushed at 2d versus 3d pipeline switches. | |
97 | * | |
98 | * read-only caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
101 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
102 | * | |
103 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
104 | * | |
105 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
106 | * invalidated when MI_EXE_FLUSH is set. | |
107 | * | |
108 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
109 | * invalidated with every MI_FLUSH. | |
110 | * | |
111 | * TLBs: | |
112 | * | |
113 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
114 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
115 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
116 | * are flushed at any MI_FLUSH. | |
117 | */ | |
118 | ||
b5321f30 | 119 | cmd = MI_FLUSH; |
7c9cf4e3 | 120 | if (mode & EMIT_INVALIDATE) { |
36d527de | 121 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
122 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
123 | cmd |= MI_INVALIDATE_ISP; | |
124 | } | |
70eac33e | 125 | |
5fb9de1a | 126 | ret = intel_ring_begin(req, 2); |
36d527de CW |
127 | if (ret) |
128 | return ret; | |
b72f3acb | 129 | |
b5321f30 CW |
130 | intel_ring_emit(ring, cmd); |
131 | intel_ring_emit(ring, MI_NOOP); | |
132 | intel_ring_advance(ring); | |
b72f3acb CW |
133 | |
134 | return 0; | |
8187a2b7 ZN |
135 | } |
136 | ||
8d315287 JB |
137 | /** |
138 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
139 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
140 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
141 | * | |
142 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
143 | * produced by non-pipelined state commands), software needs to first | |
144 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
145 | * 0. | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
148 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
149 | * | |
150 | * And the workaround for these two requires this workaround first: | |
151 | * | |
152 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
153 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
154 | * flushes. | |
155 | * | |
156 | * And this last workaround is tricky because of the requirements on | |
157 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
158 | * volume 2 part 1: | |
159 | * | |
160 | * "1 of the following must also be set: | |
161 | * - Render Target Cache Flush Enable ([12] of DW1) | |
162 | * - Depth Cache Flush Enable ([0] of DW1) | |
163 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
164 | * - Depth Stall ([13] of DW1) | |
165 | * - Post-Sync Operation ([13] of DW1) | |
166 | * - Notify Enable ([8] of DW1)" | |
167 | * | |
168 | * The cache flushes require the workaround flush that triggered this | |
169 | * one, so we can't use it. Depth stall would trigger the same. | |
170 | * Post-sync nonzero is what triggered this second workaround, so we | |
171 | * can't use that one either. Notify enable is IRQs, which aren't | |
172 | * really our business. That leaves only stall at scoreboard. | |
173 | */ | |
174 | static int | |
f2cf1fcc | 175 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 176 | { |
7e37f889 | 177 | struct intel_ring *ring = req->ring; |
b5321f30 | 178 | u32 scratch_addr = |
bde13ebd | 179 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 JB |
180 | int ret; |
181 | ||
5fb9de1a | 182 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
183 | if (ret) |
184 | return ret; | |
185 | ||
b5321f30 CW |
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
8d315287 | 194 | |
5fb9de1a | 195 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
196 | if (ret) |
197 | return ret; | |
198 | ||
b5321f30 CW |
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
8d315287 JB |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
7c9cf4e3 | 211 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 212 | { |
7e37f889 | 213 | struct intel_ring *ring = req->ring; |
b5321f30 | 214 | u32 scratch_addr = |
bde13ebd | 215 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 | 216 | u32 flags = 0; |
8d315287 JB |
217 | int ret; |
218 | ||
b3111509 | 219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 220 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
221 | if (ret) |
222 | return ret; | |
223 | ||
8d315287 JB |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance | |
226 | * impact. | |
227 | */ | |
7c9cf4e3 | 228 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
231 | /* | |
232 | * Ensure that any following seqno writes only happen | |
233 | * when the render cache is indeed flushed. | |
234 | */ | |
97f209bc | 235 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 236 | } |
7c9cf4e3 | 237 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
244 | /* | |
245 | * TLB invalidate requires a post-sync write. | |
246 | */ | |
3ac78313 | 247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 248 | } |
8d315287 | 249 | |
5fb9de1a | 250 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
251 | if (ret) |
252 | return ret; | |
253 | ||
b5321f30 CW |
254 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
255 | intel_ring_emit(ring, flags); | |
256 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | intel_ring_emit(ring, 0); | |
258 | intel_ring_advance(ring); | |
8d315287 JB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
f3987631 | 263 | static int |
f2cf1fcc | 264 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 265 | { |
7e37f889 | 266 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
267 | int ret; |
268 | ||
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
270 | if (ret) |
271 | return ret; | |
272 | ||
b5321f30 CW |
273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(ring, | |
275 | PIPE_CONTROL_CS_STALL | | |
276 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_emit(ring, 0); | |
279 | intel_ring_advance(ring); | |
f3987631 PZ |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
4772eaeb | 284 | static int |
7c9cf4e3 | 285 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 286 | { |
7e37f889 | 287 | struct intel_ring *ring = req->ring; |
b5321f30 | 288 | u32 scratch_addr = |
bde13ebd | 289 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
4772eaeb | 290 | u32 flags = 0; |
4772eaeb PZ |
291 | int ret; |
292 | ||
f3987631 PZ |
293 | /* |
294 | * Ensure that any following seqno writes only happen when the render | |
295 | * cache is indeed flushed. | |
296 | * | |
297 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
298 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
299 | * don't try to be clever and just set it unconditionally. | |
300 | */ | |
301 | flags |= PIPE_CONTROL_CS_STALL; | |
302 | ||
4772eaeb PZ |
303 | /* Just flush everything. Experiments have shown that reducing the |
304 | * number of bits based on the write domains has little performance | |
305 | * impact. | |
306 | */ | |
7c9cf4e3 | 307 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
308 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
309 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 310 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 311 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 312 | } |
7c9cf4e3 | 313 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
314 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
315 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
317 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
318 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
319 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 320 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
321 | /* |
322 | * TLB invalidate requires a post-sync write. | |
323 | */ | |
324 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 325 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 326 | |
add284a3 CW |
327 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
328 | ||
f3987631 PZ |
329 | /* Workaround: we must issue a pipe_control with CS-stall bit |
330 | * set before a pipe_control command that has the state cache | |
331 | * invalidate bit set. */ | |
f2cf1fcc | 332 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
333 | } |
334 | ||
5fb9de1a | 335 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
336 | if (ret) |
337 | return ret; | |
338 | ||
b5321f30 CW |
339 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
340 | intel_ring_emit(ring, flags); | |
341 | intel_ring_emit(ring, scratch_addr); | |
342 | intel_ring_emit(ring, 0); | |
343 | intel_ring_advance(ring); | |
4772eaeb PZ |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
884ceace | 348 | static int |
f2cf1fcc | 349 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
350 | u32 flags, u32 scratch_addr) |
351 | { | |
7e37f889 | 352 | struct intel_ring *ring = req->ring; |
884ceace KG |
353 | int ret; |
354 | ||
5fb9de1a | 355 | ret = intel_ring_begin(req, 6); |
884ceace KG |
356 | if (ret) |
357 | return ret; | |
358 | ||
b5321f30 CW |
359 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
360 | intel_ring_emit(ring, flags); | |
361 | intel_ring_emit(ring, scratch_addr); | |
362 | intel_ring_emit(ring, 0); | |
363 | intel_ring_emit(ring, 0); | |
364 | intel_ring_emit(ring, 0); | |
365 | intel_ring_advance(ring); | |
884ceace KG |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
a5f3d68e | 370 | static int |
7c9cf4e3 | 371 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 372 | { |
56c0f1a7 | 373 | u32 scratch_addr = |
bde13ebd | 374 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
b5321f30 | 375 | u32 flags = 0; |
02c9f7e3 | 376 | int ret; |
a5f3d68e BW |
377 | |
378 | flags |= PIPE_CONTROL_CS_STALL; | |
379 | ||
7c9cf4e3 | 380 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
381 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
382 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 383 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 384 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 385 | } |
7c9cf4e3 | 386 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
387 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
388 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
389 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
390 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
391 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
392 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
393 | flags |= PIPE_CONTROL_QW_WRITE; | |
394 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
395 | |
396 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 397 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
398 | PIPE_CONTROL_CS_STALL | |
399 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
400 | 0); | |
401 | if (ret) | |
402 | return ret; | |
a5f3d68e BW |
403 | } |
404 | ||
f2cf1fcc | 405 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
406 | } |
407 | ||
0bc40be8 | 408 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 409 | { |
c033666a | 410 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
411 | u32 addr; |
412 | ||
413 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 414 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
415 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
416 | I915_WRITE(HWS_PGA, addr); | |
417 | } | |
418 | ||
0bc40be8 | 419 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 420 | { |
c033666a | 421 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 422 | i915_reg_t mmio; |
af75f269 DL |
423 | |
424 | /* The ring status page addresses are no longer next to the rest of | |
425 | * the ring registers as of gen7. | |
426 | */ | |
c033666a | 427 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 428 | switch (engine->id) { |
af75f269 DL |
429 | case RCS: |
430 | mmio = RENDER_HWS_PGA_GEN7; | |
431 | break; | |
432 | case BCS: | |
433 | mmio = BLT_HWS_PGA_GEN7; | |
434 | break; | |
435 | /* | |
436 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
437 | * gcc switch check warning | |
438 | */ | |
439 | case VCS2: | |
440 | case VCS: | |
441 | mmio = BSD_HWS_PGA_GEN7; | |
442 | break; | |
443 | case VECS: | |
444 | mmio = VEBOX_HWS_PGA_GEN7; | |
445 | break; | |
446 | } | |
c033666a | 447 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 448 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
449 | } else { |
450 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 451 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
452 | } |
453 | ||
57e88531 | 454 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
455 | POSTING_READ(mmio); |
456 | ||
457 | /* | |
458 | * Flush the TLB for this page | |
459 | * | |
460 | * FIXME: These two bits have disappeared on gen8, so a question | |
461 | * arises: do we still need this and if so how should we go about | |
462 | * invalidating the TLB? | |
463 | */ | |
ac657f64 | 464 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 465 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
466 | |
467 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 468 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
469 | |
470 | I915_WRITE(reg, | |
471 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
472 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
473 | if (intel_wait_for_register(dev_priv, |
474 | reg, INSTPM_SYNC_FLUSH, 0, | |
475 | 1000)) | |
af75f269 | 476 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 477 | engine->name); |
af75f269 DL |
478 | } |
479 | } | |
480 | ||
0bc40be8 | 481 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 482 | { |
c033666a | 483 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 484 | |
21a2c58a | 485 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 486 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
487 | if (intel_wait_for_register(dev_priv, |
488 | RING_MI_MODE(engine->mmio_base), | |
489 | MODE_IDLE, | |
490 | MODE_IDLE, | |
491 | 1000)) { | |
0bc40be8 TU |
492 | DRM_ERROR("%s : timed out trying to stop ring\n", |
493 | engine->name); | |
9bec9b13 CW |
494 | /* Sometimes we observe that the idle flag is not |
495 | * set even though the ring is empty. So double | |
496 | * check before giving up. | |
497 | */ | |
0bc40be8 | 498 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 499 | return false; |
9991ae78 CW |
500 | } |
501 | } | |
b7884eb4 | 502 | |
0bc40be8 TU |
503 | I915_WRITE_CTL(engine, 0); |
504 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 505 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 506 | |
21a2c58a | 507 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
508 | (void)I915_READ_CTL(engine); |
509 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 510 | } |
a51435a3 | 511 | |
0bc40be8 | 512 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 513 | } |
8187a2b7 | 514 | |
0bc40be8 | 515 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 516 | { |
c033666a | 517 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 518 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
519 | int ret = 0; |
520 | ||
59bad947 | 521 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 522 | |
0bc40be8 | 523 | if (!stop_ring(engine)) { |
9991ae78 | 524 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
525 | DRM_DEBUG_KMS("%s head not reset to zero " |
526 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
527 | engine->name, |
528 | I915_READ_CTL(engine), | |
529 | I915_READ_HEAD(engine), | |
530 | I915_READ_TAIL(engine), | |
531 | I915_READ_START(engine)); | |
8187a2b7 | 532 | |
0bc40be8 | 533 | if (!stop_ring(engine)) { |
6fd0d56e CW |
534 | DRM_ERROR("failed to set %s head to zero " |
535 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
536 | engine->name, |
537 | I915_READ_CTL(engine), | |
538 | I915_READ_HEAD(engine), | |
539 | I915_READ_TAIL(engine), | |
540 | I915_READ_START(engine)); | |
9991ae78 CW |
541 | ret = -EIO; |
542 | goto out; | |
6fd0d56e | 543 | } |
8187a2b7 ZN |
544 | } |
545 | ||
3177659a | 546 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 547 | ring_setup_phys_status_page(engine); |
3177659a CS |
548 | else |
549 | intel_ring_setup_status_page(engine); | |
9991ae78 | 550 | |
ad07dfcd | 551 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 552 | |
ece4a17d | 553 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 554 | I915_READ_HEAD(engine); |
ece4a17d | 555 | |
0d8957c8 DV |
556 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
557 | * registers with the above sequence (the readback of the HEAD registers | |
558 | * also enforces ordering), otherwise the hw might lose the new ring | |
559 | * register values. */ | |
bde13ebd | 560 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
561 | |
562 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 563 | if (I915_READ_HEAD(engine)) |
95468892 | 564 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 565 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
566 | |
567 | intel_ring_update_space(ring); | |
568 | I915_WRITE_HEAD(engine, ring->head); | |
569 | I915_WRITE_TAIL(engine, ring->tail); | |
570 | (void)I915_READ_TAIL(engine); | |
95468892 | 571 | |
62ae14b1 | 572 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 573 | |
8187a2b7 | 574 | /* If the head is still not zero, the ring is dead */ |
821ed7df CW |
575 | if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base), |
576 | RING_VALID, RING_VALID, | |
577 | 50)) { | |
e74cfed5 | 578 | DRM_ERROR("%s initialization failed " |
821ed7df | 579 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
580 | engine->name, |
581 | I915_READ_CTL(engine), | |
582 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
583 | I915_READ_HEAD(engine), ring->head, |
584 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 585 | I915_READ_START(engine), |
bde13ebd | 586 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
587 | ret = -EIO; |
588 | goto out; | |
8187a2b7 ZN |
589 | } |
590 | ||
fc0768ce | 591 | intel_engine_init_hangcheck(engine); |
50f018df | 592 | |
b7884eb4 | 593 | out: |
59bad947 | 594 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
595 | |
596 | return ret; | |
8187a2b7 ZN |
597 | } |
598 | ||
821ed7df CW |
599 | static void reset_ring_common(struct intel_engine_cs *engine, |
600 | struct drm_i915_gem_request *request) | |
601 | { | |
c0dcb203 CW |
602 | /* Try to restore the logical GPU state to match the continuation |
603 | * of the request queue. If we skip the context/PD restore, then | |
604 | * the next request may try to execute assuming that its context | |
605 | * is valid and loaded on the GPU and so may try to access invalid | |
606 | * memory, prompting repeated GPU hangs. | |
607 | * | |
608 | * If the request was guilty, we still restore the logical state | |
609 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
610 | * but skip over the hung batch. | |
611 | * | |
612 | * If the request was innocent, we try to replay the request with | |
613 | * the restored context. | |
614 | */ | |
615 | if (request) { | |
616 | struct drm_i915_private *dev_priv = request->i915; | |
617 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
618 | struct i915_hw_ppgtt *ppgtt; | |
619 | ||
620 | /* FIXME consider gen8 reset */ | |
621 | ||
622 | if (ce->state) { | |
623 | I915_WRITE(CCID, | |
624 | i915_ggtt_offset(ce->state) | | |
625 | BIT(8) /* must be set! */ | | |
626 | CCID_EXTENDED_STATE_SAVE | | |
627 | CCID_EXTENDED_STATE_RESTORE | | |
628 | CCID_EN); | |
629 | } | |
630 | ||
631 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
632 | if (ppgtt) { | |
633 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
634 | ||
635 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
636 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
637 | ||
638 | /* Wait for the PD reload to complete */ | |
639 | if (intel_wait_for_register(dev_priv, | |
640 | RING_PP_DIR_BASE(engine), | |
641 | BIT(0), 0, | |
642 | 10)) | |
643 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 644 | |
c0dcb203 CW |
645 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
646 | } | |
647 | ||
648 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
649 | if (request->fence.error == -EIO) { | |
650 | struct intel_ring *ring = request->ring; | |
651 | ||
652 | ring->head = request->postfix; | |
653 | ring->last_retired_head = -1; | |
654 | } | |
655 | } else { | |
656 | engine->legacy_active_context = NULL; | |
657 | } | |
821ed7df CW |
658 | } |
659 | ||
e2be4faf | 660 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 661 | { |
7e37f889 | 662 | struct intel_ring *ring = req->ring; |
c033666a CW |
663 | struct i915_workarounds *w = &req->i915->workarounds; |
664 | int ret, i; | |
888b5995 | 665 | |
02235808 | 666 | if (w->count == 0) |
7225342a | 667 | return 0; |
888b5995 | 668 | |
7c9cf4e3 | 669 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
670 | if (ret) |
671 | return ret; | |
888b5995 | 672 | |
5fb9de1a | 673 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
674 | if (ret) |
675 | return ret; | |
676 | ||
b5321f30 | 677 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 678 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
679 | intel_ring_emit_reg(ring, w->reg[i].addr); |
680 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 681 | } |
b5321f30 | 682 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 683 | |
b5321f30 | 684 | intel_ring_advance(ring); |
7225342a | 685 | |
7c9cf4e3 | 686 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
687 | if (ret) |
688 | return ret; | |
888b5995 | 689 | |
7225342a | 690 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 691 | |
7225342a | 692 | return 0; |
86d7f238 AS |
693 | } |
694 | ||
8753181e | 695 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
696 | { |
697 | int ret; | |
698 | ||
e2be4faf | 699 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
700 | if (ret != 0) |
701 | return ret; | |
702 | ||
4e50f082 | 703 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 704 | if (ret) |
e26e1b97 | 705 | return ret; |
8f0e2b9d | 706 | |
e26e1b97 | 707 | return 0; |
8f0e2b9d DV |
708 | } |
709 | ||
7225342a | 710 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
711 | i915_reg_t addr, |
712 | const u32 mask, const u32 val) | |
7225342a MK |
713 | { |
714 | const u32 idx = dev_priv->workarounds.count; | |
715 | ||
716 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
717 | return -ENOSPC; | |
718 | ||
719 | dev_priv->workarounds.reg[idx].addr = addr; | |
720 | dev_priv->workarounds.reg[idx].value = val; | |
721 | dev_priv->workarounds.reg[idx].mask = mask; | |
722 | ||
723 | dev_priv->workarounds.count++; | |
724 | ||
725 | return 0; | |
86d7f238 AS |
726 | } |
727 | ||
ca5a0fbd | 728 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 729 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
730 | if (r) \ |
731 | return r; \ | |
ca5a0fbd | 732 | } while (0) |
7225342a MK |
733 | |
734 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 735 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
736 | |
737 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 738 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 739 | |
98533251 | 740 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 741 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 742 | |
cf4b0de6 DL |
743 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
744 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 745 | |
cf4b0de6 | 746 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 747 | |
0bc40be8 TU |
748 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
749 | i915_reg_t reg) | |
33136b06 | 750 | { |
c033666a | 751 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 752 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 753 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
754 | |
755 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
756 | return -EINVAL; | |
757 | ||
0bc40be8 | 758 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 759 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 760 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
761 | |
762 | return 0; | |
763 | } | |
764 | ||
0bc40be8 | 765 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 766 | { |
c033666a | 767 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
768 | |
769 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 770 | |
717d84d6 AS |
771 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
772 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
773 | ||
d0581194 AS |
774 | /* WaDisablePartialInstShootdown:bdw,chv */ |
775 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
776 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
777 | ||
a340af58 AS |
778 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
779 | * workaround for for a possible hang in the unlikely event a TLB | |
780 | * invalidation occurs during a PSD flush. | |
781 | */ | |
782 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 783 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 784 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 785 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
786 | HDC_FORCE_NON_COHERENT); |
787 | ||
6def8fdd AS |
788 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
789 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
790 | * polygons in the same 8x4 pixel/sample area to be processed without | |
791 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
792 | * buffer." | |
793 | * | |
794 | * This optimization is off by default for BDW and CHV; turn it on. | |
795 | */ | |
796 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
797 | ||
48404636 AS |
798 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
799 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
800 | ||
7eebcde6 AS |
801 | /* |
802 | * BSpec recommends 8x4 when MSAA is used, | |
803 | * however in practice 16x4 seems fastest. | |
804 | * | |
805 | * Note that PS/WM thread counts depend on the WIZ hashing | |
806 | * disable bit, which we don't touch here, but it's good | |
807 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
808 | */ | |
809 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
810 | GEN6_WIZ_HASHING_MASK, | |
811 | GEN6_WIZ_HASHING_16x4); | |
812 | ||
e9a64ada AS |
813 | return 0; |
814 | } | |
815 | ||
0bc40be8 | 816 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 817 | { |
c033666a | 818 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 819 | int ret; |
86d7f238 | 820 | |
0bc40be8 | 821 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
822 | if (ret) |
823 | return ret; | |
824 | ||
101b376d | 825 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 826 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 827 | |
101b376d | 828 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
829 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
830 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 831 | |
7225342a MK |
832 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
833 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 834 | |
7225342a | 835 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
836 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
837 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 838 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 839 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 840 | |
86d7f238 AS |
841 | return 0; |
842 | } | |
843 | ||
0bc40be8 | 844 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 845 | { |
c033666a | 846 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 847 | int ret; |
00e1e623 | 848 | |
0bc40be8 | 849 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
850 | if (ret) |
851 | return ret; | |
852 | ||
00e1e623 | 853 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 854 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 855 | |
d60de81d KG |
856 | /* Improve HiZ throughput on CHV. */ |
857 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
858 | ||
7225342a MK |
859 | return 0; |
860 | } | |
861 | ||
0bc40be8 | 862 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 863 | { |
c033666a | 864 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 865 | int ret; |
ab0dfafe | 866 | |
9fb5026f | 867 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */ |
a8ab5ed5 TG |
868 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); |
869 | ||
9fb5026f | 870 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */ |
9c4cbf82 MK |
871 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
872 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
873 | ||
e5f81d65 | 874 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
875 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
876 | ECOCHK_DIS_TLB); | |
877 | ||
9fb5026f ACO |
878 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */ |
879 | /* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */ | |
ab0dfafe | 880 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 881 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
882 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
883 | ||
e5f81d65 | 884 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
885 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
886 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
887 | ||
a117f378 JN |
888 | /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */ |
889 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
890 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
891 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 892 | |
a117f378 JN |
893 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ |
894 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
895 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
896 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
897 | /* |
898 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
899 | * but we do that in per ctx batchbuffer as there is an issue | |
900 | * with this register not getting restored on ctx restore | |
901 | */ | |
183c6dac DL |
902 | } |
903 | ||
e5f81d65 | 904 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ |
bfd8ad4e | 905 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
bfd8ad4e | 906 | GEN9_ENABLE_GPGPU_PREEMPTION); |
cac23df4 | 907 | |
9fb5026f | 908 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */ |
e5f81d65 | 909 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ |
60294683 AS |
910 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
911 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 912 | |
9fb5026f | 913 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */ |
e2db7071 DL |
914 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
915 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
916 | ||
0d0b8dcf JN |
917 | /* WaDisableMaskBasedCammingInRCC:bxt */ |
918 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
919 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
920 | PIXEL_MASK_CAMMING_DISABLE); | |
921 | ||
5b0e3659 MK |
922 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
923 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
924 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
925 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 926 | |
bbaefe72 MK |
927 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
928 | * both tied to WaForceContextSaveRestoreNonCoherent | |
929 | * in some hsds for skl. We keep the tie for all gen9. The | |
930 | * documentation is a bit hazy and so we want to get common behaviour, | |
931 | * even though there is no clear evidence we would need both on kbl/bxt. | |
932 | * This area has been source of system hangs so we play it safe | |
933 | * and mimic the skl regardless of what bspec says. | |
934 | * | |
935 | * Use Force Non-Coherent whenever executing a 3D context. This | |
936 | * is a workaround for a possible hang in the unlikely event | |
937 | * a TLB invalidation occurs during a PSD flush. | |
938 | */ | |
939 | ||
940 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
941 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
942 | HDC_FORCE_NON_COHERENT); | |
943 | ||
944 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
945 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
946 | BDW_DISABLE_HDC_INVALIDATION); | |
947 | ||
e5f81d65 MK |
948 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
949 | if (IS_SKYLAKE(dev_priv) || | |
950 | IS_KABYLAKE(dev_priv) || | |
951 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
952 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
953 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 954 | |
9fb5026f | 955 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */ |
6b6d5626 RB |
956 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
957 | ||
e5f81d65 | 958 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
959 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
960 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
961 | ||
9fb5026f | 962 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */ |
6bb62855 | 963 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); |
964 | if (ret) | |
965 | return ret; | |
966 | ||
e5f81d65 | 967 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 968 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
969 | if (ret) |
970 | return ret; | |
971 | ||
9fb5026f | 972 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */ |
0bc40be8 | 973 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
974 | if (ret) |
975 | return ret; | |
976 | ||
3b106531 HN |
977 | return 0; |
978 | } | |
979 | ||
0bc40be8 | 980 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 981 | { |
c033666a | 982 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
983 | u8 vals[3] = { 0, 0, 0 }; |
984 | unsigned int i; | |
985 | ||
986 | for (i = 0; i < 3; i++) { | |
987 | u8 ss; | |
988 | ||
989 | /* | |
990 | * Only consider slices where one, and only one, subslice has 7 | |
991 | * EUs | |
992 | */ | |
43b67998 | 993 | if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) |
b7668791 DL |
994 | continue; |
995 | ||
996 | /* | |
997 | * subslice_7eu[i] != 0 (because of the check above) and | |
998 | * ss_max == 4 (maximum number of subslices possible per slice) | |
999 | * | |
1000 | * -> 0 <= ss <= 3; | |
1001 | */ | |
43b67998 | 1002 | ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; |
b7668791 DL |
1003 | vals[i] = 3 - ss; |
1004 | } | |
1005 | ||
1006 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1007 | return 0; | |
1008 | ||
1009 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1010 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1011 | GEN9_IZ_HASHING_MASK(2) | | |
1012 | GEN9_IZ_HASHING_MASK(1) | | |
1013 | GEN9_IZ_HASHING_MASK(0), | |
1014 | GEN9_IZ_HASHING(2, vals[2]) | | |
1015 | GEN9_IZ_HASHING(1, vals[1]) | | |
1016 | GEN9_IZ_HASHING(0, vals[0])); | |
1017 | ||
1018 | return 0; | |
1019 | } | |
1020 | ||
0bc40be8 | 1021 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1022 | { |
c033666a | 1023 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1024 | int ret; |
d0bbbc4f | 1025 | |
0bc40be8 | 1026 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1027 | if (ret) |
1028 | return ret; | |
8d205494 | 1029 | |
a78536e7 AS |
1030 | /* |
1031 | * Actual WA is to disable percontext preemption granularity control | |
1032 | * until D0 which is the default case so this is equivalent to | |
1033 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1034 | */ | |
9fc736e8 JN |
1035 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
1036 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
a78536e7 | 1037 | |
9c4cbf82 | 1038 | /* WaEnableGapsTsvCreditFix:skl */ |
a117f378 JN |
1039 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1040 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
d0bbbc4f | 1041 | |
eee8efb0 MK |
1042 | /* WaDisableGafsUnitClkGating:skl */ |
1043 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1044 | ||
4ba9c1f7 MK |
1045 | /* WaInPlaceDecompressionHang:skl */ |
1046 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
1047 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1048 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1049 | ||
6107497e | 1050 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1051 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1052 | if (ret) |
1053 | return ret; | |
1054 | ||
0bc40be8 | 1055 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1056 | } |
1057 | ||
0bc40be8 | 1058 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1059 | { |
c033666a | 1060 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1061 | int ret; |
dfb601e6 | 1062 | |
0bc40be8 | 1063 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1064 | if (ret) |
1065 | return ret; | |
cae0437f | 1066 | |
9c4cbf82 MK |
1067 | /* WaStoreMultiplePTEenable:bxt */ |
1068 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1069 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1070 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1071 | ||
1072 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1073 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1074 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1075 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1076 | } | |
1077 | ||
dfb601e6 NH |
1078 | /* WaDisableThreadStallDopClockGating:bxt */ |
1079 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1080 | STALL_DOP_GATING_DISABLE); | |
1081 | ||
780f0aeb | 1082 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1083 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1084 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1085 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1086 | } | |
1087 | ||
983b4b9d | 1088 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1089 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1090 | WA_SET_BIT_MASKED( |
1091 | GEN7_HALF_SLICE_CHICKEN1, | |
1092 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1093 | } | |
1094 | ||
2c8580e4 AS |
1095 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1096 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1097 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1098 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1099 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1100 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1101 | if (ret) |
1102 | return ret; | |
a786d53a | 1103 | |
0bc40be8 | 1104 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1105 | if (ret) |
1106 | return ret; | |
2c8580e4 AS |
1107 | } |
1108 | ||
050fc465 | 1109 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1110 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1111 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1112 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1113 | |
575e3ccb MA |
1114 | /* WaToEnableHwFixForPushConstHWBug:bxt */ |
1115 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1116 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1117 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1118 | ||
4ba9c1f7 MK |
1119 | /* WaInPlaceDecompressionHang:bxt */ |
1120 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1121 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1122 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1123 | ||
cae0437f NH |
1124 | return 0; |
1125 | } | |
1126 | ||
e5f81d65 MK |
1127 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1128 | { | |
e587f6cb | 1129 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1130 | int ret; |
1131 | ||
1132 | ret = gen9_init_workarounds(engine); | |
1133 | if (ret) | |
1134 | return ret; | |
1135 | ||
e587f6cb MK |
1136 | /* WaEnableGapsTsvCreditFix:kbl */ |
1137 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1138 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1139 | ||
c0b730d5 MK |
1140 | /* WaDisableDynamicCreditSharing:kbl */ |
1141 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1142 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1143 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1144 | ||
8401d42f MK |
1145 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1146 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1147 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1148 | HDC_FENCE_DEST_SLM_DISABLE); | |
1149 | ||
575e3ccb MA |
1150 | /* WaToEnableHwFixForPushConstHWBug:kbl */ |
1151 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1152 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1153 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1154 | ||
4de5d7cc MK |
1155 | /* WaDisableGafsUnitClkGating:kbl */ |
1156 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1157 | ||
954337aa MK |
1158 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1159 | WA_SET_BIT_MASKED( | |
1160 | GEN7_HALF_SLICE_CHICKEN1, | |
1161 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1162 | ||
4ba9c1f7 MK |
1163 | /* WaInPlaceDecompressionHang:kbl */ |
1164 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1165 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1166 | ||
fe905819 MK |
1167 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1168 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1169 | if (ret) | |
1170 | return ret; | |
1171 | ||
e5f81d65 MK |
1172 | return 0; |
1173 | } | |
1174 | ||
9fb5026f ACO |
1175 | static int glk_init_workarounds(struct intel_engine_cs *engine) |
1176 | { | |
1177 | struct drm_i915_private *dev_priv = engine->i915; | |
1178 | int ret; | |
1179 | ||
1180 | ret = gen9_init_workarounds(engine); | |
1181 | if (ret) | |
1182 | return ret; | |
1183 | ||
1184 | /* WaToEnableHwFixForPushConstHWBug:glk */ | |
1185 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1186 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
0bc40be8 | 1191 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1192 | { |
c033666a | 1193 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1194 | |
0bc40be8 | 1195 | WARN_ON(engine->id != RCS); |
7225342a MK |
1196 | |
1197 | dev_priv->workarounds.count = 0; | |
33136b06 | 1198 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1199 | |
c033666a | 1200 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1201 | return bdw_init_workarounds(engine); |
7225342a | 1202 | |
c033666a | 1203 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1204 | return chv_init_workarounds(engine); |
00e1e623 | 1205 | |
c033666a | 1206 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1207 | return skl_init_workarounds(engine); |
cae0437f | 1208 | |
c033666a | 1209 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1210 | return bxt_init_workarounds(engine); |
3b106531 | 1211 | |
e5f81d65 MK |
1212 | if (IS_KABYLAKE(dev_priv)) |
1213 | return kbl_init_workarounds(engine); | |
1214 | ||
9fb5026f ACO |
1215 | if (IS_GEMINILAKE(dev_priv)) |
1216 | return glk_init_workarounds(engine); | |
1217 | ||
00e1e623 VS |
1218 | return 0; |
1219 | } | |
1220 | ||
0bc40be8 | 1221 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1222 | { |
c033666a | 1223 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1224 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1225 | if (ret) |
1226 | return ret; | |
a69ffdbf | 1227 | |
61a563a2 | 1228 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1229 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1230 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1231 | |
1232 | /* We need to disable the AsyncFlip performance optimisations in order | |
1233 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1234 | * programmed to '1' on all products. | |
8693a824 | 1235 | * |
2441f877 | 1236 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1237 | */ |
ac657f64 | 1238 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1239 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1240 | ||
f05bb0c7 | 1241 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1242 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1243 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1244 | I915_WRITE(GFX_MODE, |
aa83e30d | 1245 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1246 | |
01fa0302 | 1247 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1248 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1249 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1250 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1251 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1252 | |
c033666a | 1253 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1254 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1255 | * "If this bit is set, STCunit will have LRA as replacement | |
1256 | * policy. [...] This bit must be reset. LRA replacement | |
1257 | * policy is not supported." | |
1258 | */ | |
1259 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1260 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1261 | } |
1262 | ||
ac657f64 | 1263 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1264 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1265 | |
035ea405 VS |
1266 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1267 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1268 | |
0bc40be8 | 1269 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1270 | } |
1271 | ||
0bc40be8 | 1272 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1273 | { |
c033666a | 1274 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 1275 | |
19880c4a | 1276 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
1277 | } |
1278 | ||
caddfe71 | 1279 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *out) |
3e78998a | 1280 | { |
ad7bdb2b | 1281 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 1282 | struct intel_engine_cs *waiter; |
c3232b18 | 1283 | enum intel_engine_id id; |
3e78998a | 1284 | |
3b3f1650 | 1285 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 1286 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1287 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1288 | continue; | |
1289 | ||
caddfe71 CW |
1290 | *out++ = GFX_OP_PIPE_CONTROL(6); |
1291 | *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1292 | PIPE_CONTROL_QW_WRITE | | |
1293 | PIPE_CONTROL_CS_STALL); | |
1294 | *out++ = lower_32_bits(gtt_offset); | |
1295 | *out++ = upper_32_bits(gtt_offset); | |
1296 | *out++ = req->global_seqno; | |
1297 | *out++ = 0; | |
1298 | *out++ = (MI_SEMAPHORE_SIGNAL | | |
1299 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
1300 | *out++ = 0; | |
3e78998a BW |
1301 | } |
1302 | ||
caddfe71 | 1303 | return out; |
3e78998a BW |
1304 | } |
1305 | ||
caddfe71 | 1306 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *out) |
3e78998a | 1307 | { |
ad7bdb2b | 1308 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 1309 | struct intel_engine_cs *waiter; |
c3232b18 | 1310 | enum intel_engine_id id; |
3e78998a | 1311 | |
3b3f1650 | 1312 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 1313 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1314 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1315 | continue; | |
1316 | ||
caddfe71 CW |
1317 | *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1318 | *out++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
1319 | *out++ = upper_32_bits(gtt_offset); | |
1320 | *out++ = req->global_seqno; | |
1321 | *out++ = (MI_SEMAPHORE_SIGNAL | | |
1322 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
1323 | *out++ = 0; | |
3e78998a BW |
1324 | } |
1325 | ||
caddfe71 | 1326 | return out; |
3e78998a BW |
1327 | } |
1328 | ||
caddfe71 | 1329 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *out) |
1ec14ad3 | 1330 | { |
ad7bdb2b | 1331 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 1332 | struct intel_engine_cs *engine; |
3b3f1650 | 1333 | enum intel_engine_id id; |
caddfe71 | 1334 | int num_rings = 0; |
024a43e1 | 1335 | |
3b3f1650 | 1336 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
1337 | i915_reg_t mbox_reg; |
1338 | ||
1339 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
1340 | continue; | |
f0f59a00 | 1341 | |
318f89ca | 1342 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 1343 | if (i915_mmio_reg_valid(mbox_reg)) { |
caddfe71 CW |
1344 | *out++ = MI_LOAD_REGISTER_IMM(1); |
1345 | *out++ = i915_mmio_reg_offset(mbox_reg); | |
1346 | *out++ = req->global_seqno; | |
1347 | num_rings++; | |
78325f2d BW |
1348 | } |
1349 | } | |
caddfe71 CW |
1350 | if (num_rings & 1) |
1351 | *out++ = MI_NOOP; | |
024a43e1 | 1352 | |
caddfe71 | 1353 | return out; |
1ec14ad3 CW |
1354 | } |
1355 | ||
b0411e7d CW |
1356 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
1357 | { | |
1358 | struct drm_i915_private *dev_priv = request->i915; | |
1359 | ||
d55ac5bf CW |
1360 | i915_gem_request_submit(request); |
1361 | ||
caddfe71 | 1362 | I915_WRITE_TAIL(request->engine, request->tail); |
b0411e7d CW |
1363 | } |
1364 | ||
caddfe71 CW |
1365 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, |
1366 | u32 *out) | |
1ec14ad3 | 1367 | { |
caddfe71 CW |
1368 | *out++ = MI_STORE_DWORD_INDEX; |
1369 | *out++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
1370 | *out++ = req->global_seqno; | |
1371 | *out++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 1372 | |
caddfe71 | 1373 | req->tail = intel_ring_offset(req->ring, out); |
1ec14ad3 CW |
1374 | } |
1375 | ||
98f29e8d CW |
1376 | static const int i9xx_emit_breadcrumb_sz = 4; |
1377 | ||
b0411e7d | 1378 | /** |
9b81d556 | 1379 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
1380 | * |
1381 | * @request - request to write to the ring | |
1382 | * | |
1383 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1384 | * This acts like a signal in the canonical semaphore. | |
1385 | */ | |
caddfe71 CW |
1386 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, |
1387 | u32 *out) | |
b0411e7d | 1388 | { |
caddfe71 CW |
1389 | return i9xx_emit_breadcrumb(req, |
1390 | req->engine->semaphore.signal(req, out)); | |
b0411e7d CW |
1391 | } |
1392 | ||
caddfe71 CW |
1393 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
1394 | u32 *out) | |
a58c01aa CW |
1395 | { |
1396 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 1397 | |
caddfe71 CW |
1398 | if (engine->semaphore.signal) |
1399 | out = engine->semaphore.signal(req, out); | |
a58c01aa | 1400 | |
caddfe71 CW |
1401 | *out++ = GFX_OP_PIPE_CONTROL(6); |
1402 | *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
b5321f30 | 1403 | PIPE_CONTROL_CS_STALL | |
caddfe71 CW |
1404 | PIPE_CONTROL_QW_WRITE); |
1405 | *out++ = intel_hws_seqno_address(engine); | |
1406 | *out++ = 0; | |
1407 | *out++ = req->global_seqno; | |
a58c01aa | 1408 | /* We're thrashing one dword of HWS. */ |
caddfe71 CW |
1409 | *out++ = 0; |
1410 | *out++ = MI_USER_INTERRUPT; | |
1411 | *out++ = MI_NOOP; | |
a58c01aa | 1412 | |
caddfe71 | 1413 | req->tail = intel_ring_offset(req->ring, out); |
a58c01aa CW |
1414 | } |
1415 | ||
98f29e8d CW |
1416 | static const int gen8_render_emit_breadcrumb_sz = 8; |
1417 | ||
c8c99b0f BW |
1418 | /** |
1419 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1420 | * | |
1421 | * @waiter - ring that is waiting | |
1422 | * @signaller - ring which has, or will signal | |
1423 | * @seqno - seqno which the waiter will block on | |
1424 | */ | |
5ee426ca BW |
1425 | |
1426 | static int | |
ad7bdb2b CW |
1427 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
1428 | struct drm_i915_gem_request *signal) | |
5ee426ca | 1429 | { |
ad7bdb2b CW |
1430 | struct intel_ring *ring = req->ring; |
1431 | struct drm_i915_private *dev_priv = req->i915; | |
1432 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 1433 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1434 | int ret; |
1435 | ||
ad7bdb2b | 1436 | ret = intel_ring_begin(req, 4); |
5ee426ca BW |
1437 | if (ret) |
1438 | return ret; | |
1439 | ||
ad7bdb2b CW |
1440 | intel_ring_emit(ring, |
1441 | MI_SEMAPHORE_WAIT | | |
1442 | MI_SEMAPHORE_GLOBAL_GTT | | |
1443 | MI_SEMAPHORE_SAD_GTE_SDD); | |
65e4760e | 1444 | intel_ring_emit(ring, signal->global_seqno); |
ad7bdb2b CW |
1445 | intel_ring_emit(ring, lower_32_bits(offset)); |
1446 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1447 | intel_ring_advance(ring); | |
6ef48d7f CW |
1448 | |
1449 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1450 | * pagetables and we must reload them before executing the batch. | |
1451 | * We do this on the i915_switch_context() following the wait and | |
1452 | * before the dispatch. | |
1453 | */ | |
ad7bdb2b CW |
1454 | ppgtt = req->ctx->ppgtt; |
1455 | if (ppgtt && req->engine->id != RCS) | |
1456 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
1457 | return 0; |
1458 | } | |
1459 | ||
c8c99b0f | 1460 | static int |
ad7bdb2b CW |
1461 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
1462 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 1463 | { |
ad7bdb2b | 1464 | struct intel_ring *ring = req->ring; |
c8c99b0f BW |
1465 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1466 | MI_SEMAPHORE_COMPARE | | |
1467 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 1468 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
ebc348b2 | 1469 | int ret; |
1ec14ad3 | 1470 | |
ebc348b2 | 1471 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1472 | |
ad7bdb2b | 1473 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1474 | if (ret) |
1475 | return ret; | |
1476 | ||
ad7bdb2b | 1477 | intel_ring_emit(ring, dw1 | wait_mbox); |
ddf07be7 CW |
1478 | /* Throughout all of the GEM code, seqno passed implies our current |
1479 | * seqno is >= the last seqno executed. However for hardware the | |
1480 | * comparison is strictly greater than. | |
1481 | */ | |
65e4760e | 1482 | intel_ring_emit(ring, signal->global_seqno - 1); |
ad7bdb2b CW |
1483 | intel_ring_emit(ring, 0); |
1484 | intel_ring_emit(ring, MI_NOOP); | |
1485 | intel_ring_advance(ring); | |
1ec14ad3 CW |
1486 | |
1487 | return 0; | |
1488 | } | |
1489 | ||
f8973c21 | 1490 | static void |
38a0f2db | 1491 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1492 | { |
f8973c21 CW |
1493 | /* MI_STORE are internally buffered by the GPU and not flushed |
1494 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1495 | * MI commands. | |
c6df541c | 1496 | * |
f8973c21 CW |
1497 | * "Only the submission of the store operation is guaranteed. |
1498 | * The write result will be complete (coherent) some time later | |
1499 | * (this is practically a finite period but there is no guaranteed | |
1500 | * latency)." | |
1501 | * | |
1502 | * Empirically, we observe that we need a delay of at least 75us to | |
1503 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1504 | */ |
f8973c21 | 1505 | usleep_range(125, 250); |
c6df541c CW |
1506 | } |
1507 | ||
c04e0f3b CW |
1508 | static void |
1509 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1510 | { |
c033666a | 1511 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1512 | |
4cd53c0c DV |
1513 | /* Workaround to force correct ordering between irq and seqno writes on |
1514 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1515 | * ACTHD) before reading the status page. |
1516 | * | |
1517 | * Note that this effectively stalls the read by the time it takes to | |
1518 | * do a memory transaction, which more or less ensures that the write | |
1519 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1520 | * Alternatively we could delay the interrupt from the CS ring to give | |
1521 | * the write time to land, but that would incur a delay after every | |
1522 | * batch i.e. much more frequent than a delay when waiting for the | |
1523 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1524 | * |
1525 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1526 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1527 | */ |
bcbdb6d0 | 1528 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1529 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1530 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1531 | } |
1532 | ||
31bb59cc CW |
1533 | static void |
1534 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1535 | { |
31bb59cc | 1536 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1537 | } |
1538 | ||
1539 | static void | |
31bb59cc | 1540 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1541 | { |
31bb59cc | 1542 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1543 | } |
1544 | ||
31bb59cc CW |
1545 | static void |
1546 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1547 | { |
c033666a | 1548 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1549 | |
31bb59cc CW |
1550 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1551 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1552 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1553 | } |
1554 | ||
8187a2b7 | 1555 | static void |
31bb59cc | 1556 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1557 | { |
c033666a | 1558 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1559 | |
31bb59cc CW |
1560 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1561 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1562 | } |
1563 | ||
31bb59cc CW |
1564 | static void |
1565 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1566 | { |
c033666a | 1567 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1568 | |
31bb59cc CW |
1569 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1570 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1571 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1572 | } |
1573 | ||
1574 | static void | |
31bb59cc | 1575 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1576 | { |
c033666a | 1577 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1578 | |
31bb59cc CW |
1579 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1580 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1581 | } |
1582 | ||
b72f3acb | 1583 | static int |
7c9cf4e3 | 1584 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1585 | { |
7e37f889 | 1586 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1587 | int ret; |
1588 | ||
5fb9de1a | 1589 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1590 | if (ret) |
1591 | return ret; | |
1592 | ||
b5321f30 CW |
1593 | intel_ring_emit(ring, MI_FLUSH); |
1594 | intel_ring_emit(ring, MI_NOOP); | |
1595 | intel_ring_advance(ring); | |
b72f3acb | 1596 | return 0; |
d1b851fc ZN |
1597 | } |
1598 | ||
31bb59cc CW |
1599 | static void |
1600 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1601 | { |
c033666a | 1602 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1603 | |
61ff75ac CW |
1604 | I915_WRITE_IMR(engine, |
1605 | ~(engine->irq_enable_mask | | |
1606 | engine->irq_keep_mask)); | |
31bb59cc | 1607 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1608 | } |
1609 | ||
1610 | static void | |
31bb59cc | 1611 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1612 | { |
c033666a | 1613 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1614 | |
61ff75ac | 1615 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1616 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1617 | } |
1618 | ||
31bb59cc CW |
1619 | static void |
1620 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1621 | { |
c033666a | 1622 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1623 | |
31bb59cc | 1624 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1625 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1626 | } |
1627 | ||
1628 | static void | |
31bb59cc | 1629 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1630 | { |
c033666a | 1631 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1632 | |
31bb59cc | 1633 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1634 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1635 | } |
1636 | ||
31bb59cc CW |
1637 | static void |
1638 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1639 | { |
c033666a | 1640 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1641 | |
61ff75ac CW |
1642 | I915_WRITE_IMR(engine, |
1643 | ~(engine->irq_enable_mask | | |
1644 | engine->irq_keep_mask)); | |
31bb59cc | 1645 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1646 | } |
1647 | ||
1648 | static void | |
31bb59cc | 1649 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1650 | { |
c033666a | 1651 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1652 | |
61ff75ac | 1653 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1654 | } |
1655 | ||
d1b851fc | 1656 | static int |
803688ba CW |
1657 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1658 | u64 offset, u32 length, | |
1659 | unsigned int dispatch_flags) | |
d1b851fc | 1660 | { |
7e37f889 | 1661 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1662 | int ret; |
78501eac | 1663 | |
5fb9de1a | 1664 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1665 | if (ret) |
1666 | return ret; | |
1667 | ||
b5321f30 | 1668 | intel_ring_emit(ring, |
65f56876 CW |
1669 | MI_BATCH_BUFFER_START | |
1670 | MI_BATCH_GTT | | |
8e004efc JH |
1671 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1672 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1673 | intel_ring_emit(ring, offset); |
1674 | intel_ring_advance(ring); | |
78501eac | 1675 | |
d1b851fc ZN |
1676 | return 0; |
1677 | } | |
1678 | ||
b45305fc DV |
1679 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1680 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1681 | #define I830_TLB_ENTRIES (2) |
1682 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1683 | static int |
803688ba CW |
1684 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1685 | u64 offset, u32 len, | |
1686 | unsigned int dispatch_flags) | |
62fdfeaf | 1687 | { |
7e37f889 | 1688 | struct intel_ring *ring = req->ring; |
bde13ebd | 1689 | u32 cs_offset = i915_ggtt_offset(req->engine->scratch); |
c4e7a414 | 1690 | int ret; |
62fdfeaf | 1691 | |
5fb9de1a | 1692 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1693 | if (ret) |
1694 | return ret; | |
62fdfeaf | 1695 | |
c4d69da1 | 1696 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1697 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1698 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1699 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1700 | intel_ring_emit(ring, cs_offset); | |
1701 | intel_ring_emit(ring, 0xdeadbeef); | |
1702 | intel_ring_emit(ring, MI_NOOP); | |
1703 | intel_ring_advance(ring); | |
b45305fc | 1704 | |
8e004efc | 1705 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1706 | if (len > I830_BATCH_LIMIT) |
1707 | return -ENOSPC; | |
1708 | ||
5fb9de1a | 1709 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1710 | if (ret) |
1711 | return ret; | |
c4d69da1 CW |
1712 | |
1713 | /* Blit the batch (which has now all relocs applied) to the | |
1714 | * stable batch scratch bo area (so that the CS never | |
1715 | * stumbles over its tlb invalidation bug) ... | |
1716 | */ | |
b5321f30 CW |
1717 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1718 | intel_ring_emit(ring, | |
e2f80391 | 1719 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1720 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1721 | intel_ring_emit(ring, cs_offset); | |
1722 | intel_ring_emit(ring, 4096); | |
1723 | intel_ring_emit(ring, offset); | |
e2f80391 | 1724 | |
b5321f30 CW |
1725 | intel_ring_emit(ring, MI_FLUSH); |
1726 | intel_ring_emit(ring, MI_NOOP); | |
1727 | intel_ring_advance(ring); | |
b45305fc DV |
1728 | |
1729 | /* ... and execute it. */ | |
c4d69da1 | 1730 | offset = cs_offset; |
b45305fc | 1731 | } |
e1f99ce6 | 1732 | |
9d611c03 | 1733 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1734 | if (ret) |
1735 | return ret; | |
1736 | ||
b5321f30 CW |
1737 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1738 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1739 | 0 : MI_BATCH_NON_SECURE)); | |
1740 | intel_ring_advance(ring); | |
c4d69da1 | 1741 | |
fb3256da DV |
1742 | return 0; |
1743 | } | |
1744 | ||
1745 | static int | |
803688ba CW |
1746 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1747 | u64 offset, u32 len, | |
1748 | unsigned int dispatch_flags) | |
fb3256da | 1749 | { |
7e37f889 | 1750 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1751 | int ret; |
1752 | ||
5fb9de1a | 1753 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1754 | if (ret) |
1755 | return ret; | |
1756 | ||
b5321f30 CW |
1757 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1758 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1759 | 0 : MI_BATCH_NON_SECURE)); | |
1760 | intel_ring_advance(ring); | |
62fdfeaf | 1761 | |
62fdfeaf EA |
1762 | return 0; |
1763 | } | |
1764 | ||
0bc40be8 | 1765 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1766 | { |
c033666a | 1767 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1768 | |
1769 | if (!dev_priv->status_page_dmah) | |
1770 | return; | |
1771 | ||
91c8a326 | 1772 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1773 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1774 | } |
1775 | ||
0bc40be8 | 1776 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1777 | { |
57e88531 | 1778 | struct i915_vma *vma; |
f8a7fde4 | 1779 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1780 | |
57e88531 CW |
1781 | vma = fetch_and_zero(&engine->status_page.vma); |
1782 | if (!vma) | |
62fdfeaf | 1783 | return; |
62fdfeaf | 1784 | |
f8a7fde4 CW |
1785 | obj = vma->obj; |
1786 | ||
57e88531 | 1787 | i915_vma_unpin(vma); |
f8a7fde4 CW |
1788 | i915_vma_close(vma); |
1789 | ||
1790 | i915_gem_object_unpin_map(obj); | |
1791 | __i915_gem_object_release_unless_active(obj); | |
62fdfeaf EA |
1792 | } |
1793 | ||
0bc40be8 | 1794 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1795 | { |
57e88531 CW |
1796 | struct drm_i915_gem_object *obj; |
1797 | struct i915_vma *vma; | |
1798 | unsigned int flags; | |
920cf419 | 1799 | void *vaddr; |
57e88531 | 1800 | int ret; |
e4ffd173 | 1801 | |
f51455d4 | 1802 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); |
57e88531 CW |
1803 | if (IS_ERR(obj)) { |
1804 | DRM_ERROR("Failed to allocate status page\n"); | |
1805 | return PTR_ERR(obj); | |
1806 | } | |
62fdfeaf | 1807 | |
57e88531 CW |
1808 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1809 | if (ret) | |
1810 | goto err; | |
e3efda49 | 1811 | |
a01cb37a | 1812 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
57e88531 CW |
1813 | if (IS_ERR(vma)) { |
1814 | ret = PTR_ERR(vma); | |
1815 | goto err; | |
e3efda49 | 1816 | } |
62fdfeaf | 1817 | |
57e88531 CW |
1818 | flags = PIN_GLOBAL; |
1819 | if (!HAS_LLC(engine->i915)) | |
1820 | /* On g33, we cannot place HWS above 256MiB, so | |
1821 | * restrict its pinning to the low mappable arena. | |
1822 | * Though this restriction is not documented for | |
1823 | * gen4, gen5, or byt, they also behave similarly | |
1824 | * and hang if the HWS is placed at the top of the | |
1825 | * GTT. To generalise, it appears that all !llc | |
1826 | * platforms have issues with us placing the HWS | |
1827 | * above the mappable region (even though we never | |
1828 | * actualy map it). | |
1829 | */ | |
1830 | flags |= PIN_MAPPABLE; | |
1831 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1832 | if (ret) | |
1833 | goto err; | |
62fdfeaf | 1834 | |
920cf419 CW |
1835 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); |
1836 | if (IS_ERR(vaddr)) { | |
1837 | ret = PTR_ERR(vaddr); | |
1838 | goto err_unpin; | |
1839 | } | |
1840 | ||
57e88531 | 1841 | engine->status_page.vma = vma; |
bde13ebd | 1842 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
f51455d4 | 1843 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); |
62fdfeaf | 1844 | |
bde13ebd CW |
1845 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1846 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1847 | return 0; |
57e88531 | 1848 | |
920cf419 CW |
1849 | err_unpin: |
1850 | i915_vma_unpin(vma); | |
57e88531 CW |
1851 | err: |
1852 | i915_gem_object_put(obj); | |
1853 | return ret; | |
62fdfeaf EA |
1854 | } |
1855 | ||
0bc40be8 | 1856 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1857 | { |
c033666a | 1858 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1859 | |
57e88531 CW |
1860 | dev_priv->status_page_dmah = |
1861 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1862 | if (!dev_priv->status_page_dmah) | |
1863 | return -ENOMEM; | |
6b8294a4 | 1864 | |
0bc40be8 TU |
1865 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1866 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
d3ef1af6 | 1871 | int intel_ring_pin(struct intel_ring *ring, unsigned int offset_bias) |
7ba717cf | 1872 | { |
d3ef1af6 | 1873 | unsigned int flags; |
9d80841e | 1874 | enum i915_map_type map; |
57e88531 | 1875 | struct i915_vma *vma = ring->vma; |
8305216f | 1876 | void *addr; |
7ba717cf TD |
1877 | int ret; |
1878 | ||
57e88531 | 1879 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1880 | |
9d80841e CW |
1881 | map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC; |
1882 | ||
d3ef1af6 DCS |
1883 | flags = PIN_GLOBAL; |
1884 | if (offset_bias) | |
1885 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1886 | if (vma->obj->stolen) |
57e88531 | 1887 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1888 | |
57e88531 | 1889 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1890 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1891 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1892 | else | |
1893 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1894 | if (unlikely(ret)) | |
def0c5f6 | 1895 | return ret; |
57e88531 | 1896 | } |
7ba717cf | 1897 | |
57e88531 CW |
1898 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1899 | if (unlikely(ret)) | |
1900 | return ret; | |
def0c5f6 | 1901 | |
9d80841e | 1902 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1903 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1904 | else | |
9d80841e | 1905 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1906 | if (IS_ERR(addr)) |
1907 | goto err; | |
7ba717cf | 1908 | |
32c04f16 | 1909 | ring->vaddr = addr; |
7ba717cf | 1910 | return 0; |
d2cad535 | 1911 | |
57e88531 CW |
1912 | err: |
1913 | i915_vma_unpin(vma); | |
1914 | return PTR_ERR(addr); | |
7ba717cf TD |
1915 | } |
1916 | ||
aad29fbb CW |
1917 | void intel_ring_unpin(struct intel_ring *ring) |
1918 | { | |
1919 | GEM_BUG_ON(!ring->vma); | |
1920 | GEM_BUG_ON(!ring->vaddr); | |
1921 | ||
9d80841e | 1922 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1923 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1924 | else |
1925 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1926 | ring->vaddr = NULL; |
1927 | ||
57e88531 | 1928 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1929 | } |
1930 | ||
57e88531 CW |
1931 | static struct i915_vma * |
1932 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1933 | { |
05394f39 | 1934 | struct drm_i915_gem_object *obj; |
57e88531 | 1935 | struct i915_vma *vma; |
62fdfeaf | 1936 | |
187685cb | 1937 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1938 | if (!obj) |
12d79d78 | 1939 | obj = i915_gem_object_create(dev_priv, size); |
57e88531 CW |
1940 | if (IS_ERR(obj)) |
1941 | return ERR_CAST(obj); | |
8187a2b7 | 1942 | |
24f3a8cf AG |
1943 | /* mark ring buffers as read-only from GPU side by default */ |
1944 | obj->gt_ro = 1; | |
1945 | ||
a01cb37a | 1946 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1947 | if (IS_ERR(vma)) |
1948 | goto err; | |
1949 | ||
1950 | return vma; | |
e3efda49 | 1951 | |
57e88531 CW |
1952 | err: |
1953 | i915_gem_object_put(obj); | |
1954 | return vma; | |
e3efda49 CW |
1955 | } |
1956 | ||
7e37f889 CW |
1957 | struct intel_ring * |
1958 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1959 | { |
7e37f889 | 1960 | struct intel_ring *ring; |
57e88531 | 1961 | struct i915_vma *vma; |
01101fa7 | 1962 | |
8f942018 | 1963 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1964 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1965 | |
01101fa7 | 1966 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1967 | if (!ring) |
01101fa7 CW |
1968 | return ERR_PTR(-ENOMEM); |
1969 | ||
4a570db5 | 1970 | ring->engine = engine; |
01101fa7 | 1971 | |
675d9ad7 CW |
1972 | INIT_LIST_HEAD(&ring->request_list); |
1973 | ||
01101fa7 CW |
1974 | ring->size = size; |
1975 | /* Workaround an erratum on the i830 which causes a hang if | |
1976 | * the TAIL pointer points to within the last 2 cachelines | |
1977 | * of the buffer. | |
1978 | */ | |
1979 | ring->effective_size = size; | |
2a307c2e | 1980 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1981 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1982 | ||
1983 | ring->last_retired_head = -1; | |
1984 | intel_ring_update_space(ring); | |
1985 | ||
57e88531 CW |
1986 | vma = intel_ring_create_vma(engine->i915, size); |
1987 | if (IS_ERR(vma)) { | |
01101fa7 | 1988 | kfree(ring); |
57e88531 | 1989 | return ERR_CAST(vma); |
01101fa7 | 1990 | } |
57e88531 | 1991 | ring->vma = vma; |
01101fa7 CW |
1992 | |
1993 | return ring; | |
1994 | } | |
1995 | ||
1996 | void | |
7e37f889 | 1997 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1998 | { |
f8a7fde4 CW |
1999 | struct drm_i915_gem_object *obj = ring->vma->obj; |
2000 | ||
2001 | i915_vma_close(ring->vma); | |
2002 | __i915_gem_object_release_unless_active(obj); | |
2003 | ||
01101fa7 CW |
2004 | kfree(ring); |
2005 | } | |
2006 | ||
e8a9c58f CW |
2007 | static int context_pin(struct i915_gem_context *ctx, unsigned int flags) |
2008 | { | |
2009 | struct i915_vma *vma = ctx->engine[RCS].state; | |
2010 | int ret; | |
2011 | ||
2012 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
2013 | * We only want to do this on the first bind so that we do not stall | |
2014 | * on an active context (which by nature is already on the GPU). | |
2015 | */ | |
2016 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
2017 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
2018 | if (ret) | |
2019 | return ret; | |
2020 | } | |
2021 | ||
2022 | return i915_vma_pin(vma, 0, ctx->ggtt_alignment, PIN_GLOBAL | flags); | |
2023 | } | |
2024 | ||
2025 | static int intel_ring_context_pin(struct intel_engine_cs *engine, | |
2026 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
2027 | { |
2028 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2029 | int ret; | |
2030 | ||
91c8a326 | 2031 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2032 | |
2033 | if (ce->pin_count++) | |
2034 | return 0; | |
2035 | ||
2036 | if (ce->state) { | |
e8a9c58f CW |
2037 | unsigned int flags; |
2038 | ||
2039 | flags = 0; | |
984ff29f | 2040 | if (i915_gem_context_is_kernel(ctx)) |
e8a9c58f | 2041 | flags = PIN_HIGH; |
7abc98fa | 2042 | |
e8a9c58f CW |
2043 | ret = context_pin(ctx, flags); |
2044 | if (ret) | |
0cb26a8e CW |
2045 | goto error; |
2046 | } | |
2047 | ||
c7c3c07d CW |
2048 | /* The kernel context is only used as a placeholder for flushing the |
2049 | * active context. It is never used for submitting user rendering and | |
2050 | * as such never requires the golden render context, and so we can skip | |
2051 | * emitting it when we switch to the kernel context. This is required | |
2052 | * as during eviction we cannot allocate and pin the renderstate in | |
2053 | * order to initialise the context. | |
2054 | */ | |
984ff29f | 2055 | if (i915_gem_context_is_kernel(ctx)) |
c7c3c07d CW |
2056 | ce->initialised = true; |
2057 | ||
9a6feaf0 | 2058 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2059 | return 0; |
2060 | ||
2061 | error: | |
2062 | ce->pin_count = 0; | |
2063 | return ret; | |
2064 | } | |
2065 | ||
e8a9c58f CW |
2066 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
2067 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
2068 | { |
2069 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2070 | ||
91c8a326 | 2071 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 2072 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
2073 | |
2074 | if (--ce->pin_count) | |
2075 | return; | |
2076 | ||
2077 | if (ce->state) | |
bf3783e5 | 2078 | i915_vma_unpin(ce->state); |
0cb26a8e | 2079 | |
9a6feaf0 | 2080 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2081 | } |
2082 | ||
acd27845 | 2083 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2084 | { |
acd27845 | 2085 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2086 | struct intel_ring *ring; |
e3efda49 CW |
2087 | int ret; |
2088 | ||
0bc40be8 | 2089 | WARN_ON(engine->buffer); |
bfc882b4 | 2090 | |
019bf277 TU |
2091 | intel_engine_setup_common(engine); |
2092 | ||
019bf277 | 2093 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2094 | if (ret) |
2095 | goto error; | |
e3efda49 | 2096 | |
32c04f16 CW |
2097 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2098 | if (IS_ERR(ring)) { | |
2099 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2100 | goto error; |
2101 | } | |
01101fa7 | 2102 | |
3177659a CS |
2103 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
2104 | WARN_ON(engine->id != RCS); | |
2105 | ret = init_phys_status_page(engine); | |
e3efda49 | 2106 | if (ret) |
8ee14975 | 2107 | goto error; |
e3efda49 | 2108 | } else { |
3177659a | 2109 | ret = init_status_page(engine); |
e3efda49 | 2110 | if (ret) |
8ee14975 | 2111 | goto error; |
e3efda49 CW |
2112 | } |
2113 | ||
d3ef1af6 | 2114 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
f51455d4 | 2115 | ret = intel_ring_pin(ring, I915_GTT_PAGE_SIZE); |
bfc882b4 | 2116 | if (ret) { |
57e88531 | 2117 | intel_ring_free(ring); |
bfc882b4 | 2118 | goto error; |
e3efda49 | 2119 | } |
57e88531 | 2120 | engine->buffer = ring; |
62fdfeaf | 2121 | |
8ee14975 | 2122 | return 0; |
351e3db2 | 2123 | |
8ee14975 | 2124 | error: |
7e37f889 | 2125 | intel_engine_cleanup(engine); |
8ee14975 | 2126 | return ret; |
62fdfeaf EA |
2127 | } |
2128 | ||
7e37f889 | 2129 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2130 | { |
6402c330 | 2131 | struct drm_i915_private *dev_priv; |
33626e6a | 2132 | |
c033666a | 2133 | dev_priv = engine->i915; |
6402c330 | 2134 | |
0bc40be8 | 2135 | if (engine->buffer) { |
21a2c58a CW |
2136 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
2137 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 2138 | |
aad29fbb | 2139 | intel_ring_unpin(engine->buffer); |
7e37f889 | 2140 | intel_ring_free(engine->buffer); |
0bc40be8 | 2141 | engine->buffer = NULL; |
b0366a54 | 2142 | } |
78501eac | 2143 | |
0bc40be8 TU |
2144 | if (engine->cleanup) |
2145 | engine->cleanup(engine); | |
8d19215b | 2146 | |
3177659a | 2147 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
0bc40be8 TU |
2148 | WARN_ON(engine->id != RCS); |
2149 | cleanup_phys_status_page(engine); | |
3177659a CS |
2150 | } else { |
2151 | cleanup_status_page(engine); | |
7d3fdfff | 2152 | } |
44e895a8 | 2153 | |
96a945aa | 2154 | intel_engine_cleanup_common(engine); |
0cb26a8e | 2155 | |
c033666a | 2156 | engine->i915 = NULL; |
3b3f1650 AG |
2157 | dev_priv->engine[engine->id] = NULL; |
2158 | kfree(engine); | |
62fdfeaf EA |
2159 | } |
2160 | ||
821ed7df CW |
2161 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
2162 | { | |
2163 | struct intel_engine_cs *engine; | |
3b3f1650 | 2164 | enum intel_engine_id id; |
821ed7df | 2165 | |
3b3f1650 | 2166 | for_each_engine(engine, dev_priv, id) { |
821ed7df CW |
2167 | engine->buffer->head = engine->buffer->tail; |
2168 | engine->buffer->last_retired_head = -1; | |
2169 | } | |
2170 | } | |
2171 | ||
f73e7399 | 2172 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 2173 | { |
6310346e CW |
2174 | int ret; |
2175 | ||
e8a9c58f CW |
2176 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
2177 | ||
6310346e CW |
2178 | /* Flush enough space to reduce the likelihood of waiting after |
2179 | * we start building the request - in which case we will just | |
2180 | * have to repeat work. | |
2181 | */ | |
a0442461 | 2182 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2183 | |
e8a9c58f | 2184 | GEM_BUG_ON(!request->engine->buffer); |
1dae2dfb | 2185 | request->ring = request->engine->buffer; |
6310346e CW |
2186 | |
2187 | ret = intel_ring_begin(request, 0); | |
2188 | if (ret) | |
2189 | return ret; | |
2190 | ||
a0442461 | 2191 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2192 | return 0; |
9d773091 CW |
2193 | } |
2194 | ||
987046ad CW |
2195 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2196 | { | |
7e37f889 | 2197 | struct intel_ring *ring = req->ring; |
987046ad | 2198 | struct drm_i915_gem_request *target; |
e95433c7 CW |
2199 | long timeout; |
2200 | ||
2201 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
987046ad | 2202 | |
1dae2dfb CW |
2203 | intel_ring_update_space(ring); |
2204 | if (ring->space >= bytes) | |
987046ad CW |
2205 | return 0; |
2206 | ||
2207 | /* | |
2208 | * Space is reserved in the ringbuffer for finalising the request, | |
2209 | * as that cannot be allowed to fail. During request finalisation, | |
2210 | * reserved_space is set to 0 to stop the overallocation and the | |
2211 | * assumption is that then we never need to wait (which has the | |
2212 | * risk of failing with EINTR). | |
2213 | * | |
2214 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2215 | */ | |
0251a963 | 2216 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 2217 | |
675d9ad7 | 2218 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
2219 | unsigned space; |
2220 | ||
987046ad | 2221 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
2222 | space = __intel_ring_space(target->postfix, ring->tail, |
2223 | ring->size); | |
987046ad CW |
2224 | if (space >= bytes) |
2225 | break; | |
79bbcc29 | 2226 | } |
29b1b415 | 2227 | |
675d9ad7 | 2228 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
2229 | return -ENOSPC; |
2230 | ||
e95433c7 CW |
2231 | timeout = i915_wait_request(target, |
2232 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
2233 | MAX_SCHEDULE_TIMEOUT); | |
2234 | if (timeout < 0) | |
2235 | return timeout; | |
7da844c5 | 2236 | |
7da844c5 CW |
2237 | i915_gem_request_retire_upto(target); |
2238 | ||
2239 | intel_ring_update_space(ring); | |
2240 | GEM_BUG_ON(ring->space < bytes); | |
2241 | return 0; | |
29b1b415 JH |
2242 | } |
2243 | ||
987046ad | 2244 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2245 | { |
7e37f889 | 2246 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2247 | int remain_actual = ring->size - ring->tail; |
2248 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2249 | int bytes = num_dwords * sizeof(u32); |
2250 | int total_bytes, wait_bytes; | |
79bbcc29 | 2251 | bool need_wrap = false; |
29b1b415 | 2252 | |
0251a963 | 2253 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2254 | |
79bbcc29 JH |
2255 | if (unlikely(bytes > remain_usable)) { |
2256 | /* | |
2257 | * Not enough space for the basic request. So need to flush | |
2258 | * out the remainder and then wait for base + reserved. | |
2259 | */ | |
2260 | wait_bytes = remain_actual + total_bytes; | |
2261 | need_wrap = true; | |
987046ad CW |
2262 | } else if (unlikely(total_bytes > remain_usable)) { |
2263 | /* | |
2264 | * The base request will fit but the reserved space | |
2265 | * falls off the end. So we don't need an immediate wrap | |
2266 | * and only need to effectively wait for the reserved | |
2267 | * size space from the start of ringbuffer. | |
2268 | */ | |
0251a963 | 2269 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2270 | } else { |
987046ad CW |
2271 | /* No wrapping required, just waiting. */ |
2272 | wait_bytes = total_bytes; | |
cbcc80df MK |
2273 | } |
2274 | ||
1dae2dfb | 2275 | if (wait_bytes > ring->space) { |
987046ad | 2276 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2277 | if (unlikely(ret)) |
2278 | return ret; | |
2279 | } | |
2280 | ||
987046ad | 2281 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2282 | GEM_BUG_ON(remain_actual > ring->space); |
2283 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2284 | |
987046ad | 2285 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2286 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2287 | ring->tail = 0; | |
2288 | ring->space -= remain_actual; | |
987046ad | 2289 | } |
304d695c | 2290 | |
1dae2dfb CW |
2291 | ring->space -= bytes; |
2292 | GEM_BUG_ON(ring->space < 0); | |
eca56a35 | 2293 | GEM_BUG_ONLY(ring->advance = ring->tail + bytes); |
304d695c | 2294 | return 0; |
8187a2b7 | 2295 | } |
78501eac | 2296 | |
753b1ad4 | 2297 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2298 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2299 | { |
7e37f889 | 2300 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2301 | int num_dwords = |
2302 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2303 | int ret; |
2304 | ||
2305 | if (num_dwords == 0) | |
2306 | return 0; | |
2307 | ||
18393f63 | 2308 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2309 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2310 | if (ret) |
2311 | return ret; | |
2312 | ||
2313 | while (num_dwords--) | |
b5321f30 | 2314 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2315 | |
b5321f30 | 2316 | intel_ring_advance(ring); |
753b1ad4 VS |
2317 | |
2318 | return 0; | |
2319 | } | |
2320 | ||
c5efa1ad | 2321 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 2322 | { |
c5efa1ad | 2323 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2324 | |
76f8421f CW |
2325 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2326 | ||
881f47b6 | 2327 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2328 | |
2329 | /* Disable notification that the ring is IDLE. The GT | |
2330 | * will then assume that it is busy and bring it out of rc6. | |
2331 | */ | |
76f8421f CW |
2332 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2333 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2334 | |
2335 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2336 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2337 | |
12f55818 | 2338 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2339 | if (intel_wait_for_register_fw(dev_priv, |
2340 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2341 | GEN6_BSD_SLEEP_INDICATOR, | |
2342 | 0, | |
2343 | 50)) | |
12f55818 | 2344 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2345 | |
12f55818 | 2346 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2347 | i9xx_submit_request(request); |
12f55818 CW |
2348 | |
2349 | /* Let the ring send IDLE messages to the GT again, | |
2350 | * and so let it sleep to conserve power when idle. | |
2351 | */ | |
76f8421f CW |
2352 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2353 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2354 | ||
2355 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2356 | } |
2357 | ||
7c9cf4e3 | 2358 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 2359 | { |
7e37f889 | 2360 | struct intel_ring *ring = req->ring; |
71a77e07 | 2361 | uint32_t cmd; |
b72f3acb CW |
2362 | int ret; |
2363 | ||
5fb9de1a | 2364 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2365 | if (ret) |
2366 | return ret; | |
2367 | ||
71a77e07 | 2368 | cmd = MI_FLUSH_DW; |
c033666a | 2369 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2370 | cmd += 1; |
f0a1fb10 CW |
2371 | |
2372 | /* We always require a command barrier so that subsequent | |
2373 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2374 | * wrt the contents of the write cache being flushed to memory | |
2375 | * (and thus being coherent from the CPU). | |
2376 | */ | |
2377 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2378 | ||
9a289771 JB |
2379 | /* |
2380 | * Bspec vol 1c.5 - video engine command streamer: | |
2381 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2382 | * operation is complete. This bit is only valid when the | |
2383 | * Post-Sync Operation field is a value of 1h or 3h." | |
2384 | */ | |
7c9cf4e3 | 2385 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
2386 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2387 | ||
b5321f30 CW |
2388 | intel_ring_emit(ring, cmd); |
2389 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2390 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2391 | intel_ring_emit(ring, 0); /* upper addr */ |
2392 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2393 | } else { |
b5321f30 CW |
2394 | intel_ring_emit(ring, 0); |
2395 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2396 | } |
b5321f30 | 2397 | intel_ring_advance(ring); |
b72f3acb | 2398 | return 0; |
881f47b6 XH |
2399 | } |
2400 | ||
1c7a0623 | 2401 | static int |
803688ba CW |
2402 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
2403 | u64 offset, u32 len, | |
2404 | unsigned int dispatch_flags) | |
1c7a0623 | 2405 | { |
7e37f889 | 2406 | struct intel_ring *ring = req->ring; |
b5321f30 | 2407 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2408 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2409 | int ret; |
2410 | ||
5fb9de1a | 2411 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2412 | if (ret) |
2413 | return ret; | |
2414 | ||
2415 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2416 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2417 | (dispatch_flags & I915_DISPATCH_RS ? |
2418 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2419 | intel_ring_emit(ring, lower_32_bits(offset)); |
2420 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2421 | intel_ring_emit(ring, MI_NOOP); | |
2422 | intel_ring_advance(ring); | |
1c7a0623 BW |
2423 | |
2424 | return 0; | |
2425 | } | |
2426 | ||
d7d4eedd | 2427 | static int |
803688ba CW |
2428 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
2429 | u64 offset, u32 len, | |
2430 | unsigned int dispatch_flags) | |
d7d4eedd | 2431 | { |
7e37f889 | 2432 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2433 | int ret; |
2434 | ||
5fb9de1a | 2435 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2436 | if (ret) |
2437 | return ret; | |
2438 | ||
b5321f30 | 2439 | intel_ring_emit(ring, |
77072258 | 2440 | MI_BATCH_BUFFER_START | |
8e004efc | 2441 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2442 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2443 | (dispatch_flags & I915_DISPATCH_RS ? | |
2444 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2445 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2446 | intel_ring_emit(ring, offset); |
2447 | intel_ring_advance(ring); | |
d7d4eedd CW |
2448 | |
2449 | return 0; | |
2450 | } | |
2451 | ||
881f47b6 | 2452 | static int |
803688ba CW |
2453 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
2454 | u64 offset, u32 len, | |
2455 | unsigned int dispatch_flags) | |
881f47b6 | 2456 | { |
7e37f889 | 2457 | struct intel_ring *ring = req->ring; |
0206e353 | 2458 | int ret; |
ab6f8e32 | 2459 | |
5fb9de1a | 2460 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2461 | if (ret) |
2462 | return ret; | |
e1f99ce6 | 2463 | |
b5321f30 | 2464 | intel_ring_emit(ring, |
d7d4eedd | 2465 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2466 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2467 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2468 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2469 | intel_ring_emit(ring, offset); |
2470 | intel_ring_advance(ring); | |
ab6f8e32 | 2471 | |
0206e353 | 2472 | return 0; |
881f47b6 XH |
2473 | } |
2474 | ||
549f7365 CW |
2475 | /* Blitter support (SandyBridge+) */ |
2476 | ||
7c9cf4e3 | 2477 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 2478 | { |
7e37f889 | 2479 | struct intel_ring *ring = req->ring; |
71a77e07 | 2480 | uint32_t cmd; |
b72f3acb CW |
2481 | int ret; |
2482 | ||
5fb9de1a | 2483 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2484 | if (ret) |
2485 | return ret; | |
2486 | ||
71a77e07 | 2487 | cmd = MI_FLUSH_DW; |
c033666a | 2488 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2489 | cmd += 1; |
f0a1fb10 CW |
2490 | |
2491 | /* We always require a command barrier so that subsequent | |
2492 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2493 | * wrt the contents of the write cache being flushed to memory | |
2494 | * (and thus being coherent from the CPU). | |
2495 | */ | |
2496 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2497 | ||
9a289771 JB |
2498 | /* |
2499 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2500 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2501 | * operation is complete. This bit is only valid when the | |
2502 | * Post-Sync Operation field is a value of 1h or 3h." | |
2503 | */ | |
7c9cf4e3 | 2504 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 2505 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2506 | intel_ring_emit(ring, cmd); |
2507 | intel_ring_emit(ring, | |
e2f80391 | 2508 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2509 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2510 | intel_ring_emit(ring, 0); /* upper addr */ |
2511 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2512 | } else { |
b5321f30 CW |
2513 | intel_ring_emit(ring, 0); |
2514 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2515 | } |
b5321f30 | 2516 | intel_ring_advance(ring); |
fd3da6c9 | 2517 | |
b72f3acb | 2518 | return 0; |
8d19215b ZN |
2519 | } |
2520 | ||
d9a64610 TU |
2521 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2522 | struct intel_engine_cs *engine) | |
2523 | { | |
db3d4019 | 2524 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2525 | int ret, i; |
db3d4019 | 2526 | |
39df9190 | 2527 | if (!i915.semaphores) |
db3d4019 TU |
2528 | return; |
2529 | ||
51d545d0 CW |
2530 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
2531 | struct i915_vma *vma; | |
2532 | ||
f51455d4 | 2533 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
2534 | if (IS_ERR(obj)) |
2535 | goto err; | |
db3d4019 | 2536 | |
a01cb37a | 2537 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
2538 | if (IS_ERR(vma)) |
2539 | goto err_obj; | |
2540 | ||
2541 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
2542 | if (ret) | |
2543 | goto err_obj; | |
2544 | ||
2545 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
2546 | if (ret) | |
2547 | goto err_obj; | |
2548 | ||
2549 | dev_priv->semaphore = vma; | |
2550 | } | |
d9a64610 TU |
2551 | |
2552 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 2553 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 2554 | |
ad7bdb2b | 2555 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 2556 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
2557 | |
2558 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 2559 | u32 ring_offset; |
1b9e6650 TU |
2560 | |
2561 | if (i != engine->id) | |
2562 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2563 | else | |
2564 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2565 | ||
2566 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2567 | } | |
d9a64610 | 2568 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 2569 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 2570 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
2571 | |
2572 | /* | |
2573 | * The current semaphore is only applied on pre-gen8 | |
2574 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2575 | * platform. So the semaphore between RCS and VCS2 is | |
2576 | * initialized as INVALID. Gen8 will initialize the | |
2577 | * sema between VCS2 and RCS later. | |
2578 | */ | |
318f89ca | 2579 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
2580 | static const struct { |
2581 | u32 wait_mbox; | |
2582 | i915_reg_t mbox_reg; | |
318f89ca TU |
2583 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
2584 | [RCS_HW] = { | |
2585 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2586 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2587 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 2588 | }, |
318f89ca TU |
2589 | [VCS_HW] = { |
2590 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2591 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2592 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2593 | }, |
318f89ca TU |
2594 | [BCS_HW] = { |
2595 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2596 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2597 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2598 | }, |
318f89ca TU |
2599 | [VECS_HW] = { |
2600 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2601 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2602 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2603 | }, |
2604 | }; | |
2605 | u32 wait_mbox; | |
2606 | i915_reg_t mbox_reg; | |
2607 | ||
318f89ca | 2608 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2609 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2610 | mbox_reg = GEN6_NOSYNC; | |
2611 | } else { | |
318f89ca TU |
2612 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2613 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2614 | } |
2615 | ||
2616 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2617 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2618 | } | |
d9a64610 | 2619 | } |
51d545d0 CW |
2620 | |
2621 | return; | |
2622 | ||
2623 | err_obj: | |
2624 | i915_gem_object_put(obj); | |
2625 | err: | |
2626 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2627 | i915.semaphores = 0; | |
d9a64610 TU |
2628 | } |
2629 | ||
ed003078 CW |
2630 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2631 | struct intel_engine_cs *engine) | |
2632 | { | |
c78d6061 TU |
2633 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2634 | ||
ed003078 | 2635 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2636 | engine->irq_enable = gen8_irq_enable; |
2637 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2638 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2639 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2640 | engine->irq_enable = gen6_irq_enable; |
2641 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2642 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2643 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2644 | engine->irq_enable = gen5_irq_enable; |
2645 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2646 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2647 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2648 | engine->irq_enable = i9xx_irq_enable; |
2649 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2650 | } else { |
31bb59cc CW |
2651 | engine->irq_enable = i8xx_irq_enable; |
2652 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2653 | } |
2654 | } | |
2655 | ||
06a2fe22 TU |
2656 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2657 | struct intel_engine_cs *engine) | |
2658 | { | |
618e4ca7 CW |
2659 | intel_ring_init_irq(dev_priv, engine); |
2660 | intel_ring_init_semaphores(dev_priv, engine); | |
2661 | ||
1d8a1337 | 2662 | engine->init_hw = init_ring_common; |
821ed7df | 2663 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2664 | |
e8a9c58f CW |
2665 | engine->context_pin = intel_ring_context_pin; |
2666 | engine->context_unpin = intel_ring_context_unpin; | |
2667 | ||
f73e7399 CW |
2668 | engine->request_alloc = ring_request_alloc; |
2669 | ||
9b81d556 | 2670 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d CW |
2671 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
2672 | if (i915.semaphores) { | |
2673 | int num_rings; | |
2674 | ||
9b81d556 | 2675 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d CW |
2676 | |
2677 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2678 | if (INTEL_GEN(dev_priv) >= 8) { | |
2679 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2680 | } else { | |
2681 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2682 | if (num_rings & 1) | |
2683 | engine->emit_breadcrumb_sz++; | |
2684 | } | |
2685 | } | |
ddd66c51 | 2686 | engine->submit_request = i9xx_submit_request; |
6f7bef75 CW |
2687 | |
2688 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2689 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2690 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2691 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2692 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2693 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2694 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2695 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2696 | else |
803688ba | 2697 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2698 | } |
2699 | ||
8b3e2d36 | 2700 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2701 | { |
8b3e2d36 | 2702 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2703 | int ret; |
5c1143bb | 2704 | |
06a2fe22 TU |
2705 | intel_ring_default_vfuncs(dev_priv, engine); |
2706 | ||
61ff75ac CW |
2707 | if (HAS_L3_DPF(dev_priv)) |
2708 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2709 | |
c033666a | 2710 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2711 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2712 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2713 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2714 | engine->emit_flush = gen8_render_ring_flush; |
98f29e8d CW |
2715 | if (i915.semaphores) { |
2716 | int num_rings; | |
2717 | ||
e2f80391 | 2718 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d CW |
2719 | |
2720 | num_rings = | |
2721 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2722 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2723 | } | |
c033666a | 2724 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2725 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2726 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2727 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2728 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2729 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2730 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2731 | } else { |
c033666a | 2732 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2733 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2734 | else |
c7fe7d25 | 2735 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2736 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2737 | } |
707d9cf9 | 2738 | |
c033666a | 2739 | if (IS_HASWELL(dev_priv)) |
803688ba | 2740 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2741 | |
e2f80391 TU |
2742 | engine->init_hw = init_render_ring; |
2743 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2744 | |
acd27845 | 2745 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2746 | if (ret) |
2747 | return ret; | |
2748 | ||
f8973c21 | 2749 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2750 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2751 | if (ret) |
2752 | return ret; | |
2753 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2754 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2755 | if (ret) |
2756 | return ret; | |
2757 | } | |
2758 | ||
2759 | return 0; | |
5c1143bb XH |
2760 | } |
2761 | ||
8b3e2d36 | 2762 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2763 | { |
8b3e2d36 | 2764 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2765 | |
06a2fe22 TU |
2766 | intel_ring_default_vfuncs(dev_priv, engine); |
2767 | ||
c033666a | 2768 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2769 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2770 | if (IS_GEN6(dev_priv)) |
c5efa1ad | 2771 | engine->submit_request = gen6_bsd_submit_request; |
c7fe7d25 | 2772 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2773 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2774 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2775 | } else { |
e2f80391 | 2776 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2777 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2778 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2779 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2780 | else |
e2f80391 | 2781 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2782 | } |
58fa3835 | 2783 | |
acd27845 | 2784 | return intel_init_ring_buffer(engine); |
5c1143bb | 2785 | } |
549f7365 | 2786 | |
845f74a7 | 2787 | /** |
62659920 | 2788 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2789 | */ |
8b3e2d36 | 2790 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2791 | { |
8b3e2d36 | 2792 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2793 | |
2794 | intel_ring_default_vfuncs(dev_priv, engine); | |
2795 | ||
c7fe7d25 | 2796 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2797 | |
acd27845 | 2798 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2799 | } |
2800 | ||
8b3e2d36 | 2801 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2802 | { |
8b3e2d36 | 2803 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2804 | |
2805 | intel_ring_default_vfuncs(dev_priv, engine); | |
2806 | ||
c7fe7d25 | 2807 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2808 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2809 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2810 | |
acd27845 | 2811 | return intel_init_ring_buffer(engine); |
549f7365 | 2812 | } |
a7b9761d | 2813 | |
8b3e2d36 | 2814 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2815 | { |
8b3e2d36 | 2816 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2817 | |
2818 | intel_ring_default_vfuncs(dev_priv, engine); | |
2819 | ||
c7fe7d25 | 2820 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2821 | |
c78d6061 | 2822 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2823 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2824 | engine->irq_enable = hsw_vebox_irq_enable; |
2825 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2826 | } |
9a8a2213 | 2827 | |
acd27845 | 2828 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2829 | } |