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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
33 | |
34 | #include "i915_drv.h" | |
35 | #include "i915_gem_render_state.h" | |
eb8d0f5a | 36 | #include "i915_reset.h" |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
7d3c425f | 39 | #include "intel_workarounds.h" |
62fdfeaf | 40 | |
a0442461 CW |
41 | /* Rough estimate of the typical request size, performing a flush, |
42 | * set-context and then emitting the batch. | |
43 | */ | |
44 | #define LEGACY_REQUEST_SIZE 200 | |
45 | ||
89531e7d CW |
46 | static inline u32 hws_hangcheck_address(struct intel_engine_cs *engine) |
47 | { | |
48 | return (i915_ggtt_offset(engine->status_page.vma) + | |
49 | I915_GEM_HWS_HANGCHECK_ADDR); | |
50 | } | |
51 | ||
95aebcb2 | 52 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 53 | { |
95aebcb2 CW |
54 | unsigned int space; |
55 | ||
56 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
57 | ||
58 | ring->space = space; | |
59 | return space; | |
ebd0fd4b DG |
60 | } |
61 | ||
b72f3acb | 62 | static int |
e61e0f51 | 63 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 64 | { |
a889580c | 65 | unsigned int num_store_dw; |
73dec95e | 66 | u32 cmd, *cs; |
46f0f8d1 CW |
67 | |
68 | cmd = MI_FLUSH; | |
a889580c | 69 | num_store_dw = 0; |
7c9cf4e3 | 70 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 71 | cmd |= MI_READ_FLUSH; |
a889580c CW |
72 | if (mode & EMIT_FLUSH) |
73 | num_store_dw = 4; | |
46f0f8d1 | 74 | |
a889580c | 75 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
76 | if (IS_ERR(cs)) |
77 | return PTR_ERR(cs); | |
46f0f8d1 | 78 | |
73dec95e | 79 | *cs++ = cmd; |
a889580c CW |
80 | while (num_store_dw--) { |
81 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
82 | *cs++ = i915_scratch_offset(rq->i915); | |
83 | *cs++ = 0; | |
84 | } | |
85 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
86 | ||
e61e0f51 | 87 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
88 | |
89 | return 0; | |
90 | } | |
91 | ||
92 | static int | |
e61e0f51 | 93 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 94 | { |
73dec95e | 95 | u32 cmd, *cs; |
55f99bf2 | 96 | int i; |
6f392d54 | 97 | |
36d527de CW |
98 | /* |
99 | * read/write caches: | |
100 | * | |
101 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
102 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
103 | * also flushed at 2d versus 3d pipeline switches. | |
104 | * | |
105 | * read-only caches: | |
106 | * | |
107 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
108 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
109 | * | |
110 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
111 | * | |
112 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
113 | * invalidated when MI_EXE_FLUSH is set. | |
114 | * | |
115 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
116 | * invalidated with every MI_FLUSH. | |
117 | * | |
118 | * TLBs: | |
119 | * | |
120 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
121 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
122 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
123 | * are flushed at any MI_FLUSH. | |
124 | */ | |
125 | ||
b5321f30 | 126 | cmd = MI_FLUSH; |
7c9cf4e3 | 127 | if (mode & EMIT_INVALIDATE) { |
36d527de | 128 | cmd |= MI_EXE_FLUSH; |
cf819eff | 129 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
130 | cmd |= MI_INVALIDATE_ISP; |
131 | } | |
70eac33e | 132 | |
55f99bf2 CW |
133 | i = 2; |
134 | if (mode & EMIT_INVALIDATE) | |
135 | i += 20; | |
136 | ||
137 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
138 | if (IS_ERR(cs)) |
139 | return PTR_ERR(cs); | |
b72f3acb | 140 | |
73dec95e | 141 | *cs++ = cmd; |
55f99bf2 CW |
142 | |
143 | /* | |
144 | * A random delay to let the CS invalidate take effect? Without this | |
145 | * delay, the GPU relocation path fails as the CS does not see | |
146 | * the updated contents. Just as important, if we apply the flushes | |
147 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
148 | * write and before the invalidate on the next batch), the relocations | |
149 | * still fail. This implies that is a delay following invalidation | |
150 | * that is required to reset the caches as opposed to a delay to | |
151 | * ensure the memory is written. | |
152 | */ | |
153 | if (mode & EMIT_INVALIDATE) { | |
154 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 155 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
156 | *cs++ = 0; |
157 | *cs++ = 0; | |
158 | ||
159 | for (i = 0; i < 12; i++) | |
160 | *cs++ = MI_FLUSH; | |
161 | ||
162 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 163 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
164 | *cs++ = 0; |
165 | *cs++ = 0; | |
166 | } | |
167 | ||
168 | *cs++ = cmd; | |
169 | ||
e61e0f51 | 170 | intel_ring_advance(rq, cs); |
b72f3acb CW |
171 | |
172 | return 0; | |
8187a2b7 ZN |
173 | } |
174 | ||
179f4025 | 175 | /* |
8d315287 JB |
176 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
177 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
178 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
179 | * | |
180 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
181 | * produced by non-pipelined state commands), software needs to first | |
182 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
183 | * 0. | |
184 | * | |
185 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
186 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
187 | * | |
188 | * And the workaround for these two requires this workaround first: | |
189 | * | |
190 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
191 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
192 | * flushes. | |
193 | * | |
194 | * And this last workaround is tricky because of the requirements on | |
195 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
196 | * volume 2 part 1: | |
197 | * | |
198 | * "1 of the following must also be set: | |
199 | * - Render Target Cache Flush Enable ([12] of DW1) | |
200 | * - Depth Cache Flush Enable ([0] of DW1) | |
201 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
202 | * - Depth Stall ([13] of DW1) | |
203 | * - Post-Sync Operation ([13] of DW1) | |
204 | * - Notify Enable ([8] of DW1)" | |
205 | * | |
206 | * The cache flushes require the workaround flush that triggered this | |
207 | * one, so we can't use it. Depth stall would trigger the same. | |
208 | * Post-sync nonzero is what triggered this second workaround, so we | |
209 | * can't use that one either. Notify enable is IRQs, which aren't | |
210 | * really our business. That leaves only stall at scoreboard. | |
211 | */ | |
212 | static int | |
caa5915b | 213 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 214 | { |
51797499 | 215 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e TU |
216 | u32 *cs; |
217 | ||
e61e0f51 | 218 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
219 | if (IS_ERR(cs)) |
220 | return PTR_ERR(cs); | |
221 | ||
222 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
223 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
224 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
225 | *cs++ = 0; /* low dword */ | |
226 | *cs++ = 0; /* high dword */ | |
227 | *cs++ = MI_NOOP; | |
e61e0f51 | 228 | intel_ring_advance(rq, cs); |
73dec95e | 229 | |
e61e0f51 | 230 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
231 | if (IS_ERR(cs)) |
232 | return PTR_ERR(cs); | |
233 | ||
234 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
235 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
236 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
237 | *cs++ = 0; | |
238 | *cs++ = 0; | |
239 | *cs++ = MI_NOOP; | |
e61e0f51 | 240 | intel_ring_advance(rq, cs); |
8d315287 JB |
241 | |
242 | return 0; | |
243 | } | |
244 | ||
245 | static int | |
e61e0f51 | 246 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 247 | { |
51797499 | 248 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 249 | u32 *cs, flags = 0; |
8d315287 JB |
250 | int ret; |
251 | ||
b3111509 | 252 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 253 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
254 | if (ret) |
255 | return ret; | |
256 | ||
8d315287 JB |
257 | /* Just flush everything. Experiments have shown that reducing the |
258 | * number of bits based on the write domains has little performance | |
259 | * impact. | |
260 | */ | |
7c9cf4e3 | 261 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
262 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
263 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
264 | /* | |
265 | * Ensure that any following seqno writes only happen | |
266 | * when the render cache is indeed flushed. | |
267 | */ | |
97f209bc | 268 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 269 | } |
7c9cf4e3 | 270 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
271 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
272 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
273 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
274 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
275 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
276 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
277 | /* | |
278 | * TLB invalidate requires a post-sync write. | |
279 | */ | |
3ac78313 | 280 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 281 | } |
8d315287 | 282 | |
e61e0f51 | 283 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
284 | if (IS_ERR(cs)) |
285 | return PTR_ERR(cs); | |
8d315287 | 286 | |
73dec95e TU |
287 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
288 | *cs++ = flags; | |
289 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
290 | *cs++ = 0; | |
e61e0f51 | 291 | intel_ring_advance(rq, cs); |
8d315287 JB |
292 | |
293 | return 0; | |
294 | } | |
295 | ||
e1a73a54 | 296 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
297 | { |
298 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
299 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
300 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
301 | *cs++ = 0; | |
302 | *cs++ = 0; | |
303 | ||
304 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
305 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
306 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; | |
307 | *cs++ = 0; | |
308 | ||
309 | /* Finally we can flush and with it emit the breadcrumb */ | |
310 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
311 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
312 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
313 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
314 | PIPE_CONTROL_QW_WRITE | | |
315 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
316 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
317 | *cs++ = rq->fence.seqno; | |
318 | ||
89531e7d CW |
319 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
320 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
321 | *cs++ = hws_hangcheck_address(rq->engine) | PIPE_CONTROL_GLOBAL_GTT; | |
322 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
323 | ||
caa5915b CW |
324 | *cs++ = MI_USER_INTERRUPT; |
325 | *cs++ = MI_NOOP; | |
326 | ||
327 | rq->tail = intel_ring_offset(rq, cs); | |
328 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
329 | |
330 | return cs; | |
caa5915b | 331 | } |
caa5915b | 332 | |
f3987631 | 333 | static int |
e61e0f51 | 334 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 335 | { |
73dec95e | 336 | u32 *cs; |
f3987631 | 337 | |
e61e0f51 | 338 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
339 | if (IS_ERR(cs)) |
340 | return PTR_ERR(cs); | |
f3987631 | 341 | |
73dec95e TU |
342 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
343 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
344 | *cs++ = 0; | |
345 | *cs++ = 0; | |
e61e0f51 | 346 | intel_ring_advance(rq, cs); |
f3987631 PZ |
347 | |
348 | return 0; | |
349 | } | |
350 | ||
4772eaeb | 351 | static int |
e61e0f51 | 352 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 353 | { |
51797499 | 354 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 355 | u32 *cs, flags = 0; |
4772eaeb | 356 | |
f3987631 PZ |
357 | /* |
358 | * Ensure that any following seqno writes only happen when the render | |
359 | * cache is indeed flushed. | |
360 | * | |
361 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
362 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
363 | * don't try to be clever and just set it unconditionally. | |
364 | */ | |
365 | flags |= PIPE_CONTROL_CS_STALL; | |
366 | ||
4772eaeb PZ |
367 | /* Just flush everything. Experiments have shown that reducing the |
368 | * number of bits based on the write domains has little performance | |
369 | * impact. | |
370 | */ | |
7c9cf4e3 | 371 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
372 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
373 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 374 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 375 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 376 | } |
7c9cf4e3 | 377 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
378 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
379 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
380 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
381 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
382 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
383 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 384 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
385 | /* |
386 | * TLB invalidate requires a post-sync write. | |
387 | */ | |
388 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 389 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 390 | |
add284a3 CW |
391 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
392 | ||
f3987631 PZ |
393 | /* Workaround: we must issue a pipe_control with CS-stall bit |
394 | * set before a pipe_control command that has the state cache | |
395 | * invalidate bit set. */ | |
e61e0f51 | 396 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
397 | } |
398 | ||
e61e0f51 | 399 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
400 | if (IS_ERR(cs)) |
401 | return PTR_ERR(cs); | |
4772eaeb | 402 | |
73dec95e TU |
403 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
404 | *cs++ = flags; | |
405 | *cs++ = scratch_addr; | |
406 | *cs++ = 0; | |
e61e0f51 | 407 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
408 | |
409 | return 0; | |
410 | } | |
411 | ||
e1a73a54 | 412 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
413 | { |
414 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
415 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
416 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
417 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
418 | PIPE_CONTROL_FLUSH_ENABLE | | |
419 | PIPE_CONTROL_QW_WRITE | | |
420 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
421 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
422 | *cs++ = rq->timeline->hwsp_offset; |
423 | *cs++ = rq->fence.seqno; | |
424 | ||
89531e7d CW |
425 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
426 | *cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB; | |
427 | *cs++ = hws_hangcheck_address(rq->engine); | |
428 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
429 | ||
caa5915b CW |
430 | *cs++ = MI_USER_INTERRUPT; |
431 | *cs++ = MI_NOOP; | |
432 | ||
433 | rq->tail = intel_ring_offset(rq, cs); | |
434 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
435 | |
436 | return cs; | |
caa5915b | 437 | } |
caa5915b | 438 | |
e1a73a54 | 439 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 440 | { |
5013eb8c CW |
441 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
442 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
443 | ||
444 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
445 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
446 | *cs++ = rq->fence.seqno; | |
447 | ||
89531e7d CW |
448 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; |
449 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT; | |
450 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
451 | ||
caa5915b | 452 | *cs++ = MI_USER_INTERRUPT; |
b300fde8 | 453 | *cs++ = MI_NOOP; |
caa5915b CW |
454 | |
455 | rq->tail = intel_ring_offset(rq, cs); | |
456 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
457 | |
458 | return cs; | |
caa5915b | 459 | } |
caa5915b | 460 | |
1212bd82 | 461 | #define GEN7_XCS_WA 32 |
e1a73a54 | 462 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
463 | { |
464 | int i; | |
465 | ||
5013eb8c CW |
466 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
467 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
468 | ||
469 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
470 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
471 | *cs++ = rq->fence.seqno; | |
472 | ||
89531e7d CW |
473 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; |
474 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT; | |
475 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
476 | ||
1212bd82 CW |
477 | for (i = 0; i < GEN7_XCS_WA; i++) { |
478 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
479 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
480 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
481 | } |
482 | ||
483 | *cs++ = MI_FLUSH_DW; | |
484 | *cs++ = 0; | |
485 | *cs++ = 0; | |
486 | ||
487 | *cs++ = MI_USER_INTERRUPT; | |
1212bd82 CW |
488 | |
489 | rq->tail = intel_ring_offset(rq, cs); | |
490 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
491 | |
492 | return cs; | |
1212bd82 | 493 | } |
1212bd82 CW |
494 | #undef GEN7_XCS_WA |
495 | ||
060f2322 CW |
496 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
497 | { | |
498 | /* | |
499 | * Keep the render interrupt unmasked as this papers over | |
500 | * lost interrupts following a reset. | |
501 | */ | |
502 | if (engine->class == RENDER_CLASS) { | |
503 | if (INTEL_GEN(engine->i915) >= 6) | |
504 | mask &= ~BIT(0); | |
505 | else | |
506 | mask &= ~I915_USER_INTERRUPT; | |
507 | } | |
508 | ||
509 | intel_engine_set_hwsp_writemask(engine, mask); | |
510 | } | |
511 | ||
512 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 513 | { |
c033666a | 514 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
515 | u32 addr; |
516 | ||
d6acae36 | 517 | addr = lower_32_bits(phys); |
c033666a | 518 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
519 | addr |= (phys >> 28) & 0xf0; |
520 | ||
035dc1e0 DV |
521 | I915_WRITE(HWS_PGA, addr); |
522 | } | |
523 | ||
0ca88ba0 | 524 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 525 | { |
0ca88ba0 | 526 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 527 | |
0ca88ba0 CW |
528 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
529 | return sg_page(obj->mm.pages->sgl); | |
530 | } | |
531 | ||
532 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
533 | { | |
534 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
535 | set_hwstam(engine, ~0u); |
536 | } | |
537 | ||
538 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 539 | { |
c033666a | 540 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 541 | i915_reg_t hwsp; |
af75f269 | 542 | |
060f2322 CW |
543 | /* |
544 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
545 | * the ring registers as of gen7. |
546 | */ | |
cf819eff | 547 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 548 | switch (engine->id) { |
a2d3d265 MT |
549 | /* |
550 | * No more rings exist on Gen7. Default case is only to shut up | |
551 | * gcc switch check warning. | |
552 | */ | |
553 | default: | |
554 | GEM_BUG_ON(engine->id); | |
8a68d464 CW |
555 | /* fallthrough */ |
556 | case RCS0: | |
060f2322 | 557 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 | 558 | break; |
8a68d464 | 559 | case BCS0: |
060f2322 | 560 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 561 | break; |
8a68d464 | 562 | case VCS0: |
060f2322 | 563 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 | 564 | break; |
8a68d464 | 565 | case VECS0: |
060f2322 | 566 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
567 | break; |
568 | } | |
cf819eff | 569 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 570 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 571 | } else { |
060f2322 | 572 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 573 | } |
c5498089 | 574 | |
060f2322 CW |
575 | I915_WRITE(hwsp, offset); |
576 | POSTING_READ(hwsp); | |
577 | } | |
af75f269 | 578 | |
060f2322 CW |
579 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
580 | { | |
581 | struct drm_i915_private *dev_priv = engine->i915; | |
582 | i915_reg_t instpm = RING_INSTPM(engine->mmio_base); | |
583 | ||
584 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
585 | return; | |
586 | ||
587 | /* ring should be idle before issuing a sync flush*/ | |
588 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
589 | ||
590 | I915_WRITE(instpm, | |
591 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
592 | INSTPM_SYNC_FLUSH)); | |
593 | if (intel_wait_for_register(dev_priv, | |
594 | instpm, INSTPM_SYNC_FLUSH, 0, | |
595 | 1000)) | |
596 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
597 | engine->name); | |
598 | } | |
af75f269 | 599 | |
060f2322 CW |
600 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
601 | { | |
0ca88ba0 | 602 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 603 | set_hwstam(engine, ~0u); |
af75f269 | 604 | |
060f2322 | 605 | flush_cs_tlb(engine); |
af75f269 DL |
606 | } |
607 | ||
0bc40be8 | 608 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 609 | { |
c033666a | 610 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 611 | |
21a2c58a | 612 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 613 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
614 | if (intel_wait_for_register(dev_priv, |
615 | RING_MI_MODE(engine->mmio_base), | |
616 | MODE_IDLE, | |
617 | MODE_IDLE, | |
618 | 1000)) { | |
0bc40be8 TU |
619 | DRM_ERROR("%s : timed out trying to stop ring\n", |
620 | engine->name); | |
9bec9b13 CW |
621 | /* Sometimes we observe that the idle flag is not |
622 | * set even though the ring is empty. So double | |
623 | * check before giving up. | |
624 | */ | |
0bc40be8 | 625 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 626 | return false; |
9991ae78 CW |
627 | } |
628 | } | |
b7884eb4 | 629 | |
11caf551 CW |
630 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
631 | ||
0bc40be8 | 632 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 633 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 634 | |
11caf551 CW |
635 | /* The ring must be empty before it is disabled */ |
636 | I915_WRITE_CTL(engine, 0); | |
637 | ||
0bc40be8 | 638 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 639 | } |
8187a2b7 | 640 | |
0bc40be8 | 641 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 642 | { |
c033666a | 643 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 644 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
645 | int ret = 0; |
646 | ||
59bad947 | 647 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 648 | |
0bc40be8 | 649 | if (!stop_ring(engine)) { |
9991ae78 | 650 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
651 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
652 | "ctl %08x head %08x tail %08x start %08x\n", | |
653 | engine->name, | |
654 | I915_READ_CTL(engine), | |
655 | I915_READ_HEAD(engine), | |
656 | I915_READ_TAIL(engine), | |
657 | I915_READ_START(engine)); | |
8187a2b7 | 658 | |
0bc40be8 | 659 | if (!stop_ring(engine)) { |
6fd0d56e CW |
660 | DRM_ERROR("failed to set %s head to zero " |
661 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
662 | engine->name, |
663 | I915_READ_CTL(engine), | |
664 | I915_READ_HEAD(engine), | |
665 | I915_READ_TAIL(engine), | |
666 | I915_READ_START(engine)); | |
9991ae78 CW |
667 | ret = -EIO; |
668 | goto out; | |
6fd0d56e | 669 | } |
8187a2b7 ZN |
670 | } |
671 | ||
3177659a | 672 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 673 | ring_setup_phys_status_page(engine); |
3177659a | 674 | else |
060f2322 | 675 | ring_setup_status_page(engine); |
9991ae78 | 676 | |
ad07dfcd | 677 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 678 | |
ece4a17d | 679 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 680 | I915_READ_HEAD(engine); |
ece4a17d | 681 | |
0d8957c8 DV |
682 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
683 | * registers with the above sequence (the readback of the HEAD registers | |
684 | * also enforces ordering), otherwise the hw might lose the new ring | |
685 | * register values. */ | |
bde13ebd | 686 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
687 | |
688 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 689 | if (I915_READ_HEAD(engine)) |
8177e112 CW |
690 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
691 | engine->name, I915_READ_HEAD(engine)); | |
821ed7df | 692 | |
41d37680 CW |
693 | /* Check that the ring offsets point within the ring! */ |
694 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
695 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 696 | intel_ring_update_space(ring); |
b7f21899 CW |
697 | |
698 | /* First wake the ring up to an empty/idle ring */ | |
821ed7df | 699 | I915_WRITE_HEAD(engine, ring->head); |
b7f21899 | 700 | I915_WRITE_TAIL(engine, ring->head); |
821ed7df | 701 | (void)I915_READ_TAIL(engine); |
95468892 | 702 | |
62ae14b1 | 703 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 704 | |
8187a2b7 | 705 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
706 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
707 | RING_VALID, RING_VALID, | |
708 | 50)) { | |
e74cfed5 | 709 | DRM_ERROR("%s initialization failed " |
821ed7df | 710 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
711 | engine->name, |
712 | I915_READ_CTL(engine), | |
713 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
714 | I915_READ_HEAD(engine), ring->head, |
715 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 716 | I915_READ_START(engine), |
bde13ebd | 717 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
718 | ret = -EIO; |
719 | goto out; | |
8187a2b7 ZN |
720 | } |
721 | ||
7836cd02 CW |
722 | if (INTEL_GEN(dev_priv) > 2) |
723 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
724 | ||
b7f21899 CW |
725 | /* Now awake, let it get started */ |
726 | if (ring->tail != ring->head) { | |
727 | I915_WRITE_TAIL(engine, ring->tail); | |
728 | (void)I915_READ_TAIL(engine); | |
729 | } | |
730 | ||
d6fee0de | 731 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 732 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 733 | out: |
59bad947 | 734 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
735 | |
736 | return ret; | |
8187a2b7 ZN |
737 | } |
738 | ||
eb8d0f5a | 739 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 740 | { |
3f6e9822 | 741 | intel_engine_stop_cs(engine); |
5adfb772 CW |
742 | } |
743 | ||
eb8d0f5a | 744 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 745 | { |
eb8d0f5a CW |
746 | struct i915_timeline *tl = &engine->timeline; |
747 | struct i915_request *pos, *rq; | |
748 | unsigned long flags; | |
b3ee09a4 | 749 | u32 head; |
5adfb772 | 750 | |
eb8d0f5a CW |
751 | rq = NULL; |
752 | spin_lock_irqsave(&tl->lock, flags); | |
753 | list_for_each_entry(pos, &tl->requests, link) { | |
5013eb8c | 754 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
755 | rq = pos; |
756 | break; | |
757 | } | |
b3ee09a4 | 758 | } |
67e64564 | 759 | |
b300fde8 CW |
760 | GEM_TRACE("%s stalled? %s\n", engine->name, yesno(stalled)); |
761 | ||
67e64564 | 762 | /* |
eb8d0f5a | 763 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 764 | * |
eb8d0f5a CW |
765 | * Users of client default contexts do not rely on logical |
766 | * state preserved between batches so it is safe to execute | |
767 | * queued requests following the hang. Non default contexts | |
768 | * rely on preserved state, so skipping a batch loses the | |
769 | * evolution of the state and it needs to be considered corrupted. | |
770 | * Executing more queued batches on top of corrupted state is | |
771 | * risky. But we take the risk by trying to advance through | |
772 | * the queued requests in order to make the client behaviour | |
773 | * more predictable around resets, by not throwing away random | |
774 | * amount of batches it has prepared for execution. Sophisticated | |
775 | * clients can use gem_reset_stats_ioctl and dma fence status | |
776 | * (exported via sync_file info ioctl on explicit fences) to observe | |
777 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 778 | * |
eb8d0f5a CW |
779 | * The context ban, and ultimately the client ban, mechanism are safety |
780 | * valves if client submission ends up resulting in nothing more than | |
781 | * subsequent hangs. | |
c0dcb203 | 782 | */ |
eb8d0f5a | 783 | |
b3ee09a4 | 784 | if (rq) { |
eb8d0f5a CW |
785 | /* |
786 | * Try to restore the logical GPU state to match the | |
787 | * continuation of the request queue. If we skip the | |
788 | * context/PD restore, then the next request may try to execute | |
789 | * assuming that its context is valid and loaded on the GPU and | |
790 | * so may try to access invalid memory, prompting repeated GPU | |
791 | * hangs. | |
792 | * | |
793 | * If the request was guilty, we still restore the logical | |
794 | * state in case the next request requires it (e.g. the | |
795 | * aliasing ppgtt), but skip over the hung batch. | |
796 | * | |
797 | * If the request was innocent, we try to replay the request | |
798 | * with the restored context. | |
799 | */ | |
800 | i915_reset_request(rq, stalled); | |
801 | ||
802 | GEM_BUG_ON(rq->ring != engine->buffer); | |
803 | head = rq->head; | |
804 | } else { | |
805 | head = engine->buffer->tail; | |
c0dcb203 | 806 | } |
eb8d0f5a CW |
807 | engine->buffer->head = intel_ring_wrap(engine->buffer, head); |
808 | ||
809 | spin_unlock_irqrestore(&tl->lock, flags); | |
821ed7df CW |
810 | } |
811 | ||
5adfb772 CW |
812 | static void reset_finish(struct intel_engine_cs *engine) |
813 | { | |
814 | } | |
815 | ||
e61e0f51 | 816 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
817 | { |
818 | int ret; | |
819 | ||
452420d2 | 820 | ret = intel_engine_emit_ctx_wa(rq); |
8f0e2b9d DV |
821 | if (ret != 0) |
822 | return ret; | |
823 | ||
e61e0f51 | 824 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 825 | if (ret) |
e26e1b97 | 826 | return ret; |
8f0e2b9d | 827 | |
e26e1b97 | 828 | return 0; |
8f0e2b9d DV |
829 | } |
830 | ||
0bc40be8 | 831 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 832 | { |
c033666a | 833 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 834 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
835 | if (ret) |
836 | return ret; | |
a69ffdbf | 837 | |
61a563a2 | 838 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 839 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 840 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
841 | |
842 | /* We need to disable the AsyncFlip performance optimisations in order | |
843 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
844 | * programmed to '1' on all products. | |
8693a824 | 845 | * |
2441f877 | 846 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 847 | */ |
00690008 | 848 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
849 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
850 | ||
f05bb0c7 | 851 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 852 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 853 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 854 | I915_WRITE(GFX_MODE, |
aa83e30d | 855 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 856 | |
01fa0302 | 857 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 858 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 859 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 860 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 861 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 862 | |
cf819eff | 863 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
864 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
865 | * "If this bit is set, STCunit will have LRA as replacement | |
866 | * policy. [...] This bit must be reset. LRA replacement | |
867 | * policy is not supported." | |
868 | */ | |
869 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 870 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
871 | } |
872 | ||
00690008 | 873 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 874 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 875 | |
c56b89f1 | 876 | if (INTEL_GEN(dev_priv) >= 6) |
035ea405 | 877 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
15b9f80e | 878 | |
59b449d5 | 879 | return 0; |
8187a2b7 ZN |
880 | } |
881 | ||
27a5f61b CW |
882 | static void cancel_requests(struct intel_engine_cs *engine) |
883 | { | |
e61e0f51 | 884 | struct i915_request *request; |
27a5f61b CW |
885 | unsigned long flags; |
886 | ||
a89d1f92 | 887 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
888 | |
889 | /* Mark all submitted requests as skipped. */ | |
a89d1f92 | 890 | list_for_each_entry(request, &engine->timeline.requests, link) { |
5013eb8c CW |
891 | if (!i915_request_signaled(request)) |
892 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 893 | |
5013eb8c | 894 | i915_request_mark_complete(request); |
27a5f61b | 895 | } |
3800960a | 896 | |
27a5f61b CW |
897 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
898 | ||
a89d1f92 | 899 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
900 | } |
901 | ||
e61e0f51 | 902 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d CW |
903 | { |
904 | struct drm_i915_private *dev_priv = request->i915; | |
905 | ||
e61e0f51 | 906 | i915_request_submit(request); |
d55ac5bf | 907 | |
e6ba9992 CW |
908 | I915_WRITE_TAIL(request->engine, |
909 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
910 | } |
911 | ||
e1a73a54 | 912 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 913 | { |
5013eb8c CW |
914 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
915 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
916 | ||
caa5915b CW |
917 | *cs++ = MI_FLUSH; |
918 | ||
5013eb8c CW |
919 | *cs++ = MI_STORE_DWORD_INDEX; |
920 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
921 | *cs++ = rq->fence.seqno; | |
922 | ||
89531e7d CW |
923 | *cs++ = MI_STORE_DWORD_INDEX; |
924 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR; | |
925 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
926 | ||
73dec95e | 927 | *cs++ = MI_USER_INTERRUPT; |
1ec14ad3 | 928 | |
e61e0f51 CW |
929 | rq->tail = intel_ring_offset(rq, cs); |
930 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
931 | |
932 | return cs; | |
1ec14ad3 | 933 | } |
98f29e8d | 934 | |
835051d3 | 935 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 936 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 937 | { |
835051d3 CW |
938 | int i; |
939 | ||
5013eb8c CW |
940 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
941 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
942 | ||
835051d3 CW |
943 | *cs++ = MI_FLUSH; |
944 | ||
89531e7d CW |
945 | *cs++ = MI_STORE_DWORD_INDEX; |
946 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR; | |
947 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
948 | ||
835051d3 CW |
949 | BUILD_BUG_ON(GEN5_WA_STORES < 1); |
950 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
951 | *cs++ = MI_STORE_DWORD_INDEX; | |
b300fde8 CW |
952 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
953 | *cs++ = rq->fence.seqno; | |
835051d3 CW |
954 | } |
955 | ||
956 | *cs++ = MI_USER_INTERRUPT; | |
b300fde8 | 957 | *cs++ = MI_NOOP; |
835051d3 CW |
958 | |
959 | rq->tail = intel_ring_offset(rq, cs); | |
960 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
961 | |
962 | return cs; | |
c6df541c | 963 | } |
835051d3 | 964 | #undef GEN5_WA_STORES |
c6df541c | 965 | |
31bb59cc CW |
966 | static void |
967 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 968 | { |
31bb59cc | 969 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
970 | } |
971 | ||
972 | static void | |
31bb59cc | 973 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 974 | { |
31bb59cc | 975 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
976 | } |
977 | ||
31bb59cc CW |
978 | static void |
979 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 980 | { |
c033666a | 981 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 982 | |
31bb59cc CW |
983 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
984 | I915_WRITE(IMR, dev_priv->irq_mask); | |
985 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
986 | } |
987 | ||
8187a2b7 | 988 | static void |
31bb59cc | 989 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 990 | { |
c033666a | 991 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 992 | |
31bb59cc CW |
993 | dev_priv->irq_mask |= engine->irq_enable_mask; |
994 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
995 | } |
996 | ||
31bb59cc CW |
997 | static void |
998 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 999 | { |
c033666a | 1000 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1001 | |
31bb59cc CW |
1002 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1003 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1004 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1005 | } |
1006 | ||
1007 | static void | |
31bb59cc | 1008 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1009 | { |
c033666a | 1010 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1011 | |
31bb59cc CW |
1012 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1013 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1014 | } |
1015 | ||
b72f3acb | 1016 | static int |
e61e0f51 | 1017 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 1018 | { |
73dec95e | 1019 | u32 *cs; |
b72f3acb | 1020 | |
e61e0f51 | 1021 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1022 | if (IS_ERR(cs)) |
1023 | return PTR_ERR(cs); | |
b72f3acb | 1024 | |
73dec95e TU |
1025 | *cs++ = MI_FLUSH; |
1026 | *cs++ = MI_NOOP; | |
e61e0f51 | 1027 | intel_ring_advance(rq, cs); |
b72f3acb | 1028 | return 0; |
d1b851fc ZN |
1029 | } |
1030 | ||
31bb59cc CW |
1031 | static void |
1032 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1033 | { |
c033666a | 1034 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1035 | |
61ff75ac CW |
1036 | I915_WRITE_IMR(engine, |
1037 | ~(engine->irq_enable_mask | | |
1038 | engine->irq_keep_mask)); | |
476af9c2 CW |
1039 | |
1040 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1041 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1042 | ||
31bb59cc | 1043 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1044 | } |
1045 | ||
1046 | static void | |
31bb59cc | 1047 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1048 | { |
c033666a | 1049 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1050 | |
61ff75ac | 1051 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1052 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1053 | } |
1054 | ||
31bb59cc CW |
1055 | static void |
1056 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1057 | { |
c033666a | 1058 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1059 | |
31bb59cc | 1060 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1061 | |
1062 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1063 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1064 | ||
f4e9af4f | 1065 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1066 | } |
1067 | ||
1068 | static void | |
31bb59cc | 1069 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1070 | { |
c033666a | 1071 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1072 | |
31bb59cc | 1073 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1074 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1075 | } |
1076 | ||
d1b851fc | 1077 | static int |
e61e0f51 | 1078 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1079 | u64 offset, u32 length, |
1080 | unsigned int dispatch_flags) | |
d1b851fc | 1081 | { |
73dec95e | 1082 | u32 *cs; |
78501eac | 1083 | |
e61e0f51 | 1084 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1085 | if (IS_ERR(cs)) |
1086 | return PTR_ERR(cs); | |
e1f99ce6 | 1087 | |
73dec95e TU |
1088 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1089 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1090 | *cs++ = offset; | |
e61e0f51 | 1091 | intel_ring_advance(rq, cs); |
78501eac | 1092 | |
d1b851fc ZN |
1093 | return 0; |
1094 | } | |
1095 | ||
b45305fc | 1096 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1097 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1098 | #define I830_TLB_ENTRIES (2) |
1099 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1100 | static int |
e61e0f51 | 1101 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1102 | u64 offset, u32 len, |
1103 | unsigned int dispatch_flags) | |
62fdfeaf | 1104 | { |
51797499 CW |
1105 | u32 *cs, cs_offset = i915_scratch_offset(rq->i915); |
1106 | ||
1107 | GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE); | |
62fdfeaf | 1108 | |
e61e0f51 | 1109 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1110 | if (IS_ERR(cs)) |
1111 | return PTR_ERR(cs); | |
62fdfeaf | 1112 | |
c4d69da1 | 1113 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1114 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1115 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1116 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1117 | *cs++ = cs_offset; | |
1118 | *cs++ = 0xdeadbeef; | |
1119 | *cs++ = MI_NOOP; | |
e61e0f51 | 1120 | intel_ring_advance(rq, cs); |
b45305fc | 1121 | |
8e004efc | 1122 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1123 | if (len > I830_BATCH_LIMIT) |
1124 | return -ENOSPC; | |
1125 | ||
e61e0f51 | 1126 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1127 | if (IS_ERR(cs)) |
1128 | return PTR_ERR(cs); | |
c4d69da1 CW |
1129 | |
1130 | /* Blit the batch (which has now all relocs applied) to the | |
1131 | * stable batch scratch bo area (so that the CS never | |
1132 | * stumbles over its tlb invalidation bug) ... | |
1133 | */ | |
73dec95e TU |
1134 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1135 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1136 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1137 | *cs++ = cs_offset; | |
1138 | *cs++ = 4096; | |
1139 | *cs++ = offset; | |
1140 | ||
1141 | *cs++ = MI_FLUSH; | |
1142 | *cs++ = MI_NOOP; | |
e61e0f51 | 1143 | intel_ring_advance(rq, cs); |
b45305fc DV |
1144 | |
1145 | /* ... and execute it. */ | |
c4d69da1 | 1146 | offset = cs_offset; |
b45305fc | 1147 | } |
e1f99ce6 | 1148 | |
e61e0f51 | 1149 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1150 | if (IS_ERR(cs)) |
1151 | return PTR_ERR(cs); | |
c4d69da1 | 1152 | |
73dec95e TU |
1153 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1154 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1155 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1156 | intel_ring_advance(rq, cs); |
c4d69da1 | 1157 | |
fb3256da DV |
1158 | return 0; |
1159 | } | |
1160 | ||
1161 | static int | |
e61e0f51 | 1162 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1163 | u64 offset, u32 len, |
1164 | unsigned int dispatch_flags) | |
fb3256da | 1165 | { |
73dec95e | 1166 | u32 *cs; |
fb3256da | 1167 | |
e61e0f51 | 1168 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1169 | if (IS_ERR(cs)) |
1170 | return PTR_ERR(cs); | |
fb3256da | 1171 | |
73dec95e TU |
1172 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1173 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1174 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1175 | intel_ring_advance(rq, cs); |
62fdfeaf | 1176 | |
62fdfeaf EA |
1177 | return 0; |
1178 | } | |
1179 | ||
5503cb0d | 1180 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1181 | { |
57e88531 | 1182 | struct i915_vma *vma = ring->vma; |
89d5efcc | 1183 | enum i915_map_type map = i915_coherent_map_type(vma->vm->i915); |
d822bb18 | 1184 | unsigned int flags; |
8305216f | 1185 | void *addr; |
7ba717cf TD |
1186 | int ret; |
1187 | ||
57e88531 | 1188 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1189 | |
5013eb8c CW |
1190 | ret = i915_timeline_pin(ring->timeline); |
1191 | if (ret) | |
1192 | return ret; | |
1193 | ||
d3ef1af6 | 1194 | flags = PIN_GLOBAL; |
496bcce3 JB |
1195 | |
1196 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1197 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1198 | ||
9d80841e | 1199 | if (vma->obj->stolen) |
57e88531 | 1200 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1201 | else |
1202 | flags |= PIN_HIGH; | |
def0c5f6 | 1203 | |
57e88531 | 1204 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1205 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1206 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1207 | else | |
1208 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1209 | if (unlikely(ret)) | |
5013eb8c | 1210 | goto unpin_timeline; |
57e88531 | 1211 | } |
7ba717cf | 1212 | |
7a859c65 | 1213 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1214 | if (unlikely(ret)) |
5013eb8c | 1215 | goto unpin_timeline; |
def0c5f6 | 1216 | |
9d80841e | 1217 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1218 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1219 | else | |
9d80841e | 1220 | addr = i915_gem_object_pin_map(vma->obj, map); |
5013eb8c CW |
1221 | if (IS_ERR(addr)) { |
1222 | ret = PTR_ERR(addr); | |
1223 | goto unpin_ring; | |
1224 | } | |
7ba717cf | 1225 | |
3d574a6b CW |
1226 | vma->obj->pin_global++; |
1227 | ||
32c04f16 | 1228 | ring->vaddr = addr; |
7ba717cf | 1229 | return 0; |
d2cad535 | 1230 | |
5013eb8c | 1231 | unpin_ring: |
57e88531 | 1232 | i915_vma_unpin(vma); |
5013eb8c CW |
1233 | unpin_timeline: |
1234 | i915_timeline_unpin(ring->timeline); | |
1235 | return ret; | |
7ba717cf TD |
1236 | } |
1237 | ||
e6ba9992 CW |
1238 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1239 | { | |
41d37680 CW |
1240 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1241 | ||
e6ba9992 CW |
1242 | ring->tail = tail; |
1243 | ring->head = tail; | |
1244 | ring->emit = tail; | |
1245 | intel_ring_update_space(ring); | |
1246 | } | |
1247 | ||
aad29fbb CW |
1248 | void intel_ring_unpin(struct intel_ring *ring) |
1249 | { | |
1250 | GEM_BUG_ON(!ring->vma); | |
1251 | GEM_BUG_ON(!ring->vaddr); | |
1252 | ||
e6ba9992 CW |
1253 | /* Discard any unused bytes beyond that submitted to hw. */ |
1254 | intel_ring_reset(ring, ring->tail); | |
1255 | ||
9d80841e | 1256 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1257 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1258 | else |
1259 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1260 | ring->vaddr = NULL; |
1261 | ||
3d574a6b | 1262 | ring->vma->obj->pin_global--; |
57e88531 | 1263 | i915_vma_unpin(ring->vma); |
5013eb8c CW |
1264 | |
1265 | i915_timeline_unpin(ring->timeline); | |
2919d291 OM |
1266 | } |
1267 | ||
57e88531 CW |
1268 | static struct i915_vma * |
1269 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1270 | { |
250f8c81 | 1271 | struct i915_address_space *vm = &dev_priv->ggtt.vm; |
05394f39 | 1272 | struct drm_i915_gem_object *obj; |
57e88531 | 1273 | struct i915_vma *vma; |
62fdfeaf | 1274 | |
187685cb | 1275 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1276 | if (!obj) |
2d6c4c84 | 1277 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1278 | if (IS_ERR(obj)) |
1279 | return ERR_CAST(obj); | |
8187a2b7 | 1280 | |
250f8c81 JB |
1281 | /* |
1282 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1283 | * if supported by the platform's GGTT. | |
1284 | */ | |
1285 | if (vm->has_read_only) | |
3e977ac6 | 1286 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1287 | |
250f8c81 | 1288 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1289 | if (IS_ERR(vma)) |
1290 | goto err; | |
1291 | ||
1292 | return vma; | |
e3efda49 | 1293 | |
57e88531 CW |
1294 | err: |
1295 | i915_gem_object_put(obj); | |
1296 | return vma; | |
e3efda49 CW |
1297 | } |
1298 | ||
7e37f889 | 1299 | struct intel_ring * |
65fcb806 | 1300 | intel_engine_create_ring(struct intel_engine_cs *engine, |
a89d1f92 | 1301 | struct i915_timeline *timeline, |
65fcb806 | 1302 | int size) |
01101fa7 | 1303 | { |
7e37f889 | 1304 | struct intel_ring *ring; |
57e88531 | 1305 | struct i915_vma *vma; |
01101fa7 | 1306 | |
8f942018 | 1307 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1308 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
a89d1f92 | 1309 | GEM_BUG_ON(timeline == &engine->timeline); |
b887d615 | 1310 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
8f942018 | 1311 | |
01101fa7 | 1312 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1313 | if (!ring) |
01101fa7 CW |
1314 | return ERR_PTR(-ENOMEM); |
1315 | ||
675d9ad7 | 1316 | INIT_LIST_HEAD(&ring->request_list); |
a89d1f92 | 1317 | ring->timeline = i915_timeline_get(timeline); |
675d9ad7 | 1318 | |
01101fa7 CW |
1319 | ring->size = size; |
1320 | /* Workaround an erratum on the i830 which causes a hang if | |
1321 | * the TAIL pointer points to within the last 2 cachelines | |
1322 | * of the buffer. | |
1323 | */ | |
1324 | ring->effective_size = size; | |
2a307c2e | 1325 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1326 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1327 | ||
01101fa7 CW |
1328 | intel_ring_update_space(ring); |
1329 | ||
57e88531 CW |
1330 | vma = intel_ring_create_vma(engine->i915, size); |
1331 | if (IS_ERR(vma)) { | |
01101fa7 | 1332 | kfree(ring); |
57e88531 | 1333 | return ERR_CAST(vma); |
01101fa7 | 1334 | } |
57e88531 | 1335 | ring->vma = vma; |
01101fa7 CW |
1336 | |
1337 | return ring; | |
1338 | } | |
1339 | ||
1340 | void | |
7e37f889 | 1341 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1342 | { |
f8a7fde4 CW |
1343 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1344 | ||
1345 | i915_vma_close(ring->vma); | |
1346 | __i915_gem_object_release_unless_active(obj); | |
1347 | ||
a89d1f92 | 1348 | i915_timeline_put(ring->timeline); |
01101fa7 CW |
1349 | kfree(ring); |
1350 | } | |
1351 | ||
1fc44d9b CW |
1352 | static void intel_ring_context_destroy(struct intel_context *ce) |
1353 | { | |
1354 | GEM_BUG_ON(ce->pin_count); | |
1355 | ||
efe79d48 CW |
1356 | if (!ce->state) |
1357 | return; | |
1358 | ||
1359 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1360 | i915_gem_object_put(ce->state->obj); | |
1fc44d9b CW |
1361 | } |
1362 | ||
a2bbf714 CW |
1363 | static int __context_pin_ppgtt(struct i915_gem_context *ctx) |
1364 | { | |
1365 | struct i915_hw_ppgtt *ppgtt; | |
1366 | int err = 0; | |
1367 | ||
1368 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1369 | if (ppgtt) | |
1370 | err = gen6_ppgtt_pin(ppgtt); | |
1371 | ||
1372 | return err; | |
1373 | } | |
1374 | ||
1375 | static void __context_unpin_ppgtt(struct i915_gem_context *ctx) | |
1376 | { | |
1377 | struct i915_hw_ppgtt *ppgtt; | |
1378 | ||
1379 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1380 | if (ppgtt) | |
1381 | gen6_ppgtt_unpin(ppgtt); | |
1382 | } | |
1383 | ||
1fc44d9b | 1384 | static int __context_pin(struct intel_context *ce) |
e8a9c58f | 1385 | { |
d901e8e6 CW |
1386 | struct i915_vma *vma; |
1387 | int err; | |
1388 | ||
1389 | vma = ce->state; | |
1390 | if (!vma) | |
1391 | return 0; | |
e8a9c58f | 1392 | |
f4e15af7 CW |
1393 | /* |
1394 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1395 | * We only want to do this on the first bind so that we do not stall |
1396 | * on an active context (which by nature is already on the GPU). | |
1397 | */ | |
1398 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
d901e8e6 CW |
1399 | err = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1400 | if (err) | |
1401 | return err; | |
e8a9c58f CW |
1402 | } |
1403 | ||
7a859c65 | 1404 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
d901e8e6 CW |
1405 | if (err) |
1406 | return err; | |
1407 | ||
1408 | /* | |
1409 | * And mark is as a globally pinned object to let the shrinker know | |
1410 | * it cannot reclaim the object until we release it. | |
1411 | */ | |
1412 | vma->obj->pin_global++; | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static void __context_unpin(struct intel_context *ce) | |
1418 | { | |
1419 | struct i915_vma *vma; | |
1420 | ||
1421 | vma = ce->state; | |
1422 | if (!vma) | |
1423 | return; | |
1424 | ||
1425 | vma->obj->pin_global--; | |
1426 | i915_vma_unpin(vma); | |
1427 | } | |
1428 | ||
1429 | static void intel_ring_context_unpin(struct intel_context *ce) | |
1430 | { | |
a2bbf714 | 1431 | __context_unpin_ppgtt(ce->gem_context); |
d901e8e6 CW |
1432 | __context_unpin(ce); |
1433 | ||
7e3d9a59 | 1434 | list_del(&ce->active_link); |
d901e8e6 | 1435 | i915_gem_context_put(ce->gem_context); |
e8a9c58f CW |
1436 | } |
1437 | ||
3204c343 CW |
1438 | static struct i915_vma * |
1439 | alloc_context_vma(struct intel_engine_cs *engine) | |
1440 | { | |
1441 | struct drm_i915_private *i915 = engine->i915; | |
1442 | struct drm_i915_gem_object *obj; | |
1443 | struct i915_vma *vma; | |
d2b4b979 | 1444 | int err; |
3204c343 | 1445 | |
63ffbcda | 1446 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1447 | if (IS_ERR(obj)) |
1448 | return ERR_CAST(obj); | |
1449 | ||
d2b4b979 CW |
1450 | if (engine->default_state) { |
1451 | void *defaults, *vaddr; | |
1452 | ||
1453 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1454 | if (IS_ERR(vaddr)) { | |
1455 | err = PTR_ERR(vaddr); | |
1456 | goto err_obj; | |
1457 | } | |
1458 | ||
1459 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1460 | I915_MAP_WB); | |
1461 | if (IS_ERR(defaults)) { | |
1462 | err = PTR_ERR(defaults); | |
1463 | goto err_map; | |
1464 | } | |
1465 | ||
1466 | memcpy(vaddr, defaults, engine->context_size); | |
1467 | ||
1468 | i915_gem_object_unpin_map(engine->default_state); | |
1469 | i915_gem_object_unpin_map(obj); | |
1470 | } | |
1471 | ||
3204c343 CW |
1472 | /* |
1473 | * Try to make the context utilize L3 as well as LLC. | |
1474 | * | |
1475 | * On VLV we don't have L3 controls in the PTEs so we | |
1476 | * shouldn't touch the cache level, especially as that | |
1477 | * would make the object snooped which might have a | |
1478 | * negative performance impact. | |
1479 | * | |
1480 | * Snooping is required on non-llc platforms in execlist | |
1481 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1482 | * get snooping anyway regardless of cache_level. | |
1483 | * | |
1484 | * This is only applicable for Ivy Bridge devices since | |
1485 | * later platforms don't have L3 control bits in the PTE. | |
1486 | */ | |
1487 | if (IS_IVYBRIDGE(i915)) { | |
1488 | /* Ignore any error, regard it as a simple optimisation */ | |
1489 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1490 | } | |
1491 | ||
82ad6443 | 1492 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); |
d2b4b979 CW |
1493 | if (IS_ERR(vma)) { |
1494 | err = PTR_ERR(vma); | |
1495 | goto err_obj; | |
1496 | } | |
3204c343 CW |
1497 | |
1498 | return vma; | |
d2b4b979 CW |
1499 | |
1500 | err_map: | |
1501 | i915_gem_object_unpin_map(obj); | |
1502 | err_obj: | |
1503 | i915_gem_object_put(obj); | |
1504 | return ERR_PTR(err); | |
3204c343 CW |
1505 | } |
1506 | ||
1fc44d9b CW |
1507 | static struct intel_context * |
1508 | __ring_context_pin(struct intel_engine_cs *engine, | |
1509 | struct i915_gem_context *ctx, | |
1510 | struct intel_context *ce) | |
0cb26a8e | 1511 | { |
1fc44d9b | 1512 | int err; |
0cb26a8e | 1513 | |
7e3d9a59 CW |
1514 | /* One ringbuffer to rule them all */ |
1515 | GEM_BUG_ON(!engine->buffer); | |
1516 | ce->ring = engine->buffer; | |
1517 | ||
63ffbcda | 1518 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1519 | struct i915_vma *vma; |
1520 | ||
1521 | vma = alloc_context_vma(engine); | |
1522 | if (IS_ERR(vma)) { | |
1fc44d9b | 1523 | err = PTR_ERR(vma); |
266a240b | 1524 | goto err; |
3204c343 CW |
1525 | } |
1526 | ||
1527 | ce->state = vma; | |
1528 | } | |
1529 | ||
d901e8e6 CW |
1530 | err = __context_pin(ce); |
1531 | if (err) | |
1532 | goto err; | |
0cb26a8e | 1533 | |
a2bbf714 CW |
1534 | err = __context_pin_ppgtt(ce->gem_context); |
1535 | if (err) | |
1536 | goto err_unpin; | |
1537 | ||
7e3d9a59 CW |
1538 | mutex_lock(&ctx->mutex); |
1539 | list_add(&ce->active_link, &ctx->active_engines); | |
1540 | mutex_unlock(&ctx->mutex); | |
1fc44d9b | 1541 | |
7e3d9a59 | 1542 | i915_gem_context_get(ctx); |
1fc44d9b | 1543 | return ce; |
266a240b | 1544 | |
a2bbf714 CW |
1545 | err_unpin: |
1546 | __context_unpin(ce); | |
266a240b | 1547 | err: |
0cb26a8e | 1548 | ce->pin_count = 0; |
1fc44d9b | 1549 | return ERR_PTR(err); |
0cb26a8e CW |
1550 | } |
1551 | ||
1fc44d9b CW |
1552 | static const struct intel_context_ops ring_context_ops = { |
1553 | .unpin = intel_ring_context_unpin, | |
1554 | .destroy = intel_ring_context_destroy, | |
1555 | }; | |
1556 | ||
1557 | static struct intel_context * | |
1558 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1559 | struct i915_gem_context *ctx) | |
0cb26a8e | 1560 | { |
ab82a063 | 1561 | struct intel_context *ce = to_intel_context(ctx, engine); |
0cb26a8e | 1562 | |
91c8a326 | 1563 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1564 | |
1fc44d9b CW |
1565 | if (likely(ce->pin_count++)) |
1566 | return ce; | |
1567 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ | |
0cb26a8e | 1568 | |
1fc44d9b | 1569 | ce->ops = &ring_context_ops; |
0cb26a8e | 1570 | |
1fc44d9b | 1571 | return __ring_context_pin(engine, ctx, ce); |
0cb26a8e CW |
1572 | } |
1573 | ||
acd27845 | 1574 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1575 | { |
a89d1f92 | 1576 | struct i915_timeline *timeline; |
d9d117e4 | 1577 | struct intel_ring *ring; |
1a5788bf | 1578 | int err; |
bfc882b4 | 1579 | |
52954edd CW |
1580 | err = intel_engine_setup_common(engine); |
1581 | if (err) | |
1582 | return err; | |
019bf277 | 1583 | |
52954edd CW |
1584 | timeline = i915_timeline_create(engine->i915, |
1585 | engine->name, | |
1586 | engine->status_page.vma); | |
a89d1f92 CW |
1587 | if (IS_ERR(timeline)) { |
1588 | err = PTR_ERR(timeline); | |
1589 | goto err; | |
1590 | } | |
85474441 | 1591 | GEM_BUG_ON(timeline->has_initial_breadcrumb); |
a89d1f92 CW |
1592 | |
1593 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
1594 | i915_timeline_put(timeline); | |
d822bb18 | 1595 | if (IS_ERR(ring)) { |
1a5788bf | 1596 | err = PTR_ERR(ring); |
486e93f7 | 1597 | goto err; |
d822bb18 CW |
1598 | } |
1599 | ||
5503cb0d | 1600 | err = intel_ring_pin(ring); |
1a5788bf CW |
1601 | if (err) |
1602 | goto err_ring; | |
1603 | ||
1604 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1605 | engine->buffer = ring; |
62fdfeaf | 1606 | |
d9d117e4 CW |
1607 | err = intel_engine_init_common(engine); |
1608 | if (err) | |
51797499 | 1609 | goto err_unpin; |
d9d117e4 | 1610 | |
52954edd CW |
1611 | GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma); |
1612 | ||
8ee14975 | 1613 | return 0; |
351e3db2 | 1614 | |
1fc44d9b CW |
1615 | err_unpin: |
1616 | intel_ring_unpin(ring); | |
1a5788bf CW |
1617 | err_ring: |
1618 | intel_ring_free(ring); | |
1a5788bf CW |
1619 | err: |
1620 | intel_engine_cleanup_common(engine); | |
1621 | return err; | |
62fdfeaf EA |
1622 | } |
1623 | ||
7e37f889 | 1624 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1625 | { |
1a5788bf | 1626 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1627 | |
1a5788bf CW |
1628 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1629 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1630 | |
1a5788bf CW |
1631 | intel_ring_unpin(engine->buffer); |
1632 | intel_ring_free(engine->buffer); | |
78501eac | 1633 | |
0bc40be8 TU |
1634 | if (engine->cleanup) |
1635 | engine->cleanup(engine); | |
8d19215b | 1636 | |
96a945aa | 1637 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1638 | |
3b3f1650 AG |
1639 | dev_priv->engine[engine->id] = NULL; |
1640 | kfree(engine); | |
62fdfeaf EA |
1641 | } |
1642 | ||
821ed7df CW |
1643 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1644 | { | |
1645 | struct intel_engine_cs *engine; | |
3b3f1650 | 1646 | enum intel_engine_id id; |
821ed7df | 1647 | |
e6ba9992 | 1648 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1649 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1650 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1651 | } |
1652 | ||
b3ee09a4 CW |
1653 | static int load_pd_dir(struct i915_request *rq, |
1654 | const struct i915_hw_ppgtt *ppgtt) | |
1655 | { | |
1656 | const struct intel_engine_cs * const engine = rq->engine; | |
1657 | u32 *cs; | |
1658 | ||
1659 | cs = intel_ring_begin(rq, 6); | |
1660 | if (IS_ERR(cs)) | |
1661 | return PTR_ERR(cs); | |
1662 | ||
1663 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1664 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1665 | *cs++ = PP_DIR_DCLV_2G; | |
1666 | ||
1667 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1668 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1669 | *cs++ = ppgtt->pd.base.ggtt_offset << 10; | |
1670 | ||
1671 | intel_ring_advance(rq, cs); | |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
d9d117e4 CW |
1676 | static int flush_pd_dir(struct i915_request *rq) |
1677 | { | |
1678 | const struct intel_engine_cs * const engine = rq->engine; | |
1679 | u32 *cs; | |
1680 | ||
1681 | cs = intel_ring_begin(rq, 4); | |
1682 | if (IS_ERR(cs)) | |
1683 | return PTR_ERR(cs); | |
1684 | ||
1685 | /* Stall until the page table load is complete */ | |
1686 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1687 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
51797499 | 1688 | *cs++ = i915_scratch_offset(rq->i915); |
d9d117e4 CW |
1689 | *cs++ = MI_NOOP; |
1690 | ||
1691 | intel_ring_advance(rq, cs); | |
1692 | return 0; | |
1693 | } | |
1694 | ||
e61e0f51 | 1695 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1696 | { |
1697 | struct drm_i915_private *i915 = rq->i915; | |
1698 | struct intel_engine_cs *engine = rq->engine; | |
1699 | enum intel_engine_id id; | |
8a68d464 CW |
1700 | const int num_engines = |
1701 | IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; | |
1fc719d1 | 1702 | bool force_restore = false; |
8911a31c CW |
1703 | int len; |
1704 | u32 *cs; | |
1705 | ||
1706 | flags |= MI_MM_SPACE_GTT; | |
1707 | if (IS_HASWELL(i915)) | |
1708 | /* These flags are for resource streamer on HSW+ */ | |
1709 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1710 | else | |
1711 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
1712 | ||
1713 | len = 4; | |
cf819eff | 1714 | if (IS_GEN(i915, 7)) |
8a68d464 | 1715 | len += 2 + (num_engines ? 4 * num_engines + 6 : 0); |
1fc719d1 CW |
1716 | if (flags & MI_FORCE_RESTORE) { |
1717 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1718 | flags &= ~MI_FORCE_RESTORE; | |
1719 | force_restore = true; | |
1720 | len += 2; | |
1721 | } | |
8911a31c CW |
1722 | |
1723 | cs = intel_ring_begin(rq, len); | |
1724 | if (IS_ERR(cs)) | |
1725 | return PTR_ERR(cs); | |
1726 | ||
1727 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1728 | if (IS_GEN(i915, 7)) { |
8911a31c | 1729 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
8a68d464 | 1730 | if (num_engines) { |
8911a31c CW |
1731 | struct intel_engine_cs *signaller; |
1732 | ||
8a68d464 | 1733 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1734 | for_each_engine(signaller, i915, id) { |
1735 | if (signaller == engine) | |
1736 | continue; | |
1737 | ||
1738 | *cs++ = i915_mmio_reg_offset( | |
1739 | RING_PSMI_CTL(signaller->mmio_base)); | |
1740 | *cs++ = _MASKED_BIT_ENABLE( | |
1741 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1742 | } | |
1743 | } | |
1744 | } | |
1745 | ||
1fc719d1 CW |
1746 | if (force_restore) { |
1747 | /* | |
1748 | * The HW doesn't handle being told to restore the current | |
1749 | * context very well. Quite often it likes goes to go off and | |
1750 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1751 | * A very simple fix to force the reload is to simply switch | |
1752 | * away from the current context and back again. | |
1753 | * | |
1754 | * Note that the kernel_context will contain random state | |
1755 | * following the INHIBIT_RESTORE. We accept this since we | |
1756 | * never use the kernel_context state; it is merely a | |
1757 | * placeholder we use to flush other contexts. | |
1758 | */ | |
1759 | *cs++ = MI_SET_CONTEXT; | |
1760 | *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context, | |
1761 | engine)->state) | | |
1762 | MI_MM_SPACE_GTT | | |
1763 | MI_RESTORE_INHIBIT; | |
1764 | } | |
1765 | ||
8911a31c CW |
1766 | *cs++ = MI_NOOP; |
1767 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1768 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1769 | /* |
1770 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1771 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1772 | */ | |
1773 | *cs++ = MI_NOOP; | |
1774 | ||
cf819eff | 1775 | if (IS_GEN(i915, 7)) { |
8a68d464 | 1776 | if (num_engines) { |
8911a31c CW |
1777 | struct intel_engine_cs *signaller; |
1778 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1779 | ||
8a68d464 | 1780 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1781 | for_each_engine(signaller, i915, id) { |
1782 | if (signaller == engine) | |
1783 | continue; | |
1784 | ||
1785 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1786 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1787 | *cs++ = _MASKED_BIT_DISABLE( | |
1788 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1789 | } | |
1790 | ||
1791 | /* Insert a delay before the next switch! */ | |
1792 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1793 | *cs++ = i915_mmio_reg_offset(last_reg); | |
51797499 | 1794 | *cs++ = i915_scratch_offset(rq->i915); |
8911a31c CW |
1795 | *cs++ = MI_NOOP; |
1796 | } | |
1797 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1798 | } | |
1799 | ||
1800 | intel_ring_advance(rq, cs); | |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | ||
e61e0f51 | 1805 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1806 | { |
1807 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1808 | int i; | |
1809 | ||
1810 | if (!remap_info) | |
1811 | return 0; | |
1812 | ||
1813 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1814 | if (IS_ERR(cs)) | |
1815 | return PTR_ERR(cs); | |
1816 | ||
1817 | /* | |
1818 | * Note: We do not worry about the concurrent register cacheline hang | |
1819 | * here because no other code should access these registers other than | |
1820 | * at initialization time. | |
1821 | */ | |
1822 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1823 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1824 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1825 | *cs++ = remap_info[i]; | |
1826 | } | |
1827 | *cs++ = MI_NOOP; | |
1828 | intel_ring_advance(rq, cs); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | ||
e61e0f51 | 1833 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1834 | { |
1835 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 CW |
1836 | struct i915_gem_context *ctx = rq->gem_context; |
1837 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
1838 | unsigned int unwind_mm = 0; | |
8911a31c CW |
1839 | u32 hw_flags = 0; |
1840 | int ret, i; | |
1841 | ||
1842 | lockdep_assert_held(&rq->i915->drm.struct_mutex); | |
1843 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); | |
1844 | ||
b3ee09a4 | 1845 | if (ppgtt) { |
e2a13d1b CW |
1846 | int loops; |
1847 | ||
1848 | /* | |
1849 | * Baytail takes a little more convincing that it really needs | |
1850 | * to reload the PD between contexts. It is not just a little | |
1851 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1852 | * adding a long loop around flush_pd_dir) is not as effective | |
1853 | * as reloading the PD umpteen times. 32 is derived from | |
1854 | * experimentation (gem_exec_parallel/fds) and has no good | |
1855 | * explanation. | |
1856 | */ | |
1857 | loops = 1; | |
8a68d464 | 1858 | if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) |
e2a13d1b CW |
1859 | loops = 32; |
1860 | ||
1861 | do { | |
1862 | ret = load_pd_dir(rq, ppgtt); | |
1863 | if (ret) | |
1864 | goto err; | |
1865 | } while (--loops); | |
8911a31c | 1866 | |
8a68d464 CW |
1867 | if (ppgtt->pd_dirty_engines & engine->mask) { |
1868 | unwind_mm = engine->mask; | |
1869 | ppgtt->pd_dirty_engines &= ~unwind_mm; | |
b3ee09a4 CW |
1870 | hw_flags = MI_FORCE_RESTORE; |
1871 | } | |
8911a31c CW |
1872 | } |
1873 | ||
b3ee09a4 | 1874 | if (rq->hw_context->state) { |
8a68d464 | 1875 | GEM_BUG_ON(engine->id != RCS0); |
8911a31c CW |
1876 | |
1877 | /* | |
1878 | * The kernel context(s) is treated as pure scratch and is not | |
1879 | * expected to retain any state (as we sacrifice it during | |
1880 | * suspend and on resume it may be corrupted). This is ok, | |
1881 | * as nothing actually executes using the kernel context; it | |
1882 | * is purely used for flushing user contexts. | |
1883 | */ | |
b3ee09a4 | 1884 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1885 | hw_flags = MI_RESTORE_INHIBIT; |
1886 | ||
1887 | ret = mi_set_context(rq, hw_flags); | |
1888 | if (ret) | |
1889 | goto err_mm; | |
8911a31c | 1890 | } |
8911a31c | 1891 | |
d9d117e4 | 1892 | if (ppgtt) { |
06348d30 CW |
1893 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1894 | if (ret) | |
1895 | goto err_mm; | |
1896 | ||
d9d117e4 CW |
1897 | ret = flush_pd_dir(rq); |
1898 | if (ret) | |
1899 | goto err_mm; | |
06348d30 CW |
1900 | |
1901 | /* | |
1902 | * Not only do we need a full barrier (post-sync write) after | |
1903 | * invalidating the TLBs, but we need to wait a little bit | |
1904 | * longer. Whether this is merely delaying us, or the | |
1905 | * subsequent flush is a key part of serialising with the | |
1906 | * post-sync op, this extra pass appears vital before a | |
1907 | * mm switch! | |
1908 | */ | |
1909 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1910 | if (ret) | |
1911 | goto err_mm; | |
1912 | ||
1913 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1914 | if (ret) | |
1915 | goto err_mm; | |
8911a31c CW |
1916 | } |
1917 | ||
b3ee09a4 | 1918 | if (ctx->remap_slice) { |
8911a31c | 1919 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1920 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1921 | continue; |
1922 | ||
1923 | ret = remap_l3(rq, i); | |
1924 | if (ret) | |
b3ee09a4 | 1925 | goto err_mm; |
8911a31c CW |
1926 | } |
1927 | ||
b3ee09a4 | 1928 | ctx->remap_slice = 0; |
8911a31c CW |
1929 | } |
1930 | ||
1931 | return 0; | |
1932 | ||
8911a31c | 1933 | err_mm: |
b3ee09a4 | 1934 | if (unwind_mm) |
8a68d464 | 1935 | ppgtt->pd_dirty_engines |= unwind_mm; |
8911a31c CW |
1936 | err: |
1937 | return ret; | |
1938 | } | |
1939 | ||
e61e0f51 | 1940 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1941 | { |
fd138212 | 1942 | int ret; |
6310346e | 1943 | |
1fc44d9b | 1944 | GEM_BUG_ON(!request->hw_context->pin_count); |
85474441 | 1945 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1946 | |
5f5800a7 CW |
1947 | /* |
1948 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1949 | * we start building the request - in which case we will just |
1950 | * have to repeat work. | |
1951 | */ | |
a0442461 | 1952 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1953 | |
f2253bd9 | 1954 | ret = switch_context(request); |
fd138212 CW |
1955 | if (ret) |
1956 | return ret; | |
6310346e | 1957 | |
f2253bd9 CW |
1958 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1959 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
3fef5cda CW |
1960 | if (ret) |
1961 | return ret; | |
1962 | ||
a0442461 | 1963 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1964 | return 0; |
9d773091 CW |
1965 | } |
1966 | ||
fd138212 | 1967 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1968 | { |
e61e0f51 | 1969 | struct i915_request *target; |
e95433c7 CW |
1970 | long timeout; |
1971 | ||
fd138212 | 1972 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1973 | |
95aebcb2 | 1974 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1975 | return 0; |
1976 | ||
36620032 | 1977 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1978 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1979 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1980 | if (bytes <= __intel_ring_space(target->postfix, |
1981 | ring->emit, ring->size)) | |
987046ad | 1982 | break; |
79bbcc29 | 1983 | } |
29b1b415 | 1984 | |
675d9ad7 | 1985 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1986 | return -ENOSPC; |
1987 | ||
e61e0f51 | 1988 | timeout = i915_request_wait(target, |
e95433c7 CW |
1989 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
1990 | MAX_SCHEDULE_TIMEOUT); | |
1991 | if (timeout < 0) | |
1992 | return timeout; | |
7da844c5 | 1993 | |
e61e0f51 | 1994 | i915_request_retire_upto(target); |
7da844c5 CW |
1995 | |
1996 | intel_ring_update_space(ring); | |
1997 | GEM_BUG_ON(ring->space < bytes); | |
1998 | return 0; | |
29b1b415 JH |
1999 | } |
2000 | ||
e61e0f51 | 2001 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 2002 | { |
e61e0f51 | 2003 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
2004 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
2005 | const unsigned int bytes = num_dwords * sizeof(u32); | |
2006 | unsigned int need_wrap = 0; | |
2007 | unsigned int total_bytes; | |
73dec95e | 2008 | u32 *cs; |
29b1b415 | 2009 | |
6492ca79 CW |
2010 | /* Packets must be qword aligned. */ |
2011 | GEM_BUG_ON(num_dwords & 1); | |
2012 | ||
e61e0f51 | 2013 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 2014 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 2015 | |
5e5655c3 CW |
2016 | if (unlikely(total_bytes > remain_usable)) { |
2017 | const int remain_actual = ring->size - ring->emit; | |
2018 | ||
2019 | if (bytes > remain_usable) { | |
2020 | /* | |
2021 | * Not enough space for the basic request. So need to | |
2022 | * flush out the remainder and then wait for | |
2023 | * base + reserved. | |
2024 | */ | |
2025 | total_bytes += remain_actual; | |
2026 | need_wrap = remain_actual | 1; | |
2027 | } else { | |
2028 | /* | |
2029 | * The base request will fit but the reserved space | |
2030 | * falls off the end. So we don't need an immediate | |
2031 | * wrap and only need to effectively wait for the | |
2032 | * reserved size from the start of ringbuffer. | |
2033 | */ | |
e61e0f51 | 2034 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 2035 | } |
cbcc80df MK |
2036 | } |
2037 | ||
5e5655c3 | 2038 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
2039 | int ret; |
2040 | ||
2041 | /* | |
2042 | * Space is reserved in the ringbuffer for finalising the | |
2043 | * request, as that cannot be allowed to fail. During request | |
2044 | * finalisation, reserved_space is set to 0 to stop the | |
2045 | * overallocation and the assumption is that then we never need | |
2046 | * to wait (which has the risk of failing with EINTR). | |
2047 | * | |
e61e0f51 | 2048 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 2049 | */ |
e61e0f51 | 2050 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
2051 | |
2052 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 2053 | if (unlikely(ret)) |
73dec95e | 2054 | return ERR_PTR(ret); |
cbcc80df MK |
2055 | } |
2056 | ||
987046ad | 2057 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
2058 | need_wrap &= ~1; |
2059 | GEM_BUG_ON(need_wrap > ring->space); | |
2060 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 2061 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 2062 | |
987046ad | 2063 | /* Fill the tail with MI_NOOP */ |
46b86332 | 2064 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 2065 | ring->space -= need_wrap; |
46b86332 | 2066 | ring->emit = 0; |
987046ad | 2067 | } |
304d695c | 2068 | |
e6ba9992 | 2069 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 2070 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 2071 | cs = ring->vaddr + ring->emit; |
46b86332 | 2072 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 2073 | ring->emit += bytes; |
1dae2dfb | 2074 | ring->space -= bytes; |
73dec95e TU |
2075 | |
2076 | return cs; | |
8187a2b7 | 2077 | } |
78501eac | 2078 | |
753b1ad4 | 2079 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 2080 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 2081 | { |
1f177a13 CW |
2082 | int num_dwords; |
2083 | void *cs; | |
753b1ad4 | 2084 | |
1f177a13 | 2085 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
2086 | if (num_dwords == 0) |
2087 | return 0; | |
2088 | ||
1f177a13 CW |
2089 | num_dwords = CACHELINE_DWORDS - num_dwords; |
2090 | GEM_BUG_ON(num_dwords & 1); | |
2091 | ||
e61e0f51 | 2092 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
2093 | if (IS_ERR(cs)) |
2094 | return PTR_ERR(cs); | |
753b1ad4 | 2095 | |
1f177a13 | 2096 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 2097 | intel_ring_advance(rq, cs); |
753b1ad4 | 2098 | |
1f177a13 | 2099 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
2100 | return 0; |
2101 | } | |
2102 | ||
e61e0f51 | 2103 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 2104 | { |
c5efa1ad | 2105 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2106 | |
76f8421f CW |
2107 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2108 | ||
881f47b6 | 2109 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2110 | |
2111 | /* Disable notification that the ring is IDLE. The GT | |
2112 | * will then assume that it is busy and bring it out of rc6. | |
2113 | */ | |
76f8421f CW |
2114 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2115 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2116 | |
2117 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2118 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2119 | |
12f55818 | 2120 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
2121 | if (__intel_wait_for_register_fw(dev_priv, |
2122 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2123 | GEN6_BSD_SLEEP_INDICATOR, | |
2124 | 0, | |
2125 | 1000, 0, NULL)) | |
12f55818 | 2126 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2127 | |
12f55818 | 2128 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2129 | i9xx_submit_request(request); |
12f55818 CW |
2130 | |
2131 | /* Let the ring send IDLE messages to the GT again, | |
2132 | * and so let it sleep to conserve power when idle. | |
2133 | */ | |
76f8421f CW |
2134 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2135 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2136 | ||
2137 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2138 | } |
2139 | ||
06348d30 | 2140 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 2141 | { |
73dec95e | 2142 | u32 cmd, *cs; |
b72f3acb | 2143 | |
e61e0f51 | 2144 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
2145 | if (IS_ERR(cs)) |
2146 | return PTR_ERR(cs); | |
b72f3acb | 2147 | |
71a77e07 | 2148 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 2149 | |
70b73f9a CW |
2150 | /* |
2151 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2152 | * commands, such as breadcrumb interrupts, are strictly ordered |
2153 | * wrt the contents of the write cache being flushed to memory | |
2154 | * (and thus being coherent from the CPU). | |
2155 | */ | |
2156 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2157 | ||
9a289771 | 2158 | /* |
70b73f9a | 2159 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2160 | * "If ENABLED, all TLBs will be invalidated once the flush |
2161 | * operation is complete. This bit is only valid when the | |
2162 | * Post-Sync Operation field is a value of 1h or 3h." | |
2163 | */ | |
70b73f9a | 2164 | cmd |= flags; |
f0a1fb10 | 2165 | |
73dec95e TU |
2166 | *cs++ = cmd; |
2167 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2168 | *cs++ = 0; |
73dec95e | 2169 | *cs++ = MI_NOOP; |
70b73f9a | 2170 | |
e61e0f51 | 2171 | intel_ring_advance(rq, cs); |
70b73f9a | 2172 | |
1c7a0623 BW |
2173 | return 0; |
2174 | } | |
2175 | ||
70b73f9a CW |
2176 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2177 | { | |
06348d30 | 2178 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2179 | } |
2180 | ||
2181 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2182 | { | |
2183 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2184 | } | |
2185 | ||
d7d4eedd | 2186 | static int |
e61e0f51 | 2187 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2188 | u64 offset, u32 len, |
2189 | unsigned int dispatch_flags) | |
d7d4eedd | 2190 | { |
73dec95e | 2191 | u32 *cs; |
d7d4eedd | 2192 | |
e61e0f51 | 2193 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2194 | if (IS_ERR(cs)) |
2195 | return PTR_ERR(cs); | |
d7d4eedd | 2196 | |
73dec95e | 2197 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2198 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2199 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2200 | *cs++ = offset; |
e61e0f51 | 2201 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2202 | |
2203 | return 0; | |
2204 | } | |
2205 | ||
881f47b6 | 2206 | static int |
e61e0f51 | 2207 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2208 | u64 offset, u32 len, |
2209 | unsigned int dispatch_flags) | |
881f47b6 | 2210 | { |
73dec95e | 2211 | u32 *cs; |
ab6f8e32 | 2212 | |
e61e0f51 | 2213 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2214 | if (IS_ERR(cs)) |
2215 | return PTR_ERR(cs); | |
e1f99ce6 | 2216 | |
73dec95e TU |
2217 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2218 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2219 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2220 | *cs++ = offset; |
e61e0f51 | 2221 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2222 | |
0206e353 | 2223 | return 0; |
881f47b6 XH |
2224 | } |
2225 | ||
549f7365 CW |
2226 | /* Blitter support (SandyBridge+) */ |
2227 | ||
e61e0f51 | 2228 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2229 | { |
70b73f9a | 2230 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2231 | } |
2232 | ||
ed003078 CW |
2233 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2234 | struct intel_engine_cs *engine) | |
2235 | { | |
79e6770c | 2236 | if (INTEL_GEN(dev_priv) >= 6) { |
31bb59cc CW |
2237 | engine->irq_enable = gen6_irq_enable; |
2238 | engine->irq_disable = gen6_irq_disable; | |
ed003078 | 2239 | } else if (INTEL_GEN(dev_priv) >= 5) { |
31bb59cc CW |
2240 | engine->irq_enable = gen5_irq_enable; |
2241 | engine->irq_disable = gen5_irq_disable; | |
ed003078 | 2242 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2243 | engine->irq_enable = i9xx_irq_enable; |
2244 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2245 | } else { |
31bb59cc CW |
2246 | engine->irq_enable = i8xx_irq_enable; |
2247 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2248 | } |
2249 | } | |
2250 | ||
ff44ad51 CW |
2251 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2252 | { | |
2253 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2254 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2255 | |
2256 | engine->park = NULL; | |
2257 | engine->unpark = NULL; | |
ff44ad51 CW |
2258 | } |
2259 | ||
2260 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2261 | { | |
aba5e278 | 2262 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2263 | engine->submit_request = gen6_bsd_submit_request; |
2264 | } | |
2265 | ||
06a2fe22 TU |
2266 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2267 | struct intel_engine_cs *engine) | |
2268 | { | |
79e6770c CW |
2269 | /* gen8+ are only supported with execlists */ |
2270 | GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); | |
2271 | ||
618e4ca7 | 2272 | intel_ring_init_irq(dev_priv, engine); |
618e4ca7 | 2273 | |
1d8a1337 | 2274 | engine->init_hw = init_ring_common; |
5adfb772 CW |
2275 | engine->reset.prepare = reset_prepare; |
2276 | engine->reset.reset = reset_ring; | |
2277 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2278 | |
e8a9c58f | 2279 | engine->context_pin = intel_ring_context_pin; |
f73e7399 CW |
2280 | engine->request_alloc = ring_request_alloc; |
2281 | ||
85474441 CW |
2282 | /* |
2283 | * Using a global execution timeline; the previous final breadcrumb is | |
2284 | * equivalent to our next initial bread so we can elide | |
2285 | * engine->emit_init_breadcrumb(). | |
2286 | */ | |
2287 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
9fa4973e | 2288 | if (IS_GEN(dev_priv, 5)) |
85474441 | 2289 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2290 | |
2291 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2292 | |
79e6770c | 2293 | if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2294 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2295 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2296 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2297 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2298 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2299 | else |
803688ba | 2300 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2301 | } |
2302 | ||
8b3e2d36 | 2303 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2304 | { |
8b3e2d36 | 2305 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2306 | int ret; |
5c1143bb | 2307 | |
06a2fe22 TU |
2308 | intel_ring_default_vfuncs(dev_priv, engine); |
2309 | ||
61ff75ac CW |
2310 | if (HAS_L3_DPF(dev_priv)) |
2311 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2312 | |
fa6f071d DCS |
2313 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2314 | ||
caa5915b | 2315 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 2316 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2317 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2318 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
caa5915b CW |
2319 | } else if (IS_GEN(dev_priv, 6)) { |
2320 | engine->init_context = intel_rcs_ctx_init; | |
2321 | engine->emit_flush = gen6_render_ring_flush; | |
85474441 | 2322 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
cf819eff | 2323 | } else if (IS_GEN(dev_priv, 5)) { |
c7fe7d25 | 2324 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2325 | } else { |
c033666a | 2326 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2327 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2328 | else |
c7fe7d25 | 2329 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2330 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2331 | } |
707d9cf9 | 2332 | |
c033666a | 2333 | if (IS_HASWELL(dev_priv)) |
803688ba | 2334 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2335 | |
e2f80391 | 2336 | engine->init_hw = init_render_ring; |
59465b5f | 2337 | |
acd27845 | 2338 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2339 | if (ret) |
2340 | return ret; | |
2341 | ||
99be1dfe | 2342 | return 0; |
5c1143bb XH |
2343 | } |
2344 | ||
8b3e2d36 | 2345 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2346 | { |
8b3e2d36 | 2347 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2348 | |
06a2fe22 TU |
2349 | intel_ring_default_vfuncs(dev_priv, engine); |
2350 | ||
c033666a | 2351 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2352 | /* gen6 bsd needs a special wa for tail updates */ |
cf819eff | 2353 | if (IS_GEN(dev_priv, 6)) |
ff44ad51 | 2354 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2355 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2356 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2357 | |
9fa4973e | 2358 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2359 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2360 | else |
85474441 | 2361 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2362 | } else { |
c7fe7d25 | 2363 | engine->emit_flush = bsd_ring_flush; |
cf819eff | 2364 | if (IS_GEN(dev_priv, 5)) |
e2f80391 | 2365 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2366 | else |
e2f80391 | 2367 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2368 | } |
58fa3835 | 2369 | |
acd27845 | 2370 | return intel_init_ring_buffer(engine); |
5c1143bb | 2371 | } |
549f7365 | 2372 | |
8b3e2d36 | 2373 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2374 | { |
8b3e2d36 | 2375 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2376 | |
caa5915b CW |
2377 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); |
2378 | ||
06a2fe22 TU |
2379 | intel_ring_default_vfuncs(dev_priv, engine); |
2380 | ||
c7fe7d25 | 2381 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2382 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2383 | |
9fa4973e | 2384 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2385 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2386 | else |
85474441 | 2387 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2388 | |
acd27845 | 2389 | return intel_init_ring_buffer(engine); |
549f7365 | 2390 | } |
a7b9761d | 2391 | |
8b3e2d36 | 2392 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2393 | { |
8b3e2d36 | 2394 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2395 | |
caa5915b CW |
2396 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 7); |
2397 | ||
06a2fe22 TU |
2398 | intel_ring_default_vfuncs(dev_priv, engine); |
2399 | ||
c7fe7d25 | 2400 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2401 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2402 | engine->irq_enable = hsw_vebox_irq_enable; | |
2403 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2404 | |
85474441 | 2405 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2406 | |
acd27845 | 2407 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2408 | } |