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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
82e104cc | 37 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 38 | { |
4f54741e DG |
39 | int space = head - tail; |
40 | if (space <= 0) | |
1cf0ba14 | 41 | space += size; |
4f54741e | 42 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
43 | } |
44 | ||
ebd0fd4b DG |
45 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
46 | { | |
47 | if (ringbuf->last_retired_head != -1) { | |
48 | ringbuf->head = ringbuf->last_retired_head; | |
49 | ringbuf->last_retired_head = -1; | |
50 | } | |
51 | ||
52 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
53 | ringbuf->tail, ringbuf->size); | |
54 | } | |
55 | ||
117897f4 | 56 | bool intel_engine_stopped(struct intel_engine_cs *engine) |
09246732 | 57 | { |
0bc40be8 | 58 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
666796da | 59 | return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine); |
88b4aa87 | 60 | } |
09246732 | 61 | |
0bc40be8 | 62 | static void __intel_ring_advance(struct intel_engine_cs *engine) |
88b4aa87 | 63 | { |
0bc40be8 | 64 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 65 | ringbuf->tail &= ringbuf->size - 1; |
117897f4 | 66 | if (intel_engine_stopped(engine)) |
09246732 | 67 | return; |
0bc40be8 | 68 | engine->write_tail(engine, ringbuf->tail); |
09246732 CW |
69 | } |
70 | ||
b72f3acb | 71 | static int |
a84c3ae1 | 72 | gen2_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
73 | u32 invalidate_domains, |
74 | u32 flush_domains) | |
75 | { | |
4a570db5 | 76 | struct intel_engine_cs *engine = req->engine; |
46f0f8d1 CW |
77 | u32 cmd; |
78 | int ret; | |
79 | ||
80 | cmd = MI_FLUSH; | |
31b14c9f | 81 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
82 | cmd |= MI_NO_WRITE_FLUSH; |
83 | ||
84 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
85 | cmd |= MI_READ_FLUSH; | |
86 | ||
5fb9de1a | 87 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
88 | if (ret) |
89 | return ret; | |
90 | ||
e2f80391 TU |
91 | intel_ring_emit(engine, cmd); |
92 | intel_ring_emit(engine, MI_NOOP); | |
93 | intel_ring_advance(engine); | |
46f0f8d1 CW |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
98 | static int | |
a84c3ae1 | 99 | gen4_render_ring_flush(struct drm_i915_gem_request *req, |
46f0f8d1 CW |
100 | u32 invalidate_domains, |
101 | u32 flush_domains) | |
62fdfeaf | 102 | { |
4a570db5 | 103 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 104 | struct drm_device *dev = engine->dev; |
6f392d54 | 105 | u32 cmd; |
b72f3acb | 106 | int ret; |
6f392d54 | 107 | |
36d527de CW |
108 | /* |
109 | * read/write caches: | |
110 | * | |
111 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
112 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
113 | * also flushed at 2d versus 3d pipeline switches. | |
114 | * | |
115 | * read-only caches: | |
116 | * | |
117 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
118 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
119 | * | |
120 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
121 | * | |
122 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
123 | * invalidated when MI_EXE_FLUSH is set. | |
124 | * | |
125 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
126 | * invalidated with every MI_FLUSH. | |
127 | * | |
128 | * TLBs: | |
129 | * | |
130 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
131 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
132 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
133 | * are flushed at any MI_FLUSH. | |
134 | */ | |
135 | ||
136 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 137 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 138 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
139 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
140 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 141 | |
36d527de CW |
142 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
143 | (IS_G4X(dev) || IS_GEN5(dev))) | |
144 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 145 | |
5fb9de1a | 146 | ret = intel_ring_begin(req, 2); |
36d527de CW |
147 | if (ret) |
148 | return ret; | |
b72f3acb | 149 | |
e2f80391 TU |
150 | intel_ring_emit(engine, cmd); |
151 | intel_ring_emit(engine, MI_NOOP); | |
152 | intel_ring_advance(engine); | |
b72f3acb CW |
153 | |
154 | return 0; | |
8187a2b7 ZN |
155 | } |
156 | ||
8d315287 JB |
157 | /** |
158 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
159 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
160 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
161 | * | |
162 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
163 | * produced by non-pipelined state commands), software needs to first | |
164 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
165 | * 0. | |
166 | * | |
167 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
168 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
169 | * | |
170 | * And the workaround for these two requires this workaround first: | |
171 | * | |
172 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
173 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
174 | * flushes. | |
175 | * | |
176 | * And this last workaround is tricky because of the requirements on | |
177 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
178 | * volume 2 part 1: | |
179 | * | |
180 | * "1 of the following must also be set: | |
181 | * - Render Target Cache Flush Enable ([12] of DW1) | |
182 | * - Depth Cache Flush Enable ([0] of DW1) | |
183 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
184 | * - Depth Stall ([13] of DW1) | |
185 | * - Post-Sync Operation ([13] of DW1) | |
186 | * - Notify Enable ([8] of DW1)" | |
187 | * | |
188 | * The cache flushes require the workaround flush that triggered this | |
189 | * one, so we can't use it. Depth stall would trigger the same. | |
190 | * Post-sync nonzero is what triggered this second workaround, so we | |
191 | * can't use that one either. Notify enable is IRQs, which aren't | |
192 | * really our business. That leaves only stall at scoreboard. | |
193 | */ | |
194 | static int | |
f2cf1fcc | 195 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 196 | { |
4a570db5 | 197 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 198 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
199 | int ret; |
200 | ||
5fb9de1a | 201 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
202 | if (ret) |
203 | return ret; | |
204 | ||
e2f80391 TU |
205 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
206 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
8d315287 | 207 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
208 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
209 | intel_ring_emit(engine, 0); /* low dword */ | |
210 | intel_ring_emit(engine, 0); /* high dword */ | |
211 | intel_ring_emit(engine, MI_NOOP); | |
212 | intel_ring_advance(engine); | |
8d315287 | 213 | |
5fb9de1a | 214 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
215 | if (ret) |
216 | return ret; | |
217 | ||
e2f80391 TU |
218 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5)); |
219 | intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE); | |
220 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
221 | intel_ring_emit(engine, 0); | |
222 | intel_ring_emit(engine, 0); | |
223 | intel_ring_emit(engine, MI_NOOP); | |
224 | intel_ring_advance(engine); | |
8d315287 JB |
225 | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static int | |
a84c3ae1 JH |
230 | gen6_render_ring_flush(struct drm_i915_gem_request *req, |
231 | u32 invalidate_domains, u32 flush_domains) | |
8d315287 | 232 | { |
4a570db5 | 233 | struct intel_engine_cs *engine = req->engine; |
8d315287 | 234 | u32 flags = 0; |
e2f80391 | 235 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
236 | int ret; |
237 | ||
b3111509 | 238 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 239 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
240 | if (ret) |
241 | return ret; | |
242 | ||
8d315287 JB |
243 | /* Just flush everything. Experiments have shown that reducing the |
244 | * number of bits based on the write domains has little performance | |
245 | * impact. | |
246 | */ | |
7d54a904 CW |
247 | if (flush_domains) { |
248 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
249 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
250 | /* | |
251 | * Ensure that any following seqno writes only happen | |
252 | * when the render cache is indeed flushed. | |
253 | */ | |
97f209bc | 254 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
255 | } |
256 | if (invalidate_domains) { | |
257 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
259 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
260 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
261 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
262 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
263 | /* | |
264 | * TLB invalidate requires a post-sync write. | |
265 | */ | |
3ac78313 | 266 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 267 | } |
8d315287 | 268 | |
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
270 | if (ret) |
271 | return ret; | |
272 | ||
e2f80391 TU |
273 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(engine, flags); | |
275 | intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
276 | intel_ring_emit(engine, 0); | |
277 | intel_ring_advance(engine); | |
8d315287 JB |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
f3987631 | 282 | static int |
f2cf1fcc | 283 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 284 | { |
4a570db5 | 285 | struct intel_engine_cs *engine = req->engine; |
f3987631 PZ |
286 | int ret; |
287 | ||
5fb9de1a | 288 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
289 | if (ret) |
290 | return ret; | |
291 | ||
e2f80391 TU |
292 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
293 | intel_ring_emit(engine, PIPE_CONTROL_CS_STALL | | |
f3987631 | 294 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
e2f80391 TU |
295 | intel_ring_emit(engine, 0); |
296 | intel_ring_emit(engine, 0); | |
297 | intel_ring_advance(engine); | |
f3987631 PZ |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
4772eaeb | 302 | static int |
a84c3ae1 | 303 | gen7_render_ring_flush(struct drm_i915_gem_request *req, |
4772eaeb PZ |
304 | u32 invalidate_domains, u32 flush_domains) |
305 | { | |
4a570db5 | 306 | struct intel_engine_cs *engine = req->engine; |
4772eaeb | 307 | u32 flags = 0; |
e2f80391 | 308 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
309 | int ret; |
310 | ||
f3987631 PZ |
311 | /* |
312 | * Ensure that any following seqno writes only happen when the render | |
313 | * cache is indeed flushed. | |
314 | * | |
315 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
316 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
317 | * don't try to be clever and just set it unconditionally. | |
318 | */ | |
319 | flags |= PIPE_CONTROL_CS_STALL; | |
320 | ||
4772eaeb PZ |
321 | /* Just flush everything. Experiments have shown that reducing the |
322 | * number of bits based on the write domains has little performance | |
323 | * impact. | |
324 | */ | |
325 | if (flush_domains) { | |
326 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
327 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 328 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 329 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb PZ |
330 | } |
331 | if (invalidate_domains) { | |
332 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
335 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
336 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
337 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 338 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
339 | /* |
340 | * TLB invalidate requires a post-sync write. | |
341 | */ | |
342 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 343 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 344 | |
add284a3 CW |
345 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
346 | ||
f3987631 PZ |
347 | /* Workaround: we must issue a pipe_control with CS-stall bit |
348 | * set before a pipe_control command that has the state cache | |
349 | * invalidate bit set. */ | |
f2cf1fcc | 350 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
351 | } |
352 | ||
5fb9de1a | 353 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
354 | if (ret) |
355 | return ret; | |
356 | ||
e2f80391 TU |
357 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4)); |
358 | intel_ring_emit(engine, flags); | |
359 | intel_ring_emit(engine, scratch_addr); | |
360 | intel_ring_emit(engine, 0); | |
361 | intel_ring_advance(engine); | |
4772eaeb PZ |
362 | |
363 | return 0; | |
364 | } | |
365 | ||
884ceace | 366 | static int |
f2cf1fcc | 367 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
368 | u32 flags, u32 scratch_addr) |
369 | { | |
4a570db5 | 370 | struct intel_engine_cs *engine = req->engine; |
884ceace KG |
371 | int ret; |
372 | ||
5fb9de1a | 373 | ret = intel_ring_begin(req, 6); |
884ceace KG |
374 | if (ret) |
375 | return ret; | |
376 | ||
e2f80391 TU |
377 | intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6)); |
378 | intel_ring_emit(engine, flags); | |
379 | intel_ring_emit(engine, scratch_addr); | |
380 | intel_ring_emit(engine, 0); | |
381 | intel_ring_emit(engine, 0); | |
382 | intel_ring_emit(engine, 0); | |
383 | intel_ring_advance(engine); | |
884ceace KG |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
a5f3d68e | 388 | static int |
a84c3ae1 | 389 | gen8_render_ring_flush(struct drm_i915_gem_request *req, |
a5f3d68e BW |
390 | u32 invalidate_domains, u32 flush_domains) |
391 | { | |
392 | u32 flags = 0; | |
4a570db5 | 393 | u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 394 | int ret; |
a5f3d68e BW |
395 | |
396 | flags |= PIPE_CONTROL_CS_STALL; | |
397 | ||
398 | if (flush_domains) { | |
399 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
400 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 401 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 402 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e BW |
403 | } |
404 | if (invalidate_domains) { | |
405 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
406 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
407 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
408 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
409 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
410 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
411 | flags |= PIPE_CONTROL_QW_WRITE; | |
412 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
413 | |
414 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 415 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
416 | PIPE_CONTROL_CS_STALL | |
417 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
418 | 0); | |
419 | if (ret) | |
420 | return ret; | |
a5f3d68e BW |
421 | } |
422 | ||
f2cf1fcc | 423 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
424 | } |
425 | ||
0bc40be8 | 426 | static void ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 427 | u32 value) |
d46eefa2 | 428 | { |
0bc40be8 TU |
429 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
430 | I915_WRITE_TAIL(engine, value); | |
d46eefa2 XH |
431 | } |
432 | ||
0bc40be8 | 433 | u64 intel_ring_get_active_head(struct intel_engine_cs *engine) |
8187a2b7 | 434 | { |
0bc40be8 | 435 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
50877445 | 436 | u64 acthd; |
8187a2b7 | 437 | |
0bc40be8 TU |
438 | if (INTEL_INFO(engine->dev)->gen >= 8) |
439 | acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), | |
440 | RING_ACTHD_UDW(engine->mmio_base)); | |
441 | else if (INTEL_INFO(engine->dev)->gen >= 4) | |
442 | acthd = I915_READ(RING_ACTHD(engine->mmio_base)); | |
50877445 CW |
443 | else |
444 | acthd = I915_READ(ACTHD); | |
445 | ||
446 | return acthd; | |
8187a2b7 ZN |
447 | } |
448 | ||
0bc40be8 | 449 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 450 | { |
0bc40be8 | 451 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
035dc1e0 DV |
452 | u32 addr; |
453 | ||
454 | addr = dev_priv->status_page_dmah->busaddr; | |
0bc40be8 | 455 | if (INTEL_INFO(engine->dev)->gen >= 4) |
035dc1e0 DV |
456 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
457 | I915_WRITE(HWS_PGA, addr); | |
458 | } | |
459 | ||
0bc40be8 | 460 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 461 | { |
0bc40be8 TU |
462 | struct drm_device *dev = engine->dev; |
463 | struct drm_i915_private *dev_priv = engine->dev->dev_private; | |
f0f59a00 | 464 | i915_reg_t mmio; |
af75f269 DL |
465 | |
466 | /* The ring status page addresses are no longer next to the rest of | |
467 | * the ring registers as of gen7. | |
468 | */ | |
469 | if (IS_GEN7(dev)) { | |
0bc40be8 | 470 | switch (engine->id) { |
af75f269 DL |
471 | case RCS: |
472 | mmio = RENDER_HWS_PGA_GEN7; | |
473 | break; | |
474 | case BCS: | |
475 | mmio = BLT_HWS_PGA_GEN7; | |
476 | break; | |
477 | /* | |
478 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
479 | * gcc switch check warning | |
480 | */ | |
481 | case VCS2: | |
482 | case VCS: | |
483 | mmio = BSD_HWS_PGA_GEN7; | |
484 | break; | |
485 | case VECS: | |
486 | mmio = VEBOX_HWS_PGA_GEN7; | |
487 | break; | |
488 | } | |
0bc40be8 TU |
489 | } else if (IS_GEN6(engine->dev)) { |
490 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); | |
af75f269 DL |
491 | } else { |
492 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 493 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
494 | } |
495 | ||
0bc40be8 | 496 | I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); |
af75f269 DL |
497 | POSTING_READ(mmio); |
498 | ||
499 | /* | |
500 | * Flush the TLB for this page | |
501 | * | |
502 | * FIXME: These two bits have disappeared on gen8, so a question | |
503 | * arises: do we still need this and if so how should we go about | |
504 | * invalidating the TLB? | |
505 | */ | |
506 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
0bc40be8 | 507 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
508 | |
509 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 510 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
511 | |
512 | I915_WRITE(reg, | |
513 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
514 | INSTPM_SYNC_FLUSH)); | |
515 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
516 | 1000)) | |
517 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
0bc40be8 | 518 | engine->name); |
af75f269 DL |
519 | } |
520 | } | |
521 | ||
0bc40be8 | 522 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 523 | { |
0bc40be8 | 524 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
8187a2b7 | 525 | |
0bc40be8 TU |
526 | if (!IS_GEN2(engine->dev)) { |
527 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); | |
528 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
529 | DRM_ERROR("%s : timed out trying to stop ring\n", | |
530 | engine->name); | |
9bec9b13 CW |
531 | /* Sometimes we observe that the idle flag is not |
532 | * set even though the ring is empty. So double | |
533 | * check before giving up. | |
534 | */ | |
0bc40be8 | 535 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 536 | return false; |
9991ae78 CW |
537 | } |
538 | } | |
b7884eb4 | 539 | |
0bc40be8 TU |
540 | I915_WRITE_CTL(engine, 0); |
541 | I915_WRITE_HEAD(engine, 0); | |
542 | engine->write_tail(engine, 0); | |
8187a2b7 | 543 | |
0bc40be8 TU |
544 | if (!IS_GEN2(engine->dev)) { |
545 | (void)I915_READ_CTL(engine); | |
546 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 547 | } |
a51435a3 | 548 | |
0bc40be8 | 549 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 550 | } |
8187a2b7 | 551 | |
fc0768ce TE |
552 | void intel_engine_init_hangcheck(struct intel_engine_cs *engine) |
553 | { | |
554 | memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); | |
555 | } | |
556 | ||
0bc40be8 | 557 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 558 | { |
0bc40be8 | 559 | struct drm_device *dev = engine->dev; |
9991ae78 | 560 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 561 | struct intel_ringbuffer *ringbuf = engine->buffer; |
93b0a4e0 | 562 | struct drm_i915_gem_object *obj = ringbuf->obj; |
9991ae78 CW |
563 | int ret = 0; |
564 | ||
59bad947 | 565 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 566 | |
0bc40be8 | 567 | if (!stop_ring(engine)) { |
9991ae78 | 568 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
569 | DRM_DEBUG_KMS("%s head not reset to zero " |
570 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
571 | engine->name, |
572 | I915_READ_CTL(engine), | |
573 | I915_READ_HEAD(engine), | |
574 | I915_READ_TAIL(engine), | |
575 | I915_READ_START(engine)); | |
8187a2b7 | 576 | |
0bc40be8 | 577 | if (!stop_ring(engine)) { |
6fd0d56e CW |
578 | DRM_ERROR("failed to set %s head to zero " |
579 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
580 | engine->name, |
581 | I915_READ_CTL(engine), | |
582 | I915_READ_HEAD(engine), | |
583 | I915_READ_TAIL(engine), | |
584 | I915_READ_START(engine)); | |
9991ae78 CW |
585 | ret = -EIO; |
586 | goto out; | |
6fd0d56e | 587 | } |
8187a2b7 ZN |
588 | } |
589 | ||
9991ae78 | 590 | if (I915_NEED_GFX_HWS(dev)) |
0bc40be8 | 591 | intel_ring_setup_status_page(engine); |
9991ae78 | 592 | else |
0bc40be8 | 593 | ring_setup_phys_status_page(engine); |
9991ae78 | 594 | |
ece4a17d | 595 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 596 | I915_READ_HEAD(engine); |
ece4a17d | 597 | |
0d8957c8 DV |
598 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
599 | * registers with the above sequence (the readback of the HEAD registers | |
600 | * also enforces ordering), otherwise the hw might lose the new ring | |
601 | * register values. */ | |
0bc40be8 | 602 | I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
603 | |
604 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 605 | if (I915_READ_HEAD(engine)) |
95468892 | 606 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 TU |
607 | engine->name, I915_READ_HEAD(engine)); |
608 | I915_WRITE_HEAD(engine, 0); | |
609 | (void)I915_READ_HEAD(engine); | |
95468892 | 610 | |
0bc40be8 | 611 | I915_WRITE_CTL(engine, |
93b0a4e0 | 612 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 613 | | RING_VALID); |
8187a2b7 | 614 | |
8187a2b7 | 615 | /* If the head is still not zero, the ring is dead */ |
0bc40be8 TU |
616 | if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && |
617 | I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && | |
618 | (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 | 619 | DRM_ERROR("%s initialization failed " |
48e48a0b | 620 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
0bc40be8 TU |
621 | engine->name, |
622 | I915_READ_CTL(engine), | |
623 | I915_READ_CTL(engine) & RING_VALID, | |
624 | I915_READ_HEAD(engine), I915_READ_TAIL(engine), | |
625 | I915_READ_START(engine), | |
626 | (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
627 | ret = -EIO; |
628 | goto out; | |
8187a2b7 ZN |
629 | } |
630 | ||
ebd0fd4b | 631 | ringbuf->last_retired_head = -1; |
0bc40be8 TU |
632 | ringbuf->head = I915_READ_HEAD(engine); |
633 | ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; | |
ebd0fd4b | 634 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 635 | |
fc0768ce | 636 | intel_engine_init_hangcheck(engine); |
50f018df | 637 | |
b7884eb4 | 638 | out: |
59bad947 | 639 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
640 | |
641 | return ret; | |
8187a2b7 ZN |
642 | } |
643 | ||
9b1136d5 | 644 | void |
0bc40be8 | 645 | intel_fini_pipe_control(struct intel_engine_cs *engine) |
9b1136d5 | 646 | { |
0bc40be8 | 647 | struct drm_device *dev = engine->dev; |
9b1136d5 | 648 | |
0bc40be8 | 649 | if (engine->scratch.obj == NULL) |
9b1136d5 OM |
650 | return; |
651 | ||
652 | if (INTEL_INFO(dev)->gen >= 5) { | |
0bc40be8 TU |
653 | kunmap(sg_page(engine->scratch.obj->pages->sgl)); |
654 | i915_gem_object_ggtt_unpin(engine->scratch.obj); | |
9b1136d5 OM |
655 | } |
656 | ||
0bc40be8 TU |
657 | drm_gem_object_unreference(&engine->scratch.obj->base); |
658 | engine->scratch.obj = NULL; | |
9b1136d5 OM |
659 | } |
660 | ||
661 | int | |
0bc40be8 | 662 | intel_init_pipe_control(struct intel_engine_cs *engine) |
c6df541c | 663 | { |
c6df541c CW |
664 | int ret; |
665 | ||
0bc40be8 | 666 | WARN_ON(engine->scratch.obj); |
c6df541c | 667 | |
0bc40be8 TU |
668 | engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096); |
669 | if (engine->scratch.obj == NULL) { | |
c6df541c CW |
670 | DRM_ERROR("Failed to allocate seqno page\n"); |
671 | ret = -ENOMEM; | |
672 | goto err; | |
673 | } | |
e4ffd173 | 674 | |
0bc40be8 TU |
675 | ret = i915_gem_object_set_cache_level(engine->scratch.obj, |
676 | I915_CACHE_LLC); | |
a9cc726c DV |
677 | if (ret) |
678 | goto err_unref; | |
c6df541c | 679 | |
0bc40be8 | 680 | ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0); |
c6df541c CW |
681 | if (ret) |
682 | goto err_unref; | |
683 | ||
0bc40be8 TU |
684 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj); |
685 | engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl)); | |
686 | if (engine->scratch.cpu_page == NULL) { | |
56b085a0 | 687 | ret = -ENOMEM; |
c6df541c | 688 | goto err_unpin; |
56b085a0 | 689 | } |
c6df541c | 690 | |
2b1086cc | 691 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0bc40be8 | 692 | engine->name, engine->scratch.gtt_offset); |
c6df541c CW |
693 | return 0; |
694 | ||
695 | err_unpin: | |
0bc40be8 | 696 | i915_gem_object_ggtt_unpin(engine->scratch.obj); |
c6df541c | 697 | err_unref: |
0bc40be8 | 698 | drm_gem_object_unreference(&engine->scratch.obj->base); |
c6df541c | 699 | err: |
c6df541c CW |
700 | return ret; |
701 | } | |
702 | ||
e2be4faf | 703 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 704 | { |
7225342a | 705 | int ret, i; |
4a570db5 | 706 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 707 | struct drm_device *dev = engine->dev; |
888b5995 | 708 | struct drm_i915_private *dev_priv = dev->dev_private; |
7225342a | 709 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 710 | |
02235808 | 711 | if (w->count == 0) |
7225342a | 712 | return 0; |
888b5995 | 713 | |
e2f80391 | 714 | engine->gpu_caches_dirty = true; |
4866d729 | 715 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
716 | if (ret) |
717 | return ret; | |
888b5995 | 718 | |
5fb9de1a | 719 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
720 | if (ret) |
721 | return ret; | |
722 | ||
e2f80391 | 723 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 724 | for (i = 0; i < w->count; i++) { |
e2f80391 TU |
725 | intel_ring_emit_reg(engine, w->reg[i].addr); |
726 | intel_ring_emit(engine, w->reg[i].value); | |
7225342a | 727 | } |
e2f80391 | 728 | intel_ring_emit(engine, MI_NOOP); |
7225342a | 729 | |
e2f80391 | 730 | intel_ring_advance(engine); |
7225342a | 731 | |
e2f80391 | 732 | engine->gpu_caches_dirty = true; |
4866d729 | 733 | ret = intel_ring_flush_all_caches(req); |
7225342a MK |
734 | if (ret) |
735 | return ret; | |
888b5995 | 736 | |
7225342a | 737 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 738 | |
7225342a | 739 | return 0; |
86d7f238 AS |
740 | } |
741 | ||
8753181e | 742 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
743 | { |
744 | int ret; | |
745 | ||
e2be4faf | 746 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
747 | if (ret != 0) |
748 | return ret; | |
749 | ||
be01363f | 750 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 751 | if (ret) |
e26e1b97 | 752 | return ret; |
8f0e2b9d | 753 | |
e26e1b97 | 754 | return 0; |
8f0e2b9d DV |
755 | } |
756 | ||
7225342a | 757 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
758 | i915_reg_t addr, |
759 | const u32 mask, const u32 val) | |
7225342a MK |
760 | { |
761 | const u32 idx = dev_priv->workarounds.count; | |
762 | ||
763 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
764 | return -ENOSPC; | |
765 | ||
766 | dev_priv->workarounds.reg[idx].addr = addr; | |
767 | dev_priv->workarounds.reg[idx].value = val; | |
768 | dev_priv->workarounds.reg[idx].mask = mask; | |
769 | ||
770 | dev_priv->workarounds.count++; | |
771 | ||
772 | return 0; | |
86d7f238 AS |
773 | } |
774 | ||
ca5a0fbd | 775 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 776 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
777 | if (r) \ |
778 | return r; \ | |
ca5a0fbd | 779 | } while (0) |
7225342a MK |
780 | |
781 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 782 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
783 | |
784 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 785 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 786 | |
98533251 | 787 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 788 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 789 | |
cf4b0de6 DL |
790 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
791 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 792 | |
cf4b0de6 | 793 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 794 | |
0bc40be8 TU |
795 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
796 | i915_reg_t reg) | |
33136b06 | 797 | { |
0bc40be8 | 798 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
33136b06 | 799 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 800 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
801 | |
802 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
803 | return -EINVAL; | |
804 | ||
0bc40be8 | 805 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 806 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 807 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
0bc40be8 | 812 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 813 | { |
0bc40be8 | 814 | struct drm_device *dev = engine->dev; |
68c6198b AS |
815 | struct drm_i915_private *dev_priv = dev->dev_private; |
816 | ||
817 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 818 | |
717d84d6 AS |
819 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
820 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
821 | ||
d0581194 AS |
822 | /* WaDisablePartialInstShootdown:bdw,chv */ |
823 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
824 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
825 | ||
a340af58 AS |
826 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
827 | * workaround for for a possible hang in the unlikely event a TLB | |
828 | * invalidation occurs during a PSD flush. | |
829 | */ | |
830 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 831 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 832 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 833 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
834 | HDC_FORCE_NON_COHERENT); |
835 | ||
6def8fdd AS |
836 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
837 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
838 | * polygons in the same 8x4 pixel/sample area to be processed without | |
839 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
840 | * buffer." | |
841 | * | |
842 | * This optimization is off by default for BDW and CHV; turn it on. | |
843 | */ | |
844 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
845 | ||
48404636 AS |
846 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
847 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
848 | ||
7eebcde6 AS |
849 | /* |
850 | * BSpec recommends 8x4 when MSAA is used, | |
851 | * however in practice 16x4 seems fastest. | |
852 | * | |
853 | * Note that PS/WM thread counts depend on the WIZ hashing | |
854 | * disable bit, which we don't touch here, but it's good | |
855 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
856 | */ | |
857 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
858 | GEN6_WIZ_HASHING_MASK, | |
859 | GEN6_WIZ_HASHING_16x4); | |
860 | ||
e9a64ada AS |
861 | return 0; |
862 | } | |
863 | ||
0bc40be8 | 864 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 865 | { |
e9a64ada | 866 | int ret; |
0bc40be8 | 867 | struct drm_device *dev = engine->dev; |
888b5995 | 868 | struct drm_i915_private *dev_priv = dev->dev_private; |
86d7f238 | 869 | |
0bc40be8 | 870 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
871 | if (ret) |
872 | return ret; | |
873 | ||
101b376d | 874 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 875 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 876 | |
101b376d | 877 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
878 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
879 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 880 | |
7225342a MK |
881 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
882 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 883 | |
7225342a | 884 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
885 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
886 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 887 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 888 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 889 | |
86d7f238 AS |
890 | return 0; |
891 | } | |
892 | ||
0bc40be8 | 893 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 894 | { |
e9a64ada | 895 | int ret; |
0bc40be8 | 896 | struct drm_device *dev = engine->dev; |
00e1e623 VS |
897 | struct drm_i915_private *dev_priv = dev->dev_private; |
898 | ||
0bc40be8 | 899 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
900 | if (ret) |
901 | return ret; | |
902 | ||
00e1e623 | 903 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 904 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 905 | |
d60de81d KG |
906 | /* Improve HiZ throughput on CHV. */ |
907 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
908 | ||
7225342a MK |
909 | return 0; |
910 | } | |
911 | ||
0bc40be8 | 912 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 913 | { |
0bc40be8 | 914 | struct drm_device *dev = engine->dev; |
ab0dfafe | 915 | struct drm_i915_private *dev_priv = dev->dev_private; |
e0f3fa09 | 916 | int ret; |
ab0dfafe | 917 | |
68370e0a | 918 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
919 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
920 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
921 | ||
68370e0a | 922 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
923 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
924 | ECOCHK_DIS_TLB); | |
925 | ||
68370e0a MK |
926 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
927 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 928 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 929 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
930 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
931 | ||
68370e0a | 932 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
933 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
934 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
935 | ||
e87a005d JN |
936 | /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ |
937 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
938 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
a86eb582 DL |
939 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
940 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 941 | |
e87a005d JN |
942 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
943 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || | |
944 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { | |
183c6dac DL |
945 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
946 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
947 | /* |
948 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
949 | * but we do that in per ctx batchbuffer as there is an issue | |
950 | * with this register not getting restored on ctx restore | |
951 | */ | |
183c6dac DL |
952 | } |
953 | ||
68370e0a MK |
954 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
955 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
956 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
957 | GEN9_ENABLE_YV12_BUGFIX | | |
958 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 959 | |
68370e0a MK |
960 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
961 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
962 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
963 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 964 | |
68370e0a | 965 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
966 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
967 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
968 | ||
5a2ae95e | 969 | /* WaDisableMaskBasedCammingInRCC:skl,bxt */ |
e87a005d JN |
970 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) || |
971 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) | |
38a39a7b BW |
972 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
973 | PIXEL_MASK_CAMMING_DISABLE); | |
974 | ||
6fd72492 MK |
975 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
976 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
977 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
978 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 979 | |
60f452e6 MK |
980 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
981 | * both tied to WaForceContextSaveRestoreNonCoherent | |
982 | * in some hsds for skl. We keep the tie for all gen9. The | |
983 | * documentation is a bit hazy and so we want to get common behaviour, | |
984 | * even though there is no clear evidence we would need both on kbl/bxt. | |
985 | * This area has been source of system hangs so we play it safe | |
986 | * and mimic the skl regardless of what bspec says. | |
987 | * | |
988 | * Use Force Non-Coherent whenever executing a 3D context. This | |
989 | * is a workaround for a possible hang in the unlikely event | |
990 | * a TLB invalidation occurs during a PSD flush. | |
991 | */ | |
992 | ||
993 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
994 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
995 | HDC_FORCE_NON_COHERENT); | |
996 | ||
997 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
998 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
999 | BDW_DISABLE_HDC_INVALIDATION); | |
1000 | ||
68370e0a MK |
1001 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
1002 | if (IS_SKYLAKE(dev_priv) || | |
1003 | IS_KABYLAKE(dev_priv) || | |
1004 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
1005 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
1006 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 1007 | |
68370e0a | 1008 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
1009 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
1010 | ||
68370e0a | 1011 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
1012 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
1013 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
1014 | ||
f98edb2b | 1015 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
1016 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
1017 | if (ret) | |
1018 | return ret; | |
1019 | ||
68370e0a | 1020 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 1021 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
1022 | if (ret) |
1023 | return ret; | |
1024 | ||
68370e0a | 1025 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 1026 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
1027 | if (ret) |
1028 | return ret; | |
1029 | ||
3b106531 HN |
1030 | return 0; |
1031 | } | |
1032 | ||
0bc40be8 | 1033 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 1034 | { |
0bc40be8 | 1035 | struct drm_device *dev = engine->dev; |
b7668791 DL |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; |
1037 | u8 vals[3] = { 0, 0, 0 }; | |
1038 | unsigned int i; | |
1039 | ||
1040 | for (i = 0; i < 3; i++) { | |
1041 | u8 ss; | |
1042 | ||
1043 | /* | |
1044 | * Only consider slices where one, and only one, subslice has 7 | |
1045 | * EUs | |
1046 | */ | |
a4d8a0fe | 1047 | if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) |
b7668791 DL |
1048 | continue; |
1049 | ||
1050 | /* | |
1051 | * subslice_7eu[i] != 0 (because of the check above) and | |
1052 | * ss_max == 4 (maximum number of subslices possible per slice) | |
1053 | * | |
1054 | * -> 0 <= ss <= 3; | |
1055 | */ | |
1056 | ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; | |
1057 | vals[i] = 3 - ss; | |
1058 | } | |
1059 | ||
1060 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
1061 | return 0; | |
1062 | ||
1063 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
1064 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
1065 | GEN9_IZ_HASHING_MASK(2) | | |
1066 | GEN9_IZ_HASHING_MASK(1) | | |
1067 | GEN9_IZ_HASHING_MASK(0), | |
1068 | GEN9_IZ_HASHING(2, vals[2]) | | |
1069 | GEN9_IZ_HASHING(1, vals[1]) | | |
1070 | GEN9_IZ_HASHING(0, vals[0])); | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
0bc40be8 | 1075 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 1076 | { |
aa0011a8 | 1077 | int ret; |
0bc40be8 | 1078 | struct drm_device *dev = engine->dev; |
d0bbbc4f DL |
1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
1080 | ||
0bc40be8 | 1081 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1082 | if (ret) |
1083 | return ret; | |
8d205494 | 1084 | |
a78536e7 AS |
1085 | /* |
1086 | * Actual WA is to disable percontext preemption granularity control | |
1087 | * until D0 which is the default case so this is equivalent to | |
1088 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
1089 | */ | |
1090 | if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { | |
1091 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, | |
1092 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
1093 | } | |
1094 | ||
e87a005d | 1095 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
9c4cbf82 MK |
1096 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
1097 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
1098 | _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); | |
1099 | } | |
1100 | ||
1101 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes | |
1102 | * involving this register should also be added to WA batch as required. | |
1103 | */ | |
e87a005d | 1104 | if (IS_SKL_REVID(dev, 0, SKL_REVID_E0)) |
9c4cbf82 MK |
1105 | /* WaDisableLSQCROPERFforOCL:skl */ |
1106 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1107 | GEN8_LQSC_RO_PERF_DIS); | |
1108 | ||
1109 | /* WaEnableGapsTsvCreditFix:skl */ | |
e87a005d | 1110 | if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) { |
9c4cbf82 MK |
1111 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
1112 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1113 | } | |
1114 | ||
d0bbbc4f | 1115 | /* WaDisablePowerCompilerClockGating:skl */ |
e87a005d | 1116 | if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0)) |
d0bbbc4f DL |
1117 | WA_SET_BIT_MASKED(HIZ_CHICKEN, |
1118 | BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); | |
1119 | ||
e87a005d JN |
1120 | /* WaBarrierPerformanceFixDisable:skl */ |
1121 | if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0)) | |
5b6fd12a VS |
1122 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
1123 | HDC_FENCE_DEST_SLM_DISABLE | | |
1124 | HDC_BARRIER_PERFORMANCE_DISABLE); | |
1125 | ||
9bd9dfb4 | 1126 | /* WaDisableSbeCacheDispatchPortSharing:skl */ |
e87a005d | 1127 | if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) |
9bd9dfb4 MK |
1128 | WA_SET_BIT_MASKED( |
1129 | GEN7_HALF_SLICE_CHICKEN1, | |
1130 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
9bd9dfb4 | 1131 | |
c000456c MK |
1132 | /* WaDisableGafsUnitClkGating:skl */ |
1133 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1134 | ||
6107497e | 1135 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1136 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1137 | if (ret) |
1138 | return ret; | |
1139 | ||
0bc40be8 | 1140 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1141 | } |
1142 | ||
0bc40be8 | 1143 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1144 | { |
aa0011a8 | 1145 | int ret; |
0bc40be8 | 1146 | struct drm_device *dev = engine->dev; |
dfb601e6 NH |
1147 | struct drm_i915_private *dev_priv = dev->dev_private; |
1148 | ||
0bc40be8 | 1149 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1150 | if (ret) |
1151 | return ret; | |
cae0437f | 1152 | |
9c4cbf82 MK |
1153 | /* WaStoreMultiplePTEenable:bxt */ |
1154 | /* This is a requirement according to Hardware specification */ | |
cbdc12a9 | 1155 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1156 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1157 | ||
1158 | /* WaSetClckGatingDisableMedia:bxt */ | |
cbdc12a9 | 1159 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1160 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1161 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1162 | } | |
1163 | ||
dfb601e6 NH |
1164 | /* WaDisableThreadStallDopClockGating:bxt */ |
1165 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1166 | STALL_DOP_GATING_DISABLE); | |
1167 | ||
983b4b9d | 1168 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
e87a005d | 1169 | if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1170 | WA_SET_BIT_MASKED( |
1171 | GEN7_HALF_SLICE_CHICKEN1, | |
1172 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1173 | } | |
1174 | ||
2c8580e4 AS |
1175 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1176 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1177 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1178 | /* WaDisableLSQCROPERFforOCL:bxt */ |
2c8580e4 | 1179 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 | 1180 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1181 | if (ret) |
1182 | return ret; | |
a786d53a | 1183 | |
0bc40be8 | 1184 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1185 | if (ret) |
1186 | return ret; | |
2c8580e4 AS |
1187 | } |
1188 | ||
7b9005cd MK |
1189 | /* WaInsertDummyPushConstPs:bxt */ |
1190 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
1191 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1192 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1193 | ||
cae0437f NH |
1194 | return 0; |
1195 | } | |
1196 | ||
68370e0a MK |
1197 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1198 | { | |
79164509 | 1199 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
68370e0a MK |
1200 | int ret; |
1201 | ||
1202 | ret = gen9_init_workarounds(engine); | |
1203 | if (ret) | |
1204 | return ret; | |
1205 | ||
79164509 MK |
1206 | /* WaEnableGapsTsvCreditFix:kbl */ |
1207 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1208 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1209 | ||
b9042046 MK |
1210 | /* WaDisableDynamicCreditSharing:kbl */ |
1211 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1212 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1213 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1214 | ||
3d042d46 MK |
1215 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1216 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1217 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1218 | HDC_FENCE_DEST_SLM_DISABLE); | |
1219 | ||
738fa1b3 MK |
1220 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1221 | * involving this register should also be added to WA batch as required. | |
1222 | */ | |
1223 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1224 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1225 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1226 | GEN8_LQSC_RO_PERF_DIS); | |
1227 | ||
7b9005cd MK |
1228 | /* WaInsertDummyPushConstPs:kbl */ |
1229 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1230 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, | |
1231 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1232 | ||
3af5f113 MK |
1233 | /* WaDisableGafsUnitClkGating:kbl */ |
1234 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1235 | ||
738fa1b3 MK |
1236 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1237 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1238 | if (ret) | |
1239 | return ret; | |
1240 | ||
68370e0a MK |
1241 | return 0; |
1242 | } | |
1243 | ||
0bc40be8 | 1244 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1245 | { |
0bc40be8 | 1246 | struct drm_device *dev = engine->dev; |
7225342a MK |
1247 | struct drm_i915_private *dev_priv = dev->dev_private; |
1248 | ||
0bc40be8 | 1249 | WARN_ON(engine->id != RCS); |
7225342a MK |
1250 | |
1251 | dev_priv->workarounds.count = 0; | |
33136b06 | 1252 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a MK |
1253 | |
1254 | if (IS_BROADWELL(dev)) | |
0bc40be8 | 1255 | return bdw_init_workarounds(engine); |
7225342a MK |
1256 | |
1257 | if (IS_CHERRYVIEW(dev)) | |
0bc40be8 | 1258 | return chv_init_workarounds(engine); |
00e1e623 | 1259 | |
8d205494 | 1260 | if (IS_SKYLAKE(dev)) |
0bc40be8 | 1261 | return skl_init_workarounds(engine); |
cae0437f NH |
1262 | |
1263 | if (IS_BROXTON(dev)) | |
0bc40be8 | 1264 | return bxt_init_workarounds(engine); |
3b106531 | 1265 | |
68370e0a MK |
1266 | if (IS_KABYLAKE(dev_priv)) |
1267 | return kbl_init_workarounds(engine); | |
1268 | ||
00e1e623 VS |
1269 | return 0; |
1270 | } | |
1271 | ||
0bc40be8 | 1272 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1273 | { |
0bc40be8 | 1274 | struct drm_device *dev = engine->dev; |
1ec14ad3 | 1275 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 | 1276 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1277 | if (ret) |
1278 | return ret; | |
a69ffdbf | 1279 | |
61a563a2 AG |
1280 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1281 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1282 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1283 | |
1284 | /* We need to disable the AsyncFlip performance optimisations in order | |
1285 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1286 | * programmed to '1' on all products. | |
8693a824 | 1287 | * |
2441f877 | 1288 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1289 | */ |
2441f877 | 1290 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
1c8c38c5 CW |
1291 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1292 | ||
f05bb0c7 | 1293 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1294 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1295 | if (INTEL_INFO(dev)->gen == 6) |
1296 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1297 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1298 | |
01fa0302 | 1299 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1300 | if (IS_GEN7(dev)) |
1301 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1302 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1303 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1304 | |
5e13a0c5 | 1305 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1306 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1307 | * "If this bit is set, STCunit will have LRA as replacement | |
1308 | * policy. [...] This bit must be reset. LRA replacement | |
1309 | * policy is not supported." | |
1310 | */ | |
1311 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1312 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1313 | } |
1314 | ||
9cc83020 | 1315 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) |
6b26c86d | 1316 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1317 | |
040d2baa | 1318 | if (HAS_L3_DPF(dev)) |
0bc40be8 | 1319 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1320 | |
0bc40be8 | 1321 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1322 | } |
1323 | ||
0bc40be8 | 1324 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1325 | { |
0bc40be8 | 1326 | struct drm_device *dev = engine->dev; |
3e78998a BW |
1327 | struct drm_i915_private *dev_priv = dev->dev_private; |
1328 | ||
1329 | if (dev_priv->semaphore_obj) { | |
1330 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1331 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1332 | dev_priv->semaphore_obj = NULL; | |
1333 | } | |
b45305fc | 1334 | |
0bc40be8 | 1335 | intel_fini_pipe_control(engine); |
c6df541c CW |
1336 | } |
1337 | ||
f7169687 | 1338 | static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1339 | unsigned int num_dwords) |
1340 | { | |
1341 | #define MBOX_UPDATE_DWORDS 8 | |
4a570db5 | 1342 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1343 | struct drm_device *dev = signaller->dev; |
1344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1345 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1346 | enum intel_engine_id id; |
1347 | int ret, num_rings; | |
3e78998a BW |
1348 | |
1349 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1350 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1351 | #undef MBOX_UPDATE_DWORDS | |
1352 | ||
5fb9de1a | 1353 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1354 | if (ret) |
1355 | return ret; | |
1356 | ||
c3232b18 | 1357 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1358 | u32 seqno; |
c3232b18 | 1359 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1360 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1361 | continue; | |
1362 | ||
f7169687 | 1363 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1364 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1365 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1366 | PIPE_CONTROL_QW_WRITE | | |
1367 | PIPE_CONTROL_FLUSH_ENABLE); | |
1368 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1369 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1370 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1371 | intel_ring_emit(signaller, 0); |
1372 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
83e53802 | 1373 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1374 | intel_ring_emit(signaller, 0); |
1375 | } | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
f7169687 | 1380 | static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, |
3e78998a BW |
1381 | unsigned int num_dwords) |
1382 | { | |
1383 | #define MBOX_UPDATE_DWORDS 6 | |
4a570db5 | 1384 | struct intel_engine_cs *signaller = signaller_req->engine; |
3e78998a BW |
1385 | struct drm_device *dev = signaller->dev; |
1386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1387 | struct intel_engine_cs *waiter; | |
c3232b18 DG |
1388 | enum intel_engine_id id; |
1389 | int ret, num_rings; | |
3e78998a BW |
1390 | |
1391 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1392 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1393 | #undef MBOX_UPDATE_DWORDS | |
1394 | ||
5fb9de1a | 1395 | ret = intel_ring_begin(signaller_req, num_dwords); |
3e78998a BW |
1396 | if (ret) |
1397 | return ret; | |
1398 | ||
c3232b18 | 1399 | for_each_engine_id(waiter, dev_priv, id) { |
6259cead | 1400 | u32 seqno; |
c3232b18 | 1401 | u64 gtt_offset = signaller->semaphore.signal_ggtt[id]; |
3e78998a BW |
1402 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1403 | continue; | |
1404 | ||
f7169687 | 1405 | seqno = i915_gem_request_get_seqno(signaller_req); |
3e78998a BW |
1406 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1407 | MI_FLUSH_DW_OP_STOREDW); | |
1408 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1409 | MI_FLUSH_DW_USE_GTT); | |
1410 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1411 | intel_ring_emit(signaller, seqno); |
3e78998a | 1412 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
83e53802 | 1413 | MI_SEMAPHORE_TARGET(waiter->hw_id)); |
3e78998a BW |
1414 | intel_ring_emit(signaller, 0); |
1415 | } | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
f7169687 | 1420 | static int gen6_signal(struct drm_i915_gem_request *signaller_req, |
024a43e1 | 1421 | unsigned int num_dwords) |
1ec14ad3 | 1422 | { |
4a570db5 | 1423 | struct intel_engine_cs *signaller = signaller_req->engine; |
024a43e1 BW |
1424 | struct drm_device *dev = signaller->dev; |
1425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1426 | struct intel_engine_cs *useless; |
c3232b18 DG |
1427 | enum intel_engine_id id; |
1428 | int ret, num_rings; | |
78325f2d | 1429 | |
a1444b79 BW |
1430 | #define MBOX_UPDATE_DWORDS 3 |
1431 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1432 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1433 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 | 1434 | |
5fb9de1a | 1435 | ret = intel_ring_begin(signaller_req, num_dwords); |
024a43e1 BW |
1436 | if (ret) |
1437 | return ret; | |
024a43e1 | 1438 | |
c3232b18 DG |
1439 | for_each_engine_id(useless, dev_priv, id) { |
1440 | i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id]; | |
f0f59a00 VS |
1441 | |
1442 | if (i915_mmio_reg_valid(mbox_reg)) { | |
f7169687 | 1443 | u32 seqno = i915_gem_request_get_seqno(signaller_req); |
f0f59a00 | 1444 | |
78325f2d | 1445 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
f92a9162 | 1446 | intel_ring_emit_reg(signaller, mbox_reg); |
6259cead | 1447 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1448 | } |
1449 | } | |
024a43e1 | 1450 | |
a1444b79 BW |
1451 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1452 | if (num_rings % 2 == 0) | |
1453 | intel_ring_emit(signaller, MI_NOOP); | |
1454 | ||
024a43e1 | 1455 | return 0; |
1ec14ad3 CW |
1456 | } |
1457 | ||
c8c99b0f BW |
1458 | /** |
1459 | * gen6_add_request - Update the semaphore mailbox registers | |
ee044a88 JH |
1460 | * |
1461 | * @request - request to write to the ring | |
c8c99b0f BW |
1462 | * |
1463 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1464 | * This acts like a signal in the canonical semaphore. | |
1465 | */ | |
1ec14ad3 | 1466 | static int |
ee044a88 | 1467 | gen6_add_request(struct drm_i915_gem_request *req) |
1ec14ad3 | 1468 | { |
4a570db5 | 1469 | struct intel_engine_cs *engine = req->engine; |
024a43e1 | 1470 | int ret; |
52ed2325 | 1471 | |
e2f80391 TU |
1472 | if (engine->semaphore.signal) |
1473 | ret = engine->semaphore.signal(req, 4); | |
707d9cf9 | 1474 | else |
5fb9de1a | 1475 | ret = intel_ring_begin(req, 4); |
707d9cf9 | 1476 | |
1ec14ad3 CW |
1477 | if (ret) |
1478 | return ret; | |
1479 | ||
e2f80391 TU |
1480 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1481 | intel_ring_emit(engine, | |
1482 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1483 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1484 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1485 | __intel_ring_advance(engine); | |
1ec14ad3 | 1486 | |
1ec14ad3 CW |
1487 | return 0; |
1488 | } | |
1489 | ||
f72b3435 MK |
1490 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1491 | u32 seqno) | |
1492 | { | |
1493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1494 | return dev_priv->last_seqno < seqno; | |
1495 | } | |
1496 | ||
c8c99b0f BW |
1497 | /** |
1498 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1499 | * | |
1500 | * @waiter - ring that is waiting | |
1501 | * @signaller - ring which has, or will signal | |
1502 | * @seqno - seqno which the waiter will block on | |
1503 | */ | |
5ee426ca BW |
1504 | |
1505 | static int | |
599d924c | 1506 | gen8_ring_sync(struct drm_i915_gem_request *waiter_req, |
5ee426ca BW |
1507 | struct intel_engine_cs *signaller, |
1508 | u32 seqno) | |
1509 | { | |
4a570db5 | 1510 | struct intel_engine_cs *waiter = waiter_req->engine; |
5ee426ca BW |
1511 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; |
1512 | int ret; | |
1513 | ||
5fb9de1a | 1514 | ret = intel_ring_begin(waiter_req, 4); |
5ee426ca BW |
1515 | if (ret) |
1516 | return ret; | |
1517 | ||
1518 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1519 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1520 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1521 | MI_SEMAPHORE_SAD_GTE_SDD); |
1522 | intel_ring_emit(waiter, seqno); | |
1523 | intel_ring_emit(waiter, | |
1524 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1525 | intel_ring_emit(waiter, | |
1526 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1527 | intel_ring_advance(waiter); | |
1528 | return 0; | |
1529 | } | |
1530 | ||
c8c99b0f | 1531 | static int |
599d924c | 1532 | gen6_ring_sync(struct drm_i915_gem_request *waiter_req, |
a4872ba6 | 1533 | struct intel_engine_cs *signaller, |
686cb5f9 | 1534 | u32 seqno) |
1ec14ad3 | 1535 | { |
4a570db5 | 1536 | struct intel_engine_cs *waiter = waiter_req->engine; |
c8c99b0f BW |
1537 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1538 | MI_SEMAPHORE_COMPARE | | |
1539 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1540 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1541 | int ret; | |
1ec14ad3 | 1542 | |
1500f7ea BW |
1543 | /* Throughout all of the GEM code, seqno passed implies our current |
1544 | * seqno is >= the last seqno executed. However for hardware the | |
1545 | * comparison is strictly greater than. | |
1546 | */ | |
1547 | seqno -= 1; | |
1548 | ||
ebc348b2 | 1549 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1550 | |
5fb9de1a | 1551 | ret = intel_ring_begin(waiter_req, 4); |
1ec14ad3 CW |
1552 | if (ret) |
1553 | return ret; | |
1554 | ||
f72b3435 MK |
1555 | /* If seqno wrap happened, omit the wait with no-ops */ |
1556 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1557 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1558 | intel_ring_emit(waiter, seqno); |
1559 | intel_ring_emit(waiter, 0); | |
1560 | intel_ring_emit(waiter, MI_NOOP); | |
1561 | } else { | |
1562 | intel_ring_emit(waiter, MI_NOOP); | |
1563 | intel_ring_emit(waiter, MI_NOOP); | |
1564 | intel_ring_emit(waiter, MI_NOOP); | |
1565 | intel_ring_emit(waiter, MI_NOOP); | |
1566 | } | |
c8c99b0f | 1567 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1568 | |
1569 | return 0; | |
1570 | } | |
1571 | ||
c6df541c CW |
1572 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1573 | do { \ | |
fcbc34e4 KG |
1574 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1575 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1576 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1577 | intel_ring_emit(ring__, 0); \ | |
1578 | intel_ring_emit(ring__, 0); \ | |
1579 | } while (0) | |
1580 | ||
1581 | static int | |
ee044a88 | 1582 | pc_render_add_request(struct drm_i915_gem_request *req) |
c6df541c | 1583 | { |
4a570db5 | 1584 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1585 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1586 | int ret; |
1587 | ||
1588 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1589 | * incoherent with writes to memory, i.e. completely fubar, | |
1590 | * so we need to use PIPE_NOTIFY instead. | |
1591 | * | |
1592 | * However, we also need to workaround the qword write | |
1593 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1594 | * memory before requesting an interrupt. | |
1595 | */ | |
5fb9de1a | 1596 | ret = intel_ring_begin(req, 32); |
c6df541c CW |
1597 | if (ret) |
1598 | return ret; | |
1599 | ||
e2f80391 TU |
1600 | intel_ring_emit(engine, |
1601 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1602 | PIPE_CONTROL_WRITE_FLUSH | |
1603 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
e2f80391 TU |
1604 | intel_ring_emit(engine, |
1605 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1606 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1607 | intel_ring_emit(engine, 0); | |
1608 | PIPE_CONTROL_FLUSH(engine, scratch_addr); | |
18393f63 | 1609 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
e2f80391 | 1610 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1611 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1612 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1613 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1614 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1615 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1616 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
18393f63 | 1617 | scratch_addr += 2 * CACHELINE_BYTES; |
e2f80391 | 1618 | PIPE_CONTROL_FLUSH(engine, scratch_addr); |
a71d8d94 | 1619 | |
e2f80391 TU |
1620 | intel_ring_emit(engine, |
1621 | GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | | |
9d971b37 KG |
1622 | PIPE_CONTROL_WRITE_FLUSH | |
1623 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1624 | PIPE_CONTROL_NOTIFY); |
e2f80391 TU |
1625 | intel_ring_emit(engine, |
1626 | engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
1627 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1628 | intel_ring_emit(engine, 0); | |
1629 | __intel_ring_advance(engine); | |
c6df541c | 1630 | |
c6df541c CW |
1631 | return 0; |
1632 | } | |
1633 | ||
c04e0f3b CW |
1634 | static void |
1635 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1636 | { |
e32da7ad CW |
1637 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
1638 | ||
4cd53c0c DV |
1639 | /* Workaround to force correct ordering between irq and seqno writes on |
1640 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1641 | * ACTHD) before reading the status page. |
1642 | * | |
1643 | * Note that this effectively stalls the read by the time it takes to | |
1644 | * do a memory transaction, which more or less ensures that the write | |
1645 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1646 | * Alternatively we could delay the interrupt from the CS ring to give | |
1647 | * the write time to land, but that would incur a delay after every | |
1648 | * batch i.e. much more frequent than a delay when waiting for the | |
1649 | * interrupt (with the same net latency). | |
e32da7ad CW |
1650 | * |
1651 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1652 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1653 | */ |
e32da7ad | 1654 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1655 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
e32da7ad | 1656 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1657 | } |
1658 | ||
8187a2b7 | 1659 | static u32 |
c04e0f3b | 1660 | ring_get_seqno(struct intel_engine_cs *engine) |
8187a2b7 | 1661 | { |
0bc40be8 | 1662 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
1ec14ad3 CW |
1663 | } |
1664 | ||
b70ec5bf | 1665 | static void |
0bc40be8 | 1666 | ring_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1667 | { |
0bc40be8 | 1668 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
b70ec5bf MK |
1669 | } |
1670 | ||
c6df541c | 1671 | static u32 |
c04e0f3b | 1672 | pc_render_get_seqno(struct intel_engine_cs *engine) |
c6df541c | 1673 | { |
0bc40be8 | 1674 | return engine->scratch.cpu_page[0]; |
c6df541c CW |
1675 | } |
1676 | ||
b70ec5bf | 1677 | static void |
0bc40be8 | 1678 | pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
b70ec5bf | 1679 | { |
0bc40be8 | 1680 | engine->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1681 | } |
1682 | ||
e48d8634 | 1683 | static bool |
0bc40be8 | 1684 | gen5_ring_get_irq(struct intel_engine_cs *engine) |
e48d8634 | 1685 | { |
0bc40be8 | 1686 | struct drm_device *dev = engine->dev; |
4640c4ff | 1687 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1688 | unsigned long flags; |
e48d8634 | 1689 | |
7cd512f1 | 1690 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1691 | return false; |
1692 | ||
7338aefa | 1693 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1694 | if (engine->irq_refcount++ == 0) |
1695 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1696 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1697 | |
1698 | return true; | |
1699 | } | |
1700 | ||
1701 | static void | |
0bc40be8 | 1702 | gen5_ring_put_irq(struct intel_engine_cs *engine) |
e48d8634 | 1703 | { |
0bc40be8 | 1704 | struct drm_device *dev = engine->dev; |
4640c4ff | 1705 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1706 | unsigned long flags; |
e48d8634 | 1707 | |
7338aefa | 1708 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1709 | if (--engine->irq_refcount == 0) |
1710 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
7338aefa | 1711 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1712 | } |
1713 | ||
b13c2b96 | 1714 | static bool |
0bc40be8 | 1715 | i9xx_ring_get_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1716 | { |
0bc40be8 | 1717 | struct drm_device *dev = engine->dev; |
4640c4ff | 1718 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1719 | unsigned long flags; |
62fdfeaf | 1720 | |
7cd512f1 | 1721 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1722 | return false; |
1723 | ||
7338aefa | 1724 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1725 | if (engine->irq_refcount++ == 0) { |
1726 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
f637fde4 DV |
1727 | I915_WRITE(IMR, dev_priv->irq_mask); |
1728 | POSTING_READ(IMR); | |
1729 | } | |
7338aefa | 1730 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1731 | |
1732 | return true; | |
62fdfeaf EA |
1733 | } |
1734 | ||
8187a2b7 | 1735 | static void |
0bc40be8 | 1736 | i9xx_ring_put_irq(struct intel_engine_cs *engine) |
62fdfeaf | 1737 | { |
0bc40be8 | 1738 | struct drm_device *dev = engine->dev; |
4640c4ff | 1739 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1740 | unsigned long flags; |
62fdfeaf | 1741 | |
7338aefa | 1742 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1743 | if (--engine->irq_refcount == 0) { |
1744 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
f637fde4 DV |
1745 | I915_WRITE(IMR, dev_priv->irq_mask); |
1746 | POSTING_READ(IMR); | |
1747 | } | |
7338aefa | 1748 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1749 | } |
1750 | ||
c2798b19 | 1751 | static bool |
0bc40be8 | 1752 | i8xx_ring_get_irq(struct intel_engine_cs *engine) |
c2798b19 | 1753 | { |
0bc40be8 | 1754 | struct drm_device *dev = engine->dev; |
4640c4ff | 1755 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1756 | unsigned long flags; |
c2798b19 | 1757 | |
7cd512f1 | 1758 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1759 | return false; |
1760 | ||
7338aefa | 1761 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1762 | if (engine->irq_refcount++ == 0) { |
1763 | dev_priv->irq_mask &= ~engine->irq_enable_mask; | |
c2798b19 CW |
1764 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1765 | POSTING_READ16(IMR); | |
1766 | } | |
7338aefa | 1767 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1768 | |
1769 | return true; | |
1770 | } | |
1771 | ||
1772 | static void | |
0bc40be8 | 1773 | i8xx_ring_put_irq(struct intel_engine_cs *engine) |
c2798b19 | 1774 | { |
0bc40be8 | 1775 | struct drm_device *dev = engine->dev; |
4640c4ff | 1776 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1777 | unsigned long flags; |
c2798b19 | 1778 | |
7338aefa | 1779 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1780 | if (--engine->irq_refcount == 0) { |
1781 | dev_priv->irq_mask |= engine->irq_enable_mask; | |
c2798b19 CW |
1782 | I915_WRITE16(IMR, dev_priv->irq_mask); |
1783 | POSTING_READ16(IMR); | |
1784 | } | |
7338aefa | 1785 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1786 | } |
1787 | ||
b72f3acb | 1788 | static int |
a84c3ae1 | 1789 | bsd_ring_flush(struct drm_i915_gem_request *req, |
78501eac CW |
1790 | u32 invalidate_domains, |
1791 | u32 flush_domains) | |
d1b851fc | 1792 | { |
4a570db5 | 1793 | struct intel_engine_cs *engine = req->engine; |
b72f3acb CW |
1794 | int ret; |
1795 | ||
5fb9de1a | 1796 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1797 | if (ret) |
1798 | return ret; | |
1799 | ||
e2f80391 TU |
1800 | intel_ring_emit(engine, MI_FLUSH); |
1801 | intel_ring_emit(engine, MI_NOOP); | |
1802 | intel_ring_advance(engine); | |
b72f3acb | 1803 | return 0; |
d1b851fc ZN |
1804 | } |
1805 | ||
3cce469c | 1806 | static int |
ee044a88 | 1807 | i9xx_add_request(struct drm_i915_gem_request *req) |
d1b851fc | 1808 | { |
4a570db5 | 1809 | struct intel_engine_cs *engine = req->engine; |
3cce469c CW |
1810 | int ret; |
1811 | ||
5fb9de1a | 1812 | ret = intel_ring_begin(req, 4); |
3cce469c CW |
1813 | if (ret) |
1814 | return ret; | |
6f392d54 | 1815 | |
e2f80391 TU |
1816 | intel_ring_emit(engine, MI_STORE_DWORD_INDEX); |
1817 | intel_ring_emit(engine, | |
1818 | I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1819 | intel_ring_emit(engine, i915_gem_request_get_seqno(req)); | |
1820 | intel_ring_emit(engine, MI_USER_INTERRUPT); | |
1821 | __intel_ring_advance(engine); | |
d1b851fc | 1822 | |
3cce469c | 1823 | return 0; |
d1b851fc ZN |
1824 | } |
1825 | ||
0f46832f | 1826 | static bool |
0bc40be8 | 1827 | gen6_ring_get_irq(struct intel_engine_cs *engine) |
0f46832f | 1828 | { |
0bc40be8 | 1829 | struct drm_device *dev = engine->dev; |
4640c4ff | 1830 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1831 | unsigned long flags; |
0f46832f | 1832 | |
7cd512f1 DV |
1833 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1834 | return false; | |
0f46832f | 1835 | |
7338aefa | 1836 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1837 | if (engine->irq_refcount++ == 0) { |
1838 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1839 | I915_WRITE_IMR(engine, | |
1840 | ~(engine->irq_enable_mask | | |
35a85ac6 | 1841 | GT_PARITY_ERROR(dev))); |
15b9f80e | 1842 | else |
0bc40be8 TU |
1843 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1844 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); | |
0f46832f | 1845 | } |
7338aefa | 1846 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1847 | |
1848 | return true; | |
1849 | } | |
1850 | ||
1851 | static void | |
0bc40be8 | 1852 | gen6_ring_put_irq(struct intel_engine_cs *engine) |
0f46832f | 1853 | { |
0bc40be8 | 1854 | struct drm_device *dev = engine->dev; |
4640c4ff | 1855 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1856 | unsigned long flags; |
0f46832f | 1857 | |
7338aefa | 1858 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1859 | if (--engine->irq_refcount == 0) { |
1860 | if (HAS_L3_DPF(dev) && engine->id == RCS) | |
1861 | I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev)); | |
15b9f80e | 1862 | else |
0bc40be8 TU |
1863 | I915_WRITE_IMR(engine, ~0); |
1864 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); | |
1ec14ad3 | 1865 | } |
7338aefa | 1866 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1867 | } |
1868 | ||
a19d2933 | 1869 | static bool |
0bc40be8 | 1870 | hsw_vebox_get_irq(struct intel_engine_cs *engine) |
a19d2933 | 1871 | { |
0bc40be8 | 1872 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
1874 | unsigned long flags; | |
1875 | ||
7cd512f1 | 1876 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1877 | return false; |
1878 | ||
59cdb63d | 1879 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1880 | if (engine->irq_refcount++ == 0) { |
1881 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); | |
1882 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1883 | } |
59cdb63d | 1884 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1885 | |
1886 | return true; | |
1887 | } | |
1888 | ||
1889 | static void | |
0bc40be8 | 1890 | hsw_vebox_put_irq(struct intel_engine_cs *engine) |
a19d2933 | 1891 | { |
0bc40be8 | 1892 | struct drm_device *dev = engine->dev; |
a19d2933 BW |
1893 | struct drm_i915_private *dev_priv = dev->dev_private; |
1894 | unsigned long flags; | |
1895 | ||
59cdb63d | 1896 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
0bc40be8 TU |
1897 | if (--engine->irq_refcount == 0) { |
1898 | I915_WRITE_IMR(engine, ~0); | |
1899 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 | 1900 | } |
59cdb63d | 1901 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1902 | } |
1903 | ||
abd58f01 | 1904 | static bool |
0bc40be8 | 1905 | gen8_ring_get_irq(struct intel_engine_cs *engine) |
abd58f01 | 1906 | { |
0bc40be8 | 1907 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1908 | struct drm_i915_private *dev_priv = dev->dev_private; |
1909 | unsigned long flags; | |
1910 | ||
7cd512f1 | 1911 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1912 | return false; |
1913 | ||
1914 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1915 | if (engine->irq_refcount++ == 0) { |
1916 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1917 | I915_WRITE_IMR(engine, | |
1918 | ~(engine->irq_enable_mask | | |
abd58f01 BW |
1919 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); |
1920 | } else { | |
0bc40be8 | 1921 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
abd58f01 | 1922 | } |
0bc40be8 | 1923 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1924 | } |
1925 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1926 | ||
1927 | return true; | |
1928 | } | |
1929 | ||
1930 | static void | |
0bc40be8 | 1931 | gen8_ring_put_irq(struct intel_engine_cs *engine) |
abd58f01 | 1932 | { |
0bc40be8 | 1933 | struct drm_device *dev = engine->dev; |
abd58f01 BW |
1934 | struct drm_i915_private *dev_priv = dev->dev_private; |
1935 | unsigned long flags; | |
1936 | ||
1937 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1938 | if (--engine->irq_refcount == 0) { |
1939 | if (HAS_L3_DPF(dev) && engine->id == RCS) { | |
1940 | I915_WRITE_IMR(engine, | |
abd58f01 BW |
1941 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
1942 | } else { | |
0bc40be8 | 1943 | I915_WRITE_IMR(engine, ~0); |
abd58f01 | 1944 | } |
0bc40be8 | 1945 | POSTING_READ(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1946 | } |
1947 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1948 | } | |
1949 | ||
d1b851fc | 1950 | static int |
53fddaf7 | 1951 | i965_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 1952 | u64 offset, u32 length, |
8e004efc | 1953 | unsigned dispatch_flags) |
d1b851fc | 1954 | { |
4a570db5 | 1955 | struct intel_engine_cs *engine = req->engine; |
e1f99ce6 | 1956 | int ret; |
78501eac | 1957 | |
5fb9de1a | 1958 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1959 | if (ret) |
1960 | return ret; | |
1961 | ||
e2f80391 | 1962 | intel_ring_emit(engine, |
65f56876 CW |
1963 | MI_BATCH_BUFFER_START | |
1964 | MI_BATCH_GTT | | |
8e004efc JH |
1965 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1966 | 0 : MI_BATCH_NON_SECURE_I965)); | |
e2f80391 TU |
1967 | intel_ring_emit(engine, offset); |
1968 | intel_ring_advance(engine); | |
78501eac | 1969 | |
d1b851fc ZN |
1970 | return 0; |
1971 | } | |
1972 | ||
b45305fc DV |
1973 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1974 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1975 | #define I830_TLB_ENTRIES (2) |
1976 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1977 | static int |
53fddaf7 | 1978 | i830_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
1979 | u64 offset, u32 len, |
1980 | unsigned dispatch_flags) | |
62fdfeaf | 1981 | { |
4a570db5 | 1982 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 1983 | u32 cs_offset = engine->scratch.gtt_offset; |
c4e7a414 | 1984 | int ret; |
62fdfeaf | 1985 | |
5fb9de1a | 1986 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1987 | if (ret) |
1988 | return ret; | |
62fdfeaf | 1989 | |
c4d69da1 | 1990 | /* Evict the invalid PTE TLBs */ |
e2f80391 TU |
1991 | intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1992 | intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1993 | intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1994 | intel_ring_emit(engine, cs_offset); | |
1995 | intel_ring_emit(engine, 0xdeadbeef); | |
1996 | intel_ring_emit(engine, MI_NOOP); | |
1997 | intel_ring_advance(engine); | |
b45305fc | 1998 | |
8e004efc | 1999 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
2000 | if (len > I830_BATCH_LIMIT) |
2001 | return -ENOSPC; | |
2002 | ||
5fb9de1a | 2003 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
2004 | if (ret) |
2005 | return ret; | |
c4d69da1 CW |
2006 | |
2007 | /* Blit the batch (which has now all relocs applied) to the | |
2008 | * stable batch scratch bo area (so that the CS never | |
2009 | * stumbles over its tlb invalidation bug) ... | |
2010 | */ | |
e2f80391 TU |
2011 | intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
2012 | intel_ring_emit(engine, | |
2013 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
2014 | intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096); | |
2015 | intel_ring_emit(engine, cs_offset); | |
2016 | intel_ring_emit(engine, 4096); | |
2017 | intel_ring_emit(engine, offset); | |
2018 | ||
2019 | intel_ring_emit(engine, MI_FLUSH); | |
2020 | intel_ring_emit(engine, MI_NOOP); | |
2021 | intel_ring_advance(engine); | |
b45305fc DV |
2022 | |
2023 | /* ... and execute it. */ | |
c4d69da1 | 2024 | offset = cs_offset; |
b45305fc | 2025 | } |
e1f99ce6 | 2026 | |
9d611c03 | 2027 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
2028 | if (ret) |
2029 | return ret; | |
2030 | ||
e2f80391 TU |
2031 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2032 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2033 | 0 : MI_BATCH_NON_SECURE)); | |
2034 | intel_ring_advance(engine); | |
c4d69da1 | 2035 | |
fb3256da DV |
2036 | return 0; |
2037 | } | |
2038 | ||
2039 | static int | |
53fddaf7 | 2040 | i915_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2041 | u64 offset, u32 len, |
8e004efc | 2042 | unsigned dispatch_flags) |
fb3256da | 2043 | { |
4a570db5 | 2044 | struct intel_engine_cs *engine = req->engine; |
fb3256da DV |
2045 | int ret; |
2046 | ||
5fb9de1a | 2047 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
2048 | if (ret) |
2049 | return ret; | |
2050 | ||
e2f80391 TU |
2051 | intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
2052 | intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
2053 | 0 : MI_BATCH_NON_SECURE)); | |
2054 | intel_ring_advance(engine); | |
62fdfeaf | 2055 | |
62fdfeaf EA |
2056 | return 0; |
2057 | } | |
2058 | ||
0bc40be8 | 2059 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 2060 | { |
0bc40be8 | 2061 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
7d3fdfff VS |
2062 | |
2063 | if (!dev_priv->status_page_dmah) | |
2064 | return; | |
2065 | ||
0bc40be8 TU |
2066 | drm_pci_free(engine->dev, dev_priv->status_page_dmah); |
2067 | engine->status_page.page_addr = NULL; | |
7d3fdfff VS |
2068 | } |
2069 | ||
0bc40be8 | 2070 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2071 | { |
05394f39 | 2072 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2073 | |
0bc40be8 | 2074 | obj = engine->status_page.obj; |
8187a2b7 | 2075 | if (obj == NULL) |
62fdfeaf | 2076 | return; |
62fdfeaf | 2077 | |
9da3da66 | 2078 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 2079 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 2080 | drm_gem_object_unreference(&obj->base); |
0bc40be8 | 2081 | engine->status_page.obj = NULL; |
62fdfeaf EA |
2082 | } |
2083 | ||
0bc40be8 | 2084 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 2085 | { |
0bc40be8 | 2086 | struct drm_i915_gem_object *obj = engine->status_page.obj; |
62fdfeaf | 2087 | |
7d3fdfff | 2088 | if (obj == NULL) { |
1f767e02 | 2089 | unsigned flags; |
e3efda49 | 2090 | int ret; |
e4ffd173 | 2091 | |
0bc40be8 | 2092 | obj = i915_gem_alloc_object(engine->dev, 4096); |
e3efda49 CW |
2093 | if (obj == NULL) { |
2094 | DRM_ERROR("Failed to allocate status page\n"); | |
2095 | return -ENOMEM; | |
2096 | } | |
62fdfeaf | 2097 | |
e3efda49 CW |
2098 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
2099 | if (ret) | |
2100 | goto err_unref; | |
2101 | ||
1f767e02 | 2102 | flags = 0; |
0bc40be8 | 2103 | if (!HAS_LLC(engine->dev)) |
1f767e02 CW |
2104 | /* On g33, we cannot place HWS above 256MiB, so |
2105 | * restrict its pinning to the low mappable arena. | |
2106 | * Though this restriction is not documented for | |
2107 | * gen4, gen5, or byt, they also behave similarly | |
2108 | * and hang if the HWS is placed at the top of the | |
2109 | * GTT. To generalise, it appears that all !llc | |
2110 | * platforms have issues with us placing the HWS | |
2111 | * above the mappable region (even though we never | |
2112 | * actualy map it). | |
2113 | */ | |
2114 | flags |= PIN_MAPPABLE; | |
2115 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
2116 | if (ret) { |
2117 | err_unref: | |
2118 | drm_gem_object_unreference(&obj->base); | |
2119 | return ret; | |
2120 | } | |
2121 | ||
0bc40be8 | 2122 | engine->status_page.obj = obj; |
e3efda49 | 2123 | } |
62fdfeaf | 2124 | |
0bc40be8 TU |
2125 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
2126 | engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); | |
2127 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 2128 | |
8187a2b7 | 2129 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
0bc40be8 | 2130 | engine->name, engine->status_page.gfx_addr); |
62fdfeaf EA |
2131 | |
2132 | return 0; | |
62fdfeaf EA |
2133 | } |
2134 | ||
0bc40be8 | 2135 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 2136 | { |
0bc40be8 | 2137 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
6b8294a4 CW |
2138 | |
2139 | if (!dev_priv->status_page_dmah) { | |
2140 | dev_priv->status_page_dmah = | |
0bc40be8 | 2141 | drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE); |
6b8294a4 CW |
2142 | if (!dev_priv->status_page_dmah) |
2143 | return -ENOMEM; | |
2144 | } | |
2145 | ||
0bc40be8 TU |
2146 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
2147 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
2148 | |
2149 | return 0; | |
2150 | } | |
2151 | ||
7ba717cf | 2152 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 2153 | { |
def0c5f6 | 2154 | if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
0a798eb9 | 2155 | i915_gem_object_unpin_map(ringbuf->obj); |
def0c5f6 CW |
2156 | else |
2157 | iounmap(ringbuf->virtual_start); | |
8305216f | 2158 | ringbuf->virtual_start = NULL; |
0eb973d3 | 2159 | ringbuf->vma = NULL; |
2919d291 | 2160 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
2161 | } |
2162 | ||
2163 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
2164 | struct intel_ringbuffer *ringbuf) | |
2165 | { | |
2166 | struct drm_i915_private *dev_priv = to_i915(dev); | |
72e96d64 | 2167 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
7ba717cf | 2168 | struct drm_i915_gem_object *obj = ringbuf->obj; |
a687a43a CW |
2169 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
2170 | unsigned flags = PIN_OFFSET_BIAS | 4096; | |
8305216f | 2171 | void *addr; |
7ba717cf TD |
2172 | int ret; |
2173 | ||
def0c5f6 | 2174 | if (HAS_LLC(dev_priv) && !obj->stolen) { |
a687a43a | 2175 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
def0c5f6 CW |
2176 | if (ret) |
2177 | return ret; | |
7ba717cf | 2178 | |
def0c5f6 | 2179 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
d2cad535 CW |
2180 | if (ret) |
2181 | goto err_unpin; | |
def0c5f6 | 2182 | |
8305216f DG |
2183 | addr = i915_gem_object_pin_map(obj); |
2184 | if (IS_ERR(addr)) { | |
2185 | ret = PTR_ERR(addr); | |
d2cad535 | 2186 | goto err_unpin; |
def0c5f6 CW |
2187 | } |
2188 | } else { | |
a687a43a CW |
2189 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
2190 | flags | PIN_MAPPABLE); | |
def0c5f6 CW |
2191 | if (ret) |
2192 | return ret; | |
7ba717cf | 2193 | |
def0c5f6 | 2194 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
d2cad535 CW |
2195 | if (ret) |
2196 | goto err_unpin; | |
def0c5f6 | 2197 | |
ff3dc087 DCS |
2198 | /* Access through the GTT requires the device to be awake. */ |
2199 | assert_rpm_wakelock_held(dev_priv); | |
2200 | ||
8305216f DG |
2201 | addr = ioremap_wc(ggtt->mappable_base + |
2202 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
2203 | if (addr == NULL) { | |
d2cad535 CW |
2204 | ret = -ENOMEM; |
2205 | goto err_unpin; | |
def0c5f6 | 2206 | } |
7ba717cf TD |
2207 | } |
2208 | ||
8305216f | 2209 | ringbuf->virtual_start = addr; |
0eb973d3 | 2210 | ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
7ba717cf | 2211 | return 0; |
d2cad535 CW |
2212 | |
2213 | err_unpin: | |
2214 | i915_gem_object_ggtt_unpin(obj); | |
2215 | return ret; | |
7ba717cf TD |
2216 | } |
2217 | ||
01101fa7 | 2218 | static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
7ba717cf | 2219 | { |
2919d291 OM |
2220 | drm_gem_object_unreference(&ringbuf->obj->base); |
2221 | ringbuf->obj = NULL; | |
2222 | } | |
2223 | ||
01101fa7 CW |
2224 | static int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
2225 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 2226 | { |
05394f39 | 2227 | struct drm_i915_gem_object *obj; |
62fdfeaf | 2228 | |
ebc052e0 CW |
2229 | obj = NULL; |
2230 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 2231 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 2232 | if (obj == NULL) |
93b0a4e0 | 2233 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
2234 | if (obj == NULL) |
2235 | return -ENOMEM; | |
8187a2b7 | 2236 | |
24f3a8cf AG |
2237 | /* mark ring buffers as read-only from GPU side by default */ |
2238 | obj->gt_ro = 1; | |
2239 | ||
93b0a4e0 | 2240 | ringbuf->obj = obj; |
e3efda49 | 2241 | |
7ba717cf | 2242 | return 0; |
e3efda49 CW |
2243 | } |
2244 | ||
01101fa7 CW |
2245 | struct intel_ringbuffer * |
2246 | intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size) | |
2247 | { | |
2248 | struct intel_ringbuffer *ring; | |
2249 | int ret; | |
2250 | ||
2251 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
608c1a52 CW |
2252 | if (ring == NULL) { |
2253 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2254 | engine->name); | |
01101fa7 | 2255 | return ERR_PTR(-ENOMEM); |
608c1a52 | 2256 | } |
01101fa7 | 2257 | |
4a570db5 | 2258 | ring->engine = engine; |
608c1a52 | 2259 | list_add(&ring->link, &engine->buffers); |
01101fa7 CW |
2260 | |
2261 | ring->size = size; | |
2262 | /* Workaround an erratum on the i830 which causes a hang if | |
2263 | * the TAIL pointer points to within the last 2 cachelines | |
2264 | * of the buffer. | |
2265 | */ | |
2266 | ring->effective_size = size; | |
2267 | if (IS_I830(engine->dev) || IS_845G(engine->dev)) | |
2268 | ring->effective_size -= 2 * CACHELINE_BYTES; | |
2269 | ||
2270 | ring->last_retired_head = -1; | |
2271 | intel_ring_update_space(ring); | |
2272 | ||
2273 | ret = intel_alloc_ringbuffer_obj(engine->dev, ring); | |
2274 | if (ret) { | |
608c1a52 CW |
2275 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", |
2276 | engine->name, ret); | |
2277 | list_del(&ring->link); | |
01101fa7 CW |
2278 | kfree(ring); |
2279 | return ERR_PTR(ret); | |
2280 | } | |
2281 | ||
2282 | return ring; | |
2283 | } | |
2284 | ||
2285 | void | |
2286 | intel_ringbuffer_free(struct intel_ringbuffer *ring) | |
2287 | { | |
2288 | intel_destroy_ringbuffer_obj(ring); | |
608c1a52 | 2289 | list_del(&ring->link); |
01101fa7 CW |
2290 | kfree(ring); |
2291 | } | |
2292 | ||
e3efda49 | 2293 | static int intel_init_ring_buffer(struct drm_device *dev, |
0bc40be8 | 2294 | struct intel_engine_cs *engine) |
e3efda49 | 2295 | { |
bfc882b4 | 2296 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
2297 | int ret; |
2298 | ||
0bc40be8 | 2299 | WARN_ON(engine->buffer); |
bfc882b4 | 2300 | |
0bc40be8 TU |
2301 | engine->dev = dev; |
2302 | INIT_LIST_HEAD(&engine->active_list); | |
2303 | INIT_LIST_HEAD(&engine->request_list); | |
2304 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2305 | INIT_LIST_HEAD(&engine->buffers); | |
2306 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2307 | memset(engine->semaphore.sync_seqno, 0, | |
2308 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2309 | |
0bc40be8 | 2310 | init_waitqueue_head(&engine->irq_queue); |
e3efda49 | 2311 | |
0bc40be8 | 2312 | ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); |
b0366a54 DG |
2313 | if (IS_ERR(ringbuf)) { |
2314 | ret = PTR_ERR(ringbuf); | |
2315 | goto error; | |
2316 | } | |
0bc40be8 | 2317 | engine->buffer = ringbuf; |
01101fa7 | 2318 | |
e3efda49 | 2319 | if (I915_NEED_GFX_HWS(dev)) { |
0bc40be8 | 2320 | ret = init_status_page(engine); |
e3efda49 | 2321 | if (ret) |
8ee14975 | 2322 | goto error; |
e3efda49 | 2323 | } else { |
0bc40be8 TU |
2324 | WARN_ON(engine->id != RCS); |
2325 | ret = init_phys_status_page(engine); | |
e3efda49 | 2326 | if (ret) |
8ee14975 | 2327 | goto error; |
e3efda49 CW |
2328 | } |
2329 | ||
bfc882b4 DV |
2330 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); |
2331 | if (ret) { | |
2332 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2333 | engine->name, ret); |
bfc882b4 DV |
2334 | intel_destroy_ringbuffer_obj(ringbuf); |
2335 | goto error; | |
e3efda49 | 2336 | } |
62fdfeaf | 2337 | |
0bc40be8 | 2338 | ret = i915_cmd_parser_init_ring(engine); |
44e895a8 | 2339 | if (ret) |
8ee14975 OM |
2340 | goto error; |
2341 | ||
8ee14975 | 2342 | return 0; |
351e3db2 | 2343 | |
8ee14975 | 2344 | error: |
117897f4 | 2345 | intel_cleanup_engine(engine); |
8ee14975 | 2346 | return ret; |
62fdfeaf EA |
2347 | } |
2348 | ||
117897f4 | 2349 | void intel_cleanup_engine(struct intel_engine_cs *engine) |
62fdfeaf | 2350 | { |
6402c330 | 2351 | struct drm_i915_private *dev_priv; |
33626e6a | 2352 | |
117897f4 | 2353 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2354 | return; |
2355 | ||
0bc40be8 | 2356 | dev_priv = to_i915(engine->dev); |
6402c330 | 2357 | |
0bc40be8 | 2358 | if (engine->buffer) { |
117897f4 | 2359 | intel_stop_engine(engine); |
0bc40be8 | 2360 | WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); |
33626e6a | 2361 | |
0bc40be8 TU |
2362 | intel_unpin_ringbuffer_obj(engine->buffer); |
2363 | intel_ringbuffer_free(engine->buffer); | |
2364 | engine->buffer = NULL; | |
b0366a54 | 2365 | } |
78501eac | 2366 | |
0bc40be8 TU |
2367 | if (engine->cleanup) |
2368 | engine->cleanup(engine); | |
8d19215b | 2369 | |
0bc40be8 TU |
2370 | if (I915_NEED_GFX_HWS(engine->dev)) { |
2371 | cleanup_status_page(engine); | |
7d3fdfff | 2372 | } else { |
0bc40be8 TU |
2373 | WARN_ON(engine->id != RCS); |
2374 | cleanup_phys_status_page(engine); | |
7d3fdfff | 2375 | } |
44e895a8 | 2376 | |
0bc40be8 TU |
2377 | i915_cmd_parser_fini_ring(engine); |
2378 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
2379 | engine->dev = NULL; | |
62fdfeaf EA |
2380 | } |
2381 | ||
666796da | 2382 | int intel_engine_idle(struct intel_engine_cs *engine) |
3e960501 | 2383 | { |
a4b3a571 | 2384 | struct drm_i915_gem_request *req; |
3e960501 | 2385 | |
3e960501 | 2386 | /* Wait upon the last request to be completed */ |
0bc40be8 | 2387 | if (list_empty(&engine->request_list)) |
3e960501 CW |
2388 | return 0; |
2389 | ||
0bc40be8 TU |
2390 | req = list_entry(engine->request_list.prev, |
2391 | struct drm_i915_gem_request, | |
2392 | list); | |
b4716185 CW |
2393 | |
2394 | /* Make sure we do not trigger any retires */ | |
2395 | return __i915_wait_request(req, | |
c19ae989 | 2396 | req->i915->mm.interruptible, |
b4716185 | 2397 | NULL, NULL); |
3e960501 CW |
2398 | } |
2399 | ||
6689cb2b | 2400 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2401 | { |
4a570db5 | 2402 | request->ringbuf = request->engine->buffer; |
9eba5d4a | 2403 | return 0; |
9d773091 CW |
2404 | } |
2405 | ||
ccd98fe4 JH |
2406 | int intel_ring_reserve_space(struct drm_i915_gem_request *request) |
2407 | { | |
2408 | /* | |
2409 | * The first call merely notes the reserve request and is common for | |
2410 | * all back ends. The subsequent localised _begin() call actually | |
2411 | * ensures that the reservation is available. Without the begin, if | |
2412 | * the request creator immediately submitted the request without | |
2413 | * adding any commands to it then there might not actually be | |
2414 | * sufficient room for the submission commands. | |
2415 | */ | |
2416 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
2417 | ||
2418 | return intel_ring_begin(request, 0); | |
2419 | } | |
2420 | ||
29b1b415 JH |
2421 | void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size) |
2422 | { | |
92dcc67c | 2423 | GEM_BUG_ON(ringbuf->reserved_size); |
29b1b415 | 2424 | ringbuf->reserved_size = size; |
29b1b415 JH |
2425 | } |
2426 | ||
2427 | void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf) | |
2428 | { | |
92dcc67c | 2429 | GEM_BUG_ON(!ringbuf->reserved_size); |
29b1b415 | 2430 | ringbuf->reserved_size = 0; |
29b1b415 JH |
2431 | } |
2432 | ||
2433 | void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf) | |
2434 | { | |
92dcc67c CW |
2435 | GEM_BUG_ON(!ringbuf->reserved_size); |
2436 | ringbuf->reserved_size = 0; | |
29b1b415 JH |
2437 | } |
2438 | ||
2439 | void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf) | |
2440 | { | |
92dcc67c CW |
2441 | GEM_BUG_ON(ringbuf->reserved_size); |
2442 | } | |
2443 | ||
2444 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) | |
2445 | { | |
2446 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
2447 | struct intel_engine_cs *engine = req->engine; | |
2448 | struct drm_i915_gem_request *target; | |
2449 | ||
2450 | intel_ring_update_space(ringbuf); | |
2451 | if (ringbuf->space >= bytes) | |
2452 | return 0; | |
2453 | ||
2454 | /* | |
2455 | * Space is reserved in the ringbuffer for finalising the request, | |
2456 | * as that cannot be allowed to fail. During request finalisation, | |
2457 | * reserved_space is set to 0 to stop the overallocation and the | |
2458 | * assumption is that then we never need to wait (which has the | |
2459 | * risk of failing with EINTR). | |
2460 | * | |
2461 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2462 | */ | |
2463 | GEM_BUG_ON(!ringbuf->reserved_size); | |
2464 | ||
2465 | list_for_each_entry(target, &engine->request_list, list) { | |
2466 | unsigned space; | |
2467 | ||
79bbcc29 | 2468 | /* |
92dcc67c CW |
2469 | * The request queue is per-engine, so can contain requests |
2470 | * from multiple ringbuffers. Here, we must ignore any that | |
2471 | * aren't from the ringbuffer we're considering. | |
79bbcc29 | 2472 | */ |
92dcc67c CW |
2473 | if (target->ringbuf != ringbuf) |
2474 | continue; | |
2475 | ||
2476 | /* Would completion of this request free enough space? */ | |
2477 | space = __intel_ring_space(target->postfix, ringbuf->tail, | |
2478 | ringbuf->size); | |
2479 | if (space >= bytes) | |
2480 | break; | |
79bbcc29 | 2481 | } |
29b1b415 | 2482 | |
92dcc67c CW |
2483 | if (WARN_ON(&target->list == &engine->request_list)) |
2484 | return -ENOSPC; | |
2485 | ||
2486 | return i915_wait_request(target); | |
29b1b415 JH |
2487 | } |
2488 | ||
92dcc67c | 2489 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2490 | { |
92dcc67c | 2491 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 | 2492 | int remain_actual = ringbuf->size - ringbuf->tail; |
92dcc67c CW |
2493 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
2494 | int bytes = num_dwords * sizeof(u32); | |
2495 | int total_bytes, wait_bytes; | |
79bbcc29 | 2496 | bool need_wrap = false; |
29b1b415 | 2497 | |
92dcc67c | 2498 | total_bytes = bytes + ringbuf->reserved_size; |
29b1b415 | 2499 | |
79bbcc29 JH |
2500 | if (unlikely(bytes > remain_usable)) { |
2501 | /* | |
2502 | * Not enough space for the basic request. So need to flush | |
2503 | * out the remainder and then wait for base + reserved. | |
2504 | */ | |
2505 | wait_bytes = remain_actual + total_bytes; | |
2506 | need_wrap = true; | |
92dcc67c CW |
2507 | } else if (unlikely(total_bytes > remain_usable)) { |
2508 | /* | |
2509 | * The base request will fit but the reserved space | |
2510 | * falls off the end. So we don't need an immediate wrap | |
2511 | * and only need to effectively wait for the reserved | |
2512 | * size space from the start of ringbuffer. | |
2513 | */ | |
2514 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
79bbcc29 | 2515 | } else { |
92dcc67c CW |
2516 | /* No wrapping required, just waiting. */ |
2517 | wait_bytes = total_bytes; | |
cbcc80df MK |
2518 | } |
2519 | ||
92dcc67c CW |
2520 | if (wait_bytes > ringbuf->space) { |
2521 | int ret = wait_for_space(req, wait_bytes); | |
cbcc80df MK |
2522 | if (unlikely(ret)) |
2523 | return ret; | |
79bbcc29 | 2524 | |
92dcc67c | 2525 | intel_ring_update_space(ringbuf); |
157d2c7f CW |
2526 | if (unlikely(ringbuf->space < wait_bytes)) |
2527 | return -EAGAIN; | |
cbcc80df MK |
2528 | } |
2529 | ||
92dcc67c CW |
2530 | if (unlikely(need_wrap)) { |
2531 | GEM_BUG_ON(remain_actual > ringbuf->space); | |
2532 | GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size); | |
78501eac | 2533 | |
92dcc67c CW |
2534 | /* Fill the tail with MI_NOOP */ |
2535 | memset(ringbuf->virtual_start + ringbuf->tail, | |
2536 | 0, remain_actual); | |
2537 | ringbuf->tail = 0; | |
2538 | ringbuf->space -= remain_actual; | |
2539 | } | |
304d695c | 2540 | |
92dcc67c CW |
2541 | ringbuf->space -= bytes; |
2542 | GEM_BUG_ON(ringbuf->space < 0); | |
304d695c | 2543 | return 0; |
8187a2b7 | 2544 | } |
78501eac | 2545 | |
753b1ad4 | 2546 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2547 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2548 | { |
4a570db5 | 2549 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2550 | int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2551 | int ret; |
2552 | ||
2553 | if (num_dwords == 0) | |
2554 | return 0; | |
2555 | ||
18393f63 | 2556 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2557 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2558 | if (ret) |
2559 | return ret; | |
2560 | ||
2561 | while (num_dwords--) | |
e2f80391 | 2562 | intel_ring_emit(engine, MI_NOOP); |
753b1ad4 | 2563 | |
e2f80391 | 2564 | intel_ring_advance(engine); |
753b1ad4 VS |
2565 | |
2566 | return 0; | |
2567 | } | |
2568 | ||
0bc40be8 | 2569 | void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) |
498d2ac1 | 2570 | { |
d04bce48 | 2571 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
498d2ac1 | 2572 | |
29dcb570 CW |
2573 | /* Our semaphore implementation is strictly monotonic (i.e. we proceed |
2574 | * so long as the semaphore value in the register/page is greater | |
2575 | * than the sync value), so whenever we reset the seqno, | |
2576 | * so long as we reset the tracking semaphore value to 0, it will | |
2577 | * always be before the next request's seqno. If we don't reset | |
2578 | * the semaphore value, then when the seqno moves backwards all | |
2579 | * future waits will complete instantly (causing rendering corruption). | |
2580 | */ | |
d04bce48 | 2581 | if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { |
0bc40be8 TU |
2582 | I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); |
2583 | I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); | |
d04bce48 | 2584 | if (HAS_VEBOX(dev_priv)) |
0bc40be8 | 2585 | I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); |
e1f99ce6 | 2586 | } |
a058d934 CW |
2587 | if (dev_priv->semaphore_obj) { |
2588 | struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; | |
2589 | struct page *page = i915_gem_object_get_dirty_page(obj, 0); | |
2590 | void *semaphores = kmap(page); | |
2591 | memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), | |
2592 | 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); | |
2593 | kunmap(page); | |
2594 | } | |
29dcb570 CW |
2595 | memset(engine->semaphore.sync_seqno, 0, |
2596 | sizeof(engine->semaphore.sync_seqno)); | |
d97ed339 | 2597 | |
0bc40be8 | 2598 | engine->set_seqno(engine, seqno); |
01347126 | 2599 | engine->last_submitted_seqno = seqno; |
29dcb570 | 2600 | |
0bc40be8 | 2601 | engine->hangcheck.seqno = seqno; |
8187a2b7 | 2602 | } |
62fdfeaf | 2603 | |
0bc40be8 | 2604 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, |
297b0c5b | 2605 | u32 value) |
881f47b6 | 2606 | { |
0bc40be8 | 2607 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
881f47b6 XH |
2608 | |
2609 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2610 | |
2611 | /* Disable notification that the ring is IDLE. The GT | |
2612 | * will then assume that it is busy and bring it out of rc6. | |
2613 | */ | |
0206e353 | 2614 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2615 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2616 | ||
2617 | /* Clear the context id. Here be magic! */ | |
2618 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2619 | |
12f55818 | 2620 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2621 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2622 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2623 | 50)) | |
2624 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2625 | |
12f55818 | 2626 | /* Now that the ring is fully powered up, update the tail */ |
0bc40be8 TU |
2627 | I915_WRITE_TAIL(engine, value); |
2628 | POSTING_READ(RING_TAIL(engine->mmio_base)); | |
12f55818 CW |
2629 | |
2630 | /* Let the ring send IDLE messages to the GT again, | |
2631 | * and so let it sleep to conserve power when idle. | |
2632 | */ | |
0206e353 | 2633 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2634 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2635 | } |
2636 | ||
a84c3ae1 | 2637 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2638 | u32 invalidate, u32 flush) |
881f47b6 | 2639 | { |
4a570db5 | 2640 | struct intel_engine_cs *engine = req->engine; |
71a77e07 | 2641 | uint32_t cmd; |
b72f3acb CW |
2642 | int ret; |
2643 | ||
5fb9de1a | 2644 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2645 | if (ret) |
2646 | return ret; | |
2647 | ||
71a77e07 | 2648 | cmd = MI_FLUSH_DW; |
e2f80391 | 2649 | if (INTEL_INFO(engine->dev)->gen >= 8) |
075b3bba | 2650 | cmd += 1; |
f0a1fb10 CW |
2651 | |
2652 | /* We always require a command barrier so that subsequent | |
2653 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2654 | * wrt the contents of the write cache being flushed to memory | |
2655 | * (and thus being coherent from the CPU). | |
2656 | */ | |
2657 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2658 | ||
9a289771 JB |
2659 | /* |
2660 | * Bspec vol 1c.5 - video engine command streamer: | |
2661 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2662 | * operation is complete. This bit is only valid when the | |
2663 | * Post-Sync Operation field is a value of 1h or 3h." | |
2664 | */ | |
71a77e07 | 2665 | if (invalidate & I915_GEM_GPU_DOMAINS) |
f0a1fb10 CW |
2666 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2667 | ||
e2f80391 TU |
2668 | intel_ring_emit(engine, cmd); |
2669 | intel_ring_emit(engine, | |
2670 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
2671 | if (INTEL_INFO(engine->dev)->gen >= 8) { | |
2672 | intel_ring_emit(engine, 0); /* upper addr */ | |
2673 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2674 | } else { |
e2f80391 TU |
2675 | intel_ring_emit(engine, 0); |
2676 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2677 | } |
e2f80391 | 2678 | intel_ring_advance(engine); |
b72f3acb | 2679 | return 0; |
881f47b6 XH |
2680 | } |
2681 | ||
1c7a0623 | 2682 | static int |
53fddaf7 | 2683 | gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2684 | u64 offset, u32 len, |
8e004efc | 2685 | unsigned dispatch_flags) |
1c7a0623 | 2686 | { |
4a570db5 | 2687 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2688 | bool ppgtt = USES_PPGTT(engine->dev) && |
8e004efc | 2689 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2690 | int ret; |
2691 | ||
5fb9de1a | 2692 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2693 | if (ret) |
2694 | return ret; | |
2695 | ||
2696 | /* FIXME(BDW): Address space and security selectors. */ | |
e2f80391 | 2697 | intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2698 | (dispatch_flags & I915_DISPATCH_RS ? |
2699 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
e2f80391 TU |
2700 | intel_ring_emit(engine, lower_32_bits(offset)); |
2701 | intel_ring_emit(engine, upper_32_bits(offset)); | |
2702 | intel_ring_emit(engine, MI_NOOP); | |
2703 | intel_ring_advance(engine); | |
1c7a0623 BW |
2704 | |
2705 | return 0; | |
2706 | } | |
2707 | ||
d7d4eedd | 2708 | static int |
53fddaf7 | 2709 | hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
8e004efc JH |
2710 | u64 offset, u32 len, |
2711 | unsigned dispatch_flags) | |
d7d4eedd | 2712 | { |
4a570db5 | 2713 | struct intel_engine_cs *engine = req->engine; |
d7d4eedd CW |
2714 | int ret; |
2715 | ||
5fb9de1a | 2716 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2717 | if (ret) |
2718 | return ret; | |
2719 | ||
e2f80391 | 2720 | intel_ring_emit(engine, |
77072258 | 2721 | MI_BATCH_BUFFER_START | |
8e004efc | 2722 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2723 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2724 | (dispatch_flags & I915_DISPATCH_RS ? | |
2725 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2726 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2727 | intel_ring_emit(engine, offset); |
2728 | intel_ring_advance(engine); | |
d7d4eedd CW |
2729 | |
2730 | return 0; | |
2731 | } | |
2732 | ||
881f47b6 | 2733 | static int |
53fddaf7 | 2734 | gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req, |
9bcb144c | 2735 | u64 offset, u32 len, |
8e004efc | 2736 | unsigned dispatch_flags) |
881f47b6 | 2737 | { |
4a570db5 | 2738 | struct intel_engine_cs *engine = req->engine; |
0206e353 | 2739 | int ret; |
ab6f8e32 | 2740 | |
5fb9de1a | 2741 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2742 | if (ret) |
2743 | return ret; | |
e1f99ce6 | 2744 | |
e2f80391 | 2745 | intel_ring_emit(engine, |
d7d4eedd | 2746 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2747 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2748 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2749 | /* bit0-7 is the length on GEN6+ */ |
e2f80391 TU |
2750 | intel_ring_emit(engine, offset); |
2751 | intel_ring_advance(engine); | |
ab6f8e32 | 2752 | |
0206e353 | 2753 | return 0; |
881f47b6 XH |
2754 | } |
2755 | ||
549f7365 CW |
2756 | /* Blitter support (SandyBridge+) */ |
2757 | ||
a84c3ae1 | 2758 | static int gen6_ring_flush(struct drm_i915_gem_request *req, |
ea251324 | 2759 | u32 invalidate, u32 flush) |
8d19215b | 2760 | { |
4a570db5 | 2761 | struct intel_engine_cs *engine = req->engine; |
e2f80391 | 2762 | struct drm_device *dev = engine->dev; |
71a77e07 | 2763 | uint32_t cmd; |
b72f3acb CW |
2764 | int ret; |
2765 | ||
5fb9de1a | 2766 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2767 | if (ret) |
2768 | return ret; | |
2769 | ||
71a77e07 | 2770 | cmd = MI_FLUSH_DW; |
dbef0f15 | 2771 | if (INTEL_INFO(dev)->gen >= 8) |
075b3bba | 2772 | cmd += 1; |
f0a1fb10 CW |
2773 | |
2774 | /* We always require a command barrier so that subsequent | |
2775 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2776 | * wrt the contents of the write cache being flushed to memory | |
2777 | * (and thus being coherent from the CPU). | |
2778 | */ | |
2779 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2780 | ||
9a289771 JB |
2781 | /* |
2782 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2783 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2784 | * operation is complete. This bit is only valid when the | |
2785 | * Post-Sync Operation field is a value of 1h or 3h." | |
2786 | */ | |
71a77e07 | 2787 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
f0a1fb10 | 2788 | cmd |= MI_INVALIDATE_TLB; |
e2f80391 TU |
2789 | intel_ring_emit(engine, cmd); |
2790 | intel_ring_emit(engine, | |
2791 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
dbef0f15 | 2792 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 TU |
2793 | intel_ring_emit(engine, 0); /* upper addr */ |
2794 | intel_ring_emit(engine, 0); /* value */ | |
075b3bba | 2795 | } else { |
e2f80391 TU |
2796 | intel_ring_emit(engine, 0); |
2797 | intel_ring_emit(engine, MI_NOOP); | |
075b3bba | 2798 | } |
e2f80391 | 2799 | intel_ring_advance(engine); |
fd3da6c9 | 2800 | |
b72f3acb | 2801 | return 0; |
8d19215b ZN |
2802 | } |
2803 | ||
5c1143bb XH |
2804 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2805 | { | |
4640c4ff | 2806 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2807 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
3e78998a BW |
2808 | struct drm_i915_gem_object *obj; |
2809 | int ret; | |
5c1143bb | 2810 | |
e2f80391 TU |
2811 | engine->name = "render ring"; |
2812 | engine->id = RCS; | |
2813 | engine->exec_id = I915_EXEC_RENDER; | |
83e53802 | 2814 | engine->hw_id = 0; |
e2f80391 | 2815 | engine->mmio_base = RENDER_RING_BASE; |
59465b5f | 2816 | |
707d9cf9 | 2817 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2818 | if (i915_semaphore_is_enabled(dev)) { |
2819 | obj = i915_gem_alloc_object(dev, 4096); | |
2820 | if (obj == NULL) { | |
2821 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2822 | i915.semaphores = 0; | |
2823 | } else { | |
2824 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2825 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2826 | if (ret != 0) { | |
2827 | drm_gem_object_unreference(&obj->base); | |
2828 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2829 | i915.semaphores = 0; | |
2830 | } else | |
2831 | dev_priv->semaphore_obj = obj; | |
2832 | } | |
2833 | } | |
7225342a | 2834 | |
e2f80391 TU |
2835 | engine->init_context = intel_rcs_ctx_init; |
2836 | engine->add_request = gen6_add_request; | |
2837 | engine->flush = gen8_render_ring_flush; | |
2838 | engine->irq_get = gen8_ring_get_irq; | |
2839 | engine->irq_put = gen8_ring_put_irq; | |
2840 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2841 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2842 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2843 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2844 | if (i915_semaphore_is_enabled(dev)) { |
3e78998a | 2845 | WARN_ON(!dev_priv->semaphore_obj); |
e2f80391 TU |
2846 | engine->semaphore.sync_to = gen8_ring_sync; |
2847 | engine->semaphore.signal = gen8_rcs_signal; | |
2848 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 BW |
2849 | } |
2850 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
e2f80391 TU |
2851 | engine->init_context = intel_rcs_ctx_init; |
2852 | engine->add_request = gen6_add_request; | |
2853 | engine->flush = gen7_render_ring_flush; | |
6c6cf5aa | 2854 | if (INTEL_INFO(dev)->gen == 6) |
e2f80391 TU |
2855 | engine->flush = gen6_render_ring_flush; |
2856 | engine->irq_get = gen6_ring_get_irq; | |
2857 | engine->irq_put = gen6_ring_put_irq; | |
2858 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
c04e0f3b CW |
2859 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2860 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2861 | engine->set_seqno = ring_set_seqno; |
707d9cf9 | 2862 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2863 | engine->semaphore.sync_to = gen6_ring_sync; |
2864 | engine->semaphore.signal = gen6_signal; | |
707d9cf9 BW |
2865 | /* |
2866 | * The current semaphore is only applied on pre-gen8 | |
2867 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2868 | * platform. So the semaphore between RCS and VCS2 is | |
2869 | * initialized as INVALID. Gen8 will initialize the | |
2870 | * sema between VCS2 and RCS later. | |
2871 | */ | |
e2f80391 TU |
2872 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2873 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2874 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2875 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2876 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2877 | engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2878 | engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2879 | engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2880 | engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2881 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 2882 | } |
c6df541c | 2883 | } else if (IS_GEN5(dev)) { |
e2f80391 TU |
2884 | engine->add_request = pc_render_add_request; |
2885 | engine->flush = gen4_render_ring_flush; | |
2886 | engine->get_seqno = pc_render_get_seqno; | |
2887 | engine->set_seqno = pc_render_set_seqno; | |
2888 | engine->irq_get = gen5_ring_get_irq; | |
2889 | engine->irq_put = gen5_ring_put_irq; | |
2890 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | | |
cc609d5d | 2891 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; |
59465b5f | 2892 | } else { |
e2f80391 | 2893 | engine->add_request = i9xx_add_request; |
46f0f8d1 | 2894 | if (INTEL_INFO(dev)->gen < 4) |
e2f80391 | 2895 | engine->flush = gen2_render_ring_flush; |
46f0f8d1 | 2896 | else |
e2f80391 TU |
2897 | engine->flush = gen4_render_ring_flush; |
2898 | engine->get_seqno = ring_get_seqno; | |
2899 | engine->set_seqno = ring_set_seqno; | |
c2798b19 | 2900 | if (IS_GEN2(dev)) { |
e2f80391 TU |
2901 | engine->irq_get = i8xx_ring_get_irq; |
2902 | engine->irq_put = i8xx_ring_put_irq; | |
c2798b19 | 2903 | } else { |
e2f80391 TU |
2904 | engine->irq_get = i9xx_ring_get_irq; |
2905 | engine->irq_put = i9xx_ring_put_irq; | |
c2798b19 | 2906 | } |
e2f80391 | 2907 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2908 | } |
e2f80391 | 2909 | engine->write_tail = ring_write_tail; |
707d9cf9 | 2910 | |
d7d4eedd | 2911 | if (IS_HASWELL(dev)) |
e2f80391 | 2912 | engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; |
1c7a0623 | 2913 | else if (IS_GEN8(dev)) |
e2f80391 | 2914 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
d7d4eedd | 2915 | else if (INTEL_INFO(dev)->gen >= 6) |
e2f80391 | 2916 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
fb3256da | 2917 | else if (INTEL_INFO(dev)->gen >= 4) |
e2f80391 | 2918 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
fb3256da | 2919 | else if (IS_I830(dev) || IS_845G(dev)) |
e2f80391 | 2920 | engine->dispatch_execbuffer = i830_dispatch_execbuffer; |
fb3256da | 2921 | else |
e2f80391 TU |
2922 | engine->dispatch_execbuffer = i915_dispatch_execbuffer; |
2923 | engine->init_hw = init_render_ring; | |
2924 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2925 | |
b45305fc DV |
2926 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2927 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2928 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2929 | if (obj == NULL) { |
2930 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2931 | return -ENOMEM; | |
2932 | } | |
2933 | ||
be1fa129 | 2934 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2935 | if (ret != 0) { |
2936 | drm_gem_object_unreference(&obj->base); | |
2937 | DRM_ERROR("Failed to ping batch bo\n"); | |
2938 | return ret; | |
2939 | } | |
2940 | ||
e2f80391 TU |
2941 | engine->scratch.obj = obj; |
2942 | engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2943 | } |
2944 | ||
e2f80391 | 2945 | ret = intel_init_ring_buffer(dev, engine); |
99be1dfe DV |
2946 | if (ret) |
2947 | return ret; | |
2948 | ||
2949 | if (INTEL_INFO(dev)->gen >= 5) { | |
e2f80391 | 2950 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2951 | if (ret) |
2952 | return ret; | |
2953 | } | |
2954 | ||
2955 | return 0; | |
5c1143bb XH |
2956 | } |
2957 | ||
2958 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2959 | { | |
4640c4ff | 2960 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 2961 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
5c1143bb | 2962 | |
e2f80391 TU |
2963 | engine->name = "bsd ring"; |
2964 | engine->id = VCS; | |
2965 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 2966 | engine->hw_id = 1; |
58fa3835 | 2967 | |
e2f80391 | 2968 | engine->write_tail = ring_write_tail; |
780f18c8 | 2969 | if (INTEL_INFO(dev)->gen >= 6) { |
e2f80391 | 2970 | engine->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2971 | /* gen6 bsd needs a special wa for tail updates */ |
2972 | if (IS_GEN6(dev)) | |
e2f80391 TU |
2973 | engine->write_tail = gen6_bsd_ring_write_tail; |
2974 | engine->flush = gen6_bsd_ring_flush; | |
2975 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
2976 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2977 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 2978 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 2979 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 2980 | engine->irq_enable_mask = |
abd58f01 | 2981 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; |
e2f80391 TU |
2982 | engine->irq_get = gen8_ring_get_irq; |
2983 | engine->irq_put = gen8_ring_put_irq; | |
2984 | engine->dispatch_execbuffer = | |
1c7a0623 | 2985 | gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2986 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2987 | engine->semaphore.sync_to = gen8_ring_sync; |
2988 | engine->semaphore.signal = gen8_xcs_signal; | |
2989 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 2990 | } |
abd58f01 | 2991 | } else { |
e2f80391 TU |
2992 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
2993 | engine->irq_get = gen6_ring_get_irq; | |
2994 | engine->irq_put = gen6_ring_put_irq; | |
2995 | engine->dispatch_execbuffer = | |
1c7a0623 | 2996 | gen6_ring_dispatch_execbuffer; |
707d9cf9 | 2997 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
2998 | engine->semaphore.sync_to = gen6_ring_sync; |
2999 | engine->semaphore.signal = gen6_signal; | |
3000 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
3001 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3002 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
3003 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
3004 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3005 | engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
3006 | engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
3007 | engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
3008 | engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
3009 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3010 | } |
abd58f01 | 3011 | } |
58fa3835 | 3012 | } else { |
e2f80391 TU |
3013 | engine->mmio_base = BSD_RING_BASE; |
3014 | engine->flush = bsd_ring_flush; | |
3015 | engine->add_request = i9xx_add_request; | |
3016 | engine->get_seqno = ring_get_seqno; | |
3017 | engine->set_seqno = ring_set_seqno; | |
e48d8634 | 3018 | if (IS_GEN5(dev)) { |
e2f80391 TU |
3019 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
3020 | engine->irq_get = gen5_ring_get_irq; | |
3021 | engine->irq_put = gen5_ring_put_irq; | |
e48d8634 | 3022 | } else { |
e2f80391 TU |
3023 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
3024 | engine->irq_get = i9xx_ring_get_irq; | |
3025 | engine->irq_put = i9xx_ring_put_irq; | |
e48d8634 | 3026 | } |
e2f80391 | 3027 | engine->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 3028 | } |
e2f80391 | 3029 | engine->init_hw = init_ring_common; |
58fa3835 | 3030 | |
e2f80391 | 3031 | return intel_init_ring_buffer(dev, engine); |
5c1143bb | 3032 | } |
549f7365 | 3033 | |
845f74a7 | 3034 | /** |
62659920 | 3035 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
3036 | */ |
3037 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
3038 | { | |
3039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 3040 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
e2f80391 TU |
3041 | |
3042 | engine->name = "bsd2 ring"; | |
3043 | engine->id = VCS2; | |
3044 | engine->exec_id = I915_EXEC_BSD; | |
83e53802 | 3045 | engine->hw_id = 4; |
e2f80391 TU |
3046 | |
3047 | engine->write_tail = ring_write_tail; | |
3048 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
3049 | engine->flush = gen6_bsd_ring_flush; | |
3050 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3051 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3052 | engine->get_seqno = ring_get_seqno; | |
e2f80391 TU |
3053 | engine->set_seqno = ring_set_seqno; |
3054 | engine->irq_enable_mask = | |
845f74a7 | 3055 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; |
e2f80391 TU |
3056 | engine->irq_get = gen8_ring_get_irq; |
3057 | engine->irq_put = gen8_ring_put_irq; | |
3058 | engine->dispatch_execbuffer = | |
845f74a7 | 3059 | gen8_ring_dispatch_execbuffer; |
3e78998a | 3060 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3061 | engine->semaphore.sync_to = gen8_ring_sync; |
3062 | engine->semaphore.signal = gen8_xcs_signal; | |
3063 | GEN8_RING_SEMAPHORE_INIT(engine); | |
3e78998a | 3064 | } |
e2f80391 | 3065 | engine->init_hw = init_ring_common; |
845f74a7 | 3066 | |
e2f80391 | 3067 | return intel_init_ring_buffer(dev, engine); |
845f74a7 ZY |
3068 | } |
3069 | ||
549f7365 CW |
3070 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
3071 | { | |
4640c4ff | 3072 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3073 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
e2f80391 TU |
3074 | |
3075 | engine->name = "blitter ring"; | |
3076 | engine->id = BCS; | |
3077 | engine->exec_id = I915_EXEC_BLT; | |
83e53802 | 3078 | engine->hw_id = 2; |
e2f80391 TU |
3079 | |
3080 | engine->mmio_base = BLT_RING_BASE; | |
3081 | engine->write_tail = ring_write_tail; | |
3082 | engine->flush = gen6_ring_flush; | |
3083 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3084 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3085 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3086 | engine->set_seqno = ring_set_seqno; |
abd58f01 | 3087 | if (INTEL_INFO(dev)->gen >= 8) { |
e2f80391 | 3088 | engine->irq_enable_mask = |
abd58f01 | 3089 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; |
e2f80391 TU |
3090 | engine->irq_get = gen8_ring_get_irq; |
3091 | engine->irq_put = gen8_ring_put_irq; | |
3092 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3093 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3094 | engine->semaphore.sync_to = gen8_ring_sync; |
3095 | engine->semaphore.signal = gen8_xcs_signal; | |
3096 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3097 | } |
abd58f01 | 3098 | } else { |
e2f80391 TU |
3099 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3100 | engine->irq_get = gen6_ring_get_irq; | |
3101 | engine->irq_put = gen6_ring_put_irq; | |
3102 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3103 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3104 | engine->semaphore.signal = gen6_signal; |
3105 | engine->semaphore.sync_to = gen6_ring_sync; | |
707d9cf9 BW |
3106 | /* |
3107 | * The current semaphore is only applied on pre-gen8 | |
3108 | * platform. And there is no VCS2 ring on the pre-gen8 | |
3109 | * platform. So the semaphore between BCS and VCS2 is | |
3110 | * initialized as INVALID. Gen8 will initialize the | |
3111 | * sema between BCS and VCS2 later. | |
3112 | */ | |
e2f80391 TU |
3113 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
3114 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
3115 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
3116 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
3117 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3118 | engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
3119 | engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
3120 | engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
3121 | engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
3122 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3123 | } |
abd58f01 | 3124 | } |
e2f80391 | 3125 | engine->init_hw = init_ring_common; |
549f7365 | 3126 | |
e2f80391 | 3127 | return intel_init_ring_buffer(dev, engine); |
549f7365 | 3128 | } |
a7b9761d | 3129 | |
9a8a2213 BW |
3130 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
3131 | { | |
4640c4ff | 3132 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a570db5 | 3133 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
9a8a2213 | 3134 | |
e2f80391 TU |
3135 | engine->name = "video enhancement ring"; |
3136 | engine->id = VECS; | |
3137 | engine->exec_id = I915_EXEC_VEBOX; | |
83e53802 | 3138 | engine->hw_id = 3; |
9a8a2213 | 3139 | |
e2f80391 TU |
3140 | engine->mmio_base = VEBOX_RING_BASE; |
3141 | engine->write_tail = ring_write_tail; | |
3142 | engine->flush = gen6_ring_flush; | |
3143 | engine->add_request = gen6_add_request; | |
c04e0f3b CW |
3144 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
3145 | engine->get_seqno = ring_get_seqno; | |
e2f80391 | 3146 | engine->set_seqno = ring_set_seqno; |
abd58f01 BW |
3147 | |
3148 | if (INTEL_INFO(dev)->gen >= 8) { | |
e2f80391 | 3149 | engine->irq_enable_mask = |
40c499f9 | 3150 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
e2f80391 TU |
3151 | engine->irq_get = gen8_ring_get_irq; |
3152 | engine->irq_put = gen8_ring_put_irq; | |
3153 | engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 3154 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3155 | engine->semaphore.sync_to = gen8_ring_sync; |
3156 | engine->semaphore.signal = gen8_xcs_signal; | |
3157 | GEN8_RING_SEMAPHORE_INIT(engine); | |
707d9cf9 | 3158 | } |
abd58f01 | 3159 | } else { |
e2f80391 TU |
3160 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
3161 | engine->irq_get = hsw_vebox_get_irq; | |
3162 | engine->irq_put = hsw_vebox_put_irq; | |
3163 | engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
707d9cf9 | 3164 | if (i915_semaphore_is_enabled(dev)) { |
e2f80391 TU |
3165 | engine->semaphore.sync_to = gen6_ring_sync; |
3166 | engine->semaphore.signal = gen6_signal; | |
3167 | engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
3168 | engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
3169 | engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
3170 | engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
3171 | engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
3172 | engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
3173 | engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
3174 | engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
3175 | engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
3176 | engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
707d9cf9 | 3177 | } |
abd58f01 | 3178 | } |
e2f80391 | 3179 | engine->init_hw = init_ring_common; |
9a8a2213 | 3180 | |
e2f80391 | 3181 | return intel_init_ring_buffer(dev, engine); |
9a8a2213 BW |
3182 | } |
3183 | ||
a7b9761d | 3184 | int |
4866d729 | 3185 | intel_ring_flush_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3186 | { |
4a570db5 | 3187 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3188 | int ret; |
3189 | ||
e2f80391 | 3190 | if (!engine->gpu_caches_dirty) |
a7b9761d CW |
3191 | return 0; |
3192 | ||
e2f80391 | 3193 | ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d CW |
3194 | if (ret) |
3195 | return ret; | |
3196 | ||
a84c3ae1 | 3197 | trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS); |
a7b9761d | 3198 | |
e2f80391 | 3199 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3200 | return 0; |
3201 | } | |
3202 | ||
3203 | int | |
2f20055d | 3204 | intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
a7b9761d | 3205 | { |
4a570db5 | 3206 | struct intel_engine_cs *engine = req->engine; |
a7b9761d CW |
3207 | uint32_t flush_domains; |
3208 | int ret; | |
3209 | ||
3210 | flush_domains = 0; | |
e2f80391 | 3211 | if (engine->gpu_caches_dirty) |
a7b9761d CW |
3212 | flush_domains = I915_GEM_GPU_DOMAINS; |
3213 | ||
e2f80391 | 3214 | ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d CW |
3215 | if (ret) |
3216 | return ret; | |
3217 | ||
a84c3ae1 | 3218 | trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
a7b9761d | 3219 | |
e2f80391 | 3220 | engine->gpu_caches_dirty = false; |
a7b9761d CW |
3221 | return 0; |
3222 | } | |
e3efda49 CW |
3223 | |
3224 | void | |
117897f4 | 3225 | intel_stop_engine(struct intel_engine_cs *engine) |
e3efda49 CW |
3226 | { |
3227 | int ret; | |
3228 | ||
117897f4 | 3229 | if (!intel_engine_initialized(engine)) |
e3efda49 CW |
3230 | return; |
3231 | ||
666796da | 3232 | ret = intel_engine_idle(engine); |
f4457ae7 | 3233 | if (ret) |
e3efda49 | 3234 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 3235 | engine->name, ret); |
e3efda49 | 3236 | |
0bc40be8 | 3237 | stop_ring(engine); |
e3efda49 | 3238 | } |