]>
Commit | Line | Data |
---|---|---|
62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
605d5b32 CW |
42 | static unsigned int __intel_ring_space(unsigned int head, |
43 | unsigned int tail, | |
44 | unsigned int size) | |
c7dca47b | 45 | { |
605d5b32 CW |
46 | /* |
47 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
48 | * same cacheline, the Head Pointer must not be greater than the Tail | |
49 | * Pointer." | |
50 | */ | |
51 | GEM_BUG_ON(!is_power_of_2(size)); | |
52 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
53 | } |
54 | ||
95aebcb2 | 55 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 56 | { |
95aebcb2 CW |
57 | unsigned int space; |
58 | ||
59 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
60 | ||
61 | ring->space = space; | |
62 | return space; | |
ebd0fd4b DG |
63 | } |
64 | ||
b72f3acb | 65 | static int |
7c9cf4e3 | 66 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 67 | { |
73dec95e | 68 | u32 cmd, *cs; |
46f0f8d1 CW |
69 | |
70 | cmd = MI_FLUSH; | |
46f0f8d1 | 71 | |
7c9cf4e3 | 72 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
73 | cmd |= MI_READ_FLUSH; |
74 | ||
73dec95e TU |
75 | cs = intel_ring_begin(req, 2); |
76 | if (IS_ERR(cs)) | |
77 | return PTR_ERR(cs); | |
46f0f8d1 | 78 | |
73dec95e TU |
79 | *cs++ = cmd; |
80 | *cs++ = MI_NOOP; | |
81 | intel_ring_advance(req, cs); | |
46f0f8d1 CW |
82 | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static int | |
7c9cf4e3 | 87 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 88 | { |
73dec95e | 89 | u32 cmd, *cs; |
6f392d54 | 90 | |
36d527de CW |
91 | /* |
92 | * read/write caches: | |
93 | * | |
94 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
95 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
96 | * also flushed at 2d versus 3d pipeline switches. | |
97 | * | |
98 | * read-only caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
101 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
102 | * | |
103 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
104 | * | |
105 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
106 | * invalidated when MI_EXE_FLUSH is set. | |
107 | * | |
108 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
109 | * invalidated with every MI_FLUSH. | |
110 | * | |
111 | * TLBs: | |
112 | * | |
113 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
114 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
115 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
116 | * are flushed at any MI_FLUSH. | |
117 | */ | |
118 | ||
b5321f30 | 119 | cmd = MI_FLUSH; |
7c9cf4e3 | 120 | if (mode & EMIT_INVALIDATE) { |
36d527de | 121 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
122 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
123 | cmd |= MI_INVALIDATE_ISP; | |
124 | } | |
70eac33e | 125 | |
73dec95e TU |
126 | cs = intel_ring_begin(req, 2); |
127 | if (IS_ERR(cs)) | |
128 | return PTR_ERR(cs); | |
b72f3acb | 129 | |
73dec95e TU |
130 | *cs++ = cmd; |
131 | *cs++ = MI_NOOP; | |
132 | intel_ring_advance(req, cs); | |
b72f3acb CW |
133 | |
134 | return 0; | |
8187a2b7 ZN |
135 | } |
136 | ||
8d315287 JB |
137 | /** |
138 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
139 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
140 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
141 | * | |
142 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
143 | * produced by non-pipelined state commands), software needs to first | |
144 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
145 | * 0. | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
148 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
149 | * | |
150 | * And the workaround for these two requires this workaround first: | |
151 | * | |
152 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
153 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
154 | * flushes. | |
155 | * | |
156 | * And this last workaround is tricky because of the requirements on | |
157 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
158 | * volume 2 part 1: | |
159 | * | |
160 | * "1 of the following must also be set: | |
161 | * - Render Target Cache Flush Enable ([12] of DW1) | |
162 | * - Depth Cache Flush Enable ([0] of DW1) | |
163 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
164 | * - Depth Stall ([13] of DW1) | |
165 | * - Post-Sync Operation ([13] of DW1) | |
166 | * - Notify Enable ([8] of DW1)" | |
167 | * | |
168 | * The cache flushes require the workaround flush that triggered this | |
169 | * one, so we can't use it. Depth stall would trigger the same. | |
170 | * Post-sync nonzero is what triggered this second workaround, so we | |
171 | * can't use that one either. Notify enable is IRQs, which aren't | |
172 | * really our business. That leaves only stall at scoreboard. | |
173 | */ | |
174 | static int | |
f2cf1fcc | 175 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 176 | { |
b5321f30 | 177 | u32 scratch_addr = |
bde13ebd | 178 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
179 | u32 *cs; |
180 | ||
181 | cs = intel_ring_begin(req, 6); | |
182 | if (IS_ERR(cs)) | |
183 | return PTR_ERR(cs); | |
184 | ||
185 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
186 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
187 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
188 | *cs++ = 0; /* low dword */ | |
189 | *cs++ = 0; /* high dword */ | |
190 | *cs++ = MI_NOOP; | |
191 | intel_ring_advance(req, cs); | |
192 | ||
193 | cs = intel_ring_begin(req, 6); | |
194 | if (IS_ERR(cs)) | |
195 | return PTR_ERR(cs); | |
196 | ||
197 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
198 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
199 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
200 | *cs++ = 0; | |
201 | *cs++ = 0; | |
202 | *cs++ = MI_NOOP; | |
203 | intel_ring_advance(req, cs); | |
8d315287 JB |
204 | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int | |
7c9cf4e3 | 209 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 210 | { |
b5321f30 | 211 | u32 scratch_addr = |
bde13ebd | 212 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 213 | u32 *cs, flags = 0; |
8d315287 JB |
214 | int ret; |
215 | ||
b3111509 | 216 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 217 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
218 | if (ret) |
219 | return ret; | |
220 | ||
8d315287 JB |
221 | /* Just flush everything. Experiments have shown that reducing the |
222 | * number of bits based on the write domains has little performance | |
223 | * impact. | |
224 | */ | |
7c9cf4e3 | 225 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
226 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
227 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
228 | /* | |
229 | * Ensure that any following seqno writes only happen | |
230 | * when the render cache is indeed flushed. | |
231 | */ | |
97f209bc | 232 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 233 | } |
7c9cf4e3 | 234 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
235 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
236 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
237 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
241 | /* | |
242 | * TLB invalidate requires a post-sync write. | |
243 | */ | |
3ac78313 | 244 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 245 | } |
8d315287 | 246 | |
73dec95e TU |
247 | cs = intel_ring_begin(req, 4); |
248 | if (IS_ERR(cs)) | |
249 | return PTR_ERR(cs); | |
8d315287 | 250 | |
73dec95e TU |
251 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
252 | *cs++ = flags; | |
253 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
254 | *cs++ = 0; | |
255 | intel_ring_advance(req, cs); | |
8d315287 JB |
256 | |
257 | return 0; | |
258 | } | |
259 | ||
f3987631 | 260 | static int |
f2cf1fcc | 261 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 262 | { |
73dec95e | 263 | u32 *cs; |
f3987631 | 264 | |
73dec95e TU |
265 | cs = intel_ring_begin(req, 4); |
266 | if (IS_ERR(cs)) | |
267 | return PTR_ERR(cs); | |
f3987631 | 268 | |
73dec95e TU |
269 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
270 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
271 | *cs++ = 0; | |
272 | *cs++ = 0; | |
273 | intel_ring_advance(req, cs); | |
f3987631 PZ |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
4772eaeb | 278 | static int |
7c9cf4e3 | 279 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 280 | { |
b5321f30 | 281 | u32 scratch_addr = |
bde13ebd | 282 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 283 | u32 *cs, flags = 0; |
4772eaeb | 284 | |
f3987631 PZ |
285 | /* |
286 | * Ensure that any following seqno writes only happen when the render | |
287 | * cache is indeed flushed. | |
288 | * | |
289 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
290 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
291 | * don't try to be clever and just set it unconditionally. | |
292 | */ | |
293 | flags |= PIPE_CONTROL_CS_STALL; | |
294 | ||
4772eaeb PZ |
295 | /* Just flush everything. Experiments have shown that reducing the |
296 | * number of bits based on the write domains has little performance | |
297 | * impact. | |
298 | */ | |
7c9cf4e3 | 299 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
300 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
301 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 302 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 303 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 304 | } |
7c9cf4e3 | 305 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
306 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
307 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
308 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
309 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
310 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
311 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 312 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
313 | /* |
314 | * TLB invalidate requires a post-sync write. | |
315 | */ | |
316 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 317 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 318 | |
add284a3 CW |
319 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
320 | ||
f3987631 PZ |
321 | /* Workaround: we must issue a pipe_control with CS-stall bit |
322 | * set before a pipe_control command that has the state cache | |
323 | * invalidate bit set. */ | |
f2cf1fcc | 324 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
325 | } |
326 | ||
73dec95e TU |
327 | cs = intel_ring_begin(req, 4); |
328 | if (IS_ERR(cs)) | |
329 | return PTR_ERR(cs); | |
4772eaeb | 330 | |
73dec95e TU |
331 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
332 | *cs++ = flags; | |
333 | *cs++ = scratch_addr; | |
334 | *cs++ = 0; | |
335 | intel_ring_advance(req, cs); | |
4772eaeb PZ |
336 | |
337 | return 0; | |
338 | } | |
339 | ||
884ceace | 340 | static int |
9f235dfa | 341 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
884ceace | 342 | { |
9f235dfa | 343 | u32 flags; |
73dec95e | 344 | u32 *cs; |
884ceace | 345 | |
9f235dfa | 346 | cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6); |
73dec95e TU |
347 | if (IS_ERR(cs)) |
348 | return PTR_ERR(cs); | |
884ceace | 349 | |
9f235dfa | 350 | flags = PIPE_CONTROL_CS_STALL; |
a5f3d68e | 351 | |
7c9cf4e3 | 352 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
353 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
354 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 355 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 356 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 357 | } |
7c9cf4e3 | 358 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
359 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
360 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
361 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
362 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
363 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
364 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
365 | flags |= PIPE_CONTROL_QW_WRITE; | |
366 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
367 | |
368 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
9f235dfa TU |
369 | cs = gen8_emit_pipe_control(cs, |
370 | PIPE_CONTROL_CS_STALL | | |
371 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
372 | 0); | |
a5f3d68e BW |
373 | } |
374 | ||
9f235dfa TU |
375 | cs = gen8_emit_pipe_control(cs, flags, |
376 | i915_ggtt_offset(req->engine->scratch) + | |
377 | 2 * CACHELINE_BYTES); | |
378 | ||
379 | intel_ring_advance(req, cs); | |
380 | ||
381 | return 0; | |
a5f3d68e BW |
382 | } |
383 | ||
0bc40be8 | 384 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 385 | { |
c033666a | 386 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
387 | u32 addr; |
388 | ||
389 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 390 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
391 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
392 | I915_WRITE(HWS_PGA, addr); | |
393 | } | |
394 | ||
0bc40be8 | 395 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 396 | { |
c033666a | 397 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 398 | i915_reg_t mmio; |
af75f269 DL |
399 | |
400 | /* The ring status page addresses are no longer next to the rest of | |
401 | * the ring registers as of gen7. | |
402 | */ | |
c033666a | 403 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 404 | switch (engine->id) { |
a2d3d265 MT |
405 | /* |
406 | * No more rings exist on Gen7. Default case is only to shut up | |
407 | * gcc switch check warning. | |
408 | */ | |
409 | default: | |
410 | GEM_BUG_ON(engine->id); | |
af75f269 DL |
411 | case RCS: |
412 | mmio = RENDER_HWS_PGA_GEN7; | |
413 | break; | |
414 | case BCS: | |
415 | mmio = BLT_HWS_PGA_GEN7; | |
416 | break; | |
af75f269 DL |
417 | case VCS: |
418 | mmio = BSD_HWS_PGA_GEN7; | |
419 | break; | |
420 | case VECS: | |
421 | mmio = VEBOX_HWS_PGA_GEN7; | |
422 | break; | |
423 | } | |
c033666a | 424 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 425 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
426 | } else { |
427 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 428 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
429 | } |
430 | ||
57e88531 | 431 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
432 | POSTING_READ(mmio); |
433 | ||
434 | /* | |
435 | * Flush the TLB for this page | |
436 | * | |
437 | * FIXME: These two bits have disappeared on gen8, so a question | |
438 | * arises: do we still need this and if so how should we go about | |
439 | * invalidating the TLB? | |
440 | */ | |
ac657f64 | 441 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 442 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
443 | |
444 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 445 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
446 | |
447 | I915_WRITE(reg, | |
448 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
449 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
450 | if (intel_wait_for_register(dev_priv, |
451 | reg, INSTPM_SYNC_FLUSH, 0, | |
452 | 1000)) | |
af75f269 | 453 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 454 | engine->name); |
af75f269 DL |
455 | } |
456 | } | |
457 | ||
0bc40be8 | 458 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 459 | { |
c033666a | 460 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 461 | |
21a2c58a | 462 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 463 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
464 | if (intel_wait_for_register(dev_priv, |
465 | RING_MI_MODE(engine->mmio_base), | |
466 | MODE_IDLE, | |
467 | MODE_IDLE, | |
468 | 1000)) { | |
0bc40be8 TU |
469 | DRM_ERROR("%s : timed out trying to stop ring\n", |
470 | engine->name); | |
9bec9b13 CW |
471 | /* Sometimes we observe that the idle flag is not |
472 | * set even though the ring is empty. So double | |
473 | * check before giving up. | |
474 | */ | |
0bc40be8 | 475 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 476 | return false; |
9991ae78 CW |
477 | } |
478 | } | |
b7884eb4 | 479 | |
0bc40be8 TU |
480 | I915_WRITE_CTL(engine, 0); |
481 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 482 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 483 | |
21a2c58a | 484 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
485 | (void)I915_READ_CTL(engine); |
486 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 487 | } |
a51435a3 | 488 | |
0bc40be8 | 489 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 490 | } |
8187a2b7 | 491 | |
0bc40be8 | 492 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 493 | { |
c033666a | 494 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 495 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
496 | int ret = 0; |
497 | ||
59bad947 | 498 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 499 | |
0bc40be8 | 500 | if (!stop_ring(engine)) { |
9991ae78 | 501 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
502 | DRM_DEBUG_KMS("%s head not reset to zero " |
503 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
504 | engine->name, |
505 | I915_READ_CTL(engine), | |
506 | I915_READ_HEAD(engine), | |
507 | I915_READ_TAIL(engine), | |
508 | I915_READ_START(engine)); | |
8187a2b7 | 509 | |
0bc40be8 | 510 | if (!stop_ring(engine)) { |
6fd0d56e CW |
511 | DRM_ERROR("failed to set %s head to zero " |
512 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
513 | engine->name, |
514 | I915_READ_CTL(engine), | |
515 | I915_READ_HEAD(engine), | |
516 | I915_READ_TAIL(engine), | |
517 | I915_READ_START(engine)); | |
9991ae78 CW |
518 | ret = -EIO; |
519 | goto out; | |
6fd0d56e | 520 | } |
8187a2b7 ZN |
521 | } |
522 | ||
3177659a | 523 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 524 | ring_setup_phys_status_page(engine); |
3177659a CS |
525 | else |
526 | intel_ring_setup_status_page(engine); | |
9991ae78 | 527 | |
ad07dfcd | 528 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 529 | |
ece4a17d | 530 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 531 | I915_READ_HEAD(engine); |
ece4a17d | 532 | |
0d8957c8 DV |
533 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
534 | * registers with the above sequence (the readback of the HEAD registers | |
535 | * also enforces ordering), otherwise the hw might lose the new ring | |
536 | * register values. */ | |
bde13ebd | 537 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
538 | |
539 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 540 | if (I915_READ_HEAD(engine)) |
95468892 | 541 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 542 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
543 | |
544 | intel_ring_update_space(ring); | |
545 | I915_WRITE_HEAD(engine, ring->head); | |
546 | I915_WRITE_TAIL(engine, ring->tail); | |
547 | (void)I915_READ_TAIL(engine); | |
95468892 | 548 | |
62ae14b1 | 549 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 550 | |
8187a2b7 | 551 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
552 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
553 | RING_VALID, RING_VALID, | |
554 | 50)) { | |
e74cfed5 | 555 | DRM_ERROR("%s initialization failed " |
821ed7df | 556 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
557 | engine->name, |
558 | I915_READ_CTL(engine), | |
559 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
560 | I915_READ_HEAD(engine), ring->head, |
561 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 562 | I915_READ_START(engine), |
bde13ebd | 563 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
564 | ret = -EIO; |
565 | goto out; | |
8187a2b7 ZN |
566 | } |
567 | ||
fc0768ce | 568 | intel_engine_init_hangcheck(engine); |
50f018df | 569 | |
b7884eb4 | 570 | out: |
59bad947 | 571 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
572 | |
573 | return ret; | |
8187a2b7 ZN |
574 | } |
575 | ||
821ed7df CW |
576 | static void reset_ring_common(struct intel_engine_cs *engine, |
577 | struct drm_i915_gem_request *request) | |
578 | { | |
c0dcb203 CW |
579 | /* Try to restore the logical GPU state to match the continuation |
580 | * of the request queue. If we skip the context/PD restore, then | |
581 | * the next request may try to execute assuming that its context | |
582 | * is valid and loaded on the GPU and so may try to access invalid | |
583 | * memory, prompting repeated GPU hangs. | |
584 | * | |
585 | * If the request was guilty, we still restore the logical state | |
586 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
587 | * but skip over the hung batch. | |
588 | * | |
589 | * If the request was innocent, we try to replay the request with | |
590 | * the restored context. | |
591 | */ | |
592 | if (request) { | |
593 | struct drm_i915_private *dev_priv = request->i915; | |
594 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
595 | struct i915_hw_ppgtt *ppgtt; | |
596 | ||
597 | /* FIXME consider gen8 reset */ | |
598 | ||
599 | if (ce->state) { | |
600 | I915_WRITE(CCID, | |
601 | i915_ggtt_offset(ce->state) | | |
602 | BIT(8) /* must be set! */ | | |
603 | CCID_EXTENDED_STATE_SAVE | | |
604 | CCID_EXTENDED_STATE_RESTORE | | |
605 | CCID_EN); | |
606 | } | |
607 | ||
608 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
609 | if (ppgtt) { | |
610 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
611 | ||
612 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
613 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
614 | ||
615 | /* Wait for the PD reload to complete */ | |
616 | if (intel_wait_for_register(dev_priv, | |
617 | RING_PP_DIR_BASE(engine), | |
618 | BIT(0), 0, | |
619 | 10)) | |
620 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 621 | |
c0dcb203 CW |
622 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
623 | } | |
624 | ||
625 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
fe085f13 CW |
626 | if (request->fence.error == -EIO) |
627 | request->ring->head = request->postfix; | |
c0dcb203 CW |
628 | } else { |
629 | engine->legacy_active_context = NULL; | |
630 | } | |
821ed7df CW |
631 | } |
632 | ||
8753181e | 633 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
634 | { |
635 | int ret; | |
636 | ||
e2be4faf | 637 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
638 | if (ret != 0) |
639 | return ret; | |
640 | ||
4e50f082 | 641 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 642 | if (ret) |
e26e1b97 | 643 | return ret; |
8f0e2b9d | 644 | |
e26e1b97 | 645 | return 0; |
8f0e2b9d DV |
646 | } |
647 | ||
0bc40be8 | 648 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 649 | { |
c033666a | 650 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 651 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
652 | if (ret) |
653 | return ret; | |
a69ffdbf | 654 | |
61a563a2 | 655 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 656 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 657 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
658 | |
659 | /* We need to disable the AsyncFlip performance optimisations in order | |
660 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
661 | * programmed to '1' on all products. | |
8693a824 | 662 | * |
2441f877 | 663 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 664 | */ |
ac657f64 | 665 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
666 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
667 | ||
f05bb0c7 | 668 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 669 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 670 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 671 | I915_WRITE(GFX_MODE, |
aa83e30d | 672 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 673 | |
01fa0302 | 674 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 675 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 676 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 677 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 678 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 679 | |
c033666a | 680 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
681 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
682 | * "If this bit is set, STCunit will have LRA as replacement | |
683 | * policy. [...] This bit must be reset. LRA replacement | |
684 | * policy is not supported." | |
685 | */ | |
686 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 687 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
688 | } |
689 | ||
ac657f64 | 690 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 691 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 692 | |
035ea405 VS |
693 | if (INTEL_INFO(dev_priv)->gen >= 6) |
694 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 695 | |
0bc40be8 | 696 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
697 | } |
698 | ||
0bc40be8 | 699 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 700 | { |
c033666a | 701 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 702 | |
19880c4a | 703 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
704 | } |
705 | ||
73dec95e | 706 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 707 | { |
ad7bdb2b | 708 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 709 | struct intel_engine_cs *waiter; |
c3232b18 | 710 | enum intel_engine_id id; |
3e78998a | 711 | |
3b3f1650 | 712 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 713 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
714 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
715 | continue; | |
716 | ||
73dec95e TU |
717 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
718 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | | |
719 | PIPE_CONTROL_CS_STALL; | |
720 | *cs++ = lower_32_bits(gtt_offset); | |
721 | *cs++ = upper_32_bits(gtt_offset); | |
722 | *cs++ = req->global_seqno; | |
723 | *cs++ = 0; | |
724 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
725 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
726 | *cs++ = 0; | |
3e78998a BW |
727 | } |
728 | ||
73dec95e | 729 | return cs; |
3e78998a BW |
730 | } |
731 | ||
73dec95e | 732 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 733 | { |
ad7bdb2b | 734 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 735 | struct intel_engine_cs *waiter; |
c3232b18 | 736 | enum intel_engine_id id; |
3e78998a | 737 | |
3b3f1650 | 738 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 739 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
740 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
741 | continue; | |
742 | ||
73dec95e TU |
743 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
744 | *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
745 | *cs++ = upper_32_bits(gtt_offset); | |
746 | *cs++ = req->global_seqno; | |
747 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
748 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
749 | *cs++ = 0; | |
3e78998a BW |
750 | } |
751 | ||
73dec95e | 752 | return cs; |
3e78998a BW |
753 | } |
754 | ||
73dec95e | 755 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 756 | { |
ad7bdb2b | 757 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 758 | struct intel_engine_cs *engine; |
3b3f1650 | 759 | enum intel_engine_id id; |
caddfe71 | 760 | int num_rings = 0; |
024a43e1 | 761 | |
3b3f1650 | 762 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
763 | i915_reg_t mbox_reg; |
764 | ||
765 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
766 | continue; | |
f0f59a00 | 767 | |
318f89ca | 768 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 769 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
770 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
771 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
772 | *cs++ = req->global_seqno; | |
caddfe71 | 773 | num_rings++; |
78325f2d BW |
774 | } |
775 | } | |
caddfe71 | 776 | if (num_rings & 1) |
73dec95e | 777 | *cs++ = MI_NOOP; |
024a43e1 | 778 | |
73dec95e | 779 | return cs; |
1ec14ad3 CW |
780 | } |
781 | ||
b0411e7d CW |
782 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
783 | { | |
784 | struct drm_i915_private *dev_priv = request->i915; | |
785 | ||
d55ac5bf CW |
786 | i915_gem_request_submit(request); |
787 | ||
e6ba9992 CW |
788 | I915_WRITE_TAIL(request->engine, |
789 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
790 | } |
791 | ||
73dec95e | 792 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 793 | { |
73dec95e TU |
794 | *cs++ = MI_STORE_DWORD_INDEX; |
795 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
796 | *cs++ = req->global_seqno; | |
797 | *cs++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 798 | |
73dec95e | 799 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 800 | assert_ring_tail_valid(req->ring, req->tail); |
1ec14ad3 CW |
801 | } |
802 | ||
98f29e8d CW |
803 | static const int i9xx_emit_breadcrumb_sz = 4; |
804 | ||
b0411e7d | 805 | /** |
9b81d556 | 806 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
807 | * |
808 | * @request - request to write to the ring | |
809 | * | |
810 | * Update the mailbox registers in the *other* rings with the current seqno. | |
811 | * This acts like a signal in the canonical semaphore. | |
812 | */ | |
73dec95e | 813 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
b0411e7d | 814 | { |
caddfe71 | 815 | return i9xx_emit_breadcrumb(req, |
73dec95e | 816 | req->engine->semaphore.signal(req, cs)); |
b0411e7d CW |
817 | } |
818 | ||
caddfe71 | 819 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
73dec95e | 820 | u32 *cs) |
a58c01aa CW |
821 | { |
822 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 823 | |
caddfe71 | 824 | if (engine->semaphore.signal) |
73dec95e TU |
825 | cs = engine->semaphore.signal(req, cs); |
826 | ||
827 | *cs++ = GFX_OP_PIPE_CONTROL(6); | |
828 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
829 | PIPE_CONTROL_QW_WRITE; | |
830 | *cs++ = intel_hws_seqno_address(engine); | |
831 | *cs++ = 0; | |
832 | *cs++ = req->global_seqno; | |
a58c01aa | 833 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
834 | *cs++ = 0; |
835 | *cs++ = MI_USER_INTERRUPT; | |
836 | *cs++ = MI_NOOP; | |
a58c01aa | 837 | |
73dec95e | 838 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 839 | assert_ring_tail_valid(req->ring, req->tail); |
a58c01aa CW |
840 | } |
841 | ||
98f29e8d CW |
842 | static const int gen8_render_emit_breadcrumb_sz = 8; |
843 | ||
c8c99b0f BW |
844 | /** |
845 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
846 | * | |
847 | * @waiter - ring that is waiting | |
848 | * @signaller - ring which has, or will signal | |
849 | * @seqno - seqno which the waiter will block on | |
850 | */ | |
5ee426ca BW |
851 | |
852 | static int | |
ad7bdb2b CW |
853 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
854 | struct drm_i915_gem_request *signal) | |
5ee426ca | 855 | { |
ad7bdb2b CW |
856 | struct drm_i915_private *dev_priv = req->i915; |
857 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 858 | struct i915_hw_ppgtt *ppgtt; |
73dec95e | 859 | u32 *cs; |
5ee426ca | 860 | |
73dec95e TU |
861 | cs = intel_ring_begin(req, 4); |
862 | if (IS_ERR(cs)) | |
863 | return PTR_ERR(cs); | |
5ee426ca | 864 | |
73dec95e TU |
865 | *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | |
866 | MI_SEMAPHORE_SAD_GTE_SDD; | |
867 | *cs++ = signal->global_seqno; | |
868 | *cs++ = lower_32_bits(offset); | |
869 | *cs++ = upper_32_bits(offset); | |
870 | intel_ring_advance(req, cs); | |
6ef48d7f CW |
871 | |
872 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
873 | * pagetables and we must reload them before executing the batch. | |
874 | * We do this on the i915_switch_context() following the wait and | |
875 | * before the dispatch. | |
876 | */ | |
ad7bdb2b CW |
877 | ppgtt = req->ctx->ppgtt; |
878 | if (ppgtt && req->engine->id != RCS) | |
879 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
880 | return 0; |
881 | } | |
882 | ||
c8c99b0f | 883 | static int |
ad7bdb2b CW |
884 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
885 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 886 | { |
c8c99b0f BW |
887 | u32 dw1 = MI_SEMAPHORE_MBOX | |
888 | MI_SEMAPHORE_COMPARE | | |
889 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 890 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
73dec95e | 891 | u32 *cs; |
1ec14ad3 | 892 | |
ebc348b2 | 893 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 894 | |
73dec95e TU |
895 | cs = intel_ring_begin(req, 4); |
896 | if (IS_ERR(cs)) | |
897 | return PTR_ERR(cs); | |
1ec14ad3 | 898 | |
73dec95e | 899 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
900 | /* Throughout all of the GEM code, seqno passed implies our current |
901 | * seqno is >= the last seqno executed. However for hardware the | |
902 | * comparison is strictly greater than. | |
903 | */ | |
73dec95e TU |
904 | *cs++ = signal->global_seqno - 1; |
905 | *cs++ = 0; | |
906 | *cs++ = MI_NOOP; | |
907 | intel_ring_advance(req, cs); | |
1ec14ad3 CW |
908 | |
909 | return 0; | |
910 | } | |
911 | ||
f8973c21 | 912 | static void |
38a0f2db | 913 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 914 | { |
f8973c21 CW |
915 | /* MI_STORE are internally buffered by the GPU and not flushed |
916 | * either by MI_FLUSH or SyncFlush or any other combination of | |
917 | * MI commands. | |
c6df541c | 918 | * |
f8973c21 CW |
919 | * "Only the submission of the store operation is guaranteed. |
920 | * The write result will be complete (coherent) some time later | |
921 | * (this is practically a finite period but there is no guaranteed | |
922 | * latency)." | |
923 | * | |
924 | * Empirically, we observe that we need a delay of at least 75us to | |
925 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 926 | */ |
f8973c21 | 927 | usleep_range(125, 250); |
c6df541c CW |
928 | } |
929 | ||
c04e0f3b CW |
930 | static void |
931 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 932 | { |
c033666a | 933 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 934 | |
4cd53c0c DV |
935 | /* Workaround to force correct ordering between irq and seqno writes on |
936 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
937 | * ACTHD) before reading the status page. |
938 | * | |
939 | * Note that this effectively stalls the read by the time it takes to | |
940 | * do a memory transaction, which more or less ensures that the write | |
941 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
942 | * Alternatively we could delay the interrupt from the CS ring to give | |
943 | * the write time to land, but that would incur a delay after every | |
944 | * batch i.e. much more frequent than a delay when waiting for the | |
945 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
946 | * |
947 | * Also note that to prevent whole machine hangs on gen7, we have to | |
948 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 949 | */ |
bcbdb6d0 | 950 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 951 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 952 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
953 | } |
954 | ||
31bb59cc CW |
955 | static void |
956 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 957 | { |
31bb59cc | 958 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
959 | } |
960 | ||
961 | static void | |
31bb59cc | 962 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 963 | { |
31bb59cc | 964 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
965 | } |
966 | ||
31bb59cc CW |
967 | static void |
968 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 969 | { |
c033666a | 970 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 971 | |
31bb59cc CW |
972 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
973 | I915_WRITE(IMR, dev_priv->irq_mask); | |
974 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
975 | } |
976 | ||
8187a2b7 | 977 | static void |
31bb59cc | 978 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 979 | { |
c033666a | 980 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 981 | |
31bb59cc CW |
982 | dev_priv->irq_mask |= engine->irq_enable_mask; |
983 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
984 | } |
985 | ||
31bb59cc CW |
986 | static void |
987 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 988 | { |
c033666a | 989 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 990 | |
31bb59cc CW |
991 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
992 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
993 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
994 | } |
995 | ||
996 | static void | |
31bb59cc | 997 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 998 | { |
c033666a | 999 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1000 | |
31bb59cc CW |
1001 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1002 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1003 | } |
1004 | ||
b72f3acb | 1005 | static int |
7c9cf4e3 | 1006 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1007 | { |
73dec95e | 1008 | u32 *cs; |
b72f3acb | 1009 | |
73dec95e TU |
1010 | cs = intel_ring_begin(req, 2); |
1011 | if (IS_ERR(cs)) | |
1012 | return PTR_ERR(cs); | |
b72f3acb | 1013 | |
73dec95e TU |
1014 | *cs++ = MI_FLUSH; |
1015 | *cs++ = MI_NOOP; | |
1016 | intel_ring_advance(req, cs); | |
b72f3acb | 1017 | return 0; |
d1b851fc ZN |
1018 | } |
1019 | ||
31bb59cc CW |
1020 | static void |
1021 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1022 | { |
c033666a | 1023 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1024 | |
61ff75ac CW |
1025 | I915_WRITE_IMR(engine, |
1026 | ~(engine->irq_enable_mask | | |
1027 | engine->irq_keep_mask)); | |
31bb59cc | 1028 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1029 | } |
1030 | ||
1031 | static void | |
31bb59cc | 1032 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1033 | { |
c033666a | 1034 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1035 | |
61ff75ac | 1036 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1037 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1038 | } |
1039 | ||
31bb59cc CW |
1040 | static void |
1041 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1042 | { |
c033666a | 1043 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1044 | |
31bb59cc | 1045 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1046 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1047 | } |
1048 | ||
1049 | static void | |
31bb59cc | 1050 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1051 | { |
c033666a | 1052 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1053 | |
31bb59cc | 1054 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1055 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1056 | } |
1057 | ||
31bb59cc CW |
1058 | static void |
1059 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1060 | { |
c033666a | 1061 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1062 | |
61ff75ac CW |
1063 | I915_WRITE_IMR(engine, |
1064 | ~(engine->irq_enable_mask | | |
1065 | engine->irq_keep_mask)); | |
31bb59cc | 1066 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1067 | } |
1068 | ||
1069 | static void | |
31bb59cc | 1070 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1071 | { |
c033666a | 1072 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1073 | |
61ff75ac | 1074 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1075 | } |
1076 | ||
d1b851fc | 1077 | static int |
803688ba CW |
1078 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1079 | u64 offset, u32 length, | |
1080 | unsigned int dispatch_flags) | |
d1b851fc | 1081 | { |
73dec95e | 1082 | u32 *cs; |
78501eac | 1083 | |
73dec95e TU |
1084 | cs = intel_ring_begin(req, 2); |
1085 | if (IS_ERR(cs)) | |
1086 | return PTR_ERR(cs); | |
e1f99ce6 | 1087 | |
73dec95e TU |
1088 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1089 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1090 | *cs++ = offset; | |
1091 | intel_ring_advance(req, cs); | |
78501eac | 1092 | |
d1b851fc ZN |
1093 | return 0; |
1094 | } | |
1095 | ||
b45305fc DV |
1096 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1097 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1098 | #define I830_TLB_ENTRIES (2) |
1099 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1100 | static int |
803688ba CW |
1101 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1102 | u64 offset, u32 len, | |
1103 | unsigned int dispatch_flags) | |
62fdfeaf | 1104 | { |
73dec95e | 1105 | u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); |
62fdfeaf | 1106 | |
73dec95e TU |
1107 | cs = intel_ring_begin(req, 6); |
1108 | if (IS_ERR(cs)) | |
1109 | return PTR_ERR(cs); | |
62fdfeaf | 1110 | |
c4d69da1 | 1111 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1112 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1113 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1114 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1115 | *cs++ = cs_offset; | |
1116 | *cs++ = 0xdeadbeef; | |
1117 | *cs++ = MI_NOOP; | |
1118 | intel_ring_advance(req, cs); | |
b45305fc | 1119 | |
8e004efc | 1120 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1121 | if (len > I830_BATCH_LIMIT) |
1122 | return -ENOSPC; | |
1123 | ||
73dec95e TU |
1124 | cs = intel_ring_begin(req, 6 + 2); |
1125 | if (IS_ERR(cs)) | |
1126 | return PTR_ERR(cs); | |
c4d69da1 CW |
1127 | |
1128 | /* Blit the batch (which has now all relocs applied) to the | |
1129 | * stable batch scratch bo area (so that the CS never | |
1130 | * stumbles over its tlb invalidation bug) ... | |
1131 | */ | |
73dec95e TU |
1132 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1133 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1134 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1135 | *cs++ = cs_offset; | |
1136 | *cs++ = 4096; | |
1137 | *cs++ = offset; | |
1138 | ||
1139 | *cs++ = MI_FLUSH; | |
1140 | *cs++ = MI_NOOP; | |
1141 | intel_ring_advance(req, cs); | |
b45305fc DV |
1142 | |
1143 | /* ... and execute it. */ | |
c4d69da1 | 1144 | offset = cs_offset; |
b45305fc | 1145 | } |
e1f99ce6 | 1146 | |
73dec95e TU |
1147 | cs = intel_ring_begin(req, 2); |
1148 | if (IS_ERR(cs)) | |
1149 | return PTR_ERR(cs); | |
c4d69da1 | 1150 | |
73dec95e TU |
1151 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1152 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1153 | MI_BATCH_NON_SECURE); | |
1154 | intel_ring_advance(req, cs); | |
c4d69da1 | 1155 | |
fb3256da DV |
1156 | return 0; |
1157 | } | |
1158 | ||
1159 | static int | |
803688ba CW |
1160 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1161 | u64 offset, u32 len, | |
1162 | unsigned int dispatch_flags) | |
fb3256da | 1163 | { |
73dec95e | 1164 | u32 *cs; |
fb3256da | 1165 | |
73dec95e TU |
1166 | cs = intel_ring_begin(req, 2); |
1167 | if (IS_ERR(cs)) | |
1168 | return PTR_ERR(cs); | |
fb3256da | 1169 | |
73dec95e TU |
1170 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1171 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1172 | MI_BATCH_NON_SECURE); | |
1173 | intel_ring_advance(req, cs); | |
62fdfeaf | 1174 | |
62fdfeaf EA |
1175 | return 0; |
1176 | } | |
1177 | ||
62fdfeaf | 1178 | |
6b8294a4 | 1179 | |
d822bb18 CW |
1180 | int intel_ring_pin(struct intel_ring *ring, |
1181 | struct drm_i915_private *i915, | |
1182 | unsigned int offset_bias) | |
7ba717cf | 1183 | { |
d822bb18 | 1184 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1185 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1186 | unsigned int flags; |
8305216f | 1187 | void *addr; |
7ba717cf TD |
1188 | int ret; |
1189 | ||
57e88531 | 1190 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1191 | |
9d80841e | 1192 | |
d3ef1af6 DCS |
1193 | flags = PIN_GLOBAL; |
1194 | if (offset_bias) | |
1195 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1196 | if (vma->obj->stolen) |
57e88531 | 1197 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1198 | |
57e88531 | 1199 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1200 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1201 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1202 | else | |
1203 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1204 | if (unlikely(ret)) | |
def0c5f6 | 1205 | return ret; |
57e88531 | 1206 | } |
7ba717cf | 1207 | |
57e88531 CW |
1208 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1209 | if (unlikely(ret)) | |
1210 | return ret; | |
def0c5f6 | 1211 | |
9d80841e | 1212 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1213 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1214 | else | |
9d80841e | 1215 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1216 | if (IS_ERR(addr)) |
1217 | goto err; | |
7ba717cf | 1218 | |
32c04f16 | 1219 | ring->vaddr = addr; |
7ba717cf | 1220 | return 0; |
d2cad535 | 1221 | |
57e88531 CW |
1222 | err: |
1223 | i915_vma_unpin(vma); | |
1224 | return PTR_ERR(addr); | |
7ba717cf TD |
1225 | } |
1226 | ||
e6ba9992 CW |
1227 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1228 | { | |
1229 | GEM_BUG_ON(!list_empty(&ring->request_list)); | |
1230 | ring->tail = tail; | |
1231 | ring->head = tail; | |
1232 | ring->emit = tail; | |
1233 | intel_ring_update_space(ring); | |
1234 | } | |
1235 | ||
aad29fbb CW |
1236 | void intel_ring_unpin(struct intel_ring *ring) |
1237 | { | |
1238 | GEM_BUG_ON(!ring->vma); | |
1239 | GEM_BUG_ON(!ring->vaddr); | |
1240 | ||
e6ba9992 CW |
1241 | /* Discard any unused bytes beyond that submitted to hw. */ |
1242 | intel_ring_reset(ring, ring->tail); | |
1243 | ||
9d80841e | 1244 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1245 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1246 | else |
1247 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1248 | ring->vaddr = NULL; |
1249 | ||
57e88531 | 1250 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1251 | } |
1252 | ||
57e88531 CW |
1253 | static struct i915_vma * |
1254 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1255 | { |
05394f39 | 1256 | struct drm_i915_gem_object *obj; |
57e88531 | 1257 | struct i915_vma *vma; |
62fdfeaf | 1258 | |
187685cb | 1259 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1260 | if (!obj) |
2d6c4c84 | 1261 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1262 | if (IS_ERR(obj)) |
1263 | return ERR_CAST(obj); | |
8187a2b7 | 1264 | |
24f3a8cf AG |
1265 | /* mark ring buffers as read-only from GPU side by default */ |
1266 | obj->gt_ro = 1; | |
1267 | ||
a01cb37a | 1268 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1269 | if (IS_ERR(vma)) |
1270 | goto err; | |
1271 | ||
1272 | return vma; | |
e3efda49 | 1273 | |
57e88531 CW |
1274 | err: |
1275 | i915_gem_object_put(obj); | |
1276 | return vma; | |
e3efda49 CW |
1277 | } |
1278 | ||
7e37f889 CW |
1279 | struct intel_ring * |
1280 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1281 | { |
7e37f889 | 1282 | struct intel_ring *ring; |
57e88531 | 1283 | struct i915_vma *vma; |
01101fa7 | 1284 | |
8f942018 | 1285 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1286 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1287 | |
01101fa7 | 1288 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1289 | if (!ring) |
01101fa7 CW |
1290 | return ERR_PTR(-ENOMEM); |
1291 | ||
675d9ad7 CW |
1292 | INIT_LIST_HEAD(&ring->request_list); |
1293 | ||
01101fa7 CW |
1294 | ring->size = size; |
1295 | /* Workaround an erratum on the i830 which causes a hang if | |
1296 | * the TAIL pointer points to within the last 2 cachelines | |
1297 | * of the buffer. | |
1298 | */ | |
1299 | ring->effective_size = size; | |
2a307c2e | 1300 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1301 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1302 | ||
01101fa7 CW |
1303 | intel_ring_update_space(ring); |
1304 | ||
57e88531 CW |
1305 | vma = intel_ring_create_vma(engine->i915, size); |
1306 | if (IS_ERR(vma)) { | |
01101fa7 | 1307 | kfree(ring); |
57e88531 | 1308 | return ERR_CAST(vma); |
01101fa7 | 1309 | } |
57e88531 | 1310 | ring->vma = vma; |
01101fa7 CW |
1311 | |
1312 | return ring; | |
1313 | } | |
1314 | ||
1315 | void | |
7e37f889 | 1316 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1317 | { |
f8a7fde4 CW |
1318 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1319 | ||
1320 | i915_vma_close(ring->vma); | |
1321 | __i915_gem_object_release_unless_active(obj); | |
1322 | ||
01101fa7 CW |
1323 | kfree(ring); |
1324 | } | |
1325 | ||
72b72ae4 | 1326 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1327 | { |
1328 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1329 | int ret; | |
1330 | ||
1331 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
1332 | * We only want to do this on the first bind so that we do not stall | |
1333 | * on an active context (which by nature is already on the GPU). | |
1334 | */ | |
1335 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
1336 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
1337 | if (ret) | |
1338 | return ret; | |
1339 | } | |
1340 | ||
afeddf50 CW |
1341 | return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1342 | PIN_GLOBAL | PIN_HIGH); | |
e8a9c58f CW |
1343 | } |
1344 | ||
3204c343 CW |
1345 | static struct i915_vma * |
1346 | alloc_context_vma(struct intel_engine_cs *engine) | |
1347 | { | |
1348 | struct drm_i915_private *i915 = engine->i915; | |
1349 | struct drm_i915_gem_object *obj; | |
1350 | struct i915_vma *vma; | |
1351 | ||
63ffbcda | 1352 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1353 | if (IS_ERR(obj)) |
1354 | return ERR_CAST(obj); | |
1355 | ||
1356 | /* | |
1357 | * Try to make the context utilize L3 as well as LLC. | |
1358 | * | |
1359 | * On VLV we don't have L3 controls in the PTEs so we | |
1360 | * shouldn't touch the cache level, especially as that | |
1361 | * would make the object snooped which might have a | |
1362 | * negative performance impact. | |
1363 | * | |
1364 | * Snooping is required on non-llc platforms in execlist | |
1365 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1366 | * get snooping anyway regardless of cache_level. | |
1367 | * | |
1368 | * This is only applicable for Ivy Bridge devices since | |
1369 | * later platforms don't have L3 control bits in the PTE. | |
1370 | */ | |
1371 | if (IS_IVYBRIDGE(i915)) { | |
1372 | /* Ignore any error, regard it as a simple optimisation */ | |
1373 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1374 | } | |
1375 | ||
1376 | vma = i915_vma_instance(obj, &i915->ggtt.base, NULL); | |
1377 | if (IS_ERR(vma)) | |
1378 | i915_gem_object_put(obj); | |
1379 | ||
1380 | return vma; | |
1381 | } | |
1382 | ||
266a240b CW |
1383 | static struct intel_ring * |
1384 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1385 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1386 | { |
1387 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1388 | int ret; | |
1389 | ||
91c8a326 | 1390 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1391 | |
266a240b CW |
1392 | if (likely(ce->pin_count++)) |
1393 | goto out; | |
a533b4ba | 1394 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
0cb26a8e | 1395 | |
63ffbcda | 1396 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1397 | struct i915_vma *vma; |
1398 | ||
1399 | vma = alloc_context_vma(engine); | |
1400 | if (IS_ERR(vma)) { | |
1401 | ret = PTR_ERR(vma); | |
266a240b | 1402 | goto err; |
3204c343 CW |
1403 | } |
1404 | ||
1405 | ce->state = vma; | |
1406 | } | |
1407 | ||
0cb26a8e | 1408 | if (ce->state) { |
72b72ae4 | 1409 | ret = context_pin(ctx); |
e8a9c58f | 1410 | if (ret) |
266a240b | 1411 | goto err; |
5d4bac55 CW |
1412 | |
1413 | ce->state->obj->mm.dirty = true; | |
0cb26a8e CW |
1414 | } |
1415 | ||
c7c3c07d CW |
1416 | /* The kernel context is only used as a placeholder for flushing the |
1417 | * active context. It is never used for submitting user rendering and | |
1418 | * as such never requires the golden render context, and so we can skip | |
1419 | * emitting it when we switch to the kernel context. This is required | |
1420 | * as during eviction we cannot allocate and pin the renderstate in | |
1421 | * order to initialise the context. | |
1422 | */ | |
984ff29f | 1423 | if (i915_gem_context_is_kernel(ctx)) |
c7c3c07d CW |
1424 | ce->initialised = true; |
1425 | ||
9a6feaf0 | 1426 | i915_gem_context_get(ctx); |
0cb26a8e | 1427 | |
266a240b CW |
1428 | out: |
1429 | /* One ringbuffer to rule them all */ | |
1430 | return engine->buffer; | |
1431 | ||
1432 | err: | |
0cb26a8e | 1433 | ce->pin_count = 0; |
266a240b | 1434 | return ERR_PTR(ret); |
0cb26a8e CW |
1435 | } |
1436 | ||
e8a9c58f CW |
1437 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1438 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1439 | { |
1440 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1441 | ||
91c8a326 | 1442 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1443 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1444 | |
1445 | if (--ce->pin_count) | |
1446 | return; | |
1447 | ||
1448 | if (ce->state) | |
bf3783e5 | 1449 | i915_vma_unpin(ce->state); |
0cb26a8e | 1450 | |
9a6feaf0 | 1451 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1452 | } |
1453 | ||
acd27845 | 1454 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1455 | { |
32c04f16 | 1456 | struct intel_ring *ring; |
1a5788bf | 1457 | int err; |
bfc882b4 | 1458 | |
019bf277 TU |
1459 | intel_engine_setup_common(engine); |
1460 | ||
1a5788bf CW |
1461 | err = intel_engine_init_common(engine); |
1462 | if (err) | |
1463 | goto err; | |
e3efda49 | 1464 | |
d822bb18 CW |
1465 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1466 | if (IS_ERR(ring)) { | |
1a5788bf | 1467 | err = PTR_ERR(ring); |
486e93f7 | 1468 | goto err; |
d822bb18 CW |
1469 | } |
1470 | ||
d3ef1af6 | 1471 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1472 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1473 | if (err) | |
1474 | goto err_ring; | |
1475 | ||
1476 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1477 | engine->buffer = ring; |
62fdfeaf | 1478 | |
8ee14975 | 1479 | return 0; |
351e3db2 | 1480 | |
1a5788bf CW |
1481 | err_ring: |
1482 | intel_ring_free(ring); | |
1a5788bf CW |
1483 | err: |
1484 | intel_engine_cleanup_common(engine); | |
1485 | return err; | |
62fdfeaf EA |
1486 | } |
1487 | ||
7e37f889 | 1488 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1489 | { |
1a5788bf | 1490 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1491 | |
1a5788bf CW |
1492 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1493 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1494 | |
1a5788bf CW |
1495 | intel_ring_unpin(engine->buffer); |
1496 | intel_ring_free(engine->buffer); | |
78501eac | 1497 | |
0bc40be8 TU |
1498 | if (engine->cleanup) |
1499 | engine->cleanup(engine); | |
8d19215b | 1500 | |
96a945aa | 1501 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1502 | |
3b3f1650 AG |
1503 | dev_priv->engine[engine->id] = NULL; |
1504 | kfree(engine); | |
62fdfeaf EA |
1505 | } |
1506 | ||
821ed7df CW |
1507 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1508 | { | |
1509 | struct intel_engine_cs *engine; | |
3b3f1650 | 1510 | enum intel_engine_id id; |
821ed7df | 1511 | |
e6ba9992 | 1512 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1513 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1514 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1515 | } |
1516 | ||
f73e7399 | 1517 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 1518 | { |
73dec95e | 1519 | u32 *cs; |
6310346e | 1520 | |
e8a9c58f CW |
1521 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1522 | ||
6310346e CW |
1523 | /* Flush enough space to reduce the likelihood of waiting after |
1524 | * we start building the request - in which case we will just | |
1525 | * have to repeat work. | |
1526 | */ | |
a0442461 | 1527 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1528 | |
73dec95e TU |
1529 | cs = intel_ring_begin(request, 0); |
1530 | if (IS_ERR(cs)) | |
1531 | return PTR_ERR(cs); | |
6310346e | 1532 | |
a0442461 | 1533 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1534 | return 0; |
9d773091 CW |
1535 | } |
1536 | ||
5e5655c3 CW |
1537 | static noinline int wait_for_space(struct drm_i915_gem_request *req, |
1538 | unsigned int bytes) | |
987046ad | 1539 | { |
7e37f889 | 1540 | struct intel_ring *ring = req->ring; |
987046ad | 1541 | struct drm_i915_gem_request *target; |
e95433c7 CW |
1542 | long timeout; |
1543 | ||
1544 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
987046ad | 1545 | |
95aebcb2 | 1546 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1547 | return 0; |
1548 | ||
1549 | /* | |
1550 | * Space is reserved in the ringbuffer for finalising the request, | |
1551 | * as that cannot be allowed to fail. During request finalisation, | |
1552 | * reserved_space is set to 0 to stop the overallocation and the | |
1553 | * assumption is that then we never need to wait (which has the | |
1554 | * risk of failing with EINTR). | |
1555 | * | |
1556 | * See also i915_gem_request_alloc() and i915_add_request(). | |
1557 | */ | |
0251a963 | 1558 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 1559 | |
675d9ad7 | 1560 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1561 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1562 | if (bytes <= __intel_ring_space(target->postfix, |
1563 | ring->emit, ring->size)) | |
987046ad | 1564 | break; |
79bbcc29 | 1565 | } |
29b1b415 | 1566 | |
675d9ad7 | 1567 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1568 | return -ENOSPC; |
1569 | ||
e95433c7 CW |
1570 | timeout = i915_wait_request(target, |
1571 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
1572 | MAX_SCHEDULE_TIMEOUT); | |
1573 | if (timeout < 0) | |
1574 | return timeout; | |
7da844c5 | 1575 | |
7da844c5 CW |
1576 | i915_gem_request_retire_upto(target); |
1577 | ||
1578 | intel_ring_update_space(ring); | |
1579 | GEM_BUG_ON(ring->space < bytes); | |
1580 | return 0; | |
29b1b415 JH |
1581 | } |
1582 | ||
5e5655c3 CW |
1583 | u32 *intel_ring_begin(struct drm_i915_gem_request *req, |
1584 | unsigned int num_dwords) | |
cbcc80df | 1585 | { |
7e37f889 | 1586 | struct intel_ring *ring = req->ring; |
5e5655c3 CW |
1587 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1588 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1589 | unsigned int need_wrap = 0; | |
1590 | unsigned int total_bytes; | |
73dec95e | 1591 | u32 *cs; |
29b1b415 | 1592 | |
6492ca79 CW |
1593 | /* Packets must be qword aligned. */ |
1594 | GEM_BUG_ON(num_dwords & 1); | |
1595 | ||
0251a963 | 1596 | total_bytes = bytes + req->reserved_space; |
5e5655c3 | 1597 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1598 | |
5e5655c3 CW |
1599 | if (unlikely(total_bytes > remain_usable)) { |
1600 | const int remain_actual = ring->size - ring->emit; | |
1601 | ||
1602 | if (bytes > remain_usable) { | |
1603 | /* | |
1604 | * Not enough space for the basic request. So need to | |
1605 | * flush out the remainder and then wait for | |
1606 | * base + reserved. | |
1607 | */ | |
1608 | total_bytes += remain_actual; | |
1609 | need_wrap = remain_actual | 1; | |
1610 | } else { | |
1611 | /* | |
1612 | * The base request will fit but the reserved space | |
1613 | * falls off the end. So we don't need an immediate | |
1614 | * wrap and only need to effectively wait for the | |
1615 | * reserved size from the start of ringbuffer. | |
1616 | */ | |
1617 | total_bytes = req->reserved_space + remain_actual; | |
1618 | } | |
cbcc80df MK |
1619 | } |
1620 | ||
5e5655c3 CW |
1621 | if (unlikely(total_bytes > ring->space)) { |
1622 | int ret = wait_for_space(req, total_bytes); | |
cbcc80df | 1623 | if (unlikely(ret)) |
73dec95e | 1624 | return ERR_PTR(ret); |
cbcc80df MK |
1625 | } |
1626 | ||
987046ad | 1627 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1628 | need_wrap &= ~1; |
1629 | GEM_BUG_ON(need_wrap > ring->space); | |
1630 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
78501eac | 1631 | |
987046ad | 1632 | /* Fill the tail with MI_NOOP */ |
5e5655c3 | 1633 | memset(ring->vaddr + ring->emit, 0, need_wrap); |
e6ba9992 | 1634 | ring->emit = 0; |
5e5655c3 | 1635 | ring->space -= need_wrap; |
987046ad | 1636 | } |
304d695c | 1637 | |
e6ba9992 | 1638 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1639 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1640 | cs = ring->vaddr + ring->emit; |
01001863 | 1641 | GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes)); |
e6ba9992 | 1642 | ring->emit += bytes; |
1dae2dfb | 1643 | ring->space -= bytes; |
73dec95e TU |
1644 | |
1645 | return cs; | |
8187a2b7 | 1646 | } |
78501eac | 1647 | |
753b1ad4 | 1648 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 1649 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 1650 | { |
b5321f30 | 1651 | int num_dwords = |
e6ba9992 | 1652 | (req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
73dec95e | 1653 | u32 *cs; |
753b1ad4 VS |
1654 | |
1655 | if (num_dwords == 0) | |
1656 | return 0; | |
1657 | ||
18393f63 | 1658 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
73dec95e TU |
1659 | cs = intel_ring_begin(req, num_dwords); |
1660 | if (IS_ERR(cs)) | |
1661 | return PTR_ERR(cs); | |
753b1ad4 VS |
1662 | |
1663 | while (num_dwords--) | |
73dec95e | 1664 | *cs++ = MI_NOOP; |
753b1ad4 | 1665 | |
73dec95e | 1666 | intel_ring_advance(req, cs); |
753b1ad4 VS |
1667 | |
1668 | return 0; | |
1669 | } | |
1670 | ||
c5efa1ad | 1671 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 1672 | { |
c5efa1ad | 1673 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1674 | |
76f8421f CW |
1675 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1676 | ||
881f47b6 | 1677 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1678 | |
1679 | /* Disable notification that the ring is IDLE. The GT | |
1680 | * will then assume that it is busy and bring it out of rc6. | |
1681 | */ | |
76f8421f CW |
1682 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1683 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1684 | |
1685 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1686 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1687 | |
12f55818 | 1688 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1689 | if (__intel_wait_for_register_fw(dev_priv, |
1690 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1691 | GEN6_BSD_SLEEP_INDICATOR, | |
1692 | 0, | |
1693 | 1000, 0, NULL)) | |
12f55818 | 1694 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1695 | |
12f55818 | 1696 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1697 | i9xx_submit_request(request); |
12f55818 CW |
1698 | |
1699 | /* Let the ring send IDLE messages to the GT again, | |
1700 | * and so let it sleep to conserve power when idle. | |
1701 | */ | |
76f8421f CW |
1702 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1703 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1704 | ||
1705 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1706 | } |
1707 | ||
7c9cf4e3 | 1708 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 1709 | { |
73dec95e | 1710 | u32 cmd, *cs; |
b72f3acb | 1711 | |
73dec95e TU |
1712 | cs = intel_ring_begin(req, 4); |
1713 | if (IS_ERR(cs)) | |
1714 | return PTR_ERR(cs); | |
b72f3acb | 1715 | |
71a77e07 | 1716 | cmd = MI_FLUSH_DW; |
c033666a | 1717 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1718 | cmd += 1; |
f0a1fb10 CW |
1719 | |
1720 | /* We always require a command barrier so that subsequent | |
1721 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1722 | * wrt the contents of the write cache being flushed to memory | |
1723 | * (and thus being coherent from the CPU). | |
1724 | */ | |
1725 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1726 | ||
9a289771 JB |
1727 | /* |
1728 | * Bspec vol 1c.5 - video engine command streamer: | |
1729 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1730 | * operation is complete. This bit is only valid when the | |
1731 | * Post-Sync Operation field is a value of 1h or 3h." | |
1732 | */ | |
7c9cf4e3 | 1733 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1734 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1735 | ||
73dec95e TU |
1736 | *cs++ = cmd; |
1737 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1738 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1739 | *cs++ = 0; /* upper addr */ |
1740 | *cs++ = 0; /* value */ | |
075b3bba | 1741 | } else { |
73dec95e TU |
1742 | *cs++ = 0; |
1743 | *cs++ = MI_NOOP; | |
075b3bba | 1744 | } |
73dec95e | 1745 | intel_ring_advance(req, cs); |
b72f3acb | 1746 | return 0; |
881f47b6 XH |
1747 | } |
1748 | ||
1c7a0623 | 1749 | static int |
803688ba CW |
1750 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
1751 | u64 offset, u32 len, | |
1752 | unsigned int dispatch_flags) | |
1c7a0623 | 1753 | { |
b5321f30 | 1754 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 1755 | !(dispatch_flags & I915_DISPATCH_SECURE); |
73dec95e | 1756 | u32 *cs; |
1c7a0623 | 1757 | |
73dec95e TU |
1758 | cs = intel_ring_begin(req, 4); |
1759 | if (IS_ERR(cs)) | |
1760 | return PTR_ERR(cs); | |
1c7a0623 BW |
1761 | |
1762 | /* FIXME(BDW): Address space and security selectors. */ | |
73dec95e TU |
1763 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & |
1764 | I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
1765 | *cs++ = lower_32_bits(offset); | |
1766 | *cs++ = upper_32_bits(offset); | |
1767 | *cs++ = MI_NOOP; | |
1768 | intel_ring_advance(req, cs); | |
1c7a0623 BW |
1769 | |
1770 | return 0; | |
1771 | } | |
1772 | ||
d7d4eedd | 1773 | static int |
803688ba CW |
1774 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
1775 | u64 offset, u32 len, | |
1776 | unsigned int dispatch_flags) | |
d7d4eedd | 1777 | { |
73dec95e | 1778 | u32 *cs; |
d7d4eedd | 1779 | |
73dec95e TU |
1780 | cs = intel_ring_begin(req, 2); |
1781 | if (IS_ERR(cs)) | |
1782 | return PTR_ERR(cs); | |
d7d4eedd | 1783 | |
73dec95e TU |
1784 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1785 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1786 | (dispatch_flags & I915_DISPATCH_RS ? | |
1787 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1788 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1789 | *cs++ = offset; |
1790 | intel_ring_advance(req, cs); | |
d7d4eedd CW |
1791 | |
1792 | return 0; | |
1793 | } | |
1794 | ||
881f47b6 | 1795 | static int |
803688ba CW |
1796 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
1797 | u64 offset, u32 len, | |
1798 | unsigned int dispatch_flags) | |
881f47b6 | 1799 | { |
73dec95e | 1800 | u32 *cs; |
ab6f8e32 | 1801 | |
73dec95e TU |
1802 | cs = intel_ring_begin(req, 2); |
1803 | if (IS_ERR(cs)) | |
1804 | return PTR_ERR(cs); | |
e1f99ce6 | 1805 | |
73dec95e TU |
1806 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1807 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1808 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1809 | *cs++ = offset; |
1810 | intel_ring_advance(req, cs); | |
ab6f8e32 | 1811 | |
0206e353 | 1812 | return 0; |
881f47b6 XH |
1813 | } |
1814 | ||
549f7365 CW |
1815 | /* Blitter support (SandyBridge+) */ |
1816 | ||
7c9cf4e3 | 1817 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 1818 | { |
73dec95e | 1819 | u32 cmd, *cs; |
b72f3acb | 1820 | |
73dec95e TU |
1821 | cs = intel_ring_begin(req, 4); |
1822 | if (IS_ERR(cs)) | |
1823 | return PTR_ERR(cs); | |
b72f3acb | 1824 | |
71a77e07 | 1825 | cmd = MI_FLUSH_DW; |
c033666a | 1826 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1827 | cmd += 1; |
f0a1fb10 CW |
1828 | |
1829 | /* We always require a command barrier so that subsequent | |
1830 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1831 | * wrt the contents of the write cache being flushed to memory | |
1832 | * (and thus being coherent from the CPU). | |
1833 | */ | |
1834 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1835 | ||
9a289771 JB |
1836 | /* |
1837 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1838 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1839 | * operation is complete. This bit is only valid when the | |
1840 | * Post-Sync Operation field is a value of 1h or 3h." | |
1841 | */ | |
7c9cf4e3 | 1842 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1843 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1844 | *cs++ = cmd; |
1845 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1846 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1847 | *cs++ = 0; /* upper addr */ |
1848 | *cs++ = 0; /* value */ | |
075b3bba | 1849 | } else { |
73dec95e TU |
1850 | *cs++ = 0; |
1851 | *cs++ = MI_NOOP; | |
075b3bba | 1852 | } |
73dec95e | 1853 | intel_ring_advance(req, cs); |
fd3da6c9 | 1854 | |
b72f3acb | 1855 | return 0; |
8d19215b ZN |
1856 | } |
1857 | ||
d9a64610 TU |
1858 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1859 | struct intel_engine_cs *engine) | |
1860 | { | |
db3d4019 | 1861 | struct drm_i915_gem_object *obj; |
1b9e6650 | 1862 | int ret, i; |
db3d4019 | 1863 | |
39df9190 | 1864 | if (!i915.semaphores) |
db3d4019 TU |
1865 | return; |
1866 | ||
51d545d0 CW |
1867 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
1868 | struct i915_vma *vma; | |
1869 | ||
f51455d4 | 1870 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
1871 | if (IS_ERR(obj)) |
1872 | goto err; | |
db3d4019 | 1873 | |
a01cb37a | 1874 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
1875 | if (IS_ERR(vma)) |
1876 | goto err_obj; | |
1877 | ||
1878 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1879 | if (ret) | |
1880 | goto err_obj; | |
1881 | ||
1882 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1883 | if (ret) | |
1884 | goto err_obj; | |
1885 | ||
1886 | dev_priv->semaphore = vma; | |
1887 | } | |
d9a64610 TU |
1888 | |
1889 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 1890 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 1891 | |
ad7bdb2b | 1892 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 1893 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
1894 | |
1895 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 1896 | u32 ring_offset; |
1b9e6650 TU |
1897 | |
1898 | if (i != engine->id) | |
1899 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
1900 | else | |
1901 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
1902 | ||
1903 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
1904 | } | |
d9a64610 | 1905 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 1906 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 1907 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
1908 | |
1909 | /* | |
1910 | * The current semaphore is only applied on pre-gen8 | |
1911 | * platform. And there is no VCS2 ring on the pre-gen8 | |
1912 | * platform. So the semaphore between RCS and VCS2 is | |
1913 | * initialized as INVALID. Gen8 will initialize the | |
1914 | * sema between VCS2 and RCS later. | |
1915 | */ | |
318f89ca | 1916 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
1917 | static const struct { |
1918 | u32 wait_mbox; | |
1919 | i915_reg_t mbox_reg; | |
318f89ca TU |
1920 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
1921 | [RCS_HW] = { | |
1922 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
1923 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
1924 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 1925 | }, |
318f89ca TU |
1926 | [VCS_HW] = { |
1927 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
1928 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
1929 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 1930 | }, |
318f89ca TU |
1931 | [BCS_HW] = { |
1932 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
1933 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
1934 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 1935 | }, |
318f89ca TU |
1936 | [VECS_HW] = { |
1937 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
1938 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
1939 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
1940 | }, |
1941 | }; | |
1942 | u32 wait_mbox; | |
1943 | i915_reg_t mbox_reg; | |
1944 | ||
318f89ca | 1945 | if (i == engine->hw_id) { |
4b8e38a9 TU |
1946 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
1947 | mbox_reg = GEN6_NOSYNC; | |
1948 | } else { | |
318f89ca TU |
1949 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
1950 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
1951 | } |
1952 | ||
1953 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
1954 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
1955 | } | |
d9a64610 | 1956 | } |
51d545d0 CW |
1957 | |
1958 | return; | |
1959 | ||
1960 | err_obj: | |
1961 | i915_gem_object_put(obj); | |
1962 | err: | |
1963 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
1964 | i915.semaphores = 0; | |
d9a64610 TU |
1965 | } |
1966 | ||
ed003078 CW |
1967 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
1968 | struct intel_engine_cs *engine) | |
1969 | { | |
c78d6061 TU |
1970 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
1971 | ||
ed003078 | 1972 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
1973 | engine->irq_enable = gen8_irq_enable; |
1974 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
1975 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
1976 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
1977 | engine->irq_enable = gen6_irq_enable; |
1978 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
1979 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
1980 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
1981 | engine->irq_enable = gen5_irq_enable; |
1982 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 1983 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 1984 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
1985 | engine->irq_enable = i9xx_irq_enable; |
1986 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 1987 | } else { |
31bb59cc CW |
1988 | engine->irq_enable = i8xx_irq_enable; |
1989 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
1990 | } |
1991 | } | |
1992 | ||
ff44ad51 CW |
1993 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
1994 | { | |
1995 | engine->submit_request = i9xx_submit_request; | |
1996 | } | |
1997 | ||
1998 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
1999 | { | |
2000 | engine->submit_request = gen6_bsd_submit_request; | |
2001 | } | |
2002 | ||
06a2fe22 TU |
2003 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2004 | struct intel_engine_cs *engine) | |
2005 | { | |
618e4ca7 CW |
2006 | intel_ring_init_irq(dev_priv, engine); |
2007 | intel_ring_init_semaphores(dev_priv, engine); | |
2008 | ||
1d8a1337 | 2009 | engine->init_hw = init_ring_common; |
821ed7df | 2010 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2011 | |
e8a9c58f CW |
2012 | engine->context_pin = intel_ring_context_pin; |
2013 | engine->context_unpin = intel_ring_context_unpin; | |
2014 | ||
f73e7399 CW |
2015 | engine->request_alloc = ring_request_alloc; |
2016 | ||
9b81d556 | 2017 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d CW |
2018 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
2019 | if (i915.semaphores) { | |
2020 | int num_rings; | |
2021 | ||
9b81d556 | 2022 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d | 2023 | |
c58949f4 | 2024 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
98f29e8d CW |
2025 | if (INTEL_GEN(dev_priv) >= 8) { |
2026 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2027 | } else { | |
2028 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2029 | if (num_rings & 1) | |
2030 | engine->emit_breadcrumb_sz++; | |
2031 | } | |
2032 | } | |
ff44ad51 CW |
2033 | |
2034 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 CW |
2035 | |
2036 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2037 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2038 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2039 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2040 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2041 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2042 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2043 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2044 | else |
803688ba | 2045 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2046 | } |
2047 | ||
8b3e2d36 | 2048 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2049 | { |
8b3e2d36 | 2050 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2051 | int ret; |
5c1143bb | 2052 | |
06a2fe22 TU |
2053 | intel_ring_default_vfuncs(dev_priv, engine); |
2054 | ||
61ff75ac CW |
2055 | if (HAS_L3_DPF(dev_priv)) |
2056 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2057 | |
c033666a | 2058 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2059 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2060 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2061 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2062 | engine->emit_flush = gen8_render_ring_flush; |
98f29e8d CW |
2063 | if (i915.semaphores) { |
2064 | int num_rings; | |
2065 | ||
e2f80391 | 2066 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d | 2067 | |
c58949f4 | 2068 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
6f9b850b | 2069 | engine->emit_breadcrumb_sz += num_rings * 8; |
98f29e8d | 2070 | } |
c033666a | 2071 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2072 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2073 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2074 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2075 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2076 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2077 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2078 | } else { |
c033666a | 2079 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2080 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2081 | else |
c7fe7d25 | 2082 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2083 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2084 | } |
707d9cf9 | 2085 | |
c033666a | 2086 | if (IS_HASWELL(dev_priv)) |
803688ba | 2087 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2088 | |
e2f80391 TU |
2089 | engine->init_hw = init_render_ring; |
2090 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2091 | |
acd27845 | 2092 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2093 | if (ret) |
2094 | return ret; | |
2095 | ||
f8973c21 | 2096 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2097 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2098 | if (ret) |
2099 | return ret; | |
2100 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2101 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2102 | if (ret) |
2103 | return ret; | |
2104 | } | |
2105 | ||
2106 | return 0; | |
5c1143bb XH |
2107 | } |
2108 | ||
8b3e2d36 | 2109 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2110 | { |
8b3e2d36 | 2111 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2112 | |
06a2fe22 TU |
2113 | intel_ring_default_vfuncs(dev_priv, engine); |
2114 | ||
c033666a | 2115 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2116 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2117 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2118 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2119 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2120 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2121 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2122 | } else { |
e2f80391 | 2123 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2124 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2125 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2126 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2127 | else |
e2f80391 | 2128 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2129 | } |
58fa3835 | 2130 | |
acd27845 | 2131 | return intel_init_ring_buffer(engine); |
5c1143bb | 2132 | } |
549f7365 | 2133 | |
8b3e2d36 | 2134 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2135 | { |
8b3e2d36 | 2136 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2137 | |
2138 | intel_ring_default_vfuncs(dev_priv, engine); | |
2139 | ||
c7fe7d25 | 2140 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2141 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2142 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2143 | |
acd27845 | 2144 | return intel_init_ring_buffer(engine); |
549f7365 | 2145 | } |
a7b9761d | 2146 | |
8b3e2d36 | 2147 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2148 | { |
8b3e2d36 | 2149 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2150 | |
2151 | intel_ring_default_vfuncs(dev_priv, engine); | |
2152 | ||
c7fe7d25 | 2153 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2154 | |
c78d6061 | 2155 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2156 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2157 | engine->irq_enable = hsw_vebox_irq_enable; |
2158 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2159 | } |
9a8a2213 | 2160 | |
acd27845 | 2161 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2162 | } |