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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
8d315287 JB |
37 | /* |
38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
39 | * over cache flushing. | |
40 | */ | |
41 | struct pipe_control { | |
42 | struct drm_i915_gem_object *obj; | |
43 | volatile u32 *cpu_page; | |
44 | u32 gtt_offset; | |
45 | }; | |
46 | ||
c7dca47b CW |
47 | static inline int ring_space(struct intel_ring_buffer *ring) |
48 | { | |
49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
50 | if (space < 0) | |
51 | space += ring->size; | |
52 | return space; | |
53 | } | |
54 | ||
b72f3acb | 55 | static int |
46f0f8d1 CW |
56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
57 | u32 invalidate_domains, | |
58 | u32 flush_domains) | |
59 | { | |
60 | u32 cmd; | |
61 | int ret; | |
62 | ||
63 | cmd = MI_FLUSH; | |
31b14c9f | 64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
65 | cmd |= MI_NO_WRITE_FLUSH; |
66 | ||
67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
68 | cmd |= MI_READ_FLUSH; | |
69 | ||
70 | ret = intel_ring_begin(ring, 2); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | intel_ring_emit(ring, cmd); | |
75 | intel_ring_emit(ring, MI_NOOP); | |
76 | intel_ring_advance(ring); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int | |
82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
83 | u32 invalidate_domains, | |
84 | u32 flush_domains) | |
62fdfeaf | 85 | { |
78501eac | 86 | struct drm_device *dev = ring->dev; |
6f392d54 | 87 | u32 cmd; |
b72f3acb | 88 | int ret; |
6f392d54 | 89 | |
36d527de CW |
90 | /* |
91 | * read/write caches: | |
92 | * | |
93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
95 | * also flushed at 2d versus 3d pipeline switches. | |
96 | * | |
97 | * read-only caches: | |
98 | * | |
99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
100 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
101 | * | |
102 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
103 | * | |
104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
105 | * invalidated when MI_EXE_FLUSH is set. | |
106 | * | |
107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
108 | * invalidated with every MI_FLUSH. | |
109 | * | |
110 | * TLBs: | |
111 | * | |
112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
115 | * are flushed at any MI_FLUSH. | |
116 | */ | |
117 | ||
118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 120 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
122 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 123 | |
36d527de CW |
124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
125 | (IS_G4X(dev) || IS_GEN5(dev))) | |
126 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 127 | |
36d527de CW |
128 | ret = intel_ring_begin(ring, 2); |
129 | if (ret) | |
130 | return ret; | |
b72f3acb | 131 | |
36d527de CW |
132 | intel_ring_emit(ring, cmd); |
133 | intel_ring_emit(ring, MI_NOOP); | |
134 | intel_ring_advance(ring); | |
b72f3acb CW |
135 | |
136 | return 0; | |
8187a2b7 ZN |
137 | } |
138 | ||
8d315287 JB |
139 | /** |
140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
141 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
143 | * | |
144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
145 | * produced by non-pipelined state commands), software needs to first | |
146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
147 | * 0. | |
148 | * | |
149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
151 | * | |
152 | * And the workaround for these two requires this workaround first: | |
153 | * | |
154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
155 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
156 | * flushes. | |
157 | * | |
158 | * And this last workaround is tricky because of the requirements on | |
159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
160 | * volume 2 part 1: | |
161 | * | |
162 | * "1 of the following must also be set: | |
163 | * - Render Target Cache Flush Enable ([12] of DW1) | |
164 | * - Depth Cache Flush Enable ([0] of DW1) | |
165 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
166 | * - Depth Stall ([13] of DW1) | |
167 | * - Post-Sync Operation ([13] of DW1) | |
168 | * - Notify Enable ([8] of DW1)" | |
169 | * | |
170 | * The cache flushes require the workaround flush that triggered this | |
171 | * one, so we can't use it. Depth stall would trigger the same. | |
172 | * Post-sync nonzero is what triggered this second workaround, so we | |
173 | * can't use that one either. Notify enable is IRQs, which aren't | |
174 | * really our business. That leaves only stall at scoreboard. | |
175 | */ | |
176 | static int | |
177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
178 | { | |
179 | struct pipe_control *pc = ring->private; | |
180 | u32 scratch_addr = pc->gtt_offset + 128; | |
181 | int ret; | |
182 | ||
183 | ||
184 | ret = intel_ring_begin(ring, 6); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
189 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
190 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
192 | intel_ring_emit(ring, 0); /* low dword */ | |
193 | intel_ring_emit(ring, 0); /* high dword */ | |
194 | intel_ring_emit(ring, MI_NOOP); | |
195 | intel_ring_advance(ring); | |
196 | ||
197 | ret = intel_ring_begin(ring, 6); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
202 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
204 | intel_ring_emit(ring, 0); | |
205 | intel_ring_emit(ring, 0); | |
206 | intel_ring_emit(ring, MI_NOOP); | |
207 | intel_ring_advance(ring); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
213 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
214 | u32 invalidate_domains, u32 flush_domains) | |
215 | { | |
216 | u32 flags = 0; | |
217 | struct pipe_control *pc = ring->private; | |
218 | u32 scratch_addr = pc->gtt_offset + 128; | |
219 | int ret; | |
220 | ||
8d315287 JB |
221 | /* Just flush everything. Experiments have shown that reducing the |
222 | * number of bits based on the write domains has little performance | |
223 | * impact. | |
224 | */ | |
7d54a904 CW |
225 | if (flush_domains) { |
226 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
227 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
228 | /* | |
229 | * Ensure that any following seqno writes only happen | |
230 | * when the render cache is indeed flushed. | |
231 | */ | |
97f209bc | 232 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
233 | } |
234 | if (invalidate_domains) { | |
235 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
236 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
237 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
241 | /* | |
242 | * TLB invalidate requires a post-sync write. | |
243 | */ | |
244 | flags |= PIPE_CONTROL_QW_WRITE; | |
245 | } | |
8d315287 | 246 | |
6c6cf5aa | 247 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
248 | if (ret) |
249 | return ret; | |
250 | ||
6c6cf5aa | 251 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
252 | intel_ring_emit(ring, flags); |
253 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 254 | intel_ring_emit(ring, 0); |
8d315287 JB |
255 | intel_ring_advance(ring); |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
4772eaeb PZ |
260 | static int |
261 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
262 | u32 invalidate_domains, u32 flush_domains) | |
263 | { | |
264 | u32 flags = 0; | |
265 | struct pipe_control *pc = ring->private; | |
266 | u32 scratch_addr = pc->gtt_offset + 128; | |
267 | int ret; | |
268 | ||
269 | /* Just flush everything. Experiments have shown that reducing the | |
270 | * number of bits based on the write domains has little performance | |
271 | * impact. | |
272 | */ | |
273 | if (flush_domains) { | |
274 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
275 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
276 | /* | |
277 | * Ensure that any following seqno writes only happen | |
278 | * when the render cache is indeed flushed. | |
279 | */ | |
280 | flags |= PIPE_CONTROL_CS_STALL; | |
281 | } | |
282 | if (invalidate_domains) { | |
283 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
284 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
285 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
286 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
287 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
288 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
289 | /* | |
290 | * TLB invalidate requires a post-sync write. | |
291 | */ | |
292 | flags |= PIPE_CONTROL_QW_WRITE; | |
293 | } | |
294 | ||
295 | ret = intel_ring_begin(ring, 4); | |
296 | if (ret) | |
297 | return ret; | |
298 | ||
299 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
300 | intel_ring_emit(ring, flags); | |
301 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
302 | intel_ring_emit(ring, 0); | |
303 | intel_ring_advance(ring); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
6c6cf5aa CW |
308 | static int |
309 | gen6_render_ring_flush__wa(struct intel_ring_buffer *ring, | |
310 | u32 invalidate_domains, u32 flush_domains) | |
311 | { | |
312 | int ret; | |
313 | ||
314 | /* Force SNB workarounds for PIPE_CONTROL flushes */ | |
315 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
316 | if (ret) | |
317 | return ret; | |
318 | ||
319 | return gen6_render_ring_flush(ring, invalidate_domains, flush_domains); | |
320 | } | |
321 | ||
78501eac | 322 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 323 | u32 value) |
d46eefa2 | 324 | { |
78501eac | 325 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 326 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
327 | } |
328 | ||
78501eac | 329 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 330 | { |
78501eac CW |
331 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
332 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 333 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
334 | |
335 | return I915_READ(acthd_reg); | |
336 | } | |
337 | ||
78501eac | 338 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 339 | { |
b7884eb4 DV |
340 | struct drm_device *dev = ring->dev; |
341 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 342 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 343 | int ret = 0; |
8187a2b7 | 344 | u32 head; |
8187a2b7 | 345 | |
b7884eb4 DV |
346 | if (HAS_FORCE_WAKE(dev)) |
347 | gen6_gt_force_wake_get(dev_priv); | |
348 | ||
8187a2b7 | 349 | /* Stop the ring if it's running. */ |
7f2ab699 | 350 | I915_WRITE_CTL(ring, 0); |
570ef608 | 351 | I915_WRITE_HEAD(ring, 0); |
78501eac | 352 | ring->write_tail(ring, 0); |
8187a2b7 | 353 | |
570ef608 | 354 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
355 | |
356 | /* G45 ring initialization fails to reset head to zero */ | |
357 | if (head != 0) { | |
6fd0d56e CW |
358 | DRM_DEBUG_KMS("%s head not reset to zero " |
359 | "ctl %08x head %08x tail %08x start %08x\n", | |
360 | ring->name, | |
361 | I915_READ_CTL(ring), | |
362 | I915_READ_HEAD(ring), | |
363 | I915_READ_TAIL(ring), | |
364 | I915_READ_START(ring)); | |
8187a2b7 | 365 | |
570ef608 | 366 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 367 | |
6fd0d56e CW |
368 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
369 | DRM_ERROR("failed to set %s head to zero " | |
370 | "ctl %08x head %08x tail %08x start %08x\n", | |
371 | ring->name, | |
372 | I915_READ_CTL(ring), | |
373 | I915_READ_HEAD(ring), | |
374 | I915_READ_TAIL(ring), | |
375 | I915_READ_START(ring)); | |
376 | } | |
8187a2b7 ZN |
377 | } |
378 | ||
0d8957c8 DV |
379 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
380 | * registers with the above sequence (the readback of the HEAD registers | |
381 | * also enforces ordering), otherwise the hw might lose the new ring | |
382 | * register values. */ | |
383 | I915_WRITE_START(ring, obj->gtt_offset); | |
7f2ab699 | 384 | I915_WRITE_CTL(ring, |
ae69b42a | 385 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 386 | | RING_VALID); |
8187a2b7 | 387 | |
8187a2b7 | 388 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
389 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
390 | I915_READ_START(ring) == obj->gtt_offset && | |
391 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
392 | DRM_ERROR("%s initialization failed " |
393 | "ctl %08x head %08x tail %08x start %08x\n", | |
394 | ring->name, | |
395 | I915_READ_CTL(ring), | |
396 | I915_READ_HEAD(ring), | |
397 | I915_READ_TAIL(ring), | |
398 | I915_READ_START(ring)); | |
b7884eb4 DV |
399 | ret = -EIO; |
400 | goto out; | |
8187a2b7 ZN |
401 | } |
402 | ||
78501eac CW |
403 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
404 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 405 | else { |
c7dca47b | 406 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 407 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 408 | ring->space = ring_space(ring); |
c3b20037 | 409 | ring->last_retired_head = -1; |
8187a2b7 | 410 | } |
1ec14ad3 | 411 | |
b7884eb4 DV |
412 | out: |
413 | if (HAS_FORCE_WAKE(dev)) | |
414 | gen6_gt_force_wake_put(dev_priv); | |
415 | ||
416 | return ret; | |
8187a2b7 ZN |
417 | } |
418 | ||
c6df541c CW |
419 | static int |
420 | init_pipe_control(struct intel_ring_buffer *ring) | |
421 | { | |
422 | struct pipe_control *pc; | |
423 | struct drm_i915_gem_object *obj; | |
424 | int ret; | |
425 | ||
426 | if (ring->private) | |
427 | return 0; | |
428 | ||
429 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
430 | if (!pc) | |
431 | return -ENOMEM; | |
432 | ||
433 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
434 | if (obj == NULL) { | |
435 | DRM_ERROR("Failed to allocate seqno page\n"); | |
436 | ret = -ENOMEM; | |
437 | goto err; | |
438 | } | |
e4ffd173 CW |
439 | |
440 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c | 441 | |
86a1ee26 | 442 | ret = i915_gem_object_pin(obj, 4096, true, false); |
c6df541c CW |
443 | if (ret) |
444 | goto err_unref; | |
445 | ||
446 | pc->gtt_offset = obj->gtt_offset; | |
447 | pc->cpu_page = kmap(obj->pages[0]); | |
448 | if (pc->cpu_page == NULL) | |
449 | goto err_unpin; | |
450 | ||
451 | pc->obj = obj; | |
452 | ring->private = pc; | |
453 | return 0; | |
454 | ||
455 | err_unpin: | |
456 | i915_gem_object_unpin(obj); | |
457 | err_unref: | |
458 | drm_gem_object_unreference(&obj->base); | |
459 | err: | |
460 | kfree(pc); | |
461 | return ret; | |
462 | } | |
463 | ||
464 | static void | |
465 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
466 | { | |
467 | struct pipe_control *pc = ring->private; | |
468 | struct drm_i915_gem_object *obj; | |
469 | ||
470 | if (!ring->private) | |
471 | return; | |
472 | ||
473 | obj = pc->obj; | |
474 | kunmap(obj->pages[0]); | |
475 | i915_gem_object_unpin(obj); | |
476 | drm_gem_object_unreference(&obj->base); | |
477 | ||
478 | kfree(pc); | |
479 | ring->private = NULL; | |
480 | } | |
481 | ||
78501eac | 482 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 483 | { |
78501eac | 484 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 485 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 486 | int ret = init_ring_common(ring); |
a69ffdbf | 487 | |
a6c45cf0 | 488 | if (INTEL_INFO(dev)->gen > 3) { |
6b26c86d | 489 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
b095cd0a JB |
490 | if (IS_GEN7(dev)) |
491 | I915_WRITE(GFX_MODE_GEN7, | |
6b26c86d DV |
492 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
493 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 494 | } |
78501eac | 495 | |
8d315287 | 496 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
497 | ret = init_pipe_control(ring); |
498 | if (ret) | |
499 | return ret; | |
500 | } | |
501 | ||
5e13a0c5 | 502 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
503 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
504 | * "If this bit is set, STCunit will have LRA as replacement | |
505 | * policy. [...] This bit must be reset. LRA replacement | |
506 | * policy is not supported." | |
507 | */ | |
508 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 509 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
510 | |
511 | /* This is not explicitly set for GEN6, so read the register. | |
512 | * see intel_ring_mi_set_context() for why we care. | |
513 | * TODO: consider explicitly setting the bit for GEN5 | |
514 | */ | |
515 | ring->itlb_before_ctx_switch = | |
516 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
517 | } |
518 | ||
6b26c86d DV |
519 | if (INTEL_INFO(dev)->gen >= 6) |
520 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 521 | |
e1ef7cc2 | 522 | if (HAS_L3_GPU_CACHE(dev)) |
15b9f80e BW |
523 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
524 | ||
8187a2b7 ZN |
525 | return ret; |
526 | } | |
527 | ||
c6df541c CW |
528 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
529 | { | |
530 | if (!ring->private) | |
531 | return; | |
532 | ||
533 | cleanup_pipe_control(ring); | |
534 | } | |
535 | ||
1ec14ad3 | 536 | static void |
c8c99b0f BW |
537 | update_mboxes(struct intel_ring_buffer *ring, |
538 | u32 seqno, | |
539 | u32 mmio_offset) | |
1ec14ad3 | 540 | { |
c8c99b0f BW |
541 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
542 | MI_SEMAPHORE_GLOBAL_GTT | | |
543 | MI_SEMAPHORE_REGISTER | | |
544 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 545 | intel_ring_emit(ring, seqno); |
c8c99b0f | 546 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
547 | } |
548 | ||
c8c99b0f BW |
549 | /** |
550 | * gen6_add_request - Update the semaphore mailbox registers | |
551 | * | |
552 | * @ring - ring that is adding a request | |
553 | * @seqno - return seqno stuck into the ring | |
554 | * | |
555 | * Update the mailbox registers in the *other* rings with the current seqno. | |
556 | * This acts like a signal in the canonical semaphore. | |
557 | */ | |
1ec14ad3 CW |
558 | static int |
559 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 560 | u32 *seqno) |
1ec14ad3 | 561 | { |
c8c99b0f BW |
562 | u32 mbox1_reg; |
563 | u32 mbox2_reg; | |
1ec14ad3 CW |
564 | int ret; |
565 | ||
566 | ret = intel_ring_begin(ring, 10); | |
567 | if (ret) | |
568 | return ret; | |
569 | ||
c8c99b0f BW |
570 | mbox1_reg = ring->signal_mbox[0]; |
571 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 572 | |
53d227f2 | 573 | *seqno = i915_gem_next_request_seqno(ring); |
c8c99b0f BW |
574 | |
575 | update_mboxes(ring, *seqno, mbox1_reg); | |
576 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
577 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
578 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 579 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
580 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
581 | intel_ring_advance(ring); | |
582 | ||
1ec14ad3 CW |
583 | return 0; |
584 | } | |
585 | ||
c8c99b0f BW |
586 | /** |
587 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
588 | * | |
589 | * @waiter - ring that is waiting | |
590 | * @signaller - ring which has, or will signal | |
591 | * @seqno - seqno which the waiter will block on | |
592 | */ | |
593 | static int | |
686cb5f9 DV |
594 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
595 | struct intel_ring_buffer *signaller, | |
596 | u32 seqno) | |
1ec14ad3 CW |
597 | { |
598 | int ret; | |
c8c99b0f BW |
599 | u32 dw1 = MI_SEMAPHORE_MBOX | |
600 | MI_SEMAPHORE_COMPARE | | |
601 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 602 | |
1500f7ea BW |
603 | /* Throughout all of the GEM code, seqno passed implies our current |
604 | * seqno is >= the last seqno executed. However for hardware the | |
605 | * comparison is strictly greater than. | |
606 | */ | |
607 | seqno -= 1; | |
608 | ||
686cb5f9 DV |
609 | WARN_ON(signaller->semaphore_register[waiter->id] == |
610 | MI_SEMAPHORE_SYNC_INVALID); | |
611 | ||
c8c99b0f | 612 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
613 | if (ret) |
614 | return ret; | |
615 | ||
686cb5f9 DV |
616 | intel_ring_emit(waiter, |
617 | dw1 | signaller->semaphore_register[waiter->id]); | |
c8c99b0f BW |
618 | intel_ring_emit(waiter, seqno); |
619 | intel_ring_emit(waiter, 0); | |
620 | intel_ring_emit(waiter, MI_NOOP); | |
621 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
622 | |
623 | return 0; | |
624 | } | |
625 | ||
c6df541c CW |
626 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
627 | do { \ | |
fcbc34e4 KG |
628 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
629 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
630 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
631 | intel_ring_emit(ring__, 0); \ | |
632 | intel_ring_emit(ring__, 0); \ | |
633 | } while (0) | |
634 | ||
635 | static int | |
636 | pc_render_add_request(struct intel_ring_buffer *ring, | |
637 | u32 *result) | |
638 | { | |
53d227f2 | 639 | u32 seqno = i915_gem_next_request_seqno(ring); |
c6df541c CW |
640 | struct pipe_control *pc = ring->private; |
641 | u32 scratch_addr = pc->gtt_offset + 128; | |
642 | int ret; | |
643 | ||
644 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
645 | * incoherent with writes to memory, i.e. completely fubar, | |
646 | * so we need to use PIPE_NOTIFY instead. | |
647 | * | |
648 | * However, we also need to workaround the qword write | |
649 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
650 | * memory before requesting an interrupt. | |
651 | */ | |
652 | ret = intel_ring_begin(ring, 32); | |
653 | if (ret) | |
654 | return ret; | |
655 | ||
fcbc34e4 | 656 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
657 | PIPE_CONTROL_WRITE_FLUSH | |
658 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c CW |
659 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
660 | intel_ring_emit(ring, seqno); | |
661 | intel_ring_emit(ring, 0); | |
662 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
663 | scratch_addr += 128; /* write to separate cachelines */ | |
664 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
665 | scratch_addr += 128; | |
666 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
667 | scratch_addr += 128; | |
668 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
669 | scratch_addr += 128; | |
670 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
671 | scratch_addr += 128; | |
672 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 673 | |
fcbc34e4 | 674 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
675 | PIPE_CONTROL_WRITE_FLUSH | |
676 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
677 | PIPE_CONTROL_NOTIFY); |
678 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
679 | intel_ring_emit(ring, seqno); | |
680 | intel_ring_emit(ring, 0); | |
681 | intel_ring_advance(ring); | |
682 | ||
683 | *result = seqno; | |
684 | return 0; | |
685 | } | |
686 | ||
4cd53c0c | 687 | static u32 |
b2eadbc8 | 688 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 689 | { |
4cd53c0c DV |
690 | /* Workaround to force correct ordering between irq and seqno writes on |
691 | * ivb (and maybe also on snb) by reading from a CS register (like | |
692 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 693 | if (!lazy_coherency) |
4cd53c0c DV |
694 | intel_ring_get_active_head(ring); |
695 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
696 | } | |
697 | ||
8187a2b7 | 698 | static u32 |
b2eadbc8 | 699 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 700 | { |
1ec14ad3 CW |
701 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
702 | } | |
703 | ||
c6df541c | 704 | static u32 |
b2eadbc8 | 705 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c CW |
706 | { |
707 | struct pipe_control *pc = ring->private; | |
708 | return pc->cpu_page[0]; | |
709 | } | |
710 | ||
e48d8634 DV |
711 | static bool |
712 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
713 | { | |
714 | struct drm_device *dev = ring->dev; | |
715 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 716 | unsigned long flags; |
e48d8634 DV |
717 | |
718 | if (!dev->irq_enabled) | |
719 | return false; | |
720 | ||
7338aefa | 721 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
722 | if (ring->irq_refcount++ == 0) { |
723 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; | |
724 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
725 | POSTING_READ(GTIMR); | |
726 | } | |
7338aefa | 727 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
728 | |
729 | return true; | |
730 | } | |
731 | ||
732 | static void | |
733 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
734 | { | |
735 | struct drm_device *dev = ring->dev; | |
736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 737 | unsigned long flags; |
e48d8634 | 738 | |
7338aefa | 739 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
740 | if (--ring->irq_refcount == 0) { |
741 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; | |
742 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
743 | POSTING_READ(GTIMR); | |
744 | } | |
7338aefa | 745 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
746 | } |
747 | ||
b13c2b96 | 748 | static bool |
e3670319 | 749 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 750 | { |
78501eac | 751 | struct drm_device *dev = ring->dev; |
01a03331 | 752 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 753 | unsigned long flags; |
62fdfeaf | 754 | |
b13c2b96 CW |
755 | if (!dev->irq_enabled) |
756 | return false; | |
757 | ||
7338aefa | 758 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
759 | if (ring->irq_refcount++ == 0) { |
760 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
761 | I915_WRITE(IMR, dev_priv->irq_mask); | |
762 | POSTING_READ(IMR); | |
763 | } | |
7338aefa | 764 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
765 | |
766 | return true; | |
62fdfeaf EA |
767 | } |
768 | ||
8187a2b7 | 769 | static void |
e3670319 | 770 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 771 | { |
78501eac | 772 | struct drm_device *dev = ring->dev; |
01a03331 | 773 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 774 | unsigned long flags; |
62fdfeaf | 775 | |
7338aefa | 776 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
777 | if (--ring->irq_refcount == 0) { |
778 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
779 | I915_WRITE(IMR, dev_priv->irq_mask); | |
780 | POSTING_READ(IMR); | |
781 | } | |
7338aefa | 782 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
783 | } |
784 | ||
c2798b19 CW |
785 | static bool |
786 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
787 | { | |
788 | struct drm_device *dev = ring->dev; | |
789 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 790 | unsigned long flags; |
c2798b19 CW |
791 | |
792 | if (!dev->irq_enabled) | |
793 | return false; | |
794 | ||
7338aefa | 795 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
796 | if (ring->irq_refcount++ == 0) { |
797 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
798 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
799 | POSTING_READ16(IMR); | |
800 | } | |
7338aefa | 801 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
802 | |
803 | return true; | |
804 | } | |
805 | ||
806 | static void | |
807 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
808 | { | |
809 | struct drm_device *dev = ring->dev; | |
810 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 811 | unsigned long flags; |
c2798b19 | 812 | |
7338aefa | 813 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
814 | if (--ring->irq_refcount == 0) { |
815 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
816 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
817 | POSTING_READ16(IMR); | |
818 | } | |
7338aefa | 819 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
820 | } |
821 | ||
78501eac | 822 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 823 | { |
4593010b | 824 | struct drm_device *dev = ring->dev; |
78501eac | 825 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
826 | u32 mmio = 0; |
827 | ||
828 | /* The ring status page addresses are no longer next to the rest of | |
829 | * the ring registers as of gen7. | |
830 | */ | |
831 | if (IS_GEN7(dev)) { | |
832 | switch (ring->id) { | |
96154f2f | 833 | case RCS: |
4593010b EA |
834 | mmio = RENDER_HWS_PGA_GEN7; |
835 | break; | |
96154f2f | 836 | case BCS: |
4593010b EA |
837 | mmio = BLT_HWS_PGA_GEN7; |
838 | break; | |
96154f2f | 839 | case VCS: |
4593010b EA |
840 | mmio = BSD_HWS_PGA_GEN7; |
841 | break; | |
842 | } | |
843 | } else if (IS_GEN6(ring->dev)) { | |
844 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
845 | } else { | |
846 | mmio = RING_HWS_PGA(ring->mmio_base); | |
847 | } | |
848 | ||
78501eac CW |
849 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
850 | POSTING_READ(mmio); | |
8187a2b7 ZN |
851 | } |
852 | ||
b72f3acb | 853 | static int |
78501eac CW |
854 | bsd_ring_flush(struct intel_ring_buffer *ring, |
855 | u32 invalidate_domains, | |
856 | u32 flush_domains) | |
d1b851fc | 857 | { |
b72f3acb CW |
858 | int ret; |
859 | ||
b72f3acb CW |
860 | ret = intel_ring_begin(ring, 2); |
861 | if (ret) | |
862 | return ret; | |
863 | ||
864 | intel_ring_emit(ring, MI_FLUSH); | |
865 | intel_ring_emit(ring, MI_NOOP); | |
866 | intel_ring_advance(ring); | |
867 | return 0; | |
d1b851fc ZN |
868 | } |
869 | ||
3cce469c | 870 | static int |
8620a3a9 | 871 | i9xx_add_request(struct intel_ring_buffer *ring, |
3cce469c | 872 | u32 *result) |
d1b851fc ZN |
873 | { |
874 | u32 seqno; | |
3cce469c CW |
875 | int ret; |
876 | ||
877 | ret = intel_ring_begin(ring, 4); | |
878 | if (ret) | |
879 | return ret; | |
6f392d54 | 880 | |
53d227f2 | 881 | seqno = i915_gem_next_request_seqno(ring); |
6f392d54 | 882 | |
3cce469c CW |
883 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
884 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
885 | intel_ring_emit(ring, seqno); | |
886 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
887 | intel_ring_advance(ring); | |
d1b851fc | 888 | |
3cce469c CW |
889 | *result = seqno; |
890 | return 0; | |
d1b851fc ZN |
891 | } |
892 | ||
0f46832f | 893 | static bool |
25c06300 | 894 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
895 | { |
896 | struct drm_device *dev = ring->dev; | |
01a03331 | 897 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 898 | unsigned long flags; |
0f46832f CW |
899 | |
900 | if (!dev->irq_enabled) | |
901 | return false; | |
902 | ||
4cd53c0c DV |
903 | /* It looks like we need to prevent the gt from suspending while waiting |
904 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
905 | * blt/bsd rings on ivb. */ | |
99ffa162 | 906 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 907 | |
7338aefa | 908 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 909 | if (ring->irq_refcount++ == 0) { |
e1ef7cc2 | 910 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
911 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
912 | GEN6_RENDER_L3_PARITY_ERROR)); | |
913 | else | |
914 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
f637fde4 DV |
915 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
916 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
917 | POSTING_READ(GTIMR); | |
0f46832f | 918 | } |
7338aefa | 919 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
920 | |
921 | return true; | |
922 | } | |
923 | ||
924 | static void | |
25c06300 | 925 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
926 | { |
927 | struct drm_device *dev = ring->dev; | |
01a03331 | 928 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 929 | unsigned long flags; |
0f46832f | 930 | |
7338aefa | 931 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 932 | if (--ring->irq_refcount == 0) { |
e1ef7cc2 | 933 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
934 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
935 | else | |
936 | I915_WRITE_IMR(ring, ~0); | |
f637fde4 DV |
937 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
938 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
939 | POSTING_READ(GTIMR); | |
1ec14ad3 | 940 | } |
7338aefa | 941 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 942 | |
99ffa162 | 943 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
944 | } |
945 | ||
d1b851fc | 946 | static int |
fb3256da | 947 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 948 | { |
e1f99ce6 | 949 | int ret; |
78501eac | 950 | |
e1f99ce6 CW |
951 | ret = intel_ring_begin(ring, 2); |
952 | if (ret) | |
953 | return ret; | |
954 | ||
78501eac | 955 | intel_ring_emit(ring, |
65f56876 CW |
956 | MI_BATCH_BUFFER_START | |
957 | MI_BATCH_GTT | | |
78501eac | 958 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 959 | intel_ring_emit(ring, offset); |
78501eac CW |
960 | intel_ring_advance(ring); |
961 | ||
d1b851fc ZN |
962 | return 0; |
963 | } | |
964 | ||
8187a2b7 | 965 | static int |
fb3256da | 966 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 967 | u32 offset, u32 len) |
62fdfeaf | 968 | { |
c4e7a414 | 969 | int ret; |
62fdfeaf | 970 | |
fb3256da DV |
971 | ret = intel_ring_begin(ring, 4); |
972 | if (ret) | |
973 | return ret; | |
62fdfeaf | 974 | |
fb3256da DV |
975 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
976 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
977 | intel_ring_emit(ring, offset + len - 8); | |
978 | intel_ring_emit(ring, 0); | |
979 | intel_ring_advance(ring); | |
e1f99ce6 | 980 | |
fb3256da DV |
981 | return 0; |
982 | } | |
983 | ||
984 | static int | |
985 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
986 | u32 offset, u32 len) | |
987 | { | |
988 | int ret; | |
989 | ||
990 | ret = intel_ring_begin(ring, 2); | |
991 | if (ret) | |
992 | return ret; | |
993 | ||
65f56876 | 994 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
fb3256da | 995 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
c4e7a414 | 996 | intel_ring_advance(ring); |
62fdfeaf | 997 | |
62fdfeaf EA |
998 | return 0; |
999 | } | |
1000 | ||
78501eac | 1001 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1002 | { |
05394f39 | 1003 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1004 | |
8187a2b7 ZN |
1005 | obj = ring->status_page.obj; |
1006 | if (obj == NULL) | |
62fdfeaf | 1007 | return; |
62fdfeaf | 1008 | |
05394f39 | 1009 | kunmap(obj->pages[0]); |
62fdfeaf | 1010 | i915_gem_object_unpin(obj); |
05394f39 | 1011 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1012 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1013 | } |
1014 | ||
78501eac | 1015 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1016 | { |
78501eac | 1017 | struct drm_device *dev = ring->dev; |
05394f39 | 1018 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1019 | int ret; |
1020 | ||
62fdfeaf EA |
1021 | obj = i915_gem_alloc_object(dev, 4096); |
1022 | if (obj == NULL) { | |
1023 | DRM_ERROR("Failed to allocate status page\n"); | |
1024 | ret = -ENOMEM; | |
1025 | goto err; | |
1026 | } | |
e4ffd173 CW |
1027 | |
1028 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1029 | |
86a1ee26 | 1030 | ret = i915_gem_object_pin(obj, 4096, true, false); |
62fdfeaf | 1031 | if (ret != 0) { |
62fdfeaf EA |
1032 | goto err_unref; |
1033 | } | |
1034 | ||
05394f39 CW |
1035 | ring->status_page.gfx_addr = obj->gtt_offset; |
1036 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 1037 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1038 | ret = -ENOMEM; |
62fdfeaf EA |
1039 | goto err_unpin; |
1040 | } | |
8187a2b7 ZN |
1041 | ring->status_page.obj = obj; |
1042 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1043 | |
78501eac | 1044 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
1045 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1046 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1047 | |
1048 | return 0; | |
1049 | ||
1050 | err_unpin: | |
1051 | i915_gem_object_unpin(obj); | |
1052 | err_unref: | |
05394f39 | 1053 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1054 | err: |
8187a2b7 | 1055 | return ret; |
62fdfeaf EA |
1056 | } |
1057 | ||
c43b5634 BW |
1058 | static int intel_init_ring_buffer(struct drm_device *dev, |
1059 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1060 | { |
05394f39 | 1061 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1062 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1063 | int ret; |
1064 | ||
8187a2b7 | 1065 | ring->dev = dev; |
23bc5982 CW |
1066 | INIT_LIST_HEAD(&ring->active_list); |
1067 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1068 | ring->size = 32 * PAGE_SIZE; |
0dc79fb2 | 1069 | |
b259f673 | 1070 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1071 | |
8187a2b7 | 1072 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1073 | ret = init_status_page(ring); |
8187a2b7 ZN |
1074 | if (ret) |
1075 | return ret; | |
1076 | } | |
62fdfeaf | 1077 | |
8187a2b7 | 1078 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
1079 | if (obj == NULL) { |
1080 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1081 | ret = -ENOMEM; |
dd785e35 | 1082 | goto err_hws; |
62fdfeaf | 1083 | } |
62fdfeaf | 1084 | |
05394f39 | 1085 | ring->obj = obj; |
8187a2b7 | 1086 | |
86a1ee26 | 1087 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1088 | if (ret) |
1089 | goto err_unref; | |
62fdfeaf | 1090 | |
3eef8918 CW |
1091 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1092 | if (ret) | |
1093 | goto err_unpin; | |
1094 | ||
dd2757f8 DV |
1095 | ring->virtual_start = |
1096 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, | |
1097 | ring->size); | |
4225d0f2 | 1098 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1099 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1100 | ret = -EINVAL; |
dd785e35 | 1101 | goto err_unpin; |
62fdfeaf EA |
1102 | } |
1103 | ||
78501eac | 1104 | ret = ring->init(ring); |
dd785e35 CW |
1105 | if (ret) |
1106 | goto err_unmap; | |
62fdfeaf | 1107 | |
55249baa CW |
1108 | /* Workaround an erratum on the i830 which causes a hang if |
1109 | * the TAIL pointer points to within the last 2 cachelines | |
1110 | * of the buffer. | |
1111 | */ | |
1112 | ring->effective_size = ring->size; | |
27c1cbd0 | 1113 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1114 | ring->effective_size -= 128; |
1115 | ||
c584fe47 | 1116 | return 0; |
dd785e35 CW |
1117 | |
1118 | err_unmap: | |
4225d0f2 | 1119 | iounmap(ring->virtual_start); |
dd785e35 CW |
1120 | err_unpin: |
1121 | i915_gem_object_unpin(obj); | |
1122 | err_unref: | |
05394f39 CW |
1123 | drm_gem_object_unreference(&obj->base); |
1124 | ring->obj = NULL; | |
dd785e35 | 1125 | err_hws: |
78501eac | 1126 | cleanup_status_page(ring); |
8187a2b7 | 1127 | return ret; |
62fdfeaf EA |
1128 | } |
1129 | ||
78501eac | 1130 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1131 | { |
33626e6a CW |
1132 | struct drm_i915_private *dev_priv; |
1133 | int ret; | |
1134 | ||
05394f39 | 1135 | if (ring->obj == NULL) |
62fdfeaf EA |
1136 | return; |
1137 | ||
33626e6a CW |
1138 | /* Disable the ring buffer. The ring must be idle at this point */ |
1139 | dev_priv = ring->dev->dev_private; | |
96f298aa | 1140 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
1141 | if (ret) |
1142 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1143 | ring->name, ret); | |
1144 | ||
33626e6a CW |
1145 | I915_WRITE_CTL(ring, 0); |
1146 | ||
4225d0f2 | 1147 | iounmap(ring->virtual_start); |
62fdfeaf | 1148 | |
05394f39 CW |
1149 | i915_gem_object_unpin(ring->obj); |
1150 | drm_gem_object_unreference(&ring->obj->base); | |
1151 | ring->obj = NULL; | |
78501eac | 1152 | |
8d19215b ZN |
1153 | if (ring->cleanup) |
1154 | ring->cleanup(ring); | |
1155 | ||
78501eac | 1156 | cleanup_status_page(ring); |
62fdfeaf EA |
1157 | } |
1158 | ||
78501eac | 1159 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1160 | { |
4225d0f2 | 1161 | uint32_t __iomem *virt; |
55249baa | 1162 | int rem = ring->size - ring->tail; |
62fdfeaf | 1163 | |
8187a2b7 | 1164 | if (ring->space < rem) { |
78501eac | 1165 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
1166 | if (ret) |
1167 | return ret; | |
1168 | } | |
62fdfeaf | 1169 | |
4225d0f2 DV |
1170 | virt = ring->virtual_start + ring->tail; |
1171 | rem /= 4; | |
1172 | while (rem--) | |
1173 | iowrite32(MI_NOOP, virt++); | |
62fdfeaf | 1174 | |
8187a2b7 | 1175 | ring->tail = 0; |
c7dca47b | 1176 | ring->space = ring_space(ring); |
62fdfeaf EA |
1177 | |
1178 | return 0; | |
1179 | } | |
1180 | ||
a71d8d94 CW |
1181 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1182 | { | |
a71d8d94 CW |
1183 | int ret; |
1184 | ||
199b2bc2 | 1185 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1186 | if (!ret) |
1187 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1188 | |
1189 | return ret; | |
1190 | } | |
1191 | ||
1192 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1193 | { | |
1194 | struct drm_i915_gem_request *request; | |
1195 | u32 seqno = 0; | |
1196 | int ret; | |
1197 | ||
1198 | i915_gem_retire_requests_ring(ring); | |
1199 | ||
1200 | if (ring->last_retired_head != -1) { | |
1201 | ring->head = ring->last_retired_head; | |
1202 | ring->last_retired_head = -1; | |
1203 | ring->space = ring_space(ring); | |
1204 | if (ring->space >= n) | |
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | list_for_each_entry(request, &ring->request_list, list) { | |
1209 | int space; | |
1210 | ||
1211 | if (request->tail == -1) | |
1212 | continue; | |
1213 | ||
1214 | space = request->tail - (ring->tail + 8); | |
1215 | if (space < 0) | |
1216 | space += ring->size; | |
1217 | if (space >= n) { | |
1218 | seqno = request->seqno; | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | /* Consume this request in case we need more space than | |
1223 | * is available and so need to prevent a race between | |
1224 | * updating last_retired_head and direct reads of | |
1225 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1226 | */ | |
1227 | request->tail = -1; | |
1228 | } | |
1229 | ||
1230 | if (seqno == 0) | |
1231 | return -ENOSPC; | |
1232 | ||
1233 | ret = intel_ring_wait_seqno(ring, seqno); | |
1234 | if (ret) | |
1235 | return ret; | |
1236 | ||
1237 | if (WARN_ON(ring->last_retired_head == -1)) | |
1238 | return -ENOSPC; | |
1239 | ||
1240 | ring->head = ring->last_retired_head; | |
1241 | ring->last_retired_head = -1; | |
1242 | ring->space = ring_space(ring); | |
1243 | if (WARN_ON(ring->space < n)) | |
1244 | return -ENOSPC; | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
78501eac | 1249 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1250 | { |
78501eac | 1251 | struct drm_device *dev = ring->dev; |
cae5852d | 1252 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1253 | unsigned long end; |
a71d8d94 | 1254 | int ret; |
c7dca47b | 1255 | |
a71d8d94 CW |
1256 | ret = intel_ring_wait_request(ring, n); |
1257 | if (ret != -ENOSPC) | |
1258 | return ret; | |
1259 | ||
db53a302 | 1260 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1261 | /* With GEM the hangcheck timer should kick us out of the loop, |
1262 | * leaving it early runs the risk of corrupting GEM state (due | |
1263 | * to running on almost untested codepaths). But on resume | |
1264 | * timers don't work yet, so prevent a complete hang in that | |
1265 | * case by choosing an insanely large timeout. */ | |
1266 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1267 | |
8187a2b7 | 1268 | do { |
c7dca47b CW |
1269 | ring->head = I915_READ_HEAD(ring); |
1270 | ring->space = ring_space(ring); | |
62fdfeaf | 1271 | if (ring->space >= n) { |
db53a302 | 1272 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1273 | return 0; |
1274 | } | |
1275 | ||
1276 | if (dev->primary->master) { | |
1277 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1278 | if (master_priv->sarea_priv) | |
1279 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1280 | } | |
d1b851fc | 1281 | |
e60a0b10 | 1282 | msleep(1); |
d6b2c790 DV |
1283 | |
1284 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); | |
1285 | if (ret) | |
1286 | return ret; | |
8187a2b7 | 1287 | } while (!time_after(jiffies, end)); |
db53a302 | 1288 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1289 | return -EBUSY; |
1290 | } | |
62fdfeaf | 1291 | |
e1f99ce6 CW |
1292 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1293 | int num_dwords) | |
8187a2b7 | 1294 | { |
de2b9985 | 1295 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
be26a10b | 1296 | int n = 4*num_dwords; |
e1f99ce6 | 1297 | int ret; |
78501eac | 1298 | |
de2b9985 DV |
1299 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
1300 | if (ret) | |
1301 | return ret; | |
21dd3734 | 1302 | |
55249baa | 1303 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1304 | ret = intel_wrap_ring_buffer(ring); |
1305 | if (unlikely(ret)) | |
1306 | return ret; | |
1307 | } | |
78501eac | 1308 | |
e1f99ce6 CW |
1309 | if (unlikely(ring->space < n)) { |
1310 | ret = intel_wait_ring_buffer(ring, n); | |
1311 | if (unlikely(ret)) | |
1312 | return ret; | |
1313 | } | |
d97ed339 CW |
1314 | |
1315 | ring->space -= n; | |
e1f99ce6 | 1316 | return 0; |
8187a2b7 | 1317 | } |
62fdfeaf | 1318 | |
78501eac | 1319 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1320 | { |
e5eb3d63 DV |
1321 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1322 | ||
d97ed339 | 1323 | ring->tail &= ring->size - 1; |
e5eb3d63 DV |
1324 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
1325 | return; | |
78501eac | 1326 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1327 | } |
62fdfeaf | 1328 | |
881f47b6 | 1329 | |
78501eac | 1330 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1331 | u32 value) |
881f47b6 | 1332 | { |
0206e353 | 1333 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1334 | |
1335 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1336 | |
1337 | /* Disable notification that the ring is IDLE. The GT | |
1338 | * will then assume that it is busy and bring it out of rc6. | |
1339 | */ | |
0206e353 | 1340 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1341 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1342 | ||
1343 | /* Clear the context id. Here be magic! */ | |
1344 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1345 | |
12f55818 | 1346 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1347 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1348 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1349 | 50)) | |
1350 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1351 | |
12f55818 | 1352 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1353 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1354 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1355 | ||
1356 | /* Let the ring send IDLE messages to the GT again, | |
1357 | * and so let it sleep to conserve power when idle. | |
1358 | */ | |
0206e353 | 1359 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1360 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1361 | } |
1362 | ||
b72f3acb | 1363 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1364 | u32 invalidate, u32 flush) |
881f47b6 | 1365 | { |
71a77e07 | 1366 | uint32_t cmd; |
b72f3acb CW |
1367 | int ret; |
1368 | ||
b72f3acb CW |
1369 | ret = intel_ring_begin(ring, 4); |
1370 | if (ret) | |
1371 | return ret; | |
1372 | ||
71a77e07 CW |
1373 | cmd = MI_FLUSH_DW; |
1374 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1375 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1376 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1377 | intel_ring_emit(ring, 0); |
1378 | intel_ring_emit(ring, 0); | |
71a77e07 | 1379 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1380 | intel_ring_advance(ring); |
1381 | return 0; | |
881f47b6 XH |
1382 | } |
1383 | ||
1384 | static int | |
78501eac | 1385 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1386 | u32 offset, u32 len) |
881f47b6 | 1387 | { |
0206e353 | 1388 | int ret; |
ab6f8e32 | 1389 | |
0206e353 AJ |
1390 | ret = intel_ring_begin(ring, 2); |
1391 | if (ret) | |
1392 | return ret; | |
e1f99ce6 | 1393 | |
0206e353 AJ |
1394 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1395 | /* bit0-7 is the length on GEN6+ */ | |
1396 | intel_ring_emit(ring, offset); | |
1397 | intel_ring_advance(ring); | |
ab6f8e32 | 1398 | |
0206e353 | 1399 | return 0; |
881f47b6 XH |
1400 | } |
1401 | ||
549f7365 CW |
1402 | /* Blitter support (SandyBridge+) */ |
1403 | ||
b72f3acb | 1404 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1405 | u32 invalidate, u32 flush) |
8d19215b | 1406 | { |
71a77e07 | 1407 | uint32_t cmd; |
b72f3acb CW |
1408 | int ret; |
1409 | ||
6a233c78 | 1410 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1411 | if (ret) |
1412 | return ret; | |
1413 | ||
71a77e07 CW |
1414 | cmd = MI_FLUSH_DW; |
1415 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1416 | cmd |= MI_INVALIDATE_TLB; | |
1417 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1418 | intel_ring_emit(ring, 0); |
1419 | intel_ring_emit(ring, 0); | |
71a77e07 | 1420 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1421 | intel_ring_advance(ring); |
1422 | return 0; | |
8d19215b ZN |
1423 | } |
1424 | ||
5c1143bb XH |
1425 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1426 | { | |
1427 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1428 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1429 | |
59465b5f DV |
1430 | ring->name = "render ring"; |
1431 | ring->id = RCS; | |
1432 | ring->mmio_base = RENDER_RING_BASE; | |
1433 | ||
1ec14ad3 CW |
1434 | if (INTEL_INFO(dev)->gen >= 6) { |
1435 | ring->add_request = gen6_add_request; | |
4772eaeb | 1436 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa CW |
1437 | if (INTEL_INFO(dev)->gen == 6) |
1438 | ring->flush = gen6_render_ring_flush__wa; | |
25c06300 BW |
1439 | ring->irq_get = gen6_ring_get_irq; |
1440 | ring->irq_put = gen6_ring_put_irq; | |
6a848ccb | 1441 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
4cd53c0c | 1442 | ring->get_seqno = gen6_ring_get_seqno; |
686cb5f9 | 1443 | ring->sync_to = gen6_ring_sync; |
59465b5f DV |
1444 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
1445 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; | |
1446 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; | |
1447 | ring->signal_mbox[0] = GEN6_VRSYNC; | |
1448 | ring->signal_mbox[1] = GEN6_BRSYNC; | |
c6df541c CW |
1449 | } else if (IS_GEN5(dev)) { |
1450 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1451 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1452 | ring->get_seqno = pc_render_get_seqno; |
e48d8634 DV |
1453 | ring->irq_get = gen5_ring_get_irq; |
1454 | ring->irq_put = gen5_ring_put_irq; | |
e3670319 | 1455 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
59465b5f | 1456 | } else { |
8620a3a9 | 1457 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1458 | if (INTEL_INFO(dev)->gen < 4) |
1459 | ring->flush = gen2_render_ring_flush; | |
1460 | else | |
1461 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1462 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1463 | if (IS_GEN2(dev)) { |
1464 | ring->irq_get = i8xx_ring_get_irq; | |
1465 | ring->irq_put = i8xx_ring_put_irq; | |
1466 | } else { | |
1467 | ring->irq_get = i9xx_ring_get_irq; | |
1468 | ring->irq_put = i9xx_ring_put_irq; | |
1469 | } | |
e3670319 | 1470 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1471 | } |
59465b5f | 1472 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1473 | if (INTEL_INFO(dev)->gen >= 6) |
1474 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1475 | else if (INTEL_INFO(dev)->gen >= 4) | |
1476 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1477 | else if (IS_I830(dev) || IS_845G(dev)) | |
1478 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1479 | else | |
1480 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1481 | ring->init = init_render_ring; |
1482 | ring->cleanup = render_ring_cleanup; | |
1483 | ||
5c1143bb XH |
1484 | |
1485 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1486 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1487 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1488 | } |
1489 | ||
1ec14ad3 | 1490 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1491 | } |
1492 | ||
e8616b6c CW |
1493 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1494 | { | |
1495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1496 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1497 | ||
59465b5f DV |
1498 | ring->name = "render ring"; |
1499 | ring->id = RCS; | |
1500 | ring->mmio_base = RENDER_RING_BASE; | |
1501 | ||
e8616b6c | 1502 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1503 | /* non-kms not supported on gen6+ */ |
1504 | return -ENODEV; | |
e8616b6c | 1505 | } |
28f0cbf7 DV |
1506 | |
1507 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1508 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1509 | * the special gen5 functions. */ | |
1510 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1511 | if (INTEL_INFO(dev)->gen < 4) |
1512 | ring->flush = gen2_render_ring_flush; | |
1513 | else | |
1514 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1515 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1516 | if (IS_GEN2(dev)) { |
1517 | ring->irq_get = i8xx_ring_get_irq; | |
1518 | ring->irq_put = i8xx_ring_put_irq; | |
1519 | } else { | |
1520 | ring->irq_get = i9xx_ring_get_irq; | |
1521 | ring->irq_put = i9xx_ring_put_irq; | |
1522 | } | |
28f0cbf7 | 1523 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1524 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1525 | if (INTEL_INFO(dev)->gen >= 4) |
1526 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1527 | else if (IS_I830(dev) || IS_845G(dev)) | |
1528 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1529 | else | |
1530 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1531 | ring->init = init_render_ring; |
1532 | ring->cleanup = render_ring_cleanup; | |
e8616b6c | 1533 | |
f3234706 KP |
1534 | if (!I915_NEED_GFX_HWS(dev)) |
1535 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1536 | ||
e8616b6c CW |
1537 | ring->dev = dev; |
1538 | INIT_LIST_HEAD(&ring->active_list); | |
1539 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1540 | |
1541 | ring->size = size; | |
1542 | ring->effective_size = ring->size; | |
1543 | if (IS_I830(ring->dev)) | |
1544 | ring->effective_size -= 128; | |
1545 | ||
4225d0f2 DV |
1546 | ring->virtual_start = ioremap_wc(start, size); |
1547 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1548 | DRM_ERROR("can not ioremap virtual address for" |
1549 | " ring buffer\n"); | |
1550 | return -ENOMEM; | |
1551 | } | |
1552 | ||
e8616b6c CW |
1553 | return 0; |
1554 | } | |
1555 | ||
5c1143bb XH |
1556 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1557 | { | |
1558 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1559 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1560 | |
58fa3835 DV |
1561 | ring->name = "bsd ring"; |
1562 | ring->id = VCS; | |
1563 | ||
0fd2c201 | 1564 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1565 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1566 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1567 | /* gen6 bsd needs a special wa for tail updates */ |
1568 | if (IS_GEN6(dev)) | |
1569 | ring->write_tail = gen6_bsd_ring_write_tail; | |
58fa3835 DV |
1570 | ring->flush = gen6_ring_flush; |
1571 | ring->add_request = gen6_add_request; | |
1572 | ring->get_seqno = gen6_ring_get_seqno; | |
1573 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; | |
1574 | ring->irq_get = gen6_ring_get_irq; | |
1575 | ring->irq_put = gen6_ring_put_irq; | |
1576 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1577 | ring->sync_to = gen6_ring_sync; |
58fa3835 DV |
1578 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
1579 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; | |
1580 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; | |
1581 | ring->signal_mbox[0] = GEN6_RVSYNC; | |
1582 | ring->signal_mbox[1] = GEN6_BVSYNC; | |
1583 | } else { | |
1584 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1585 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1586 | ring->add_request = i9xx_add_request; |
58fa3835 | 1587 | ring->get_seqno = ring_get_seqno; |
e48d8634 | 1588 | if (IS_GEN5(dev)) { |
e3670319 | 1589 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
e48d8634 DV |
1590 | ring->irq_get = gen5_ring_get_irq; |
1591 | ring->irq_put = gen5_ring_put_irq; | |
1592 | } else { | |
e3670319 | 1593 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1594 | ring->irq_get = i9xx_ring_get_irq; |
1595 | ring->irq_put = i9xx_ring_put_irq; | |
1596 | } | |
fb3256da | 1597 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1598 | } |
1599 | ring->init = init_ring_common; | |
1600 | ||
5c1143bb | 1601 | |
1ec14ad3 | 1602 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1603 | } |
549f7365 CW |
1604 | |
1605 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1606 | { | |
1607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1608 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1609 | |
3535d9dd DV |
1610 | ring->name = "blitter ring"; |
1611 | ring->id = BCS; | |
1612 | ||
1613 | ring->mmio_base = BLT_RING_BASE; | |
1614 | ring->write_tail = ring_write_tail; | |
1615 | ring->flush = blt_ring_flush; | |
1616 | ring->add_request = gen6_add_request; | |
1617 | ring->get_seqno = gen6_ring_get_seqno; | |
1618 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; | |
1619 | ring->irq_get = gen6_ring_get_irq; | |
1620 | ring->irq_put = gen6_ring_put_irq; | |
1621 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1622 | ring->sync_to = gen6_ring_sync; |
3535d9dd DV |
1623 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
1624 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; | |
1625 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; | |
1626 | ring->signal_mbox[0] = GEN6_RBSYNC; | |
1627 | ring->signal_mbox[1] = GEN6_VBSYNC; | |
1628 | ring->init = init_ring_common; | |
549f7365 | 1629 | |
1ec14ad3 | 1630 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1631 | } |
a7b9761d CW |
1632 | |
1633 | int | |
1634 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
1635 | { | |
1636 | int ret; | |
1637 | ||
1638 | if (!ring->gpu_caches_dirty) | |
1639 | return 0; | |
1640 | ||
1641 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1642 | if (ret) | |
1643 | return ret; | |
1644 | ||
1645 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1646 | ||
1647 | ring->gpu_caches_dirty = false; | |
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | int | |
1652 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
1653 | { | |
1654 | uint32_t flush_domains; | |
1655 | int ret; | |
1656 | ||
1657 | flush_domains = 0; | |
1658 | if (ring->gpu_caches_dirty) | |
1659 | flush_domains = I915_GEM_GPU_DOMAINS; | |
1660 | ||
1661 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1662 | if (ret) | |
1663 | return ret; | |
1664 | ||
1665 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1666 | ||
1667 | ring->gpu_caches_dirty = false; | |
1668 | return 0; | |
1669 | } |