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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
33 | |
34 | #include "i915_drv.h" | |
35 | #include "i915_gem_render_state.h" | |
eb8d0f5a | 36 | #include "i915_reset.h" |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
7d3c425f | 39 | #include "intel_workarounds.h" |
62fdfeaf | 40 | |
a0442461 CW |
41 | /* Rough estimate of the typical request size, performing a flush, |
42 | * set-context and then emitting the batch. | |
43 | */ | |
44 | #define LEGACY_REQUEST_SIZE 200 | |
45 | ||
95aebcb2 | 46 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 47 | { |
95aebcb2 CW |
48 | unsigned int space; |
49 | ||
50 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
51 | ||
52 | ring->space = space; | |
53 | return space; | |
ebd0fd4b DG |
54 | } |
55 | ||
b72f3acb | 56 | static int |
e61e0f51 | 57 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 58 | { |
a889580c | 59 | unsigned int num_store_dw; |
73dec95e | 60 | u32 cmd, *cs; |
46f0f8d1 CW |
61 | |
62 | cmd = MI_FLUSH; | |
a889580c | 63 | num_store_dw = 0; |
7c9cf4e3 | 64 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 | 65 | cmd |= MI_READ_FLUSH; |
a889580c CW |
66 | if (mode & EMIT_FLUSH) |
67 | num_store_dw = 4; | |
46f0f8d1 | 68 | |
a889580c | 69 | cs = intel_ring_begin(rq, 2 + 3 * num_store_dw); |
73dec95e TU |
70 | if (IS_ERR(cs)) |
71 | return PTR_ERR(cs); | |
46f0f8d1 | 72 | |
73dec95e | 73 | *cs++ = cmd; |
a889580c CW |
74 | while (num_store_dw--) { |
75 | *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL; | |
76 | *cs++ = i915_scratch_offset(rq->i915); | |
77 | *cs++ = 0; | |
78 | } | |
79 | *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
80 | ||
e61e0f51 | 81 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
82 | |
83 | return 0; | |
84 | } | |
85 | ||
86 | static int | |
e61e0f51 | 87 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 88 | { |
73dec95e | 89 | u32 cmd, *cs; |
55f99bf2 | 90 | int i; |
6f392d54 | 91 | |
36d527de CW |
92 | /* |
93 | * read/write caches: | |
94 | * | |
95 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
96 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
97 | * also flushed at 2d versus 3d pipeline switches. | |
98 | * | |
99 | * read-only caches: | |
100 | * | |
101 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
102 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
103 | * | |
104 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
105 | * | |
106 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
107 | * invalidated when MI_EXE_FLUSH is set. | |
108 | * | |
109 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
110 | * invalidated with every MI_FLUSH. | |
111 | * | |
112 | * TLBs: | |
113 | * | |
114 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
115 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
116 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
117 | * are flushed at any MI_FLUSH. | |
118 | */ | |
119 | ||
b5321f30 | 120 | cmd = MI_FLUSH; |
7c9cf4e3 | 121 | if (mode & EMIT_INVALIDATE) { |
36d527de | 122 | cmd |= MI_EXE_FLUSH; |
cf819eff | 123 | if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5)) |
b5321f30 CW |
124 | cmd |= MI_INVALIDATE_ISP; |
125 | } | |
70eac33e | 126 | |
55f99bf2 CW |
127 | i = 2; |
128 | if (mode & EMIT_INVALIDATE) | |
129 | i += 20; | |
130 | ||
131 | cs = intel_ring_begin(rq, i); | |
73dec95e TU |
132 | if (IS_ERR(cs)) |
133 | return PTR_ERR(cs); | |
b72f3acb | 134 | |
73dec95e | 135 | *cs++ = cmd; |
55f99bf2 CW |
136 | |
137 | /* | |
138 | * A random delay to let the CS invalidate take effect? Without this | |
139 | * delay, the GPU relocation path fails as the CS does not see | |
140 | * the updated contents. Just as important, if we apply the flushes | |
141 | * to the EMIT_FLUSH branch (i.e. immediately after the relocation | |
142 | * write and before the invalidate on the next batch), the relocations | |
143 | * still fail. This implies that is a delay following invalidation | |
144 | * that is required to reset the caches as opposed to a delay to | |
145 | * ensure the memory is written. | |
146 | */ | |
147 | if (mode & EMIT_INVALIDATE) { | |
148 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 149 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
150 | *cs++ = 0; |
151 | *cs++ = 0; | |
152 | ||
153 | for (i = 0; i < 12; i++) | |
154 | *cs++ = MI_FLUSH; | |
155 | ||
156 | *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; | |
51797499 | 157 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; |
55f99bf2 CW |
158 | *cs++ = 0; |
159 | *cs++ = 0; | |
160 | } | |
161 | ||
162 | *cs++ = cmd; | |
163 | ||
e61e0f51 | 164 | intel_ring_advance(rq, cs); |
b72f3acb CW |
165 | |
166 | return 0; | |
8187a2b7 ZN |
167 | } |
168 | ||
179f4025 | 169 | /* |
8d315287 JB |
170 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
171 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
172 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
173 | * | |
174 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
175 | * produced by non-pipelined state commands), software needs to first | |
176 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
177 | * 0. | |
178 | * | |
179 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
180 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
181 | * | |
182 | * And the workaround for these two requires this workaround first: | |
183 | * | |
184 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
185 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
186 | * flushes. | |
187 | * | |
188 | * And this last workaround is tricky because of the requirements on | |
189 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
190 | * volume 2 part 1: | |
191 | * | |
192 | * "1 of the following must also be set: | |
193 | * - Render Target Cache Flush Enable ([12] of DW1) | |
194 | * - Depth Cache Flush Enable ([0] of DW1) | |
195 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
196 | * - Depth Stall ([13] of DW1) | |
197 | * - Post-Sync Operation ([13] of DW1) | |
198 | * - Notify Enable ([8] of DW1)" | |
199 | * | |
200 | * The cache flushes require the workaround flush that triggered this | |
201 | * one, so we can't use it. Depth stall would trigger the same. | |
202 | * Post-sync nonzero is what triggered this second workaround, so we | |
203 | * can't use that one either. Notify enable is IRQs, which aren't | |
204 | * really our business. That leaves only stall at scoreboard. | |
205 | */ | |
206 | static int | |
caa5915b | 207 | gen6_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 208 | { |
51797499 | 209 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e TU |
210 | u32 *cs; |
211 | ||
e61e0f51 | 212 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
213 | if (IS_ERR(cs)) |
214 | return PTR_ERR(cs); | |
215 | ||
216 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
217 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
218 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
219 | *cs++ = 0; /* low dword */ | |
220 | *cs++ = 0; /* high dword */ | |
221 | *cs++ = MI_NOOP; | |
e61e0f51 | 222 | intel_ring_advance(rq, cs); |
73dec95e | 223 | |
e61e0f51 | 224 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
225 | if (IS_ERR(cs)) |
226 | return PTR_ERR(cs); | |
227 | ||
228 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
229 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
230 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
231 | *cs++ = 0; | |
232 | *cs++ = 0; | |
233 | *cs++ = MI_NOOP; | |
e61e0f51 | 234 | intel_ring_advance(rq, cs); |
8d315287 JB |
235 | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static int | |
e61e0f51 | 240 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 241 | { |
51797499 | 242 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 243 | u32 *cs, flags = 0; |
8d315287 JB |
244 | int ret; |
245 | ||
b3111509 | 246 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
caa5915b | 247 | ret = gen6_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
248 | if (ret) |
249 | return ret; | |
250 | ||
8d315287 JB |
251 | /* Just flush everything. Experiments have shown that reducing the |
252 | * number of bits based on the write domains has little performance | |
253 | * impact. | |
254 | */ | |
7c9cf4e3 | 255 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
256 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
257 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
258 | /* | |
259 | * Ensure that any following seqno writes only happen | |
260 | * when the render cache is indeed flushed. | |
261 | */ | |
97f209bc | 262 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 263 | } |
7c9cf4e3 | 264 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
265 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
266 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
267 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
268 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
269 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
270 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
271 | /* | |
272 | * TLB invalidate requires a post-sync write. | |
273 | */ | |
3ac78313 | 274 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 275 | } |
8d315287 | 276 | |
e61e0f51 | 277 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
278 | if (IS_ERR(cs)) |
279 | return PTR_ERR(cs); | |
8d315287 | 280 | |
73dec95e TU |
281 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
282 | *cs++ = flags; | |
283 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
284 | *cs++ = 0; | |
e61e0f51 | 285 | intel_ring_advance(rq, cs); |
8d315287 JB |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
e1a73a54 | 290 | static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
291 | { |
292 | /* First we do the gen6_emit_post_sync_nonzero_flush w/a */ | |
293 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
294 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
295 | *cs++ = 0; | |
296 | *cs++ = 0; | |
297 | ||
298 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
299 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
300 | *cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT; | |
301 | *cs++ = 0; | |
302 | ||
303 | /* Finally we can flush and with it emit the breadcrumb */ | |
304 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
305 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
306 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
307 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
308 | PIPE_CONTROL_QW_WRITE | | |
309 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
310 | *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; |
311 | *cs++ = rq->fence.seqno; | |
312 | ||
89531e7d | 313 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
54939ea0 CW |
314 | *cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_STORE_DATA_INDEX; |
315 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | PIPE_CONTROL_GLOBAL_GTT; | |
89531e7d CW |
316 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); |
317 | ||
caa5915b CW |
318 | *cs++ = MI_USER_INTERRUPT; |
319 | *cs++ = MI_NOOP; | |
320 | ||
321 | rq->tail = intel_ring_offset(rq, cs); | |
322 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
323 | |
324 | return cs; | |
caa5915b | 325 | } |
caa5915b | 326 | |
f3987631 | 327 | static int |
e61e0f51 | 328 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 329 | { |
73dec95e | 330 | u32 *cs; |
f3987631 | 331 | |
e61e0f51 | 332 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
333 | if (IS_ERR(cs)) |
334 | return PTR_ERR(cs); | |
f3987631 | 335 | |
73dec95e TU |
336 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
337 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
338 | *cs++ = 0; | |
339 | *cs++ = 0; | |
e61e0f51 | 340 | intel_ring_advance(rq, cs); |
f3987631 PZ |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
4772eaeb | 345 | static int |
e61e0f51 | 346 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 347 | { |
51797499 | 348 | u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES; |
73dec95e | 349 | u32 *cs, flags = 0; |
4772eaeb | 350 | |
f3987631 PZ |
351 | /* |
352 | * Ensure that any following seqno writes only happen when the render | |
353 | * cache is indeed flushed. | |
354 | * | |
355 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
356 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
357 | * don't try to be clever and just set it unconditionally. | |
358 | */ | |
359 | flags |= PIPE_CONTROL_CS_STALL; | |
360 | ||
4772eaeb PZ |
361 | /* Just flush everything. Experiments have shown that reducing the |
362 | * number of bits based on the write domains has little performance | |
363 | * impact. | |
364 | */ | |
7c9cf4e3 | 365 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
366 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
367 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 368 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 369 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 370 | } |
7c9cf4e3 | 371 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
372 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
373 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
375 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
376 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
377 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 378 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
379 | /* |
380 | * TLB invalidate requires a post-sync write. | |
381 | */ | |
382 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 383 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 384 | |
add284a3 CW |
385 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
386 | ||
f3987631 PZ |
387 | /* Workaround: we must issue a pipe_control with CS-stall bit |
388 | * set before a pipe_control command that has the state cache | |
389 | * invalidate bit set. */ | |
e61e0f51 | 390 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
391 | } |
392 | ||
e61e0f51 | 393 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
394 | if (IS_ERR(cs)) |
395 | return PTR_ERR(cs); | |
4772eaeb | 396 | |
73dec95e TU |
397 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
398 | *cs++ = flags; | |
399 | *cs++ = scratch_addr; | |
400 | *cs++ = 0; | |
e61e0f51 | 401 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
e1a73a54 | 406 | static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b CW |
407 | { |
408 | *cs++ = GFX_OP_PIPE_CONTROL(4); | |
409 | *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | | |
410 | PIPE_CONTROL_DEPTH_CACHE_FLUSH | | |
411 | PIPE_CONTROL_DC_FLUSH_ENABLE | | |
412 | PIPE_CONTROL_FLUSH_ENABLE | | |
413 | PIPE_CONTROL_QW_WRITE | | |
414 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
415 | PIPE_CONTROL_CS_STALL); | |
5013eb8c CW |
416 | *cs++ = rq->timeline->hwsp_offset; |
417 | *cs++ = rq->fence.seqno; | |
418 | ||
89531e7d | 419 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
54939ea0 CW |
420 | *cs++ = (PIPE_CONTROL_QW_WRITE | |
421 | PIPE_CONTROL_STORE_DATA_INDEX | | |
422 | PIPE_CONTROL_GLOBAL_GTT_IVB); | |
423 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR; | |
89531e7d CW |
424 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); |
425 | ||
caa5915b CW |
426 | *cs++ = MI_USER_INTERRUPT; |
427 | *cs++ = MI_NOOP; | |
428 | ||
429 | rq->tail = intel_ring_offset(rq, cs); | |
430 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
431 | |
432 | return cs; | |
caa5915b | 433 | } |
caa5915b | 434 | |
e1a73a54 | 435 | static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
caa5915b | 436 | { |
5013eb8c CW |
437 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
438 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
439 | ||
440 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
441 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
442 | *cs++ = rq->fence.seqno; | |
443 | ||
89531e7d CW |
444 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; |
445 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT; | |
446 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
447 | ||
caa5915b | 448 | *cs++ = MI_USER_INTERRUPT; |
b300fde8 | 449 | *cs++ = MI_NOOP; |
caa5915b CW |
450 | |
451 | rq->tail = intel_ring_offset(rq, cs); | |
452 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
453 | |
454 | return cs; | |
caa5915b | 455 | } |
caa5915b | 456 | |
1212bd82 | 457 | #define GEN7_XCS_WA 32 |
e1a73a54 | 458 | static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1212bd82 CW |
459 | { |
460 | int i; | |
461 | ||
5013eb8c CW |
462 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
463 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
464 | ||
465 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; | |
466 | *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; | |
467 | *cs++ = rq->fence.seqno; | |
468 | ||
89531e7d CW |
469 | *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX; |
470 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR | MI_FLUSH_DW_USE_GTT; | |
471 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
472 | ||
1212bd82 CW |
473 | for (i = 0; i < GEN7_XCS_WA; i++) { |
474 | *cs++ = MI_STORE_DWORD_INDEX; | |
5013eb8c CW |
475 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
476 | *cs++ = rq->fence.seqno; | |
1212bd82 CW |
477 | } |
478 | ||
479 | *cs++ = MI_FLUSH_DW; | |
480 | *cs++ = 0; | |
481 | *cs++ = 0; | |
482 | ||
483 | *cs++ = MI_USER_INTERRUPT; | |
1212bd82 CW |
484 | |
485 | rq->tail = intel_ring_offset(rq, cs); | |
486 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
487 | |
488 | return cs; | |
1212bd82 | 489 | } |
1212bd82 CW |
490 | #undef GEN7_XCS_WA |
491 | ||
060f2322 CW |
492 | static void set_hwstam(struct intel_engine_cs *engine, u32 mask) |
493 | { | |
494 | /* | |
495 | * Keep the render interrupt unmasked as this papers over | |
496 | * lost interrupts following a reset. | |
497 | */ | |
498 | if (engine->class == RENDER_CLASS) { | |
499 | if (INTEL_GEN(engine->i915) >= 6) | |
500 | mask &= ~BIT(0); | |
501 | else | |
502 | mask &= ~I915_USER_INTERRUPT; | |
503 | } | |
504 | ||
505 | intel_engine_set_hwsp_writemask(engine, mask); | |
506 | } | |
507 | ||
508 | static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) | |
035dc1e0 | 509 | { |
c033666a | 510 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
511 | u32 addr; |
512 | ||
d6acae36 | 513 | addr = lower_32_bits(phys); |
c033666a | 514 | if (INTEL_GEN(dev_priv) >= 4) |
d6acae36 CW |
515 | addr |= (phys >> 28) & 0xf0; |
516 | ||
035dc1e0 DV |
517 | I915_WRITE(HWS_PGA, addr); |
518 | } | |
519 | ||
0ca88ba0 | 520 | static struct page *status_page(struct intel_engine_cs *engine) |
060f2322 | 521 | { |
0ca88ba0 | 522 | struct drm_i915_gem_object *obj = engine->status_page.vma->obj; |
060f2322 | 523 | |
0ca88ba0 CW |
524 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
525 | return sg_page(obj->mm.pages->sgl); | |
526 | } | |
527 | ||
528 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) | |
529 | { | |
530 | set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); | |
060f2322 CW |
531 | set_hwstam(engine, ~0u); |
532 | } | |
533 | ||
534 | static void set_hwsp(struct intel_engine_cs *engine, u32 offset) | |
af75f269 | 535 | { |
c033666a | 536 | struct drm_i915_private *dev_priv = engine->i915; |
060f2322 | 537 | i915_reg_t hwsp; |
af75f269 | 538 | |
060f2322 CW |
539 | /* |
540 | * The ring status page addresses are no longer next to the rest of | |
af75f269 DL |
541 | * the ring registers as of gen7. |
542 | */ | |
cf819eff | 543 | if (IS_GEN(dev_priv, 7)) { |
0bc40be8 | 544 | switch (engine->id) { |
a2d3d265 MT |
545 | /* |
546 | * No more rings exist on Gen7. Default case is only to shut up | |
547 | * gcc switch check warning. | |
548 | */ | |
549 | default: | |
550 | GEM_BUG_ON(engine->id); | |
8a68d464 CW |
551 | /* fallthrough */ |
552 | case RCS0: | |
060f2322 | 553 | hwsp = RENDER_HWS_PGA_GEN7; |
af75f269 | 554 | break; |
8a68d464 | 555 | case BCS0: |
060f2322 | 556 | hwsp = BLT_HWS_PGA_GEN7; |
af75f269 | 557 | break; |
8a68d464 | 558 | case VCS0: |
060f2322 | 559 | hwsp = BSD_HWS_PGA_GEN7; |
af75f269 | 560 | break; |
8a68d464 | 561 | case VECS0: |
060f2322 | 562 | hwsp = VEBOX_HWS_PGA_GEN7; |
af75f269 DL |
563 | break; |
564 | } | |
cf819eff | 565 | } else if (IS_GEN(dev_priv, 6)) { |
060f2322 | 566 | hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 567 | } else { |
060f2322 | 568 | hwsp = RING_HWS_PGA(engine->mmio_base); |
a4a71701 | 569 | } |
c5498089 | 570 | |
060f2322 CW |
571 | I915_WRITE(hwsp, offset); |
572 | POSTING_READ(hwsp); | |
573 | } | |
af75f269 | 574 | |
060f2322 CW |
575 | static void flush_cs_tlb(struct intel_engine_cs *engine) |
576 | { | |
577 | struct drm_i915_private *dev_priv = engine->i915; | |
578 | i915_reg_t instpm = RING_INSTPM(engine->mmio_base); | |
579 | ||
580 | if (!IS_GEN_RANGE(dev_priv, 6, 7)) | |
581 | return; | |
582 | ||
583 | /* ring should be idle before issuing a sync flush*/ | |
584 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
585 | ||
586 | I915_WRITE(instpm, | |
587 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
588 | INSTPM_SYNC_FLUSH)); | |
589 | if (intel_wait_for_register(dev_priv, | |
590 | instpm, INSTPM_SYNC_FLUSH, 0, | |
591 | 1000)) | |
592 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
593 | engine->name); | |
594 | } | |
af75f269 | 595 | |
060f2322 CW |
596 | static void ring_setup_status_page(struct intel_engine_cs *engine) |
597 | { | |
0ca88ba0 | 598 | set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); |
060f2322 | 599 | set_hwstam(engine, ~0u); |
af75f269 | 600 | |
060f2322 | 601 | flush_cs_tlb(engine); |
af75f269 DL |
602 | } |
603 | ||
0bc40be8 | 604 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 605 | { |
c033666a | 606 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 607 | |
21a2c58a | 608 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 609 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
610 | if (intel_wait_for_register(dev_priv, |
611 | RING_MI_MODE(engine->mmio_base), | |
612 | MODE_IDLE, | |
613 | MODE_IDLE, | |
614 | 1000)) { | |
0bc40be8 TU |
615 | DRM_ERROR("%s : timed out trying to stop ring\n", |
616 | engine->name); | |
9bec9b13 CW |
617 | /* Sometimes we observe that the idle flag is not |
618 | * set even though the ring is empty. So double | |
619 | * check before giving up. | |
620 | */ | |
0bc40be8 | 621 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 622 | return false; |
9991ae78 CW |
623 | } |
624 | } | |
b7884eb4 | 625 | |
11caf551 CW |
626 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
627 | ||
0bc40be8 | 628 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 629 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 630 | |
11caf551 CW |
631 | /* The ring must be empty before it is disabled */ |
632 | I915_WRITE_CTL(engine, 0); | |
633 | ||
0bc40be8 | 634 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 635 | } |
8187a2b7 | 636 | |
0bc40be8 | 637 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 638 | { |
c033666a | 639 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 640 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
641 | int ret = 0; |
642 | ||
3ceea6a1 | 643 | intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); |
9991ae78 | 644 | |
0bc40be8 | 645 | if (!stop_ring(engine)) { |
9991ae78 | 646 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
647 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
648 | "ctl %08x head %08x tail %08x start %08x\n", | |
649 | engine->name, | |
650 | I915_READ_CTL(engine), | |
651 | I915_READ_HEAD(engine), | |
652 | I915_READ_TAIL(engine), | |
653 | I915_READ_START(engine)); | |
8187a2b7 | 654 | |
0bc40be8 | 655 | if (!stop_ring(engine)) { |
6fd0d56e CW |
656 | DRM_ERROR("failed to set %s head to zero " |
657 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
658 | engine->name, |
659 | I915_READ_CTL(engine), | |
660 | I915_READ_HEAD(engine), | |
661 | I915_READ_TAIL(engine), | |
662 | I915_READ_START(engine)); | |
9991ae78 CW |
663 | ret = -EIO; |
664 | goto out; | |
6fd0d56e | 665 | } |
8187a2b7 ZN |
666 | } |
667 | ||
3177659a | 668 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 669 | ring_setup_phys_status_page(engine); |
3177659a | 670 | else |
060f2322 | 671 | ring_setup_status_page(engine); |
9991ae78 | 672 | |
ad07dfcd | 673 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 674 | |
ece4a17d | 675 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 676 | I915_READ_HEAD(engine); |
ece4a17d | 677 | |
0d8957c8 DV |
678 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
679 | * registers with the above sequence (the readback of the HEAD registers | |
680 | * also enforces ordering), otherwise the hw might lose the new ring | |
681 | * register values. */ | |
bde13ebd | 682 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
683 | |
684 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 685 | if (I915_READ_HEAD(engine)) |
8177e112 CW |
686 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
687 | engine->name, I915_READ_HEAD(engine)); | |
821ed7df | 688 | |
41d37680 CW |
689 | /* Check that the ring offsets point within the ring! */ |
690 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
691 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
821ed7df | 692 | intel_ring_update_space(ring); |
b7f21899 CW |
693 | |
694 | /* First wake the ring up to an empty/idle ring */ | |
821ed7df | 695 | I915_WRITE_HEAD(engine, ring->head); |
b7f21899 | 696 | I915_WRITE_TAIL(engine, ring->head); |
821ed7df | 697 | (void)I915_READ_TAIL(engine); |
95468892 | 698 | |
62ae14b1 | 699 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 700 | |
8187a2b7 | 701 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
702 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
703 | RING_VALID, RING_VALID, | |
704 | 50)) { | |
e74cfed5 | 705 | DRM_ERROR("%s initialization failed " |
821ed7df | 706 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
707 | engine->name, |
708 | I915_READ_CTL(engine), | |
709 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
710 | I915_READ_HEAD(engine), ring->head, |
711 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 712 | I915_READ_START(engine), |
bde13ebd | 713 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
714 | ret = -EIO; |
715 | goto out; | |
8187a2b7 ZN |
716 | } |
717 | ||
7836cd02 CW |
718 | if (INTEL_GEN(dev_priv) > 2) |
719 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
720 | ||
b7f21899 CW |
721 | /* Now awake, let it get started */ |
722 | if (ring->tail != ring->head) { | |
723 | I915_WRITE_TAIL(engine, ring->tail); | |
724 | (void)I915_READ_TAIL(engine); | |
725 | } | |
726 | ||
d6fee0de | 727 | /* Papering over lost _interrupts_ immediately following the restart */ |
52c0fdb2 | 728 | intel_engine_queue_breadcrumbs(engine); |
b7884eb4 | 729 | out: |
3ceea6a1 | 730 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
b7884eb4 DV |
731 | |
732 | return ret; | |
8187a2b7 ZN |
733 | } |
734 | ||
eb8d0f5a | 735 | static void reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 736 | { |
3f6e9822 | 737 | intel_engine_stop_cs(engine); |
5adfb772 CW |
738 | } |
739 | ||
eb8d0f5a | 740 | static void reset_ring(struct intel_engine_cs *engine, bool stalled) |
5adfb772 | 741 | { |
eb8d0f5a CW |
742 | struct i915_timeline *tl = &engine->timeline; |
743 | struct i915_request *pos, *rq; | |
744 | unsigned long flags; | |
b3ee09a4 | 745 | u32 head; |
5adfb772 | 746 | |
eb8d0f5a CW |
747 | rq = NULL; |
748 | spin_lock_irqsave(&tl->lock, flags); | |
749 | list_for_each_entry(pos, &tl->requests, link) { | |
5013eb8c | 750 | if (!i915_request_completed(pos)) { |
eb8d0f5a CW |
751 | rq = pos; |
752 | break; | |
753 | } | |
b3ee09a4 | 754 | } |
67e64564 CW |
755 | |
756 | /* | |
eb8d0f5a | 757 | * The guilty request will get skipped on a hung engine. |
c0dcb203 | 758 | * |
eb8d0f5a CW |
759 | * Users of client default contexts do not rely on logical |
760 | * state preserved between batches so it is safe to execute | |
761 | * queued requests following the hang. Non default contexts | |
762 | * rely on preserved state, so skipping a batch loses the | |
763 | * evolution of the state and it needs to be considered corrupted. | |
764 | * Executing more queued batches on top of corrupted state is | |
765 | * risky. But we take the risk by trying to advance through | |
766 | * the queued requests in order to make the client behaviour | |
767 | * more predictable around resets, by not throwing away random | |
768 | * amount of batches it has prepared for execution. Sophisticated | |
769 | * clients can use gem_reset_stats_ioctl and dma fence status | |
770 | * (exported via sync_file info ioctl on explicit fences) to observe | |
771 | * when it loses the context state and should rebuild accordingly. | |
c0dcb203 | 772 | * |
eb8d0f5a CW |
773 | * The context ban, and ultimately the client ban, mechanism are safety |
774 | * valves if client submission ends up resulting in nothing more than | |
775 | * subsequent hangs. | |
c0dcb203 | 776 | */ |
eb8d0f5a | 777 | |
b3ee09a4 | 778 | if (rq) { |
eb8d0f5a CW |
779 | /* |
780 | * Try to restore the logical GPU state to match the | |
781 | * continuation of the request queue. If we skip the | |
782 | * context/PD restore, then the next request may try to execute | |
783 | * assuming that its context is valid and loaded on the GPU and | |
784 | * so may try to access invalid memory, prompting repeated GPU | |
785 | * hangs. | |
786 | * | |
787 | * If the request was guilty, we still restore the logical | |
788 | * state in case the next request requires it (e.g. the | |
789 | * aliasing ppgtt), but skip over the hung batch. | |
790 | * | |
791 | * If the request was innocent, we try to replay the request | |
792 | * with the restored context. | |
793 | */ | |
794 | i915_reset_request(rq, stalled); | |
795 | ||
796 | GEM_BUG_ON(rq->ring != engine->buffer); | |
797 | head = rq->head; | |
798 | } else { | |
799 | head = engine->buffer->tail; | |
c0dcb203 | 800 | } |
eb8d0f5a CW |
801 | engine->buffer->head = intel_ring_wrap(engine->buffer, head); |
802 | ||
803 | spin_unlock_irqrestore(&tl->lock, flags); | |
821ed7df CW |
804 | } |
805 | ||
5adfb772 CW |
806 | static void reset_finish(struct intel_engine_cs *engine) |
807 | { | |
808 | } | |
809 | ||
e61e0f51 | 810 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
811 | { |
812 | int ret; | |
813 | ||
452420d2 | 814 | ret = intel_engine_emit_ctx_wa(rq); |
8f0e2b9d DV |
815 | if (ret != 0) |
816 | return ret; | |
817 | ||
e61e0f51 | 818 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 819 | if (ret) |
e26e1b97 | 820 | return ret; |
8f0e2b9d | 821 | |
e26e1b97 | 822 | return 0; |
8f0e2b9d DV |
823 | } |
824 | ||
0bc40be8 | 825 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 826 | { |
c033666a | 827 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 828 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
829 | if (ret) |
830 | return ret; | |
a69ffdbf | 831 | |
61a563a2 | 832 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
00690008 | 833 | if (IS_GEN_RANGE(dev_priv, 4, 6)) |
6b26c86d | 834 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
835 | |
836 | /* We need to disable the AsyncFlip performance optimisations in order | |
837 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
838 | * programmed to '1' on all products. | |
8693a824 | 839 | * |
2441f877 | 840 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 841 | */ |
00690008 | 842 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
1c8c38c5 CW |
843 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
844 | ||
f05bb0c7 | 845 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 846 | /* WaEnableFlushTlbInvalidationMode:snb */ |
cf819eff | 847 | if (IS_GEN(dev_priv, 6)) |
f05bb0c7 | 848 | I915_WRITE(GFX_MODE, |
aa83e30d | 849 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 850 | |
01fa0302 | 851 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
cf819eff | 852 | if (IS_GEN(dev_priv, 7)) |
1c8c38c5 | 853 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 854 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 855 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 856 | |
cf819eff | 857 | if (IS_GEN(dev_priv, 6)) { |
3a69ddd6 KG |
858 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
859 | * "If this bit is set, STCunit will have LRA as replacement | |
860 | * policy. [...] This bit must be reset. LRA replacement | |
861 | * policy is not supported." | |
862 | */ | |
863 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 864 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
865 | } |
866 | ||
00690008 | 867 | if (IS_GEN_RANGE(dev_priv, 6, 7)) |
6b26c86d | 868 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 869 | |
c56b89f1 | 870 | if (INTEL_GEN(dev_priv) >= 6) |
035ea405 | 871 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
15b9f80e | 872 | |
59b449d5 | 873 | return 0; |
8187a2b7 ZN |
874 | } |
875 | ||
27a5f61b CW |
876 | static void cancel_requests(struct intel_engine_cs *engine) |
877 | { | |
e61e0f51 | 878 | struct i915_request *request; |
27a5f61b CW |
879 | unsigned long flags; |
880 | ||
a89d1f92 | 881 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
882 | |
883 | /* Mark all submitted requests as skipped. */ | |
a89d1f92 | 884 | list_for_each_entry(request, &engine->timeline.requests, link) { |
5013eb8c CW |
885 | if (!i915_request_signaled(request)) |
886 | dma_fence_set_error(&request->fence, -EIO); | |
3800960a | 887 | |
5013eb8c | 888 | i915_request_mark_complete(request); |
27a5f61b | 889 | } |
3800960a | 890 | |
27a5f61b CW |
891 | /* Remaining _unready_ requests will be nop'ed when submitted */ |
892 | ||
a89d1f92 | 893 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
894 | } |
895 | ||
e61e0f51 | 896 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d CW |
897 | { |
898 | struct drm_i915_private *dev_priv = request->i915; | |
899 | ||
e61e0f51 | 900 | i915_request_submit(request); |
d55ac5bf | 901 | |
e6ba9992 CW |
902 | I915_WRITE_TAIL(request->engine, |
903 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
904 | } |
905 | ||
e1a73a54 | 906 | static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 907 | { |
5013eb8c CW |
908 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
909 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
910 | ||
caa5915b CW |
911 | *cs++ = MI_FLUSH; |
912 | ||
5013eb8c CW |
913 | *cs++ = MI_STORE_DWORD_INDEX; |
914 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; | |
915 | *cs++ = rq->fence.seqno; | |
916 | ||
89531e7d CW |
917 | *cs++ = MI_STORE_DWORD_INDEX; |
918 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR; | |
919 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
920 | ||
73dec95e | 921 | *cs++ = MI_USER_INTERRUPT; |
1ec14ad3 | 922 | |
e61e0f51 CW |
923 | rq->tail = intel_ring_offset(rq, cs); |
924 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
925 | |
926 | return cs; | |
1ec14ad3 | 927 | } |
98f29e8d | 928 | |
835051d3 | 929 | #define GEN5_WA_STORES 8 /* must be at least 1! */ |
e1a73a54 | 930 | static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
c6df541c | 931 | { |
835051d3 CW |
932 | int i; |
933 | ||
5013eb8c CW |
934 | GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); |
935 | GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); | |
936 | ||
835051d3 CW |
937 | *cs++ = MI_FLUSH; |
938 | ||
89531e7d CW |
939 | *cs++ = MI_STORE_DWORD_INDEX; |
940 | *cs++ = I915_GEM_HWS_HANGCHECK_ADDR; | |
941 | *cs++ = intel_engine_next_hangcheck_seqno(rq->engine); | |
942 | ||
835051d3 CW |
943 | BUILD_BUG_ON(GEN5_WA_STORES < 1); |
944 | for (i = 0; i < GEN5_WA_STORES; i++) { | |
945 | *cs++ = MI_STORE_DWORD_INDEX; | |
b300fde8 CW |
946 | *cs++ = I915_GEM_HWS_SEQNO_ADDR; |
947 | *cs++ = rq->fence.seqno; | |
835051d3 CW |
948 | } |
949 | ||
950 | *cs++ = MI_USER_INTERRUPT; | |
b300fde8 | 951 | *cs++ = MI_NOOP; |
835051d3 CW |
952 | |
953 | rq->tail = intel_ring_offset(rq, cs); | |
954 | assert_ring_tail_valid(rq->ring, rq->tail); | |
e1a73a54 CW |
955 | |
956 | return cs; | |
c6df541c | 957 | } |
835051d3 | 958 | #undef GEN5_WA_STORES |
c6df541c | 959 | |
31bb59cc CW |
960 | static void |
961 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 962 | { |
31bb59cc | 963 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
964 | } |
965 | ||
966 | static void | |
31bb59cc | 967 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 968 | { |
31bb59cc | 969 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
970 | } |
971 | ||
31bb59cc CW |
972 | static void |
973 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 974 | { |
c033666a | 975 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 976 | |
31bb59cc CW |
977 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
978 | I915_WRITE(IMR, dev_priv->irq_mask); | |
979 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
980 | } |
981 | ||
8187a2b7 | 982 | static void |
31bb59cc | 983 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 984 | { |
c033666a | 985 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 986 | |
31bb59cc CW |
987 | dev_priv->irq_mask |= engine->irq_enable_mask; |
988 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
989 | } |
990 | ||
31bb59cc CW |
991 | static void |
992 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 993 | { |
c033666a | 994 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 995 | |
31bb59cc CW |
996 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
997 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
998 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
999 | } |
1000 | ||
1001 | static void | |
31bb59cc | 1002 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1003 | { |
c033666a | 1004 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1005 | |
31bb59cc CW |
1006 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1007 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1008 | } |
1009 | ||
b72f3acb | 1010 | static int |
e61e0f51 | 1011 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 1012 | { |
73dec95e | 1013 | u32 *cs; |
b72f3acb | 1014 | |
e61e0f51 | 1015 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1016 | if (IS_ERR(cs)) |
1017 | return PTR_ERR(cs); | |
b72f3acb | 1018 | |
73dec95e TU |
1019 | *cs++ = MI_FLUSH; |
1020 | *cs++ = MI_NOOP; | |
e61e0f51 | 1021 | intel_ring_advance(rq, cs); |
b72f3acb | 1022 | return 0; |
d1b851fc ZN |
1023 | } |
1024 | ||
31bb59cc CW |
1025 | static void |
1026 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1027 | { |
c033666a | 1028 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1029 | |
61ff75ac CW |
1030 | I915_WRITE_IMR(engine, |
1031 | ~(engine->irq_enable_mask | | |
1032 | engine->irq_keep_mask)); | |
476af9c2 CW |
1033 | |
1034 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1035 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1036 | ||
31bb59cc | 1037 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1038 | } |
1039 | ||
1040 | static void | |
31bb59cc | 1041 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1042 | { |
c033666a | 1043 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1044 | |
61ff75ac | 1045 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1046 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1047 | } |
1048 | ||
31bb59cc CW |
1049 | static void |
1050 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1051 | { |
c033666a | 1052 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1053 | |
31bb59cc | 1054 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
e4fc69f2 CW |
1055 | |
1056 | /* Flush/delay to ensure the RING_IMR is active before the GT IMR */ | |
1057 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
1058 | ||
f4e9af4f | 1059 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1060 | } |
1061 | ||
1062 | static void | |
31bb59cc | 1063 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1064 | { |
c033666a | 1065 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1066 | |
31bb59cc | 1067 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1068 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1069 | } |
1070 | ||
d1b851fc | 1071 | static int |
e61e0f51 | 1072 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1073 | u64 offset, u32 length, |
1074 | unsigned int dispatch_flags) | |
d1b851fc | 1075 | { |
73dec95e | 1076 | u32 *cs; |
78501eac | 1077 | |
e61e0f51 | 1078 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1079 | if (IS_ERR(cs)) |
1080 | return PTR_ERR(cs); | |
e1f99ce6 | 1081 | |
73dec95e TU |
1082 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1083 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1084 | *cs++ = offset; | |
e61e0f51 | 1085 | intel_ring_advance(rq, cs); |
78501eac | 1086 | |
d1b851fc ZN |
1087 | return 0; |
1088 | } | |
1089 | ||
b45305fc | 1090 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
51797499 | 1091 | #define I830_BATCH_LIMIT SZ_256K |
c4d69da1 CW |
1092 | #define I830_TLB_ENTRIES (2) |
1093 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1094 | static int |
e61e0f51 | 1095 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1096 | u64 offset, u32 len, |
1097 | unsigned int dispatch_flags) | |
62fdfeaf | 1098 | { |
51797499 CW |
1099 | u32 *cs, cs_offset = i915_scratch_offset(rq->i915); |
1100 | ||
1101 | GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE); | |
62fdfeaf | 1102 | |
e61e0f51 | 1103 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
1104 | if (IS_ERR(cs)) |
1105 | return PTR_ERR(cs); | |
62fdfeaf | 1106 | |
c4d69da1 | 1107 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1108 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1109 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1110 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1111 | *cs++ = cs_offset; | |
1112 | *cs++ = 0xdeadbeef; | |
1113 | *cs++ = MI_NOOP; | |
e61e0f51 | 1114 | intel_ring_advance(rq, cs); |
b45305fc | 1115 | |
8e004efc | 1116 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1117 | if (len > I830_BATCH_LIMIT) |
1118 | return -ENOSPC; | |
1119 | ||
e61e0f51 | 1120 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
1121 | if (IS_ERR(cs)) |
1122 | return PTR_ERR(cs); | |
c4d69da1 CW |
1123 | |
1124 | /* Blit the batch (which has now all relocs applied) to the | |
1125 | * stable batch scratch bo area (so that the CS never | |
1126 | * stumbles over its tlb invalidation bug) ... | |
1127 | */ | |
73dec95e TU |
1128 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1129 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1130 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1131 | *cs++ = cs_offset; | |
1132 | *cs++ = 4096; | |
1133 | *cs++ = offset; | |
1134 | ||
1135 | *cs++ = MI_FLUSH; | |
1136 | *cs++ = MI_NOOP; | |
e61e0f51 | 1137 | intel_ring_advance(rq, cs); |
b45305fc DV |
1138 | |
1139 | /* ... and execute it. */ | |
c4d69da1 | 1140 | offset = cs_offset; |
b45305fc | 1141 | } |
e1f99ce6 | 1142 | |
e61e0f51 | 1143 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1144 | if (IS_ERR(cs)) |
1145 | return PTR_ERR(cs); | |
c4d69da1 | 1146 | |
73dec95e TU |
1147 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1148 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1149 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1150 | intel_ring_advance(rq, cs); |
c4d69da1 | 1151 | |
fb3256da DV |
1152 | return 0; |
1153 | } | |
1154 | ||
1155 | static int | |
e61e0f51 | 1156 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1157 | u64 offset, u32 len, |
1158 | unsigned int dispatch_flags) | |
fb3256da | 1159 | { |
73dec95e | 1160 | u32 *cs; |
fb3256da | 1161 | |
e61e0f51 | 1162 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1163 | if (IS_ERR(cs)) |
1164 | return PTR_ERR(cs); | |
fb3256da | 1165 | |
73dec95e TU |
1166 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1167 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1168 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1169 | intel_ring_advance(rq, cs); |
62fdfeaf | 1170 | |
62fdfeaf EA |
1171 | return 0; |
1172 | } | |
1173 | ||
5503cb0d | 1174 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1175 | { |
57e88531 | 1176 | struct i915_vma *vma = ring->vma; |
89d5efcc | 1177 | enum i915_map_type map = i915_coherent_map_type(vma->vm->i915); |
d822bb18 | 1178 | unsigned int flags; |
8305216f | 1179 | void *addr; |
7ba717cf TD |
1180 | int ret; |
1181 | ||
57e88531 | 1182 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1183 | |
5013eb8c CW |
1184 | ret = i915_timeline_pin(ring->timeline); |
1185 | if (ret) | |
1186 | return ret; | |
1187 | ||
d3ef1af6 | 1188 | flags = PIN_GLOBAL; |
496bcce3 JB |
1189 | |
1190 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ | |
1191 | flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma); | |
1192 | ||
9d80841e | 1193 | if (vma->obj->stolen) |
57e88531 | 1194 | flags |= PIN_MAPPABLE; |
2edd4e69 CW |
1195 | else |
1196 | flags |= PIN_HIGH; | |
def0c5f6 | 1197 | |
57e88531 | 1198 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1199 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1200 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1201 | else | |
1202 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1203 | if (unlikely(ret)) | |
5013eb8c | 1204 | goto unpin_timeline; |
57e88531 | 1205 | } |
7ba717cf | 1206 | |
7a859c65 | 1207 | ret = i915_vma_pin(vma, 0, 0, flags); |
57e88531 | 1208 | if (unlikely(ret)) |
5013eb8c | 1209 | goto unpin_timeline; |
def0c5f6 | 1210 | |
9d80841e | 1211 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1212 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1213 | else | |
9d80841e | 1214 | addr = i915_gem_object_pin_map(vma->obj, map); |
5013eb8c CW |
1215 | if (IS_ERR(addr)) { |
1216 | ret = PTR_ERR(addr); | |
1217 | goto unpin_ring; | |
1218 | } | |
7ba717cf | 1219 | |
3d574a6b CW |
1220 | vma->obj->pin_global++; |
1221 | ||
32c04f16 | 1222 | ring->vaddr = addr; |
7ba717cf | 1223 | return 0; |
d2cad535 | 1224 | |
5013eb8c | 1225 | unpin_ring: |
57e88531 | 1226 | i915_vma_unpin(vma); |
5013eb8c CW |
1227 | unpin_timeline: |
1228 | i915_timeline_unpin(ring->timeline); | |
1229 | return ret; | |
7ba717cf TD |
1230 | } |
1231 | ||
e6ba9992 CW |
1232 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1233 | { | |
41d37680 CW |
1234 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1235 | ||
e6ba9992 CW |
1236 | ring->tail = tail; |
1237 | ring->head = tail; | |
1238 | ring->emit = tail; | |
1239 | intel_ring_update_space(ring); | |
1240 | } | |
1241 | ||
aad29fbb CW |
1242 | void intel_ring_unpin(struct intel_ring *ring) |
1243 | { | |
1244 | GEM_BUG_ON(!ring->vma); | |
1245 | GEM_BUG_ON(!ring->vaddr); | |
1246 | ||
e6ba9992 CW |
1247 | /* Discard any unused bytes beyond that submitted to hw. */ |
1248 | intel_ring_reset(ring, ring->tail); | |
1249 | ||
9d80841e | 1250 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1251 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1252 | else |
1253 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1254 | ring->vaddr = NULL; |
1255 | ||
3d574a6b | 1256 | ring->vma->obj->pin_global--; |
57e88531 | 1257 | i915_vma_unpin(ring->vma); |
5013eb8c CW |
1258 | |
1259 | i915_timeline_unpin(ring->timeline); | |
2919d291 OM |
1260 | } |
1261 | ||
57e88531 CW |
1262 | static struct i915_vma * |
1263 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1264 | { |
250f8c81 | 1265 | struct i915_address_space *vm = &dev_priv->ggtt.vm; |
05394f39 | 1266 | struct drm_i915_gem_object *obj; |
57e88531 | 1267 | struct i915_vma *vma; |
62fdfeaf | 1268 | |
187685cb | 1269 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1270 | if (!obj) |
2d6c4c84 | 1271 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1272 | if (IS_ERR(obj)) |
1273 | return ERR_CAST(obj); | |
8187a2b7 | 1274 | |
250f8c81 JB |
1275 | /* |
1276 | * Mark ring buffers as read-only from GPU side (so no stray overwrites) | |
1277 | * if supported by the platform's GGTT. | |
1278 | */ | |
1279 | if (vm->has_read_only) | |
3e977ac6 | 1280 | i915_gem_object_set_readonly(obj); |
24f3a8cf | 1281 | |
250f8c81 | 1282 | vma = i915_vma_instance(obj, vm, NULL); |
57e88531 CW |
1283 | if (IS_ERR(vma)) |
1284 | goto err; | |
1285 | ||
1286 | return vma; | |
e3efda49 | 1287 | |
57e88531 CW |
1288 | err: |
1289 | i915_gem_object_put(obj); | |
1290 | return vma; | |
e3efda49 CW |
1291 | } |
1292 | ||
7e37f889 | 1293 | struct intel_ring * |
65fcb806 | 1294 | intel_engine_create_ring(struct intel_engine_cs *engine, |
a89d1f92 | 1295 | struct i915_timeline *timeline, |
65fcb806 | 1296 | int size) |
01101fa7 | 1297 | { |
7e37f889 | 1298 | struct intel_ring *ring; |
57e88531 | 1299 | struct i915_vma *vma; |
01101fa7 | 1300 | |
8f942018 | 1301 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1302 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
a89d1f92 | 1303 | GEM_BUG_ON(timeline == &engine->timeline); |
b887d615 | 1304 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
8f942018 | 1305 | |
01101fa7 | 1306 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1307 | if (!ring) |
01101fa7 CW |
1308 | return ERR_PTR(-ENOMEM); |
1309 | ||
65baf0ef | 1310 | kref_init(&ring->ref); |
675d9ad7 | 1311 | INIT_LIST_HEAD(&ring->request_list); |
a89d1f92 | 1312 | ring->timeline = i915_timeline_get(timeline); |
675d9ad7 | 1313 | |
01101fa7 CW |
1314 | ring->size = size; |
1315 | /* Workaround an erratum on the i830 which causes a hang if | |
1316 | * the TAIL pointer points to within the last 2 cachelines | |
1317 | * of the buffer. | |
1318 | */ | |
1319 | ring->effective_size = size; | |
2a307c2e | 1320 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1321 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1322 | ||
01101fa7 CW |
1323 | intel_ring_update_space(ring); |
1324 | ||
57e88531 CW |
1325 | vma = intel_ring_create_vma(engine->i915, size); |
1326 | if (IS_ERR(vma)) { | |
01101fa7 | 1327 | kfree(ring); |
57e88531 | 1328 | return ERR_CAST(vma); |
01101fa7 | 1329 | } |
57e88531 | 1330 | ring->vma = vma; |
01101fa7 CW |
1331 | |
1332 | return ring; | |
1333 | } | |
1334 | ||
65baf0ef | 1335 | void intel_ring_free(struct kref *ref) |
01101fa7 | 1336 | { |
65baf0ef | 1337 | struct intel_ring *ring = container_of(ref, typeof(*ring), ref); |
f8a7fde4 CW |
1338 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1339 | ||
1340 | i915_vma_close(ring->vma); | |
1341 | __i915_gem_object_release_unless_active(obj); | |
1342 | ||
a89d1f92 | 1343 | i915_timeline_put(ring->timeline); |
01101fa7 CW |
1344 | kfree(ring); |
1345 | } | |
1346 | ||
c4d52feb CW |
1347 | static void __ring_context_fini(struct intel_context *ce) |
1348 | { | |
1349 | GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj)); | |
1350 | i915_gem_object_put(ce->state->obj); | |
1351 | } | |
1352 | ||
4c5896dc | 1353 | static void ring_context_destroy(struct kref *ref) |
1fc44d9b | 1354 | { |
4c5896dc CW |
1355 | struct intel_context *ce = container_of(ref, typeof(*ce), ref); |
1356 | ||
08819549 | 1357 | GEM_BUG_ON(intel_context_is_pinned(ce)); |
1fc44d9b | 1358 | |
c4d52feb CW |
1359 | if (ce->state) |
1360 | __ring_context_fini(ce); | |
efe79d48 | 1361 | |
c4d52feb | 1362 | intel_context_free(ce); |
1fc44d9b CW |
1363 | } |
1364 | ||
a2bbf714 CW |
1365 | static int __context_pin_ppgtt(struct i915_gem_context *ctx) |
1366 | { | |
1367 | struct i915_hw_ppgtt *ppgtt; | |
1368 | int err = 0; | |
1369 | ||
1370 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1371 | if (ppgtt) | |
1372 | err = gen6_ppgtt_pin(ppgtt); | |
1373 | ||
1374 | return err; | |
1375 | } | |
1376 | ||
1377 | static void __context_unpin_ppgtt(struct i915_gem_context *ctx) | |
1378 | { | |
1379 | struct i915_hw_ppgtt *ppgtt; | |
1380 | ||
1381 | ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt; | |
1382 | if (ppgtt) | |
1383 | gen6_ppgtt_unpin(ppgtt); | |
1384 | } | |
1385 | ||
1fc44d9b | 1386 | static int __context_pin(struct intel_context *ce) |
e8a9c58f | 1387 | { |
d901e8e6 CW |
1388 | struct i915_vma *vma; |
1389 | int err; | |
1390 | ||
1391 | vma = ce->state; | |
1392 | if (!vma) | |
1393 | return 0; | |
e8a9c58f | 1394 | |
f4e15af7 CW |
1395 | /* |
1396 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1397 | * We only want to do this on the first bind so that we do not stall |
1398 | * on an active context (which by nature is already on the GPU). | |
1399 | */ | |
1400 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
d901e8e6 CW |
1401 | err = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1402 | if (err) | |
1403 | return err; | |
e8a9c58f CW |
1404 | } |
1405 | ||
7a859c65 | 1406 | err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); |
d901e8e6 CW |
1407 | if (err) |
1408 | return err; | |
1409 | ||
1410 | /* | |
1411 | * And mark is as a globally pinned object to let the shrinker know | |
1412 | * it cannot reclaim the object until we release it. | |
1413 | */ | |
1414 | vma->obj->pin_global++; | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static void __context_unpin(struct intel_context *ce) | |
1420 | { | |
1421 | struct i915_vma *vma; | |
1422 | ||
1423 | vma = ce->state; | |
1424 | if (!vma) | |
1425 | return; | |
1426 | ||
1427 | vma->obj->pin_global--; | |
1428 | i915_vma_unpin(vma); | |
1429 | } | |
1430 | ||
4dc84b77 | 1431 | static void ring_context_unpin(struct intel_context *ce) |
d901e8e6 | 1432 | { |
a2bbf714 | 1433 | __context_unpin_ppgtt(ce->gem_context); |
d901e8e6 | 1434 | __context_unpin(ce); |
e8a9c58f CW |
1435 | } |
1436 | ||
3204c343 CW |
1437 | static struct i915_vma * |
1438 | alloc_context_vma(struct intel_engine_cs *engine) | |
1439 | { | |
1440 | struct drm_i915_private *i915 = engine->i915; | |
1441 | struct drm_i915_gem_object *obj; | |
1442 | struct i915_vma *vma; | |
d2b4b979 | 1443 | int err; |
3204c343 | 1444 | |
63ffbcda | 1445 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1446 | if (IS_ERR(obj)) |
1447 | return ERR_CAST(obj); | |
1448 | ||
d2b4b979 CW |
1449 | if (engine->default_state) { |
1450 | void *defaults, *vaddr; | |
1451 | ||
1452 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1453 | if (IS_ERR(vaddr)) { | |
1454 | err = PTR_ERR(vaddr); | |
1455 | goto err_obj; | |
1456 | } | |
1457 | ||
1458 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1459 | I915_MAP_WB); | |
1460 | if (IS_ERR(defaults)) { | |
1461 | err = PTR_ERR(defaults); | |
1462 | goto err_map; | |
1463 | } | |
1464 | ||
1465 | memcpy(vaddr, defaults, engine->context_size); | |
1466 | ||
1467 | i915_gem_object_unpin_map(engine->default_state); | |
1468 | i915_gem_object_unpin_map(obj); | |
1469 | } | |
1470 | ||
3204c343 CW |
1471 | /* |
1472 | * Try to make the context utilize L3 as well as LLC. | |
1473 | * | |
1474 | * On VLV we don't have L3 controls in the PTEs so we | |
1475 | * shouldn't touch the cache level, especially as that | |
1476 | * would make the object snooped which might have a | |
1477 | * negative performance impact. | |
1478 | * | |
1479 | * Snooping is required on non-llc platforms in execlist | |
1480 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1481 | * get snooping anyway regardless of cache_level. | |
1482 | * | |
1483 | * This is only applicable for Ivy Bridge devices since | |
1484 | * later platforms don't have L3 control bits in the PTE. | |
1485 | */ | |
1486 | if (IS_IVYBRIDGE(i915)) { | |
1487 | /* Ignore any error, regard it as a simple optimisation */ | |
1488 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1489 | } | |
1490 | ||
82ad6443 | 1491 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); |
d2b4b979 CW |
1492 | if (IS_ERR(vma)) { |
1493 | err = PTR_ERR(vma); | |
1494 | goto err_obj; | |
1495 | } | |
3204c343 CW |
1496 | |
1497 | return vma; | |
d2b4b979 CW |
1498 | |
1499 | err_map: | |
1500 | i915_gem_object_unpin_map(obj); | |
1501 | err_obj: | |
1502 | i915_gem_object_put(obj); | |
1503 | return ERR_PTR(err); | |
3204c343 CW |
1504 | } |
1505 | ||
95f697eb | 1506 | static int ring_context_pin(struct intel_context *ce) |
0cb26a8e | 1507 | { |
95f697eb | 1508 | struct intel_engine_cs *engine = ce->engine; |
1fc44d9b | 1509 | int err; |
0cb26a8e | 1510 | |
7e3d9a59 CW |
1511 | /* One ringbuffer to rule them all */ |
1512 | GEM_BUG_ON(!engine->buffer); | |
1513 | ce->ring = engine->buffer; | |
1514 | ||
63ffbcda | 1515 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1516 | struct i915_vma *vma; |
1517 | ||
1518 | vma = alloc_context_vma(engine); | |
95f697eb CW |
1519 | if (IS_ERR(vma)) |
1520 | return PTR_ERR(vma); | |
3204c343 CW |
1521 | |
1522 | ce->state = vma; | |
1523 | } | |
1524 | ||
d901e8e6 CW |
1525 | err = __context_pin(ce); |
1526 | if (err) | |
95f697eb | 1527 | return err; |
0cb26a8e | 1528 | |
a2bbf714 CW |
1529 | err = __context_pin_ppgtt(ce->gem_context); |
1530 | if (err) | |
1531 | goto err_unpin; | |
1532 | ||
95f697eb | 1533 | return 0; |
266a240b | 1534 | |
a2bbf714 CW |
1535 | err_unpin: |
1536 | __context_unpin(ce); | |
95f697eb | 1537 | return err; |
0cb26a8e CW |
1538 | } |
1539 | ||
4dc84b77 | 1540 | static const struct intel_context_ops ring_context_ops = { |
95f697eb | 1541 | .pin = ring_context_pin, |
4dc84b77 CW |
1542 | .unpin = ring_context_unpin, |
1543 | .destroy = ring_context_destroy, | |
1544 | }; | |
1545 | ||
acd27845 | 1546 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1547 | { |
a89d1f92 | 1548 | struct i915_timeline *timeline; |
d9d117e4 | 1549 | struct intel_ring *ring; |
1a5788bf | 1550 | int err; |
bfc882b4 | 1551 | |
52954edd CW |
1552 | err = intel_engine_setup_common(engine); |
1553 | if (err) | |
1554 | return err; | |
019bf277 | 1555 | |
4daffb66 | 1556 | timeline = i915_timeline_create(engine->i915, engine->status_page.vma); |
a89d1f92 CW |
1557 | if (IS_ERR(timeline)) { |
1558 | err = PTR_ERR(timeline); | |
1559 | goto err; | |
1560 | } | |
85474441 | 1561 | GEM_BUG_ON(timeline->has_initial_breadcrumb); |
a89d1f92 CW |
1562 | |
1563 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
1564 | i915_timeline_put(timeline); | |
d822bb18 | 1565 | if (IS_ERR(ring)) { |
1a5788bf | 1566 | err = PTR_ERR(ring); |
486e93f7 | 1567 | goto err; |
d822bb18 CW |
1568 | } |
1569 | ||
5503cb0d | 1570 | err = intel_ring_pin(ring); |
1a5788bf CW |
1571 | if (err) |
1572 | goto err_ring; | |
1573 | ||
1574 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1575 | engine->buffer = ring; |
62fdfeaf | 1576 | |
d9d117e4 CW |
1577 | err = intel_engine_init_common(engine); |
1578 | if (err) | |
51797499 | 1579 | goto err_unpin; |
d9d117e4 | 1580 | |
52954edd CW |
1581 | GEM_BUG_ON(ring->timeline->hwsp_ggtt != engine->status_page.vma); |
1582 | ||
8ee14975 | 1583 | return 0; |
351e3db2 | 1584 | |
1fc44d9b CW |
1585 | err_unpin: |
1586 | intel_ring_unpin(ring); | |
1a5788bf | 1587 | err_ring: |
65baf0ef | 1588 | intel_ring_put(ring); |
1a5788bf CW |
1589 | err: |
1590 | intel_engine_cleanup_common(engine); | |
1591 | return err; | |
62fdfeaf EA |
1592 | } |
1593 | ||
7e37f889 | 1594 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1595 | { |
1a5788bf | 1596 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1597 | |
1a5788bf CW |
1598 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1599 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1600 | |
1a5788bf | 1601 | intel_ring_unpin(engine->buffer); |
65baf0ef | 1602 | intel_ring_put(engine->buffer); |
78501eac | 1603 | |
0bc40be8 TU |
1604 | if (engine->cleanup) |
1605 | engine->cleanup(engine); | |
8d19215b | 1606 | |
96a945aa | 1607 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1608 | |
3b3f1650 AG |
1609 | dev_priv->engine[engine->id] = NULL; |
1610 | kfree(engine); | |
62fdfeaf EA |
1611 | } |
1612 | ||
821ed7df CW |
1613 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1614 | { | |
1615 | struct intel_engine_cs *engine; | |
3b3f1650 | 1616 | enum intel_engine_id id; |
821ed7df | 1617 | |
e6ba9992 | 1618 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1619 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1620 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1621 | } |
1622 | ||
b3ee09a4 CW |
1623 | static int load_pd_dir(struct i915_request *rq, |
1624 | const struct i915_hw_ppgtt *ppgtt) | |
1625 | { | |
1626 | const struct intel_engine_cs * const engine = rq->engine; | |
1627 | u32 *cs; | |
1628 | ||
1629 | cs = intel_ring_begin(rq, 6); | |
1630 | if (IS_ERR(cs)) | |
1631 | return PTR_ERR(cs); | |
1632 | ||
1633 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1634 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1635 | *cs++ = PP_DIR_DCLV_2G; | |
1636 | ||
1637 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1638 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1639 | *cs++ = ppgtt->pd.base.ggtt_offset << 10; | |
1640 | ||
1641 | intel_ring_advance(rq, cs); | |
1642 | ||
1643 | return 0; | |
1644 | } | |
1645 | ||
d9d117e4 CW |
1646 | static int flush_pd_dir(struct i915_request *rq) |
1647 | { | |
1648 | const struct intel_engine_cs * const engine = rq->engine; | |
1649 | u32 *cs; | |
1650 | ||
1651 | cs = intel_ring_begin(rq, 4); | |
1652 | if (IS_ERR(cs)) | |
1653 | return PTR_ERR(cs); | |
1654 | ||
1655 | /* Stall until the page table load is complete */ | |
1656 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1657 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
51797499 | 1658 | *cs++ = i915_scratch_offset(rq->i915); |
d9d117e4 CW |
1659 | *cs++ = MI_NOOP; |
1660 | ||
1661 | intel_ring_advance(rq, cs); | |
1662 | return 0; | |
1663 | } | |
1664 | ||
e61e0f51 | 1665 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1666 | { |
1667 | struct drm_i915_private *i915 = rq->i915; | |
1668 | struct intel_engine_cs *engine = rq->engine; | |
1669 | enum intel_engine_id id; | |
8a68d464 CW |
1670 | const int num_engines = |
1671 | IS_HSW_GT1(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0; | |
1fc719d1 | 1672 | bool force_restore = false; |
8911a31c CW |
1673 | int len; |
1674 | u32 *cs; | |
1675 | ||
1676 | flags |= MI_MM_SPACE_GTT; | |
1677 | if (IS_HASWELL(i915)) | |
1678 | /* These flags are for resource streamer on HSW+ */ | |
1679 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1680 | else | |
1681 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
1682 | ||
1683 | len = 4; | |
cf819eff | 1684 | if (IS_GEN(i915, 7)) |
8a68d464 | 1685 | len += 2 + (num_engines ? 4 * num_engines + 6 : 0); |
1fc719d1 CW |
1686 | if (flags & MI_FORCE_RESTORE) { |
1687 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1688 | flags &= ~MI_FORCE_RESTORE; | |
1689 | force_restore = true; | |
1690 | len += 2; | |
1691 | } | |
8911a31c CW |
1692 | |
1693 | cs = intel_ring_begin(rq, len); | |
1694 | if (IS_ERR(cs)) | |
1695 | return PTR_ERR(cs); | |
1696 | ||
1697 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
cf819eff | 1698 | if (IS_GEN(i915, 7)) { |
8911a31c | 1699 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
8a68d464 | 1700 | if (num_engines) { |
8911a31c CW |
1701 | struct intel_engine_cs *signaller; |
1702 | ||
8a68d464 | 1703 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1704 | for_each_engine(signaller, i915, id) { |
1705 | if (signaller == engine) | |
1706 | continue; | |
1707 | ||
1708 | *cs++ = i915_mmio_reg_offset( | |
1709 | RING_PSMI_CTL(signaller->mmio_base)); | |
1710 | *cs++ = _MASKED_BIT_ENABLE( | |
1711 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1712 | } | |
1713 | } | |
1714 | } | |
1715 | ||
1fc719d1 CW |
1716 | if (force_restore) { |
1717 | /* | |
1718 | * The HW doesn't handle being told to restore the current | |
1719 | * context very well. Quite often it likes goes to go off and | |
1720 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1721 | * A very simple fix to force the reload is to simply switch | |
1722 | * away from the current context and back again. | |
1723 | * | |
1724 | * Note that the kernel_context will contain random state | |
1725 | * following the INHIBIT_RESTORE. We accept this since we | |
1726 | * never use the kernel_context state; it is merely a | |
1727 | * placeholder we use to flush other contexts. | |
1728 | */ | |
1729 | *cs++ = MI_SET_CONTEXT; | |
9dbfea98 | 1730 | *cs++ = i915_ggtt_offset(engine->kernel_context->state) | |
1fc719d1 CW |
1731 | MI_MM_SPACE_GTT | |
1732 | MI_RESTORE_INHIBIT; | |
1733 | } | |
1734 | ||
8911a31c CW |
1735 | *cs++ = MI_NOOP; |
1736 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1737 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1738 | /* |
1739 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1740 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1741 | */ | |
1742 | *cs++ = MI_NOOP; | |
1743 | ||
cf819eff | 1744 | if (IS_GEN(i915, 7)) { |
8a68d464 | 1745 | if (num_engines) { |
8911a31c CW |
1746 | struct intel_engine_cs *signaller; |
1747 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1748 | ||
8a68d464 | 1749 | *cs++ = MI_LOAD_REGISTER_IMM(num_engines); |
8911a31c CW |
1750 | for_each_engine(signaller, i915, id) { |
1751 | if (signaller == engine) | |
1752 | continue; | |
1753 | ||
1754 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1755 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1756 | *cs++ = _MASKED_BIT_DISABLE( | |
1757 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1758 | } | |
1759 | ||
1760 | /* Insert a delay before the next switch! */ | |
1761 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1762 | *cs++ = i915_mmio_reg_offset(last_reg); | |
51797499 | 1763 | *cs++ = i915_scratch_offset(rq->i915); |
8911a31c CW |
1764 | *cs++ = MI_NOOP; |
1765 | } | |
1766 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1767 | } | |
1768 | ||
1769 | intel_ring_advance(rq, cs); | |
1770 | ||
1771 | return 0; | |
1772 | } | |
1773 | ||
e61e0f51 | 1774 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1775 | { |
1776 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1777 | int i; | |
1778 | ||
1779 | if (!remap_info) | |
1780 | return 0; | |
1781 | ||
1782 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1783 | if (IS_ERR(cs)) | |
1784 | return PTR_ERR(cs); | |
1785 | ||
1786 | /* | |
1787 | * Note: We do not worry about the concurrent register cacheline hang | |
1788 | * here because no other code should access these registers other than | |
1789 | * at initialization time. | |
1790 | */ | |
1791 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1792 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1793 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1794 | *cs++ = remap_info[i]; | |
1795 | } | |
1796 | *cs++ = MI_NOOP; | |
1797 | intel_ring_advance(rq, cs); | |
1798 | ||
1799 | return 0; | |
1800 | } | |
1801 | ||
e61e0f51 | 1802 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1803 | { |
1804 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 CW |
1805 | struct i915_gem_context *ctx = rq->gem_context; |
1806 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
1807 | unsigned int unwind_mm = 0; | |
8911a31c CW |
1808 | u32 hw_flags = 0; |
1809 | int ret, i; | |
1810 | ||
1811 | lockdep_assert_held(&rq->i915->drm.struct_mutex); | |
1812 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); | |
1813 | ||
b3ee09a4 | 1814 | if (ppgtt) { |
e2a13d1b CW |
1815 | int loops; |
1816 | ||
1817 | /* | |
1818 | * Baytail takes a little more convincing that it really needs | |
1819 | * to reload the PD between contexts. It is not just a little | |
1820 | * longer, as adding more stalls after the load_pd_dir (i.e. | |
1821 | * adding a long loop around flush_pd_dir) is not as effective | |
1822 | * as reloading the PD umpteen times. 32 is derived from | |
1823 | * experimentation (gem_exec_parallel/fds) and has no good | |
1824 | * explanation. | |
1825 | */ | |
1826 | loops = 1; | |
8a68d464 | 1827 | if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) |
e2a13d1b CW |
1828 | loops = 32; |
1829 | ||
1830 | do { | |
1831 | ret = load_pd_dir(rq, ppgtt); | |
1832 | if (ret) | |
1833 | goto err; | |
1834 | } while (--loops); | |
8911a31c | 1835 | |
8a68d464 CW |
1836 | if (ppgtt->pd_dirty_engines & engine->mask) { |
1837 | unwind_mm = engine->mask; | |
1838 | ppgtt->pd_dirty_engines &= ~unwind_mm; | |
b3ee09a4 CW |
1839 | hw_flags = MI_FORCE_RESTORE; |
1840 | } | |
8911a31c CW |
1841 | } |
1842 | ||
b3ee09a4 | 1843 | if (rq->hw_context->state) { |
8a68d464 | 1844 | GEM_BUG_ON(engine->id != RCS0); |
8911a31c CW |
1845 | |
1846 | /* | |
1847 | * The kernel context(s) is treated as pure scratch and is not | |
1848 | * expected to retain any state (as we sacrifice it during | |
1849 | * suspend and on resume it may be corrupted). This is ok, | |
1850 | * as nothing actually executes using the kernel context; it | |
1851 | * is purely used for flushing user contexts. | |
1852 | */ | |
b3ee09a4 | 1853 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1854 | hw_flags = MI_RESTORE_INHIBIT; |
1855 | ||
1856 | ret = mi_set_context(rq, hw_flags); | |
1857 | if (ret) | |
1858 | goto err_mm; | |
8911a31c | 1859 | } |
8911a31c | 1860 | |
d9d117e4 | 1861 | if (ppgtt) { |
06348d30 CW |
1862 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); |
1863 | if (ret) | |
1864 | goto err_mm; | |
1865 | ||
d9d117e4 CW |
1866 | ret = flush_pd_dir(rq); |
1867 | if (ret) | |
1868 | goto err_mm; | |
06348d30 CW |
1869 | |
1870 | /* | |
1871 | * Not only do we need a full barrier (post-sync write) after | |
1872 | * invalidating the TLBs, but we need to wait a little bit | |
1873 | * longer. Whether this is merely delaying us, or the | |
1874 | * subsequent flush is a key part of serialising with the | |
1875 | * post-sync op, this extra pass appears vital before a | |
1876 | * mm switch! | |
1877 | */ | |
1878 | ret = engine->emit_flush(rq, EMIT_INVALIDATE); | |
1879 | if (ret) | |
1880 | goto err_mm; | |
1881 | ||
1882 | ret = engine->emit_flush(rq, EMIT_FLUSH); | |
1883 | if (ret) | |
1884 | goto err_mm; | |
8911a31c CW |
1885 | } |
1886 | ||
b3ee09a4 | 1887 | if (ctx->remap_slice) { |
8911a31c | 1888 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1889 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1890 | continue; |
1891 | ||
1892 | ret = remap_l3(rq, i); | |
1893 | if (ret) | |
b3ee09a4 | 1894 | goto err_mm; |
8911a31c CW |
1895 | } |
1896 | ||
b3ee09a4 | 1897 | ctx->remap_slice = 0; |
8911a31c CW |
1898 | } |
1899 | ||
1900 | return 0; | |
1901 | ||
8911a31c | 1902 | err_mm: |
b3ee09a4 | 1903 | if (unwind_mm) |
8a68d464 | 1904 | ppgtt->pd_dirty_engines |= unwind_mm; |
8911a31c CW |
1905 | err: |
1906 | return ret; | |
1907 | } | |
1908 | ||
e61e0f51 | 1909 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1910 | { |
fd138212 | 1911 | int ret; |
6310346e | 1912 | |
08819549 | 1913 | GEM_BUG_ON(!intel_context_is_pinned(request->hw_context)); |
85474441 | 1914 | GEM_BUG_ON(request->timeline->has_initial_breadcrumb); |
e8a9c58f | 1915 | |
5f5800a7 CW |
1916 | /* |
1917 | * Flush enough space to reduce the likelihood of waiting after | |
6310346e CW |
1918 | * we start building the request - in which case we will just |
1919 | * have to repeat work. | |
1920 | */ | |
a0442461 | 1921 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1922 | |
f2253bd9 | 1923 | ret = switch_context(request); |
fd138212 CW |
1924 | if (ret) |
1925 | return ret; | |
6310346e | 1926 | |
f2253bd9 CW |
1927 | /* Unconditionally invalidate GPU caches and TLBs. */ |
1928 | ret = request->engine->emit_flush(request, EMIT_INVALIDATE); | |
3fef5cda CW |
1929 | if (ret) |
1930 | return ret; | |
1931 | ||
a0442461 | 1932 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1933 | return 0; |
9d773091 CW |
1934 | } |
1935 | ||
fd138212 | 1936 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1937 | { |
e61e0f51 | 1938 | struct i915_request *target; |
e95433c7 CW |
1939 | long timeout; |
1940 | ||
fd138212 | 1941 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1942 | |
95aebcb2 | 1943 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1944 | return 0; |
1945 | ||
36620032 | 1946 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1947 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1948 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1949 | if (bytes <= __intel_ring_space(target->postfix, |
1950 | ring->emit, ring->size)) | |
987046ad | 1951 | break; |
79bbcc29 | 1952 | } |
29b1b415 | 1953 | |
675d9ad7 | 1954 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1955 | return -ENOSPC; |
1956 | ||
e61e0f51 | 1957 | timeout = i915_request_wait(target, |
e95433c7 CW |
1958 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
1959 | MAX_SCHEDULE_TIMEOUT); | |
1960 | if (timeout < 0) | |
1961 | return timeout; | |
7da844c5 | 1962 | |
e61e0f51 | 1963 | i915_request_retire_upto(target); |
7da844c5 CW |
1964 | |
1965 | intel_ring_update_space(ring); | |
1966 | GEM_BUG_ON(ring->space < bytes); | |
1967 | return 0; | |
29b1b415 JH |
1968 | } |
1969 | ||
e61e0f51 | 1970 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1971 | { |
e61e0f51 | 1972 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1973 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1974 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1975 | unsigned int need_wrap = 0; | |
1976 | unsigned int total_bytes; | |
73dec95e | 1977 | u32 *cs; |
29b1b415 | 1978 | |
6492ca79 CW |
1979 | /* Packets must be qword aligned. */ |
1980 | GEM_BUG_ON(num_dwords & 1); | |
1981 | ||
e61e0f51 | 1982 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1983 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1984 | |
5e5655c3 CW |
1985 | if (unlikely(total_bytes > remain_usable)) { |
1986 | const int remain_actual = ring->size - ring->emit; | |
1987 | ||
1988 | if (bytes > remain_usable) { | |
1989 | /* | |
1990 | * Not enough space for the basic request. So need to | |
1991 | * flush out the remainder and then wait for | |
1992 | * base + reserved. | |
1993 | */ | |
1994 | total_bytes += remain_actual; | |
1995 | need_wrap = remain_actual | 1; | |
1996 | } else { | |
1997 | /* | |
1998 | * The base request will fit but the reserved space | |
1999 | * falls off the end. So we don't need an immediate | |
2000 | * wrap and only need to effectively wait for the | |
2001 | * reserved size from the start of ringbuffer. | |
2002 | */ | |
e61e0f51 | 2003 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 2004 | } |
cbcc80df MK |
2005 | } |
2006 | ||
5e5655c3 | 2007 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
2008 | int ret; |
2009 | ||
2010 | /* | |
2011 | * Space is reserved in the ringbuffer for finalising the | |
2012 | * request, as that cannot be allowed to fail. During request | |
2013 | * finalisation, reserved_space is set to 0 to stop the | |
2014 | * overallocation and the assumption is that then we never need | |
2015 | * to wait (which has the risk of failing with EINTR). | |
2016 | * | |
e61e0f51 | 2017 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 2018 | */ |
e61e0f51 | 2019 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
2020 | |
2021 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 2022 | if (unlikely(ret)) |
73dec95e | 2023 | return ERR_PTR(ret); |
cbcc80df MK |
2024 | } |
2025 | ||
987046ad | 2026 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
2027 | need_wrap &= ~1; |
2028 | GEM_BUG_ON(need_wrap > ring->space); | |
2029 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 2030 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 2031 | |
987046ad | 2032 | /* Fill the tail with MI_NOOP */ |
46b86332 | 2033 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 2034 | ring->space -= need_wrap; |
46b86332 | 2035 | ring->emit = 0; |
987046ad | 2036 | } |
304d695c | 2037 | |
e6ba9992 | 2038 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 2039 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 2040 | cs = ring->vaddr + ring->emit; |
46b86332 | 2041 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 2042 | ring->emit += bytes; |
1dae2dfb | 2043 | ring->space -= bytes; |
73dec95e TU |
2044 | |
2045 | return cs; | |
8187a2b7 | 2046 | } |
78501eac | 2047 | |
753b1ad4 | 2048 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 2049 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 2050 | { |
1f177a13 CW |
2051 | int num_dwords; |
2052 | void *cs; | |
753b1ad4 | 2053 | |
1f177a13 | 2054 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
2055 | if (num_dwords == 0) |
2056 | return 0; | |
2057 | ||
1f177a13 CW |
2058 | num_dwords = CACHELINE_DWORDS - num_dwords; |
2059 | GEM_BUG_ON(num_dwords & 1); | |
2060 | ||
e61e0f51 | 2061 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
2062 | if (IS_ERR(cs)) |
2063 | return PTR_ERR(cs); | |
753b1ad4 | 2064 | |
1f177a13 | 2065 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 2066 | intel_ring_advance(rq, cs); |
753b1ad4 | 2067 | |
1f177a13 | 2068 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
2069 | return 0; |
2070 | } | |
2071 | ||
e61e0f51 | 2072 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 2073 | { |
c5efa1ad | 2074 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2075 | |
3ceea6a1 | 2076 | intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); |
76f8421f | 2077 | |
881f47b6 | 2078 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2079 | |
2080 | /* Disable notification that the ring is IDLE. The GT | |
2081 | * will then assume that it is busy and bring it out of rc6. | |
2082 | */ | |
76f8421f CW |
2083 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2084 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2085 | |
2086 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2087 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2088 | |
12f55818 | 2089 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
2090 | if (__intel_wait_for_register_fw(dev_priv, |
2091 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2092 | GEN6_BSD_SLEEP_INDICATOR, | |
2093 | 0, | |
2094 | 1000, 0, NULL)) | |
12f55818 | 2095 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2096 | |
12f55818 | 2097 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2098 | i9xx_submit_request(request); |
12f55818 CW |
2099 | |
2100 | /* Let the ring send IDLE messages to the GT again, | |
2101 | * and so let it sleep to conserve power when idle. | |
2102 | */ | |
76f8421f CW |
2103 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2104 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2105 | ||
3ceea6a1 | 2106 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
881f47b6 XH |
2107 | } |
2108 | ||
06348d30 | 2109 | static int mi_flush_dw(struct i915_request *rq, u32 flags) |
881f47b6 | 2110 | { |
73dec95e | 2111 | u32 cmd, *cs; |
b72f3acb | 2112 | |
e61e0f51 | 2113 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
2114 | if (IS_ERR(cs)) |
2115 | return PTR_ERR(cs); | |
b72f3acb | 2116 | |
71a77e07 | 2117 | cmd = MI_FLUSH_DW; |
f0a1fb10 | 2118 | |
70b73f9a CW |
2119 | /* |
2120 | * We always require a command barrier so that subsequent | |
f0a1fb10 CW |
2121 | * commands, such as breadcrumb interrupts, are strictly ordered |
2122 | * wrt the contents of the write cache being flushed to memory | |
2123 | * (and thus being coherent from the CPU). | |
2124 | */ | |
2125 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2126 | ||
9a289771 | 2127 | /* |
70b73f9a | 2128 | * Bspec vol 1c.3 - blitter engine command streamer: |
9a289771 JB |
2129 | * "If ENABLED, all TLBs will be invalidated once the flush |
2130 | * operation is complete. This bit is only valid when the | |
2131 | * Post-Sync Operation field is a value of 1h or 3h." | |
2132 | */ | |
70b73f9a | 2133 | cmd |= flags; |
f0a1fb10 | 2134 | |
73dec95e TU |
2135 | *cs++ = cmd; |
2136 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 2137 | *cs++ = 0; |
73dec95e | 2138 | *cs++ = MI_NOOP; |
70b73f9a | 2139 | |
e61e0f51 | 2140 | intel_ring_advance(rq, cs); |
70b73f9a | 2141 | |
1c7a0623 BW |
2142 | return 0; |
2143 | } | |
2144 | ||
70b73f9a CW |
2145 | static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags) |
2146 | { | |
06348d30 | 2147 | return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0); |
70b73f9a CW |
2148 | } |
2149 | ||
2150 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) | |
2151 | { | |
2152 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); | |
2153 | } | |
2154 | ||
d7d4eedd | 2155 | static int |
e61e0f51 | 2156 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2157 | u64 offset, u32 len, |
2158 | unsigned int dispatch_flags) | |
d7d4eedd | 2159 | { |
73dec95e | 2160 | u32 *cs; |
d7d4eedd | 2161 | |
e61e0f51 | 2162 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2163 | if (IS_ERR(cs)) |
2164 | return PTR_ERR(cs); | |
d7d4eedd | 2165 | |
73dec95e | 2166 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
08e3e21a | 2167 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW); |
d7d4eedd | 2168 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2169 | *cs++ = offset; |
e61e0f51 | 2170 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
2171 | |
2172 | return 0; | |
2173 | } | |
2174 | ||
881f47b6 | 2175 | static int |
e61e0f51 | 2176 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
2177 | u64 offset, u32 len, |
2178 | unsigned int dispatch_flags) | |
881f47b6 | 2179 | { |
73dec95e | 2180 | u32 *cs; |
ab6f8e32 | 2181 | |
e61e0f51 | 2182 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
2183 | if (IS_ERR(cs)) |
2184 | return PTR_ERR(cs); | |
e1f99ce6 | 2185 | |
73dec95e TU |
2186 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
2187 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 2188 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 2189 | *cs++ = offset; |
e61e0f51 | 2190 | intel_ring_advance(rq, cs); |
ab6f8e32 | 2191 | |
0206e353 | 2192 | return 0; |
881f47b6 XH |
2193 | } |
2194 | ||
549f7365 CW |
2195 | /* Blitter support (SandyBridge+) */ |
2196 | ||
e61e0f51 | 2197 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 2198 | { |
70b73f9a | 2199 | return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); |
8d19215b ZN |
2200 | } |
2201 | ||
ed003078 CW |
2202 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2203 | struct intel_engine_cs *engine) | |
2204 | { | |
79e6770c | 2205 | if (INTEL_GEN(dev_priv) >= 6) { |
31bb59cc CW |
2206 | engine->irq_enable = gen6_irq_enable; |
2207 | engine->irq_disable = gen6_irq_disable; | |
ed003078 | 2208 | } else if (INTEL_GEN(dev_priv) >= 5) { |
31bb59cc CW |
2209 | engine->irq_enable = gen5_irq_enable; |
2210 | engine->irq_disable = gen5_irq_disable; | |
ed003078 | 2211 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2212 | engine->irq_enable = i9xx_irq_enable; |
2213 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2214 | } else { |
31bb59cc CW |
2215 | engine->irq_enable = i8xx_irq_enable; |
2216 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2217 | } |
2218 | } | |
2219 | ||
ff44ad51 CW |
2220 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2221 | { | |
2222 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2223 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2224 | |
2225 | engine->park = NULL; | |
2226 | engine->unpark = NULL; | |
ff44ad51 CW |
2227 | } |
2228 | ||
2229 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2230 | { | |
aba5e278 | 2231 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2232 | engine->submit_request = gen6_bsd_submit_request; |
2233 | } | |
2234 | ||
06a2fe22 TU |
2235 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2236 | struct intel_engine_cs *engine) | |
2237 | { | |
79e6770c CW |
2238 | /* gen8+ are only supported with execlists */ |
2239 | GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); | |
2240 | ||
618e4ca7 | 2241 | intel_ring_init_irq(dev_priv, engine); |
618e4ca7 | 2242 | |
1d8a1337 | 2243 | engine->init_hw = init_ring_common; |
5adfb772 CW |
2244 | engine->reset.prepare = reset_prepare; |
2245 | engine->reset.reset = reset_ring; | |
2246 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2247 | |
4dc84b77 | 2248 | engine->cops = &ring_context_ops; |
f73e7399 CW |
2249 | engine->request_alloc = ring_request_alloc; |
2250 | ||
85474441 CW |
2251 | /* |
2252 | * Using a global execution timeline; the previous final breadcrumb is | |
2253 | * equivalent to our next initial bread so we can elide | |
2254 | * engine->emit_init_breadcrumb(). | |
2255 | */ | |
2256 | engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; | |
9fa4973e | 2257 | if (IS_GEN(dev_priv, 5)) |
85474441 | 2258 | engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; |
ff44ad51 CW |
2259 | |
2260 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2261 | |
79e6770c | 2262 | if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2263 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2264 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2265 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2266 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2267 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2268 | else |
803688ba | 2269 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2270 | } |
2271 | ||
8b3e2d36 | 2272 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2273 | { |
8b3e2d36 | 2274 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2275 | int ret; |
5c1143bb | 2276 | |
06a2fe22 TU |
2277 | intel_ring_default_vfuncs(dev_priv, engine); |
2278 | ||
61ff75ac CW |
2279 | if (HAS_L3_DPF(dev_priv)) |
2280 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2281 | |
fa6f071d DCS |
2282 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2283 | ||
caa5915b | 2284 | if (INTEL_GEN(dev_priv) >= 7) { |
e2f80391 | 2285 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2286 | engine->emit_flush = gen7_render_ring_flush; |
85474441 | 2287 | engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; |
caa5915b CW |
2288 | } else if (IS_GEN(dev_priv, 6)) { |
2289 | engine->init_context = intel_rcs_ctx_init; | |
2290 | engine->emit_flush = gen6_render_ring_flush; | |
85474441 | 2291 | engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; |
cf819eff | 2292 | } else if (IS_GEN(dev_priv, 5)) { |
c7fe7d25 | 2293 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2294 | } else { |
c033666a | 2295 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2296 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2297 | else |
c7fe7d25 | 2298 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2299 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2300 | } |
707d9cf9 | 2301 | |
c033666a | 2302 | if (IS_HASWELL(dev_priv)) |
803688ba | 2303 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2304 | |
e2f80391 | 2305 | engine->init_hw = init_render_ring; |
59465b5f | 2306 | |
acd27845 | 2307 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2308 | if (ret) |
2309 | return ret; | |
2310 | ||
99be1dfe | 2311 | return 0; |
5c1143bb XH |
2312 | } |
2313 | ||
8b3e2d36 | 2314 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2315 | { |
8b3e2d36 | 2316 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2317 | |
06a2fe22 TU |
2318 | intel_ring_default_vfuncs(dev_priv, engine); |
2319 | ||
c033666a | 2320 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2321 | /* gen6 bsd needs a special wa for tail updates */ |
cf819eff | 2322 | if (IS_GEN(dev_priv, 6)) |
ff44ad51 | 2323 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2324 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2325 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
caa5915b | 2326 | |
9fa4973e | 2327 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2328 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2329 | else |
85474441 | 2330 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
58fa3835 | 2331 | } else { |
c7fe7d25 | 2332 | engine->emit_flush = bsd_ring_flush; |
cf819eff | 2333 | if (IS_GEN(dev_priv, 5)) |
e2f80391 | 2334 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2335 | else |
e2f80391 | 2336 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2337 | } |
58fa3835 | 2338 | |
acd27845 | 2339 | return intel_init_ring_buffer(engine); |
5c1143bb | 2340 | } |
549f7365 | 2341 | |
8b3e2d36 | 2342 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2343 | { |
8b3e2d36 | 2344 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2345 | |
caa5915b CW |
2346 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); |
2347 | ||
06a2fe22 TU |
2348 | intel_ring_default_vfuncs(dev_priv, engine); |
2349 | ||
c7fe7d25 | 2350 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2351 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2352 | |
9fa4973e | 2353 | if (IS_GEN(dev_priv, 6)) |
85474441 | 2354 | engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; |
9fa4973e | 2355 | else |
85474441 | 2356 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2357 | |
acd27845 | 2358 | return intel_init_ring_buffer(engine); |
549f7365 | 2359 | } |
a7b9761d | 2360 | |
8b3e2d36 | 2361 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2362 | { |
8b3e2d36 | 2363 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 | 2364 | |
caa5915b CW |
2365 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 7); |
2366 | ||
06a2fe22 TU |
2367 | intel_ring_default_vfuncs(dev_priv, engine); |
2368 | ||
c7fe7d25 | 2369 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2370 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2371 | engine->irq_enable = hsw_vebox_irq_enable; | |
2372 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2373 | |
85474441 | 2374 | engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; |
caa5915b | 2375 | |
acd27845 | 2376 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2377 | } |