]>
Commit | Line | Data |
---|---|---|
62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
18393f63 CW |
36 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
37 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
38 | * to give some inclination as to some of the magic values used in the various | |
39 | * workarounds! | |
40 | */ | |
41 | #define CACHELINE_BYTES 64 | |
42 | ||
1cf0ba14 | 43 | static inline int __ring_space(int head, int tail, int size) |
c7dca47b | 44 | { |
1cf0ba14 | 45 | int space = head - (tail + I915_RING_FREE_SPACE); |
c7dca47b | 46 | if (space < 0) |
1cf0ba14 | 47 | space += size; |
c7dca47b CW |
48 | return space; |
49 | } | |
50 | ||
a4872ba6 | 51 | static inline int ring_space(struct intel_engine_cs *ring) |
1cf0ba14 | 52 | { |
93b0a4e0 OM |
53 | struct intel_ringbuffer *ringbuf = ring->buffer; |
54 | return __ring_space(ringbuf->head & HEAD_ADDR, ringbuf->tail, ringbuf->size); | |
1cf0ba14 CW |
55 | } |
56 | ||
a4872ba6 | 57 | static bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
58 | { |
59 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
60 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
61 | } | |
09246732 | 62 | |
a4872ba6 | 63 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 64 | { |
93b0a4e0 OM |
65 | struct intel_ringbuffer *ringbuf = ring->buffer; |
66 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 67 | if (intel_ring_stopped(ring)) |
09246732 | 68 | return; |
93b0a4e0 | 69 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
70 | } |
71 | ||
b72f3acb | 72 | static int |
a4872ba6 | 73 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
74 | u32 invalidate_domains, |
75 | u32 flush_domains) | |
76 | { | |
77 | u32 cmd; | |
78 | int ret; | |
79 | ||
80 | cmd = MI_FLUSH; | |
31b14c9f | 81 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
82 | cmd |= MI_NO_WRITE_FLUSH; |
83 | ||
84 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
85 | cmd |= MI_READ_FLUSH; | |
86 | ||
87 | ret = intel_ring_begin(ring, 2); | |
88 | if (ret) | |
89 | return ret; | |
90 | ||
91 | intel_ring_emit(ring, cmd); | |
92 | intel_ring_emit(ring, MI_NOOP); | |
93 | intel_ring_advance(ring); | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static int | |
a4872ba6 | 99 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
100 | u32 invalidate_domains, |
101 | u32 flush_domains) | |
62fdfeaf | 102 | { |
78501eac | 103 | struct drm_device *dev = ring->dev; |
6f392d54 | 104 | u32 cmd; |
b72f3acb | 105 | int ret; |
6f392d54 | 106 | |
36d527de CW |
107 | /* |
108 | * read/write caches: | |
109 | * | |
110 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
111 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
112 | * also flushed at 2d versus 3d pipeline switches. | |
113 | * | |
114 | * read-only caches: | |
115 | * | |
116 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
117 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
118 | * | |
119 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
120 | * | |
121 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
122 | * invalidated when MI_EXE_FLUSH is set. | |
123 | * | |
124 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
125 | * invalidated with every MI_FLUSH. | |
126 | * | |
127 | * TLBs: | |
128 | * | |
129 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
130 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
131 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
132 | * are flushed at any MI_FLUSH. | |
133 | */ | |
134 | ||
135 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 136 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 137 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
138 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
139 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 140 | |
36d527de CW |
141 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
142 | (IS_G4X(dev) || IS_GEN5(dev))) | |
143 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 144 | |
36d527de CW |
145 | ret = intel_ring_begin(ring, 2); |
146 | if (ret) | |
147 | return ret; | |
b72f3acb | 148 | |
36d527de CW |
149 | intel_ring_emit(ring, cmd); |
150 | intel_ring_emit(ring, MI_NOOP); | |
151 | intel_ring_advance(ring); | |
b72f3acb CW |
152 | |
153 | return 0; | |
8187a2b7 ZN |
154 | } |
155 | ||
8d315287 JB |
156 | /** |
157 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
158 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
159 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
160 | * | |
161 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
162 | * produced by non-pipelined state commands), software needs to first | |
163 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
164 | * 0. | |
165 | * | |
166 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
167 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
168 | * | |
169 | * And the workaround for these two requires this workaround first: | |
170 | * | |
171 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
172 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
173 | * flushes. | |
174 | * | |
175 | * And this last workaround is tricky because of the requirements on | |
176 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
177 | * volume 2 part 1: | |
178 | * | |
179 | * "1 of the following must also be set: | |
180 | * - Render Target Cache Flush Enable ([12] of DW1) | |
181 | * - Depth Cache Flush Enable ([0] of DW1) | |
182 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
183 | * - Depth Stall ([13] of DW1) | |
184 | * - Post-Sync Operation ([13] of DW1) | |
185 | * - Notify Enable ([8] of DW1)" | |
186 | * | |
187 | * The cache flushes require the workaround flush that triggered this | |
188 | * one, so we can't use it. Depth stall would trigger the same. | |
189 | * Post-sync nonzero is what triggered this second workaround, so we | |
190 | * can't use that one either. Notify enable is IRQs, which aren't | |
191 | * really our business. That leaves only stall at scoreboard. | |
192 | */ | |
193 | static int | |
a4872ba6 | 194 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 195 | { |
18393f63 | 196 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
197 | int ret; |
198 | ||
199 | ||
200 | ret = intel_ring_begin(ring, 6); | |
201 | if (ret) | |
202 | return ret; | |
203 | ||
204 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
205 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
206 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
207 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
208 | intel_ring_emit(ring, 0); /* low dword */ | |
209 | intel_ring_emit(ring, 0); /* high dword */ | |
210 | intel_ring_emit(ring, MI_NOOP); | |
211 | intel_ring_advance(ring); | |
212 | ||
213 | ret = intel_ring_begin(ring, 6); | |
214 | if (ret) | |
215 | return ret; | |
216 | ||
217 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
218 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
219 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
220 | intel_ring_emit(ring, 0); | |
221 | intel_ring_emit(ring, 0); | |
222 | intel_ring_emit(ring, MI_NOOP); | |
223 | intel_ring_advance(ring); | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static int | |
a4872ba6 | 229 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
230 | u32 invalidate_domains, u32 flush_domains) |
231 | { | |
232 | u32 flags = 0; | |
18393f63 | 233 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
234 | int ret; |
235 | ||
b3111509 PZ |
236 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
237 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
238 | if (ret) | |
239 | return ret; | |
240 | ||
8d315287 JB |
241 | /* Just flush everything. Experiments have shown that reducing the |
242 | * number of bits based on the write domains has little performance | |
243 | * impact. | |
244 | */ | |
7d54a904 CW |
245 | if (flush_domains) { |
246 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
247 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
248 | /* | |
249 | * Ensure that any following seqno writes only happen | |
250 | * when the render cache is indeed flushed. | |
251 | */ | |
97f209bc | 252 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
253 | } |
254 | if (invalidate_domains) { | |
255 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
256 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
257 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
258 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
259 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
260 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
261 | /* | |
262 | * TLB invalidate requires a post-sync write. | |
263 | */ | |
3ac78313 | 264 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 265 | } |
8d315287 | 266 | |
6c6cf5aa | 267 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
268 | if (ret) |
269 | return ret; | |
270 | ||
6c6cf5aa | 271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
272 | intel_ring_emit(ring, flags); |
273 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 274 | intel_ring_emit(ring, 0); |
8d315287 JB |
275 | intel_ring_advance(ring); |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
f3987631 | 280 | static int |
a4872ba6 | 281 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
282 | { |
283 | int ret; | |
284 | ||
285 | ret = intel_ring_begin(ring, 4); | |
286 | if (ret) | |
287 | return ret; | |
288 | ||
289 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
290 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
291 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
292 | intel_ring_emit(ring, 0); | |
293 | intel_ring_emit(ring, 0); | |
294 | intel_ring_advance(ring); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
a4872ba6 | 299 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
300 | { |
301 | int ret; | |
302 | ||
303 | if (!ring->fbc_dirty) | |
304 | return 0; | |
305 | ||
37c1d94f | 306 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
307 | if (ret) |
308 | return ret; | |
fd3da6c9 RV |
309 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
310 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
311 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
312 | intel_ring_emit(ring, value); | |
37c1d94f VS |
313 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
314 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
315 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
316 | intel_ring_advance(ring); |
317 | ||
318 | ring->fbc_dirty = false; | |
319 | return 0; | |
320 | } | |
321 | ||
4772eaeb | 322 | static int |
a4872ba6 | 323 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
324 | u32 invalidate_domains, u32 flush_domains) |
325 | { | |
326 | u32 flags = 0; | |
18393f63 | 327 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
328 | int ret; |
329 | ||
f3987631 PZ |
330 | /* |
331 | * Ensure that any following seqno writes only happen when the render | |
332 | * cache is indeed flushed. | |
333 | * | |
334 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
335 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
336 | * don't try to be clever and just set it unconditionally. | |
337 | */ | |
338 | flags |= PIPE_CONTROL_CS_STALL; | |
339 | ||
4772eaeb PZ |
340 | /* Just flush everything. Experiments have shown that reducing the |
341 | * number of bits based on the write domains has little performance | |
342 | * impact. | |
343 | */ | |
344 | if (flush_domains) { | |
345 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
346 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
347 | } |
348 | if (invalidate_domains) { | |
349 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
350 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
351 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
352 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
353 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
354 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
355 | /* | |
356 | * TLB invalidate requires a post-sync write. | |
357 | */ | |
358 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 359 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
360 | |
361 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
362 | * set before a pipe_control command that has the state cache | |
363 | * invalidate bit set. */ | |
364 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
365 | } |
366 | ||
367 | ret = intel_ring_begin(ring, 4); | |
368 | if (ret) | |
369 | return ret; | |
370 | ||
371 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
372 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 373 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
374 | intel_ring_emit(ring, 0); |
375 | intel_ring_advance(ring); | |
376 | ||
9688ecad | 377 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
378 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
379 | ||
4772eaeb PZ |
380 | return 0; |
381 | } | |
382 | ||
a5f3d68e | 383 | static int |
a4872ba6 | 384 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
385 | u32 invalidate_domains, u32 flush_domains) |
386 | { | |
387 | u32 flags = 0; | |
18393f63 | 388 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
a5f3d68e BW |
389 | int ret; |
390 | ||
391 | flags |= PIPE_CONTROL_CS_STALL; | |
392 | ||
393 | if (flush_domains) { | |
394 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
395 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
396 | } | |
397 | if (invalidate_domains) { | |
398 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
399 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
400 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
401 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
402 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
403 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
404 | flags |= PIPE_CONTROL_QW_WRITE; | |
405 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
406 | } | |
407 | ||
408 | ret = intel_ring_begin(ring, 6); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
412 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
413 | intel_ring_emit(ring, flags); | |
414 | intel_ring_emit(ring, scratch_addr); | |
415 | intel_ring_emit(ring, 0); | |
416 | intel_ring_emit(ring, 0); | |
417 | intel_ring_emit(ring, 0); | |
418 | intel_ring_advance(ring); | |
419 | ||
420 | return 0; | |
421 | ||
422 | } | |
423 | ||
a4872ba6 | 424 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 425 | u32 value) |
d46eefa2 | 426 | { |
4640c4ff | 427 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 428 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
429 | } |
430 | ||
a4872ba6 | 431 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 432 | { |
4640c4ff | 433 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 434 | u64 acthd; |
8187a2b7 | 435 | |
50877445 CW |
436 | if (INTEL_INFO(ring->dev)->gen >= 8) |
437 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
438 | RING_ACTHD_UDW(ring->mmio_base)); | |
439 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
440 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
441 | else | |
442 | acthd = I915_READ(ACTHD); | |
443 | ||
444 | return acthd; | |
8187a2b7 ZN |
445 | } |
446 | ||
a4872ba6 | 447 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
448 | { |
449 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
450 | u32 addr; | |
451 | ||
452 | addr = dev_priv->status_page_dmah->busaddr; | |
453 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
454 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
455 | I915_WRITE(HWS_PGA, addr); | |
456 | } | |
457 | ||
a4872ba6 | 458 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 459 | { |
9991ae78 | 460 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 461 | |
9991ae78 CW |
462 | if (!IS_GEN2(ring->dev)) { |
463 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
464 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
465 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
466 | return false; | |
467 | } | |
468 | } | |
b7884eb4 | 469 | |
7f2ab699 | 470 | I915_WRITE_CTL(ring, 0); |
570ef608 | 471 | I915_WRITE_HEAD(ring, 0); |
78501eac | 472 | ring->write_tail(ring, 0); |
8187a2b7 | 473 | |
9991ae78 CW |
474 | if (!IS_GEN2(ring->dev)) { |
475 | (void)I915_READ_CTL(ring); | |
476 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
477 | } | |
a51435a3 | 478 | |
9991ae78 CW |
479 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
480 | } | |
8187a2b7 | 481 | |
a4872ba6 | 482 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
483 | { |
484 | struct drm_device *dev = ring->dev; | |
485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
486 | struct intel_ringbuffer *ringbuf = ring->buffer; |
487 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
488 | int ret = 0; |
489 | ||
490 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
491 | ||
492 | if (!stop_ring(ring)) { | |
493 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
494 | DRM_DEBUG_KMS("%s head not reset to zero " |
495 | "ctl %08x head %08x tail %08x start %08x\n", | |
496 | ring->name, | |
497 | I915_READ_CTL(ring), | |
498 | I915_READ_HEAD(ring), | |
499 | I915_READ_TAIL(ring), | |
500 | I915_READ_START(ring)); | |
8187a2b7 | 501 | |
9991ae78 | 502 | if (!stop_ring(ring)) { |
6fd0d56e CW |
503 | DRM_ERROR("failed to set %s head to zero " |
504 | "ctl %08x head %08x tail %08x start %08x\n", | |
505 | ring->name, | |
506 | I915_READ_CTL(ring), | |
507 | I915_READ_HEAD(ring), | |
508 | I915_READ_TAIL(ring), | |
509 | I915_READ_START(ring)); | |
9991ae78 CW |
510 | ret = -EIO; |
511 | goto out; | |
6fd0d56e | 512 | } |
8187a2b7 ZN |
513 | } |
514 | ||
9991ae78 CW |
515 | if (I915_NEED_GFX_HWS(dev)) |
516 | intel_ring_setup_status_page(ring); | |
517 | else | |
518 | ring_setup_phys_status_page(ring); | |
519 | ||
0d8957c8 DV |
520 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
521 | * registers with the above sequence (the readback of the HEAD registers | |
522 | * also enforces ordering), otherwise the hw might lose the new ring | |
523 | * register values. */ | |
f343c5f6 | 524 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 525 | I915_WRITE_CTL(ring, |
93b0a4e0 | 526 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 527 | | RING_VALID); |
8187a2b7 | 528 | |
8187a2b7 | 529 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 530 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 531 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 532 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 533 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
534 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
535 | ring->name, | |
536 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
537 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
538 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
539 | ret = -EIO; |
540 | goto out; | |
8187a2b7 ZN |
541 | } |
542 | ||
78501eac CW |
543 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
544 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 545 | else { |
93b0a4e0 OM |
546 | ringbuf->head = I915_READ_HEAD(ring); |
547 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
548 | ringbuf->space = ring_space(ring); | |
549 | ringbuf->last_retired_head = -1; | |
8187a2b7 | 550 | } |
1ec14ad3 | 551 | |
50f018df CW |
552 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
553 | ||
b7884eb4 | 554 | out: |
c8d9a590 | 555 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
556 | |
557 | return ret; | |
8187a2b7 ZN |
558 | } |
559 | ||
c6df541c | 560 | static int |
a4872ba6 | 561 | init_pipe_control(struct intel_engine_cs *ring) |
c6df541c | 562 | { |
c6df541c CW |
563 | int ret; |
564 | ||
0d1aacac | 565 | if (ring->scratch.obj) |
c6df541c CW |
566 | return 0; |
567 | ||
0d1aacac CW |
568 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
569 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
570 | DRM_ERROR("Failed to allocate seqno page\n"); |
571 | ret = -ENOMEM; | |
572 | goto err; | |
573 | } | |
e4ffd173 | 574 | |
a9cc726c DV |
575 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
576 | if (ret) | |
577 | goto err_unref; | |
c6df541c | 578 | |
1ec9e26d | 579 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
580 | if (ret) |
581 | goto err_unref; | |
582 | ||
0d1aacac CW |
583 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
584 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
585 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 586 | ret = -ENOMEM; |
c6df541c | 587 | goto err_unpin; |
56b085a0 | 588 | } |
c6df541c | 589 | |
2b1086cc | 590 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 591 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
592 | return 0; |
593 | ||
594 | err_unpin: | |
d7f46fc4 | 595 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 596 | err_unref: |
0d1aacac | 597 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 598 | err: |
c6df541c CW |
599 | return ret; |
600 | } | |
601 | ||
a4872ba6 | 602 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 603 | { |
78501eac | 604 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 605 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 606 | int ret = init_ring_common(ring); |
a69ffdbf | 607 | |
61a563a2 AG |
608 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
609 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 610 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
611 | |
612 | /* We need to disable the AsyncFlip performance optimisations in order | |
613 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
614 | * programmed to '1' on all products. | |
8693a824 | 615 | * |
b3f797ac | 616 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 CW |
617 | */ |
618 | if (INTEL_INFO(dev)->gen >= 6) | |
619 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
620 | ||
f05bb0c7 | 621 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 622 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
623 | if (INTEL_INFO(dev)->gen == 6) |
624 | I915_WRITE(GFX_MODE, | |
aa83e30d | 625 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 626 | |
01fa0302 | 627 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
628 | if (IS_GEN7(dev)) |
629 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 630 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 631 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 632 | |
8d315287 | 633 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
634 | ret = init_pipe_control(ring); |
635 | if (ret) | |
636 | return ret; | |
637 | } | |
638 | ||
5e13a0c5 | 639 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
640 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
641 | * "If this bit is set, STCunit will have LRA as replacement | |
642 | * policy. [...] This bit must be reset. LRA replacement | |
643 | * policy is not supported." | |
644 | */ | |
645 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 646 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
647 | } |
648 | ||
6b26c86d DV |
649 | if (INTEL_INFO(dev)->gen >= 6) |
650 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 651 | |
040d2baa | 652 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 653 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 654 | |
8187a2b7 ZN |
655 | return ret; |
656 | } | |
657 | ||
a4872ba6 | 658 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 659 | { |
b45305fc DV |
660 | struct drm_device *dev = ring->dev; |
661 | ||
0d1aacac | 662 | if (ring->scratch.obj == NULL) |
c6df541c CW |
663 | return; |
664 | ||
0d1aacac CW |
665 | if (INTEL_INFO(dev)->gen >= 5) { |
666 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
d7f46fc4 | 667 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
0d1aacac | 668 | } |
aaf8a516 | 669 | |
0d1aacac CW |
670 | drm_gem_object_unreference(&ring->scratch.obj->base); |
671 | ring->scratch.obj = NULL; | |
c6df541c CW |
672 | } |
673 | ||
a4872ba6 | 674 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 675 | unsigned int num_dwords) |
1ec14ad3 | 676 | { |
024a43e1 BW |
677 | struct drm_device *dev = signaller->dev; |
678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 679 | struct intel_engine_cs *useless; |
024a43e1 | 680 | int i, ret; |
78325f2d | 681 | |
024a43e1 BW |
682 | /* NB: In order to be able to do semaphore MBOX updates for varying |
683 | * number of rings, it's easiest if we round up each individual update | |
684 | * to a multiple of 2 (since ring updates must always be a multiple of | |
685 | * 2) even though the actual update only requires 3 dwords. | |
686 | */ | |
ad776f8b | 687 | #define MBOX_UPDATE_DWORDS 4 |
024a43e1 BW |
688 | if (i915_semaphore_is_enabled(dev)) |
689 | num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS); | |
6e450ab2 MK |
690 | else |
691 | return intel_ring_begin(signaller, num_dwords); | |
024a43e1 BW |
692 | |
693 | ret = intel_ring_begin(signaller, num_dwords); | |
694 | if (ret) | |
695 | return ret; | |
696 | #undef MBOX_UPDATE_DWORDS | |
697 | ||
78325f2d BW |
698 | for_each_ring(useless, dev_priv, i) { |
699 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
700 | if (mbox_reg != GEN6_NOSYNC) { | |
701 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); | |
702 | intel_ring_emit(signaller, mbox_reg); | |
703 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
704 | intel_ring_emit(signaller, MI_NOOP); | |
705 | } else { | |
706 | intel_ring_emit(signaller, MI_NOOP); | |
707 | intel_ring_emit(signaller, MI_NOOP); | |
708 | intel_ring_emit(signaller, MI_NOOP); | |
709 | intel_ring_emit(signaller, MI_NOOP); | |
710 | } | |
711 | } | |
024a43e1 BW |
712 | |
713 | return 0; | |
1ec14ad3 CW |
714 | } |
715 | ||
c8c99b0f BW |
716 | /** |
717 | * gen6_add_request - Update the semaphore mailbox registers | |
718 | * | |
719 | * @ring - ring that is adding a request | |
720 | * @seqno - return seqno stuck into the ring | |
721 | * | |
722 | * Update the mailbox registers in the *other* rings with the current seqno. | |
723 | * This acts like a signal in the canonical semaphore. | |
724 | */ | |
1ec14ad3 | 725 | static int |
a4872ba6 | 726 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 727 | { |
024a43e1 | 728 | int ret; |
52ed2325 | 729 | |
024a43e1 | 730 | ret = ring->semaphore.signal(ring, 4); |
1ec14ad3 CW |
731 | if (ret) |
732 | return ret; | |
733 | ||
1ec14ad3 CW |
734 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
735 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 736 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 737 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 738 | __intel_ring_advance(ring); |
1ec14ad3 | 739 | |
1ec14ad3 CW |
740 | return 0; |
741 | } | |
742 | ||
f72b3435 MK |
743 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
744 | u32 seqno) | |
745 | { | |
746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
747 | return dev_priv->last_seqno < seqno; | |
748 | } | |
749 | ||
c8c99b0f BW |
750 | /** |
751 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
752 | * | |
753 | * @waiter - ring that is waiting | |
754 | * @signaller - ring which has, or will signal | |
755 | * @seqno - seqno which the waiter will block on | |
756 | */ | |
757 | static int | |
a4872ba6 OM |
758 | gen6_ring_sync(struct intel_engine_cs *waiter, |
759 | struct intel_engine_cs *signaller, | |
686cb5f9 | 760 | u32 seqno) |
1ec14ad3 | 761 | { |
c8c99b0f BW |
762 | u32 dw1 = MI_SEMAPHORE_MBOX | |
763 | MI_SEMAPHORE_COMPARE | | |
764 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
765 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
766 | int ret; | |
1ec14ad3 | 767 | |
1500f7ea BW |
768 | /* Throughout all of the GEM code, seqno passed implies our current |
769 | * seqno is >= the last seqno executed. However for hardware the | |
770 | * comparison is strictly greater than. | |
771 | */ | |
772 | seqno -= 1; | |
773 | ||
ebc348b2 | 774 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 775 | |
c8c99b0f | 776 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
777 | if (ret) |
778 | return ret; | |
779 | ||
f72b3435 MK |
780 | /* If seqno wrap happened, omit the wait with no-ops */ |
781 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 782 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
783 | intel_ring_emit(waiter, seqno); |
784 | intel_ring_emit(waiter, 0); | |
785 | intel_ring_emit(waiter, MI_NOOP); | |
786 | } else { | |
787 | intel_ring_emit(waiter, MI_NOOP); | |
788 | intel_ring_emit(waiter, MI_NOOP); | |
789 | intel_ring_emit(waiter, MI_NOOP); | |
790 | intel_ring_emit(waiter, MI_NOOP); | |
791 | } | |
c8c99b0f | 792 | intel_ring_advance(waiter); |
1ec14ad3 CW |
793 | |
794 | return 0; | |
795 | } | |
796 | ||
c6df541c CW |
797 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
798 | do { \ | |
fcbc34e4 KG |
799 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
800 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
801 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
802 | intel_ring_emit(ring__, 0); \ | |
803 | intel_ring_emit(ring__, 0); \ | |
804 | } while (0) | |
805 | ||
806 | static int | |
a4872ba6 | 807 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 808 | { |
18393f63 | 809 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
810 | int ret; |
811 | ||
812 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
813 | * incoherent with writes to memory, i.e. completely fubar, | |
814 | * so we need to use PIPE_NOTIFY instead. | |
815 | * | |
816 | * However, we also need to workaround the qword write | |
817 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
818 | * memory before requesting an interrupt. | |
819 | */ | |
820 | ret = intel_ring_begin(ring, 32); | |
821 | if (ret) | |
822 | return ret; | |
823 | ||
fcbc34e4 | 824 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
825 | PIPE_CONTROL_WRITE_FLUSH | |
826 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 827 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 828 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
829 | intel_ring_emit(ring, 0); |
830 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 831 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 832 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 833 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 834 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 835 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 836 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 837 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 838 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 839 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 840 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 841 | |
fcbc34e4 | 842 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
843 | PIPE_CONTROL_WRITE_FLUSH | |
844 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 845 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 846 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 847 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 848 | intel_ring_emit(ring, 0); |
09246732 | 849 | __intel_ring_advance(ring); |
c6df541c | 850 | |
c6df541c CW |
851 | return 0; |
852 | } | |
853 | ||
4cd53c0c | 854 | static u32 |
a4872ba6 | 855 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 856 | { |
4cd53c0c DV |
857 | /* Workaround to force correct ordering between irq and seqno writes on |
858 | * ivb (and maybe also on snb) by reading from a CS register (like | |
859 | * ACTHD) before reading the status page. */ | |
50877445 CW |
860 | if (!lazy_coherency) { |
861 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
862 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
863 | } | |
864 | ||
4cd53c0c DV |
865 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
866 | } | |
867 | ||
8187a2b7 | 868 | static u32 |
a4872ba6 | 869 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 870 | { |
1ec14ad3 CW |
871 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
872 | } | |
873 | ||
b70ec5bf | 874 | static void |
a4872ba6 | 875 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
876 | { |
877 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
878 | } | |
879 | ||
c6df541c | 880 | static u32 |
a4872ba6 | 881 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 882 | { |
0d1aacac | 883 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
884 | } |
885 | ||
b70ec5bf | 886 | static void |
a4872ba6 | 887 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 888 | { |
0d1aacac | 889 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
890 | } |
891 | ||
e48d8634 | 892 | static bool |
a4872ba6 | 893 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
894 | { |
895 | struct drm_device *dev = ring->dev; | |
4640c4ff | 896 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 897 | unsigned long flags; |
e48d8634 DV |
898 | |
899 | if (!dev->irq_enabled) | |
900 | return false; | |
901 | ||
7338aefa | 902 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
903 | if (ring->irq_refcount++ == 0) |
904 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 905 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
906 | |
907 | return true; | |
908 | } | |
909 | ||
910 | static void | |
a4872ba6 | 911 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
912 | { |
913 | struct drm_device *dev = ring->dev; | |
4640c4ff | 914 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 915 | unsigned long flags; |
e48d8634 | 916 | |
7338aefa | 917 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
918 | if (--ring->irq_refcount == 0) |
919 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 920 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
921 | } |
922 | ||
b13c2b96 | 923 | static bool |
a4872ba6 | 924 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 925 | { |
78501eac | 926 | struct drm_device *dev = ring->dev; |
4640c4ff | 927 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 928 | unsigned long flags; |
62fdfeaf | 929 | |
b13c2b96 CW |
930 | if (!dev->irq_enabled) |
931 | return false; | |
932 | ||
7338aefa | 933 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 934 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
935 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
936 | I915_WRITE(IMR, dev_priv->irq_mask); | |
937 | POSTING_READ(IMR); | |
938 | } | |
7338aefa | 939 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
940 | |
941 | return true; | |
62fdfeaf EA |
942 | } |
943 | ||
8187a2b7 | 944 | static void |
a4872ba6 | 945 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 946 | { |
78501eac | 947 | struct drm_device *dev = ring->dev; |
4640c4ff | 948 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 949 | unsigned long flags; |
62fdfeaf | 950 | |
7338aefa | 951 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 952 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
953 | dev_priv->irq_mask |= ring->irq_enable_mask; |
954 | I915_WRITE(IMR, dev_priv->irq_mask); | |
955 | POSTING_READ(IMR); | |
956 | } | |
7338aefa | 957 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
958 | } |
959 | ||
c2798b19 | 960 | static bool |
a4872ba6 | 961 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
962 | { |
963 | struct drm_device *dev = ring->dev; | |
4640c4ff | 964 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 965 | unsigned long flags; |
c2798b19 CW |
966 | |
967 | if (!dev->irq_enabled) | |
968 | return false; | |
969 | ||
7338aefa | 970 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 971 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
972 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
973 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
974 | POSTING_READ16(IMR); | |
975 | } | |
7338aefa | 976 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
977 | |
978 | return true; | |
979 | } | |
980 | ||
981 | static void | |
a4872ba6 | 982 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
983 | { |
984 | struct drm_device *dev = ring->dev; | |
4640c4ff | 985 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 986 | unsigned long flags; |
c2798b19 | 987 | |
7338aefa | 988 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 989 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
990 | dev_priv->irq_mask |= ring->irq_enable_mask; |
991 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
992 | POSTING_READ16(IMR); | |
993 | } | |
7338aefa | 994 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
995 | } |
996 | ||
a4872ba6 | 997 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 998 | { |
4593010b | 999 | struct drm_device *dev = ring->dev; |
4640c4ff | 1000 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1001 | u32 mmio = 0; |
1002 | ||
1003 | /* The ring status page addresses are no longer next to the rest of | |
1004 | * the ring registers as of gen7. | |
1005 | */ | |
1006 | if (IS_GEN7(dev)) { | |
1007 | switch (ring->id) { | |
96154f2f | 1008 | case RCS: |
4593010b EA |
1009 | mmio = RENDER_HWS_PGA_GEN7; |
1010 | break; | |
96154f2f | 1011 | case BCS: |
4593010b EA |
1012 | mmio = BLT_HWS_PGA_GEN7; |
1013 | break; | |
77fe2ff3 ZY |
1014 | /* |
1015 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1016 | * gcc switch check warning | |
1017 | */ | |
1018 | case VCS2: | |
96154f2f | 1019 | case VCS: |
4593010b EA |
1020 | mmio = BSD_HWS_PGA_GEN7; |
1021 | break; | |
4a3dd19d | 1022 | case VECS: |
9a8a2213 BW |
1023 | mmio = VEBOX_HWS_PGA_GEN7; |
1024 | break; | |
4593010b EA |
1025 | } |
1026 | } else if (IS_GEN6(ring->dev)) { | |
1027 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1028 | } else { | |
eb0d4b75 | 1029 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1030 | mmio = RING_HWS_PGA(ring->mmio_base); |
1031 | } | |
1032 | ||
78501eac CW |
1033 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1034 | POSTING_READ(mmio); | |
884020bf | 1035 | |
dc616b89 DL |
1036 | /* |
1037 | * Flush the TLB for this page | |
1038 | * | |
1039 | * FIXME: These two bits have disappeared on gen8, so a question | |
1040 | * arises: do we still need this and if so how should we go about | |
1041 | * invalidating the TLB? | |
1042 | */ | |
1043 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1044 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1045 | |
1046 | /* ring should be idle before issuing a sync flush*/ | |
1047 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1048 | ||
884020bf CW |
1049 | I915_WRITE(reg, |
1050 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1051 | INSTPM_SYNC_FLUSH)); | |
1052 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1053 | 1000)) | |
1054 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1055 | ring->name); | |
1056 | } | |
8187a2b7 ZN |
1057 | } |
1058 | ||
b72f3acb | 1059 | static int |
a4872ba6 | 1060 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1061 | u32 invalidate_domains, |
1062 | u32 flush_domains) | |
d1b851fc | 1063 | { |
b72f3acb CW |
1064 | int ret; |
1065 | ||
b72f3acb CW |
1066 | ret = intel_ring_begin(ring, 2); |
1067 | if (ret) | |
1068 | return ret; | |
1069 | ||
1070 | intel_ring_emit(ring, MI_FLUSH); | |
1071 | intel_ring_emit(ring, MI_NOOP); | |
1072 | intel_ring_advance(ring); | |
1073 | return 0; | |
d1b851fc ZN |
1074 | } |
1075 | ||
3cce469c | 1076 | static int |
a4872ba6 | 1077 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1078 | { |
3cce469c CW |
1079 | int ret; |
1080 | ||
1081 | ret = intel_ring_begin(ring, 4); | |
1082 | if (ret) | |
1083 | return ret; | |
6f392d54 | 1084 | |
3cce469c CW |
1085 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1086 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1087 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1088 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1089 | __intel_ring_advance(ring); |
d1b851fc | 1090 | |
3cce469c | 1091 | return 0; |
d1b851fc ZN |
1092 | } |
1093 | ||
0f46832f | 1094 | static bool |
a4872ba6 | 1095 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1096 | { |
1097 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1098 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1099 | unsigned long flags; |
0f46832f CW |
1100 | |
1101 | if (!dev->irq_enabled) | |
1102 | return false; | |
1103 | ||
7338aefa | 1104 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1105 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1106 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1107 | I915_WRITE_IMR(ring, |
1108 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1109 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1110 | else |
1111 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1112 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1113 | } |
7338aefa | 1114 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1115 | |
1116 | return true; | |
1117 | } | |
1118 | ||
1119 | static void | |
a4872ba6 | 1120 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1121 | { |
1122 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1123 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1124 | unsigned long flags; |
0f46832f | 1125 | |
7338aefa | 1126 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1127 | if (--ring->irq_refcount == 0) { |
040d2baa | 1128 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1129 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1130 | else |
1131 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1132 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1133 | } |
7338aefa | 1134 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1135 | } |
1136 | ||
a19d2933 | 1137 | static bool |
a4872ba6 | 1138 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1139 | { |
1140 | struct drm_device *dev = ring->dev; | |
1141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1142 | unsigned long flags; | |
1143 | ||
1144 | if (!dev->irq_enabled) | |
1145 | return false; | |
1146 | ||
59cdb63d | 1147 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1148 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1149 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1150 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1151 | } |
59cdb63d | 1152 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1153 | |
1154 | return true; | |
1155 | } | |
1156 | ||
1157 | static void | |
a4872ba6 | 1158 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1159 | { |
1160 | struct drm_device *dev = ring->dev; | |
1161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1162 | unsigned long flags; | |
1163 | ||
1164 | if (!dev->irq_enabled) | |
1165 | return; | |
1166 | ||
59cdb63d | 1167 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1168 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1169 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1170 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1171 | } |
59cdb63d | 1172 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1173 | } |
1174 | ||
abd58f01 | 1175 | static bool |
a4872ba6 | 1176 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1177 | { |
1178 | struct drm_device *dev = ring->dev; | |
1179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1180 | unsigned long flags; | |
1181 | ||
1182 | if (!dev->irq_enabled) | |
1183 | return false; | |
1184 | ||
1185 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1186 | if (ring->irq_refcount++ == 0) { | |
1187 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1188 | I915_WRITE_IMR(ring, | |
1189 | ~(ring->irq_enable_mask | | |
1190 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1191 | } else { | |
1192 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1193 | } | |
1194 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1195 | } | |
1196 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1197 | ||
1198 | return true; | |
1199 | } | |
1200 | ||
1201 | static void | |
a4872ba6 | 1202 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1203 | { |
1204 | struct drm_device *dev = ring->dev; | |
1205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1206 | unsigned long flags; | |
1207 | ||
1208 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1209 | if (--ring->irq_refcount == 0) { | |
1210 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1211 | I915_WRITE_IMR(ring, | |
1212 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1213 | } else { | |
1214 | I915_WRITE_IMR(ring, ~0); | |
1215 | } | |
1216 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1217 | } | |
1218 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1219 | } | |
1220 | ||
d1b851fc | 1221 | static int |
a4872ba6 | 1222 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1223 | u64 offset, u32 length, |
d7d4eedd | 1224 | unsigned flags) |
d1b851fc | 1225 | { |
e1f99ce6 | 1226 | int ret; |
78501eac | 1227 | |
e1f99ce6 CW |
1228 | ret = intel_ring_begin(ring, 2); |
1229 | if (ret) | |
1230 | return ret; | |
1231 | ||
78501eac | 1232 | intel_ring_emit(ring, |
65f56876 CW |
1233 | MI_BATCH_BUFFER_START | |
1234 | MI_BATCH_GTT | | |
d7d4eedd | 1235 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1236 | intel_ring_emit(ring, offset); |
78501eac CW |
1237 | intel_ring_advance(ring); |
1238 | ||
d1b851fc ZN |
1239 | return 0; |
1240 | } | |
1241 | ||
b45305fc DV |
1242 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1243 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1244 | static int |
a4872ba6 | 1245 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1246 | u64 offset, u32 len, |
d7d4eedd | 1247 | unsigned flags) |
62fdfeaf | 1248 | { |
c4e7a414 | 1249 | int ret; |
62fdfeaf | 1250 | |
b45305fc DV |
1251 | if (flags & I915_DISPATCH_PINNED) { |
1252 | ret = intel_ring_begin(ring, 4); | |
1253 | if (ret) | |
1254 | return ret; | |
62fdfeaf | 1255 | |
b45305fc DV |
1256 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1257 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1258 | intel_ring_emit(ring, offset + len - 8); | |
1259 | intel_ring_emit(ring, MI_NOOP); | |
1260 | intel_ring_advance(ring); | |
1261 | } else { | |
0d1aacac | 1262 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1263 | |
1264 | if (len > I830_BATCH_LIMIT) | |
1265 | return -ENOSPC; | |
1266 | ||
1267 | ret = intel_ring_begin(ring, 9+3); | |
1268 | if (ret) | |
1269 | return ret; | |
1270 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1271 | * scratch bo area (so that the CS never stumbles over its tlb | |
1272 | * invalidation bug) ... */ | |
1273 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1274 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1275 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1276 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1277 | intel_ring_emit(ring, 0); | |
1278 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1279 | intel_ring_emit(ring, cs_offset); | |
1280 | intel_ring_emit(ring, 0); | |
1281 | intel_ring_emit(ring, 4096); | |
1282 | intel_ring_emit(ring, offset); | |
1283 | intel_ring_emit(ring, MI_FLUSH); | |
1284 | ||
1285 | /* ... and execute it. */ | |
1286 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1287 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1288 | intel_ring_emit(ring, cs_offset + len - 8); | |
1289 | intel_ring_advance(ring); | |
1290 | } | |
e1f99ce6 | 1291 | |
fb3256da DV |
1292 | return 0; |
1293 | } | |
1294 | ||
1295 | static int | |
a4872ba6 | 1296 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1297 | u64 offset, u32 len, |
d7d4eedd | 1298 | unsigned flags) |
fb3256da DV |
1299 | { |
1300 | int ret; | |
1301 | ||
1302 | ret = intel_ring_begin(ring, 2); | |
1303 | if (ret) | |
1304 | return ret; | |
1305 | ||
65f56876 | 1306 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1307 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1308 | intel_ring_advance(ring); |
62fdfeaf | 1309 | |
62fdfeaf EA |
1310 | return 0; |
1311 | } | |
1312 | ||
a4872ba6 | 1313 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1314 | { |
05394f39 | 1315 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1316 | |
8187a2b7 ZN |
1317 | obj = ring->status_page.obj; |
1318 | if (obj == NULL) | |
62fdfeaf | 1319 | return; |
62fdfeaf | 1320 | |
9da3da66 | 1321 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1322 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1323 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1324 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1325 | } |
1326 | ||
a4872ba6 | 1327 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1328 | { |
05394f39 | 1329 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1330 | |
e3efda49 CW |
1331 | if ((obj = ring->status_page.obj) == NULL) { |
1332 | int ret; | |
e4ffd173 | 1333 | |
e3efda49 CW |
1334 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1335 | if (obj == NULL) { | |
1336 | DRM_ERROR("Failed to allocate status page\n"); | |
1337 | return -ENOMEM; | |
1338 | } | |
62fdfeaf | 1339 | |
e3efda49 CW |
1340 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1341 | if (ret) | |
1342 | goto err_unref; | |
1343 | ||
1344 | ret = i915_gem_obj_ggtt_pin(obj, 4096, 0); | |
1345 | if (ret) { | |
1346 | err_unref: | |
1347 | drm_gem_object_unreference(&obj->base); | |
1348 | return ret; | |
1349 | } | |
1350 | ||
1351 | ring->status_page.obj = obj; | |
1352 | } | |
62fdfeaf | 1353 | |
f343c5f6 | 1354 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1355 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1356 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1357 | |
8187a2b7 ZN |
1358 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1359 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1360 | |
1361 | return 0; | |
62fdfeaf EA |
1362 | } |
1363 | ||
a4872ba6 | 1364 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1365 | { |
1366 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1367 | |
1368 | if (!dev_priv->status_page_dmah) { | |
1369 | dev_priv->status_page_dmah = | |
1370 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1371 | if (!dev_priv->status_page_dmah) | |
1372 | return -ENOMEM; | |
1373 | } | |
1374 | ||
6b8294a4 CW |
1375 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1376 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
a4872ba6 | 1381 | static int allocate_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1382 | { |
e3efda49 CW |
1383 | struct drm_device *dev = ring->dev; |
1384 | struct drm_i915_private *dev_priv = to_i915(dev); | |
93b0a4e0 | 1385 | struct intel_ringbuffer *ringbuf = ring->buffer; |
05394f39 | 1386 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
1387 | int ret; |
1388 | ||
93b0a4e0 | 1389 | if (intel_ring_initialized(ring)) |
e3efda49 | 1390 | return 0; |
62fdfeaf | 1391 | |
ebc052e0 CW |
1392 | obj = NULL; |
1393 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1394 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1395 | if (obj == NULL) |
93b0a4e0 | 1396 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1397 | if (obj == NULL) |
1398 | return -ENOMEM; | |
8187a2b7 | 1399 | |
1ec9e26d | 1400 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1401 | if (ret) |
1402 | goto err_unref; | |
62fdfeaf | 1403 | |
3eef8918 CW |
1404 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1405 | if (ret) | |
1406 | goto err_unpin; | |
1407 | ||
93b0a4e0 | 1408 | ringbuf->virtual_start = |
f343c5f6 | 1409 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
93b0a4e0 OM |
1410 | ringbuf->size); |
1411 | if (ringbuf->virtual_start == NULL) { | |
8187a2b7 | 1412 | ret = -EINVAL; |
dd785e35 | 1413 | goto err_unpin; |
62fdfeaf EA |
1414 | } |
1415 | ||
93b0a4e0 | 1416 | ringbuf->obj = obj; |
e3efda49 CW |
1417 | return 0; |
1418 | ||
1419 | err_unpin: | |
1420 | i915_gem_object_ggtt_unpin(obj); | |
1421 | err_unref: | |
1422 | drm_gem_object_unreference(&obj->base); | |
1423 | return ret; | |
1424 | } | |
1425 | ||
1426 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1427 | struct intel_engine_cs *ring) |
e3efda49 | 1428 | { |
8ee14975 | 1429 | struct intel_ringbuffer *ringbuf = ring->buffer; |
e3efda49 CW |
1430 | int ret; |
1431 | ||
8ee14975 OM |
1432 | if (ringbuf == NULL) { |
1433 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1434 | if (!ringbuf) | |
1435 | return -ENOMEM; | |
1436 | ring->buffer = ringbuf; | |
1437 | } | |
1438 | ||
e3efda49 CW |
1439 | ring->dev = dev; |
1440 | INIT_LIST_HEAD(&ring->active_list); | |
1441 | INIT_LIST_HEAD(&ring->request_list); | |
93b0a4e0 | 1442 | ringbuf->size = 32 * PAGE_SIZE; |
ebc348b2 | 1443 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1444 | |
1445 | init_waitqueue_head(&ring->irq_queue); | |
1446 | ||
1447 | if (I915_NEED_GFX_HWS(dev)) { | |
1448 | ret = init_status_page(ring); | |
1449 | if (ret) | |
8ee14975 | 1450 | goto error; |
e3efda49 CW |
1451 | } else { |
1452 | BUG_ON(ring->id != RCS); | |
1453 | ret = init_phys_status_page(ring); | |
1454 | if (ret) | |
8ee14975 | 1455 | goto error; |
e3efda49 CW |
1456 | } |
1457 | ||
1458 | ret = allocate_ring_buffer(ring); | |
1459 | if (ret) { | |
1460 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); | |
8ee14975 | 1461 | goto error; |
e3efda49 | 1462 | } |
62fdfeaf | 1463 | |
55249baa CW |
1464 | /* Workaround an erratum on the i830 which causes a hang if |
1465 | * the TAIL pointer points to within the last 2 cachelines | |
1466 | * of the buffer. | |
1467 | */ | |
93b0a4e0 | 1468 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1469 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1470 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1471 | |
44e895a8 BV |
1472 | ret = i915_cmd_parser_init_ring(ring); |
1473 | if (ret) | |
8ee14975 OM |
1474 | goto error; |
1475 | ||
1476 | ret = ring->init(ring); | |
1477 | if (ret) | |
1478 | goto error; | |
1479 | ||
1480 | return 0; | |
351e3db2 | 1481 | |
8ee14975 OM |
1482 | error: |
1483 | kfree(ringbuf); | |
1484 | ring->buffer = NULL; | |
1485 | return ret; | |
62fdfeaf EA |
1486 | } |
1487 | ||
a4872ba6 | 1488 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1489 | { |
e3efda49 | 1490 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
93b0a4e0 | 1491 | struct intel_ringbuffer *ringbuf = ring->buffer; |
33626e6a | 1492 | |
93b0a4e0 | 1493 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1494 | return; |
1495 | ||
e3efda49 | 1496 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1497 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1498 | |
93b0a4e0 | 1499 | iounmap(ringbuf->virtual_start); |
62fdfeaf | 1500 | |
93b0a4e0 OM |
1501 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
1502 | drm_gem_object_unreference(&ringbuf->obj->base); | |
1503 | ringbuf->obj = NULL; | |
3d57e5bd BW |
1504 | ring->preallocated_lazy_request = NULL; |
1505 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1506 | |
8d19215b ZN |
1507 | if (ring->cleanup) |
1508 | ring->cleanup(ring); | |
1509 | ||
78501eac | 1510 | cleanup_status_page(ring); |
44e895a8 BV |
1511 | |
1512 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1513 | |
93b0a4e0 | 1514 | kfree(ringbuf); |
8ee14975 | 1515 | ring->buffer = NULL; |
62fdfeaf EA |
1516 | } |
1517 | ||
a4872ba6 | 1518 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1519 | { |
93b0a4e0 | 1520 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1521 | struct drm_i915_gem_request *request; |
1cf0ba14 | 1522 | u32 seqno = 0; |
a71d8d94 CW |
1523 | int ret; |
1524 | ||
93b0a4e0 OM |
1525 | if (ringbuf->last_retired_head != -1) { |
1526 | ringbuf->head = ringbuf->last_retired_head; | |
1527 | ringbuf->last_retired_head = -1; | |
1f70999f | 1528 | |
93b0a4e0 OM |
1529 | ringbuf->space = ring_space(ring); |
1530 | if (ringbuf->space >= n) | |
a71d8d94 CW |
1531 | return 0; |
1532 | } | |
1533 | ||
1534 | list_for_each_entry(request, &ring->request_list, list) { | |
93b0a4e0 | 1535 | if (__ring_space(request->tail, ringbuf->tail, ringbuf->size) >= n) { |
a71d8d94 CW |
1536 | seqno = request->seqno; |
1537 | break; | |
1538 | } | |
a71d8d94 CW |
1539 | } |
1540 | ||
1541 | if (seqno == 0) | |
1542 | return -ENOSPC; | |
1543 | ||
1f70999f | 1544 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1545 | if (ret) |
1546 | return ret; | |
1547 | ||
1cf0ba14 | 1548 | i915_gem_retire_requests_ring(ring); |
93b0a4e0 OM |
1549 | ringbuf->head = ringbuf->last_retired_head; |
1550 | ringbuf->last_retired_head = -1; | |
a71d8d94 | 1551 | |
93b0a4e0 | 1552 | ringbuf->space = ring_space(ring); |
a71d8d94 CW |
1553 | return 0; |
1554 | } | |
1555 | ||
a4872ba6 | 1556 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1557 | { |
78501eac | 1558 | struct drm_device *dev = ring->dev; |
cae5852d | 1559 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1560 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1561 | unsigned long end; |
a71d8d94 | 1562 | int ret; |
c7dca47b | 1563 | |
a71d8d94 CW |
1564 | ret = intel_ring_wait_request(ring, n); |
1565 | if (ret != -ENOSPC) | |
1566 | return ret; | |
1567 | ||
09246732 CW |
1568 | /* force the tail write in case we have been skipping them */ |
1569 | __intel_ring_advance(ring); | |
1570 | ||
63ed2cb2 DV |
1571 | /* With GEM the hangcheck timer should kick us out of the loop, |
1572 | * leaving it early runs the risk of corrupting GEM state (due | |
1573 | * to running on almost untested codepaths). But on resume | |
1574 | * timers don't work yet, so prevent a complete hang in that | |
1575 | * case by choosing an insanely large timeout. */ | |
1576 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1577 | |
dcfe0506 | 1578 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1579 | do { |
93b0a4e0 OM |
1580 | ringbuf->head = I915_READ_HEAD(ring); |
1581 | ringbuf->space = ring_space(ring); | |
1582 | if (ringbuf->space >= n) { | |
dcfe0506 CW |
1583 | ret = 0; |
1584 | break; | |
62fdfeaf EA |
1585 | } |
1586 | ||
fb19e2ac DV |
1587 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1588 | dev->primary->master) { | |
62fdfeaf EA |
1589 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1590 | if (master_priv->sarea_priv) | |
1591 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1592 | } | |
d1b851fc | 1593 | |
e60a0b10 | 1594 | msleep(1); |
d6b2c790 | 1595 | |
dcfe0506 CW |
1596 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1597 | ret = -ERESTARTSYS; | |
1598 | break; | |
1599 | } | |
1600 | ||
33196ded DV |
1601 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1602 | dev_priv->mm.interruptible); | |
d6b2c790 | 1603 | if (ret) |
dcfe0506 CW |
1604 | break; |
1605 | ||
1606 | if (time_after(jiffies, end)) { | |
1607 | ret = -EBUSY; | |
1608 | break; | |
1609 | } | |
1610 | } while (1); | |
db53a302 | 1611 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1612 | return ret; |
8187a2b7 | 1613 | } |
62fdfeaf | 1614 | |
a4872ba6 | 1615 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1616 | { |
1617 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1618 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1619 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1620 | |
93b0a4e0 | 1621 | if (ringbuf->space < rem) { |
3e960501 CW |
1622 | int ret = ring_wait_for_space(ring, rem); |
1623 | if (ret) | |
1624 | return ret; | |
1625 | } | |
1626 | ||
93b0a4e0 | 1627 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1628 | rem /= 4; |
1629 | while (rem--) | |
1630 | iowrite32(MI_NOOP, virt++); | |
1631 | ||
93b0a4e0 OM |
1632 | ringbuf->tail = 0; |
1633 | ringbuf->space = ring_space(ring); | |
3e960501 CW |
1634 | |
1635 | return 0; | |
1636 | } | |
1637 | ||
a4872ba6 | 1638 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 CW |
1639 | { |
1640 | u32 seqno; | |
1641 | int ret; | |
1642 | ||
1643 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1644 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1645 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1646 | if (ret) |
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | /* Wait upon the last request to be completed */ | |
1651 | if (list_empty(&ring->request_list)) | |
1652 | return 0; | |
1653 | ||
1654 | seqno = list_entry(ring->request_list.prev, | |
1655 | struct drm_i915_gem_request, | |
1656 | list)->seqno; | |
1657 | ||
1658 | return i915_wait_seqno(ring, seqno); | |
1659 | } | |
1660 | ||
9d773091 | 1661 | static int |
a4872ba6 | 1662 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
9d773091 | 1663 | { |
1823521d | 1664 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1665 | return 0; |
1666 | ||
3c0e234c CW |
1667 | if (ring->preallocated_lazy_request == NULL) { |
1668 | struct drm_i915_gem_request *request; | |
1669 | ||
1670 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1671 | if (request == NULL) | |
1672 | return -ENOMEM; | |
1673 | ||
1674 | ring->preallocated_lazy_request = request; | |
1675 | } | |
1676 | ||
1823521d | 1677 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1678 | } |
1679 | ||
a4872ba6 | 1680 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 1681 | int bytes) |
cbcc80df | 1682 | { |
93b0a4e0 | 1683 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
1684 | int ret; |
1685 | ||
93b0a4e0 | 1686 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
1687 | ret = intel_wrap_ring_buffer(ring); |
1688 | if (unlikely(ret)) | |
1689 | return ret; | |
1690 | } | |
1691 | ||
93b0a4e0 | 1692 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
1693 | ret = ring_wait_for_space(ring, bytes); |
1694 | if (unlikely(ret)) | |
1695 | return ret; | |
1696 | } | |
1697 | ||
cbcc80df MK |
1698 | return 0; |
1699 | } | |
1700 | ||
a4872ba6 | 1701 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 1702 | int num_dwords) |
8187a2b7 | 1703 | { |
4640c4ff | 1704 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1705 | int ret; |
78501eac | 1706 | |
33196ded DV |
1707 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1708 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1709 | if (ret) |
1710 | return ret; | |
21dd3734 | 1711 | |
304d695c CW |
1712 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
1713 | if (ret) | |
1714 | return ret; | |
1715 | ||
9d773091 CW |
1716 | /* Preallocate the olr before touching the ring */ |
1717 | ret = intel_ring_alloc_seqno(ring); | |
1718 | if (ret) | |
1719 | return ret; | |
1720 | ||
ee1b1e5e | 1721 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 1722 | return 0; |
8187a2b7 | 1723 | } |
78501eac | 1724 | |
753b1ad4 | 1725 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 1726 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 1727 | { |
ee1b1e5e | 1728 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
1729 | int ret; |
1730 | ||
1731 | if (num_dwords == 0) | |
1732 | return 0; | |
1733 | ||
18393f63 | 1734 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
1735 | ret = intel_ring_begin(ring, num_dwords); |
1736 | if (ret) | |
1737 | return ret; | |
1738 | ||
1739 | while (num_dwords--) | |
1740 | intel_ring_emit(ring, MI_NOOP); | |
1741 | ||
1742 | intel_ring_advance(ring); | |
1743 | ||
1744 | return 0; | |
1745 | } | |
1746 | ||
a4872ba6 | 1747 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 1748 | { |
3b2cc8ab OM |
1749 | struct drm_device *dev = ring->dev; |
1750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 1751 | |
1823521d | 1752 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1753 | |
3b2cc8ab | 1754 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
1755 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
1756 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 1757 | if (HAS_VEBOX(dev)) |
5020150b | 1758 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 1759 | } |
d97ed339 | 1760 | |
f7e98ad4 | 1761 | ring->set_seqno(ring, seqno); |
92cab734 | 1762 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1763 | } |
62fdfeaf | 1764 | |
a4872ba6 | 1765 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 1766 | u32 value) |
881f47b6 | 1767 | { |
4640c4ff | 1768 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1769 | |
1770 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1771 | |
1772 | /* Disable notification that the ring is IDLE. The GT | |
1773 | * will then assume that it is busy and bring it out of rc6. | |
1774 | */ | |
0206e353 | 1775 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1776 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1777 | ||
1778 | /* Clear the context id. Here be magic! */ | |
1779 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1780 | |
12f55818 | 1781 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1782 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1783 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1784 | 50)) | |
1785 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1786 | |
12f55818 | 1787 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1788 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1789 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1790 | ||
1791 | /* Let the ring send IDLE messages to the GT again, | |
1792 | * and so let it sleep to conserve power when idle. | |
1793 | */ | |
0206e353 | 1794 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1795 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1796 | } |
1797 | ||
a4872ba6 | 1798 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 1799 | u32 invalidate, u32 flush) |
881f47b6 | 1800 | { |
71a77e07 | 1801 | uint32_t cmd; |
b72f3acb CW |
1802 | int ret; |
1803 | ||
b72f3acb CW |
1804 | ret = intel_ring_begin(ring, 4); |
1805 | if (ret) | |
1806 | return ret; | |
1807 | ||
71a77e07 | 1808 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1809 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1810 | cmd += 1; | |
9a289771 JB |
1811 | /* |
1812 | * Bspec vol 1c.5 - video engine command streamer: | |
1813 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1814 | * operation is complete. This bit is only valid when the | |
1815 | * Post-Sync Operation field is a value of 1h or 3h." | |
1816 | */ | |
71a77e07 | 1817 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1818 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1819 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1820 | intel_ring_emit(ring, cmd); |
9a289771 | 1821 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1822 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1823 | intel_ring_emit(ring, 0); /* upper addr */ | |
1824 | intel_ring_emit(ring, 0); /* value */ | |
1825 | } else { | |
1826 | intel_ring_emit(ring, 0); | |
1827 | intel_ring_emit(ring, MI_NOOP); | |
1828 | } | |
b72f3acb CW |
1829 | intel_ring_advance(ring); |
1830 | return 0; | |
881f47b6 XH |
1831 | } |
1832 | ||
1c7a0623 | 1833 | static int |
a4872ba6 | 1834 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1835 | u64 offset, u32 len, |
1c7a0623 BW |
1836 | unsigned flags) |
1837 | { | |
28cf5415 BW |
1838 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1839 | bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL && | |
1840 | !(flags & I915_DISPATCH_SECURE); | |
1c7a0623 BW |
1841 | int ret; |
1842 | ||
1843 | ret = intel_ring_begin(ring, 4); | |
1844 | if (ret) | |
1845 | return ret; | |
1846 | ||
1847 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 1848 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
1849 | intel_ring_emit(ring, lower_32_bits(offset)); |
1850 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
1851 | intel_ring_emit(ring, MI_NOOP); |
1852 | intel_ring_advance(ring); | |
1853 | ||
1854 | return 0; | |
1855 | } | |
1856 | ||
d7d4eedd | 1857 | static int |
a4872ba6 | 1858 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1859 | u64 offset, u32 len, |
d7d4eedd CW |
1860 | unsigned flags) |
1861 | { | |
1862 | int ret; | |
1863 | ||
1864 | ret = intel_ring_begin(ring, 2); | |
1865 | if (ret) | |
1866 | return ret; | |
1867 | ||
1868 | intel_ring_emit(ring, | |
1869 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1870 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1871 | /* bit0-7 is the length on GEN6+ */ | |
1872 | intel_ring_emit(ring, offset); | |
1873 | intel_ring_advance(ring); | |
1874 | ||
1875 | return 0; | |
1876 | } | |
1877 | ||
881f47b6 | 1878 | static int |
a4872ba6 | 1879 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1880 | u64 offset, u32 len, |
d7d4eedd | 1881 | unsigned flags) |
881f47b6 | 1882 | { |
0206e353 | 1883 | int ret; |
ab6f8e32 | 1884 | |
0206e353 AJ |
1885 | ret = intel_ring_begin(ring, 2); |
1886 | if (ret) | |
1887 | return ret; | |
e1f99ce6 | 1888 | |
d7d4eedd CW |
1889 | intel_ring_emit(ring, |
1890 | MI_BATCH_BUFFER_START | | |
1891 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1892 | /* bit0-7 is the length on GEN6+ */ |
1893 | intel_ring_emit(ring, offset); | |
1894 | intel_ring_advance(ring); | |
ab6f8e32 | 1895 | |
0206e353 | 1896 | return 0; |
881f47b6 XH |
1897 | } |
1898 | ||
549f7365 CW |
1899 | /* Blitter support (SandyBridge+) */ |
1900 | ||
a4872ba6 | 1901 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 1902 | u32 invalidate, u32 flush) |
8d19215b | 1903 | { |
fd3da6c9 | 1904 | struct drm_device *dev = ring->dev; |
71a77e07 | 1905 | uint32_t cmd; |
b72f3acb CW |
1906 | int ret; |
1907 | ||
6a233c78 | 1908 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1909 | if (ret) |
1910 | return ret; | |
1911 | ||
71a77e07 | 1912 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1913 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1914 | cmd += 1; | |
9a289771 JB |
1915 | /* |
1916 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1917 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1918 | * operation is complete. This bit is only valid when the | |
1919 | * Post-Sync Operation field is a value of 1h or 3h." | |
1920 | */ | |
71a77e07 | 1921 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1922 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1923 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1924 | intel_ring_emit(ring, cmd); |
9a289771 | 1925 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1926 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1927 | intel_ring_emit(ring, 0); /* upper addr */ | |
1928 | intel_ring_emit(ring, 0); /* value */ | |
1929 | } else { | |
1930 | intel_ring_emit(ring, 0); | |
1931 | intel_ring_emit(ring, MI_NOOP); | |
1932 | } | |
b72f3acb | 1933 | intel_ring_advance(ring); |
fd3da6c9 | 1934 | |
9688ecad | 1935 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
1936 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
1937 | ||
b72f3acb | 1938 | return 0; |
8d19215b ZN |
1939 | } |
1940 | ||
5c1143bb XH |
1941 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1942 | { | |
4640c4ff | 1943 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1944 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1945 | |
59465b5f DV |
1946 | ring->name = "render ring"; |
1947 | ring->id = RCS; | |
1948 | ring->mmio_base = RENDER_RING_BASE; | |
1949 | ||
1ec14ad3 CW |
1950 | if (INTEL_INFO(dev)->gen >= 6) { |
1951 | ring->add_request = gen6_add_request; | |
4772eaeb | 1952 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1953 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1954 | ring->flush = gen6_render_ring_flush; |
abd58f01 | 1955 | if (INTEL_INFO(dev)->gen >= 8) { |
a5f3d68e | 1956 | ring->flush = gen8_render_ring_flush; |
abd58f01 BW |
1957 | ring->irq_get = gen8_ring_get_irq; |
1958 | ring->irq_put = gen8_ring_put_irq; | |
1959 | } else { | |
1960 | ring->irq_get = gen6_ring_get_irq; | |
1961 | ring->irq_put = gen6_ring_put_irq; | |
1962 | } | |
cc609d5d | 1963 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1964 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1965 | ring->set_seqno = ring_set_seqno; |
ebc348b2 | 1966 | ring->semaphore.sync_to = gen6_ring_sync; |
78325f2d | 1967 | ring->semaphore.signal = gen6_signal; |
845f74a7 ZY |
1968 | /* |
1969 | * The current semaphore is only applied on pre-gen8 platform. | |
1970 | * And there is no VCS2 ring on the pre-gen8 platform. So the | |
1971 | * semaphore between RCS and VCS2 is initialized as INVALID. | |
1972 | * Gen8 will initialize the sema between VCS2 and RCS later. | |
1973 | */ | |
ebc348b2 BW |
1974 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1975 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1976 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1977 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
1978 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
1979 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
1980 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
1981 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
1982 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
1983 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
c6df541c CW |
1984 | } else if (IS_GEN5(dev)) { |
1985 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1986 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1987 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1988 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1989 | ring->irq_get = gen5_ring_get_irq; |
1990 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1991 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1992 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1993 | } else { |
8620a3a9 | 1994 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1995 | if (INTEL_INFO(dev)->gen < 4) |
1996 | ring->flush = gen2_render_ring_flush; | |
1997 | else | |
1998 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1999 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2000 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2001 | if (IS_GEN2(dev)) { |
2002 | ring->irq_get = i8xx_ring_get_irq; | |
2003 | ring->irq_put = i8xx_ring_put_irq; | |
2004 | } else { | |
2005 | ring->irq_get = i9xx_ring_get_irq; | |
2006 | ring->irq_put = i9xx_ring_put_irq; | |
2007 | } | |
e3670319 | 2008 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2009 | } |
59465b5f | 2010 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
2011 | if (IS_HASWELL(dev)) |
2012 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2013 | else if (IS_GEN8(dev)) |
2014 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2015 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2016 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2017 | else if (INTEL_INFO(dev)->gen >= 4) | |
2018 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2019 | else if (IS_I830(dev) || IS_845G(dev)) | |
2020 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2021 | else | |
2022 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2023 | ring->init = init_render_ring; |
2024 | ring->cleanup = render_ring_cleanup; | |
2025 | ||
b45305fc DV |
2026 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2027 | if (HAS_BROKEN_CS_TLB(dev)) { | |
2028 | struct drm_i915_gem_object *obj; | |
2029 | int ret; | |
2030 | ||
2031 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
2032 | if (obj == NULL) { | |
2033 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2034 | return -ENOMEM; | |
2035 | } | |
2036 | ||
be1fa129 | 2037 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2038 | if (ret != 0) { |
2039 | drm_gem_object_unreference(&obj->base); | |
2040 | DRM_ERROR("Failed to ping batch bo\n"); | |
2041 | return ret; | |
2042 | } | |
2043 | ||
0d1aacac CW |
2044 | ring->scratch.obj = obj; |
2045 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2046 | } |
2047 | ||
1ec14ad3 | 2048 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2049 | } |
2050 | ||
e8616b6c CW |
2051 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2052 | { | |
4640c4ff | 2053 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2054 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
8ee14975 | 2055 | struct intel_ringbuffer *ringbuf = ring->buffer; |
6b8294a4 | 2056 | int ret; |
e8616b6c | 2057 | |
8ee14975 OM |
2058 | if (ringbuf == NULL) { |
2059 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
2060 | if (!ringbuf) | |
2061 | return -ENOMEM; | |
2062 | ring->buffer = ringbuf; | |
2063 | } | |
2064 | ||
59465b5f DV |
2065 | ring->name = "render ring"; |
2066 | ring->id = RCS; | |
2067 | ring->mmio_base = RENDER_RING_BASE; | |
2068 | ||
e8616b6c | 2069 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a | 2070 | /* non-kms not supported on gen6+ */ |
8ee14975 OM |
2071 | ret = -ENODEV; |
2072 | goto err_ringbuf; | |
e8616b6c | 2073 | } |
28f0cbf7 DV |
2074 | |
2075 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2076 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2077 | * the special gen5 functions. */ | |
2078 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2079 | if (INTEL_INFO(dev)->gen < 4) |
2080 | ring->flush = gen2_render_ring_flush; | |
2081 | else | |
2082 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2083 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2084 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2085 | if (IS_GEN2(dev)) { |
2086 | ring->irq_get = i8xx_ring_get_irq; | |
2087 | ring->irq_put = i8xx_ring_put_irq; | |
2088 | } else { | |
2089 | ring->irq_get = i9xx_ring_get_irq; | |
2090 | ring->irq_put = i9xx_ring_put_irq; | |
2091 | } | |
28f0cbf7 | 2092 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2093 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2094 | if (INTEL_INFO(dev)->gen >= 4) |
2095 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2096 | else if (IS_I830(dev) || IS_845G(dev)) | |
2097 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2098 | else | |
2099 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2100 | ring->init = init_render_ring; |
2101 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2102 | |
2103 | ring->dev = dev; | |
2104 | INIT_LIST_HEAD(&ring->active_list); | |
2105 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c | 2106 | |
93b0a4e0 OM |
2107 | ringbuf->size = size; |
2108 | ringbuf->effective_size = ringbuf->size; | |
17f10fdc | 2109 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
93b0a4e0 | 2110 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2111 | |
93b0a4e0 OM |
2112 | ringbuf->virtual_start = ioremap_wc(start, size); |
2113 | if (ringbuf->virtual_start == NULL) { | |
e8616b6c CW |
2114 | DRM_ERROR("can not ioremap virtual address for" |
2115 | " ring buffer\n"); | |
8ee14975 OM |
2116 | ret = -ENOMEM; |
2117 | goto err_ringbuf; | |
e8616b6c CW |
2118 | } |
2119 | ||
6b8294a4 | 2120 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2121 | ret = init_phys_status_page(ring); |
6b8294a4 | 2122 | if (ret) |
8ee14975 | 2123 | goto err_vstart; |
6b8294a4 CW |
2124 | } |
2125 | ||
e8616b6c | 2126 | return 0; |
8ee14975 OM |
2127 | |
2128 | err_vstart: | |
93b0a4e0 | 2129 | iounmap(ringbuf->virtual_start); |
8ee14975 OM |
2130 | err_ringbuf: |
2131 | kfree(ringbuf); | |
2132 | ring->buffer = NULL; | |
2133 | return ret; | |
e8616b6c CW |
2134 | } |
2135 | ||
5c1143bb XH |
2136 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2137 | { | |
4640c4ff | 2138 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2139 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2140 | |
58fa3835 DV |
2141 | ring->name = "bsd ring"; |
2142 | ring->id = VCS; | |
2143 | ||
0fd2c201 | 2144 | ring->write_tail = ring_write_tail; |
780f18c8 | 2145 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2146 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2147 | /* gen6 bsd needs a special wa for tail updates */ |
2148 | if (IS_GEN6(dev)) | |
2149 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2150 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2151 | ring->add_request = gen6_add_request; |
2152 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2153 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2154 | if (INTEL_INFO(dev)->gen >= 8) { |
2155 | ring->irq_enable_mask = | |
2156 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2157 | ring->irq_get = gen8_ring_get_irq; | |
2158 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2159 | ring->dispatch_execbuffer = |
2160 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
2161 | } else { |
2162 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2163 | ring->irq_get = gen6_ring_get_irq; | |
2164 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2165 | ring->dispatch_execbuffer = |
2166 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2167 | } |
ebc348b2 | 2168 | ring->semaphore.sync_to = gen6_ring_sync; |
78325f2d | 2169 | ring->semaphore.signal = gen6_signal; |
845f74a7 ZY |
2170 | /* |
2171 | * The current semaphore is only applied on pre-gen8 platform. | |
2172 | * And there is no VCS2 ring on the pre-gen8 platform. So the | |
2173 | * semaphore between VCS and VCS2 is initialized as INVALID. | |
2174 | * Gen8 will initialize the sema between VCS2 and VCS later. | |
2175 | */ | |
ebc348b2 BW |
2176 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; |
2177 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2178 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2179 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2180 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2181 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2182 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2183 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2184 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2185 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
58fa3835 DV |
2186 | } else { |
2187 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2188 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2189 | ring->add_request = i9xx_add_request; |
58fa3835 | 2190 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2191 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2192 | if (IS_GEN5(dev)) { |
cc609d5d | 2193 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2194 | ring->irq_get = gen5_ring_get_irq; |
2195 | ring->irq_put = gen5_ring_put_irq; | |
2196 | } else { | |
e3670319 | 2197 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2198 | ring->irq_get = i9xx_ring_get_irq; |
2199 | ring->irq_put = i9xx_ring_put_irq; | |
2200 | } | |
fb3256da | 2201 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2202 | } |
2203 | ring->init = init_ring_common; | |
2204 | ||
1ec14ad3 | 2205 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2206 | } |
549f7365 | 2207 | |
845f74a7 ZY |
2208 | /** |
2209 | * Initialize the second BSD ring for Broadwell GT3. | |
2210 | * It is noted that this only exists on Broadwell GT3. | |
2211 | */ | |
2212 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2213 | { | |
2214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2215 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2216 | |
2217 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2218 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2219 | return -EINVAL; | |
2220 | } | |
2221 | ||
2222 | ring->name = "bds2_ring"; | |
2223 | ring->id = VCS2; | |
2224 | ||
2225 | ring->write_tail = ring_write_tail; | |
2226 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2227 | ring->flush = gen6_bsd_ring_flush; | |
2228 | ring->add_request = gen6_add_request; | |
2229 | ring->get_seqno = gen6_ring_get_seqno; | |
2230 | ring->set_seqno = ring_set_seqno; | |
2231 | ring->irq_enable_mask = | |
2232 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2233 | ring->irq_get = gen8_ring_get_irq; | |
2234 | ring->irq_put = gen8_ring_put_irq; | |
2235 | ring->dispatch_execbuffer = | |
2236 | gen8_ring_dispatch_execbuffer; | |
ebc348b2 | 2237 | ring->semaphore.sync_to = gen6_ring_sync; |
d1533379 | 2238 | ring->semaphore.signal = gen6_signal; |
845f74a7 ZY |
2239 | /* |
2240 | * The current semaphore is only applied on the pre-gen8. And there | |
2241 | * is no bsd2 ring on the pre-gen8. So now the semaphore_register | |
2242 | * between VCS2 and other ring is initialized as invalid. | |
2243 | * Gen8 will initialize the sema between VCS2 and other ring later. | |
2244 | */ | |
ebc348b2 BW |
2245 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
2246 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2247 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2248 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2249 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2250 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2251 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2252 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2253 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2254 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
845f74a7 ZY |
2255 | |
2256 | ring->init = init_ring_common; | |
2257 | ||
2258 | return intel_init_ring_buffer(dev, ring); | |
2259 | } | |
2260 | ||
549f7365 CW |
2261 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2262 | { | |
4640c4ff | 2263 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2264 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2265 | |
3535d9dd DV |
2266 | ring->name = "blitter ring"; |
2267 | ring->id = BCS; | |
2268 | ||
2269 | ring->mmio_base = BLT_RING_BASE; | |
2270 | ring->write_tail = ring_write_tail; | |
ea251324 | 2271 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2272 | ring->add_request = gen6_add_request; |
2273 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2274 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2275 | if (INTEL_INFO(dev)->gen >= 8) { |
2276 | ring->irq_enable_mask = | |
2277 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2278 | ring->irq_get = gen8_ring_get_irq; | |
2279 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2280 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2281 | } else { |
2282 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2283 | ring->irq_get = gen6_ring_get_irq; | |
2284 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2285 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2286 | } |
ebc348b2 | 2287 | ring->semaphore.sync_to = gen6_ring_sync; |
78325f2d | 2288 | ring->semaphore.signal = gen6_signal; |
845f74a7 ZY |
2289 | /* |
2290 | * The current semaphore is only applied on pre-gen8 platform. And | |
2291 | * there is no VCS2 ring on the pre-gen8 platform. So the semaphore | |
2292 | * between BCS and VCS2 is initialized as INVALID. | |
2293 | * Gen8 will initialize the sema between BCS and VCS2 later. | |
2294 | */ | |
ebc348b2 BW |
2295 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; |
2296 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2297 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2298 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2299 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2300 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2301 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2302 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2303 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2304 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
3535d9dd | 2305 | ring->init = init_ring_common; |
549f7365 | 2306 | |
1ec14ad3 | 2307 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2308 | } |
a7b9761d | 2309 | |
9a8a2213 BW |
2310 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2311 | { | |
4640c4ff | 2312 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2313 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2314 | |
2315 | ring->name = "video enhancement ring"; | |
2316 | ring->id = VECS; | |
2317 | ||
2318 | ring->mmio_base = VEBOX_RING_BASE; | |
2319 | ring->write_tail = ring_write_tail; | |
2320 | ring->flush = gen6_ring_flush; | |
2321 | ring->add_request = gen6_add_request; | |
2322 | ring->get_seqno = gen6_ring_get_seqno; | |
2323 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2324 | |
2325 | if (INTEL_INFO(dev)->gen >= 8) { | |
2326 | ring->irq_enable_mask = | |
40c499f9 | 2327 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2328 | ring->irq_get = gen8_ring_get_irq; |
2329 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2330 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2331 | } else { |
2332 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2333 | ring->irq_get = hsw_vebox_get_irq; | |
2334 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2335 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2336 | } |
ebc348b2 | 2337 | ring->semaphore.sync_to = gen6_ring_sync; |
78325f2d | 2338 | ring->semaphore.signal = gen6_signal; |
ebc348b2 BW |
2339 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; |
2340 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2341 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2342 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2343 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2344 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2345 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2346 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2347 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2348 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
9a8a2213 BW |
2349 | ring->init = init_ring_common; |
2350 | ||
2351 | return intel_init_ring_buffer(dev, ring); | |
2352 | } | |
2353 | ||
a7b9761d | 2354 | int |
a4872ba6 | 2355 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2356 | { |
2357 | int ret; | |
2358 | ||
2359 | if (!ring->gpu_caches_dirty) | |
2360 | return 0; | |
2361 | ||
2362 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2363 | if (ret) | |
2364 | return ret; | |
2365 | ||
2366 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2367 | ||
2368 | ring->gpu_caches_dirty = false; | |
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | int | |
a4872ba6 | 2373 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2374 | { |
2375 | uint32_t flush_domains; | |
2376 | int ret; | |
2377 | ||
2378 | flush_domains = 0; | |
2379 | if (ring->gpu_caches_dirty) | |
2380 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2381 | ||
2382 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2383 | if (ret) | |
2384 | return ret; | |
2385 | ||
2386 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2387 | ||
2388 | ring->gpu_caches_dirty = false; | |
2389 | return 0; | |
2390 | } | |
e3efda49 CW |
2391 | |
2392 | void | |
a4872ba6 | 2393 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2394 | { |
2395 | int ret; | |
2396 | ||
2397 | if (!intel_ring_initialized(ring)) | |
2398 | return; | |
2399 | ||
2400 | ret = intel_ring_idle(ring); | |
2401 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2402 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2403 | ring->name, ret); | |
2404 | ||
2405 | stop_ring(ring); | |
2406 | } |