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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
605d5b32 CW |
42 | static unsigned int __intel_ring_space(unsigned int head, |
43 | unsigned int tail, | |
44 | unsigned int size) | |
c7dca47b | 45 | { |
605d5b32 CW |
46 | /* |
47 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
48 | * same cacheline, the Head Pointer must not be greater than the Tail | |
49 | * Pointer." | |
50 | */ | |
51 | GEM_BUG_ON(!is_power_of_2(size)); | |
52 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
53 | } |
54 | ||
32c04f16 | 55 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 56 | { |
e6ba9992 | 57 | ring->space = __intel_ring_space(ring->head, ring->emit, ring->size); |
ebd0fd4b DG |
58 | } |
59 | ||
b72f3acb | 60 | static int |
7c9cf4e3 | 61 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 62 | { |
73dec95e | 63 | u32 cmd, *cs; |
46f0f8d1 CW |
64 | |
65 | cmd = MI_FLUSH; | |
46f0f8d1 | 66 | |
7c9cf4e3 | 67 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
68 | cmd |= MI_READ_FLUSH; |
69 | ||
73dec95e TU |
70 | cs = intel_ring_begin(req, 2); |
71 | if (IS_ERR(cs)) | |
72 | return PTR_ERR(cs); | |
46f0f8d1 | 73 | |
73dec95e TU |
74 | *cs++ = cmd; |
75 | *cs++ = MI_NOOP; | |
76 | intel_ring_advance(req, cs); | |
46f0f8d1 CW |
77 | |
78 | return 0; | |
79 | } | |
80 | ||
81 | static int | |
7c9cf4e3 | 82 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 83 | { |
73dec95e | 84 | u32 cmd, *cs; |
6f392d54 | 85 | |
36d527de CW |
86 | /* |
87 | * read/write caches: | |
88 | * | |
89 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
90 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
91 | * also flushed at 2d versus 3d pipeline switches. | |
92 | * | |
93 | * read-only caches: | |
94 | * | |
95 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
96 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
97 | * | |
98 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
99 | * | |
100 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
101 | * invalidated when MI_EXE_FLUSH is set. | |
102 | * | |
103 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
104 | * invalidated with every MI_FLUSH. | |
105 | * | |
106 | * TLBs: | |
107 | * | |
108 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
109 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
110 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
111 | * are flushed at any MI_FLUSH. | |
112 | */ | |
113 | ||
b5321f30 | 114 | cmd = MI_FLUSH; |
7c9cf4e3 | 115 | if (mode & EMIT_INVALIDATE) { |
36d527de | 116 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
117 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
118 | cmd |= MI_INVALIDATE_ISP; | |
119 | } | |
70eac33e | 120 | |
73dec95e TU |
121 | cs = intel_ring_begin(req, 2); |
122 | if (IS_ERR(cs)) | |
123 | return PTR_ERR(cs); | |
b72f3acb | 124 | |
73dec95e TU |
125 | *cs++ = cmd; |
126 | *cs++ = MI_NOOP; | |
127 | intel_ring_advance(req, cs); | |
b72f3acb CW |
128 | |
129 | return 0; | |
8187a2b7 ZN |
130 | } |
131 | ||
8d315287 JB |
132 | /** |
133 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
134 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
135 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
136 | * | |
137 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
138 | * produced by non-pipelined state commands), software needs to first | |
139 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
140 | * 0. | |
141 | * | |
142 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
143 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
144 | * | |
145 | * And the workaround for these two requires this workaround first: | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
148 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
149 | * flushes. | |
150 | * | |
151 | * And this last workaround is tricky because of the requirements on | |
152 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
153 | * volume 2 part 1: | |
154 | * | |
155 | * "1 of the following must also be set: | |
156 | * - Render Target Cache Flush Enable ([12] of DW1) | |
157 | * - Depth Cache Flush Enable ([0] of DW1) | |
158 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
159 | * - Depth Stall ([13] of DW1) | |
160 | * - Post-Sync Operation ([13] of DW1) | |
161 | * - Notify Enable ([8] of DW1)" | |
162 | * | |
163 | * The cache flushes require the workaround flush that triggered this | |
164 | * one, so we can't use it. Depth stall would trigger the same. | |
165 | * Post-sync nonzero is what triggered this second workaround, so we | |
166 | * can't use that one either. Notify enable is IRQs, which aren't | |
167 | * really our business. That leaves only stall at scoreboard. | |
168 | */ | |
169 | static int | |
f2cf1fcc | 170 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 171 | { |
b5321f30 | 172 | u32 scratch_addr = |
bde13ebd | 173 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
174 | u32 *cs; |
175 | ||
176 | cs = intel_ring_begin(req, 6); | |
177 | if (IS_ERR(cs)) | |
178 | return PTR_ERR(cs); | |
179 | ||
180 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
181 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
182 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
183 | *cs++ = 0; /* low dword */ | |
184 | *cs++ = 0; /* high dword */ | |
185 | *cs++ = MI_NOOP; | |
186 | intel_ring_advance(req, cs); | |
187 | ||
188 | cs = intel_ring_begin(req, 6); | |
189 | if (IS_ERR(cs)) | |
190 | return PTR_ERR(cs); | |
191 | ||
192 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
193 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
194 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
195 | *cs++ = 0; | |
196 | *cs++ = 0; | |
197 | *cs++ = MI_NOOP; | |
198 | intel_ring_advance(req, cs); | |
8d315287 JB |
199 | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static int | |
7c9cf4e3 | 204 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 205 | { |
b5321f30 | 206 | u32 scratch_addr = |
bde13ebd | 207 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 208 | u32 *cs, flags = 0; |
8d315287 JB |
209 | int ret; |
210 | ||
b3111509 | 211 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 212 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
213 | if (ret) |
214 | return ret; | |
215 | ||
8d315287 JB |
216 | /* Just flush everything. Experiments have shown that reducing the |
217 | * number of bits based on the write domains has little performance | |
218 | * impact. | |
219 | */ | |
7c9cf4e3 | 220 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
221 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
222 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
223 | /* | |
224 | * Ensure that any following seqno writes only happen | |
225 | * when the render cache is indeed flushed. | |
226 | */ | |
97f209bc | 227 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 228 | } |
7c9cf4e3 | 229 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
230 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
231 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
232 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
233 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
234 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
235 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
236 | /* | |
237 | * TLB invalidate requires a post-sync write. | |
238 | */ | |
3ac78313 | 239 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 240 | } |
8d315287 | 241 | |
73dec95e TU |
242 | cs = intel_ring_begin(req, 4); |
243 | if (IS_ERR(cs)) | |
244 | return PTR_ERR(cs); | |
8d315287 | 245 | |
73dec95e TU |
246 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
247 | *cs++ = flags; | |
248 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
249 | *cs++ = 0; | |
250 | intel_ring_advance(req, cs); | |
8d315287 JB |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
f3987631 | 255 | static int |
f2cf1fcc | 256 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 257 | { |
73dec95e | 258 | u32 *cs; |
f3987631 | 259 | |
73dec95e TU |
260 | cs = intel_ring_begin(req, 4); |
261 | if (IS_ERR(cs)) | |
262 | return PTR_ERR(cs); | |
f3987631 | 263 | |
73dec95e TU |
264 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
265 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
266 | *cs++ = 0; | |
267 | *cs++ = 0; | |
268 | intel_ring_advance(req, cs); | |
f3987631 PZ |
269 | |
270 | return 0; | |
271 | } | |
272 | ||
4772eaeb | 273 | static int |
7c9cf4e3 | 274 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 275 | { |
b5321f30 | 276 | u32 scratch_addr = |
bde13ebd | 277 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 278 | u32 *cs, flags = 0; |
4772eaeb | 279 | |
f3987631 PZ |
280 | /* |
281 | * Ensure that any following seqno writes only happen when the render | |
282 | * cache is indeed flushed. | |
283 | * | |
284 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
285 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
286 | * don't try to be clever and just set it unconditionally. | |
287 | */ | |
288 | flags |= PIPE_CONTROL_CS_STALL; | |
289 | ||
4772eaeb PZ |
290 | /* Just flush everything. Experiments have shown that reducing the |
291 | * number of bits based on the write domains has little performance | |
292 | * impact. | |
293 | */ | |
7c9cf4e3 | 294 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
295 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
296 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 297 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 298 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 299 | } |
7c9cf4e3 | 300 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
301 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
302 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
303 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
304 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
305 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
306 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 307 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
308 | /* |
309 | * TLB invalidate requires a post-sync write. | |
310 | */ | |
311 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 312 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 313 | |
add284a3 CW |
314 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
315 | ||
f3987631 PZ |
316 | /* Workaround: we must issue a pipe_control with CS-stall bit |
317 | * set before a pipe_control command that has the state cache | |
318 | * invalidate bit set. */ | |
f2cf1fcc | 319 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
320 | } |
321 | ||
73dec95e TU |
322 | cs = intel_ring_begin(req, 4); |
323 | if (IS_ERR(cs)) | |
324 | return PTR_ERR(cs); | |
4772eaeb | 325 | |
73dec95e TU |
326 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
327 | *cs++ = flags; | |
328 | *cs++ = scratch_addr; | |
329 | *cs++ = 0; | |
330 | intel_ring_advance(req, cs); | |
4772eaeb PZ |
331 | |
332 | return 0; | |
333 | } | |
334 | ||
884ceace | 335 | static int |
9f235dfa | 336 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
884ceace | 337 | { |
9f235dfa | 338 | u32 flags; |
73dec95e | 339 | u32 *cs; |
884ceace | 340 | |
9f235dfa | 341 | cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6); |
73dec95e TU |
342 | if (IS_ERR(cs)) |
343 | return PTR_ERR(cs); | |
884ceace | 344 | |
9f235dfa | 345 | flags = PIPE_CONTROL_CS_STALL; |
a5f3d68e | 346 | |
7c9cf4e3 | 347 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
348 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
349 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 350 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 351 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 352 | } |
7c9cf4e3 | 353 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
354 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
355 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
356 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
357 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
358 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
359 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
360 | flags |= PIPE_CONTROL_QW_WRITE; | |
361 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
362 | |
363 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
9f235dfa TU |
364 | cs = gen8_emit_pipe_control(cs, |
365 | PIPE_CONTROL_CS_STALL | | |
366 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
367 | 0); | |
a5f3d68e BW |
368 | } |
369 | ||
9f235dfa TU |
370 | cs = gen8_emit_pipe_control(cs, flags, |
371 | i915_ggtt_offset(req->engine->scratch) + | |
372 | 2 * CACHELINE_BYTES); | |
373 | ||
374 | intel_ring_advance(req, cs); | |
375 | ||
376 | return 0; | |
a5f3d68e BW |
377 | } |
378 | ||
0bc40be8 | 379 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 380 | { |
c033666a | 381 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
382 | u32 addr; |
383 | ||
384 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 385 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
386 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
387 | I915_WRITE(HWS_PGA, addr); | |
388 | } | |
389 | ||
0bc40be8 | 390 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 391 | { |
c033666a | 392 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 393 | i915_reg_t mmio; |
af75f269 DL |
394 | |
395 | /* The ring status page addresses are no longer next to the rest of | |
396 | * the ring registers as of gen7. | |
397 | */ | |
c033666a | 398 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 399 | switch (engine->id) { |
af75f269 DL |
400 | case RCS: |
401 | mmio = RENDER_HWS_PGA_GEN7; | |
402 | break; | |
403 | case BCS: | |
404 | mmio = BLT_HWS_PGA_GEN7; | |
405 | break; | |
406 | /* | |
407 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
408 | * gcc switch check warning | |
409 | */ | |
410 | case VCS2: | |
411 | case VCS: | |
412 | mmio = BSD_HWS_PGA_GEN7; | |
413 | break; | |
414 | case VECS: | |
415 | mmio = VEBOX_HWS_PGA_GEN7; | |
416 | break; | |
417 | } | |
c033666a | 418 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 419 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
420 | } else { |
421 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 422 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
423 | } |
424 | ||
57e88531 | 425 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
426 | POSTING_READ(mmio); |
427 | ||
428 | /* | |
429 | * Flush the TLB for this page | |
430 | * | |
431 | * FIXME: These two bits have disappeared on gen8, so a question | |
432 | * arises: do we still need this and if so how should we go about | |
433 | * invalidating the TLB? | |
434 | */ | |
ac657f64 | 435 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 436 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
437 | |
438 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 439 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
440 | |
441 | I915_WRITE(reg, | |
442 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
443 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
444 | if (intel_wait_for_register(dev_priv, |
445 | reg, INSTPM_SYNC_FLUSH, 0, | |
446 | 1000)) | |
af75f269 | 447 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 448 | engine->name); |
af75f269 DL |
449 | } |
450 | } | |
451 | ||
0bc40be8 | 452 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 453 | { |
c033666a | 454 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 455 | |
21a2c58a | 456 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 457 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
458 | if (intel_wait_for_register(dev_priv, |
459 | RING_MI_MODE(engine->mmio_base), | |
460 | MODE_IDLE, | |
461 | MODE_IDLE, | |
462 | 1000)) { | |
0bc40be8 TU |
463 | DRM_ERROR("%s : timed out trying to stop ring\n", |
464 | engine->name); | |
9bec9b13 CW |
465 | /* Sometimes we observe that the idle flag is not |
466 | * set even though the ring is empty. So double | |
467 | * check before giving up. | |
468 | */ | |
0bc40be8 | 469 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 470 | return false; |
9991ae78 CW |
471 | } |
472 | } | |
b7884eb4 | 473 | |
0bc40be8 TU |
474 | I915_WRITE_CTL(engine, 0); |
475 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 476 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 477 | |
21a2c58a | 478 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
479 | (void)I915_READ_CTL(engine); |
480 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 481 | } |
a51435a3 | 482 | |
0bc40be8 | 483 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 484 | } |
8187a2b7 | 485 | |
0bc40be8 | 486 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 487 | { |
c033666a | 488 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 489 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
490 | int ret = 0; |
491 | ||
59bad947 | 492 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 493 | |
0bc40be8 | 494 | if (!stop_ring(engine)) { |
9991ae78 | 495 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
496 | DRM_DEBUG_KMS("%s head not reset to zero " |
497 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
498 | engine->name, |
499 | I915_READ_CTL(engine), | |
500 | I915_READ_HEAD(engine), | |
501 | I915_READ_TAIL(engine), | |
502 | I915_READ_START(engine)); | |
8187a2b7 | 503 | |
0bc40be8 | 504 | if (!stop_ring(engine)) { |
6fd0d56e CW |
505 | DRM_ERROR("failed to set %s head to zero " |
506 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
507 | engine->name, |
508 | I915_READ_CTL(engine), | |
509 | I915_READ_HEAD(engine), | |
510 | I915_READ_TAIL(engine), | |
511 | I915_READ_START(engine)); | |
9991ae78 CW |
512 | ret = -EIO; |
513 | goto out; | |
6fd0d56e | 514 | } |
8187a2b7 ZN |
515 | } |
516 | ||
3177659a | 517 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 518 | ring_setup_phys_status_page(engine); |
3177659a CS |
519 | else |
520 | intel_ring_setup_status_page(engine); | |
9991ae78 | 521 | |
ad07dfcd | 522 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 523 | |
ece4a17d | 524 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 525 | I915_READ_HEAD(engine); |
ece4a17d | 526 | |
0d8957c8 DV |
527 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
528 | * registers with the above sequence (the readback of the HEAD registers | |
529 | * also enforces ordering), otherwise the hw might lose the new ring | |
530 | * register values. */ | |
bde13ebd | 531 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
532 | |
533 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 534 | if (I915_READ_HEAD(engine)) |
95468892 | 535 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 536 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
537 | |
538 | intel_ring_update_space(ring); | |
539 | I915_WRITE_HEAD(engine, ring->head); | |
540 | I915_WRITE_TAIL(engine, ring->tail); | |
541 | (void)I915_READ_TAIL(engine); | |
95468892 | 542 | |
62ae14b1 | 543 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 544 | |
8187a2b7 | 545 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
546 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
547 | RING_VALID, RING_VALID, | |
548 | 50)) { | |
e74cfed5 | 549 | DRM_ERROR("%s initialization failed " |
821ed7df | 550 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
551 | engine->name, |
552 | I915_READ_CTL(engine), | |
553 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
554 | I915_READ_HEAD(engine), ring->head, |
555 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 556 | I915_READ_START(engine), |
bde13ebd | 557 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
558 | ret = -EIO; |
559 | goto out; | |
8187a2b7 ZN |
560 | } |
561 | ||
fc0768ce | 562 | intel_engine_init_hangcheck(engine); |
50f018df | 563 | |
b7884eb4 | 564 | out: |
59bad947 | 565 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
566 | |
567 | return ret; | |
8187a2b7 ZN |
568 | } |
569 | ||
821ed7df CW |
570 | static void reset_ring_common(struct intel_engine_cs *engine, |
571 | struct drm_i915_gem_request *request) | |
572 | { | |
c0dcb203 CW |
573 | /* Try to restore the logical GPU state to match the continuation |
574 | * of the request queue. If we skip the context/PD restore, then | |
575 | * the next request may try to execute assuming that its context | |
576 | * is valid and loaded on the GPU and so may try to access invalid | |
577 | * memory, prompting repeated GPU hangs. | |
578 | * | |
579 | * If the request was guilty, we still restore the logical state | |
580 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
581 | * but skip over the hung batch. | |
582 | * | |
583 | * If the request was innocent, we try to replay the request with | |
584 | * the restored context. | |
585 | */ | |
586 | if (request) { | |
587 | struct drm_i915_private *dev_priv = request->i915; | |
588 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
589 | struct i915_hw_ppgtt *ppgtt; | |
590 | ||
591 | /* FIXME consider gen8 reset */ | |
592 | ||
593 | if (ce->state) { | |
594 | I915_WRITE(CCID, | |
595 | i915_ggtt_offset(ce->state) | | |
596 | BIT(8) /* must be set! */ | | |
597 | CCID_EXTENDED_STATE_SAVE | | |
598 | CCID_EXTENDED_STATE_RESTORE | | |
599 | CCID_EN); | |
600 | } | |
601 | ||
602 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
603 | if (ppgtt) { | |
604 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
605 | ||
606 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
607 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
608 | ||
609 | /* Wait for the PD reload to complete */ | |
610 | if (intel_wait_for_register(dev_priv, | |
611 | RING_PP_DIR_BASE(engine), | |
612 | BIT(0), 0, | |
613 | 10)) | |
614 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 615 | |
c0dcb203 CW |
616 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
617 | } | |
618 | ||
619 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
fe085f13 CW |
620 | if (request->fence.error == -EIO) |
621 | request->ring->head = request->postfix; | |
c0dcb203 CW |
622 | } else { |
623 | engine->legacy_active_context = NULL; | |
624 | } | |
821ed7df CW |
625 | } |
626 | ||
8753181e | 627 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
628 | { |
629 | int ret; | |
630 | ||
e2be4faf | 631 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
632 | if (ret != 0) |
633 | return ret; | |
634 | ||
4e50f082 | 635 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 636 | if (ret) |
e26e1b97 | 637 | return ret; |
8f0e2b9d | 638 | |
e26e1b97 | 639 | return 0; |
8f0e2b9d DV |
640 | } |
641 | ||
0bc40be8 | 642 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 643 | { |
c033666a | 644 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 645 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
646 | if (ret) |
647 | return ret; | |
a69ffdbf | 648 | |
61a563a2 | 649 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 650 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 651 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
652 | |
653 | /* We need to disable the AsyncFlip performance optimisations in order | |
654 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
655 | * programmed to '1' on all products. | |
8693a824 | 656 | * |
2441f877 | 657 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 658 | */ |
ac657f64 | 659 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
660 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
661 | ||
f05bb0c7 | 662 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 663 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 664 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 665 | I915_WRITE(GFX_MODE, |
aa83e30d | 666 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 667 | |
01fa0302 | 668 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 669 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 670 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 671 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 672 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 673 | |
c033666a | 674 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
675 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
676 | * "If this bit is set, STCunit will have LRA as replacement | |
677 | * policy. [...] This bit must be reset. LRA replacement | |
678 | * policy is not supported." | |
679 | */ | |
680 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 681 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
682 | } |
683 | ||
ac657f64 | 684 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 685 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 686 | |
035ea405 VS |
687 | if (INTEL_INFO(dev_priv)->gen >= 6) |
688 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 689 | |
0bc40be8 | 690 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
691 | } |
692 | ||
0bc40be8 | 693 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 694 | { |
c033666a | 695 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 696 | |
19880c4a | 697 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
698 | } |
699 | ||
73dec95e | 700 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 701 | { |
ad7bdb2b | 702 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 703 | struct intel_engine_cs *waiter; |
c3232b18 | 704 | enum intel_engine_id id; |
3e78998a | 705 | |
3b3f1650 | 706 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 707 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
708 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
709 | continue; | |
710 | ||
73dec95e TU |
711 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
712 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | | |
713 | PIPE_CONTROL_CS_STALL; | |
714 | *cs++ = lower_32_bits(gtt_offset); | |
715 | *cs++ = upper_32_bits(gtt_offset); | |
716 | *cs++ = req->global_seqno; | |
717 | *cs++ = 0; | |
718 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
719 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
720 | *cs++ = 0; | |
3e78998a BW |
721 | } |
722 | ||
73dec95e | 723 | return cs; |
3e78998a BW |
724 | } |
725 | ||
73dec95e | 726 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 727 | { |
ad7bdb2b | 728 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 729 | struct intel_engine_cs *waiter; |
c3232b18 | 730 | enum intel_engine_id id; |
3e78998a | 731 | |
3b3f1650 | 732 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 733 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
734 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
735 | continue; | |
736 | ||
73dec95e TU |
737 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
738 | *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
739 | *cs++ = upper_32_bits(gtt_offset); | |
740 | *cs++ = req->global_seqno; | |
741 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
742 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
743 | *cs++ = 0; | |
3e78998a BW |
744 | } |
745 | ||
73dec95e | 746 | return cs; |
3e78998a BW |
747 | } |
748 | ||
73dec95e | 749 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 750 | { |
ad7bdb2b | 751 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 752 | struct intel_engine_cs *engine; |
3b3f1650 | 753 | enum intel_engine_id id; |
caddfe71 | 754 | int num_rings = 0; |
024a43e1 | 755 | |
3b3f1650 | 756 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
757 | i915_reg_t mbox_reg; |
758 | ||
759 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
760 | continue; | |
f0f59a00 | 761 | |
318f89ca | 762 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 763 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
764 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
765 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
766 | *cs++ = req->global_seqno; | |
caddfe71 | 767 | num_rings++; |
78325f2d BW |
768 | } |
769 | } | |
caddfe71 | 770 | if (num_rings & 1) |
73dec95e | 771 | *cs++ = MI_NOOP; |
024a43e1 | 772 | |
73dec95e | 773 | return cs; |
1ec14ad3 CW |
774 | } |
775 | ||
b0411e7d CW |
776 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
777 | { | |
778 | struct drm_i915_private *dev_priv = request->i915; | |
779 | ||
d55ac5bf CW |
780 | i915_gem_request_submit(request); |
781 | ||
e6ba9992 CW |
782 | I915_WRITE_TAIL(request->engine, |
783 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
784 | } |
785 | ||
73dec95e | 786 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 787 | { |
73dec95e TU |
788 | *cs++ = MI_STORE_DWORD_INDEX; |
789 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
790 | *cs++ = req->global_seqno; | |
791 | *cs++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 792 | |
73dec95e | 793 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 794 | assert_ring_tail_valid(req->ring, req->tail); |
1ec14ad3 CW |
795 | } |
796 | ||
98f29e8d CW |
797 | static const int i9xx_emit_breadcrumb_sz = 4; |
798 | ||
b0411e7d | 799 | /** |
9b81d556 | 800 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
801 | * |
802 | * @request - request to write to the ring | |
803 | * | |
804 | * Update the mailbox registers in the *other* rings with the current seqno. | |
805 | * This acts like a signal in the canonical semaphore. | |
806 | */ | |
73dec95e | 807 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
b0411e7d | 808 | { |
caddfe71 | 809 | return i9xx_emit_breadcrumb(req, |
73dec95e | 810 | req->engine->semaphore.signal(req, cs)); |
b0411e7d CW |
811 | } |
812 | ||
caddfe71 | 813 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
73dec95e | 814 | u32 *cs) |
a58c01aa CW |
815 | { |
816 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 817 | |
caddfe71 | 818 | if (engine->semaphore.signal) |
73dec95e TU |
819 | cs = engine->semaphore.signal(req, cs); |
820 | ||
821 | *cs++ = GFX_OP_PIPE_CONTROL(6); | |
822 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
823 | PIPE_CONTROL_QW_WRITE; | |
824 | *cs++ = intel_hws_seqno_address(engine); | |
825 | *cs++ = 0; | |
826 | *cs++ = req->global_seqno; | |
a58c01aa | 827 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
828 | *cs++ = 0; |
829 | *cs++ = MI_USER_INTERRUPT; | |
830 | *cs++ = MI_NOOP; | |
a58c01aa | 831 | |
73dec95e | 832 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 833 | assert_ring_tail_valid(req->ring, req->tail); |
a58c01aa CW |
834 | } |
835 | ||
98f29e8d CW |
836 | static const int gen8_render_emit_breadcrumb_sz = 8; |
837 | ||
c8c99b0f BW |
838 | /** |
839 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
840 | * | |
841 | * @waiter - ring that is waiting | |
842 | * @signaller - ring which has, or will signal | |
843 | * @seqno - seqno which the waiter will block on | |
844 | */ | |
5ee426ca BW |
845 | |
846 | static int | |
ad7bdb2b CW |
847 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
848 | struct drm_i915_gem_request *signal) | |
5ee426ca | 849 | { |
ad7bdb2b CW |
850 | struct drm_i915_private *dev_priv = req->i915; |
851 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 852 | struct i915_hw_ppgtt *ppgtt; |
73dec95e | 853 | u32 *cs; |
5ee426ca | 854 | |
73dec95e TU |
855 | cs = intel_ring_begin(req, 4); |
856 | if (IS_ERR(cs)) | |
857 | return PTR_ERR(cs); | |
5ee426ca | 858 | |
73dec95e TU |
859 | *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | |
860 | MI_SEMAPHORE_SAD_GTE_SDD; | |
861 | *cs++ = signal->global_seqno; | |
862 | *cs++ = lower_32_bits(offset); | |
863 | *cs++ = upper_32_bits(offset); | |
864 | intel_ring_advance(req, cs); | |
6ef48d7f CW |
865 | |
866 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
867 | * pagetables and we must reload them before executing the batch. | |
868 | * We do this on the i915_switch_context() following the wait and | |
869 | * before the dispatch. | |
870 | */ | |
ad7bdb2b CW |
871 | ppgtt = req->ctx->ppgtt; |
872 | if (ppgtt && req->engine->id != RCS) | |
873 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
874 | return 0; |
875 | } | |
876 | ||
c8c99b0f | 877 | static int |
ad7bdb2b CW |
878 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
879 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 880 | { |
c8c99b0f BW |
881 | u32 dw1 = MI_SEMAPHORE_MBOX | |
882 | MI_SEMAPHORE_COMPARE | | |
883 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 884 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
73dec95e | 885 | u32 *cs; |
1ec14ad3 | 886 | |
ebc348b2 | 887 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 888 | |
73dec95e TU |
889 | cs = intel_ring_begin(req, 4); |
890 | if (IS_ERR(cs)) | |
891 | return PTR_ERR(cs); | |
1ec14ad3 | 892 | |
73dec95e | 893 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
894 | /* Throughout all of the GEM code, seqno passed implies our current |
895 | * seqno is >= the last seqno executed. However for hardware the | |
896 | * comparison is strictly greater than. | |
897 | */ | |
73dec95e TU |
898 | *cs++ = signal->global_seqno - 1; |
899 | *cs++ = 0; | |
900 | *cs++ = MI_NOOP; | |
901 | intel_ring_advance(req, cs); | |
1ec14ad3 CW |
902 | |
903 | return 0; | |
904 | } | |
905 | ||
f8973c21 | 906 | static void |
38a0f2db | 907 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 908 | { |
f8973c21 CW |
909 | /* MI_STORE are internally buffered by the GPU and not flushed |
910 | * either by MI_FLUSH or SyncFlush or any other combination of | |
911 | * MI commands. | |
c6df541c | 912 | * |
f8973c21 CW |
913 | * "Only the submission of the store operation is guaranteed. |
914 | * The write result will be complete (coherent) some time later | |
915 | * (this is practically a finite period but there is no guaranteed | |
916 | * latency)." | |
917 | * | |
918 | * Empirically, we observe that we need a delay of at least 75us to | |
919 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 920 | */ |
f8973c21 | 921 | usleep_range(125, 250); |
c6df541c CW |
922 | } |
923 | ||
c04e0f3b CW |
924 | static void |
925 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 926 | { |
c033666a | 927 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 928 | |
4cd53c0c DV |
929 | /* Workaround to force correct ordering between irq and seqno writes on |
930 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
931 | * ACTHD) before reading the status page. |
932 | * | |
933 | * Note that this effectively stalls the read by the time it takes to | |
934 | * do a memory transaction, which more or less ensures that the write | |
935 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
936 | * Alternatively we could delay the interrupt from the CS ring to give | |
937 | * the write time to land, but that would incur a delay after every | |
938 | * batch i.e. much more frequent than a delay when waiting for the | |
939 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
940 | * |
941 | * Also note that to prevent whole machine hangs on gen7, we have to | |
942 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 943 | */ |
bcbdb6d0 | 944 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 945 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 946 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
947 | } |
948 | ||
31bb59cc CW |
949 | static void |
950 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 951 | { |
31bb59cc | 952 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
953 | } |
954 | ||
955 | static void | |
31bb59cc | 956 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 957 | { |
31bb59cc | 958 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
959 | } |
960 | ||
31bb59cc CW |
961 | static void |
962 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 963 | { |
c033666a | 964 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 965 | |
31bb59cc CW |
966 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
967 | I915_WRITE(IMR, dev_priv->irq_mask); | |
968 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
969 | } |
970 | ||
8187a2b7 | 971 | static void |
31bb59cc | 972 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 973 | { |
c033666a | 974 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 975 | |
31bb59cc CW |
976 | dev_priv->irq_mask |= engine->irq_enable_mask; |
977 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
978 | } |
979 | ||
31bb59cc CW |
980 | static void |
981 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 982 | { |
c033666a | 983 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 984 | |
31bb59cc CW |
985 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
986 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
987 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
988 | } |
989 | ||
990 | static void | |
31bb59cc | 991 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 992 | { |
c033666a | 993 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 994 | |
31bb59cc CW |
995 | dev_priv->irq_mask |= engine->irq_enable_mask; |
996 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
997 | } |
998 | ||
b72f3acb | 999 | static int |
7c9cf4e3 | 1000 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1001 | { |
73dec95e | 1002 | u32 *cs; |
b72f3acb | 1003 | |
73dec95e TU |
1004 | cs = intel_ring_begin(req, 2); |
1005 | if (IS_ERR(cs)) | |
1006 | return PTR_ERR(cs); | |
b72f3acb | 1007 | |
73dec95e TU |
1008 | *cs++ = MI_FLUSH; |
1009 | *cs++ = MI_NOOP; | |
1010 | intel_ring_advance(req, cs); | |
b72f3acb | 1011 | return 0; |
d1b851fc ZN |
1012 | } |
1013 | ||
31bb59cc CW |
1014 | static void |
1015 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1016 | { |
c033666a | 1017 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1018 | |
61ff75ac CW |
1019 | I915_WRITE_IMR(engine, |
1020 | ~(engine->irq_enable_mask | | |
1021 | engine->irq_keep_mask)); | |
31bb59cc | 1022 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1023 | } |
1024 | ||
1025 | static void | |
31bb59cc | 1026 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1027 | { |
c033666a | 1028 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1029 | |
61ff75ac | 1030 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1031 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1032 | } |
1033 | ||
31bb59cc CW |
1034 | static void |
1035 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1036 | { |
c033666a | 1037 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1038 | |
31bb59cc | 1039 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1040 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1041 | } |
1042 | ||
1043 | static void | |
31bb59cc | 1044 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1045 | { |
c033666a | 1046 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1047 | |
31bb59cc | 1048 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1049 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1050 | } |
1051 | ||
31bb59cc CW |
1052 | static void |
1053 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1054 | { |
c033666a | 1055 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1056 | |
61ff75ac CW |
1057 | I915_WRITE_IMR(engine, |
1058 | ~(engine->irq_enable_mask | | |
1059 | engine->irq_keep_mask)); | |
31bb59cc | 1060 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1061 | } |
1062 | ||
1063 | static void | |
31bb59cc | 1064 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1065 | { |
c033666a | 1066 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1067 | |
61ff75ac | 1068 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1069 | } |
1070 | ||
d1b851fc | 1071 | static int |
803688ba CW |
1072 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1073 | u64 offset, u32 length, | |
1074 | unsigned int dispatch_flags) | |
d1b851fc | 1075 | { |
73dec95e | 1076 | u32 *cs; |
78501eac | 1077 | |
73dec95e TU |
1078 | cs = intel_ring_begin(req, 2); |
1079 | if (IS_ERR(cs)) | |
1080 | return PTR_ERR(cs); | |
e1f99ce6 | 1081 | |
73dec95e TU |
1082 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1083 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1084 | *cs++ = offset; | |
1085 | intel_ring_advance(req, cs); | |
78501eac | 1086 | |
d1b851fc ZN |
1087 | return 0; |
1088 | } | |
1089 | ||
b45305fc DV |
1090 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1091 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1092 | #define I830_TLB_ENTRIES (2) |
1093 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1094 | static int |
803688ba CW |
1095 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1096 | u64 offset, u32 len, | |
1097 | unsigned int dispatch_flags) | |
62fdfeaf | 1098 | { |
73dec95e | 1099 | u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); |
62fdfeaf | 1100 | |
73dec95e TU |
1101 | cs = intel_ring_begin(req, 6); |
1102 | if (IS_ERR(cs)) | |
1103 | return PTR_ERR(cs); | |
62fdfeaf | 1104 | |
c4d69da1 | 1105 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1106 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1107 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1108 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1109 | *cs++ = cs_offset; | |
1110 | *cs++ = 0xdeadbeef; | |
1111 | *cs++ = MI_NOOP; | |
1112 | intel_ring_advance(req, cs); | |
b45305fc | 1113 | |
8e004efc | 1114 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1115 | if (len > I830_BATCH_LIMIT) |
1116 | return -ENOSPC; | |
1117 | ||
73dec95e TU |
1118 | cs = intel_ring_begin(req, 6 + 2); |
1119 | if (IS_ERR(cs)) | |
1120 | return PTR_ERR(cs); | |
c4d69da1 CW |
1121 | |
1122 | /* Blit the batch (which has now all relocs applied) to the | |
1123 | * stable batch scratch bo area (so that the CS never | |
1124 | * stumbles over its tlb invalidation bug) ... | |
1125 | */ | |
73dec95e TU |
1126 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1127 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1128 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1129 | *cs++ = cs_offset; | |
1130 | *cs++ = 4096; | |
1131 | *cs++ = offset; | |
1132 | ||
1133 | *cs++ = MI_FLUSH; | |
1134 | *cs++ = MI_NOOP; | |
1135 | intel_ring_advance(req, cs); | |
b45305fc DV |
1136 | |
1137 | /* ... and execute it. */ | |
c4d69da1 | 1138 | offset = cs_offset; |
b45305fc | 1139 | } |
e1f99ce6 | 1140 | |
73dec95e TU |
1141 | cs = intel_ring_begin(req, 2); |
1142 | if (IS_ERR(cs)) | |
1143 | return PTR_ERR(cs); | |
c4d69da1 | 1144 | |
73dec95e TU |
1145 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1146 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1147 | MI_BATCH_NON_SECURE); | |
1148 | intel_ring_advance(req, cs); | |
c4d69da1 | 1149 | |
fb3256da DV |
1150 | return 0; |
1151 | } | |
1152 | ||
1153 | static int | |
803688ba CW |
1154 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1155 | u64 offset, u32 len, | |
1156 | unsigned int dispatch_flags) | |
fb3256da | 1157 | { |
73dec95e | 1158 | u32 *cs; |
fb3256da | 1159 | |
73dec95e TU |
1160 | cs = intel_ring_begin(req, 2); |
1161 | if (IS_ERR(cs)) | |
1162 | return PTR_ERR(cs); | |
fb3256da | 1163 | |
73dec95e TU |
1164 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1165 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1166 | MI_BATCH_NON_SECURE); | |
1167 | intel_ring_advance(req, cs); | |
62fdfeaf | 1168 | |
62fdfeaf EA |
1169 | return 0; |
1170 | } | |
1171 | ||
0bc40be8 | 1172 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1173 | { |
c033666a | 1174 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1175 | |
1176 | if (!dev_priv->status_page_dmah) | |
1177 | return; | |
1178 | ||
91c8a326 | 1179 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1180 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1181 | } |
1182 | ||
0bc40be8 | 1183 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1184 | { |
57e88531 | 1185 | struct i915_vma *vma; |
f8a7fde4 | 1186 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1187 | |
57e88531 CW |
1188 | vma = fetch_and_zero(&engine->status_page.vma); |
1189 | if (!vma) | |
62fdfeaf | 1190 | return; |
62fdfeaf | 1191 | |
f8a7fde4 CW |
1192 | obj = vma->obj; |
1193 | ||
57e88531 | 1194 | i915_vma_unpin(vma); |
f8a7fde4 CW |
1195 | i915_vma_close(vma); |
1196 | ||
1197 | i915_gem_object_unpin_map(obj); | |
1198 | __i915_gem_object_release_unless_active(obj); | |
62fdfeaf EA |
1199 | } |
1200 | ||
0bc40be8 | 1201 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1202 | { |
57e88531 CW |
1203 | struct drm_i915_gem_object *obj; |
1204 | struct i915_vma *vma; | |
1205 | unsigned int flags; | |
920cf419 | 1206 | void *vaddr; |
57e88531 | 1207 | int ret; |
e4ffd173 | 1208 | |
f51455d4 | 1209 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); |
57e88531 CW |
1210 | if (IS_ERR(obj)) { |
1211 | DRM_ERROR("Failed to allocate status page\n"); | |
1212 | return PTR_ERR(obj); | |
1213 | } | |
62fdfeaf | 1214 | |
57e88531 CW |
1215 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1216 | if (ret) | |
1217 | goto err; | |
e3efda49 | 1218 | |
a01cb37a | 1219 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
57e88531 CW |
1220 | if (IS_ERR(vma)) { |
1221 | ret = PTR_ERR(vma); | |
1222 | goto err; | |
e3efda49 | 1223 | } |
62fdfeaf | 1224 | |
57e88531 CW |
1225 | flags = PIN_GLOBAL; |
1226 | if (!HAS_LLC(engine->i915)) | |
1227 | /* On g33, we cannot place HWS above 256MiB, so | |
1228 | * restrict its pinning to the low mappable arena. | |
1229 | * Though this restriction is not documented for | |
1230 | * gen4, gen5, or byt, they also behave similarly | |
1231 | * and hang if the HWS is placed at the top of the | |
1232 | * GTT. To generalise, it appears that all !llc | |
1233 | * platforms have issues with us placing the HWS | |
1234 | * above the mappable region (even though we never | |
1235 | * actualy map it). | |
1236 | */ | |
1237 | flags |= PIN_MAPPABLE; | |
1238 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1239 | if (ret) | |
1240 | goto err; | |
62fdfeaf | 1241 | |
920cf419 CW |
1242 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); |
1243 | if (IS_ERR(vaddr)) { | |
1244 | ret = PTR_ERR(vaddr); | |
1245 | goto err_unpin; | |
1246 | } | |
1247 | ||
57e88531 | 1248 | engine->status_page.vma = vma; |
bde13ebd | 1249 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
f51455d4 | 1250 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); |
62fdfeaf | 1251 | |
bde13ebd CW |
1252 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1253 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1254 | return 0; |
57e88531 | 1255 | |
920cf419 CW |
1256 | err_unpin: |
1257 | i915_vma_unpin(vma); | |
57e88531 CW |
1258 | err: |
1259 | i915_gem_object_put(obj); | |
1260 | return ret; | |
62fdfeaf EA |
1261 | } |
1262 | ||
0bc40be8 | 1263 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1264 | { |
c033666a | 1265 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1266 | |
1a5788bf CW |
1267 | GEM_BUG_ON(engine->id != RCS); |
1268 | ||
57e88531 CW |
1269 | dev_priv->status_page_dmah = |
1270 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1271 | if (!dev_priv->status_page_dmah) | |
1272 | return -ENOMEM; | |
6b8294a4 | 1273 | |
0bc40be8 TU |
1274 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1275 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1276 | |
1277 | return 0; | |
1278 | } | |
1279 | ||
d822bb18 CW |
1280 | int intel_ring_pin(struct intel_ring *ring, |
1281 | struct drm_i915_private *i915, | |
1282 | unsigned int offset_bias) | |
7ba717cf | 1283 | { |
d822bb18 | 1284 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1285 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1286 | unsigned int flags; |
8305216f | 1287 | void *addr; |
7ba717cf TD |
1288 | int ret; |
1289 | ||
57e88531 | 1290 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1291 | |
9d80841e | 1292 | |
d3ef1af6 DCS |
1293 | flags = PIN_GLOBAL; |
1294 | if (offset_bias) | |
1295 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1296 | if (vma->obj->stolen) |
57e88531 | 1297 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1298 | |
57e88531 | 1299 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1300 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1301 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1302 | else | |
1303 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1304 | if (unlikely(ret)) | |
def0c5f6 | 1305 | return ret; |
57e88531 | 1306 | } |
7ba717cf | 1307 | |
57e88531 CW |
1308 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1309 | if (unlikely(ret)) | |
1310 | return ret; | |
def0c5f6 | 1311 | |
9d80841e | 1312 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1313 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1314 | else | |
9d80841e | 1315 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1316 | if (IS_ERR(addr)) |
1317 | goto err; | |
7ba717cf | 1318 | |
32c04f16 | 1319 | ring->vaddr = addr; |
7ba717cf | 1320 | return 0; |
d2cad535 | 1321 | |
57e88531 CW |
1322 | err: |
1323 | i915_vma_unpin(vma); | |
1324 | return PTR_ERR(addr); | |
7ba717cf TD |
1325 | } |
1326 | ||
e6ba9992 CW |
1327 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1328 | { | |
1329 | GEM_BUG_ON(!list_empty(&ring->request_list)); | |
1330 | ring->tail = tail; | |
1331 | ring->head = tail; | |
1332 | ring->emit = tail; | |
1333 | intel_ring_update_space(ring); | |
1334 | } | |
1335 | ||
aad29fbb CW |
1336 | void intel_ring_unpin(struct intel_ring *ring) |
1337 | { | |
1338 | GEM_BUG_ON(!ring->vma); | |
1339 | GEM_BUG_ON(!ring->vaddr); | |
1340 | ||
e6ba9992 CW |
1341 | /* Discard any unused bytes beyond that submitted to hw. */ |
1342 | intel_ring_reset(ring, ring->tail); | |
1343 | ||
9d80841e | 1344 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1345 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1346 | else |
1347 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1348 | ring->vaddr = NULL; |
1349 | ||
57e88531 | 1350 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1351 | } |
1352 | ||
57e88531 CW |
1353 | static struct i915_vma * |
1354 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1355 | { |
05394f39 | 1356 | struct drm_i915_gem_object *obj; |
57e88531 | 1357 | struct i915_vma *vma; |
62fdfeaf | 1358 | |
187685cb | 1359 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1360 | if (!obj) |
2d6c4c84 | 1361 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1362 | if (IS_ERR(obj)) |
1363 | return ERR_CAST(obj); | |
8187a2b7 | 1364 | |
24f3a8cf AG |
1365 | /* mark ring buffers as read-only from GPU side by default */ |
1366 | obj->gt_ro = 1; | |
1367 | ||
a01cb37a | 1368 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1369 | if (IS_ERR(vma)) |
1370 | goto err; | |
1371 | ||
1372 | return vma; | |
e3efda49 | 1373 | |
57e88531 CW |
1374 | err: |
1375 | i915_gem_object_put(obj); | |
1376 | return vma; | |
e3efda49 CW |
1377 | } |
1378 | ||
7e37f889 CW |
1379 | struct intel_ring * |
1380 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1381 | { |
7e37f889 | 1382 | struct intel_ring *ring; |
57e88531 | 1383 | struct i915_vma *vma; |
01101fa7 | 1384 | |
8f942018 | 1385 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1386 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1387 | |
01101fa7 | 1388 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1389 | if (!ring) |
01101fa7 CW |
1390 | return ERR_PTR(-ENOMEM); |
1391 | ||
675d9ad7 CW |
1392 | INIT_LIST_HEAD(&ring->request_list); |
1393 | ||
01101fa7 CW |
1394 | ring->size = size; |
1395 | /* Workaround an erratum on the i830 which causes a hang if | |
1396 | * the TAIL pointer points to within the last 2 cachelines | |
1397 | * of the buffer. | |
1398 | */ | |
1399 | ring->effective_size = size; | |
2a307c2e | 1400 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1401 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1402 | ||
01101fa7 CW |
1403 | intel_ring_update_space(ring); |
1404 | ||
57e88531 CW |
1405 | vma = intel_ring_create_vma(engine->i915, size); |
1406 | if (IS_ERR(vma)) { | |
01101fa7 | 1407 | kfree(ring); |
57e88531 | 1408 | return ERR_CAST(vma); |
01101fa7 | 1409 | } |
57e88531 | 1410 | ring->vma = vma; |
01101fa7 CW |
1411 | |
1412 | return ring; | |
1413 | } | |
1414 | ||
1415 | void | |
7e37f889 | 1416 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1417 | { |
f8a7fde4 CW |
1418 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1419 | ||
1420 | i915_vma_close(ring->vma); | |
1421 | __i915_gem_object_release_unless_active(obj); | |
1422 | ||
01101fa7 CW |
1423 | kfree(ring); |
1424 | } | |
1425 | ||
72b72ae4 | 1426 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1427 | { |
1428 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1429 | int ret; | |
1430 | ||
1431 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
1432 | * We only want to do this on the first bind so that we do not stall | |
1433 | * on an active context (which by nature is already on the GPU). | |
1434 | */ | |
1435 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
1436 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
1437 | if (ret) | |
1438 | return ret; | |
1439 | } | |
1440 | ||
afeddf50 CW |
1441 | return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1442 | PIN_GLOBAL | PIN_HIGH); | |
e8a9c58f CW |
1443 | } |
1444 | ||
3204c343 CW |
1445 | static struct i915_vma * |
1446 | alloc_context_vma(struct intel_engine_cs *engine) | |
1447 | { | |
1448 | struct drm_i915_private *i915 = engine->i915; | |
1449 | struct drm_i915_gem_object *obj; | |
1450 | struct i915_vma *vma; | |
1451 | ||
63ffbcda | 1452 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1453 | if (IS_ERR(obj)) |
1454 | return ERR_CAST(obj); | |
1455 | ||
1456 | /* | |
1457 | * Try to make the context utilize L3 as well as LLC. | |
1458 | * | |
1459 | * On VLV we don't have L3 controls in the PTEs so we | |
1460 | * shouldn't touch the cache level, especially as that | |
1461 | * would make the object snooped which might have a | |
1462 | * negative performance impact. | |
1463 | * | |
1464 | * Snooping is required on non-llc platforms in execlist | |
1465 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1466 | * get snooping anyway regardless of cache_level. | |
1467 | * | |
1468 | * This is only applicable for Ivy Bridge devices since | |
1469 | * later platforms don't have L3 control bits in the PTE. | |
1470 | */ | |
1471 | if (IS_IVYBRIDGE(i915)) { | |
1472 | /* Ignore any error, regard it as a simple optimisation */ | |
1473 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1474 | } | |
1475 | ||
1476 | vma = i915_vma_instance(obj, &i915->ggtt.base, NULL); | |
1477 | if (IS_ERR(vma)) | |
1478 | i915_gem_object_put(obj); | |
1479 | ||
1480 | return vma; | |
1481 | } | |
1482 | ||
266a240b CW |
1483 | static struct intel_ring * |
1484 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1485 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1486 | { |
1487 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1488 | int ret; | |
1489 | ||
91c8a326 | 1490 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1491 | |
266a240b CW |
1492 | if (likely(ce->pin_count++)) |
1493 | goto out; | |
a533b4ba | 1494 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
0cb26a8e | 1495 | |
63ffbcda | 1496 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1497 | struct i915_vma *vma; |
1498 | ||
1499 | vma = alloc_context_vma(engine); | |
1500 | if (IS_ERR(vma)) { | |
1501 | ret = PTR_ERR(vma); | |
266a240b | 1502 | goto err; |
3204c343 CW |
1503 | } |
1504 | ||
1505 | ce->state = vma; | |
1506 | } | |
1507 | ||
0cb26a8e | 1508 | if (ce->state) { |
72b72ae4 | 1509 | ret = context_pin(ctx); |
e8a9c58f | 1510 | if (ret) |
266a240b | 1511 | goto err; |
5d4bac55 CW |
1512 | |
1513 | ce->state->obj->mm.dirty = true; | |
0cb26a8e CW |
1514 | } |
1515 | ||
c7c3c07d CW |
1516 | /* The kernel context is only used as a placeholder for flushing the |
1517 | * active context. It is never used for submitting user rendering and | |
1518 | * as such never requires the golden render context, and so we can skip | |
1519 | * emitting it when we switch to the kernel context. This is required | |
1520 | * as during eviction we cannot allocate and pin the renderstate in | |
1521 | * order to initialise the context. | |
1522 | */ | |
984ff29f | 1523 | if (i915_gem_context_is_kernel(ctx)) |
c7c3c07d CW |
1524 | ce->initialised = true; |
1525 | ||
9a6feaf0 | 1526 | i915_gem_context_get(ctx); |
0cb26a8e | 1527 | |
266a240b CW |
1528 | out: |
1529 | /* One ringbuffer to rule them all */ | |
1530 | return engine->buffer; | |
1531 | ||
1532 | err: | |
0cb26a8e | 1533 | ce->pin_count = 0; |
266a240b | 1534 | return ERR_PTR(ret); |
0cb26a8e CW |
1535 | } |
1536 | ||
e8a9c58f CW |
1537 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1538 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1539 | { |
1540 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1541 | ||
91c8a326 | 1542 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1543 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1544 | |
1545 | if (--ce->pin_count) | |
1546 | return; | |
1547 | ||
1548 | if (ce->state) | |
bf3783e5 | 1549 | i915_vma_unpin(ce->state); |
0cb26a8e | 1550 | |
9a6feaf0 | 1551 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1552 | } |
1553 | ||
acd27845 | 1554 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1555 | { |
32c04f16 | 1556 | struct intel_ring *ring; |
1a5788bf | 1557 | int err; |
bfc882b4 | 1558 | |
019bf277 TU |
1559 | intel_engine_setup_common(engine); |
1560 | ||
1a5788bf CW |
1561 | err = intel_engine_init_common(engine); |
1562 | if (err) | |
1563 | goto err; | |
e3efda49 | 1564 | |
1a5788bf CW |
1565 | if (HWS_NEEDS_PHYSICAL(engine->i915)) |
1566 | err = init_phys_status_page(engine); | |
1567 | else | |
1568 | err = init_status_page(engine); | |
1569 | if (err) | |
1570 | goto err; | |
e3efda49 | 1571 | |
d822bb18 CW |
1572 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1573 | if (IS_ERR(ring)) { | |
1a5788bf CW |
1574 | err = PTR_ERR(ring); |
1575 | goto err_hws; | |
d822bb18 CW |
1576 | } |
1577 | ||
d3ef1af6 | 1578 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1579 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1580 | if (err) | |
1581 | goto err_ring; | |
1582 | ||
1583 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1584 | engine->buffer = ring; |
62fdfeaf | 1585 | |
8ee14975 | 1586 | return 0; |
351e3db2 | 1587 | |
1a5788bf CW |
1588 | err_ring: |
1589 | intel_ring_free(ring); | |
1590 | err_hws: | |
1591 | if (HWS_NEEDS_PHYSICAL(engine->i915)) | |
1592 | cleanup_phys_status_page(engine); | |
1593 | else | |
1594 | cleanup_status_page(engine); | |
1595 | err: | |
1596 | intel_engine_cleanup_common(engine); | |
1597 | return err; | |
62fdfeaf EA |
1598 | } |
1599 | ||
7e37f889 | 1600 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1601 | { |
1a5788bf | 1602 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1603 | |
1a5788bf CW |
1604 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1605 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1606 | |
1a5788bf CW |
1607 | intel_ring_unpin(engine->buffer); |
1608 | intel_ring_free(engine->buffer); | |
78501eac | 1609 | |
0bc40be8 TU |
1610 | if (engine->cleanup) |
1611 | engine->cleanup(engine); | |
8d19215b | 1612 | |
1a5788bf | 1613 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 1614 | cleanup_phys_status_page(engine); |
1a5788bf | 1615 | else |
3177659a | 1616 | cleanup_status_page(engine); |
44e895a8 | 1617 | |
96a945aa | 1618 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1619 | |
3b3f1650 AG |
1620 | dev_priv->engine[engine->id] = NULL; |
1621 | kfree(engine); | |
62fdfeaf EA |
1622 | } |
1623 | ||
821ed7df CW |
1624 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1625 | { | |
1626 | struct intel_engine_cs *engine; | |
3b3f1650 | 1627 | enum intel_engine_id id; |
821ed7df | 1628 | |
e6ba9992 | 1629 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1630 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1631 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1632 | } |
1633 | ||
f73e7399 | 1634 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 1635 | { |
73dec95e | 1636 | u32 *cs; |
6310346e | 1637 | |
e8a9c58f CW |
1638 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1639 | ||
6310346e CW |
1640 | /* Flush enough space to reduce the likelihood of waiting after |
1641 | * we start building the request - in which case we will just | |
1642 | * have to repeat work. | |
1643 | */ | |
a0442461 | 1644 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1645 | |
73dec95e TU |
1646 | cs = intel_ring_begin(request, 0); |
1647 | if (IS_ERR(cs)) | |
1648 | return PTR_ERR(cs); | |
6310346e | 1649 | |
a0442461 | 1650 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1651 | return 0; |
9d773091 CW |
1652 | } |
1653 | ||
987046ad CW |
1654 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
1655 | { | |
7e37f889 | 1656 | struct intel_ring *ring = req->ring; |
987046ad | 1657 | struct drm_i915_gem_request *target; |
e95433c7 CW |
1658 | long timeout; |
1659 | ||
1660 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
987046ad | 1661 | |
1dae2dfb CW |
1662 | intel_ring_update_space(ring); |
1663 | if (ring->space >= bytes) | |
987046ad CW |
1664 | return 0; |
1665 | ||
1666 | /* | |
1667 | * Space is reserved in the ringbuffer for finalising the request, | |
1668 | * as that cannot be allowed to fail. During request finalisation, | |
1669 | * reserved_space is set to 0 to stop the overallocation and the | |
1670 | * assumption is that then we never need to wait (which has the | |
1671 | * risk of failing with EINTR). | |
1672 | * | |
1673 | * See also i915_gem_request_alloc() and i915_add_request(). | |
1674 | */ | |
0251a963 | 1675 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 1676 | |
675d9ad7 | 1677 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1678 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1679 | if (bytes <= __intel_ring_space(target->postfix, |
1680 | ring->emit, ring->size)) | |
987046ad | 1681 | break; |
79bbcc29 | 1682 | } |
29b1b415 | 1683 | |
675d9ad7 | 1684 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1685 | return -ENOSPC; |
1686 | ||
e95433c7 CW |
1687 | timeout = i915_wait_request(target, |
1688 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
1689 | MAX_SCHEDULE_TIMEOUT); | |
1690 | if (timeout < 0) | |
1691 | return timeout; | |
7da844c5 | 1692 | |
7da844c5 CW |
1693 | i915_gem_request_retire_upto(target); |
1694 | ||
1695 | intel_ring_update_space(ring); | |
1696 | GEM_BUG_ON(ring->space < bytes); | |
1697 | return 0; | |
29b1b415 JH |
1698 | } |
1699 | ||
73dec95e | 1700 | u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 1701 | { |
7e37f889 | 1702 | struct intel_ring *ring = req->ring; |
e6ba9992 CW |
1703 | int remain_actual = ring->size - ring->emit; |
1704 | int remain_usable = ring->effective_size - ring->emit; | |
987046ad CW |
1705 | int bytes = num_dwords * sizeof(u32); |
1706 | int total_bytes, wait_bytes; | |
79bbcc29 | 1707 | bool need_wrap = false; |
73dec95e | 1708 | u32 *cs; |
29b1b415 | 1709 | |
0251a963 | 1710 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 1711 | |
79bbcc29 JH |
1712 | if (unlikely(bytes > remain_usable)) { |
1713 | /* | |
1714 | * Not enough space for the basic request. So need to flush | |
1715 | * out the remainder and then wait for base + reserved. | |
1716 | */ | |
1717 | wait_bytes = remain_actual + total_bytes; | |
1718 | need_wrap = true; | |
987046ad CW |
1719 | } else if (unlikely(total_bytes > remain_usable)) { |
1720 | /* | |
1721 | * The base request will fit but the reserved space | |
1722 | * falls off the end. So we don't need an immediate wrap | |
1723 | * and only need to effectively wait for the reserved | |
1724 | * size space from the start of ringbuffer. | |
1725 | */ | |
0251a963 | 1726 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 1727 | } else { |
987046ad CW |
1728 | /* No wrapping required, just waiting. */ |
1729 | wait_bytes = total_bytes; | |
cbcc80df MK |
1730 | } |
1731 | ||
1dae2dfb | 1732 | if (wait_bytes > ring->space) { |
987046ad | 1733 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df | 1734 | if (unlikely(ret)) |
73dec95e | 1735 | return ERR_PTR(ret); |
cbcc80df MK |
1736 | } |
1737 | ||
987046ad | 1738 | if (unlikely(need_wrap)) { |
1dae2dfb | 1739 | GEM_BUG_ON(remain_actual > ring->space); |
e6ba9992 | 1740 | GEM_BUG_ON(ring->emit + remain_actual > ring->size); |
78501eac | 1741 | |
987046ad | 1742 | /* Fill the tail with MI_NOOP */ |
e6ba9992 CW |
1743 | memset(ring->vaddr + ring->emit, 0, remain_actual); |
1744 | ring->emit = 0; | |
1dae2dfb | 1745 | ring->space -= remain_actual; |
987046ad | 1746 | } |
304d695c | 1747 | |
e6ba9992 | 1748 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1749 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1750 | cs = ring->vaddr + ring->emit; |
01001863 | 1751 | GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes)); |
e6ba9992 | 1752 | ring->emit += bytes; |
1dae2dfb | 1753 | ring->space -= bytes; |
73dec95e TU |
1754 | |
1755 | return cs; | |
8187a2b7 | 1756 | } |
78501eac | 1757 | |
753b1ad4 | 1758 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 1759 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 1760 | { |
b5321f30 | 1761 | int num_dwords = |
e6ba9992 | 1762 | (req->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
73dec95e | 1763 | u32 *cs; |
753b1ad4 VS |
1764 | |
1765 | if (num_dwords == 0) | |
1766 | return 0; | |
1767 | ||
18393f63 | 1768 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
73dec95e TU |
1769 | cs = intel_ring_begin(req, num_dwords); |
1770 | if (IS_ERR(cs)) | |
1771 | return PTR_ERR(cs); | |
753b1ad4 VS |
1772 | |
1773 | while (num_dwords--) | |
73dec95e | 1774 | *cs++ = MI_NOOP; |
753b1ad4 | 1775 | |
73dec95e | 1776 | intel_ring_advance(req, cs); |
753b1ad4 VS |
1777 | |
1778 | return 0; | |
1779 | } | |
1780 | ||
c5efa1ad | 1781 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 1782 | { |
c5efa1ad | 1783 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1784 | |
76f8421f CW |
1785 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1786 | ||
881f47b6 | 1787 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1788 | |
1789 | /* Disable notification that the ring is IDLE. The GT | |
1790 | * will then assume that it is busy and bring it out of rc6. | |
1791 | */ | |
76f8421f CW |
1792 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1793 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1794 | |
1795 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1796 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1797 | |
12f55818 | 1798 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1799 | if (__intel_wait_for_register_fw(dev_priv, |
1800 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1801 | GEN6_BSD_SLEEP_INDICATOR, | |
1802 | 0, | |
1803 | 1000, 0, NULL)) | |
12f55818 | 1804 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1805 | |
12f55818 | 1806 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1807 | i9xx_submit_request(request); |
12f55818 CW |
1808 | |
1809 | /* Let the ring send IDLE messages to the GT again, | |
1810 | * and so let it sleep to conserve power when idle. | |
1811 | */ | |
76f8421f CW |
1812 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1813 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1814 | ||
1815 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1816 | } |
1817 | ||
7c9cf4e3 | 1818 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 1819 | { |
73dec95e | 1820 | u32 cmd, *cs; |
b72f3acb | 1821 | |
73dec95e TU |
1822 | cs = intel_ring_begin(req, 4); |
1823 | if (IS_ERR(cs)) | |
1824 | return PTR_ERR(cs); | |
b72f3acb | 1825 | |
71a77e07 | 1826 | cmd = MI_FLUSH_DW; |
c033666a | 1827 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1828 | cmd += 1; |
f0a1fb10 CW |
1829 | |
1830 | /* We always require a command barrier so that subsequent | |
1831 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1832 | * wrt the contents of the write cache being flushed to memory | |
1833 | * (and thus being coherent from the CPU). | |
1834 | */ | |
1835 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1836 | ||
9a289771 JB |
1837 | /* |
1838 | * Bspec vol 1c.5 - video engine command streamer: | |
1839 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1840 | * operation is complete. This bit is only valid when the | |
1841 | * Post-Sync Operation field is a value of 1h or 3h." | |
1842 | */ | |
7c9cf4e3 | 1843 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1844 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1845 | ||
73dec95e TU |
1846 | *cs++ = cmd; |
1847 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1848 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1849 | *cs++ = 0; /* upper addr */ |
1850 | *cs++ = 0; /* value */ | |
075b3bba | 1851 | } else { |
73dec95e TU |
1852 | *cs++ = 0; |
1853 | *cs++ = MI_NOOP; | |
075b3bba | 1854 | } |
73dec95e | 1855 | intel_ring_advance(req, cs); |
b72f3acb | 1856 | return 0; |
881f47b6 XH |
1857 | } |
1858 | ||
1c7a0623 | 1859 | static int |
803688ba CW |
1860 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
1861 | u64 offset, u32 len, | |
1862 | unsigned int dispatch_flags) | |
1c7a0623 | 1863 | { |
b5321f30 | 1864 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 1865 | !(dispatch_flags & I915_DISPATCH_SECURE); |
73dec95e | 1866 | u32 *cs; |
1c7a0623 | 1867 | |
73dec95e TU |
1868 | cs = intel_ring_begin(req, 4); |
1869 | if (IS_ERR(cs)) | |
1870 | return PTR_ERR(cs); | |
1c7a0623 BW |
1871 | |
1872 | /* FIXME(BDW): Address space and security selectors. */ | |
73dec95e TU |
1873 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & |
1874 | I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
1875 | *cs++ = lower_32_bits(offset); | |
1876 | *cs++ = upper_32_bits(offset); | |
1877 | *cs++ = MI_NOOP; | |
1878 | intel_ring_advance(req, cs); | |
1c7a0623 BW |
1879 | |
1880 | return 0; | |
1881 | } | |
1882 | ||
d7d4eedd | 1883 | static int |
803688ba CW |
1884 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
1885 | u64 offset, u32 len, | |
1886 | unsigned int dispatch_flags) | |
d7d4eedd | 1887 | { |
73dec95e | 1888 | u32 *cs; |
d7d4eedd | 1889 | |
73dec95e TU |
1890 | cs = intel_ring_begin(req, 2); |
1891 | if (IS_ERR(cs)) | |
1892 | return PTR_ERR(cs); | |
d7d4eedd | 1893 | |
73dec95e TU |
1894 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1895 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1896 | (dispatch_flags & I915_DISPATCH_RS ? | |
1897 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1898 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1899 | *cs++ = offset; |
1900 | intel_ring_advance(req, cs); | |
d7d4eedd CW |
1901 | |
1902 | return 0; | |
1903 | } | |
1904 | ||
881f47b6 | 1905 | static int |
803688ba CW |
1906 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
1907 | u64 offset, u32 len, | |
1908 | unsigned int dispatch_flags) | |
881f47b6 | 1909 | { |
73dec95e | 1910 | u32 *cs; |
ab6f8e32 | 1911 | |
73dec95e TU |
1912 | cs = intel_ring_begin(req, 2); |
1913 | if (IS_ERR(cs)) | |
1914 | return PTR_ERR(cs); | |
e1f99ce6 | 1915 | |
73dec95e TU |
1916 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1917 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1918 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1919 | *cs++ = offset; |
1920 | intel_ring_advance(req, cs); | |
ab6f8e32 | 1921 | |
0206e353 | 1922 | return 0; |
881f47b6 XH |
1923 | } |
1924 | ||
549f7365 CW |
1925 | /* Blitter support (SandyBridge+) */ |
1926 | ||
7c9cf4e3 | 1927 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 1928 | { |
73dec95e | 1929 | u32 cmd, *cs; |
b72f3acb | 1930 | |
73dec95e TU |
1931 | cs = intel_ring_begin(req, 4); |
1932 | if (IS_ERR(cs)) | |
1933 | return PTR_ERR(cs); | |
b72f3acb | 1934 | |
71a77e07 | 1935 | cmd = MI_FLUSH_DW; |
c033666a | 1936 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1937 | cmd += 1; |
f0a1fb10 CW |
1938 | |
1939 | /* We always require a command barrier so that subsequent | |
1940 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1941 | * wrt the contents of the write cache being flushed to memory | |
1942 | * (and thus being coherent from the CPU). | |
1943 | */ | |
1944 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1945 | ||
9a289771 JB |
1946 | /* |
1947 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1948 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1949 | * operation is complete. This bit is only valid when the | |
1950 | * Post-Sync Operation field is a value of 1h or 3h." | |
1951 | */ | |
7c9cf4e3 | 1952 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1953 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1954 | *cs++ = cmd; |
1955 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1956 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1957 | *cs++ = 0; /* upper addr */ |
1958 | *cs++ = 0; /* value */ | |
075b3bba | 1959 | } else { |
73dec95e TU |
1960 | *cs++ = 0; |
1961 | *cs++ = MI_NOOP; | |
075b3bba | 1962 | } |
73dec95e | 1963 | intel_ring_advance(req, cs); |
fd3da6c9 | 1964 | |
b72f3acb | 1965 | return 0; |
8d19215b ZN |
1966 | } |
1967 | ||
d9a64610 TU |
1968 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1969 | struct intel_engine_cs *engine) | |
1970 | { | |
db3d4019 | 1971 | struct drm_i915_gem_object *obj; |
1b9e6650 | 1972 | int ret, i; |
db3d4019 | 1973 | |
39df9190 | 1974 | if (!i915.semaphores) |
db3d4019 TU |
1975 | return; |
1976 | ||
51d545d0 CW |
1977 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
1978 | struct i915_vma *vma; | |
1979 | ||
f51455d4 | 1980 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
1981 | if (IS_ERR(obj)) |
1982 | goto err; | |
db3d4019 | 1983 | |
a01cb37a | 1984 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
1985 | if (IS_ERR(vma)) |
1986 | goto err_obj; | |
1987 | ||
1988 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1989 | if (ret) | |
1990 | goto err_obj; | |
1991 | ||
1992 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1993 | if (ret) | |
1994 | goto err_obj; | |
1995 | ||
1996 | dev_priv->semaphore = vma; | |
1997 | } | |
d9a64610 TU |
1998 | |
1999 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 2000 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 2001 | |
ad7bdb2b | 2002 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 2003 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
2004 | |
2005 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 2006 | u32 ring_offset; |
1b9e6650 TU |
2007 | |
2008 | if (i != engine->id) | |
2009 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2010 | else | |
2011 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2012 | ||
2013 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2014 | } | |
d9a64610 | 2015 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 2016 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 2017 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
2018 | |
2019 | /* | |
2020 | * The current semaphore is only applied on pre-gen8 | |
2021 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2022 | * platform. So the semaphore between RCS and VCS2 is | |
2023 | * initialized as INVALID. Gen8 will initialize the | |
2024 | * sema between VCS2 and RCS later. | |
2025 | */ | |
318f89ca | 2026 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
2027 | static const struct { |
2028 | u32 wait_mbox; | |
2029 | i915_reg_t mbox_reg; | |
318f89ca TU |
2030 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
2031 | [RCS_HW] = { | |
2032 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2033 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2034 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 2035 | }, |
318f89ca TU |
2036 | [VCS_HW] = { |
2037 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2038 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2039 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2040 | }, |
318f89ca TU |
2041 | [BCS_HW] = { |
2042 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2043 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2044 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2045 | }, |
318f89ca TU |
2046 | [VECS_HW] = { |
2047 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2048 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2049 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2050 | }, |
2051 | }; | |
2052 | u32 wait_mbox; | |
2053 | i915_reg_t mbox_reg; | |
2054 | ||
318f89ca | 2055 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2056 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2057 | mbox_reg = GEN6_NOSYNC; | |
2058 | } else { | |
318f89ca TU |
2059 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2060 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2061 | } |
2062 | ||
2063 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2064 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2065 | } | |
d9a64610 | 2066 | } |
51d545d0 CW |
2067 | |
2068 | return; | |
2069 | ||
2070 | err_obj: | |
2071 | i915_gem_object_put(obj); | |
2072 | err: | |
2073 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2074 | i915.semaphores = 0; | |
d9a64610 TU |
2075 | } |
2076 | ||
ed003078 CW |
2077 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2078 | struct intel_engine_cs *engine) | |
2079 | { | |
c78d6061 TU |
2080 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2081 | ||
ed003078 | 2082 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2083 | engine->irq_enable = gen8_irq_enable; |
2084 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2085 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2086 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2087 | engine->irq_enable = gen6_irq_enable; |
2088 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2089 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2090 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2091 | engine->irq_enable = gen5_irq_enable; |
2092 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2093 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2094 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2095 | engine->irq_enable = i9xx_irq_enable; |
2096 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2097 | } else { |
31bb59cc CW |
2098 | engine->irq_enable = i8xx_irq_enable; |
2099 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2100 | } |
2101 | } | |
2102 | ||
ff44ad51 CW |
2103 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2104 | { | |
2105 | engine->submit_request = i9xx_submit_request; | |
2106 | } | |
2107 | ||
2108 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2109 | { | |
2110 | engine->submit_request = gen6_bsd_submit_request; | |
2111 | } | |
2112 | ||
06a2fe22 TU |
2113 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2114 | struct intel_engine_cs *engine) | |
2115 | { | |
618e4ca7 CW |
2116 | intel_ring_init_irq(dev_priv, engine); |
2117 | intel_ring_init_semaphores(dev_priv, engine); | |
2118 | ||
1d8a1337 | 2119 | engine->init_hw = init_ring_common; |
821ed7df | 2120 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2121 | |
e8a9c58f CW |
2122 | engine->context_pin = intel_ring_context_pin; |
2123 | engine->context_unpin = intel_ring_context_unpin; | |
2124 | ||
f73e7399 CW |
2125 | engine->request_alloc = ring_request_alloc; |
2126 | ||
9b81d556 | 2127 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d CW |
2128 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
2129 | if (i915.semaphores) { | |
2130 | int num_rings; | |
2131 | ||
9b81d556 | 2132 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d CW |
2133 | |
2134 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2135 | if (INTEL_GEN(dev_priv) >= 8) { | |
2136 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2137 | } else { | |
2138 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2139 | if (num_rings & 1) | |
2140 | engine->emit_breadcrumb_sz++; | |
2141 | } | |
2142 | } | |
ff44ad51 CW |
2143 | |
2144 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 CW |
2145 | |
2146 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2147 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2148 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2149 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2150 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2151 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2152 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2153 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2154 | else |
803688ba | 2155 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2156 | } |
2157 | ||
8b3e2d36 | 2158 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2159 | { |
8b3e2d36 | 2160 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2161 | int ret; |
5c1143bb | 2162 | |
06a2fe22 TU |
2163 | intel_ring_default_vfuncs(dev_priv, engine); |
2164 | ||
61ff75ac CW |
2165 | if (HAS_L3_DPF(dev_priv)) |
2166 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2167 | |
c033666a | 2168 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2169 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2170 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2171 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2172 | engine->emit_flush = gen8_render_ring_flush; |
98f29e8d CW |
2173 | if (i915.semaphores) { |
2174 | int num_rings; | |
2175 | ||
e2f80391 | 2176 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d CW |
2177 | |
2178 | num_rings = | |
2179 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
6f9b850b | 2180 | engine->emit_breadcrumb_sz += num_rings * 8; |
98f29e8d | 2181 | } |
c033666a | 2182 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2183 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2184 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2185 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2186 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2187 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2188 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2189 | } else { |
c033666a | 2190 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2191 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2192 | else |
c7fe7d25 | 2193 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2194 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2195 | } |
707d9cf9 | 2196 | |
c033666a | 2197 | if (IS_HASWELL(dev_priv)) |
803688ba | 2198 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2199 | |
e2f80391 TU |
2200 | engine->init_hw = init_render_ring; |
2201 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2202 | |
acd27845 | 2203 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2204 | if (ret) |
2205 | return ret; | |
2206 | ||
f8973c21 | 2207 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2208 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2209 | if (ret) |
2210 | return ret; | |
2211 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2212 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2213 | if (ret) |
2214 | return ret; | |
2215 | } | |
2216 | ||
2217 | return 0; | |
5c1143bb XH |
2218 | } |
2219 | ||
8b3e2d36 | 2220 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2221 | { |
8b3e2d36 | 2222 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2223 | |
06a2fe22 TU |
2224 | intel_ring_default_vfuncs(dev_priv, engine); |
2225 | ||
c033666a | 2226 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2227 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2228 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2229 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2230 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2231 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2232 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2233 | } else { |
e2f80391 | 2234 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2235 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2236 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2237 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2238 | else |
e2f80391 | 2239 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2240 | } |
58fa3835 | 2241 | |
acd27845 | 2242 | return intel_init_ring_buffer(engine); |
5c1143bb | 2243 | } |
549f7365 | 2244 | |
8b3e2d36 | 2245 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2246 | { |
8b3e2d36 | 2247 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2248 | |
2249 | intel_ring_default_vfuncs(dev_priv, engine); | |
2250 | ||
c7fe7d25 | 2251 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2252 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2253 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2254 | |
acd27845 | 2255 | return intel_init_ring_buffer(engine); |
549f7365 | 2256 | } |
a7b9761d | 2257 | |
8b3e2d36 | 2258 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2259 | { |
8b3e2d36 | 2260 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2261 | |
2262 | intel_ring_default_vfuncs(dev_priv, engine); | |
2263 | ||
c7fe7d25 | 2264 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2265 | |
c78d6061 | 2266 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2267 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2268 | engine->irq_enable = hsw_vebox_irq_enable; |
2269 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2270 | } |
9a8a2213 | 2271 | |
acd27845 | 2272 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2273 | } |