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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
7c2fa7fa | 31 | |
760285e7 | 32 | #include <drm/drmP.h> |
760285e7 | 33 | #include <drm/i915_drm.h> |
7c2fa7fa CW |
34 | |
35 | #include "i915_drv.h" | |
36 | #include "i915_gem_render_state.h" | |
62fdfeaf | 37 | #include "i915_trace.h" |
881f47b6 | 38 | #include "intel_drv.h" |
7d3c425f | 39 | #include "intel_workarounds.h" |
62fdfeaf | 40 | |
a0442461 CW |
41 | /* Rough estimate of the typical request size, performing a flush, |
42 | * set-context and then emitting the batch. | |
43 | */ | |
44 | #define LEGACY_REQUEST_SIZE 200 | |
45 | ||
605d5b32 CW |
46 | static unsigned int __intel_ring_space(unsigned int head, |
47 | unsigned int tail, | |
48 | unsigned int size) | |
c7dca47b | 49 | { |
605d5b32 CW |
50 | /* |
51 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
52 | * same cacheline, the Head Pointer must not be greater than the Tail | |
53 | * Pointer." | |
54 | */ | |
55 | GEM_BUG_ON(!is_power_of_2(size)); | |
56 | return (head - tail - CACHELINE_BYTES) & (size - 1); | |
c7dca47b CW |
57 | } |
58 | ||
95aebcb2 | 59 | unsigned int intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 60 | { |
95aebcb2 CW |
61 | unsigned int space; |
62 | ||
63 | space = __intel_ring_space(ring->head, ring->emit, ring->size); | |
64 | ||
65 | ring->space = space; | |
66 | return space; | |
ebd0fd4b DG |
67 | } |
68 | ||
b72f3acb | 69 | static int |
e61e0f51 | 70 | gen2_render_ring_flush(struct i915_request *rq, u32 mode) |
46f0f8d1 | 71 | { |
73dec95e | 72 | u32 cmd, *cs; |
46f0f8d1 CW |
73 | |
74 | cmd = MI_FLUSH; | |
46f0f8d1 | 75 | |
7c9cf4e3 | 76 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
77 | cmd |= MI_READ_FLUSH; |
78 | ||
e61e0f51 | 79 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
80 | if (IS_ERR(cs)) |
81 | return PTR_ERR(cs); | |
46f0f8d1 | 82 | |
73dec95e TU |
83 | *cs++ = cmd; |
84 | *cs++ = MI_NOOP; | |
e61e0f51 | 85 | intel_ring_advance(rq, cs); |
46f0f8d1 CW |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static int | |
e61e0f51 | 91 | gen4_render_ring_flush(struct i915_request *rq, u32 mode) |
62fdfeaf | 92 | { |
73dec95e | 93 | u32 cmd, *cs; |
6f392d54 | 94 | |
36d527de CW |
95 | /* |
96 | * read/write caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
99 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
100 | * also flushed at 2d versus 3d pipeline switches. | |
101 | * | |
102 | * read-only caches: | |
103 | * | |
104 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
105 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
106 | * | |
107 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
108 | * | |
109 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
110 | * invalidated when MI_EXE_FLUSH is set. | |
111 | * | |
112 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
113 | * invalidated with every MI_FLUSH. | |
114 | * | |
115 | * TLBs: | |
116 | * | |
117 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
118 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
119 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
120 | * are flushed at any MI_FLUSH. | |
121 | */ | |
122 | ||
b5321f30 | 123 | cmd = MI_FLUSH; |
7c9cf4e3 | 124 | if (mode & EMIT_INVALIDATE) { |
36d527de | 125 | cmd |= MI_EXE_FLUSH; |
e61e0f51 | 126 | if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) |
b5321f30 CW |
127 | cmd |= MI_INVALIDATE_ISP; |
128 | } | |
70eac33e | 129 | |
e61e0f51 | 130 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
131 | if (IS_ERR(cs)) |
132 | return PTR_ERR(cs); | |
b72f3acb | 133 | |
73dec95e TU |
134 | *cs++ = cmd; |
135 | *cs++ = MI_NOOP; | |
e61e0f51 | 136 | intel_ring_advance(rq, cs); |
b72f3acb CW |
137 | |
138 | return 0; | |
8187a2b7 ZN |
139 | } |
140 | ||
179f4025 | 141 | /* |
8d315287 JB |
142 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
143 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
144 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
145 | * | |
146 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
147 | * produced by non-pipelined state commands), software needs to first | |
148 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
149 | * 0. | |
150 | * | |
151 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
152 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
153 | * | |
154 | * And the workaround for these two requires this workaround first: | |
155 | * | |
156 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
157 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
158 | * flushes. | |
159 | * | |
160 | * And this last workaround is tricky because of the requirements on | |
161 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
162 | * volume 2 part 1: | |
163 | * | |
164 | * "1 of the following must also be set: | |
165 | * - Render Target Cache Flush Enable ([12] of DW1) | |
166 | * - Depth Cache Flush Enable ([0] of DW1) | |
167 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
168 | * - Depth Stall ([13] of DW1) | |
169 | * - Post-Sync Operation ([13] of DW1) | |
170 | * - Notify Enable ([8] of DW1)" | |
171 | * | |
172 | * The cache flushes require the workaround flush that triggered this | |
173 | * one, so we can't use it. Depth stall would trigger the same. | |
174 | * Post-sync nonzero is what triggered this second workaround, so we | |
175 | * can't use that one either. Notify enable is IRQs, which aren't | |
176 | * really our business. That leaves only stall at scoreboard. | |
177 | */ | |
178 | static int | |
e61e0f51 | 179 | intel_emit_post_sync_nonzero_flush(struct i915_request *rq) |
8d315287 | 180 | { |
b5321f30 | 181 | u32 scratch_addr = |
e61e0f51 | 182 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
183 | u32 *cs; |
184 | ||
e61e0f51 | 185 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
186 | if (IS_ERR(cs)) |
187 | return PTR_ERR(cs); | |
188 | ||
189 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
190 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
191 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
192 | *cs++ = 0; /* low dword */ | |
193 | *cs++ = 0; /* high dword */ | |
194 | *cs++ = MI_NOOP; | |
e61e0f51 | 195 | intel_ring_advance(rq, cs); |
73dec95e | 196 | |
e61e0f51 | 197 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
198 | if (IS_ERR(cs)) |
199 | return PTR_ERR(cs); | |
200 | ||
201 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
202 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
203 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
204 | *cs++ = 0; | |
205 | *cs++ = 0; | |
206 | *cs++ = MI_NOOP; | |
e61e0f51 | 207 | intel_ring_advance(rq, cs); |
8d315287 JB |
208 | |
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
e61e0f51 | 213 | gen6_render_ring_flush(struct i915_request *rq, u32 mode) |
8d315287 | 214 | { |
b5321f30 | 215 | u32 scratch_addr = |
e61e0f51 | 216 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 217 | u32 *cs, flags = 0; |
8d315287 JB |
218 | int ret; |
219 | ||
b3111509 | 220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
e61e0f51 | 221 | ret = intel_emit_post_sync_nonzero_flush(rq); |
b3111509 PZ |
222 | if (ret) |
223 | return ret; | |
224 | ||
8d315287 JB |
225 | /* Just flush everything. Experiments have shown that reducing the |
226 | * number of bits based on the write domains has little performance | |
227 | * impact. | |
228 | */ | |
7c9cf4e3 | 229 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
231 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
232 | /* | |
233 | * Ensure that any following seqno writes only happen | |
234 | * when the render cache is indeed flushed. | |
235 | */ | |
97f209bc | 236 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 237 | } |
7c9cf4e3 | 238 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
239 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
240 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
244 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
245 | /* | |
246 | * TLB invalidate requires a post-sync write. | |
247 | */ | |
3ac78313 | 248 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 249 | } |
8d315287 | 250 | |
e61e0f51 | 251 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
252 | if (IS_ERR(cs)) |
253 | return PTR_ERR(cs); | |
8d315287 | 254 | |
73dec95e TU |
255 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
256 | *cs++ = flags; | |
257 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
258 | *cs++ = 0; | |
e61e0f51 | 259 | intel_ring_advance(rq, cs); |
8d315287 JB |
260 | |
261 | return 0; | |
262 | } | |
263 | ||
f3987631 | 264 | static int |
e61e0f51 | 265 | gen7_render_ring_cs_stall_wa(struct i915_request *rq) |
f3987631 | 266 | { |
73dec95e | 267 | u32 *cs; |
f3987631 | 268 | |
e61e0f51 | 269 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
270 | if (IS_ERR(cs)) |
271 | return PTR_ERR(cs); | |
f3987631 | 272 | |
73dec95e TU |
273 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
274 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
275 | *cs++ = 0; | |
276 | *cs++ = 0; | |
e61e0f51 | 277 | intel_ring_advance(rq, cs); |
f3987631 PZ |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
4772eaeb | 282 | static int |
e61e0f51 | 283 | gen7_render_ring_flush(struct i915_request *rq, u32 mode) |
4772eaeb | 284 | { |
b5321f30 | 285 | u32 scratch_addr = |
e61e0f51 | 286 | i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 287 | u32 *cs, flags = 0; |
4772eaeb | 288 | |
f3987631 PZ |
289 | /* |
290 | * Ensure that any following seqno writes only happen when the render | |
291 | * cache is indeed flushed. | |
292 | * | |
293 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
294 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
295 | * don't try to be clever and just set it unconditionally. | |
296 | */ | |
297 | flags |= PIPE_CONTROL_CS_STALL; | |
298 | ||
4772eaeb PZ |
299 | /* Just flush everything. Experiments have shown that reducing the |
300 | * number of bits based on the write domains has little performance | |
301 | * impact. | |
302 | */ | |
7c9cf4e3 | 303 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
304 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
305 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 306 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 307 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 308 | } |
7c9cf4e3 | 309 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
310 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
311 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
312 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
313 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
314 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
315 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 316 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
317 | /* |
318 | * TLB invalidate requires a post-sync write. | |
319 | */ | |
320 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 321 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 322 | |
add284a3 CW |
323 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
324 | ||
f3987631 PZ |
325 | /* Workaround: we must issue a pipe_control with CS-stall bit |
326 | * set before a pipe_control command that has the state cache | |
327 | * invalidate bit set. */ | |
e61e0f51 | 328 | gen7_render_ring_cs_stall_wa(rq); |
4772eaeb PZ |
329 | } |
330 | ||
e61e0f51 | 331 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
332 | if (IS_ERR(cs)) |
333 | return PTR_ERR(cs); | |
4772eaeb | 334 | |
73dec95e TU |
335 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
336 | *cs++ = flags; | |
337 | *cs++ = scratch_addr; | |
338 | *cs++ = 0; | |
e61e0f51 | 339 | intel_ring_advance(rq, cs); |
4772eaeb PZ |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
0bc40be8 | 344 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 345 | { |
c033666a | 346 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
347 | u32 addr; |
348 | ||
349 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 350 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
351 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
352 | I915_WRITE(HWS_PGA, addr); | |
353 | } | |
354 | ||
0bc40be8 | 355 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 356 | { |
c033666a | 357 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 358 | i915_reg_t mmio; |
af75f269 DL |
359 | |
360 | /* The ring status page addresses are no longer next to the rest of | |
361 | * the ring registers as of gen7. | |
362 | */ | |
c033666a | 363 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 364 | switch (engine->id) { |
a2d3d265 MT |
365 | /* |
366 | * No more rings exist on Gen7. Default case is only to shut up | |
367 | * gcc switch check warning. | |
368 | */ | |
369 | default: | |
370 | GEM_BUG_ON(engine->id); | |
af75f269 DL |
371 | case RCS: |
372 | mmio = RENDER_HWS_PGA_GEN7; | |
373 | break; | |
374 | case BCS: | |
375 | mmio = BLT_HWS_PGA_GEN7; | |
376 | break; | |
af75f269 DL |
377 | case VCS: |
378 | mmio = BSD_HWS_PGA_GEN7; | |
379 | break; | |
380 | case VECS: | |
381 | mmio = VEBOX_HWS_PGA_GEN7; | |
382 | break; | |
383 | } | |
c033666a | 384 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 385 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 | 386 | } else { |
0bc40be8 | 387 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
388 | } |
389 | ||
c5498089 VS |
390 | if (INTEL_GEN(dev_priv) >= 6) |
391 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
392 | ||
57e88531 | 393 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
394 | POSTING_READ(mmio); |
395 | ||
79e6770c | 396 | /* Flush the TLB for this page */ |
ac657f64 | 397 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 398 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
399 | |
400 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 401 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
402 | |
403 | I915_WRITE(reg, | |
404 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
405 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
406 | if (intel_wait_for_register(dev_priv, |
407 | reg, INSTPM_SYNC_FLUSH, 0, | |
408 | 1000)) | |
af75f269 | 409 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 410 | engine->name); |
af75f269 DL |
411 | } |
412 | } | |
413 | ||
0bc40be8 | 414 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 415 | { |
c033666a | 416 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 417 | |
21a2c58a | 418 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 419 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
420 | if (intel_wait_for_register(dev_priv, |
421 | RING_MI_MODE(engine->mmio_base), | |
422 | MODE_IDLE, | |
423 | MODE_IDLE, | |
424 | 1000)) { | |
0bc40be8 TU |
425 | DRM_ERROR("%s : timed out trying to stop ring\n", |
426 | engine->name); | |
9bec9b13 CW |
427 | /* Sometimes we observe that the idle flag is not |
428 | * set even though the ring is empty. So double | |
429 | * check before giving up. | |
430 | */ | |
0bc40be8 | 431 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 432 | return false; |
9991ae78 CW |
433 | } |
434 | } | |
b7884eb4 | 435 | |
11caf551 CW |
436 | I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); |
437 | ||
0bc40be8 | 438 | I915_WRITE_HEAD(engine, 0); |
c5efa1ad | 439 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 440 | |
11caf551 CW |
441 | /* The ring must be empty before it is disabled */ |
442 | I915_WRITE_CTL(engine, 0); | |
443 | ||
0bc40be8 | 444 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 445 | } |
8187a2b7 | 446 | |
0bc40be8 | 447 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 448 | { |
c033666a | 449 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 450 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
451 | int ret = 0; |
452 | ||
59bad947 | 453 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 454 | |
0bc40be8 | 455 | if (!stop_ring(engine)) { |
9991ae78 | 456 | /* G45 ring initialization often fails to reset head to zero */ |
8177e112 CW |
457 | DRM_DEBUG_DRIVER("%s head not reset to zero " |
458 | "ctl %08x head %08x tail %08x start %08x\n", | |
459 | engine->name, | |
460 | I915_READ_CTL(engine), | |
461 | I915_READ_HEAD(engine), | |
462 | I915_READ_TAIL(engine), | |
463 | I915_READ_START(engine)); | |
8187a2b7 | 464 | |
0bc40be8 | 465 | if (!stop_ring(engine)) { |
6fd0d56e CW |
466 | DRM_ERROR("failed to set %s head to zero " |
467 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
468 | engine->name, |
469 | I915_READ_CTL(engine), | |
470 | I915_READ_HEAD(engine), | |
471 | I915_READ_TAIL(engine), | |
472 | I915_READ_START(engine)); | |
9991ae78 CW |
473 | ret = -EIO; |
474 | goto out; | |
6fd0d56e | 475 | } |
8187a2b7 ZN |
476 | } |
477 | ||
3177659a | 478 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 479 | ring_setup_phys_status_page(engine); |
3177659a CS |
480 | else |
481 | intel_ring_setup_status_page(engine); | |
9991ae78 | 482 | |
ad07dfcd | 483 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 484 | |
ece4a17d | 485 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 486 | I915_READ_HEAD(engine); |
ece4a17d | 487 | |
0d8957c8 DV |
488 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
489 | * registers with the above sequence (the readback of the HEAD registers | |
490 | * also enforces ordering), otherwise the hw might lose the new ring | |
491 | * register values. */ | |
bde13ebd | 492 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
493 | |
494 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 495 | if (I915_READ_HEAD(engine)) |
8177e112 CW |
496 | DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n", |
497 | engine->name, I915_READ_HEAD(engine)); | |
821ed7df | 498 | |
41d37680 CW |
499 | /* Check that the ring offsets point within the ring! */ |
500 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head)); | |
501 | GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail)); | |
502 | ||
821ed7df CW |
503 | intel_ring_update_space(ring); |
504 | I915_WRITE_HEAD(engine, ring->head); | |
505 | I915_WRITE_TAIL(engine, ring->tail); | |
506 | (void)I915_READ_TAIL(engine); | |
95468892 | 507 | |
62ae14b1 | 508 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 509 | |
8187a2b7 | 510 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
511 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
512 | RING_VALID, RING_VALID, | |
513 | 50)) { | |
e74cfed5 | 514 | DRM_ERROR("%s initialization failed " |
821ed7df | 515 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
516 | engine->name, |
517 | I915_READ_CTL(engine), | |
518 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
519 | I915_READ_HEAD(engine), ring->head, |
520 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 521 | I915_READ_START(engine), |
bde13ebd | 522 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
523 | ret = -EIO; |
524 | goto out; | |
8187a2b7 ZN |
525 | } |
526 | ||
fc0768ce | 527 | intel_engine_init_hangcheck(engine); |
50f018df | 528 | |
7836cd02 CW |
529 | if (INTEL_GEN(dev_priv) > 2) |
530 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
531 | ||
b7884eb4 | 532 | out: |
59bad947 | 533 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
534 | |
535 | return ret; | |
8187a2b7 ZN |
536 | } |
537 | ||
5adfb772 | 538 | static struct i915_request *reset_prepare(struct intel_engine_cs *engine) |
821ed7df | 539 | { |
3f6e9822 CW |
540 | intel_engine_stop_cs(engine); |
541 | ||
5adfb772 CW |
542 | if (engine->irq_seqno_barrier) |
543 | engine->irq_seqno_barrier(engine); | |
544 | ||
545 | return i915_gem_find_active_request(engine); | |
546 | } | |
547 | ||
b3ee09a4 | 548 | static void skip_request(struct i915_request *rq) |
5adfb772 | 549 | { |
b3ee09a4 CW |
550 | void *vaddr = rq->ring->vaddr; |
551 | u32 head; | |
552 | ||
553 | head = rq->infix; | |
554 | if (rq->postfix < head) { | |
555 | memset32(vaddr + head, MI_NOOP, | |
556 | (rq->ring->size - head) / sizeof(u32)); | |
557 | head = 0; | |
558 | } | |
559 | memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32)); | |
560 | } | |
561 | ||
562 | static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq) | |
563 | { | |
564 | GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0); | |
5adfb772 | 565 | |
67e64564 CW |
566 | /* |
567 | * RC6 must be prevented until the reset is complete and the engine | |
568 | * reinitialised. If it occurs in the middle of this sequence, the | |
569 | * state written to/loaded from the power context is ill-defined (e.g. | |
570 | * the PP_BASE_DIR may be lost). | |
571 | */ | |
572 | assert_forcewakes_active(engine->i915, FORCEWAKE_ALL); | |
573 | ||
574 | /* | |
575 | * Try to restore the logical GPU state to match the continuation | |
c0dcb203 CW |
576 | * of the request queue. If we skip the context/PD restore, then |
577 | * the next request may try to execute assuming that its context | |
578 | * is valid and loaded on the GPU and so may try to access invalid | |
579 | * memory, prompting repeated GPU hangs. | |
580 | * | |
581 | * If the request was guilty, we still restore the logical state | |
582 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
583 | * but skip over the hung batch. | |
584 | * | |
585 | * If the request was innocent, we try to replay the request with | |
586 | * the restored context. | |
587 | */ | |
b3ee09a4 | 588 | if (rq) { |
c0dcb203 | 589 | /* If the rq hung, jump to its breadcrumb and skip the batch */ |
b3ee09a4 CW |
590 | rq->ring->head = intel_ring_wrap(rq->ring, rq->head); |
591 | if (rq->fence.error == -EIO) | |
592 | skip_request(rq); | |
c0dcb203 | 593 | } |
821ed7df CW |
594 | } |
595 | ||
5adfb772 CW |
596 | static void reset_finish(struct intel_engine_cs *engine) |
597 | { | |
598 | } | |
599 | ||
e61e0f51 | 600 | static int intel_rcs_ctx_init(struct i915_request *rq) |
8f0e2b9d DV |
601 | { |
602 | int ret; | |
603 | ||
59b449d5 | 604 | ret = intel_ctx_workarounds_emit(rq); |
8f0e2b9d DV |
605 | if (ret != 0) |
606 | return ret; | |
607 | ||
e61e0f51 | 608 | ret = i915_gem_render_state_emit(rq); |
8f0e2b9d | 609 | if (ret) |
e26e1b97 | 610 | return ret; |
8f0e2b9d | 611 | |
e26e1b97 | 612 | return 0; |
8f0e2b9d DV |
613 | } |
614 | ||
0bc40be8 | 615 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 616 | { |
c033666a | 617 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 618 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
619 | if (ret) |
620 | return ret; | |
a69ffdbf | 621 | |
f4ecfbfc | 622 | intel_whitelist_workarounds_apply(engine); |
59b449d5 | 623 | |
61a563a2 | 624 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 625 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 626 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
627 | |
628 | /* We need to disable the AsyncFlip performance optimisations in order | |
629 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
630 | * programmed to '1' on all products. | |
8693a824 | 631 | * |
2441f877 | 632 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 633 | */ |
ac657f64 | 634 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
635 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
636 | ||
f05bb0c7 | 637 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 638 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 639 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 640 | I915_WRITE(GFX_MODE, |
aa83e30d | 641 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 642 | |
01fa0302 | 643 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 644 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 645 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 646 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 647 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 648 | |
c033666a | 649 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
650 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
651 | * "If this bit is set, STCunit will have LRA as replacement | |
652 | * policy. [...] This bit must be reset. LRA replacement | |
653 | * policy is not supported." | |
654 | */ | |
655 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 656 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
657 | } |
658 | ||
ac657f64 | 659 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 660 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 661 | |
c56b89f1 | 662 | if (INTEL_GEN(dev_priv) >= 6) |
035ea405 | 663 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
15b9f80e | 664 | |
59b449d5 | 665 | return 0; |
8187a2b7 ZN |
666 | } |
667 | ||
e61e0f51 | 668 | static u32 *gen6_signal(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 669 | { |
e61e0f51 | 670 | struct drm_i915_private *dev_priv = rq->i915; |
318f89ca | 671 | struct intel_engine_cs *engine; |
3b3f1650 | 672 | enum intel_engine_id id; |
caddfe71 | 673 | int num_rings = 0; |
024a43e1 | 674 | |
3b3f1650 | 675 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
676 | i915_reg_t mbox_reg; |
677 | ||
678 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
679 | continue; | |
f0f59a00 | 680 | |
e61e0f51 | 681 | mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 682 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
683 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
684 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
e61e0f51 | 685 | *cs++ = rq->global_seqno; |
caddfe71 | 686 | num_rings++; |
78325f2d BW |
687 | } |
688 | } | |
caddfe71 | 689 | if (num_rings & 1) |
73dec95e | 690 | *cs++ = MI_NOOP; |
024a43e1 | 691 | |
73dec95e | 692 | return cs; |
1ec14ad3 CW |
693 | } |
694 | ||
27a5f61b CW |
695 | static void cancel_requests(struct intel_engine_cs *engine) |
696 | { | |
e61e0f51 | 697 | struct i915_request *request; |
27a5f61b CW |
698 | unsigned long flags; |
699 | ||
a89d1f92 | 700 | spin_lock_irqsave(&engine->timeline.lock, flags); |
27a5f61b CW |
701 | |
702 | /* Mark all submitted requests as skipped. */ | |
a89d1f92 | 703 | list_for_each_entry(request, &engine->timeline.requests, link) { |
27a5f61b | 704 | GEM_BUG_ON(!request->global_seqno); |
e61e0f51 | 705 | if (!i915_request_completed(request)) |
27a5f61b CW |
706 | dma_fence_set_error(&request->fence, -EIO); |
707 | } | |
708 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
709 | ||
a89d1f92 | 710 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
27a5f61b CW |
711 | } |
712 | ||
e61e0f51 | 713 | static void i9xx_submit_request(struct i915_request *request) |
b0411e7d CW |
714 | { |
715 | struct drm_i915_private *dev_priv = request->i915; | |
716 | ||
e61e0f51 | 717 | i915_request_submit(request); |
d55ac5bf | 718 | |
e6ba9992 CW |
719 | I915_WRITE_TAIL(request->engine, |
720 | intel_ring_set_tail(request->ring, request->tail)); | |
b0411e7d CW |
721 | } |
722 | ||
e61e0f51 | 723 | static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
1ec14ad3 | 724 | { |
73dec95e TU |
725 | *cs++ = MI_STORE_DWORD_INDEX; |
726 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
e61e0f51 | 727 | *cs++ = rq->global_seqno; |
73dec95e | 728 | *cs++ = MI_USER_INTERRUPT; |
1ec14ad3 | 729 | |
e61e0f51 CW |
730 | rq->tail = intel_ring_offset(rq, cs); |
731 | assert_ring_tail_valid(rq->ring, rq->tail); | |
1ec14ad3 CW |
732 | } |
733 | ||
98f29e8d CW |
734 | static const int i9xx_emit_breadcrumb_sz = 4; |
735 | ||
e61e0f51 | 736 | static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs) |
b0411e7d | 737 | { |
e61e0f51 | 738 | return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs)); |
b0411e7d CW |
739 | } |
740 | ||
c8c99b0f | 741 | static int |
e61e0f51 | 742 | gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal) |
1ec14ad3 | 743 | { |
c8c99b0f BW |
744 | u32 dw1 = MI_SEMAPHORE_MBOX | |
745 | MI_SEMAPHORE_COMPARE | | |
746 | MI_SEMAPHORE_REGISTER; | |
e61e0f51 | 747 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id]; |
73dec95e | 748 | u32 *cs; |
1ec14ad3 | 749 | |
ebc348b2 | 750 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 751 | |
e61e0f51 | 752 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
753 | if (IS_ERR(cs)) |
754 | return PTR_ERR(cs); | |
1ec14ad3 | 755 | |
73dec95e | 756 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
757 | /* Throughout all of the GEM code, seqno passed implies our current |
758 | * seqno is >= the last seqno executed. However for hardware the | |
759 | * comparison is strictly greater than. | |
760 | */ | |
73dec95e TU |
761 | *cs++ = signal->global_seqno - 1; |
762 | *cs++ = 0; | |
763 | *cs++ = MI_NOOP; | |
e61e0f51 | 764 | intel_ring_advance(rq, cs); |
1ec14ad3 CW |
765 | |
766 | return 0; | |
767 | } | |
768 | ||
f8973c21 | 769 | static void |
38a0f2db | 770 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 771 | { |
f8973c21 CW |
772 | /* MI_STORE are internally buffered by the GPU and not flushed |
773 | * either by MI_FLUSH or SyncFlush or any other combination of | |
774 | * MI commands. | |
c6df541c | 775 | * |
f8973c21 CW |
776 | * "Only the submission of the store operation is guaranteed. |
777 | * The write result will be complete (coherent) some time later | |
778 | * (this is practically a finite period but there is no guaranteed | |
779 | * latency)." | |
780 | * | |
781 | * Empirically, we observe that we need a delay of at least 75us to | |
782 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 783 | */ |
f8973c21 | 784 | usleep_range(125, 250); |
c6df541c CW |
785 | } |
786 | ||
c04e0f3b CW |
787 | static void |
788 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 789 | { |
c033666a | 790 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 791 | |
4cd53c0c DV |
792 | /* Workaround to force correct ordering between irq and seqno writes on |
793 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
794 | * ACTHD) before reading the status page. |
795 | * | |
796 | * Note that this effectively stalls the read by the time it takes to | |
797 | * do a memory transaction, which more or less ensures that the write | |
798 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
799 | * Alternatively we could delay the interrupt from the CS ring to give | |
800 | * the write time to land, but that would incur a delay after every | |
801 | * batch i.e. much more frequent than a delay when waiting for the | |
802 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
803 | * |
804 | * Also note that to prevent whole machine hangs on gen7, we have to | |
805 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 806 | */ |
bcbdb6d0 | 807 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 808 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 809 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
810 | } |
811 | ||
31bb59cc CW |
812 | static void |
813 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 814 | { |
31bb59cc | 815 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
816 | } |
817 | ||
818 | static void | |
31bb59cc | 819 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 820 | { |
31bb59cc | 821 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
822 | } |
823 | ||
31bb59cc CW |
824 | static void |
825 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 826 | { |
c033666a | 827 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 828 | |
31bb59cc CW |
829 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
830 | I915_WRITE(IMR, dev_priv->irq_mask); | |
831 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
832 | } |
833 | ||
8187a2b7 | 834 | static void |
31bb59cc | 835 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 836 | { |
c033666a | 837 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 838 | |
31bb59cc CW |
839 | dev_priv->irq_mask |= engine->irq_enable_mask; |
840 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
841 | } |
842 | ||
31bb59cc CW |
843 | static void |
844 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 845 | { |
c033666a | 846 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 847 | |
31bb59cc CW |
848 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
849 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
850 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
851 | } |
852 | ||
853 | static void | |
31bb59cc | 854 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 855 | { |
c033666a | 856 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 857 | |
31bb59cc CW |
858 | dev_priv->irq_mask |= engine->irq_enable_mask; |
859 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
860 | } |
861 | ||
b72f3acb | 862 | static int |
e61e0f51 | 863 | bsd_ring_flush(struct i915_request *rq, u32 mode) |
d1b851fc | 864 | { |
73dec95e | 865 | u32 *cs; |
b72f3acb | 866 | |
e61e0f51 | 867 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
868 | if (IS_ERR(cs)) |
869 | return PTR_ERR(cs); | |
b72f3acb | 870 | |
73dec95e TU |
871 | *cs++ = MI_FLUSH; |
872 | *cs++ = MI_NOOP; | |
e61e0f51 | 873 | intel_ring_advance(rq, cs); |
b72f3acb | 874 | return 0; |
d1b851fc ZN |
875 | } |
876 | ||
31bb59cc CW |
877 | static void |
878 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 879 | { |
c033666a | 880 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 881 | |
61ff75ac CW |
882 | I915_WRITE_IMR(engine, |
883 | ~(engine->irq_enable_mask | | |
884 | engine->irq_keep_mask)); | |
31bb59cc | 885 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
886 | } |
887 | ||
888 | static void | |
31bb59cc | 889 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 890 | { |
c033666a | 891 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 892 | |
61ff75ac | 893 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 894 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
895 | } |
896 | ||
31bb59cc CW |
897 | static void |
898 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 899 | { |
c033666a | 900 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 901 | |
31bb59cc | 902 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 903 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
904 | } |
905 | ||
906 | static void | |
31bb59cc | 907 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 908 | { |
c033666a | 909 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 910 | |
31bb59cc | 911 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 912 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
913 | } |
914 | ||
d1b851fc | 915 | static int |
e61e0f51 | 916 | i965_emit_bb_start(struct i915_request *rq, |
803688ba CW |
917 | u64 offset, u32 length, |
918 | unsigned int dispatch_flags) | |
d1b851fc | 919 | { |
73dec95e | 920 | u32 *cs; |
78501eac | 921 | |
e61e0f51 | 922 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
923 | if (IS_ERR(cs)) |
924 | return PTR_ERR(cs); | |
e1f99ce6 | 925 | |
73dec95e TU |
926 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
927 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
928 | *cs++ = offset; | |
e61e0f51 | 929 | intel_ring_advance(rq, cs); |
78501eac | 930 | |
d1b851fc ZN |
931 | return 0; |
932 | } | |
933 | ||
b45305fc DV |
934 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
935 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
936 | #define I830_TLB_ENTRIES (2) |
937 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 938 | static int |
e61e0f51 | 939 | i830_emit_bb_start(struct i915_request *rq, |
803688ba CW |
940 | u64 offset, u32 len, |
941 | unsigned int dispatch_flags) | |
62fdfeaf | 942 | { |
e61e0f51 | 943 | u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); |
62fdfeaf | 944 | |
e61e0f51 | 945 | cs = intel_ring_begin(rq, 6); |
73dec95e TU |
946 | if (IS_ERR(cs)) |
947 | return PTR_ERR(cs); | |
62fdfeaf | 948 | |
c4d69da1 | 949 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
950 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
951 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
952 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
953 | *cs++ = cs_offset; | |
954 | *cs++ = 0xdeadbeef; | |
955 | *cs++ = MI_NOOP; | |
e61e0f51 | 956 | intel_ring_advance(rq, cs); |
b45305fc | 957 | |
8e004efc | 958 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
959 | if (len > I830_BATCH_LIMIT) |
960 | return -ENOSPC; | |
961 | ||
e61e0f51 | 962 | cs = intel_ring_begin(rq, 6 + 2); |
73dec95e TU |
963 | if (IS_ERR(cs)) |
964 | return PTR_ERR(cs); | |
c4d69da1 CW |
965 | |
966 | /* Blit the batch (which has now all relocs applied) to the | |
967 | * stable batch scratch bo area (so that the CS never | |
968 | * stumbles over its tlb invalidation bug) ... | |
969 | */ | |
73dec95e TU |
970 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
971 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
972 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
973 | *cs++ = cs_offset; | |
974 | *cs++ = 4096; | |
975 | *cs++ = offset; | |
976 | ||
977 | *cs++ = MI_FLUSH; | |
978 | *cs++ = MI_NOOP; | |
e61e0f51 | 979 | intel_ring_advance(rq, cs); |
b45305fc DV |
980 | |
981 | /* ... and execute it. */ | |
c4d69da1 | 982 | offset = cs_offset; |
b45305fc | 983 | } |
e1f99ce6 | 984 | |
e61e0f51 | 985 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
986 | if (IS_ERR(cs)) |
987 | return PTR_ERR(cs); | |
c4d69da1 | 988 | |
73dec95e TU |
989 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
990 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
991 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 992 | intel_ring_advance(rq, cs); |
c4d69da1 | 993 | |
fb3256da DV |
994 | return 0; |
995 | } | |
996 | ||
997 | static int | |
e61e0f51 | 998 | i915_emit_bb_start(struct i915_request *rq, |
803688ba CW |
999 | u64 offset, u32 len, |
1000 | unsigned int dispatch_flags) | |
fb3256da | 1001 | { |
73dec95e | 1002 | u32 *cs; |
fb3256da | 1003 | |
e61e0f51 | 1004 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1005 | if (IS_ERR(cs)) |
1006 | return PTR_ERR(cs); | |
fb3256da | 1007 | |
73dec95e TU |
1008 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1009 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1010 | MI_BATCH_NON_SECURE); | |
e61e0f51 | 1011 | intel_ring_advance(rq, cs); |
62fdfeaf | 1012 | |
62fdfeaf EA |
1013 | return 0; |
1014 | } | |
1015 | ||
62fdfeaf | 1016 | |
6b8294a4 | 1017 | |
d822bb18 CW |
1018 | int intel_ring_pin(struct intel_ring *ring, |
1019 | struct drm_i915_private *i915, | |
1020 | unsigned int offset_bias) | |
7ba717cf | 1021 | { |
d822bb18 | 1022 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1023 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1024 | unsigned int flags; |
8305216f | 1025 | void *addr; |
7ba717cf TD |
1026 | int ret; |
1027 | ||
57e88531 | 1028 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1029 | |
9d80841e | 1030 | |
d3ef1af6 DCS |
1031 | flags = PIN_GLOBAL; |
1032 | if (offset_bias) | |
1033 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1034 | if (vma->obj->stolen) |
57e88531 | 1035 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1036 | |
57e88531 | 1037 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1038 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1039 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1040 | else | |
1041 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1042 | if (unlikely(ret)) | |
def0c5f6 | 1043 | return ret; |
57e88531 | 1044 | } |
7ba717cf | 1045 | |
57e88531 CW |
1046 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1047 | if (unlikely(ret)) | |
1048 | return ret; | |
def0c5f6 | 1049 | |
9d80841e | 1050 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1051 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1052 | else | |
9d80841e | 1053 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1054 | if (IS_ERR(addr)) |
1055 | goto err; | |
7ba717cf | 1056 | |
3d574a6b CW |
1057 | vma->obj->pin_global++; |
1058 | ||
32c04f16 | 1059 | ring->vaddr = addr; |
7ba717cf | 1060 | return 0; |
d2cad535 | 1061 | |
57e88531 CW |
1062 | err: |
1063 | i915_vma_unpin(vma); | |
1064 | return PTR_ERR(addr); | |
7ba717cf TD |
1065 | } |
1066 | ||
e6ba9992 CW |
1067 | void intel_ring_reset(struct intel_ring *ring, u32 tail) |
1068 | { | |
41d37680 CW |
1069 | GEM_BUG_ON(!intel_ring_offset_valid(ring, tail)); |
1070 | ||
e6ba9992 CW |
1071 | ring->tail = tail; |
1072 | ring->head = tail; | |
1073 | ring->emit = tail; | |
1074 | intel_ring_update_space(ring); | |
1075 | } | |
1076 | ||
aad29fbb CW |
1077 | void intel_ring_unpin(struct intel_ring *ring) |
1078 | { | |
1079 | GEM_BUG_ON(!ring->vma); | |
1080 | GEM_BUG_ON(!ring->vaddr); | |
1081 | ||
e6ba9992 CW |
1082 | /* Discard any unused bytes beyond that submitted to hw. */ |
1083 | intel_ring_reset(ring, ring->tail); | |
1084 | ||
9d80841e | 1085 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1086 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1087 | else |
1088 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1089 | ring->vaddr = NULL; |
1090 | ||
3d574a6b | 1091 | ring->vma->obj->pin_global--; |
57e88531 | 1092 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1093 | } |
1094 | ||
57e88531 CW |
1095 | static struct i915_vma * |
1096 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1097 | { |
05394f39 | 1098 | struct drm_i915_gem_object *obj; |
57e88531 | 1099 | struct i915_vma *vma; |
62fdfeaf | 1100 | |
187685cb | 1101 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1102 | if (!obj) |
2d6c4c84 | 1103 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1104 | if (IS_ERR(obj)) |
1105 | return ERR_CAST(obj); | |
8187a2b7 | 1106 | |
24f3a8cf AG |
1107 | /* mark ring buffers as read-only from GPU side by default */ |
1108 | obj->gt_ro = 1; | |
1109 | ||
82ad6443 | 1110 | vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL); |
57e88531 CW |
1111 | if (IS_ERR(vma)) |
1112 | goto err; | |
1113 | ||
1114 | return vma; | |
e3efda49 | 1115 | |
57e88531 CW |
1116 | err: |
1117 | i915_gem_object_put(obj); | |
1118 | return vma; | |
e3efda49 CW |
1119 | } |
1120 | ||
7e37f889 | 1121 | struct intel_ring * |
65fcb806 | 1122 | intel_engine_create_ring(struct intel_engine_cs *engine, |
a89d1f92 | 1123 | struct i915_timeline *timeline, |
65fcb806 | 1124 | int size) |
01101fa7 | 1125 | { |
7e37f889 | 1126 | struct intel_ring *ring; |
57e88531 | 1127 | struct i915_vma *vma; |
01101fa7 | 1128 | |
8f942018 | 1129 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1130 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
a89d1f92 | 1131 | GEM_BUG_ON(timeline == &engine->timeline); |
b887d615 | 1132 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
8f942018 | 1133 | |
01101fa7 | 1134 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1135 | if (!ring) |
01101fa7 CW |
1136 | return ERR_PTR(-ENOMEM); |
1137 | ||
675d9ad7 | 1138 | INIT_LIST_HEAD(&ring->request_list); |
a89d1f92 | 1139 | ring->timeline = i915_timeline_get(timeline); |
675d9ad7 | 1140 | |
01101fa7 CW |
1141 | ring->size = size; |
1142 | /* Workaround an erratum on the i830 which causes a hang if | |
1143 | * the TAIL pointer points to within the last 2 cachelines | |
1144 | * of the buffer. | |
1145 | */ | |
1146 | ring->effective_size = size; | |
2a307c2e | 1147 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1148 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1149 | ||
01101fa7 CW |
1150 | intel_ring_update_space(ring); |
1151 | ||
57e88531 CW |
1152 | vma = intel_ring_create_vma(engine->i915, size); |
1153 | if (IS_ERR(vma)) { | |
01101fa7 | 1154 | kfree(ring); |
57e88531 | 1155 | return ERR_CAST(vma); |
01101fa7 | 1156 | } |
57e88531 | 1157 | ring->vma = vma; |
01101fa7 CW |
1158 | |
1159 | return ring; | |
1160 | } | |
1161 | ||
1162 | void | |
7e37f889 | 1163 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1164 | { |
f8a7fde4 CW |
1165 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1166 | ||
1167 | i915_vma_close(ring->vma); | |
1168 | __i915_gem_object_release_unless_active(obj); | |
1169 | ||
a89d1f92 | 1170 | i915_timeline_put(ring->timeline); |
01101fa7 CW |
1171 | kfree(ring); |
1172 | } | |
1173 | ||
1fc44d9b CW |
1174 | static void intel_ring_context_destroy(struct intel_context *ce) |
1175 | { | |
1176 | GEM_BUG_ON(ce->pin_count); | |
1177 | ||
1178 | if (ce->state) | |
1179 | __i915_gem_object_release_unless_active(ce->state->obj); | |
1180 | } | |
1181 | ||
1fc44d9b | 1182 | static int __context_pin(struct intel_context *ce) |
e8a9c58f | 1183 | { |
d901e8e6 CW |
1184 | struct i915_vma *vma; |
1185 | int err; | |
1186 | ||
1187 | vma = ce->state; | |
1188 | if (!vma) | |
1189 | return 0; | |
e8a9c58f | 1190 | |
f4e15af7 CW |
1191 | /* |
1192 | * Clear this page out of any CPU caches for coherent swap-in/out. | |
e8a9c58f CW |
1193 | * We only want to do this on the first bind so that we do not stall |
1194 | * on an active context (which by nature is already on the GPU). | |
1195 | */ | |
1196 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
d901e8e6 CW |
1197 | err = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1198 | if (err) | |
1199 | return err; | |
e8a9c58f CW |
1200 | } |
1201 | ||
d901e8e6 CW |
1202 | err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1203 | PIN_GLOBAL | PIN_HIGH); | |
1204 | if (err) | |
1205 | return err; | |
1206 | ||
1207 | /* | |
1208 | * And mark is as a globally pinned object to let the shrinker know | |
1209 | * it cannot reclaim the object until we release it. | |
1210 | */ | |
1211 | vma->obj->pin_global++; | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static void __context_unpin(struct intel_context *ce) | |
1217 | { | |
1218 | struct i915_vma *vma; | |
1219 | ||
1220 | vma = ce->state; | |
1221 | if (!vma) | |
1222 | return; | |
1223 | ||
1224 | vma->obj->pin_global--; | |
1225 | i915_vma_unpin(vma); | |
1226 | } | |
1227 | ||
1228 | static void intel_ring_context_unpin(struct intel_context *ce) | |
1229 | { | |
1230 | __context_unpin(ce); | |
1231 | ||
1232 | i915_gem_context_put(ce->gem_context); | |
e8a9c58f CW |
1233 | } |
1234 | ||
3204c343 CW |
1235 | static struct i915_vma * |
1236 | alloc_context_vma(struct intel_engine_cs *engine) | |
1237 | { | |
1238 | struct drm_i915_private *i915 = engine->i915; | |
1239 | struct drm_i915_gem_object *obj; | |
1240 | struct i915_vma *vma; | |
d2b4b979 | 1241 | int err; |
3204c343 | 1242 | |
63ffbcda | 1243 | obj = i915_gem_object_create(i915, engine->context_size); |
3204c343 CW |
1244 | if (IS_ERR(obj)) |
1245 | return ERR_CAST(obj); | |
1246 | ||
d2b4b979 CW |
1247 | if (engine->default_state) { |
1248 | void *defaults, *vaddr; | |
1249 | ||
1250 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); | |
1251 | if (IS_ERR(vaddr)) { | |
1252 | err = PTR_ERR(vaddr); | |
1253 | goto err_obj; | |
1254 | } | |
1255 | ||
1256 | defaults = i915_gem_object_pin_map(engine->default_state, | |
1257 | I915_MAP_WB); | |
1258 | if (IS_ERR(defaults)) { | |
1259 | err = PTR_ERR(defaults); | |
1260 | goto err_map; | |
1261 | } | |
1262 | ||
1263 | memcpy(vaddr, defaults, engine->context_size); | |
1264 | ||
1265 | i915_gem_object_unpin_map(engine->default_state); | |
1266 | i915_gem_object_unpin_map(obj); | |
1267 | } | |
1268 | ||
3204c343 CW |
1269 | /* |
1270 | * Try to make the context utilize L3 as well as LLC. | |
1271 | * | |
1272 | * On VLV we don't have L3 controls in the PTEs so we | |
1273 | * shouldn't touch the cache level, especially as that | |
1274 | * would make the object snooped which might have a | |
1275 | * negative performance impact. | |
1276 | * | |
1277 | * Snooping is required on non-llc platforms in execlist | |
1278 | * mode, but since all GGTT accesses use PAT entry 0 we | |
1279 | * get snooping anyway regardless of cache_level. | |
1280 | * | |
1281 | * This is only applicable for Ivy Bridge devices since | |
1282 | * later platforms don't have L3 control bits in the PTE. | |
1283 | */ | |
1284 | if (IS_IVYBRIDGE(i915)) { | |
1285 | /* Ignore any error, regard it as a simple optimisation */ | |
1286 | i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC); | |
1287 | } | |
1288 | ||
82ad6443 | 1289 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); |
d2b4b979 CW |
1290 | if (IS_ERR(vma)) { |
1291 | err = PTR_ERR(vma); | |
1292 | goto err_obj; | |
1293 | } | |
3204c343 CW |
1294 | |
1295 | return vma; | |
d2b4b979 CW |
1296 | |
1297 | err_map: | |
1298 | i915_gem_object_unpin_map(obj); | |
1299 | err_obj: | |
1300 | i915_gem_object_put(obj); | |
1301 | return ERR_PTR(err); | |
3204c343 CW |
1302 | } |
1303 | ||
1fc44d9b CW |
1304 | static struct intel_context * |
1305 | __ring_context_pin(struct intel_engine_cs *engine, | |
1306 | struct i915_gem_context *ctx, | |
1307 | struct intel_context *ce) | |
0cb26a8e | 1308 | { |
1fc44d9b | 1309 | int err; |
0cb26a8e | 1310 | |
63ffbcda | 1311 | if (!ce->state && engine->context_size) { |
3204c343 CW |
1312 | struct i915_vma *vma; |
1313 | ||
1314 | vma = alloc_context_vma(engine); | |
1315 | if (IS_ERR(vma)) { | |
1fc44d9b | 1316 | err = PTR_ERR(vma); |
266a240b | 1317 | goto err; |
3204c343 CW |
1318 | } |
1319 | ||
1320 | ce->state = vma; | |
1321 | } | |
1322 | ||
d901e8e6 CW |
1323 | err = __context_pin(ce); |
1324 | if (err) | |
1325 | goto err; | |
0cb26a8e | 1326 | |
9a6feaf0 | 1327 | i915_gem_context_get(ctx); |
0cb26a8e | 1328 | |
266a240b | 1329 | /* One ringbuffer to rule them all */ |
1fc44d9b CW |
1330 | GEM_BUG_ON(!engine->buffer); |
1331 | ce->ring = engine->buffer; | |
1332 | ||
1333 | return ce; | |
266a240b CW |
1334 | |
1335 | err: | |
0cb26a8e | 1336 | ce->pin_count = 0; |
1fc44d9b | 1337 | return ERR_PTR(err); |
0cb26a8e CW |
1338 | } |
1339 | ||
1fc44d9b CW |
1340 | static const struct intel_context_ops ring_context_ops = { |
1341 | .unpin = intel_ring_context_unpin, | |
1342 | .destroy = intel_ring_context_destroy, | |
1343 | }; | |
1344 | ||
1345 | static struct intel_context * | |
1346 | intel_ring_context_pin(struct intel_engine_cs *engine, | |
1347 | struct i915_gem_context *ctx) | |
0cb26a8e | 1348 | { |
ab82a063 | 1349 | struct intel_context *ce = to_intel_context(ctx, engine); |
0cb26a8e | 1350 | |
91c8a326 | 1351 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e | 1352 | |
1fc44d9b CW |
1353 | if (likely(ce->pin_count++)) |
1354 | return ce; | |
1355 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ | |
0cb26a8e | 1356 | |
1fc44d9b | 1357 | ce->ops = &ring_context_ops; |
0cb26a8e | 1358 | |
1fc44d9b | 1359 | return __ring_context_pin(engine, ctx, ce); |
0cb26a8e CW |
1360 | } |
1361 | ||
acd27845 | 1362 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1363 | { |
32c04f16 | 1364 | struct intel_ring *ring; |
a89d1f92 | 1365 | struct i915_timeline *timeline; |
1a5788bf | 1366 | int err; |
bfc882b4 | 1367 | |
019bf277 TU |
1368 | intel_engine_setup_common(engine); |
1369 | ||
a89d1f92 CW |
1370 | timeline = i915_timeline_create(engine->i915, engine->name); |
1371 | if (IS_ERR(timeline)) { | |
1372 | err = PTR_ERR(timeline); | |
1373 | goto err; | |
1374 | } | |
1375 | ||
1376 | ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); | |
1377 | i915_timeline_put(timeline); | |
d822bb18 | 1378 | if (IS_ERR(ring)) { |
1a5788bf | 1379 | err = PTR_ERR(ring); |
486e93f7 | 1380 | goto err; |
d822bb18 CW |
1381 | } |
1382 | ||
d3ef1af6 | 1383 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1384 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1385 | if (err) | |
1386 | goto err_ring; | |
1387 | ||
1388 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1389 | engine->buffer = ring; |
62fdfeaf | 1390 | |
1fc44d9b CW |
1391 | err = intel_engine_init_common(engine); |
1392 | if (err) | |
1393 | goto err_unpin; | |
1394 | ||
8ee14975 | 1395 | return 0; |
351e3db2 | 1396 | |
1fc44d9b CW |
1397 | err_unpin: |
1398 | intel_ring_unpin(ring); | |
1a5788bf CW |
1399 | err_ring: |
1400 | intel_ring_free(ring); | |
1a5788bf CW |
1401 | err: |
1402 | intel_engine_cleanup_common(engine); | |
1403 | return err; | |
62fdfeaf EA |
1404 | } |
1405 | ||
7e37f889 | 1406 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1407 | { |
1a5788bf | 1408 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1409 | |
1a5788bf CW |
1410 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1411 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1412 | |
1a5788bf CW |
1413 | intel_ring_unpin(engine->buffer); |
1414 | intel_ring_free(engine->buffer); | |
78501eac | 1415 | |
0bc40be8 TU |
1416 | if (engine->cleanup) |
1417 | engine->cleanup(engine); | |
8d19215b | 1418 | |
96a945aa | 1419 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1420 | |
3b3f1650 AG |
1421 | dev_priv->engine[engine->id] = NULL; |
1422 | kfree(engine); | |
62fdfeaf EA |
1423 | } |
1424 | ||
821ed7df CW |
1425 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1426 | { | |
1427 | struct intel_engine_cs *engine; | |
3b3f1650 | 1428 | enum intel_engine_id id; |
821ed7df | 1429 | |
e6ba9992 | 1430 | /* Restart from the beginning of the rings for convenience */ |
fe085f13 | 1431 | for_each_engine(engine, dev_priv, id) |
e6ba9992 | 1432 | intel_ring_reset(engine->buffer, 0); |
821ed7df CW |
1433 | } |
1434 | ||
b3ee09a4 CW |
1435 | static int load_pd_dir(struct i915_request *rq, |
1436 | const struct i915_hw_ppgtt *ppgtt) | |
1437 | { | |
1438 | const struct intel_engine_cs * const engine = rq->engine; | |
1439 | u32 *cs; | |
1440 | ||
1441 | cs = intel_ring_begin(rq, 6); | |
1442 | if (IS_ERR(cs)) | |
1443 | return PTR_ERR(cs); | |
1444 | ||
1445 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1446 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); | |
1447 | *cs++ = PP_DIR_DCLV_2G; | |
1448 | ||
1449 | *cs++ = MI_LOAD_REGISTER_IMM(1); | |
1450 | *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); | |
1451 | *cs++ = ppgtt->pd.base.ggtt_offset << 10; | |
1452 | ||
1453 | intel_ring_advance(rq, cs); | |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
e61e0f51 | 1458 | static inline int mi_set_context(struct i915_request *rq, u32 flags) |
8911a31c CW |
1459 | { |
1460 | struct drm_i915_private *i915 = rq->i915; | |
1461 | struct intel_engine_cs *engine = rq->engine; | |
1462 | enum intel_engine_id id; | |
1463 | const int num_rings = | |
1464 | /* Use an extended w/a on gen7 if signalling from other rings */ | |
1465 | (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? | |
1466 | INTEL_INFO(i915)->num_rings - 1 : | |
1467 | 0; | |
1fc719d1 | 1468 | bool force_restore = false; |
8911a31c CW |
1469 | int len; |
1470 | u32 *cs; | |
1471 | ||
1472 | flags |= MI_MM_SPACE_GTT; | |
1473 | if (IS_HASWELL(i915)) | |
1474 | /* These flags are for resource streamer on HSW+ */ | |
1475 | flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; | |
1476 | else | |
1477 | flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; | |
1478 | ||
1479 | len = 4; | |
1480 | if (IS_GEN7(i915)) | |
1481 | len += 2 + (num_rings ? 4*num_rings + 6 : 0); | |
1fc719d1 CW |
1482 | if (flags & MI_FORCE_RESTORE) { |
1483 | GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); | |
1484 | flags &= ~MI_FORCE_RESTORE; | |
1485 | force_restore = true; | |
1486 | len += 2; | |
1487 | } | |
8911a31c CW |
1488 | |
1489 | cs = intel_ring_begin(rq, len); | |
1490 | if (IS_ERR(cs)) | |
1491 | return PTR_ERR(cs); | |
1492 | ||
1493 | /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ | |
1494 | if (IS_GEN7(i915)) { | |
1495 | *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; | |
1496 | if (num_rings) { | |
1497 | struct intel_engine_cs *signaller; | |
1498 | ||
1499 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1500 | for_each_engine(signaller, i915, id) { | |
1501 | if (signaller == engine) | |
1502 | continue; | |
1503 | ||
1504 | *cs++ = i915_mmio_reg_offset( | |
1505 | RING_PSMI_CTL(signaller->mmio_base)); | |
1506 | *cs++ = _MASKED_BIT_ENABLE( | |
1507 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1508 | } | |
1509 | } | |
1510 | } | |
1511 | ||
1fc719d1 CW |
1512 | if (force_restore) { |
1513 | /* | |
1514 | * The HW doesn't handle being told to restore the current | |
1515 | * context very well. Quite often it likes goes to go off and | |
1516 | * sulk, especially when it is meant to be reloading PP_DIR. | |
1517 | * A very simple fix to force the reload is to simply switch | |
1518 | * away from the current context and back again. | |
1519 | * | |
1520 | * Note that the kernel_context will contain random state | |
1521 | * following the INHIBIT_RESTORE. We accept this since we | |
1522 | * never use the kernel_context state; it is merely a | |
1523 | * placeholder we use to flush other contexts. | |
1524 | */ | |
1525 | *cs++ = MI_SET_CONTEXT; | |
1526 | *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context, | |
1527 | engine)->state) | | |
1528 | MI_MM_SPACE_GTT | | |
1529 | MI_RESTORE_INHIBIT; | |
1530 | } | |
1531 | ||
8911a31c CW |
1532 | *cs++ = MI_NOOP; |
1533 | *cs++ = MI_SET_CONTEXT; | |
1fc44d9b | 1534 | *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags; |
8911a31c CW |
1535 | /* |
1536 | * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP | |
1537 | * WaMiSetContext_Hang:snb,ivb,vlv | |
1538 | */ | |
1539 | *cs++ = MI_NOOP; | |
1540 | ||
1541 | if (IS_GEN7(i915)) { | |
1542 | if (num_rings) { | |
1543 | struct intel_engine_cs *signaller; | |
1544 | i915_reg_t last_reg = {}; /* keep gcc quiet */ | |
1545 | ||
1546 | *cs++ = MI_LOAD_REGISTER_IMM(num_rings); | |
1547 | for_each_engine(signaller, i915, id) { | |
1548 | if (signaller == engine) | |
1549 | continue; | |
1550 | ||
1551 | last_reg = RING_PSMI_CTL(signaller->mmio_base); | |
1552 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1553 | *cs++ = _MASKED_BIT_DISABLE( | |
1554 | GEN6_PSMI_SLEEP_MSG_DISABLE); | |
1555 | } | |
1556 | ||
1557 | /* Insert a delay before the next switch! */ | |
1558 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; | |
1559 | *cs++ = i915_mmio_reg_offset(last_reg); | |
1560 | *cs++ = i915_ggtt_offset(engine->scratch); | |
1561 | *cs++ = MI_NOOP; | |
1562 | } | |
1563 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; | |
1564 | } | |
1565 | ||
1566 | intel_ring_advance(rq, cs); | |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
e61e0f51 | 1571 | static int remap_l3(struct i915_request *rq, int slice) |
8911a31c CW |
1572 | { |
1573 | u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice]; | |
1574 | int i; | |
1575 | ||
1576 | if (!remap_info) | |
1577 | return 0; | |
1578 | ||
1579 | cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2); | |
1580 | if (IS_ERR(cs)) | |
1581 | return PTR_ERR(cs); | |
1582 | ||
1583 | /* | |
1584 | * Note: We do not worry about the concurrent register cacheline hang | |
1585 | * here because no other code should access these registers other than | |
1586 | * at initialization time. | |
1587 | */ | |
1588 | *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); | |
1589 | for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { | |
1590 | *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); | |
1591 | *cs++ = remap_info[i]; | |
1592 | } | |
1593 | *cs++ = MI_NOOP; | |
1594 | intel_ring_advance(rq, cs); | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
e61e0f51 | 1599 | static int switch_context(struct i915_request *rq) |
8911a31c CW |
1600 | { |
1601 | struct intel_engine_cs *engine = rq->engine; | |
b3ee09a4 CW |
1602 | struct i915_gem_context *ctx = rq->gem_context; |
1603 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
1604 | unsigned int unwind_mm = 0; | |
8911a31c CW |
1605 | u32 hw_flags = 0; |
1606 | int ret, i; | |
1607 | ||
1608 | lockdep_assert_held(&rq->i915->drm.struct_mutex); | |
1609 | GEM_BUG_ON(HAS_EXECLISTS(rq->i915)); | |
1610 | ||
b3ee09a4 CW |
1611 | if (ppgtt) { |
1612 | ret = load_pd_dir(rq, ppgtt); | |
8911a31c CW |
1613 | if (ret) |
1614 | goto err; | |
1615 | ||
b3ee09a4 CW |
1616 | if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) { |
1617 | unwind_mm = intel_engine_flag(engine); | |
1618 | ppgtt->pd_dirty_rings &= ~unwind_mm; | |
1619 | hw_flags = MI_FORCE_RESTORE; | |
1620 | } | |
8911a31c CW |
1621 | } |
1622 | ||
b3ee09a4 | 1623 | if (rq->hw_context->state) { |
8911a31c CW |
1624 | GEM_BUG_ON(engine->id != RCS); |
1625 | ||
1626 | /* | |
1627 | * The kernel context(s) is treated as pure scratch and is not | |
1628 | * expected to retain any state (as we sacrifice it during | |
1629 | * suspend and on resume it may be corrupted). This is ok, | |
1630 | * as nothing actually executes using the kernel context; it | |
1631 | * is purely used for flushing user contexts. | |
1632 | */ | |
b3ee09a4 | 1633 | if (i915_gem_context_is_kernel(ctx)) |
8911a31c CW |
1634 | hw_flags = MI_RESTORE_INHIBIT; |
1635 | ||
1636 | ret = mi_set_context(rq, hw_flags); | |
1637 | if (ret) | |
1638 | goto err_mm; | |
8911a31c CW |
1639 | } |
1640 | ||
b3ee09a4 | 1641 | if (ctx->remap_slice) { |
8911a31c | 1642 | for (i = 0; i < MAX_L3_SLICES; i++) { |
b3ee09a4 | 1643 | if (!(ctx->remap_slice & BIT(i))) |
8911a31c CW |
1644 | continue; |
1645 | ||
1646 | ret = remap_l3(rq, i); | |
1647 | if (ret) | |
b3ee09a4 | 1648 | goto err_mm; |
8911a31c CW |
1649 | } |
1650 | ||
b3ee09a4 | 1651 | ctx->remap_slice = 0; |
8911a31c CW |
1652 | } |
1653 | ||
1654 | return 0; | |
1655 | ||
8911a31c | 1656 | err_mm: |
b3ee09a4 CW |
1657 | if (unwind_mm) |
1658 | ppgtt->pd_dirty_rings |= unwind_mm; | |
8911a31c CW |
1659 | err: |
1660 | return ret; | |
1661 | } | |
1662 | ||
e61e0f51 | 1663 | static int ring_request_alloc(struct i915_request *request) |
9d773091 | 1664 | { |
fd138212 | 1665 | int ret; |
6310346e | 1666 | |
1fc44d9b | 1667 | GEM_BUG_ON(!request->hw_context->pin_count); |
e8a9c58f | 1668 | |
6310346e CW |
1669 | /* Flush enough space to reduce the likelihood of waiting after |
1670 | * we start building the request - in which case we will just | |
1671 | * have to repeat work. | |
1672 | */ | |
a0442461 | 1673 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1674 | |
fd138212 CW |
1675 | ret = intel_ring_wait_for_space(request->ring, request->reserved_space); |
1676 | if (ret) | |
1677 | return ret; | |
6310346e | 1678 | |
8911a31c | 1679 | ret = switch_context(request); |
3fef5cda CW |
1680 | if (ret) |
1681 | return ret; | |
1682 | ||
a0442461 | 1683 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1684 | return 0; |
9d773091 CW |
1685 | } |
1686 | ||
fd138212 | 1687 | static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes) |
987046ad | 1688 | { |
e61e0f51 | 1689 | struct i915_request *target; |
e95433c7 CW |
1690 | long timeout; |
1691 | ||
fd138212 | 1692 | lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex); |
987046ad | 1693 | |
95aebcb2 | 1694 | if (intel_ring_update_space(ring) >= bytes) |
987046ad CW |
1695 | return 0; |
1696 | ||
36620032 | 1697 | GEM_BUG_ON(list_empty(&ring->request_list)); |
675d9ad7 | 1698 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad | 1699 | /* Would completion of this request free enough space? */ |
605d5b32 CW |
1700 | if (bytes <= __intel_ring_space(target->postfix, |
1701 | ring->emit, ring->size)) | |
987046ad | 1702 | break; |
79bbcc29 | 1703 | } |
29b1b415 | 1704 | |
675d9ad7 | 1705 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1706 | return -ENOSPC; |
1707 | ||
e61e0f51 | 1708 | timeout = i915_request_wait(target, |
e95433c7 CW |
1709 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, |
1710 | MAX_SCHEDULE_TIMEOUT); | |
1711 | if (timeout < 0) | |
1712 | return timeout; | |
7da844c5 | 1713 | |
e61e0f51 | 1714 | i915_request_retire_upto(target); |
7da844c5 CW |
1715 | |
1716 | intel_ring_update_space(ring); | |
1717 | GEM_BUG_ON(ring->space < bytes); | |
1718 | return 0; | |
29b1b415 JH |
1719 | } |
1720 | ||
fd138212 CW |
1721 | int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes) |
1722 | { | |
1723 | GEM_BUG_ON(bytes > ring->effective_size); | |
1724 | if (unlikely(bytes > ring->effective_size - ring->emit)) | |
1725 | bytes += ring->size - ring->emit; | |
1726 | ||
1727 | if (unlikely(bytes > ring->space)) { | |
1728 | int ret = wait_for_space(ring, bytes); | |
1729 | if (unlikely(ret)) | |
1730 | return ret; | |
1731 | } | |
1732 | ||
1733 | GEM_BUG_ON(ring->space < bytes); | |
1734 | return 0; | |
1735 | } | |
1736 | ||
e61e0f51 | 1737 | u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords) |
cbcc80df | 1738 | { |
e61e0f51 | 1739 | struct intel_ring *ring = rq->ring; |
5e5655c3 CW |
1740 | const unsigned int remain_usable = ring->effective_size - ring->emit; |
1741 | const unsigned int bytes = num_dwords * sizeof(u32); | |
1742 | unsigned int need_wrap = 0; | |
1743 | unsigned int total_bytes; | |
73dec95e | 1744 | u32 *cs; |
29b1b415 | 1745 | |
6492ca79 CW |
1746 | /* Packets must be qword aligned. */ |
1747 | GEM_BUG_ON(num_dwords & 1); | |
1748 | ||
e61e0f51 | 1749 | total_bytes = bytes + rq->reserved_space; |
5e5655c3 | 1750 | GEM_BUG_ON(total_bytes > ring->effective_size); |
29b1b415 | 1751 | |
5e5655c3 CW |
1752 | if (unlikely(total_bytes > remain_usable)) { |
1753 | const int remain_actual = ring->size - ring->emit; | |
1754 | ||
1755 | if (bytes > remain_usable) { | |
1756 | /* | |
1757 | * Not enough space for the basic request. So need to | |
1758 | * flush out the remainder and then wait for | |
1759 | * base + reserved. | |
1760 | */ | |
1761 | total_bytes += remain_actual; | |
1762 | need_wrap = remain_actual | 1; | |
1763 | } else { | |
1764 | /* | |
1765 | * The base request will fit but the reserved space | |
1766 | * falls off the end. So we don't need an immediate | |
1767 | * wrap and only need to effectively wait for the | |
1768 | * reserved size from the start of ringbuffer. | |
1769 | */ | |
e61e0f51 | 1770 | total_bytes = rq->reserved_space + remain_actual; |
5e5655c3 | 1771 | } |
cbcc80df MK |
1772 | } |
1773 | ||
5e5655c3 | 1774 | if (unlikely(total_bytes > ring->space)) { |
fd138212 CW |
1775 | int ret; |
1776 | ||
1777 | /* | |
1778 | * Space is reserved in the ringbuffer for finalising the | |
1779 | * request, as that cannot be allowed to fail. During request | |
1780 | * finalisation, reserved_space is set to 0 to stop the | |
1781 | * overallocation and the assumption is that then we never need | |
1782 | * to wait (which has the risk of failing with EINTR). | |
1783 | * | |
e61e0f51 | 1784 | * See also i915_request_alloc() and i915_request_add(). |
fd138212 | 1785 | */ |
e61e0f51 | 1786 | GEM_BUG_ON(!rq->reserved_space); |
fd138212 CW |
1787 | |
1788 | ret = wait_for_space(ring, total_bytes); | |
cbcc80df | 1789 | if (unlikely(ret)) |
73dec95e | 1790 | return ERR_PTR(ret); |
cbcc80df MK |
1791 | } |
1792 | ||
987046ad | 1793 | if (unlikely(need_wrap)) { |
5e5655c3 CW |
1794 | need_wrap &= ~1; |
1795 | GEM_BUG_ON(need_wrap > ring->space); | |
1796 | GEM_BUG_ON(ring->emit + need_wrap > ring->size); | |
46b86332 | 1797 | GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64))); |
78501eac | 1798 | |
987046ad | 1799 | /* Fill the tail with MI_NOOP */ |
46b86332 | 1800 | memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64)); |
5e5655c3 | 1801 | ring->space -= need_wrap; |
46b86332 | 1802 | ring->emit = 0; |
987046ad | 1803 | } |
304d695c | 1804 | |
e6ba9992 | 1805 | GEM_BUG_ON(ring->emit > ring->size - bytes); |
605d5b32 | 1806 | GEM_BUG_ON(ring->space < bytes); |
e6ba9992 | 1807 | cs = ring->vaddr + ring->emit; |
46b86332 | 1808 | GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs))); |
e6ba9992 | 1809 | ring->emit += bytes; |
1dae2dfb | 1810 | ring->space -= bytes; |
73dec95e TU |
1811 | |
1812 | return cs; | |
8187a2b7 | 1813 | } |
78501eac | 1814 | |
753b1ad4 | 1815 | /* Align the ring tail to a cacheline boundary */ |
e61e0f51 | 1816 | int intel_ring_cacheline_align(struct i915_request *rq) |
753b1ad4 | 1817 | { |
1f177a13 CW |
1818 | int num_dwords; |
1819 | void *cs; | |
753b1ad4 | 1820 | |
1f177a13 | 1821 | num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); |
753b1ad4 VS |
1822 | if (num_dwords == 0) |
1823 | return 0; | |
1824 | ||
1f177a13 CW |
1825 | num_dwords = CACHELINE_DWORDS - num_dwords; |
1826 | GEM_BUG_ON(num_dwords & 1); | |
1827 | ||
e61e0f51 | 1828 | cs = intel_ring_begin(rq, num_dwords); |
73dec95e TU |
1829 | if (IS_ERR(cs)) |
1830 | return PTR_ERR(cs); | |
753b1ad4 | 1831 | |
1f177a13 | 1832 | memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2); |
e61e0f51 | 1833 | intel_ring_advance(rq, cs); |
753b1ad4 | 1834 | |
1f177a13 | 1835 | GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); |
753b1ad4 VS |
1836 | return 0; |
1837 | } | |
1838 | ||
e61e0f51 | 1839 | static void gen6_bsd_submit_request(struct i915_request *request) |
881f47b6 | 1840 | { |
c5efa1ad | 1841 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1842 | |
76f8421f CW |
1843 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1844 | ||
881f47b6 | 1845 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1846 | |
1847 | /* Disable notification that the ring is IDLE. The GT | |
1848 | * will then assume that it is busy and bring it out of rc6. | |
1849 | */ | |
76f8421f CW |
1850 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1851 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1852 | |
1853 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1854 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1855 | |
12f55818 | 1856 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1857 | if (__intel_wait_for_register_fw(dev_priv, |
1858 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1859 | GEN6_BSD_SLEEP_INDICATOR, | |
1860 | 0, | |
1861 | 1000, 0, NULL)) | |
12f55818 | 1862 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1863 | |
12f55818 | 1864 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1865 | i9xx_submit_request(request); |
12f55818 CW |
1866 | |
1867 | /* Let the ring send IDLE messages to the GT again, | |
1868 | * and so let it sleep to conserve power when idle. | |
1869 | */ | |
76f8421f CW |
1870 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1871 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1872 | ||
1873 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1874 | } |
1875 | ||
e61e0f51 | 1876 | static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode) |
881f47b6 | 1877 | { |
73dec95e | 1878 | u32 cmd, *cs; |
b72f3acb | 1879 | |
e61e0f51 | 1880 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
1881 | if (IS_ERR(cs)) |
1882 | return PTR_ERR(cs); | |
b72f3acb | 1883 | |
71a77e07 | 1884 | cmd = MI_FLUSH_DW; |
f0a1fb10 CW |
1885 | |
1886 | /* We always require a command barrier so that subsequent | |
1887 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1888 | * wrt the contents of the write cache being flushed to memory | |
1889 | * (and thus being coherent from the CPU). | |
1890 | */ | |
1891 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1892 | ||
9a289771 JB |
1893 | /* |
1894 | * Bspec vol 1c.5 - video engine command streamer: | |
1895 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1896 | * operation is complete. This bit is only valid when the | |
1897 | * Post-Sync Operation field is a value of 1h or 3h." | |
1898 | */ | |
7c9cf4e3 | 1899 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1900 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1901 | ||
73dec95e TU |
1902 | *cs++ = cmd; |
1903 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c | 1904 | *cs++ = 0; |
73dec95e | 1905 | *cs++ = MI_NOOP; |
e61e0f51 | 1906 | intel_ring_advance(rq, cs); |
1c7a0623 BW |
1907 | return 0; |
1908 | } | |
1909 | ||
d7d4eedd | 1910 | static int |
e61e0f51 | 1911 | hsw_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1912 | u64 offset, u32 len, |
1913 | unsigned int dispatch_flags) | |
d7d4eedd | 1914 | { |
73dec95e | 1915 | u32 *cs; |
d7d4eedd | 1916 | |
e61e0f51 | 1917 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1918 | if (IS_ERR(cs)) |
1919 | return PTR_ERR(cs); | |
d7d4eedd | 1920 | |
73dec95e TU |
1921 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1922 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1923 | (dispatch_flags & I915_DISPATCH_RS ? | |
1924 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1925 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 1926 | *cs++ = offset; |
e61e0f51 | 1927 | intel_ring_advance(rq, cs); |
d7d4eedd CW |
1928 | |
1929 | return 0; | |
1930 | } | |
1931 | ||
881f47b6 | 1932 | static int |
e61e0f51 | 1933 | gen6_emit_bb_start(struct i915_request *rq, |
803688ba CW |
1934 | u64 offset, u32 len, |
1935 | unsigned int dispatch_flags) | |
881f47b6 | 1936 | { |
73dec95e | 1937 | u32 *cs; |
ab6f8e32 | 1938 | |
e61e0f51 | 1939 | cs = intel_ring_begin(rq, 2); |
73dec95e TU |
1940 | if (IS_ERR(cs)) |
1941 | return PTR_ERR(cs); | |
e1f99ce6 | 1942 | |
73dec95e TU |
1943 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1944 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1945 | /* bit0-7 is the length on GEN6+ */ |
73dec95e | 1946 | *cs++ = offset; |
e61e0f51 | 1947 | intel_ring_advance(rq, cs); |
ab6f8e32 | 1948 | |
0206e353 | 1949 | return 0; |
881f47b6 XH |
1950 | } |
1951 | ||
549f7365 CW |
1952 | /* Blitter support (SandyBridge+) */ |
1953 | ||
e61e0f51 | 1954 | static int gen6_ring_flush(struct i915_request *rq, u32 mode) |
8d19215b | 1955 | { |
73dec95e | 1956 | u32 cmd, *cs; |
b72f3acb | 1957 | |
e61e0f51 | 1958 | cs = intel_ring_begin(rq, 4); |
73dec95e TU |
1959 | if (IS_ERR(cs)) |
1960 | return PTR_ERR(cs); | |
b72f3acb | 1961 | |
71a77e07 | 1962 | cmd = MI_FLUSH_DW; |
f0a1fb10 CW |
1963 | |
1964 | /* We always require a command barrier so that subsequent | |
1965 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1966 | * wrt the contents of the write cache being flushed to memory | |
1967 | * (and thus being coherent from the CPU). | |
1968 | */ | |
1969 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1970 | ||
9a289771 JB |
1971 | /* |
1972 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1973 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1974 | * operation is complete. This bit is only valid when the | |
1975 | * Post-Sync Operation field is a value of 1h or 3h." | |
1976 | */ | |
7c9cf4e3 | 1977 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1978 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1979 | *cs++ = cmd; |
1980 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
79e6770c CW |
1981 | *cs++ = 0; |
1982 | *cs++ = MI_NOOP; | |
e61e0f51 | 1983 | intel_ring_advance(rq, cs); |
fd3da6c9 | 1984 | |
b72f3acb | 1985 | return 0; |
8d19215b ZN |
1986 | } |
1987 | ||
d9a64610 TU |
1988 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1989 | struct intel_engine_cs *engine) | |
1990 | { | |
79e6770c | 1991 | int i; |
db3d4019 | 1992 | |
93c6e966 | 1993 | if (!HAS_LEGACY_SEMAPHORES(dev_priv)) |
db3d4019 TU |
1994 | return; |
1995 | ||
79e6770c CW |
1996 | GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); |
1997 | engine->semaphore.sync_to = gen6_ring_sync_to; | |
1998 | engine->semaphore.signal = gen6_signal; | |
51d545d0 | 1999 | |
79e6770c CW |
2000 | /* |
2001 | * The current semaphore is only applied on pre-gen8 | |
2002 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2003 | * platform. So the semaphore between RCS and VCS2 is | |
2004 | * initialized as INVALID. | |
2005 | */ | |
2006 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { | |
2007 | static const struct { | |
4b8e38a9 TU |
2008 | u32 wait_mbox; |
2009 | i915_reg_t mbox_reg; | |
79e6770c CW |
2010 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
2011 | [RCS_HW] = { | |
2012 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2013 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2014 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
2015 | }, | |
2016 | [VCS_HW] = { | |
2017 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2018 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2019 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
2020 | }, | |
2021 | [BCS_HW] = { | |
2022 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2023 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2024 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
2025 | }, | |
2026 | [VECS_HW] = { | |
2027 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2028 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2029 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
2030 | }, | |
2031 | }; | |
2032 | u32 wait_mbox; | |
2033 | i915_reg_t mbox_reg; | |
4b8e38a9 | 2034 | |
79e6770c CW |
2035 | if (i == engine->hw_id) { |
2036 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; | |
2037 | mbox_reg = GEN6_NOSYNC; | |
2038 | } else { | |
2039 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; | |
2040 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 | 2041 | } |
51d545d0 | 2042 | |
79e6770c CW |
2043 | engine->semaphore.mbox.wait[i] = wait_mbox; |
2044 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2045 | } | |
d9a64610 TU |
2046 | } |
2047 | ||
ed003078 CW |
2048 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2049 | struct intel_engine_cs *engine) | |
2050 | { | |
79e6770c | 2051 | if (INTEL_GEN(dev_priv) >= 6) { |
31bb59cc CW |
2052 | engine->irq_enable = gen6_irq_enable; |
2053 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2054 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2055 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2056 | engine->irq_enable = gen5_irq_enable; |
2057 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2058 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2059 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2060 | engine->irq_enable = i9xx_irq_enable; |
2061 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2062 | } else { |
31bb59cc CW |
2063 | engine->irq_enable = i8xx_irq_enable; |
2064 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2065 | } |
2066 | } | |
2067 | ||
ff44ad51 CW |
2068 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2069 | { | |
2070 | engine->submit_request = i9xx_submit_request; | |
27a5f61b | 2071 | engine->cancel_requests = cancel_requests; |
aba5e278 CW |
2072 | |
2073 | engine->park = NULL; | |
2074 | engine->unpark = NULL; | |
ff44ad51 CW |
2075 | } |
2076 | ||
2077 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2078 | { | |
aba5e278 | 2079 | i9xx_set_default_submission(engine); |
ff44ad51 CW |
2080 | engine->submit_request = gen6_bsd_submit_request; |
2081 | } | |
2082 | ||
06a2fe22 TU |
2083 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2084 | struct intel_engine_cs *engine) | |
2085 | { | |
79e6770c CW |
2086 | /* gen8+ are only supported with execlists */ |
2087 | GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); | |
2088 | ||
618e4ca7 CW |
2089 | intel_ring_init_irq(dev_priv, engine); |
2090 | intel_ring_init_semaphores(dev_priv, engine); | |
2091 | ||
1d8a1337 | 2092 | engine->init_hw = init_ring_common; |
5adfb772 CW |
2093 | engine->reset.prepare = reset_prepare; |
2094 | engine->reset.reset = reset_ring; | |
2095 | engine->reset.finish = reset_finish; | |
7445a2a4 | 2096 | |
e8a9c58f | 2097 | engine->context_pin = intel_ring_context_pin; |
f73e7399 CW |
2098 | engine->request_alloc = ring_request_alloc; |
2099 | ||
9b81d556 | 2100 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d | 2101 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
93c6e966 | 2102 | if (HAS_LEGACY_SEMAPHORES(dev_priv)) { |
98f29e8d CW |
2103 | int num_rings; |
2104 | ||
9b81d556 | 2105 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d | 2106 | |
c58949f4 | 2107 | num_rings = INTEL_INFO(dev_priv)->num_rings - 1; |
79e6770c CW |
2108 | engine->emit_breadcrumb_sz += num_rings * 3; |
2109 | if (num_rings & 1) | |
2110 | engine->emit_breadcrumb_sz++; | |
98f29e8d | 2111 | } |
ff44ad51 CW |
2112 | |
2113 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 | 2114 | |
79e6770c | 2115 | if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2116 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2117 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2118 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2119 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2120 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2121 | else |
803688ba | 2122 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2123 | } |
2124 | ||
8b3e2d36 | 2125 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2126 | { |
8b3e2d36 | 2127 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2128 | int ret; |
5c1143bb | 2129 | |
06a2fe22 TU |
2130 | intel_ring_default_vfuncs(dev_priv, engine); |
2131 | ||
61ff75ac CW |
2132 | if (HAS_L3_DPF(dev_priv)) |
2133 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2134 | |
fa6f071d DCS |
2135 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
2136 | ||
79e6770c | 2137 | if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2138 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2139 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2140 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2141 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2142 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2143 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2144 | } else { |
c033666a | 2145 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2146 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2147 | else |
c7fe7d25 | 2148 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2149 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2150 | } |
707d9cf9 | 2151 | |
c033666a | 2152 | if (IS_HASWELL(dev_priv)) |
803688ba | 2153 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2154 | |
e2f80391 | 2155 | engine->init_hw = init_render_ring; |
59465b5f | 2156 | |
acd27845 | 2157 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2158 | if (ret) |
2159 | return ret; | |
2160 | ||
f8973c21 | 2161 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2162 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2163 | if (ret) |
2164 | return ret; | |
2165 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2166 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2167 | if (ret) |
2168 | return ret; | |
2169 | } | |
2170 | ||
2171 | return 0; | |
5c1143bb XH |
2172 | } |
2173 | ||
8b3e2d36 | 2174 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2175 | { |
8b3e2d36 | 2176 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2177 | |
06a2fe22 TU |
2178 | intel_ring_default_vfuncs(dev_priv, engine); |
2179 | ||
c033666a | 2180 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2181 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2182 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2183 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2184 | engine->emit_flush = gen6_bsd_ring_flush; |
79e6770c | 2185 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2186 | } else { |
c7fe7d25 | 2187 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2188 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2189 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2190 | else |
e2f80391 | 2191 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2192 | } |
58fa3835 | 2193 | |
acd27845 | 2194 | return intel_init_ring_buffer(engine); |
5c1143bb | 2195 | } |
549f7365 | 2196 | |
8b3e2d36 | 2197 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2198 | { |
8b3e2d36 | 2199 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2200 | |
2201 | intel_ring_default_vfuncs(dev_priv, engine); | |
2202 | ||
c7fe7d25 | 2203 | engine->emit_flush = gen6_ring_flush; |
79e6770c | 2204 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2205 | |
acd27845 | 2206 | return intel_init_ring_buffer(engine); |
549f7365 | 2207 | } |
a7b9761d | 2208 | |
8b3e2d36 | 2209 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2210 | { |
8b3e2d36 | 2211 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2212 | |
2213 | intel_ring_default_vfuncs(dev_priv, engine); | |
2214 | ||
c7fe7d25 | 2215 | engine->emit_flush = gen6_ring_flush; |
79e6770c CW |
2216 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
2217 | engine->irq_enable = hsw_vebox_irq_enable; | |
2218 | engine->irq_disable = hsw_vebox_irq_disable; | |
9a8a2213 | 2219 | |
acd27845 | 2220 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2221 | } |