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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
2f35afe9 | 42 | static int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
fe085f13 | 52 | ring->space = __intel_ring_space(ring->head, ring->tail, ring->size); |
ebd0fd4b DG |
53 | } |
54 | ||
b72f3acb | 55 | static int |
7c9cf4e3 | 56 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 57 | { |
73dec95e | 58 | u32 cmd, *cs; |
46f0f8d1 CW |
59 | |
60 | cmd = MI_FLUSH; | |
46f0f8d1 | 61 | |
7c9cf4e3 | 62 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
63 | cmd |= MI_READ_FLUSH; |
64 | ||
73dec95e TU |
65 | cs = intel_ring_begin(req, 2); |
66 | if (IS_ERR(cs)) | |
67 | return PTR_ERR(cs); | |
46f0f8d1 | 68 | |
73dec95e TU |
69 | *cs++ = cmd; |
70 | *cs++ = MI_NOOP; | |
71 | intel_ring_advance(req, cs); | |
46f0f8d1 CW |
72 | |
73 | return 0; | |
74 | } | |
75 | ||
76 | static int | |
7c9cf4e3 | 77 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 78 | { |
73dec95e | 79 | u32 cmd, *cs; |
6f392d54 | 80 | |
36d527de CW |
81 | /* |
82 | * read/write caches: | |
83 | * | |
84 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
85 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
86 | * also flushed at 2d versus 3d pipeline switches. | |
87 | * | |
88 | * read-only caches: | |
89 | * | |
90 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
91 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
92 | * | |
93 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
94 | * | |
95 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
96 | * invalidated when MI_EXE_FLUSH is set. | |
97 | * | |
98 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
99 | * invalidated with every MI_FLUSH. | |
100 | * | |
101 | * TLBs: | |
102 | * | |
103 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
104 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
105 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
106 | * are flushed at any MI_FLUSH. | |
107 | */ | |
108 | ||
b5321f30 | 109 | cmd = MI_FLUSH; |
7c9cf4e3 | 110 | if (mode & EMIT_INVALIDATE) { |
36d527de | 111 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
112 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
113 | cmd |= MI_INVALIDATE_ISP; | |
114 | } | |
70eac33e | 115 | |
73dec95e TU |
116 | cs = intel_ring_begin(req, 2); |
117 | if (IS_ERR(cs)) | |
118 | return PTR_ERR(cs); | |
b72f3acb | 119 | |
73dec95e TU |
120 | *cs++ = cmd; |
121 | *cs++ = MI_NOOP; | |
122 | intel_ring_advance(req, cs); | |
b72f3acb CW |
123 | |
124 | return 0; | |
8187a2b7 ZN |
125 | } |
126 | ||
8d315287 JB |
127 | /** |
128 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
129 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
130 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
131 | * | |
132 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
133 | * produced by non-pipelined state commands), software needs to first | |
134 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
135 | * 0. | |
136 | * | |
137 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
138 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
139 | * | |
140 | * And the workaround for these two requires this workaround first: | |
141 | * | |
142 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
143 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
144 | * flushes. | |
145 | * | |
146 | * And this last workaround is tricky because of the requirements on | |
147 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
148 | * volume 2 part 1: | |
149 | * | |
150 | * "1 of the following must also be set: | |
151 | * - Render Target Cache Flush Enable ([12] of DW1) | |
152 | * - Depth Cache Flush Enable ([0] of DW1) | |
153 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
154 | * - Depth Stall ([13] of DW1) | |
155 | * - Post-Sync Operation ([13] of DW1) | |
156 | * - Notify Enable ([8] of DW1)" | |
157 | * | |
158 | * The cache flushes require the workaround flush that triggered this | |
159 | * one, so we can't use it. Depth stall would trigger the same. | |
160 | * Post-sync nonzero is what triggered this second workaround, so we | |
161 | * can't use that one either. Notify enable is IRQs, which aren't | |
162 | * really our business. That leaves only stall at scoreboard. | |
163 | */ | |
164 | static int | |
f2cf1fcc | 165 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 166 | { |
b5321f30 | 167 | u32 scratch_addr = |
bde13ebd | 168 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e TU |
169 | u32 *cs; |
170 | ||
171 | cs = intel_ring_begin(req, 6); | |
172 | if (IS_ERR(cs)) | |
173 | return PTR_ERR(cs); | |
174 | ||
175 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
176 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
177 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
178 | *cs++ = 0; /* low dword */ | |
179 | *cs++ = 0; /* high dword */ | |
180 | *cs++ = MI_NOOP; | |
181 | intel_ring_advance(req, cs); | |
182 | ||
183 | cs = intel_ring_begin(req, 6); | |
184 | if (IS_ERR(cs)) | |
185 | return PTR_ERR(cs); | |
186 | ||
187 | *cs++ = GFX_OP_PIPE_CONTROL(5); | |
188 | *cs++ = PIPE_CONTROL_QW_WRITE; | |
189 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
190 | *cs++ = 0; | |
191 | *cs++ = 0; | |
192 | *cs++ = MI_NOOP; | |
193 | intel_ring_advance(req, cs); | |
8d315287 JB |
194 | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int | |
7c9cf4e3 | 199 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 200 | { |
b5321f30 | 201 | u32 scratch_addr = |
bde13ebd | 202 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 203 | u32 *cs, flags = 0; |
8d315287 JB |
204 | int ret; |
205 | ||
b3111509 | 206 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 207 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
208 | if (ret) |
209 | return ret; | |
210 | ||
8d315287 JB |
211 | /* Just flush everything. Experiments have shown that reducing the |
212 | * number of bits based on the write domains has little performance | |
213 | * impact. | |
214 | */ | |
7c9cf4e3 | 215 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
216 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
217 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
218 | /* | |
219 | * Ensure that any following seqno writes only happen | |
220 | * when the render cache is indeed flushed. | |
221 | */ | |
97f209bc | 222 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 223 | } |
7c9cf4e3 | 224 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
225 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
226 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
227 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
228 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
229 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
230 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
231 | /* | |
232 | * TLB invalidate requires a post-sync write. | |
233 | */ | |
3ac78313 | 234 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 235 | } |
8d315287 | 236 | |
73dec95e TU |
237 | cs = intel_ring_begin(req, 4); |
238 | if (IS_ERR(cs)) | |
239 | return PTR_ERR(cs); | |
8d315287 | 240 | |
73dec95e TU |
241 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
242 | *cs++ = flags; | |
243 | *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT; | |
244 | *cs++ = 0; | |
245 | intel_ring_advance(req, cs); | |
8d315287 JB |
246 | |
247 | return 0; | |
248 | } | |
249 | ||
f3987631 | 250 | static int |
f2cf1fcc | 251 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 252 | { |
73dec95e | 253 | u32 *cs; |
f3987631 | 254 | |
73dec95e TU |
255 | cs = intel_ring_begin(req, 4); |
256 | if (IS_ERR(cs)) | |
257 | return PTR_ERR(cs); | |
f3987631 | 258 | |
73dec95e TU |
259 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
260 | *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD; | |
261 | *cs++ = 0; | |
262 | *cs++ = 0; | |
263 | intel_ring_advance(req, cs); | |
f3987631 PZ |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
4772eaeb | 268 | static int |
7c9cf4e3 | 269 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 270 | { |
b5321f30 | 271 | u32 scratch_addr = |
bde13ebd | 272 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
73dec95e | 273 | u32 *cs, flags = 0; |
4772eaeb | 274 | |
f3987631 PZ |
275 | /* |
276 | * Ensure that any following seqno writes only happen when the render | |
277 | * cache is indeed flushed. | |
278 | * | |
279 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
280 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
281 | * don't try to be clever and just set it unconditionally. | |
282 | */ | |
283 | flags |= PIPE_CONTROL_CS_STALL; | |
284 | ||
4772eaeb PZ |
285 | /* Just flush everything. Experiments have shown that reducing the |
286 | * number of bits based on the write domains has little performance | |
287 | * impact. | |
288 | */ | |
7c9cf4e3 | 289 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
290 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
291 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 292 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 293 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 294 | } |
7c9cf4e3 | 295 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
296 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
297 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
298 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
299 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
300 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
301 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 302 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
303 | /* |
304 | * TLB invalidate requires a post-sync write. | |
305 | */ | |
306 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 307 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 308 | |
add284a3 CW |
309 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
310 | ||
f3987631 PZ |
311 | /* Workaround: we must issue a pipe_control with CS-stall bit |
312 | * set before a pipe_control command that has the state cache | |
313 | * invalidate bit set. */ | |
f2cf1fcc | 314 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
315 | } |
316 | ||
73dec95e TU |
317 | cs = intel_ring_begin(req, 4); |
318 | if (IS_ERR(cs)) | |
319 | return PTR_ERR(cs); | |
4772eaeb | 320 | |
73dec95e TU |
321 | *cs++ = GFX_OP_PIPE_CONTROL(4); |
322 | *cs++ = flags; | |
323 | *cs++ = scratch_addr; | |
324 | *cs++ = 0; | |
325 | intel_ring_advance(req, cs); | |
4772eaeb PZ |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
884ceace | 330 | static int |
9f235dfa | 331 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
884ceace | 332 | { |
9f235dfa | 333 | u32 flags; |
73dec95e | 334 | u32 *cs; |
884ceace | 335 | |
9f235dfa | 336 | cs = intel_ring_begin(req, mode & EMIT_INVALIDATE ? 12 : 6); |
73dec95e TU |
337 | if (IS_ERR(cs)) |
338 | return PTR_ERR(cs); | |
884ceace | 339 | |
9f235dfa | 340 | flags = PIPE_CONTROL_CS_STALL; |
a5f3d68e | 341 | |
7c9cf4e3 | 342 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
343 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
344 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 345 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 346 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 347 | } |
7c9cf4e3 | 348 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
349 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
350 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
351 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
352 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
353 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
354 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
355 | flags |= PIPE_CONTROL_QW_WRITE; | |
356 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
357 | |
358 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
9f235dfa TU |
359 | cs = gen8_emit_pipe_control(cs, |
360 | PIPE_CONTROL_CS_STALL | | |
361 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
362 | 0); | |
a5f3d68e BW |
363 | } |
364 | ||
9f235dfa TU |
365 | cs = gen8_emit_pipe_control(cs, flags, |
366 | i915_ggtt_offset(req->engine->scratch) + | |
367 | 2 * CACHELINE_BYTES); | |
368 | ||
369 | intel_ring_advance(req, cs); | |
370 | ||
371 | return 0; | |
a5f3d68e BW |
372 | } |
373 | ||
0bc40be8 | 374 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 375 | { |
c033666a | 376 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
377 | u32 addr; |
378 | ||
379 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 380 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
381 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
382 | I915_WRITE(HWS_PGA, addr); | |
383 | } | |
384 | ||
0bc40be8 | 385 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 386 | { |
c033666a | 387 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 388 | i915_reg_t mmio; |
af75f269 DL |
389 | |
390 | /* The ring status page addresses are no longer next to the rest of | |
391 | * the ring registers as of gen7. | |
392 | */ | |
c033666a | 393 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 394 | switch (engine->id) { |
af75f269 DL |
395 | case RCS: |
396 | mmio = RENDER_HWS_PGA_GEN7; | |
397 | break; | |
398 | case BCS: | |
399 | mmio = BLT_HWS_PGA_GEN7; | |
400 | break; | |
401 | /* | |
402 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
403 | * gcc switch check warning | |
404 | */ | |
405 | case VCS2: | |
406 | case VCS: | |
407 | mmio = BSD_HWS_PGA_GEN7; | |
408 | break; | |
409 | case VECS: | |
410 | mmio = VEBOX_HWS_PGA_GEN7; | |
411 | break; | |
412 | } | |
c033666a | 413 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 414 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
415 | } else { |
416 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 417 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
418 | } |
419 | ||
57e88531 | 420 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
421 | POSTING_READ(mmio); |
422 | ||
423 | /* | |
424 | * Flush the TLB for this page | |
425 | * | |
426 | * FIXME: These two bits have disappeared on gen8, so a question | |
427 | * arises: do we still need this and if so how should we go about | |
428 | * invalidating the TLB? | |
429 | */ | |
ac657f64 | 430 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 431 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
432 | |
433 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 434 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
435 | |
436 | I915_WRITE(reg, | |
437 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
438 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
439 | if (intel_wait_for_register(dev_priv, |
440 | reg, INSTPM_SYNC_FLUSH, 0, | |
441 | 1000)) | |
af75f269 | 442 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 443 | engine->name); |
af75f269 DL |
444 | } |
445 | } | |
446 | ||
0bc40be8 | 447 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 448 | { |
c033666a | 449 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 450 | |
21a2c58a | 451 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 452 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
453 | if (intel_wait_for_register(dev_priv, |
454 | RING_MI_MODE(engine->mmio_base), | |
455 | MODE_IDLE, | |
456 | MODE_IDLE, | |
457 | 1000)) { | |
0bc40be8 TU |
458 | DRM_ERROR("%s : timed out trying to stop ring\n", |
459 | engine->name); | |
9bec9b13 CW |
460 | /* Sometimes we observe that the idle flag is not |
461 | * set even though the ring is empty. So double | |
462 | * check before giving up. | |
463 | */ | |
0bc40be8 | 464 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 465 | return false; |
9991ae78 CW |
466 | } |
467 | } | |
b7884eb4 | 468 | |
0bc40be8 TU |
469 | I915_WRITE_CTL(engine, 0); |
470 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 471 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 472 | |
21a2c58a | 473 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
474 | (void)I915_READ_CTL(engine); |
475 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 476 | } |
a51435a3 | 477 | |
0bc40be8 | 478 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 479 | } |
8187a2b7 | 480 | |
0bc40be8 | 481 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 482 | { |
c033666a | 483 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 484 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
485 | int ret = 0; |
486 | ||
59bad947 | 487 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 488 | |
0bc40be8 | 489 | if (!stop_ring(engine)) { |
9991ae78 | 490 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
491 | DRM_DEBUG_KMS("%s head not reset to zero " |
492 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
493 | engine->name, |
494 | I915_READ_CTL(engine), | |
495 | I915_READ_HEAD(engine), | |
496 | I915_READ_TAIL(engine), | |
497 | I915_READ_START(engine)); | |
8187a2b7 | 498 | |
0bc40be8 | 499 | if (!stop_ring(engine)) { |
6fd0d56e CW |
500 | DRM_ERROR("failed to set %s head to zero " |
501 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
502 | engine->name, |
503 | I915_READ_CTL(engine), | |
504 | I915_READ_HEAD(engine), | |
505 | I915_READ_TAIL(engine), | |
506 | I915_READ_START(engine)); | |
9991ae78 CW |
507 | ret = -EIO; |
508 | goto out; | |
6fd0d56e | 509 | } |
8187a2b7 ZN |
510 | } |
511 | ||
3177659a | 512 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 513 | ring_setup_phys_status_page(engine); |
3177659a CS |
514 | else |
515 | intel_ring_setup_status_page(engine); | |
9991ae78 | 516 | |
ad07dfcd | 517 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 518 | |
ece4a17d | 519 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 520 | I915_READ_HEAD(engine); |
ece4a17d | 521 | |
0d8957c8 DV |
522 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
523 | * registers with the above sequence (the readback of the HEAD registers | |
524 | * also enforces ordering), otherwise the hw might lose the new ring | |
525 | * register values. */ | |
bde13ebd | 526 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
527 | |
528 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 529 | if (I915_READ_HEAD(engine)) |
95468892 | 530 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 531 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
532 | |
533 | intel_ring_update_space(ring); | |
534 | I915_WRITE_HEAD(engine, ring->head); | |
535 | I915_WRITE_TAIL(engine, ring->tail); | |
536 | (void)I915_READ_TAIL(engine); | |
95468892 | 537 | |
62ae14b1 | 538 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 539 | |
8187a2b7 | 540 | /* If the head is still not zero, the ring is dead */ |
f42bb651 CW |
541 | if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), |
542 | RING_VALID, RING_VALID, | |
543 | 50)) { | |
e74cfed5 | 544 | DRM_ERROR("%s initialization failed " |
821ed7df | 545 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
546 | engine->name, |
547 | I915_READ_CTL(engine), | |
548 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
549 | I915_READ_HEAD(engine), ring->head, |
550 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 551 | I915_READ_START(engine), |
bde13ebd | 552 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
553 | ret = -EIO; |
554 | goto out; | |
8187a2b7 ZN |
555 | } |
556 | ||
fc0768ce | 557 | intel_engine_init_hangcheck(engine); |
50f018df | 558 | |
b7884eb4 | 559 | out: |
59bad947 | 560 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
561 | |
562 | return ret; | |
8187a2b7 ZN |
563 | } |
564 | ||
821ed7df CW |
565 | static void reset_ring_common(struct intel_engine_cs *engine, |
566 | struct drm_i915_gem_request *request) | |
567 | { | |
c0dcb203 CW |
568 | /* Try to restore the logical GPU state to match the continuation |
569 | * of the request queue. If we skip the context/PD restore, then | |
570 | * the next request may try to execute assuming that its context | |
571 | * is valid and loaded on the GPU and so may try to access invalid | |
572 | * memory, prompting repeated GPU hangs. | |
573 | * | |
574 | * If the request was guilty, we still restore the logical state | |
575 | * in case the next request requires it (e.g. the aliasing ppgtt), | |
576 | * but skip over the hung batch. | |
577 | * | |
578 | * If the request was innocent, we try to replay the request with | |
579 | * the restored context. | |
580 | */ | |
581 | if (request) { | |
582 | struct drm_i915_private *dev_priv = request->i915; | |
583 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
584 | struct i915_hw_ppgtt *ppgtt; | |
585 | ||
586 | /* FIXME consider gen8 reset */ | |
587 | ||
588 | if (ce->state) { | |
589 | I915_WRITE(CCID, | |
590 | i915_ggtt_offset(ce->state) | | |
591 | BIT(8) /* must be set! */ | | |
592 | CCID_EXTENDED_STATE_SAVE | | |
593 | CCID_EXTENDED_STATE_RESTORE | | |
594 | CCID_EN); | |
595 | } | |
596 | ||
597 | ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt; | |
598 | if (ppgtt) { | |
599 | u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10; | |
600 | ||
601 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); | |
602 | I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset); | |
603 | ||
604 | /* Wait for the PD reload to complete */ | |
605 | if (intel_wait_for_register(dev_priv, | |
606 | RING_PP_DIR_BASE(engine), | |
607 | BIT(0), 0, | |
608 | 10)) | |
609 | DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n"); | |
821ed7df | 610 | |
c0dcb203 CW |
611 | ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); |
612 | } | |
613 | ||
614 | /* If the rq hung, jump to its breadcrumb and skip the batch */ | |
fe085f13 CW |
615 | if (request->fence.error == -EIO) |
616 | request->ring->head = request->postfix; | |
c0dcb203 CW |
617 | } else { |
618 | engine->legacy_active_context = NULL; | |
619 | } | |
821ed7df CW |
620 | } |
621 | ||
8753181e | 622 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
623 | { |
624 | int ret; | |
625 | ||
e2be4faf | 626 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
627 | if (ret != 0) |
628 | return ret; | |
629 | ||
4e50f082 | 630 | ret = i915_gem_render_state_emit(req); |
8f0e2b9d | 631 | if (ret) |
e26e1b97 | 632 | return ret; |
8f0e2b9d | 633 | |
e26e1b97 | 634 | return 0; |
8f0e2b9d DV |
635 | } |
636 | ||
0bc40be8 | 637 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 638 | { |
c033666a | 639 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 640 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
641 | if (ret) |
642 | return ret; | |
a69ffdbf | 643 | |
61a563a2 | 644 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 645 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 646 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
647 | |
648 | /* We need to disable the AsyncFlip performance optimisations in order | |
649 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
650 | * programmed to '1' on all products. | |
8693a824 | 651 | * |
2441f877 | 652 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 653 | */ |
ac657f64 | 654 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
655 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
656 | ||
f05bb0c7 | 657 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 658 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 659 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 660 | I915_WRITE(GFX_MODE, |
aa83e30d | 661 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 662 | |
01fa0302 | 663 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 664 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 665 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 666 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 667 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 668 | |
c033666a | 669 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
670 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
671 | * "If this bit is set, STCunit will have LRA as replacement | |
672 | * policy. [...] This bit must be reset. LRA replacement | |
673 | * policy is not supported." | |
674 | */ | |
675 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 676 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
677 | } |
678 | ||
ac657f64 | 679 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 680 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 681 | |
035ea405 VS |
682 | if (INTEL_INFO(dev_priv)->gen >= 6) |
683 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 684 | |
0bc40be8 | 685 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
686 | } |
687 | ||
0bc40be8 | 688 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 689 | { |
c033666a | 690 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 691 | |
19880c4a | 692 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
693 | } |
694 | ||
73dec95e | 695 | static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 696 | { |
ad7bdb2b | 697 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 698 | struct intel_engine_cs *waiter; |
c3232b18 | 699 | enum intel_engine_id id; |
3e78998a | 700 | |
3b3f1650 | 701 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 702 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
703 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
704 | continue; | |
705 | ||
73dec95e TU |
706 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
707 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | | |
708 | PIPE_CONTROL_CS_STALL; | |
709 | *cs++ = lower_32_bits(gtt_offset); | |
710 | *cs++ = upper_32_bits(gtt_offset); | |
711 | *cs++ = req->global_seqno; | |
712 | *cs++ = 0; | |
713 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
714 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
715 | *cs++ = 0; | |
3e78998a BW |
716 | } |
717 | ||
73dec95e | 718 | return cs; |
3e78998a BW |
719 | } |
720 | ||
73dec95e | 721 | static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *cs) |
3e78998a | 722 | { |
ad7bdb2b | 723 | struct drm_i915_private *dev_priv = req->i915; |
3e78998a | 724 | struct intel_engine_cs *waiter; |
c3232b18 | 725 | enum intel_engine_id id; |
3e78998a | 726 | |
3b3f1650 | 727 | for_each_engine(waiter, dev_priv, id) { |
ad7bdb2b | 728 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
729 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
730 | continue; | |
731 | ||
73dec95e TU |
732 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
733 | *cs++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT; | |
734 | *cs++ = upper_32_bits(gtt_offset); | |
735 | *cs++ = req->global_seqno; | |
736 | *cs++ = MI_SEMAPHORE_SIGNAL | | |
737 | MI_SEMAPHORE_TARGET(waiter->hw_id); | |
738 | *cs++ = 0; | |
3e78998a BW |
739 | } |
740 | ||
73dec95e | 741 | return cs; |
3e78998a BW |
742 | } |
743 | ||
73dec95e | 744 | static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 745 | { |
ad7bdb2b | 746 | struct drm_i915_private *dev_priv = req->i915; |
318f89ca | 747 | struct intel_engine_cs *engine; |
3b3f1650 | 748 | enum intel_engine_id id; |
caddfe71 | 749 | int num_rings = 0; |
024a43e1 | 750 | |
3b3f1650 | 751 | for_each_engine(engine, dev_priv, id) { |
318f89ca TU |
752 | i915_reg_t mbox_reg; |
753 | ||
754 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
755 | continue; | |
f0f59a00 | 756 | |
318f89ca | 757 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 758 | if (i915_mmio_reg_valid(mbox_reg)) { |
73dec95e TU |
759 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
760 | *cs++ = i915_mmio_reg_offset(mbox_reg); | |
761 | *cs++ = req->global_seqno; | |
caddfe71 | 762 | num_rings++; |
78325f2d BW |
763 | } |
764 | } | |
caddfe71 | 765 | if (num_rings & 1) |
73dec95e | 766 | *cs++ = MI_NOOP; |
024a43e1 | 767 | |
73dec95e | 768 | return cs; |
1ec14ad3 CW |
769 | } |
770 | ||
b0411e7d CW |
771 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
772 | { | |
773 | struct drm_i915_private *dev_priv = request->i915; | |
774 | ||
d55ac5bf CW |
775 | i915_gem_request_submit(request); |
776 | ||
ed1501d4 | 777 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 778 | I915_WRITE_TAIL(request->engine, request->tail); |
b0411e7d CW |
779 | } |
780 | ||
73dec95e | 781 | static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
1ec14ad3 | 782 | { |
73dec95e TU |
783 | *cs++ = MI_STORE_DWORD_INDEX; |
784 | *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT; | |
785 | *cs++ = req->global_seqno; | |
786 | *cs++ = MI_USER_INTERRUPT; | |
1ec14ad3 | 787 | |
73dec95e | 788 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 789 | assert_ring_tail_valid(req->ring, req->tail); |
1ec14ad3 CW |
790 | } |
791 | ||
98f29e8d CW |
792 | static const int i9xx_emit_breadcrumb_sz = 4; |
793 | ||
b0411e7d | 794 | /** |
9b81d556 | 795 | * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers |
b0411e7d CW |
796 | * |
797 | * @request - request to write to the ring | |
798 | * | |
799 | * Update the mailbox registers in the *other* rings with the current seqno. | |
800 | * This acts like a signal in the canonical semaphore. | |
801 | */ | |
73dec95e | 802 | static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) |
b0411e7d | 803 | { |
caddfe71 | 804 | return i9xx_emit_breadcrumb(req, |
73dec95e | 805 | req->engine->semaphore.signal(req, cs)); |
b0411e7d CW |
806 | } |
807 | ||
caddfe71 | 808 | static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, |
73dec95e | 809 | u32 *cs) |
a58c01aa CW |
810 | { |
811 | struct intel_engine_cs *engine = req->engine; | |
9242f974 | 812 | |
caddfe71 | 813 | if (engine->semaphore.signal) |
73dec95e TU |
814 | cs = engine->semaphore.signal(req, cs); |
815 | ||
816 | *cs++ = GFX_OP_PIPE_CONTROL(6); | |
817 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
818 | PIPE_CONTROL_QW_WRITE; | |
819 | *cs++ = intel_hws_seqno_address(engine); | |
820 | *cs++ = 0; | |
821 | *cs++ = req->global_seqno; | |
a58c01aa | 822 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
823 | *cs++ = 0; |
824 | *cs++ = MI_USER_INTERRUPT; | |
825 | *cs++ = MI_NOOP; | |
a58c01aa | 826 | |
73dec95e | 827 | req->tail = intel_ring_offset(req, cs); |
ed1501d4 | 828 | assert_ring_tail_valid(req->ring, req->tail); |
a58c01aa CW |
829 | } |
830 | ||
98f29e8d CW |
831 | static const int gen8_render_emit_breadcrumb_sz = 8; |
832 | ||
c8c99b0f BW |
833 | /** |
834 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
835 | * | |
836 | * @waiter - ring that is waiting | |
837 | * @signaller - ring which has, or will signal | |
838 | * @seqno - seqno which the waiter will block on | |
839 | */ | |
5ee426ca BW |
840 | |
841 | static int | |
ad7bdb2b CW |
842 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
843 | struct drm_i915_gem_request *signal) | |
5ee426ca | 844 | { |
ad7bdb2b CW |
845 | struct drm_i915_private *dev_priv = req->i915; |
846 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 847 | struct i915_hw_ppgtt *ppgtt; |
73dec95e | 848 | u32 *cs; |
5ee426ca | 849 | |
73dec95e TU |
850 | cs = intel_ring_begin(req, 4); |
851 | if (IS_ERR(cs)) | |
852 | return PTR_ERR(cs); | |
5ee426ca | 853 | |
73dec95e TU |
854 | *cs++ = MI_SEMAPHORE_WAIT | MI_SEMAPHORE_GLOBAL_GTT | |
855 | MI_SEMAPHORE_SAD_GTE_SDD; | |
856 | *cs++ = signal->global_seqno; | |
857 | *cs++ = lower_32_bits(offset); | |
858 | *cs++ = upper_32_bits(offset); | |
859 | intel_ring_advance(req, cs); | |
6ef48d7f CW |
860 | |
861 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
862 | * pagetables and we must reload them before executing the batch. | |
863 | * We do this on the i915_switch_context() following the wait and | |
864 | * before the dispatch. | |
865 | */ | |
ad7bdb2b CW |
866 | ppgtt = req->ctx->ppgtt; |
867 | if (ppgtt && req->engine->id != RCS) | |
868 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
869 | return 0; |
870 | } | |
871 | ||
c8c99b0f | 872 | static int |
ad7bdb2b CW |
873 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
874 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 875 | { |
c8c99b0f BW |
876 | u32 dw1 = MI_SEMAPHORE_MBOX | |
877 | MI_SEMAPHORE_COMPARE | | |
878 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 879 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
73dec95e | 880 | u32 *cs; |
1ec14ad3 | 881 | |
ebc348b2 | 882 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 883 | |
73dec95e TU |
884 | cs = intel_ring_begin(req, 4); |
885 | if (IS_ERR(cs)) | |
886 | return PTR_ERR(cs); | |
1ec14ad3 | 887 | |
73dec95e | 888 | *cs++ = dw1 | wait_mbox; |
ddf07be7 CW |
889 | /* Throughout all of the GEM code, seqno passed implies our current |
890 | * seqno is >= the last seqno executed. However for hardware the | |
891 | * comparison is strictly greater than. | |
892 | */ | |
73dec95e TU |
893 | *cs++ = signal->global_seqno - 1; |
894 | *cs++ = 0; | |
895 | *cs++ = MI_NOOP; | |
896 | intel_ring_advance(req, cs); | |
1ec14ad3 CW |
897 | |
898 | return 0; | |
899 | } | |
900 | ||
f8973c21 | 901 | static void |
38a0f2db | 902 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 903 | { |
f8973c21 CW |
904 | /* MI_STORE are internally buffered by the GPU and not flushed |
905 | * either by MI_FLUSH or SyncFlush or any other combination of | |
906 | * MI commands. | |
c6df541c | 907 | * |
f8973c21 CW |
908 | * "Only the submission of the store operation is guaranteed. |
909 | * The write result will be complete (coherent) some time later | |
910 | * (this is practically a finite period but there is no guaranteed | |
911 | * latency)." | |
912 | * | |
913 | * Empirically, we observe that we need a delay of at least 75us to | |
914 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 915 | */ |
f8973c21 | 916 | usleep_range(125, 250); |
c6df541c CW |
917 | } |
918 | ||
c04e0f3b CW |
919 | static void |
920 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 921 | { |
c033666a | 922 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 923 | |
4cd53c0c DV |
924 | /* Workaround to force correct ordering between irq and seqno writes on |
925 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
926 | * ACTHD) before reading the status page. |
927 | * | |
928 | * Note that this effectively stalls the read by the time it takes to | |
929 | * do a memory transaction, which more or less ensures that the write | |
930 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
931 | * Alternatively we could delay the interrupt from the CS ring to give | |
932 | * the write time to land, but that would incur a delay after every | |
933 | * batch i.e. much more frequent than a delay when waiting for the | |
934 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
935 | * |
936 | * Also note that to prevent whole machine hangs on gen7, we have to | |
937 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 938 | */ |
bcbdb6d0 | 939 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 940 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 941 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
942 | } |
943 | ||
31bb59cc CW |
944 | static void |
945 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 946 | { |
31bb59cc | 947 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
948 | } |
949 | ||
950 | static void | |
31bb59cc | 951 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 952 | { |
31bb59cc | 953 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
954 | } |
955 | ||
31bb59cc CW |
956 | static void |
957 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 958 | { |
c033666a | 959 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 960 | |
31bb59cc CW |
961 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
962 | I915_WRITE(IMR, dev_priv->irq_mask); | |
963 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
964 | } |
965 | ||
8187a2b7 | 966 | static void |
31bb59cc | 967 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 968 | { |
c033666a | 969 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 970 | |
31bb59cc CW |
971 | dev_priv->irq_mask |= engine->irq_enable_mask; |
972 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
973 | } |
974 | ||
31bb59cc CW |
975 | static void |
976 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 977 | { |
c033666a | 978 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 979 | |
31bb59cc CW |
980 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
981 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
982 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
983 | } |
984 | ||
985 | static void | |
31bb59cc | 986 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 987 | { |
c033666a | 988 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 989 | |
31bb59cc CW |
990 | dev_priv->irq_mask |= engine->irq_enable_mask; |
991 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
992 | } |
993 | ||
b72f3acb | 994 | static int |
7c9cf4e3 | 995 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 996 | { |
73dec95e | 997 | u32 *cs; |
b72f3acb | 998 | |
73dec95e TU |
999 | cs = intel_ring_begin(req, 2); |
1000 | if (IS_ERR(cs)) | |
1001 | return PTR_ERR(cs); | |
b72f3acb | 1002 | |
73dec95e TU |
1003 | *cs++ = MI_FLUSH; |
1004 | *cs++ = MI_NOOP; | |
1005 | intel_ring_advance(req, cs); | |
b72f3acb | 1006 | return 0; |
d1b851fc ZN |
1007 | } |
1008 | ||
31bb59cc CW |
1009 | static void |
1010 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1011 | { |
c033666a | 1012 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1013 | |
61ff75ac CW |
1014 | I915_WRITE_IMR(engine, |
1015 | ~(engine->irq_enable_mask | | |
1016 | engine->irq_keep_mask)); | |
31bb59cc | 1017 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1018 | } |
1019 | ||
1020 | static void | |
31bb59cc | 1021 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1022 | { |
c033666a | 1023 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1024 | |
61ff75ac | 1025 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1026 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1027 | } |
1028 | ||
31bb59cc CW |
1029 | static void |
1030 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1031 | { |
c033666a | 1032 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1033 | |
31bb59cc | 1034 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
f4e9af4f | 1035 | gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1036 | } |
1037 | ||
1038 | static void | |
31bb59cc | 1039 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1040 | { |
c033666a | 1041 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1042 | |
31bb59cc | 1043 | I915_WRITE_IMR(engine, ~0); |
f4e9af4f | 1044 | gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); |
a19d2933 BW |
1045 | } |
1046 | ||
31bb59cc CW |
1047 | static void |
1048 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1049 | { |
c033666a | 1050 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1051 | |
61ff75ac CW |
1052 | I915_WRITE_IMR(engine, |
1053 | ~(engine->irq_enable_mask | | |
1054 | engine->irq_keep_mask)); | |
31bb59cc | 1055 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1056 | } |
1057 | ||
1058 | static void | |
31bb59cc | 1059 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1060 | { |
c033666a | 1061 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1062 | |
61ff75ac | 1063 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1064 | } |
1065 | ||
d1b851fc | 1066 | static int |
803688ba CW |
1067 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1068 | u64 offset, u32 length, | |
1069 | unsigned int dispatch_flags) | |
d1b851fc | 1070 | { |
73dec95e | 1071 | u32 *cs; |
78501eac | 1072 | |
73dec95e TU |
1073 | cs = intel_ring_begin(req, 2); |
1074 | if (IS_ERR(cs)) | |
1075 | return PTR_ERR(cs); | |
e1f99ce6 | 1076 | |
73dec95e TU |
1077 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags & |
1078 | I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965); | |
1079 | *cs++ = offset; | |
1080 | intel_ring_advance(req, cs); | |
78501eac | 1081 | |
d1b851fc ZN |
1082 | return 0; |
1083 | } | |
1084 | ||
b45305fc DV |
1085 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1086 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1087 | #define I830_TLB_ENTRIES (2) |
1088 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1089 | static int |
803688ba CW |
1090 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1091 | u64 offset, u32 len, | |
1092 | unsigned int dispatch_flags) | |
62fdfeaf | 1093 | { |
73dec95e | 1094 | u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); |
62fdfeaf | 1095 | |
73dec95e TU |
1096 | cs = intel_ring_begin(req, 6); |
1097 | if (IS_ERR(cs)) | |
1098 | return PTR_ERR(cs); | |
62fdfeaf | 1099 | |
c4d69da1 | 1100 | /* Evict the invalid PTE TLBs */ |
73dec95e TU |
1101 | *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; |
1102 | *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096; | |
1103 | *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */ | |
1104 | *cs++ = cs_offset; | |
1105 | *cs++ = 0xdeadbeef; | |
1106 | *cs++ = MI_NOOP; | |
1107 | intel_ring_advance(req, cs); | |
b45305fc | 1108 | |
8e004efc | 1109 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1110 | if (len > I830_BATCH_LIMIT) |
1111 | return -ENOSPC; | |
1112 | ||
73dec95e TU |
1113 | cs = intel_ring_begin(req, 6 + 2); |
1114 | if (IS_ERR(cs)) | |
1115 | return PTR_ERR(cs); | |
c4d69da1 CW |
1116 | |
1117 | /* Blit the batch (which has now all relocs applied) to the | |
1118 | * stable batch scratch bo area (so that the CS never | |
1119 | * stumbles over its tlb invalidation bug) ... | |
1120 | */ | |
73dec95e TU |
1121 | *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA; |
1122 | *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096; | |
1123 | *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096; | |
1124 | *cs++ = cs_offset; | |
1125 | *cs++ = 4096; | |
1126 | *cs++ = offset; | |
1127 | ||
1128 | *cs++ = MI_FLUSH; | |
1129 | *cs++ = MI_NOOP; | |
1130 | intel_ring_advance(req, cs); | |
b45305fc DV |
1131 | |
1132 | /* ... and execute it. */ | |
c4d69da1 | 1133 | offset = cs_offset; |
b45305fc | 1134 | } |
e1f99ce6 | 1135 | |
73dec95e TU |
1136 | cs = intel_ring_begin(req, 2); |
1137 | if (IS_ERR(cs)) | |
1138 | return PTR_ERR(cs); | |
c4d69da1 | 1139 | |
73dec95e TU |
1140 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1141 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1142 | MI_BATCH_NON_SECURE); | |
1143 | intel_ring_advance(req, cs); | |
c4d69da1 | 1144 | |
fb3256da DV |
1145 | return 0; |
1146 | } | |
1147 | ||
1148 | static int | |
803688ba CW |
1149 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1150 | u64 offset, u32 len, | |
1151 | unsigned int dispatch_flags) | |
fb3256da | 1152 | { |
73dec95e | 1153 | u32 *cs; |
fb3256da | 1154 | |
73dec95e TU |
1155 | cs = intel_ring_begin(req, 2); |
1156 | if (IS_ERR(cs)) | |
1157 | return PTR_ERR(cs); | |
fb3256da | 1158 | |
73dec95e TU |
1159 | *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT; |
1160 | *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 : | |
1161 | MI_BATCH_NON_SECURE); | |
1162 | intel_ring_advance(req, cs); | |
62fdfeaf | 1163 | |
62fdfeaf EA |
1164 | return 0; |
1165 | } | |
1166 | ||
0bc40be8 | 1167 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1168 | { |
c033666a | 1169 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1170 | |
1171 | if (!dev_priv->status_page_dmah) | |
1172 | return; | |
1173 | ||
91c8a326 | 1174 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1175 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1176 | } |
1177 | ||
0bc40be8 | 1178 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1179 | { |
57e88531 | 1180 | struct i915_vma *vma; |
f8a7fde4 | 1181 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1182 | |
57e88531 CW |
1183 | vma = fetch_and_zero(&engine->status_page.vma); |
1184 | if (!vma) | |
62fdfeaf | 1185 | return; |
62fdfeaf | 1186 | |
f8a7fde4 CW |
1187 | obj = vma->obj; |
1188 | ||
57e88531 | 1189 | i915_vma_unpin(vma); |
f8a7fde4 CW |
1190 | i915_vma_close(vma); |
1191 | ||
1192 | i915_gem_object_unpin_map(obj); | |
1193 | __i915_gem_object_release_unless_active(obj); | |
62fdfeaf EA |
1194 | } |
1195 | ||
0bc40be8 | 1196 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1197 | { |
57e88531 CW |
1198 | struct drm_i915_gem_object *obj; |
1199 | struct i915_vma *vma; | |
1200 | unsigned int flags; | |
920cf419 | 1201 | void *vaddr; |
57e88531 | 1202 | int ret; |
e4ffd173 | 1203 | |
f51455d4 | 1204 | obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE); |
57e88531 CW |
1205 | if (IS_ERR(obj)) { |
1206 | DRM_ERROR("Failed to allocate status page\n"); | |
1207 | return PTR_ERR(obj); | |
1208 | } | |
62fdfeaf | 1209 | |
57e88531 CW |
1210 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1211 | if (ret) | |
1212 | goto err; | |
e3efda49 | 1213 | |
a01cb37a | 1214 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
57e88531 CW |
1215 | if (IS_ERR(vma)) { |
1216 | ret = PTR_ERR(vma); | |
1217 | goto err; | |
e3efda49 | 1218 | } |
62fdfeaf | 1219 | |
57e88531 CW |
1220 | flags = PIN_GLOBAL; |
1221 | if (!HAS_LLC(engine->i915)) | |
1222 | /* On g33, we cannot place HWS above 256MiB, so | |
1223 | * restrict its pinning to the low mappable arena. | |
1224 | * Though this restriction is not documented for | |
1225 | * gen4, gen5, or byt, they also behave similarly | |
1226 | * and hang if the HWS is placed at the top of the | |
1227 | * GTT. To generalise, it appears that all !llc | |
1228 | * platforms have issues with us placing the HWS | |
1229 | * above the mappable region (even though we never | |
1230 | * actualy map it). | |
1231 | */ | |
1232 | flags |= PIN_MAPPABLE; | |
1233 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1234 | if (ret) | |
1235 | goto err; | |
62fdfeaf | 1236 | |
920cf419 CW |
1237 | vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); |
1238 | if (IS_ERR(vaddr)) { | |
1239 | ret = PTR_ERR(vaddr); | |
1240 | goto err_unpin; | |
1241 | } | |
1242 | ||
57e88531 | 1243 | engine->status_page.vma = vma; |
bde13ebd | 1244 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
f51455d4 | 1245 | engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE); |
62fdfeaf | 1246 | |
bde13ebd CW |
1247 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1248 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1249 | return 0; |
57e88531 | 1250 | |
920cf419 CW |
1251 | err_unpin: |
1252 | i915_vma_unpin(vma); | |
57e88531 CW |
1253 | err: |
1254 | i915_gem_object_put(obj); | |
1255 | return ret; | |
62fdfeaf EA |
1256 | } |
1257 | ||
0bc40be8 | 1258 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1259 | { |
c033666a | 1260 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1261 | |
1a5788bf CW |
1262 | GEM_BUG_ON(engine->id != RCS); |
1263 | ||
57e88531 CW |
1264 | dev_priv->status_page_dmah = |
1265 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1266 | if (!dev_priv->status_page_dmah) | |
1267 | return -ENOMEM; | |
6b8294a4 | 1268 | |
0bc40be8 TU |
1269 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1270 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1271 | |
1272 | return 0; | |
1273 | } | |
1274 | ||
d822bb18 CW |
1275 | int intel_ring_pin(struct intel_ring *ring, |
1276 | struct drm_i915_private *i915, | |
1277 | unsigned int offset_bias) | |
7ba717cf | 1278 | { |
d822bb18 | 1279 | enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; |
57e88531 | 1280 | struct i915_vma *vma = ring->vma; |
d822bb18 | 1281 | unsigned int flags; |
8305216f | 1282 | void *addr; |
7ba717cf TD |
1283 | int ret; |
1284 | ||
57e88531 | 1285 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1286 | |
9d80841e | 1287 | |
d3ef1af6 DCS |
1288 | flags = PIN_GLOBAL; |
1289 | if (offset_bias) | |
1290 | flags |= PIN_OFFSET_BIAS | offset_bias; | |
9d80841e | 1291 | if (vma->obj->stolen) |
57e88531 | 1292 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1293 | |
57e88531 | 1294 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1295 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1296 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1297 | else | |
1298 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1299 | if (unlikely(ret)) | |
def0c5f6 | 1300 | return ret; |
57e88531 | 1301 | } |
7ba717cf | 1302 | |
57e88531 CW |
1303 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1304 | if (unlikely(ret)) | |
1305 | return ret; | |
def0c5f6 | 1306 | |
9d80841e | 1307 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1308 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1309 | else | |
9d80841e | 1310 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1311 | if (IS_ERR(addr)) |
1312 | goto err; | |
7ba717cf | 1313 | |
32c04f16 | 1314 | ring->vaddr = addr; |
7ba717cf | 1315 | return 0; |
d2cad535 | 1316 | |
57e88531 CW |
1317 | err: |
1318 | i915_vma_unpin(vma); | |
1319 | return PTR_ERR(addr); | |
7ba717cf TD |
1320 | } |
1321 | ||
aad29fbb CW |
1322 | void intel_ring_unpin(struct intel_ring *ring) |
1323 | { | |
1324 | GEM_BUG_ON(!ring->vma); | |
1325 | GEM_BUG_ON(!ring->vaddr); | |
1326 | ||
9d80841e | 1327 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1328 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1329 | else |
1330 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1331 | ring->vaddr = NULL; |
1332 | ||
57e88531 | 1333 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1334 | } |
1335 | ||
57e88531 CW |
1336 | static struct i915_vma * |
1337 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1338 | { |
05394f39 | 1339 | struct drm_i915_gem_object *obj; |
57e88531 | 1340 | struct i915_vma *vma; |
62fdfeaf | 1341 | |
187685cb | 1342 | obj = i915_gem_object_create_stolen(dev_priv, size); |
c58b735f | 1343 | if (!obj) |
2d6c4c84 | 1344 | obj = i915_gem_object_create_internal(dev_priv, size); |
57e88531 CW |
1345 | if (IS_ERR(obj)) |
1346 | return ERR_CAST(obj); | |
8187a2b7 | 1347 | |
24f3a8cf AG |
1348 | /* mark ring buffers as read-only from GPU side by default */ |
1349 | obj->gt_ro = 1; | |
1350 | ||
a01cb37a | 1351 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
57e88531 CW |
1352 | if (IS_ERR(vma)) |
1353 | goto err; | |
1354 | ||
1355 | return vma; | |
e3efda49 | 1356 | |
57e88531 CW |
1357 | err: |
1358 | i915_gem_object_put(obj); | |
1359 | return vma; | |
e3efda49 CW |
1360 | } |
1361 | ||
7e37f889 CW |
1362 | struct intel_ring * |
1363 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1364 | { |
7e37f889 | 1365 | struct intel_ring *ring; |
57e88531 | 1366 | struct i915_vma *vma; |
01101fa7 | 1367 | |
8f942018 | 1368 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1369 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1370 | |
01101fa7 | 1371 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1372 | if (!ring) |
01101fa7 CW |
1373 | return ERR_PTR(-ENOMEM); |
1374 | ||
675d9ad7 CW |
1375 | INIT_LIST_HEAD(&ring->request_list); |
1376 | ||
01101fa7 CW |
1377 | ring->size = size; |
1378 | /* Workaround an erratum on the i830 which causes a hang if | |
1379 | * the TAIL pointer points to within the last 2 cachelines | |
1380 | * of the buffer. | |
1381 | */ | |
1382 | ring->effective_size = size; | |
2a307c2e | 1383 | if (IS_I830(engine->i915) || IS_I845G(engine->i915)) |
01101fa7 CW |
1384 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1385 | ||
01101fa7 CW |
1386 | intel_ring_update_space(ring); |
1387 | ||
57e88531 CW |
1388 | vma = intel_ring_create_vma(engine->i915, size); |
1389 | if (IS_ERR(vma)) { | |
01101fa7 | 1390 | kfree(ring); |
57e88531 | 1391 | return ERR_CAST(vma); |
01101fa7 | 1392 | } |
57e88531 | 1393 | ring->vma = vma; |
01101fa7 CW |
1394 | |
1395 | return ring; | |
1396 | } | |
1397 | ||
1398 | void | |
7e37f889 | 1399 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1400 | { |
f8a7fde4 CW |
1401 | struct drm_i915_gem_object *obj = ring->vma->obj; |
1402 | ||
1403 | i915_vma_close(ring->vma); | |
1404 | __i915_gem_object_release_unless_active(obj); | |
1405 | ||
01101fa7 CW |
1406 | kfree(ring); |
1407 | } | |
1408 | ||
72b72ae4 | 1409 | static int context_pin(struct i915_gem_context *ctx) |
e8a9c58f CW |
1410 | { |
1411 | struct i915_vma *vma = ctx->engine[RCS].state; | |
1412 | int ret; | |
1413 | ||
1414 | /* Clear this page out of any CPU caches for coherent swap-in/out. | |
1415 | * We only want to do this on the first bind so that we do not stall | |
1416 | * on an active context (which by nature is already on the GPU). | |
1417 | */ | |
1418 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { | |
1419 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, false); | |
1420 | if (ret) | |
1421 | return ret; | |
1422 | } | |
1423 | ||
afeddf50 CW |
1424 | return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT, |
1425 | PIN_GLOBAL | PIN_HIGH); | |
e8a9c58f CW |
1426 | } |
1427 | ||
1428 | static int intel_ring_context_pin(struct intel_engine_cs *engine, | |
1429 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1430 | { |
1431 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1432 | int ret; | |
1433 | ||
91c8a326 | 1434 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
1435 | |
1436 | if (ce->pin_count++) | |
1437 | return 0; | |
a533b4ba | 1438 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
0cb26a8e CW |
1439 | |
1440 | if (ce->state) { | |
72b72ae4 | 1441 | ret = context_pin(ctx); |
e8a9c58f | 1442 | if (ret) |
0cb26a8e | 1443 | goto error; |
5d4bac55 CW |
1444 | |
1445 | ce->state->obj->mm.dirty = true; | |
0cb26a8e CW |
1446 | } |
1447 | ||
c7c3c07d CW |
1448 | /* The kernel context is only used as a placeholder for flushing the |
1449 | * active context. It is never used for submitting user rendering and | |
1450 | * as such never requires the golden render context, and so we can skip | |
1451 | * emitting it when we switch to the kernel context. This is required | |
1452 | * as during eviction we cannot allocate and pin the renderstate in | |
1453 | * order to initialise the context. | |
1454 | */ | |
984ff29f | 1455 | if (i915_gem_context_is_kernel(ctx)) |
c7c3c07d CW |
1456 | ce->initialised = true; |
1457 | ||
9a6feaf0 | 1458 | i915_gem_context_get(ctx); |
0cb26a8e CW |
1459 | return 0; |
1460 | ||
1461 | error: | |
1462 | ce->pin_count = 0; | |
1463 | return ret; | |
1464 | } | |
1465 | ||
e8a9c58f CW |
1466 | static void intel_ring_context_unpin(struct intel_engine_cs *engine, |
1467 | struct i915_gem_context *ctx) | |
0cb26a8e CW |
1468 | { |
1469 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1470 | ||
91c8a326 | 1471 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
e8a9c58f | 1472 | GEM_BUG_ON(ce->pin_count == 0); |
0cb26a8e CW |
1473 | |
1474 | if (--ce->pin_count) | |
1475 | return; | |
1476 | ||
1477 | if (ce->state) | |
bf3783e5 | 1478 | i915_vma_unpin(ce->state); |
0cb26a8e | 1479 | |
9a6feaf0 | 1480 | i915_gem_context_put(ctx); |
0cb26a8e CW |
1481 | } |
1482 | ||
acd27845 | 1483 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 1484 | { |
32c04f16 | 1485 | struct intel_ring *ring; |
1a5788bf | 1486 | int err; |
bfc882b4 | 1487 | |
019bf277 TU |
1488 | intel_engine_setup_common(engine); |
1489 | ||
1a5788bf CW |
1490 | err = intel_engine_init_common(engine); |
1491 | if (err) | |
1492 | goto err; | |
e3efda49 | 1493 | |
1a5788bf CW |
1494 | if (HWS_NEEDS_PHYSICAL(engine->i915)) |
1495 | err = init_phys_status_page(engine); | |
1496 | else | |
1497 | err = init_status_page(engine); | |
1498 | if (err) | |
1499 | goto err; | |
e3efda49 | 1500 | |
d822bb18 CW |
1501 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
1502 | if (IS_ERR(ring)) { | |
1a5788bf CW |
1503 | err = PTR_ERR(ring); |
1504 | goto err_hws; | |
d822bb18 CW |
1505 | } |
1506 | ||
d3ef1af6 | 1507 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
1a5788bf CW |
1508 | err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); |
1509 | if (err) | |
1510 | goto err_ring; | |
1511 | ||
1512 | GEM_BUG_ON(engine->buffer); | |
57e88531 | 1513 | engine->buffer = ring; |
62fdfeaf | 1514 | |
8ee14975 | 1515 | return 0; |
351e3db2 | 1516 | |
1a5788bf CW |
1517 | err_ring: |
1518 | intel_ring_free(ring); | |
1519 | err_hws: | |
1520 | if (HWS_NEEDS_PHYSICAL(engine->i915)) | |
1521 | cleanup_phys_status_page(engine); | |
1522 | else | |
1523 | cleanup_status_page(engine); | |
1524 | err: | |
1525 | intel_engine_cleanup_common(engine); | |
1526 | return err; | |
62fdfeaf EA |
1527 | } |
1528 | ||
7e37f889 | 1529 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 1530 | { |
1a5788bf | 1531 | struct drm_i915_private *dev_priv = engine->i915; |
6402c330 | 1532 | |
1a5788bf CW |
1533 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
1534 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 1535 | |
1a5788bf CW |
1536 | intel_ring_unpin(engine->buffer); |
1537 | intel_ring_free(engine->buffer); | |
78501eac | 1538 | |
0bc40be8 TU |
1539 | if (engine->cleanup) |
1540 | engine->cleanup(engine); | |
8d19215b | 1541 | |
1a5788bf | 1542 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 1543 | cleanup_phys_status_page(engine); |
1a5788bf | 1544 | else |
3177659a | 1545 | cleanup_status_page(engine); |
44e895a8 | 1546 | |
96a945aa | 1547 | intel_engine_cleanup_common(engine); |
0cb26a8e | 1548 | |
3b3f1650 AG |
1549 | dev_priv->engine[engine->id] = NULL; |
1550 | kfree(engine); | |
62fdfeaf EA |
1551 | } |
1552 | ||
821ed7df CW |
1553 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
1554 | { | |
1555 | struct intel_engine_cs *engine; | |
3b3f1650 | 1556 | enum intel_engine_id id; |
821ed7df | 1557 | |
fe085f13 | 1558 | for_each_engine(engine, dev_priv, id) |
821ed7df | 1559 | engine->buffer->head = engine->buffer->tail; |
821ed7df CW |
1560 | } |
1561 | ||
f73e7399 | 1562 | static int ring_request_alloc(struct drm_i915_gem_request *request) |
9d773091 | 1563 | { |
73dec95e | 1564 | u32 *cs; |
6310346e | 1565 | |
e8a9c58f CW |
1566 | GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count); |
1567 | ||
6310346e CW |
1568 | /* Flush enough space to reduce the likelihood of waiting after |
1569 | * we start building the request - in which case we will just | |
1570 | * have to repeat work. | |
1571 | */ | |
a0442461 | 1572 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 1573 | |
e8a9c58f | 1574 | GEM_BUG_ON(!request->engine->buffer); |
1dae2dfb | 1575 | request->ring = request->engine->buffer; |
6310346e | 1576 | |
73dec95e TU |
1577 | cs = intel_ring_begin(request, 0); |
1578 | if (IS_ERR(cs)) | |
1579 | return PTR_ERR(cs); | |
6310346e | 1580 | |
a0442461 | 1581 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 1582 | return 0; |
9d773091 CW |
1583 | } |
1584 | ||
987046ad CW |
1585 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
1586 | { | |
7e37f889 | 1587 | struct intel_ring *ring = req->ring; |
987046ad | 1588 | struct drm_i915_gem_request *target; |
e95433c7 CW |
1589 | long timeout; |
1590 | ||
1591 | lockdep_assert_held(&req->i915->drm.struct_mutex); | |
987046ad | 1592 | |
1dae2dfb CW |
1593 | intel_ring_update_space(ring); |
1594 | if (ring->space >= bytes) | |
987046ad CW |
1595 | return 0; |
1596 | ||
1597 | /* | |
1598 | * Space is reserved in the ringbuffer for finalising the request, | |
1599 | * as that cannot be allowed to fail. During request finalisation, | |
1600 | * reserved_space is set to 0 to stop the overallocation and the | |
1601 | * assumption is that then we never need to wait (which has the | |
1602 | * risk of failing with EINTR). | |
1603 | * | |
1604 | * See also i915_gem_request_alloc() and i915_add_request(). | |
1605 | */ | |
0251a963 | 1606 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 1607 | |
675d9ad7 | 1608 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
1609 | unsigned space; |
1610 | ||
987046ad | 1611 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
1612 | space = __intel_ring_space(target->postfix, ring->tail, |
1613 | ring->size); | |
987046ad CW |
1614 | if (space >= bytes) |
1615 | break; | |
79bbcc29 | 1616 | } |
29b1b415 | 1617 | |
675d9ad7 | 1618 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
1619 | return -ENOSPC; |
1620 | ||
e95433c7 CW |
1621 | timeout = i915_wait_request(target, |
1622 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
1623 | MAX_SCHEDULE_TIMEOUT); | |
1624 | if (timeout < 0) | |
1625 | return timeout; | |
7da844c5 | 1626 | |
7da844c5 CW |
1627 | i915_gem_request_retire_upto(target); |
1628 | ||
1629 | intel_ring_update_space(ring); | |
1630 | GEM_BUG_ON(ring->space < bytes); | |
1631 | return 0; | |
29b1b415 JH |
1632 | } |
1633 | ||
73dec95e | 1634 | u32 *intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 1635 | { |
7e37f889 | 1636 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
1637 | int remain_actual = ring->size - ring->tail; |
1638 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
1639 | int bytes = num_dwords * sizeof(u32); |
1640 | int total_bytes, wait_bytes; | |
79bbcc29 | 1641 | bool need_wrap = false; |
73dec95e | 1642 | u32 *cs; |
29b1b415 | 1643 | |
0251a963 | 1644 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 1645 | |
79bbcc29 JH |
1646 | if (unlikely(bytes > remain_usable)) { |
1647 | /* | |
1648 | * Not enough space for the basic request. So need to flush | |
1649 | * out the remainder and then wait for base + reserved. | |
1650 | */ | |
1651 | wait_bytes = remain_actual + total_bytes; | |
1652 | need_wrap = true; | |
987046ad CW |
1653 | } else if (unlikely(total_bytes > remain_usable)) { |
1654 | /* | |
1655 | * The base request will fit but the reserved space | |
1656 | * falls off the end. So we don't need an immediate wrap | |
1657 | * and only need to effectively wait for the reserved | |
1658 | * size space from the start of ringbuffer. | |
1659 | */ | |
0251a963 | 1660 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 1661 | } else { |
987046ad CW |
1662 | /* No wrapping required, just waiting. */ |
1663 | wait_bytes = total_bytes; | |
cbcc80df MK |
1664 | } |
1665 | ||
1dae2dfb | 1666 | if (wait_bytes > ring->space) { |
987046ad | 1667 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df | 1668 | if (unlikely(ret)) |
73dec95e | 1669 | return ERR_PTR(ret); |
cbcc80df MK |
1670 | } |
1671 | ||
987046ad | 1672 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
1673 | GEM_BUG_ON(remain_actual > ring->space); |
1674 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 1675 | |
987046ad | 1676 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
1677 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
1678 | ring->tail = 0; | |
1679 | ring->space -= remain_actual; | |
987046ad | 1680 | } |
304d695c | 1681 | |
73dec95e TU |
1682 | GEM_BUG_ON(ring->tail > ring->size - bytes); |
1683 | cs = ring->vaddr + ring->tail; | |
1684 | ring->tail += bytes; | |
1dae2dfb CW |
1685 | ring->space -= bytes; |
1686 | GEM_BUG_ON(ring->space < 0); | |
73dec95e TU |
1687 | |
1688 | return cs; | |
8187a2b7 | 1689 | } |
78501eac | 1690 | |
753b1ad4 | 1691 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 1692 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 1693 | { |
b5321f30 | 1694 | int num_dwords = |
73dec95e TU |
1695 | (req->ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
1696 | u32 *cs; | |
753b1ad4 VS |
1697 | |
1698 | if (num_dwords == 0) | |
1699 | return 0; | |
1700 | ||
18393f63 | 1701 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
73dec95e TU |
1702 | cs = intel_ring_begin(req, num_dwords); |
1703 | if (IS_ERR(cs)) | |
1704 | return PTR_ERR(cs); | |
753b1ad4 VS |
1705 | |
1706 | while (num_dwords--) | |
73dec95e | 1707 | *cs++ = MI_NOOP; |
753b1ad4 | 1708 | |
73dec95e | 1709 | intel_ring_advance(req, cs); |
753b1ad4 VS |
1710 | |
1711 | return 0; | |
1712 | } | |
1713 | ||
c5efa1ad | 1714 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 1715 | { |
c5efa1ad | 1716 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 1717 | |
76f8421f CW |
1718 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
1719 | ||
881f47b6 | 1720 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
1721 | |
1722 | /* Disable notification that the ring is IDLE. The GT | |
1723 | * will then assume that it is busy and bring it out of rc6. | |
1724 | */ | |
76f8421f CW |
1725 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1726 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
1727 | |
1728 | /* Clear the context id. Here be magic! */ | |
76f8421f | 1729 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 1730 | |
12f55818 | 1731 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
02b312d0 CW |
1732 | if (__intel_wait_for_register_fw(dev_priv, |
1733 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1734 | GEN6_BSD_SLEEP_INDICATOR, | |
1735 | 0, | |
1736 | 1000, 0, NULL)) | |
12f55818 | 1737 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 1738 | |
12f55818 | 1739 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 1740 | i9xx_submit_request(request); |
12f55818 CW |
1741 | |
1742 | /* Let the ring send IDLE messages to the GT again, | |
1743 | * and so let it sleep to conserve power when idle. | |
1744 | */ | |
76f8421f CW |
1745 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1746 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
1747 | ||
1748 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
1749 | } |
1750 | ||
7c9cf4e3 | 1751 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 1752 | { |
73dec95e | 1753 | u32 cmd, *cs; |
b72f3acb | 1754 | |
73dec95e TU |
1755 | cs = intel_ring_begin(req, 4); |
1756 | if (IS_ERR(cs)) | |
1757 | return PTR_ERR(cs); | |
b72f3acb | 1758 | |
71a77e07 | 1759 | cmd = MI_FLUSH_DW; |
c033666a | 1760 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1761 | cmd += 1; |
f0a1fb10 CW |
1762 | |
1763 | /* We always require a command barrier so that subsequent | |
1764 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1765 | * wrt the contents of the write cache being flushed to memory | |
1766 | * (and thus being coherent from the CPU). | |
1767 | */ | |
1768 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1769 | ||
9a289771 JB |
1770 | /* |
1771 | * Bspec vol 1c.5 - video engine command streamer: | |
1772 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1773 | * operation is complete. This bit is only valid when the | |
1774 | * Post-Sync Operation field is a value of 1h or 3h." | |
1775 | */ | |
7c9cf4e3 | 1776 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
1777 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
1778 | ||
73dec95e TU |
1779 | *cs++ = cmd; |
1780 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1781 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1782 | *cs++ = 0; /* upper addr */ |
1783 | *cs++ = 0; /* value */ | |
075b3bba | 1784 | } else { |
73dec95e TU |
1785 | *cs++ = 0; |
1786 | *cs++ = MI_NOOP; | |
075b3bba | 1787 | } |
73dec95e | 1788 | intel_ring_advance(req, cs); |
b72f3acb | 1789 | return 0; |
881f47b6 XH |
1790 | } |
1791 | ||
1c7a0623 | 1792 | static int |
803688ba CW |
1793 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
1794 | u64 offset, u32 len, | |
1795 | unsigned int dispatch_flags) | |
1c7a0623 | 1796 | { |
b5321f30 | 1797 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 1798 | !(dispatch_flags & I915_DISPATCH_SECURE); |
73dec95e | 1799 | u32 *cs; |
1c7a0623 | 1800 | |
73dec95e TU |
1801 | cs = intel_ring_begin(req, 4); |
1802 | if (IS_ERR(cs)) | |
1803 | return PTR_ERR(cs); | |
1c7a0623 BW |
1804 | |
1805 | /* FIXME(BDW): Address space and security selectors. */ | |
73dec95e TU |
1806 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags & |
1807 | I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
1808 | *cs++ = lower_32_bits(offset); | |
1809 | *cs++ = upper_32_bits(offset); | |
1810 | *cs++ = MI_NOOP; | |
1811 | intel_ring_advance(req, cs); | |
1c7a0623 BW |
1812 | |
1813 | return 0; | |
1814 | } | |
1815 | ||
d7d4eedd | 1816 | static int |
803688ba CW |
1817 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
1818 | u64 offset, u32 len, | |
1819 | unsigned int dispatch_flags) | |
d7d4eedd | 1820 | { |
73dec95e | 1821 | u32 *cs; |
d7d4eedd | 1822 | |
73dec95e TU |
1823 | cs = intel_ring_begin(req, 2); |
1824 | if (IS_ERR(cs)) | |
1825 | return PTR_ERR(cs); | |
d7d4eedd | 1826 | |
73dec95e TU |
1827 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1828 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | | |
1829 | (dispatch_flags & I915_DISPATCH_RS ? | |
1830 | MI_BATCH_RESOURCE_STREAMER : 0); | |
d7d4eedd | 1831 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1832 | *cs++ = offset; |
1833 | intel_ring_advance(req, cs); | |
d7d4eedd CW |
1834 | |
1835 | return 0; | |
1836 | } | |
1837 | ||
881f47b6 | 1838 | static int |
803688ba CW |
1839 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
1840 | u64 offset, u32 len, | |
1841 | unsigned int dispatch_flags) | |
881f47b6 | 1842 | { |
73dec95e | 1843 | u32 *cs; |
ab6f8e32 | 1844 | |
73dec95e TU |
1845 | cs = intel_ring_begin(req, 2); |
1846 | if (IS_ERR(cs)) | |
1847 | return PTR_ERR(cs); | |
e1f99ce6 | 1848 | |
73dec95e TU |
1849 | *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ? |
1850 | 0 : MI_BATCH_NON_SECURE_I965); | |
0206e353 | 1851 | /* bit0-7 is the length on GEN6+ */ |
73dec95e TU |
1852 | *cs++ = offset; |
1853 | intel_ring_advance(req, cs); | |
ab6f8e32 | 1854 | |
0206e353 | 1855 | return 0; |
881f47b6 XH |
1856 | } |
1857 | ||
549f7365 CW |
1858 | /* Blitter support (SandyBridge+) */ |
1859 | ||
7c9cf4e3 | 1860 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 1861 | { |
73dec95e | 1862 | u32 cmd, *cs; |
b72f3acb | 1863 | |
73dec95e TU |
1864 | cs = intel_ring_begin(req, 4); |
1865 | if (IS_ERR(cs)) | |
1866 | return PTR_ERR(cs); | |
b72f3acb | 1867 | |
71a77e07 | 1868 | cmd = MI_FLUSH_DW; |
c033666a | 1869 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 1870 | cmd += 1; |
f0a1fb10 CW |
1871 | |
1872 | /* We always require a command barrier so that subsequent | |
1873 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1874 | * wrt the contents of the write cache being flushed to memory | |
1875 | * (and thus being coherent from the CPU). | |
1876 | */ | |
1877 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1878 | ||
9a289771 JB |
1879 | /* |
1880 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1881 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1882 | * operation is complete. This bit is only valid when the | |
1883 | * Post-Sync Operation field is a value of 1h or 3h." | |
1884 | */ | |
7c9cf4e3 | 1885 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 1886 | cmd |= MI_INVALIDATE_TLB; |
73dec95e TU |
1887 | *cs++ = cmd; |
1888 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
c033666a | 1889 | if (INTEL_GEN(req->i915) >= 8) { |
73dec95e TU |
1890 | *cs++ = 0; /* upper addr */ |
1891 | *cs++ = 0; /* value */ | |
075b3bba | 1892 | } else { |
73dec95e TU |
1893 | *cs++ = 0; |
1894 | *cs++ = MI_NOOP; | |
075b3bba | 1895 | } |
73dec95e | 1896 | intel_ring_advance(req, cs); |
fd3da6c9 | 1897 | |
b72f3acb | 1898 | return 0; |
8d19215b ZN |
1899 | } |
1900 | ||
d9a64610 TU |
1901 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
1902 | struct intel_engine_cs *engine) | |
1903 | { | |
db3d4019 | 1904 | struct drm_i915_gem_object *obj; |
1b9e6650 | 1905 | int ret, i; |
db3d4019 | 1906 | |
39df9190 | 1907 | if (!i915.semaphores) |
db3d4019 TU |
1908 | return; |
1909 | ||
51d545d0 CW |
1910 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
1911 | struct i915_vma *vma; | |
1912 | ||
f51455d4 | 1913 | obj = i915_gem_object_create(dev_priv, PAGE_SIZE); |
51d545d0 CW |
1914 | if (IS_ERR(obj)) |
1915 | goto err; | |
db3d4019 | 1916 | |
a01cb37a | 1917 | vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL); |
51d545d0 CW |
1918 | if (IS_ERR(vma)) |
1919 | goto err_obj; | |
1920 | ||
1921 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1922 | if (ret) | |
1923 | goto err_obj; | |
1924 | ||
1925 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
1926 | if (ret) | |
1927 | goto err_obj; | |
1928 | ||
1929 | dev_priv->semaphore = vma; | |
1930 | } | |
d9a64610 TU |
1931 | |
1932 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 1933 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 1934 | |
ad7bdb2b | 1935 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 1936 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
1937 | |
1938 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 1939 | u32 ring_offset; |
1b9e6650 TU |
1940 | |
1941 | if (i != engine->id) | |
1942 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
1943 | else | |
1944 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
1945 | ||
1946 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
1947 | } | |
d9a64610 | 1948 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 1949 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 1950 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
1951 | |
1952 | /* | |
1953 | * The current semaphore is only applied on pre-gen8 | |
1954 | * platform. And there is no VCS2 ring on the pre-gen8 | |
1955 | * platform. So the semaphore between RCS and VCS2 is | |
1956 | * initialized as INVALID. Gen8 will initialize the | |
1957 | * sema between VCS2 and RCS later. | |
1958 | */ | |
318f89ca | 1959 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
1960 | static const struct { |
1961 | u32 wait_mbox; | |
1962 | i915_reg_t mbox_reg; | |
318f89ca TU |
1963 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
1964 | [RCS_HW] = { | |
1965 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
1966 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
1967 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 1968 | }, |
318f89ca TU |
1969 | [VCS_HW] = { |
1970 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
1971 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
1972 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 1973 | }, |
318f89ca TU |
1974 | [BCS_HW] = { |
1975 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
1976 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
1977 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 1978 | }, |
318f89ca TU |
1979 | [VECS_HW] = { |
1980 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
1981 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
1982 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
1983 | }, |
1984 | }; | |
1985 | u32 wait_mbox; | |
1986 | i915_reg_t mbox_reg; | |
1987 | ||
318f89ca | 1988 | if (i == engine->hw_id) { |
4b8e38a9 TU |
1989 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
1990 | mbox_reg = GEN6_NOSYNC; | |
1991 | } else { | |
318f89ca TU |
1992 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
1993 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
1994 | } |
1995 | ||
1996 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
1997 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
1998 | } | |
d9a64610 | 1999 | } |
51d545d0 CW |
2000 | |
2001 | return; | |
2002 | ||
2003 | err_obj: | |
2004 | i915_gem_object_put(obj); | |
2005 | err: | |
2006 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2007 | i915.semaphores = 0; | |
d9a64610 TU |
2008 | } |
2009 | ||
ed003078 CW |
2010 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2011 | struct intel_engine_cs *engine) | |
2012 | { | |
c78d6061 TU |
2013 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2014 | ||
ed003078 | 2015 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2016 | engine->irq_enable = gen8_irq_enable; |
2017 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2018 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2019 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2020 | engine->irq_enable = gen6_irq_enable; |
2021 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2022 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2023 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2024 | engine->irq_enable = gen5_irq_enable; |
2025 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2026 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2027 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2028 | engine->irq_enable = i9xx_irq_enable; |
2029 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2030 | } else { |
31bb59cc CW |
2031 | engine->irq_enable = i8xx_irq_enable; |
2032 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2033 | } |
2034 | } | |
2035 | ||
ff44ad51 CW |
2036 | static void i9xx_set_default_submission(struct intel_engine_cs *engine) |
2037 | { | |
2038 | engine->submit_request = i9xx_submit_request; | |
2039 | } | |
2040 | ||
2041 | static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) | |
2042 | { | |
2043 | engine->submit_request = gen6_bsd_submit_request; | |
2044 | } | |
2045 | ||
06a2fe22 TU |
2046 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2047 | struct intel_engine_cs *engine) | |
2048 | { | |
618e4ca7 CW |
2049 | intel_ring_init_irq(dev_priv, engine); |
2050 | intel_ring_init_semaphores(dev_priv, engine); | |
2051 | ||
1d8a1337 | 2052 | engine->init_hw = init_ring_common; |
821ed7df | 2053 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2054 | |
e8a9c58f CW |
2055 | engine->context_pin = intel_ring_context_pin; |
2056 | engine->context_unpin = intel_ring_context_unpin; | |
2057 | ||
f73e7399 CW |
2058 | engine->request_alloc = ring_request_alloc; |
2059 | ||
9b81d556 | 2060 | engine->emit_breadcrumb = i9xx_emit_breadcrumb; |
98f29e8d CW |
2061 | engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; |
2062 | if (i915.semaphores) { | |
2063 | int num_rings; | |
2064 | ||
9b81d556 | 2065 | engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; |
98f29e8d CW |
2066 | |
2067 | num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
2068 | if (INTEL_GEN(dev_priv) >= 8) { | |
2069 | engine->emit_breadcrumb_sz += num_rings * 6; | |
2070 | } else { | |
2071 | engine->emit_breadcrumb_sz += num_rings * 3; | |
2072 | if (num_rings & 1) | |
2073 | engine->emit_breadcrumb_sz++; | |
2074 | } | |
2075 | } | |
ff44ad51 CW |
2076 | |
2077 | engine->set_default_submission = i9xx_set_default_submission; | |
6f7bef75 CW |
2078 | |
2079 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2080 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2081 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2082 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2083 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2084 | engine->emit_bb_start = i965_emit_bb_start; |
2a307c2e | 2085 | else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
803688ba | 2086 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2087 | else |
803688ba | 2088 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2089 | } |
2090 | ||
8b3e2d36 | 2091 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2092 | { |
8b3e2d36 | 2093 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2094 | int ret; |
5c1143bb | 2095 | |
06a2fe22 TU |
2096 | intel_ring_default_vfuncs(dev_priv, engine); |
2097 | ||
61ff75ac CW |
2098 | if (HAS_L3_DPF(dev_priv)) |
2099 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2100 | |
c033666a | 2101 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2102 | engine->init_context = intel_rcs_ctx_init; |
9b81d556 | 2103 | engine->emit_breadcrumb = gen8_render_emit_breadcrumb; |
98f29e8d | 2104 | engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz; |
c7fe7d25 | 2105 | engine->emit_flush = gen8_render_ring_flush; |
98f29e8d CW |
2106 | if (i915.semaphores) { |
2107 | int num_rings; | |
2108 | ||
e2f80391 | 2109 | engine->semaphore.signal = gen8_rcs_signal; |
98f29e8d CW |
2110 | |
2111 | num_rings = | |
2112 | hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1; | |
6f9b850b | 2113 | engine->emit_breadcrumb_sz += num_rings * 8; |
98f29e8d | 2114 | } |
c033666a | 2115 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2116 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2117 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2118 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2119 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2120 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2121 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2122 | } else { |
c033666a | 2123 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2124 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2125 | else |
c7fe7d25 | 2126 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2127 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2128 | } |
707d9cf9 | 2129 | |
c033666a | 2130 | if (IS_HASWELL(dev_priv)) |
803688ba | 2131 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2132 | |
e2f80391 TU |
2133 | engine->init_hw = init_render_ring; |
2134 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2135 | |
acd27845 | 2136 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2137 | if (ret) |
2138 | return ret; | |
2139 | ||
f8973c21 | 2140 | if (INTEL_GEN(dev_priv) >= 6) { |
f51455d4 | 2141 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
7d5ea807 CW |
2142 | if (ret) |
2143 | return ret; | |
2144 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2145 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2146 | if (ret) |
2147 | return ret; | |
2148 | } | |
2149 | ||
2150 | return 0; | |
5c1143bb XH |
2151 | } |
2152 | ||
8b3e2d36 | 2153 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2154 | { |
8b3e2d36 | 2155 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2156 | |
06a2fe22 TU |
2157 | intel_ring_default_vfuncs(dev_priv, engine); |
2158 | ||
c033666a | 2159 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2160 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2161 | if (IS_GEN6(dev_priv)) |
ff44ad51 | 2162 | engine->set_default_submission = gen6_bsd_set_default_submission; |
c7fe7d25 | 2163 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2164 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2165 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2166 | } else { |
e2f80391 | 2167 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2168 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2169 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2170 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2171 | else |
e2f80391 | 2172 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2173 | } |
58fa3835 | 2174 | |
acd27845 | 2175 | return intel_init_ring_buffer(engine); |
5c1143bb | 2176 | } |
549f7365 | 2177 | |
8b3e2d36 | 2178 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2179 | { |
8b3e2d36 | 2180 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2181 | |
2182 | intel_ring_default_vfuncs(dev_priv, engine); | |
2183 | ||
c7fe7d25 | 2184 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2185 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2186 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2187 | |
acd27845 | 2188 | return intel_init_ring_buffer(engine); |
549f7365 | 2189 | } |
a7b9761d | 2190 | |
8b3e2d36 | 2191 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2192 | { |
8b3e2d36 | 2193 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2194 | |
2195 | intel_ring_default_vfuncs(dev_priv, engine); | |
2196 | ||
c7fe7d25 | 2197 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2198 | |
c78d6061 | 2199 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2200 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2201 | engine->irq_enable = hsw_vebox_irq_enable; |
2202 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2203 | } |
9a8a2213 | 2204 | |
acd27845 | 2205 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2206 | } |