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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
8d315287 JB |
37 | /* |
38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
39 | * over cache flushing. | |
40 | */ | |
41 | struct pipe_control { | |
42 | struct drm_i915_gem_object *obj; | |
43 | volatile u32 *cpu_page; | |
44 | u32 gtt_offset; | |
45 | }; | |
46 | ||
c7dca47b CW |
47 | static inline int ring_space(struct intel_ring_buffer *ring) |
48 | { | |
49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
50 | if (space < 0) | |
51 | space += ring->size; | |
52 | return space; | |
53 | } | |
54 | ||
b72f3acb | 55 | static int |
78501eac | 56 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
57 | u32 invalidate_domains, |
58 | u32 flush_domains) | |
62fdfeaf | 59 | { |
78501eac | 60 | struct drm_device *dev = ring->dev; |
6f392d54 | 61 | u32 cmd; |
b72f3acb | 62 | int ret; |
6f392d54 | 63 | |
36d527de CW |
64 | /* |
65 | * read/write caches: | |
66 | * | |
67 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
68 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
69 | * also flushed at 2d versus 3d pipeline switches. | |
70 | * | |
71 | * read-only caches: | |
72 | * | |
73 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
74 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
75 | * | |
76 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
77 | * | |
78 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
79 | * invalidated when MI_EXE_FLUSH is set. | |
80 | * | |
81 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
82 | * invalidated with every MI_FLUSH. | |
83 | * | |
84 | * TLBs: | |
85 | * | |
86 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
87 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
88 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
89 | * are flushed at any MI_FLUSH. | |
90 | */ | |
91 | ||
92 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
93 | if ((invalidate_domains|flush_domains) & | |
94 | I915_GEM_DOMAIN_RENDER) | |
95 | cmd &= ~MI_NO_WRITE_FLUSH; | |
96 | if (INTEL_INFO(dev)->gen < 4) { | |
62fdfeaf | 97 | /* |
36d527de CW |
98 | * On the 965, the sampler cache always gets flushed |
99 | * and this bit is reserved. | |
62fdfeaf | 100 | */ |
36d527de CW |
101 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
102 | cmd |= MI_READ_FLUSH; | |
103 | } | |
104 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
105 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 106 | |
36d527de CW |
107 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
108 | (IS_G4X(dev) || IS_GEN5(dev))) | |
109 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 110 | |
36d527de CW |
111 | ret = intel_ring_begin(ring, 2); |
112 | if (ret) | |
113 | return ret; | |
b72f3acb | 114 | |
36d527de CW |
115 | intel_ring_emit(ring, cmd); |
116 | intel_ring_emit(ring, MI_NOOP); | |
117 | intel_ring_advance(ring); | |
b72f3acb CW |
118 | |
119 | return 0; | |
8187a2b7 ZN |
120 | } |
121 | ||
8d315287 JB |
122 | /** |
123 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
124 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
125 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
126 | * | |
127 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
128 | * produced by non-pipelined state commands), software needs to first | |
129 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
130 | * 0. | |
131 | * | |
132 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
133 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
134 | * | |
135 | * And the workaround for these two requires this workaround first: | |
136 | * | |
137 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
138 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
139 | * flushes. | |
140 | * | |
141 | * And this last workaround is tricky because of the requirements on | |
142 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
143 | * volume 2 part 1: | |
144 | * | |
145 | * "1 of the following must also be set: | |
146 | * - Render Target Cache Flush Enable ([12] of DW1) | |
147 | * - Depth Cache Flush Enable ([0] of DW1) | |
148 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
149 | * - Depth Stall ([13] of DW1) | |
150 | * - Post-Sync Operation ([13] of DW1) | |
151 | * - Notify Enable ([8] of DW1)" | |
152 | * | |
153 | * The cache flushes require the workaround flush that triggered this | |
154 | * one, so we can't use it. Depth stall would trigger the same. | |
155 | * Post-sync nonzero is what triggered this second workaround, so we | |
156 | * can't use that one either. Notify enable is IRQs, which aren't | |
157 | * really our business. That leaves only stall at scoreboard. | |
158 | */ | |
159 | static int | |
160 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
161 | { | |
162 | struct pipe_control *pc = ring->private; | |
163 | u32 scratch_addr = pc->gtt_offset + 128; | |
164 | int ret; | |
165 | ||
166 | ||
167 | ret = intel_ring_begin(ring, 6); | |
168 | if (ret) | |
169 | return ret; | |
170 | ||
171 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
172 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
173 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
174 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
175 | intel_ring_emit(ring, 0); /* low dword */ | |
176 | intel_ring_emit(ring, 0); /* high dword */ | |
177 | intel_ring_emit(ring, MI_NOOP); | |
178 | intel_ring_advance(ring); | |
179 | ||
180 | ret = intel_ring_begin(ring, 6); | |
181 | if (ret) | |
182 | return ret; | |
183 | ||
184 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
185 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
186 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
187 | intel_ring_emit(ring, 0); | |
188 | intel_ring_emit(ring, 0); | |
189 | intel_ring_emit(ring, MI_NOOP); | |
190 | intel_ring_advance(ring); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static int | |
196 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
197 | u32 invalidate_domains, u32 flush_domains) | |
198 | { | |
199 | u32 flags = 0; | |
200 | struct pipe_control *pc = ring->private; | |
201 | u32 scratch_addr = pc->gtt_offset + 128; | |
202 | int ret; | |
203 | ||
204 | /* Force SNB workarounds for PIPE_CONTROL flushes */ | |
205 | intel_emit_post_sync_nonzero_flush(ring); | |
206 | ||
207 | /* Just flush everything. Experiments have shown that reducing the | |
208 | * number of bits based on the write domains has little performance | |
209 | * impact. | |
210 | */ | |
211 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
212 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
213 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
214 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
215 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
216 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
217 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
218 | ||
219 | ret = intel_ring_begin(ring, 6); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
223 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
224 | intel_ring_emit(ring, flags); | |
225 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
226 | intel_ring_emit(ring, 0); /* lower dword */ | |
227 | intel_ring_emit(ring, 0); /* uppwer dword */ | |
228 | intel_ring_emit(ring, MI_NOOP); | |
229 | intel_ring_advance(ring); | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
78501eac | 234 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 235 | u32 value) |
d46eefa2 | 236 | { |
78501eac | 237 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 238 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
239 | } |
240 | ||
78501eac | 241 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 242 | { |
78501eac CW |
243 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
244 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 245 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
246 | |
247 | return I915_READ(acthd_reg); | |
248 | } | |
249 | ||
78501eac | 250 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 251 | { |
78501eac | 252 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 253 | struct drm_i915_gem_object *obj = ring->obj; |
8187a2b7 | 254 | u32 head; |
8187a2b7 ZN |
255 | |
256 | /* Stop the ring if it's running. */ | |
7f2ab699 | 257 | I915_WRITE_CTL(ring, 0); |
570ef608 | 258 | I915_WRITE_HEAD(ring, 0); |
78501eac | 259 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
260 | |
261 | /* Initialize the ring. */ | |
05394f39 | 262 | I915_WRITE_START(ring, obj->gtt_offset); |
570ef608 | 263 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
264 | |
265 | /* G45 ring initialization fails to reset head to zero */ | |
266 | if (head != 0) { | |
6fd0d56e CW |
267 | DRM_DEBUG_KMS("%s head not reset to zero " |
268 | "ctl %08x head %08x tail %08x start %08x\n", | |
269 | ring->name, | |
270 | I915_READ_CTL(ring), | |
271 | I915_READ_HEAD(ring), | |
272 | I915_READ_TAIL(ring), | |
273 | I915_READ_START(ring)); | |
8187a2b7 | 274 | |
570ef608 | 275 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 276 | |
6fd0d56e CW |
277 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
278 | DRM_ERROR("failed to set %s head to zero " | |
279 | "ctl %08x head %08x tail %08x start %08x\n", | |
280 | ring->name, | |
281 | I915_READ_CTL(ring), | |
282 | I915_READ_HEAD(ring), | |
283 | I915_READ_TAIL(ring), | |
284 | I915_READ_START(ring)); | |
285 | } | |
8187a2b7 ZN |
286 | } |
287 | ||
7f2ab699 | 288 | I915_WRITE_CTL(ring, |
ae69b42a | 289 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 290 | | RING_VALID); |
8187a2b7 | 291 | |
8187a2b7 | 292 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
293 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
294 | I915_READ_START(ring) == obj->gtt_offset && | |
295 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
296 | DRM_ERROR("%s initialization failed " |
297 | "ctl %08x head %08x tail %08x start %08x\n", | |
298 | ring->name, | |
299 | I915_READ_CTL(ring), | |
300 | I915_READ_HEAD(ring), | |
301 | I915_READ_TAIL(ring), | |
302 | I915_READ_START(ring)); | |
303 | return -EIO; | |
8187a2b7 ZN |
304 | } |
305 | ||
78501eac CW |
306 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
307 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 308 | else { |
c7dca47b | 309 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 310 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 311 | ring->space = ring_space(ring); |
8187a2b7 | 312 | } |
1ec14ad3 | 313 | |
8187a2b7 ZN |
314 | return 0; |
315 | } | |
316 | ||
c6df541c CW |
317 | static int |
318 | init_pipe_control(struct intel_ring_buffer *ring) | |
319 | { | |
320 | struct pipe_control *pc; | |
321 | struct drm_i915_gem_object *obj; | |
322 | int ret; | |
323 | ||
324 | if (ring->private) | |
325 | return 0; | |
326 | ||
327 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
328 | if (!pc) | |
329 | return -ENOMEM; | |
330 | ||
331 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
332 | if (obj == NULL) { | |
333 | DRM_ERROR("Failed to allocate seqno page\n"); | |
334 | ret = -ENOMEM; | |
335 | goto err; | |
336 | } | |
e4ffd173 CW |
337 | |
338 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c CW |
339 | |
340 | ret = i915_gem_object_pin(obj, 4096, true); | |
341 | if (ret) | |
342 | goto err_unref; | |
343 | ||
344 | pc->gtt_offset = obj->gtt_offset; | |
345 | pc->cpu_page = kmap(obj->pages[0]); | |
346 | if (pc->cpu_page == NULL) | |
347 | goto err_unpin; | |
348 | ||
349 | pc->obj = obj; | |
350 | ring->private = pc; | |
351 | return 0; | |
352 | ||
353 | err_unpin: | |
354 | i915_gem_object_unpin(obj); | |
355 | err_unref: | |
356 | drm_gem_object_unreference(&obj->base); | |
357 | err: | |
358 | kfree(pc); | |
359 | return ret; | |
360 | } | |
361 | ||
362 | static void | |
363 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
364 | { | |
365 | struct pipe_control *pc = ring->private; | |
366 | struct drm_i915_gem_object *obj; | |
367 | ||
368 | if (!ring->private) | |
369 | return; | |
370 | ||
371 | obj = pc->obj; | |
372 | kunmap(obj->pages[0]); | |
373 | i915_gem_object_unpin(obj); | |
374 | drm_gem_object_unreference(&obj->base); | |
375 | ||
376 | kfree(pc); | |
377 | ring->private = NULL; | |
378 | } | |
379 | ||
78501eac | 380 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 381 | { |
78501eac | 382 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 384 | int ret = init_ring_common(ring); |
a69ffdbf | 385 | |
a6c45cf0 | 386 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac | 387 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
a69ffdbf | 388 | I915_WRITE(MI_MODE, mode); |
b095cd0a JB |
389 | if (IS_GEN7(dev)) |
390 | I915_WRITE(GFX_MODE_GEN7, | |
391 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
392 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 393 | } |
78501eac | 394 | |
8d315287 | 395 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
396 | ret = init_pipe_control(ring); |
397 | if (ret) | |
398 | return ret; | |
399 | } | |
400 | ||
84f9f938 BW |
401 | if (INTEL_INFO(dev)->gen >= 6) { |
402 | I915_WRITE(INSTPM, | |
403 | INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); | |
404 | } | |
405 | ||
8187a2b7 ZN |
406 | return ret; |
407 | } | |
408 | ||
c6df541c CW |
409 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
410 | { | |
411 | if (!ring->private) | |
412 | return; | |
413 | ||
414 | cleanup_pipe_control(ring); | |
415 | } | |
416 | ||
1ec14ad3 | 417 | static void |
c8c99b0f BW |
418 | update_mboxes(struct intel_ring_buffer *ring, |
419 | u32 seqno, | |
420 | u32 mmio_offset) | |
1ec14ad3 | 421 | { |
c8c99b0f BW |
422 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
423 | MI_SEMAPHORE_GLOBAL_GTT | | |
424 | MI_SEMAPHORE_REGISTER | | |
425 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 426 | intel_ring_emit(ring, seqno); |
c8c99b0f | 427 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
428 | } |
429 | ||
c8c99b0f BW |
430 | /** |
431 | * gen6_add_request - Update the semaphore mailbox registers | |
432 | * | |
433 | * @ring - ring that is adding a request | |
434 | * @seqno - return seqno stuck into the ring | |
435 | * | |
436 | * Update the mailbox registers in the *other* rings with the current seqno. | |
437 | * This acts like a signal in the canonical semaphore. | |
438 | */ | |
1ec14ad3 CW |
439 | static int |
440 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 441 | u32 *seqno) |
1ec14ad3 | 442 | { |
c8c99b0f BW |
443 | u32 mbox1_reg; |
444 | u32 mbox2_reg; | |
1ec14ad3 CW |
445 | int ret; |
446 | ||
447 | ret = intel_ring_begin(ring, 10); | |
448 | if (ret) | |
449 | return ret; | |
450 | ||
c8c99b0f BW |
451 | mbox1_reg = ring->signal_mbox[0]; |
452 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 453 | |
53d227f2 | 454 | *seqno = i915_gem_next_request_seqno(ring); |
c8c99b0f BW |
455 | |
456 | update_mboxes(ring, *seqno, mbox1_reg); | |
457 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
458 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
459 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 460 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
461 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
462 | intel_ring_advance(ring); | |
463 | ||
1ec14ad3 CW |
464 | return 0; |
465 | } | |
466 | ||
c8c99b0f BW |
467 | /** |
468 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
469 | * | |
470 | * @waiter - ring that is waiting | |
471 | * @signaller - ring which has, or will signal | |
472 | * @seqno - seqno which the waiter will block on | |
473 | */ | |
474 | static int | |
686cb5f9 DV |
475 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
476 | struct intel_ring_buffer *signaller, | |
477 | u32 seqno) | |
1ec14ad3 CW |
478 | { |
479 | int ret; | |
c8c99b0f BW |
480 | u32 dw1 = MI_SEMAPHORE_MBOX | |
481 | MI_SEMAPHORE_COMPARE | | |
482 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 483 | |
1500f7ea BW |
484 | /* Throughout all of the GEM code, seqno passed implies our current |
485 | * seqno is >= the last seqno executed. However for hardware the | |
486 | * comparison is strictly greater than. | |
487 | */ | |
488 | seqno -= 1; | |
489 | ||
686cb5f9 DV |
490 | WARN_ON(signaller->semaphore_register[waiter->id] == |
491 | MI_SEMAPHORE_SYNC_INVALID); | |
492 | ||
c8c99b0f | 493 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
494 | if (ret) |
495 | return ret; | |
496 | ||
686cb5f9 DV |
497 | intel_ring_emit(waiter, |
498 | dw1 | signaller->semaphore_register[waiter->id]); | |
c8c99b0f BW |
499 | intel_ring_emit(waiter, seqno); |
500 | intel_ring_emit(waiter, 0); | |
501 | intel_ring_emit(waiter, MI_NOOP); | |
502 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
503 | |
504 | return 0; | |
505 | } | |
506 | ||
c6df541c CW |
507 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
508 | do { \ | |
fcbc34e4 KG |
509 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
510 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
511 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
512 | intel_ring_emit(ring__, 0); \ | |
513 | intel_ring_emit(ring__, 0); \ | |
514 | } while (0) | |
515 | ||
516 | static int | |
517 | pc_render_add_request(struct intel_ring_buffer *ring, | |
518 | u32 *result) | |
519 | { | |
53d227f2 | 520 | u32 seqno = i915_gem_next_request_seqno(ring); |
c6df541c CW |
521 | struct pipe_control *pc = ring->private; |
522 | u32 scratch_addr = pc->gtt_offset + 128; | |
523 | int ret; | |
524 | ||
525 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
526 | * incoherent with writes to memory, i.e. completely fubar, | |
527 | * so we need to use PIPE_NOTIFY instead. | |
528 | * | |
529 | * However, we also need to workaround the qword write | |
530 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
531 | * memory before requesting an interrupt. | |
532 | */ | |
533 | ret = intel_ring_begin(ring, 32); | |
534 | if (ret) | |
535 | return ret; | |
536 | ||
fcbc34e4 | 537 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
538 | PIPE_CONTROL_WRITE_FLUSH | |
539 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c CW |
540 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
541 | intel_ring_emit(ring, seqno); | |
542 | intel_ring_emit(ring, 0); | |
543 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
544 | scratch_addr += 128; /* write to separate cachelines */ | |
545 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
546 | scratch_addr += 128; | |
547 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
548 | scratch_addr += 128; | |
549 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
550 | scratch_addr += 128; | |
551 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
552 | scratch_addr += 128; | |
553 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 554 | |
fcbc34e4 | 555 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
556 | PIPE_CONTROL_WRITE_FLUSH | |
557 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
558 | PIPE_CONTROL_NOTIFY); |
559 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
560 | intel_ring_emit(ring, seqno); | |
561 | intel_ring_emit(ring, 0); | |
562 | intel_ring_advance(ring); | |
563 | ||
564 | *result = seqno; | |
565 | return 0; | |
566 | } | |
567 | ||
4cd53c0c DV |
568 | static u32 |
569 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) | |
570 | { | |
571 | struct drm_device *dev = ring->dev; | |
572 | ||
573 | /* Workaround to force correct ordering between irq and seqno writes on | |
574 | * ivb (and maybe also on snb) by reading from a CS register (like | |
575 | * ACTHD) before reading the status page. */ | |
1c7eaac7 | 576 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
4cd53c0c DV |
577 | intel_ring_get_active_head(ring); |
578 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
579 | } | |
580 | ||
8187a2b7 | 581 | static u32 |
1ec14ad3 | 582 | ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 583 | { |
1ec14ad3 CW |
584 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
585 | } | |
586 | ||
c6df541c CW |
587 | static u32 |
588 | pc_render_get_seqno(struct intel_ring_buffer *ring) | |
589 | { | |
590 | struct pipe_control *pc = ring->private; | |
591 | return pc->cpu_page[0]; | |
592 | } | |
593 | ||
e48d8634 DV |
594 | static bool |
595 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
596 | { | |
597 | struct drm_device *dev = ring->dev; | |
598 | drm_i915_private_t *dev_priv = dev->dev_private; | |
599 | ||
600 | if (!dev->irq_enabled) | |
601 | return false; | |
602 | ||
603 | spin_lock(&ring->irq_lock); | |
f637fde4 DV |
604 | if (ring->irq_refcount++ == 0) { |
605 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; | |
606 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
607 | POSTING_READ(GTIMR); | |
608 | } | |
e48d8634 DV |
609 | spin_unlock(&ring->irq_lock); |
610 | ||
611 | return true; | |
612 | } | |
613 | ||
614 | static void | |
615 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
616 | { | |
617 | struct drm_device *dev = ring->dev; | |
618 | drm_i915_private_t *dev_priv = dev->dev_private; | |
619 | ||
620 | spin_lock(&ring->irq_lock); | |
f637fde4 DV |
621 | if (--ring->irq_refcount == 0) { |
622 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; | |
623 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
624 | POSTING_READ(GTIMR); | |
625 | } | |
e48d8634 DV |
626 | spin_unlock(&ring->irq_lock); |
627 | } | |
628 | ||
b13c2b96 | 629 | static bool |
e3670319 | 630 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 631 | { |
78501eac | 632 | struct drm_device *dev = ring->dev; |
01a03331 | 633 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf | 634 | |
b13c2b96 CW |
635 | if (!dev->irq_enabled) |
636 | return false; | |
637 | ||
0dc79fb2 | 638 | spin_lock(&ring->irq_lock); |
f637fde4 DV |
639 | if (ring->irq_refcount++ == 0) { |
640 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
641 | I915_WRITE(IMR, dev_priv->irq_mask); | |
642 | POSTING_READ(IMR); | |
643 | } | |
0dc79fb2 | 644 | spin_unlock(&ring->irq_lock); |
b13c2b96 CW |
645 | |
646 | return true; | |
62fdfeaf EA |
647 | } |
648 | ||
8187a2b7 | 649 | static void |
e3670319 | 650 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 651 | { |
78501eac | 652 | struct drm_device *dev = ring->dev; |
01a03331 | 653 | drm_i915_private_t *dev_priv = dev->dev_private; |
62fdfeaf | 654 | |
0dc79fb2 | 655 | spin_lock(&ring->irq_lock); |
f637fde4 DV |
656 | if (--ring->irq_refcount == 0) { |
657 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
658 | I915_WRITE(IMR, dev_priv->irq_mask); | |
659 | POSTING_READ(IMR); | |
660 | } | |
0dc79fb2 | 661 | spin_unlock(&ring->irq_lock); |
62fdfeaf EA |
662 | } |
663 | ||
78501eac | 664 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 665 | { |
4593010b | 666 | struct drm_device *dev = ring->dev; |
78501eac | 667 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
668 | u32 mmio = 0; |
669 | ||
670 | /* The ring status page addresses are no longer next to the rest of | |
671 | * the ring registers as of gen7. | |
672 | */ | |
673 | if (IS_GEN7(dev)) { | |
674 | switch (ring->id) { | |
96154f2f | 675 | case RCS: |
4593010b EA |
676 | mmio = RENDER_HWS_PGA_GEN7; |
677 | break; | |
96154f2f | 678 | case BCS: |
4593010b EA |
679 | mmio = BLT_HWS_PGA_GEN7; |
680 | break; | |
96154f2f | 681 | case VCS: |
4593010b EA |
682 | mmio = BSD_HWS_PGA_GEN7; |
683 | break; | |
684 | } | |
685 | } else if (IS_GEN6(ring->dev)) { | |
686 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
687 | } else { | |
688 | mmio = RING_HWS_PGA(ring->mmio_base); | |
689 | } | |
690 | ||
78501eac CW |
691 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
692 | POSTING_READ(mmio); | |
8187a2b7 ZN |
693 | } |
694 | ||
b72f3acb | 695 | static int |
78501eac CW |
696 | bsd_ring_flush(struct intel_ring_buffer *ring, |
697 | u32 invalidate_domains, | |
698 | u32 flush_domains) | |
d1b851fc | 699 | { |
b72f3acb CW |
700 | int ret; |
701 | ||
b72f3acb CW |
702 | ret = intel_ring_begin(ring, 2); |
703 | if (ret) | |
704 | return ret; | |
705 | ||
706 | intel_ring_emit(ring, MI_FLUSH); | |
707 | intel_ring_emit(ring, MI_NOOP); | |
708 | intel_ring_advance(ring); | |
709 | return 0; | |
d1b851fc ZN |
710 | } |
711 | ||
3cce469c | 712 | static int |
8620a3a9 | 713 | i9xx_add_request(struct intel_ring_buffer *ring, |
3cce469c | 714 | u32 *result) |
d1b851fc ZN |
715 | { |
716 | u32 seqno; | |
3cce469c CW |
717 | int ret; |
718 | ||
719 | ret = intel_ring_begin(ring, 4); | |
720 | if (ret) | |
721 | return ret; | |
6f392d54 | 722 | |
53d227f2 | 723 | seqno = i915_gem_next_request_seqno(ring); |
6f392d54 | 724 | |
3cce469c CW |
725 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
726 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
727 | intel_ring_emit(ring, seqno); | |
728 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
729 | intel_ring_advance(ring); | |
d1b851fc | 730 | |
3cce469c CW |
731 | *result = seqno; |
732 | return 0; | |
d1b851fc ZN |
733 | } |
734 | ||
0f46832f | 735 | static bool |
25c06300 | 736 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
737 | { |
738 | struct drm_device *dev = ring->dev; | |
01a03331 | 739 | drm_i915_private_t *dev_priv = dev->dev_private; |
0f46832f CW |
740 | |
741 | if (!dev->irq_enabled) | |
742 | return false; | |
743 | ||
4cd53c0c DV |
744 | /* It looks like we need to prevent the gt from suspending while waiting |
745 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
746 | * blt/bsd rings on ivb. */ | |
99ffa162 | 747 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 748 | |
0dc79fb2 | 749 | spin_lock(&ring->irq_lock); |
01a03331 | 750 | if (ring->irq_refcount++ == 0) { |
6a848ccb | 751 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
f637fde4 DV |
752 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
753 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
754 | POSTING_READ(GTIMR); | |
0f46832f | 755 | } |
0dc79fb2 | 756 | spin_unlock(&ring->irq_lock); |
0f46832f CW |
757 | |
758 | return true; | |
759 | } | |
760 | ||
761 | static void | |
25c06300 | 762 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
763 | { |
764 | struct drm_device *dev = ring->dev; | |
01a03331 | 765 | drm_i915_private_t *dev_priv = dev->dev_private; |
0f46832f | 766 | |
0dc79fb2 | 767 | spin_lock(&ring->irq_lock); |
01a03331 | 768 | if (--ring->irq_refcount == 0) { |
6a848ccb | 769 | I915_WRITE_IMR(ring, ~0); |
f637fde4 DV |
770 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
771 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
772 | POSTING_READ(GTIMR); | |
1ec14ad3 | 773 | } |
0dc79fb2 | 774 | spin_unlock(&ring->irq_lock); |
4cd53c0c | 775 | |
99ffa162 | 776 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
777 | } |
778 | ||
d1b851fc | 779 | static int |
fb3256da | 780 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 781 | { |
e1f99ce6 | 782 | int ret; |
78501eac | 783 | |
e1f99ce6 CW |
784 | ret = intel_ring_begin(ring, 2); |
785 | if (ret) | |
786 | return ret; | |
787 | ||
78501eac | 788 | intel_ring_emit(ring, |
65f56876 CW |
789 | MI_BATCH_BUFFER_START | |
790 | MI_BATCH_GTT | | |
78501eac | 791 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 792 | intel_ring_emit(ring, offset); |
78501eac CW |
793 | intel_ring_advance(ring); |
794 | ||
d1b851fc ZN |
795 | return 0; |
796 | } | |
797 | ||
8187a2b7 | 798 | static int |
fb3256da | 799 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 800 | u32 offset, u32 len) |
62fdfeaf | 801 | { |
c4e7a414 | 802 | int ret; |
62fdfeaf | 803 | |
fb3256da DV |
804 | ret = intel_ring_begin(ring, 4); |
805 | if (ret) | |
806 | return ret; | |
62fdfeaf | 807 | |
fb3256da DV |
808 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
809 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
810 | intel_ring_emit(ring, offset + len - 8); | |
811 | intel_ring_emit(ring, 0); | |
812 | intel_ring_advance(ring); | |
e1f99ce6 | 813 | |
fb3256da DV |
814 | return 0; |
815 | } | |
816 | ||
817 | static int | |
818 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
819 | u32 offset, u32 len) | |
820 | { | |
821 | int ret; | |
822 | ||
823 | ret = intel_ring_begin(ring, 2); | |
824 | if (ret) | |
825 | return ret; | |
826 | ||
65f56876 | 827 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
fb3256da | 828 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
c4e7a414 | 829 | intel_ring_advance(ring); |
62fdfeaf | 830 | |
62fdfeaf EA |
831 | return 0; |
832 | } | |
833 | ||
78501eac | 834 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 835 | { |
78501eac | 836 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
05394f39 | 837 | struct drm_i915_gem_object *obj; |
62fdfeaf | 838 | |
8187a2b7 ZN |
839 | obj = ring->status_page.obj; |
840 | if (obj == NULL) | |
62fdfeaf | 841 | return; |
62fdfeaf | 842 | |
05394f39 | 843 | kunmap(obj->pages[0]); |
62fdfeaf | 844 | i915_gem_object_unpin(obj); |
05394f39 | 845 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 846 | ring->status_page.obj = NULL; |
62fdfeaf EA |
847 | |
848 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
849 | } |
850 | ||
78501eac | 851 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 852 | { |
78501eac | 853 | struct drm_device *dev = ring->dev; |
62fdfeaf | 854 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 855 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
856 | int ret; |
857 | ||
62fdfeaf EA |
858 | obj = i915_gem_alloc_object(dev, 4096); |
859 | if (obj == NULL) { | |
860 | DRM_ERROR("Failed to allocate status page\n"); | |
861 | ret = -ENOMEM; | |
862 | goto err; | |
863 | } | |
e4ffd173 CW |
864 | |
865 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 866 | |
75e9e915 | 867 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 868 | if (ret != 0) { |
62fdfeaf EA |
869 | goto err_unref; |
870 | } | |
871 | ||
05394f39 CW |
872 | ring->status_page.gfx_addr = obj->gtt_offset; |
873 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 874 | if (ring->status_page.page_addr == NULL) { |
62fdfeaf | 875 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
876 | goto err_unpin; |
877 | } | |
8187a2b7 ZN |
878 | ring->status_page.obj = obj; |
879 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 880 | |
78501eac | 881 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
882 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
883 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
884 | |
885 | return 0; | |
886 | ||
887 | err_unpin: | |
888 | i915_gem_object_unpin(obj); | |
889 | err_unref: | |
05394f39 | 890 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 891 | err: |
8187a2b7 | 892 | return ret; |
62fdfeaf EA |
893 | } |
894 | ||
c43b5634 BW |
895 | static int intel_init_ring_buffer(struct drm_device *dev, |
896 | struct intel_ring_buffer *ring) | |
62fdfeaf | 897 | { |
05394f39 | 898 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
899 | int ret; |
900 | ||
8187a2b7 | 901 | ring->dev = dev; |
23bc5982 CW |
902 | INIT_LIST_HEAD(&ring->active_list); |
903 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 904 | INIT_LIST_HEAD(&ring->gpu_write_list); |
dfc9ef2f | 905 | ring->size = 32 * PAGE_SIZE; |
0dc79fb2 | 906 | |
b259f673 | 907 | init_waitqueue_head(&ring->irq_queue); |
0dc79fb2 | 908 | spin_lock_init(&ring->irq_lock); |
62fdfeaf | 909 | |
8187a2b7 | 910 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 911 | ret = init_status_page(ring); |
8187a2b7 ZN |
912 | if (ret) |
913 | return ret; | |
914 | } | |
62fdfeaf | 915 | |
8187a2b7 | 916 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
917 | if (obj == NULL) { |
918 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 919 | ret = -ENOMEM; |
dd785e35 | 920 | goto err_hws; |
62fdfeaf | 921 | } |
62fdfeaf | 922 | |
05394f39 | 923 | ring->obj = obj; |
8187a2b7 | 924 | |
75e9e915 | 925 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
926 | if (ret) |
927 | goto err_unref; | |
62fdfeaf | 928 | |
8187a2b7 | 929 | ring->map.size = ring->size; |
05394f39 | 930 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
62fdfeaf EA |
931 | ring->map.type = 0; |
932 | ring->map.flags = 0; | |
933 | ring->map.mtrr = 0; | |
934 | ||
935 | drm_core_ioremap_wc(&ring->map, dev); | |
936 | if (ring->map.handle == NULL) { | |
937 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 938 | ret = -EINVAL; |
dd785e35 | 939 | goto err_unpin; |
62fdfeaf EA |
940 | } |
941 | ||
8187a2b7 | 942 | ring->virtual_start = ring->map.handle; |
78501eac | 943 | ret = ring->init(ring); |
dd785e35 CW |
944 | if (ret) |
945 | goto err_unmap; | |
62fdfeaf | 946 | |
55249baa CW |
947 | /* Workaround an erratum on the i830 which causes a hang if |
948 | * the TAIL pointer points to within the last 2 cachelines | |
949 | * of the buffer. | |
950 | */ | |
951 | ring->effective_size = ring->size; | |
27c1cbd0 | 952 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
953 | ring->effective_size -= 128; |
954 | ||
c584fe47 | 955 | return 0; |
dd785e35 CW |
956 | |
957 | err_unmap: | |
958 | drm_core_ioremapfree(&ring->map, dev); | |
959 | err_unpin: | |
960 | i915_gem_object_unpin(obj); | |
961 | err_unref: | |
05394f39 CW |
962 | drm_gem_object_unreference(&obj->base); |
963 | ring->obj = NULL; | |
dd785e35 | 964 | err_hws: |
78501eac | 965 | cleanup_status_page(ring); |
8187a2b7 | 966 | return ret; |
62fdfeaf EA |
967 | } |
968 | ||
78501eac | 969 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 970 | { |
33626e6a CW |
971 | struct drm_i915_private *dev_priv; |
972 | int ret; | |
973 | ||
05394f39 | 974 | if (ring->obj == NULL) |
62fdfeaf EA |
975 | return; |
976 | ||
33626e6a CW |
977 | /* Disable the ring buffer. The ring must be idle at this point */ |
978 | dev_priv = ring->dev->dev_private; | |
96f298aa | 979 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
980 | if (ret) |
981 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
982 | ring->name, ret); | |
983 | ||
33626e6a CW |
984 | I915_WRITE_CTL(ring, 0); |
985 | ||
78501eac | 986 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 987 | |
05394f39 CW |
988 | i915_gem_object_unpin(ring->obj); |
989 | drm_gem_object_unreference(&ring->obj->base); | |
990 | ring->obj = NULL; | |
78501eac | 991 | |
8d19215b ZN |
992 | if (ring->cleanup) |
993 | ring->cleanup(ring); | |
994 | ||
78501eac | 995 | cleanup_status_page(ring); |
62fdfeaf EA |
996 | } |
997 | ||
78501eac | 998 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 999 | { |
8187a2b7 | 1000 | unsigned int *virt; |
55249baa | 1001 | int rem = ring->size - ring->tail; |
62fdfeaf | 1002 | |
8187a2b7 | 1003 | if (ring->space < rem) { |
78501eac | 1004 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
1005 | if (ret) |
1006 | return ret; | |
1007 | } | |
62fdfeaf | 1008 | |
8187a2b7 | 1009 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
1010 | rem /= 8; |
1011 | while (rem--) { | |
62fdfeaf | 1012 | *virt++ = MI_NOOP; |
1741dd4a CW |
1013 | *virt++ = MI_NOOP; |
1014 | } | |
62fdfeaf | 1015 | |
8187a2b7 | 1016 | ring->tail = 0; |
c7dca47b | 1017 | ring->space = ring_space(ring); |
62fdfeaf EA |
1018 | |
1019 | return 0; | |
1020 | } | |
1021 | ||
a71d8d94 CW |
1022 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1023 | { | |
1024 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1025 | bool was_interruptible; | |
1026 | int ret; | |
1027 | ||
1028 | /* XXX As we have not yet audited all the paths to check that | |
1029 | * they are ready for ERESTARTSYS from intel_ring_begin, do not | |
1030 | * allow us to be interruptible by a signal. | |
1031 | */ | |
1032 | was_interruptible = dev_priv->mm.interruptible; | |
1033 | dev_priv->mm.interruptible = false; | |
1034 | ||
1035 | ret = i915_wait_request(ring, seqno, true); | |
1036 | ||
1037 | dev_priv->mm.interruptible = was_interruptible; | |
1038 | ||
1039 | return ret; | |
1040 | } | |
1041 | ||
1042 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1043 | { | |
1044 | struct drm_i915_gem_request *request; | |
1045 | u32 seqno = 0; | |
1046 | int ret; | |
1047 | ||
1048 | i915_gem_retire_requests_ring(ring); | |
1049 | ||
1050 | if (ring->last_retired_head != -1) { | |
1051 | ring->head = ring->last_retired_head; | |
1052 | ring->last_retired_head = -1; | |
1053 | ring->space = ring_space(ring); | |
1054 | if (ring->space >= n) | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | list_for_each_entry(request, &ring->request_list, list) { | |
1059 | int space; | |
1060 | ||
1061 | if (request->tail == -1) | |
1062 | continue; | |
1063 | ||
1064 | space = request->tail - (ring->tail + 8); | |
1065 | if (space < 0) | |
1066 | space += ring->size; | |
1067 | if (space >= n) { | |
1068 | seqno = request->seqno; | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | /* Consume this request in case we need more space than | |
1073 | * is available and so need to prevent a race between | |
1074 | * updating last_retired_head and direct reads of | |
1075 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1076 | */ | |
1077 | request->tail = -1; | |
1078 | } | |
1079 | ||
1080 | if (seqno == 0) | |
1081 | return -ENOSPC; | |
1082 | ||
1083 | ret = intel_ring_wait_seqno(ring, seqno); | |
1084 | if (ret) | |
1085 | return ret; | |
1086 | ||
1087 | if (WARN_ON(ring->last_retired_head == -1)) | |
1088 | return -ENOSPC; | |
1089 | ||
1090 | ring->head = ring->last_retired_head; | |
1091 | ring->last_retired_head = -1; | |
1092 | ring->space = ring_space(ring); | |
1093 | if (WARN_ON(ring->space < n)) | |
1094 | return -ENOSPC; | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
78501eac | 1099 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1100 | { |
78501eac | 1101 | struct drm_device *dev = ring->dev; |
cae5852d | 1102 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1103 | unsigned long end; |
a71d8d94 | 1104 | int ret; |
c7dca47b | 1105 | |
a71d8d94 CW |
1106 | ret = intel_ring_wait_request(ring, n); |
1107 | if (ret != -ENOSPC) | |
1108 | return ret; | |
1109 | ||
db53a302 | 1110 | trace_i915_ring_wait_begin(ring); |
e6bfaf85 DV |
1111 | if (drm_core_check_feature(dev, DRIVER_GEM)) |
1112 | /* With GEM the hangcheck timer should kick us out of the loop, | |
1113 | * leaving it early runs the risk of corrupting GEM state (due | |
1114 | * to running on almost untested codepaths). But on resume | |
1115 | * timers don't work yet, so prevent a complete hang in that | |
1116 | * case by choosing an insanely large timeout. */ | |
1117 | end = jiffies + 60 * HZ; | |
1118 | else | |
1119 | end = jiffies + 3 * HZ; | |
1120 | ||
8187a2b7 | 1121 | do { |
c7dca47b CW |
1122 | ring->head = I915_READ_HEAD(ring); |
1123 | ring->space = ring_space(ring); | |
62fdfeaf | 1124 | if (ring->space >= n) { |
db53a302 | 1125 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1126 | return 0; |
1127 | } | |
1128 | ||
1129 | if (dev->primary->master) { | |
1130 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1131 | if (master_priv->sarea_priv) | |
1132 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1133 | } | |
d1b851fc | 1134 | |
e60a0b10 | 1135 | msleep(1); |
f4e0b29b CW |
1136 | if (atomic_read(&dev_priv->mm.wedged)) |
1137 | return -EAGAIN; | |
8187a2b7 | 1138 | } while (!time_after(jiffies, end)); |
db53a302 | 1139 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1140 | return -EBUSY; |
1141 | } | |
62fdfeaf | 1142 | |
e1f99ce6 CW |
1143 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1144 | int num_dwords) | |
8187a2b7 | 1145 | { |
21dd3734 | 1146 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
be26a10b | 1147 | int n = 4*num_dwords; |
e1f99ce6 | 1148 | int ret; |
78501eac | 1149 | |
21dd3734 CW |
1150 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
1151 | return -EIO; | |
1152 | ||
55249baa | 1153 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1154 | ret = intel_wrap_ring_buffer(ring); |
1155 | if (unlikely(ret)) | |
1156 | return ret; | |
1157 | } | |
78501eac | 1158 | |
e1f99ce6 CW |
1159 | if (unlikely(ring->space < n)) { |
1160 | ret = intel_wait_ring_buffer(ring, n); | |
1161 | if (unlikely(ret)) | |
1162 | return ret; | |
1163 | } | |
d97ed339 CW |
1164 | |
1165 | ring->space -= n; | |
e1f99ce6 | 1166 | return 0; |
8187a2b7 | 1167 | } |
62fdfeaf | 1168 | |
78501eac | 1169 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1170 | { |
d97ed339 | 1171 | ring->tail &= ring->size - 1; |
78501eac | 1172 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1173 | } |
62fdfeaf | 1174 | |
881f47b6 | 1175 | |
78501eac | 1176 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1177 | u32 value) |
881f47b6 | 1178 | { |
0206e353 | 1179 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1180 | |
1181 | /* Every tail move must follow the sequence below */ | |
0206e353 AJ |
1182 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1183 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1184 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
1185 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
1186 | ||
1187 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
1188 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
1189 | 50)) | |
1190 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
1191 | ||
1192 | I915_WRITE_TAIL(ring, value); | |
1193 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1194 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1195 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
881f47b6 XH |
1196 | } |
1197 | ||
b72f3acb | 1198 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1199 | u32 invalidate, u32 flush) |
881f47b6 | 1200 | { |
71a77e07 | 1201 | uint32_t cmd; |
b72f3acb CW |
1202 | int ret; |
1203 | ||
b72f3acb CW |
1204 | ret = intel_ring_begin(ring, 4); |
1205 | if (ret) | |
1206 | return ret; | |
1207 | ||
71a77e07 CW |
1208 | cmd = MI_FLUSH_DW; |
1209 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1210 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1211 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1212 | intel_ring_emit(ring, 0); |
1213 | intel_ring_emit(ring, 0); | |
71a77e07 | 1214 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1215 | intel_ring_advance(ring); |
1216 | return 0; | |
881f47b6 XH |
1217 | } |
1218 | ||
1219 | static int | |
78501eac | 1220 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1221 | u32 offset, u32 len) |
881f47b6 | 1222 | { |
0206e353 | 1223 | int ret; |
ab6f8e32 | 1224 | |
0206e353 AJ |
1225 | ret = intel_ring_begin(ring, 2); |
1226 | if (ret) | |
1227 | return ret; | |
e1f99ce6 | 1228 | |
0206e353 AJ |
1229 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1230 | /* bit0-7 is the length on GEN6+ */ | |
1231 | intel_ring_emit(ring, offset); | |
1232 | intel_ring_advance(ring); | |
ab6f8e32 | 1233 | |
0206e353 | 1234 | return 0; |
881f47b6 XH |
1235 | } |
1236 | ||
549f7365 CW |
1237 | /* Blitter support (SandyBridge+) */ |
1238 | ||
b72f3acb | 1239 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1240 | u32 invalidate, u32 flush) |
8d19215b | 1241 | { |
71a77e07 | 1242 | uint32_t cmd; |
b72f3acb CW |
1243 | int ret; |
1244 | ||
6a233c78 | 1245 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1246 | if (ret) |
1247 | return ret; | |
1248 | ||
71a77e07 CW |
1249 | cmd = MI_FLUSH_DW; |
1250 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1251 | cmd |= MI_INVALIDATE_TLB; | |
1252 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1253 | intel_ring_emit(ring, 0); |
1254 | intel_ring_emit(ring, 0); | |
71a77e07 | 1255 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1256 | intel_ring_advance(ring); |
1257 | return 0; | |
8d19215b ZN |
1258 | } |
1259 | ||
5c1143bb XH |
1260 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1261 | { | |
1262 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1263 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1264 | |
59465b5f DV |
1265 | ring->name = "render ring"; |
1266 | ring->id = RCS; | |
1267 | ring->mmio_base = RENDER_RING_BASE; | |
1268 | ||
1ec14ad3 CW |
1269 | if (INTEL_INFO(dev)->gen >= 6) { |
1270 | ring->add_request = gen6_add_request; | |
8d315287 | 1271 | ring->flush = gen6_render_ring_flush; |
25c06300 BW |
1272 | ring->irq_get = gen6_ring_get_irq; |
1273 | ring->irq_put = gen6_ring_put_irq; | |
6a848ccb | 1274 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
4cd53c0c | 1275 | ring->get_seqno = gen6_ring_get_seqno; |
686cb5f9 | 1276 | ring->sync_to = gen6_ring_sync; |
59465b5f DV |
1277 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
1278 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; | |
1279 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; | |
1280 | ring->signal_mbox[0] = GEN6_VRSYNC; | |
1281 | ring->signal_mbox[1] = GEN6_BRSYNC; | |
c6df541c CW |
1282 | } else if (IS_GEN5(dev)) { |
1283 | ring->add_request = pc_render_add_request; | |
59465b5f | 1284 | ring->flush = render_ring_flush; |
c6df541c | 1285 | ring->get_seqno = pc_render_get_seqno; |
e48d8634 DV |
1286 | ring->irq_get = gen5_ring_get_irq; |
1287 | ring->irq_put = gen5_ring_put_irq; | |
e3670319 | 1288 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
59465b5f | 1289 | } else { |
8620a3a9 | 1290 | ring->add_request = i9xx_add_request; |
59465b5f DV |
1291 | ring->flush = render_ring_flush; |
1292 | ring->get_seqno = ring_get_seqno; | |
e3670319 DV |
1293 | ring->irq_get = i9xx_ring_get_irq; |
1294 | ring->irq_put = i9xx_ring_put_irq; | |
1295 | ring->irq_enable_mask = I915_USER_INTERRUPT; | |
1ec14ad3 | 1296 | } |
59465b5f | 1297 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1298 | if (INTEL_INFO(dev)->gen >= 6) |
1299 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1300 | else if (INTEL_INFO(dev)->gen >= 4) | |
1301 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1302 | else if (IS_I830(dev) || IS_845G(dev)) | |
1303 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1304 | else | |
1305 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1306 | ring->init = init_render_ring; |
1307 | ring->cleanup = render_ring_cleanup; | |
1308 | ||
5c1143bb XH |
1309 | |
1310 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1311 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1312 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1313 | } |
1314 | ||
1ec14ad3 | 1315 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1316 | } |
1317 | ||
e8616b6c CW |
1318 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1319 | { | |
1320 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1321 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1322 | ||
59465b5f DV |
1323 | ring->name = "render ring"; |
1324 | ring->id = RCS; | |
1325 | ring->mmio_base = RENDER_RING_BASE; | |
1326 | ||
e8616b6c | 1327 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1328 | /* non-kms not supported on gen6+ */ |
1329 | return -ENODEV; | |
e8616b6c | 1330 | } |
28f0cbf7 DV |
1331 | |
1332 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1333 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1334 | * the special gen5 functions. */ | |
1335 | ring->add_request = i9xx_add_request; | |
1336 | ring->flush = render_ring_flush; | |
1337 | ring->get_seqno = ring_get_seqno; | |
1338 | ring->irq_get = i9xx_ring_get_irq; | |
1339 | ring->irq_put = i9xx_ring_put_irq; | |
1340 | ring->irq_enable_mask = I915_USER_INTERRUPT; | |
59465b5f | 1341 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1342 | if (INTEL_INFO(dev)->gen >= 4) |
1343 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1344 | else if (IS_I830(dev) || IS_845G(dev)) | |
1345 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1346 | else | |
1347 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1348 | ring->init = init_render_ring; |
1349 | ring->cleanup = render_ring_cleanup; | |
e8616b6c | 1350 | |
f3234706 KP |
1351 | if (!I915_NEED_GFX_HWS(dev)) |
1352 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1353 | ||
e8616b6c CW |
1354 | ring->dev = dev; |
1355 | INIT_LIST_HEAD(&ring->active_list); | |
1356 | INIT_LIST_HEAD(&ring->request_list); | |
1357 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
1358 | ||
1359 | ring->size = size; | |
1360 | ring->effective_size = ring->size; | |
1361 | if (IS_I830(ring->dev)) | |
1362 | ring->effective_size -= 128; | |
1363 | ||
1364 | ring->map.offset = start; | |
1365 | ring->map.size = size; | |
1366 | ring->map.type = 0; | |
1367 | ring->map.flags = 0; | |
1368 | ring->map.mtrr = 0; | |
1369 | ||
1370 | drm_core_ioremap_wc(&ring->map, dev); | |
1371 | if (ring->map.handle == NULL) { | |
1372 | DRM_ERROR("can not ioremap virtual address for" | |
1373 | " ring buffer\n"); | |
1374 | return -ENOMEM; | |
1375 | } | |
1376 | ||
1377 | ring->virtual_start = (void __force __iomem *)ring->map.handle; | |
1378 | return 0; | |
1379 | } | |
1380 | ||
5c1143bb XH |
1381 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1382 | { | |
1383 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1384 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1385 | |
58fa3835 DV |
1386 | ring->name = "bsd ring"; |
1387 | ring->id = VCS; | |
1388 | ||
0fd2c201 | 1389 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1390 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1391 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1392 | /* gen6 bsd needs a special wa for tail updates */ |
1393 | if (IS_GEN6(dev)) | |
1394 | ring->write_tail = gen6_bsd_ring_write_tail; | |
58fa3835 DV |
1395 | ring->flush = gen6_ring_flush; |
1396 | ring->add_request = gen6_add_request; | |
1397 | ring->get_seqno = gen6_ring_get_seqno; | |
1398 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; | |
1399 | ring->irq_get = gen6_ring_get_irq; | |
1400 | ring->irq_put = gen6_ring_put_irq; | |
1401 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1402 | ring->sync_to = gen6_ring_sync; |
58fa3835 DV |
1403 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
1404 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; | |
1405 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; | |
1406 | ring->signal_mbox[0] = GEN6_RVSYNC; | |
1407 | ring->signal_mbox[1] = GEN6_BVSYNC; | |
1408 | } else { | |
1409 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1410 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1411 | ring->add_request = i9xx_add_request; |
58fa3835 | 1412 | ring->get_seqno = ring_get_seqno; |
e48d8634 | 1413 | if (IS_GEN5(dev)) { |
e3670319 | 1414 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
e48d8634 DV |
1415 | ring->irq_get = gen5_ring_get_irq; |
1416 | ring->irq_put = gen5_ring_put_irq; | |
1417 | } else { | |
e3670319 | 1418 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1419 | ring->irq_get = i9xx_ring_get_irq; |
1420 | ring->irq_put = i9xx_ring_put_irq; | |
1421 | } | |
fb3256da | 1422 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1423 | } |
1424 | ring->init = init_ring_common; | |
1425 | ||
5c1143bb | 1426 | |
1ec14ad3 | 1427 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1428 | } |
549f7365 CW |
1429 | |
1430 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1431 | { | |
1432 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1433 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1434 | |
3535d9dd DV |
1435 | ring->name = "blitter ring"; |
1436 | ring->id = BCS; | |
1437 | ||
1438 | ring->mmio_base = BLT_RING_BASE; | |
1439 | ring->write_tail = ring_write_tail; | |
1440 | ring->flush = blt_ring_flush; | |
1441 | ring->add_request = gen6_add_request; | |
1442 | ring->get_seqno = gen6_ring_get_seqno; | |
1443 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; | |
1444 | ring->irq_get = gen6_ring_get_irq; | |
1445 | ring->irq_put = gen6_ring_put_irq; | |
1446 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1447 | ring->sync_to = gen6_ring_sync; |
3535d9dd DV |
1448 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
1449 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; | |
1450 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; | |
1451 | ring->signal_mbox[0] = GEN6_RBSYNC; | |
1452 | ring->signal_mbox[1] = GEN6_VBSYNC; | |
1453 | ring->init = init_ring_common; | |
549f7365 | 1454 | |
1ec14ad3 | 1455 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1456 | } |