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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
8d315287 JB |
37 | /* |
38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
39 | * over cache flushing. | |
40 | */ | |
41 | struct pipe_control { | |
42 | struct drm_i915_gem_object *obj; | |
43 | volatile u32 *cpu_page; | |
44 | u32 gtt_offset; | |
45 | }; | |
46 | ||
c7dca47b CW |
47 | static inline int ring_space(struct intel_ring_buffer *ring) |
48 | { | |
49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
50 | if (space < 0) | |
51 | space += ring->size; | |
52 | return space; | |
53 | } | |
54 | ||
b72f3acb | 55 | static int |
46f0f8d1 CW |
56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
57 | u32 invalidate_domains, | |
58 | u32 flush_domains) | |
59 | { | |
60 | u32 cmd; | |
61 | int ret; | |
62 | ||
63 | cmd = MI_FLUSH; | |
31b14c9f | 64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
65 | cmd |= MI_NO_WRITE_FLUSH; |
66 | ||
67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
68 | cmd |= MI_READ_FLUSH; | |
69 | ||
70 | ret = intel_ring_begin(ring, 2); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | intel_ring_emit(ring, cmd); | |
75 | intel_ring_emit(ring, MI_NOOP); | |
76 | intel_ring_advance(ring); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int | |
82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
83 | u32 invalidate_domains, | |
84 | u32 flush_domains) | |
62fdfeaf | 85 | { |
78501eac | 86 | struct drm_device *dev = ring->dev; |
6f392d54 | 87 | u32 cmd; |
b72f3acb | 88 | int ret; |
6f392d54 | 89 | |
36d527de CW |
90 | /* |
91 | * read/write caches: | |
92 | * | |
93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
95 | * also flushed at 2d versus 3d pipeline switches. | |
96 | * | |
97 | * read-only caches: | |
98 | * | |
99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
100 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
101 | * | |
102 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
103 | * | |
104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
105 | * invalidated when MI_EXE_FLUSH is set. | |
106 | * | |
107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
108 | * invalidated with every MI_FLUSH. | |
109 | * | |
110 | * TLBs: | |
111 | * | |
112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
115 | * are flushed at any MI_FLUSH. | |
116 | */ | |
117 | ||
118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 120 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
122 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 123 | |
36d527de CW |
124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
125 | (IS_G4X(dev) || IS_GEN5(dev))) | |
126 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 127 | |
36d527de CW |
128 | ret = intel_ring_begin(ring, 2); |
129 | if (ret) | |
130 | return ret; | |
b72f3acb | 131 | |
36d527de CW |
132 | intel_ring_emit(ring, cmd); |
133 | intel_ring_emit(ring, MI_NOOP); | |
134 | intel_ring_advance(ring); | |
b72f3acb CW |
135 | |
136 | return 0; | |
8187a2b7 ZN |
137 | } |
138 | ||
8d315287 JB |
139 | /** |
140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
141 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
143 | * | |
144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
145 | * produced by non-pipelined state commands), software needs to first | |
146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
147 | * 0. | |
148 | * | |
149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
151 | * | |
152 | * And the workaround for these two requires this workaround first: | |
153 | * | |
154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
155 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
156 | * flushes. | |
157 | * | |
158 | * And this last workaround is tricky because of the requirements on | |
159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
160 | * volume 2 part 1: | |
161 | * | |
162 | * "1 of the following must also be set: | |
163 | * - Render Target Cache Flush Enable ([12] of DW1) | |
164 | * - Depth Cache Flush Enable ([0] of DW1) | |
165 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
166 | * - Depth Stall ([13] of DW1) | |
167 | * - Post-Sync Operation ([13] of DW1) | |
168 | * - Notify Enable ([8] of DW1)" | |
169 | * | |
170 | * The cache flushes require the workaround flush that triggered this | |
171 | * one, so we can't use it. Depth stall would trigger the same. | |
172 | * Post-sync nonzero is what triggered this second workaround, so we | |
173 | * can't use that one either. Notify enable is IRQs, which aren't | |
174 | * really our business. That leaves only stall at scoreboard. | |
175 | */ | |
176 | static int | |
177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
178 | { | |
179 | struct pipe_control *pc = ring->private; | |
180 | u32 scratch_addr = pc->gtt_offset + 128; | |
181 | int ret; | |
182 | ||
183 | ||
184 | ret = intel_ring_begin(ring, 6); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
189 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
190 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
192 | intel_ring_emit(ring, 0); /* low dword */ | |
193 | intel_ring_emit(ring, 0); /* high dword */ | |
194 | intel_ring_emit(ring, MI_NOOP); | |
195 | intel_ring_advance(ring); | |
196 | ||
197 | ret = intel_ring_begin(ring, 6); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
202 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
204 | intel_ring_emit(ring, 0); | |
205 | intel_ring_emit(ring, 0); | |
206 | intel_ring_emit(ring, MI_NOOP); | |
207 | intel_ring_advance(ring); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
213 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
214 | u32 invalidate_domains, u32 flush_domains) | |
215 | { | |
216 | u32 flags = 0; | |
217 | struct pipe_control *pc = ring->private; | |
218 | u32 scratch_addr = pc->gtt_offset + 128; | |
219 | int ret; | |
220 | ||
b3111509 PZ |
221 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
222 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
223 | if (ret) | |
224 | return ret; | |
225 | ||
8d315287 JB |
226 | /* Just flush everything. Experiments have shown that reducing the |
227 | * number of bits based on the write domains has little performance | |
228 | * impact. | |
229 | */ | |
7d54a904 CW |
230 | if (flush_domains) { |
231 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
232 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
233 | /* | |
234 | * Ensure that any following seqno writes only happen | |
235 | * when the render cache is indeed flushed. | |
236 | */ | |
97f209bc | 237 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
238 | } |
239 | if (invalidate_domains) { | |
240 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
244 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
245 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
246 | /* | |
247 | * TLB invalidate requires a post-sync write. | |
248 | */ | |
249 | flags |= PIPE_CONTROL_QW_WRITE; | |
250 | } | |
8d315287 | 251 | |
6c6cf5aa | 252 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
253 | if (ret) |
254 | return ret; | |
255 | ||
6c6cf5aa | 256 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
257 | intel_ring_emit(ring, flags); |
258 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 259 | intel_ring_emit(ring, 0); |
8d315287 JB |
260 | intel_ring_advance(ring); |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
f3987631 PZ |
265 | static int |
266 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
267 | { | |
268 | int ret; | |
269 | ||
270 | ret = intel_ring_begin(ring, 4); | |
271 | if (ret) | |
272 | return ret; | |
273 | ||
274 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
275 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
276 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_emit(ring, 0); | |
279 | intel_ring_advance(ring); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
4772eaeb PZ |
284 | static int |
285 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
286 | u32 invalidate_domains, u32 flush_domains) | |
287 | { | |
288 | u32 flags = 0; | |
289 | struct pipe_control *pc = ring->private; | |
290 | u32 scratch_addr = pc->gtt_offset + 128; | |
291 | int ret; | |
292 | ||
f3987631 PZ |
293 | /* |
294 | * Ensure that any following seqno writes only happen when the render | |
295 | * cache is indeed flushed. | |
296 | * | |
297 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
298 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
299 | * don't try to be clever and just set it unconditionally. | |
300 | */ | |
301 | flags |= PIPE_CONTROL_CS_STALL; | |
302 | ||
4772eaeb PZ |
303 | /* Just flush everything. Experiments have shown that reducing the |
304 | * number of bits based on the write domains has little performance | |
305 | * impact. | |
306 | */ | |
307 | if (flush_domains) { | |
308 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
309 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
310 | } |
311 | if (invalidate_domains) { | |
312 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
313 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
314 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
315 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
317 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
318 | /* | |
319 | * TLB invalidate requires a post-sync write. | |
320 | */ | |
321 | flags |= PIPE_CONTROL_QW_WRITE; | |
f3987631 PZ |
322 | |
323 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
324 | * set before a pipe_control command that has the state cache | |
325 | * invalidate bit set. */ | |
326 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
327 | } |
328 | ||
329 | ret = intel_ring_begin(ring, 4); | |
330 | if (ret) | |
331 | return ret; | |
332 | ||
333 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
334 | intel_ring_emit(ring, flags); | |
335 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
336 | intel_ring_emit(ring, 0); | |
337 | intel_ring_advance(ring); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
78501eac | 342 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 343 | u32 value) |
d46eefa2 | 344 | { |
78501eac | 345 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 346 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
347 | } |
348 | ||
78501eac | 349 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 350 | { |
78501eac CW |
351 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
352 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 353 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
354 | |
355 | return I915_READ(acthd_reg); | |
356 | } | |
357 | ||
78501eac | 358 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 359 | { |
b7884eb4 DV |
360 | struct drm_device *dev = ring->dev; |
361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 362 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 363 | int ret = 0; |
8187a2b7 | 364 | u32 head; |
8187a2b7 | 365 | |
b7884eb4 DV |
366 | if (HAS_FORCE_WAKE(dev)) |
367 | gen6_gt_force_wake_get(dev_priv); | |
368 | ||
8187a2b7 | 369 | /* Stop the ring if it's running. */ |
7f2ab699 | 370 | I915_WRITE_CTL(ring, 0); |
570ef608 | 371 | I915_WRITE_HEAD(ring, 0); |
78501eac | 372 | ring->write_tail(ring, 0); |
8187a2b7 | 373 | |
570ef608 | 374 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
375 | |
376 | /* G45 ring initialization fails to reset head to zero */ | |
377 | if (head != 0) { | |
6fd0d56e CW |
378 | DRM_DEBUG_KMS("%s head not reset to zero " |
379 | "ctl %08x head %08x tail %08x start %08x\n", | |
380 | ring->name, | |
381 | I915_READ_CTL(ring), | |
382 | I915_READ_HEAD(ring), | |
383 | I915_READ_TAIL(ring), | |
384 | I915_READ_START(ring)); | |
8187a2b7 | 385 | |
570ef608 | 386 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 387 | |
6fd0d56e CW |
388 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
389 | DRM_ERROR("failed to set %s head to zero " | |
390 | "ctl %08x head %08x tail %08x start %08x\n", | |
391 | ring->name, | |
392 | I915_READ_CTL(ring), | |
393 | I915_READ_HEAD(ring), | |
394 | I915_READ_TAIL(ring), | |
395 | I915_READ_START(ring)); | |
396 | } | |
8187a2b7 ZN |
397 | } |
398 | ||
0d8957c8 DV |
399 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
400 | * registers with the above sequence (the readback of the HEAD registers | |
401 | * also enforces ordering), otherwise the hw might lose the new ring | |
402 | * register values. */ | |
403 | I915_WRITE_START(ring, obj->gtt_offset); | |
7f2ab699 | 404 | I915_WRITE_CTL(ring, |
ae69b42a | 405 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 406 | | RING_VALID); |
8187a2b7 | 407 | |
8187a2b7 | 408 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
409 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
410 | I915_READ_START(ring) == obj->gtt_offset && | |
411 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
412 | DRM_ERROR("%s initialization failed " |
413 | "ctl %08x head %08x tail %08x start %08x\n", | |
414 | ring->name, | |
415 | I915_READ_CTL(ring), | |
416 | I915_READ_HEAD(ring), | |
417 | I915_READ_TAIL(ring), | |
418 | I915_READ_START(ring)); | |
b7884eb4 DV |
419 | ret = -EIO; |
420 | goto out; | |
8187a2b7 ZN |
421 | } |
422 | ||
78501eac CW |
423 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
424 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 425 | else { |
c7dca47b | 426 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 427 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 428 | ring->space = ring_space(ring); |
c3b20037 | 429 | ring->last_retired_head = -1; |
8187a2b7 | 430 | } |
1ec14ad3 | 431 | |
b7884eb4 DV |
432 | out: |
433 | if (HAS_FORCE_WAKE(dev)) | |
434 | gen6_gt_force_wake_put(dev_priv); | |
435 | ||
436 | return ret; | |
8187a2b7 ZN |
437 | } |
438 | ||
c6df541c CW |
439 | static int |
440 | init_pipe_control(struct intel_ring_buffer *ring) | |
441 | { | |
442 | struct pipe_control *pc; | |
443 | struct drm_i915_gem_object *obj; | |
444 | int ret; | |
445 | ||
446 | if (ring->private) | |
447 | return 0; | |
448 | ||
449 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
450 | if (!pc) | |
451 | return -ENOMEM; | |
452 | ||
453 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
454 | if (obj == NULL) { | |
455 | DRM_ERROR("Failed to allocate seqno page\n"); | |
456 | ret = -ENOMEM; | |
457 | goto err; | |
458 | } | |
e4ffd173 CW |
459 | |
460 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c | 461 | |
86a1ee26 | 462 | ret = i915_gem_object_pin(obj, 4096, true, false); |
c6df541c CW |
463 | if (ret) |
464 | goto err_unref; | |
465 | ||
466 | pc->gtt_offset = obj->gtt_offset; | |
9da3da66 | 467 | pc->cpu_page = kmap(sg_page(obj->pages->sgl)); |
c6df541c CW |
468 | if (pc->cpu_page == NULL) |
469 | goto err_unpin; | |
470 | ||
471 | pc->obj = obj; | |
472 | ring->private = pc; | |
473 | return 0; | |
474 | ||
475 | err_unpin: | |
476 | i915_gem_object_unpin(obj); | |
477 | err_unref: | |
478 | drm_gem_object_unreference(&obj->base); | |
479 | err: | |
480 | kfree(pc); | |
481 | return ret; | |
482 | } | |
483 | ||
484 | static void | |
485 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
486 | { | |
487 | struct pipe_control *pc = ring->private; | |
488 | struct drm_i915_gem_object *obj; | |
489 | ||
490 | if (!ring->private) | |
491 | return; | |
492 | ||
493 | obj = pc->obj; | |
9da3da66 CW |
494 | |
495 | kunmap(sg_page(obj->pages->sgl)); | |
c6df541c CW |
496 | i915_gem_object_unpin(obj); |
497 | drm_gem_object_unreference(&obj->base); | |
498 | ||
499 | kfree(pc); | |
500 | ring->private = NULL; | |
501 | } | |
502 | ||
78501eac | 503 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 504 | { |
78501eac | 505 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 506 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 507 | int ret = init_ring_common(ring); |
a69ffdbf | 508 | |
a6c45cf0 | 509 | if (INTEL_INFO(dev)->gen > 3) { |
6b26c86d | 510 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
b095cd0a JB |
511 | if (IS_GEN7(dev)) |
512 | I915_WRITE(GFX_MODE_GEN7, | |
6b26c86d DV |
513 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
514 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 515 | } |
78501eac | 516 | |
8d315287 | 517 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
518 | ret = init_pipe_control(ring); |
519 | if (ret) | |
520 | return ret; | |
521 | } | |
522 | ||
5e13a0c5 | 523 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
524 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
525 | * "If this bit is set, STCunit will have LRA as replacement | |
526 | * policy. [...] This bit must be reset. LRA replacement | |
527 | * policy is not supported." | |
528 | */ | |
529 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 530 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
531 | |
532 | /* This is not explicitly set for GEN6, so read the register. | |
533 | * see intel_ring_mi_set_context() for why we care. | |
534 | * TODO: consider explicitly setting the bit for GEN5 | |
535 | */ | |
536 | ring->itlb_before_ctx_switch = | |
537 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
538 | } |
539 | ||
6b26c86d DV |
540 | if (INTEL_INFO(dev)->gen >= 6) |
541 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 542 | |
e1ef7cc2 | 543 | if (HAS_L3_GPU_CACHE(dev)) |
15b9f80e BW |
544 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
545 | ||
8187a2b7 ZN |
546 | return ret; |
547 | } | |
548 | ||
c6df541c CW |
549 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
550 | { | |
551 | if (!ring->private) | |
552 | return; | |
553 | ||
554 | cleanup_pipe_control(ring); | |
555 | } | |
556 | ||
1ec14ad3 | 557 | static void |
c8c99b0f BW |
558 | update_mboxes(struct intel_ring_buffer *ring, |
559 | u32 seqno, | |
560 | u32 mmio_offset) | |
1ec14ad3 | 561 | { |
c8c99b0f BW |
562 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
563 | MI_SEMAPHORE_GLOBAL_GTT | | |
564 | MI_SEMAPHORE_REGISTER | | |
565 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 566 | intel_ring_emit(ring, seqno); |
c8c99b0f | 567 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
568 | } |
569 | ||
c8c99b0f BW |
570 | /** |
571 | * gen6_add_request - Update the semaphore mailbox registers | |
572 | * | |
573 | * @ring - ring that is adding a request | |
574 | * @seqno - return seqno stuck into the ring | |
575 | * | |
576 | * Update the mailbox registers in the *other* rings with the current seqno. | |
577 | * This acts like a signal in the canonical semaphore. | |
578 | */ | |
1ec14ad3 CW |
579 | static int |
580 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 581 | u32 *seqno) |
1ec14ad3 | 582 | { |
c8c99b0f BW |
583 | u32 mbox1_reg; |
584 | u32 mbox2_reg; | |
1ec14ad3 CW |
585 | int ret; |
586 | ||
587 | ret = intel_ring_begin(ring, 10); | |
588 | if (ret) | |
589 | return ret; | |
590 | ||
c8c99b0f BW |
591 | mbox1_reg = ring->signal_mbox[0]; |
592 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 593 | |
53d227f2 | 594 | *seqno = i915_gem_next_request_seqno(ring); |
c8c99b0f BW |
595 | |
596 | update_mboxes(ring, *seqno, mbox1_reg); | |
597 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
598 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
599 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 600 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
601 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
602 | intel_ring_advance(ring); | |
603 | ||
1ec14ad3 CW |
604 | return 0; |
605 | } | |
606 | ||
c8c99b0f BW |
607 | /** |
608 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
609 | * | |
610 | * @waiter - ring that is waiting | |
611 | * @signaller - ring which has, or will signal | |
612 | * @seqno - seqno which the waiter will block on | |
613 | */ | |
614 | static int | |
686cb5f9 DV |
615 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
616 | struct intel_ring_buffer *signaller, | |
617 | u32 seqno) | |
1ec14ad3 CW |
618 | { |
619 | int ret; | |
c8c99b0f BW |
620 | u32 dw1 = MI_SEMAPHORE_MBOX | |
621 | MI_SEMAPHORE_COMPARE | | |
622 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 623 | |
1500f7ea BW |
624 | /* Throughout all of the GEM code, seqno passed implies our current |
625 | * seqno is >= the last seqno executed. However for hardware the | |
626 | * comparison is strictly greater than. | |
627 | */ | |
628 | seqno -= 1; | |
629 | ||
686cb5f9 DV |
630 | WARN_ON(signaller->semaphore_register[waiter->id] == |
631 | MI_SEMAPHORE_SYNC_INVALID); | |
632 | ||
c8c99b0f | 633 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
634 | if (ret) |
635 | return ret; | |
636 | ||
686cb5f9 DV |
637 | intel_ring_emit(waiter, |
638 | dw1 | signaller->semaphore_register[waiter->id]); | |
c8c99b0f BW |
639 | intel_ring_emit(waiter, seqno); |
640 | intel_ring_emit(waiter, 0); | |
641 | intel_ring_emit(waiter, MI_NOOP); | |
642 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
643 | |
644 | return 0; | |
645 | } | |
646 | ||
c6df541c CW |
647 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
648 | do { \ | |
fcbc34e4 KG |
649 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
650 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
651 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
652 | intel_ring_emit(ring__, 0); \ | |
653 | intel_ring_emit(ring__, 0); \ | |
654 | } while (0) | |
655 | ||
656 | static int | |
657 | pc_render_add_request(struct intel_ring_buffer *ring, | |
658 | u32 *result) | |
659 | { | |
53d227f2 | 660 | u32 seqno = i915_gem_next_request_seqno(ring); |
c6df541c CW |
661 | struct pipe_control *pc = ring->private; |
662 | u32 scratch_addr = pc->gtt_offset + 128; | |
663 | int ret; | |
664 | ||
665 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
666 | * incoherent with writes to memory, i.e. completely fubar, | |
667 | * so we need to use PIPE_NOTIFY instead. | |
668 | * | |
669 | * However, we also need to workaround the qword write | |
670 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
671 | * memory before requesting an interrupt. | |
672 | */ | |
673 | ret = intel_ring_begin(ring, 32); | |
674 | if (ret) | |
675 | return ret; | |
676 | ||
fcbc34e4 | 677 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
678 | PIPE_CONTROL_WRITE_FLUSH | |
679 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c CW |
680 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
681 | intel_ring_emit(ring, seqno); | |
682 | intel_ring_emit(ring, 0); | |
683 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
684 | scratch_addr += 128; /* write to separate cachelines */ | |
685 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
686 | scratch_addr += 128; | |
687 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
688 | scratch_addr += 128; | |
689 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
690 | scratch_addr += 128; | |
691 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
692 | scratch_addr += 128; | |
693 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 694 | |
fcbc34e4 | 695 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
696 | PIPE_CONTROL_WRITE_FLUSH | |
697 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
698 | PIPE_CONTROL_NOTIFY); |
699 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
700 | intel_ring_emit(ring, seqno); | |
701 | intel_ring_emit(ring, 0); | |
702 | intel_ring_advance(ring); | |
703 | ||
704 | *result = seqno; | |
705 | return 0; | |
706 | } | |
707 | ||
4cd53c0c | 708 | static u32 |
b2eadbc8 | 709 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 710 | { |
4cd53c0c DV |
711 | /* Workaround to force correct ordering between irq and seqno writes on |
712 | * ivb (and maybe also on snb) by reading from a CS register (like | |
713 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 714 | if (!lazy_coherency) |
4cd53c0c DV |
715 | intel_ring_get_active_head(ring); |
716 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
717 | } | |
718 | ||
8187a2b7 | 719 | static u32 |
b2eadbc8 | 720 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 721 | { |
1ec14ad3 CW |
722 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
723 | } | |
724 | ||
c6df541c | 725 | static u32 |
b2eadbc8 | 726 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c CW |
727 | { |
728 | struct pipe_control *pc = ring->private; | |
729 | return pc->cpu_page[0]; | |
730 | } | |
731 | ||
e48d8634 DV |
732 | static bool |
733 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
734 | { | |
735 | struct drm_device *dev = ring->dev; | |
736 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 737 | unsigned long flags; |
e48d8634 DV |
738 | |
739 | if (!dev->irq_enabled) | |
740 | return false; | |
741 | ||
7338aefa | 742 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
743 | if (ring->irq_refcount++ == 0) { |
744 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; | |
745 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
746 | POSTING_READ(GTIMR); | |
747 | } | |
7338aefa | 748 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
749 | |
750 | return true; | |
751 | } | |
752 | ||
753 | static void | |
754 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
755 | { | |
756 | struct drm_device *dev = ring->dev; | |
757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 758 | unsigned long flags; |
e48d8634 | 759 | |
7338aefa | 760 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
761 | if (--ring->irq_refcount == 0) { |
762 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; | |
763 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
764 | POSTING_READ(GTIMR); | |
765 | } | |
7338aefa | 766 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
767 | } |
768 | ||
b13c2b96 | 769 | static bool |
e3670319 | 770 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 771 | { |
78501eac | 772 | struct drm_device *dev = ring->dev; |
01a03331 | 773 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 774 | unsigned long flags; |
62fdfeaf | 775 | |
b13c2b96 CW |
776 | if (!dev->irq_enabled) |
777 | return false; | |
778 | ||
7338aefa | 779 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
780 | if (ring->irq_refcount++ == 0) { |
781 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
782 | I915_WRITE(IMR, dev_priv->irq_mask); | |
783 | POSTING_READ(IMR); | |
784 | } | |
7338aefa | 785 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
786 | |
787 | return true; | |
62fdfeaf EA |
788 | } |
789 | ||
8187a2b7 | 790 | static void |
e3670319 | 791 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 792 | { |
78501eac | 793 | struct drm_device *dev = ring->dev; |
01a03331 | 794 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 795 | unsigned long flags; |
62fdfeaf | 796 | |
7338aefa | 797 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
798 | if (--ring->irq_refcount == 0) { |
799 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
800 | I915_WRITE(IMR, dev_priv->irq_mask); | |
801 | POSTING_READ(IMR); | |
802 | } | |
7338aefa | 803 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
804 | } |
805 | ||
c2798b19 CW |
806 | static bool |
807 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
808 | { | |
809 | struct drm_device *dev = ring->dev; | |
810 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 811 | unsigned long flags; |
c2798b19 CW |
812 | |
813 | if (!dev->irq_enabled) | |
814 | return false; | |
815 | ||
7338aefa | 816 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
817 | if (ring->irq_refcount++ == 0) { |
818 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
819 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
820 | POSTING_READ16(IMR); | |
821 | } | |
7338aefa | 822 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
823 | |
824 | return true; | |
825 | } | |
826 | ||
827 | static void | |
828 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
829 | { | |
830 | struct drm_device *dev = ring->dev; | |
831 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 832 | unsigned long flags; |
c2798b19 | 833 | |
7338aefa | 834 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
835 | if (--ring->irq_refcount == 0) { |
836 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
837 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
838 | POSTING_READ16(IMR); | |
839 | } | |
7338aefa | 840 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
841 | } |
842 | ||
78501eac | 843 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 844 | { |
4593010b | 845 | struct drm_device *dev = ring->dev; |
78501eac | 846 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
847 | u32 mmio = 0; |
848 | ||
849 | /* The ring status page addresses are no longer next to the rest of | |
850 | * the ring registers as of gen7. | |
851 | */ | |
852 | if (IS_GEN7(dev)) { | |
853 | switch (ring->id) { | |
96154f2f | 854 | case RCS: |
4593010b EA |
855 | mmio = RENDER_HWS_PGA_GEN7; |
856 | break; | |
96154f2f | 857 | case BCS: |
4593010b EA |
858 | mmio = BLT_HWS_PGA_GEN7; |
859 | break; | |
96154f2f | 860 | case VCS: |
4593010b EA |
861 | mmio = BSD_HWS_PGA_GEN7; |
862 | break; | |
863 | } | |
864 | } else if (IS_GEN6(ring->dev)) { | |
865 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
866 | } else { | |
867 | mmio = RING_HWS_PGA(ring->mmio_base); | |
868 | } | |
869 | ||
78501eac CW |
870 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
871 | POSTING_READ(mmio); | |
8187a2b7 ZN |
872 | } |
873 | ||
b72f3acb | 874 | static int |
78501eac CW |
875 | bsd_ring_flush(struct intel_ring_buffer *ring, |
876 | u32 invalidate_domains, | |
877 | u32 flush_domains) | |
d1b851fc | 878 | { |
b72f3acb CW |
879 | int ret; |
880 | ||
b72f3acb CW |
881 | ret = intel_ring_begin(ring, 2); |
882 | if (ret) | |
883 | return ret; | |
884 | ||
885 | intel_ring_emit(ring, MI_FLUSH); | |
886 | intel_ring_emit(ring, MI_NOOP); | |
887 | intel_ring_advance(ring); | |
888 | return 0; | |
d1b851fc ZN |
889 | } |
890 | ||
3cce469c | 891 | static int |
8620a3a9 | 892 | i9xx_add_request(struct intel_ring_buffer *ring, |
3cce469c | 893 | u32 *result) |
d1b851fc ZN |
894 | { |
895 | u32 seqno; | |
3cce469c CW |
896 | int ret; |
897 | ||
898 | ret = intel_ring_begin(ring, 4); | |
899 | if (ret) | |
900 | return ret; | |
6f392d54 | 901 | |
53d227f2 | 902 | seqno = i915_gem_next_request_seqno(ring); |
6f392d54 | 903 | |
3cce469c CW |
904 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
905 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
906 | intel_ring_emit(ring, seqno); | |
907 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
908 | intel_ring_advance(ring); | |
d1b851fc | 909 | |
3cce469c CW |
910 | *result = seqno; |
911 | return 0; | |
d1b851fc ZN |
912 | } |
913 | ||
0f46832f | 914 | static bool |
25c06300 | 915 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
916 | { |
917 | struct drm_device *dev = ring->dev; | |
01a03331 | 918 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 919 | unsigned long flags; |
0f46832f CW |
920 | |
921 | if (!dev->irq_enabled) | |
922 | return false; | |
923 | ||
4cd53c0c DV |
924 | /* It looks like we need to prevent the gt from suspending while waiting |
925 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
926 | * blt/bsd rings on ivb. */ | |
99ffa162 | 927 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 928 | |
7338aefa | 929 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 930 | if (ring->irq_refcount++ == 0) { |
e1ef7cc2 | 931 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
932 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
933 | GEN6_RENDER_L3_PARITY_ERROR)); | |
934 | else | |
935 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
f637fde4 DV |
936 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
937 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
938 | POSTING_READ(GTIMR); | |
0f46832f | 939 | } |
7338aefa | 940 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
941 | |
942 | return true; | |
943 | } | |
944 | ||
945 | static void | |
25c06300 | 946 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
947 | { |
948 | struct drm_device *dev = ring->dev; | |
01a03331 | 949 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 950 | unsigned long flags; |
0f46832f | 951 | |
7338aefa | 952 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 953 | if (--ring->irq_refcount == 0) { |
e1ef7cc2 | 954 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
15b9f80e BW |
955 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
956 | else | |
957 | I915_WRITE_IMR(ring, ~0); | |
f637fde4 DV |
958 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
959 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
960 | POSTING_READ(GTIMR); | |
1ec14ad3 | 961 | } |
7338aefa | 962 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 963 | |
99ffa162 | 964 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
965 | } |
966 | ||
d1b851fc | 967 | static int |
fb3256da | 968 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 969 | { |
e1f99ce6 | 970 | int ret; |
78501eac | 971 | |
e1f99ce6 CW |
972 | ret = intel_ring_begin(ring, 2); |
973 | if (ret) | |
974 | return ret; | |
975 | ||
78501eac | 976 | intel_ring_emit(ring, |
65f56876 CW |
977 | MI_BATCH_BUFFER_START | |
978 | MI_BATCH_GTT | | |
78501eac | 979 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 980 | intel_ring_emit(ring, offset); |
78501eac CW |
981 | intel_ring_advance(ring); |
982 | ||
d1b851fc ZN |
983 | return 0; |
984 | } | |
985 | ||
8187a2b7 | 986 | static int |
fb3256da | 987 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 988 | u32 offset, u32 len) |
62fdfeaf | 989 | { |
c4e7a414 | 990 | int ret; |
62fdfeaf | 991 | |
fb3256da DV |
992 | ret = intel_ring_begin(ring, 4); |
993 | if (ret) | |
994 | return ret; | |
62fdfeaf | 995 | |
fb3256da DV |
996 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
997 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
998 | intel_ring_emit(ring, offset + len - 8); | |
999 | intel_ring_emit(ring, 0); | |
1000 | intel_ring_advance(ring); | |
e1f99ce6 | 1001 | |
fb3256da DV |
1002 | return 0; |
1003 | } | |
1004 | ||
1005 | static int | |
1006 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1007 | u32 offset, u32 len) | |
1008 | { | |
1009 | int ret; | |
1010 | ||
1011 | ret = intel_ring_begin(ring, 2); | |
1012 | if (ret) | |
1013 | return ret; | |
1014 | ||
65f56876 | 1015 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
fb3256da | 1016 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
c4e7a414 | 1017 | intel_ring_advance(ring); |
62fdfeaf | 1018 | |
62fdfeaf EA |
1019 | return 0; |
1020 | } | |
1021 | ||
78501eac | 1022 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1023 | { |
05394f39 | 1024 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1025 | |
8187a2b7 ZN |
1026 | obj = ring->status_page.obj; |
1027 | if (obj == NULL) | |
62fdfeaf | 1028 | return; |
62fdfeaf | 1029 | |
9da3da66 | 1030 | kunmap(sg_page(obj->pages->sgl)); |
62fdfeaf | 1031 | i915_gem_object_unpin(obj); |
05394f39 | 1032 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1033 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1034 | } |
1035 | ||
78501eac | 1036 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1037 | { |
78501eac | 1038 | struct drm_device *dev = ring->dev; |
05394f39 | 1039 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1040 | int ret; |
1041 | ||
62fdfeaf EA |
1042 | obj = i915_gem_alloc_object(dev, 4096); |
1043 | if (obj == NULL) { | |
1044 | DRM_ERROR("Failed to allocate status page\n"); | |
1045 | ret = -ENOMEM; | |
1046 | goto err; | |
1047 | } | |
e4ffd173 CW |
1048 | |
1049 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1050 | |
86a1ee26 | 1051 | ret = i915_gem_object_pin(obj, 4096, true, false); |
62fdfeaf | 1052 | if (ret != 0) { |
62fdfeaf EA |
1053 | goto err_unref; |
1054 | } | |
1055 | ||
05394f39 | 1056 | ring->status_page.gfx_addr = obj->gtt_offset; |
9da3da66 | 1057 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1058 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1059 | ret = -ENOMEM; |
62fdfeaf EA |
1060 | goto err_unpin; |
1061 | } | |
8187a2b7 ZN |
1062 | ring->status_page.obj = obj; |
1063 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1064 | |
78501eac | 1065 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
1066 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1067 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1068 | |
1069 | return 0; | |
1070 | ||
1071 | err_unpin: | |
1072 | i915_gem_object_unpin(obj); | |
1073 | err_unref: | |
05394f39 | 1074 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1075 | err: |
8187a2b7 | 1076 | return ret; |
62fdfeaf EA |
1077 | } |
1078 | ||
c43b5634 BW |
1079 | static int intel_init_ring_buffer(struct drm_device *dev, |
1080 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1081 | { |
05394f39 | 1082 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1083 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1084 | int ret; |
1085 | ||
8187a2b7 | 1086 | ring->dev = dev; |
23bc5982 CW |
1087 | INIT_LIST_HEAD(&ring->active_list); |
1088 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1089 | ring->size = 32 * PAGE_SIZE; |
0dc79fb2 | 1090 | |
b259f673 | 1091 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1092 | |
8187a2b7 | 1093 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1094 | ret = init_status_page(ring); |
8187a2b7 ZN |
1095 | if (ret) |
1096 | return ret; | |
1097 | } | |
62fdfeaf | 1098 | |
8187a2b7 | 1099 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
1100 | if (obj == NULL) { |
1101 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1102 | ret = -ENOMEM; |
dd785e35 | 1103 | goto err_hws; |
62fdfeaf | 1104 | } |
62fdfeaf | 1105 | |
05394f39 | 1106 | ring->obj = obj; |
8187a2b7 | 1107 | |
86a1ee26 | 1108 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1109 | if (ret) |
1110 | goto err_unref; | |
62fdfeaf | 1111 | |
3eef8918 CW |
1112 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1113 | if (ret) | |
1114 | goto err_unpin; | |
1115 | ||
dd2757f8 DV |
1116 | ring->virtual_start = |
1117 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, | |
1118 | ring->size); | |
4225d0f2 | 1119 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1120 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1121 | ret = -EINVAL; |
dd785e35 | 1122 | goto err_unpin; |
62fdfeaf EA |
1123 | } |
1124 | ||
78501eac | 1125 | ret = ring->init(ring); |
dd785e35 CW |
1126 | if (ret) |
1127 | goto err_unmap; | |
62fdfeaf | 1128 | |
55249baa CW |
1129 | /* Workaround an erratum on the i830 which causes a hang if |
1130 | * the TAIL pointer points to within the last 2 cachelines | |
1131 | * of the buffer. | |
1132 | */ | |
1133 | ring->effective_size = ring->size; | |
27c1cbd0 | 1134 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1135 | ring->effective_size -= 128; |
1136 | ||
c584fe47 | 1137 | return 0; |
dd785e35 CW |
1138 | |
1139 | err_unmap: | |
4225d0f2 | 1140 | iounmap(ring->virtual_start); |
dd785e35 CW |
1141 | err_unpin: |
1142 | i915_gem_object_unpin(obj); | |
1143 | err_unref: | |
05394f39 CW |
1144 | drm_gem_object_unreference(&obj->base); |
1145 | ring->obj = NULL; | |
dd785e35 | 1146 | err_hws: |
78501eac | 1147 | cleanup_status_page(ring); |
8187a2b7 | 1148 | return ret; |
62fdfeaf EA |
1149 | } |
1150 | ||
78501eac | 1151 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1152 | { |
33626e6a CW |
1153 | struct drm_i915_private *dev_priv; |
1154 | int ret; | |
1155 | ||
05394f39 | 1156 | if (ring->obj == NULL) |
62fdfeaf EA |
1157 | return; |
1158 | ||
33626e6a CW |
1159 | /* Disable the ring buffer. The ring must be idle at this point */ |
1160 | dev_priv = ring->dev->dev_private; | |
96f298aa | 1161 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
1162 | if (ret) |
1163 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1164 | ring->name, ret); | |
1165 | ||
33626e6a CW |
1166 | I915_WRITE_CTL(ring, 0); |
1167 | ||
4225d0f2 | 1168 | iounmap(ring->virtual_start); |
62fdfeaf | 1169 | |
05394f39 CW |
1170 | i915_gem_object_unpin(ring->obj); |
1171 | drm_gem_object_unreference(&ring->obj->base); | |
1172 | ring->obj = NULL; | |
78501eac | 1173 | |
8d19215b ZN |
1174 | if (ring->cleanup) |
1175 | ring->cleanup(ring); | |
1176 | ||
78501eac | 1177 | cleanup_status_page(ring); |
62fdfeaf EA |
1178 | } |
1179 | ||
78501eac | 1180 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1181 | { |
4225d0f2 | 1182 | uint32_t __iomem *virt; |
55249baa | 1183 | int rem = ring->size - ring->tail; |
62fdfeaf | 1184 | |
8187a2b7 | 1185 | if (ring->space < rem) { |
78501eac | 1186 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
1187 | if (ret) |
1188 | return ret; | |
1189 | } | |
62fdfeaf | 1190 | |
4225d0f2 DV |
1191 | virt = ring->virtual_start + ring->tail; |
1192 | rem /= 4; | |
1193 | while (rem--) | |
1194 | iowrite32(MI_NOOP, virt++); | |
62fdfeaf | 1195 | |
8187a2b7 | 1196 | ring->tail = 0; |
c7dca47b | 1197 | ring->space = ring_space(ring); |
62fdfeaf EA |
1198 | |
1199 | return 0; | |
1200 | } | |
1201 | ||
a71d8d94 CW |
1202 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1203 | { | |
a71d8d94 CW |
1204 | int ret; |
1205 | ||
199b2bc2 | 1206 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1207 | if (!ret) |
1208 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1209 | |
1210 | return ret; | |
1211 | } | |
1212 | ||
1213 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1214 | { | |
1215 | struct drm_i915_gem_request *request; | |
1216 | u32 seqno = 0; | |
1217 | int ret; | |
1218 | ||
1219 | i915_gem_retire_requests_ring(ring); | |
1220 | ||
1221 | if (ring->last_retired_head != -1) { | |
1222 | ring->head = ring->last_retired_head; | |
1223 | ring->last_retired_head = -1; | |
1224 | ring->space = ring_space(ring); | |
1225 | if (ring->space >= n) | |
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | list_for_each_entry(request, &ring->request_list, list) { | |
1230 | int space; | |
1231 | ||
1232 | if (request->tail == -1) | |
1233 | continue; | |
1234 | ||
1235 | space = request->tail - (ring->tail + 8); | |
1236 | if (space < 0) | |
1237 | space += ring->size; | |
1238 | if (space >= n) { | |
1239 | seqno = request->seqno; | |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | /* Consume this request in case we need more space than | |
1244 | * is available and so need to prevent a race between | |
1245 | * updating last_retired_head and direct reads of | |
1246 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1247 | */ | |
1248 | request->tail = -1; | |
1249 | } | |
1250 | ||
1251 | if (seqno == 0) | |
1252 | return -ENOSPC; | |
1253 | ||
1254 | ret = intel_ring_wait_seqno(ring, seqno); | |
1255 | if (ret) | |
1256 | return ret; | |
1257 | ||
1258 | if (WARN_ON(ring->last_retired_head == -1)) | |
1259 | return -ENOSPC; | |
1260 | ||
1261 | ring->head = ring->last_retired_head; | |
1262 | ring->last_retired_head = -1; | |
1263 | ring->space = ring_space(ring); | |
1264 | if (WARN_ON(ring->space < n)) | |
1265 | return -ENOSPC; | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
78501eac | 1270 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1271 | { |
78501eac | 1272 | struct drm_device *dev = ring->dev; |
cae5852d | 1273 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1274 | unsigned long end; |
a71d8d94 | 1275 | int ret; |
c7dca47b | 1276 | |
a71d8d94 CW |
1277 | ret = intel_ring_wait_request(ring, n); |
1278 | if (ret != -ENOSPC) | |
1279 | return ret; | |
1280 | ||
db53a302 | 1281 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1282 | /* With GEM the hangcheck timer should kick us out of the loop, |
1283 | * leaving it early runs the risk of corrupting GEM state (due | |
1284 | * to running on almost untested codepaths). But on resume | |
1285 | * timers don't work yet, so prevent a complete hang in that | |
1286 | * case by choosing an insanely large timeout. */ | |
1287 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1288 | |
8187a2b7 | 1289 | do { |
c7dca47b CW |
1290 | ring->head = I915_READ_HEAD(ring); |
1291 | ring->space = ring_space(ring); | |
62fdfeaf | 1292 | if (ring->space >= n) { |
db53a302 | 1293 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1294 | return 0; |
1295 | } | |
1296 | ||
1297 | if (dev->primary->master) { | |
1298 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1299 | if (master_priv->sarea_priv) | |
1300 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1301 | } | |
d1b851fc | 1302 | |
e60a0b10 | 1303 | msleep(1); |
d6b2c790 DV |
1304 | |
1305 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); | |
1306 | if (ret) | |
1307 | return ret; | |
8187a2b7 | 1308 | } while (!time_after(jiffies, end)); |
db53a302 | 1309 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1310 | return -EBUSY; |
1311 | } | |
62fdfeaf | 1312 | |
e1f99ce6 CW |
1313 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1314 | int num_dwords) | |
8187a2b7 | 1315 | { |
de2b9985 | 1316 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
be26a10b | 1317 | int n = 4*num_dwords; |
e1f99ce6 | 1318 | int ret; |
78501eac | 1319 | |
de2b9985 DV |
1320 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
1321 | if (ret) | |
1322 | return ret; | |
21dd3734 | 1323 | |
55249baa | 1324 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1325 | ret = intel_wrap_ring_buffer(ring); |
1326 | if (unlikely(ret)) | |
1327 | return ret; | |
1328 | } | |
78501eac | 1329 | |
e1f99ce6 CW |
1330 | if (unlikely(ring->space < n)) { |
1331 | ret = intel_wait_ring_buffer(ring, n); | |
1332 | if (unlikely(ret)) | |
1333 | return ret; | |
1334 | } | |
d97ed339 CW |
1335 | |
1336 | ring->space -= n; | |
e1f99ce6 | 1337 | return 0; |
8187a2b7 | 1338 | } |
62fdfeaf | 1339 | |
78501eac | 1340 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1341 | { |
e5eb3d63 DV |
1342 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1343 | ||
d97ed339 | 1344 | ring->tail &= ring->size - 1; |
e5eb3d63 DV |
1345 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
1346 | return; | |
78501eac | 1347 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1348 | } |
62fdfeaf | 1349 | |
881f47b6 | 1350 | |
78501eac | 1351 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1352 | u32 value) |
881f47b6 | 1353 | { |
0206e353 | 1354 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1355 | |
1356 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1357 | |
1358 | /* Disable notification that the ring is IDLE. The GT | |
1359 | * will then assume that it is busy and bring it out of rc6. | |
1360 | */ | |
0206e353 | 1361 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1362 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1363 | ||
1364 | /* Clear the context id. Here be magic! */ | |
1365 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1366 | |
12f55818 | 1367 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1368 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1369 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1370 | 50)) | |
1371 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1372 | |
12f55818 | 1373 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1374 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1375 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1376 | ||
1377 | /* Let the ring send IDLE messages to the GT again, | |
1378 | * and so let it sleep to conserve power when idle. | |
1379 | */ | |
0206e353 | 1380 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1381 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1382 | } |
1383 | ||
b72f3acb | 1384 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1385 | u32 invalidate, u32 flush) |
881f47b6 | 1386 | { |
71a77e07 | 1387 | uint32_t cmd; |
b72f3acb CW |
1388 | int ret; |
1389 | ||
b72f3acb CW |
1390 | ret = intel_ring_begin(ring, 4); |
1391 | if (ret) | |
1392 | return ret; | |
1393 | ||
71a77e07 CW |
1394 | cmd = MI_FLUSH_DW; |
1395 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1396 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1397 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1398 | intel_ring_emit(ring, 0); |
1399 | intel_ring_emit(ring, 0); | |
71a77e07 | 1400 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1401 | intel_ring_advance(ring); |
1402 | return 0; | |
881f47b6 XH |
1403 | } |
1404 | ||
1405 | static int | |
78501eac | 1406 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1407 | u32 offset, u32 len) |
881f47b6 | 1408 | { |
0206e353 | 1409 | int ret; |
ab6f8e32 | 1410 | |
0206e353 AJ |
1411 | ret = intel_ring_begin(ring, 2); |
1412 | if (ret) | |
1413 | return ret; | |
e1f99ce6 | 1414 | |
0206e353 AJ |
1415 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1416 | /* bit0-7 is the length on GEN6+ */ | |
1417 | intel_ring_emit(ring, offset); | |
1418 | intel_ring_advance(ring); | |
ab6f8e32 | 1419 | |
0206e353 | 1420 | return 0; |
881f47b6 XH |
1421 | } |
1422 | ||
549f7365 CW |
1423 | /* Blitter support (SandyBridge+) */ |
1424 | ||
b72f3acb | 1425 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1426 | u32 invalidate, u32 flush) |
8d19215b | 1427 | { |
71a77e07 | 1428 | uint32_t cmd; |
b72f3acb CW |
1429 | int ret; |
1430 | ||
6a233c78 | 1431 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1432 | if (ret) |
1433 | return ret; | |
1434 | ||
71a77e07 CW |
1435 | cmd = MI_FLUSH_DW; |
1436 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1437 | cmd |= MI_INVALIDATE_TLB; | |
1438 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1439 | intel_ring_emit(ring, 0); |
1440 | intel_ring_emit(ring, 0); | |
71a77e07 | 1441 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1442 | intel_ring_advance(ring); |
1443 | return 0; | |
8d19215b ZN |
1444 | } |
1445 | ||
5c1143bb XH |
1446 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1447 | { | |
1448 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1449 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1450 | |
59465b5f DV |
1451 | ring->name = "render ring"; |
1452 | ring->id = RCS; | |
1453 | ring->mmio_base = RENDER_RING_BASE; | |
1454 | ||
1ec14ad3 CW |
1455 | if (INTEL_INFO(dev)->gen >= 6) { |
1456 | ring->add_request = gen6_add_request; | |
4772eaeb | 1457 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1458 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1459 | ring->flush = gen6_render_ring_flush; |
25c06300 BW |
1460 | ring->irq_get = gen6_ring_get_irq; |
1461 | ring->irq_put = gen6_ring_put_irq; | |
6a848ccb | 1462 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
4cd53c0c | 1463 | ring->get_seqno = gen6_ring_get_seqno; |
686cb5f9 | 1464 | ring->sync_to = gen6_ring_sync; |
59465b5f DV |
1465 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
1466 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; | |
1467 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; | |
1468 | ring->signal_mbox[0] = GEN6_VRSYNC; | |
1469 | ring->signal_mbox[1] = GEN6_BRSYNC; | |
c6df541c CW |
1470 | } else if (IS_GEN5(dev)) { |
1471 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1472 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1473 | ring->get_seqno = pc_render_get_seqno; |
e48d8634 DV |
1474 | ring->irq_get = gen5_ring_get_irq; |
1475 | ring->irq_put = gen5_ring_put_irq; | |
e3670319 | 1476 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
59465b5f | 1477 | } else { |
8620a3a9 | 1478 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1479 | if (INTEL_INFO(dev)->gen < 4) |
1480 | ring->flush = gen2_render_ring_flush; | |
1481 | else | |
1482 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1483 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1484 | if (IS_GEN2(dev)) { |
1485 | ring->irq_get = i8xx_ring_get_irq; | |
1486 | ring->irq_put = i8xx_ring_put_irq; | |
1487 | } else { | |
1488 | ring->irq_get = i9xx_ring_get_irq; | |
1489 | ring->irq_put = i9xx_ring_put_irq; | |
1490 | } | |
e3670319 | 1491 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1492 | } |
59465b5f | 1493 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1494 | if (INTEL_INFO(dev)->gen >= 6) |
1495 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1496 | else if (INTEL_INFO(dev)->gen >= 4) | |
1497 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1498 | else if (IS_I830(dev) || IS_845G(dev)) | |
1499 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1500 | else | |
1501 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1502 | ring->init = init_render_ring; |
1503 | ring->cleanup = render_ring_cleanup; | |
1504 | ||
5c1143bb XH |
1505 | |
1506 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1507 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1508 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1509 | } |
1510 | ||
1ec14ad3 | 1511 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1512 | } |
1513 | ||
e8616b6c CW |
1514 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1515 | { | |
1516 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1517 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1518 | ||
59465b5f DV |
1519 | ring->name = "render ring"; |
1520 | ring->id = RCS; | |
1521 | ring->mmio_base = RENDER_RING_BASE; | |
1522 | ||
e8616b6c | 1523 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1524 | /* non-kms not supported on gen6+ */ |
1525 | return -ENODEV; | |
e8616b6c | 1526 | } |
28f0cbf7 DV |
1527 | |
1528 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1529 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1530 | * the special gen5 functions. */ | |
1531 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1532 | if (INTEL_INFO(dev)->gen < 4) |
1533 | ring->flush = gen2_render_ring_flush; | |
1534 | else | |
1535 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1536 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1537 | if (IS_GEN2(dev)) { |
1538 | ring->irq_get = i8xx_ring_get_irq; | |
1539 | ring->irq_put = i8xx_ring_put_irq; | |
1540 | } else { | |
1541 | ring->irq_get = i9xx_ring_get_irq; | |
1542 | ring->irq_put = i9xx_ring_put_irq; | |
1543 | } | |
28f0cbf7 | 1544 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1545 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1546 | if (INTEL_INFO(dev)->gen >= 4) |
1547 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1548 | else if (IS_I830(dev) || IS_845G(dev)) | |
1549 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1550 | else | |
1551 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1552 | ring->init = init_render_ring; |
1553 | ring->cleanup = render_ring_cleanup; | |
e8616b6c | 1554 | |
f3234706 KP |
1555 | if (!I915_NEED_GFX_HWS(dev)) |
1556 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1557 | ||
e8616b6c CW |
1558 | ring->dev = dev; |
1559 | INIT_LIST_HEAD(&ring->active_list); | |
1560 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1561 | |
1562 | ring->size = size; | |
1563 | ring->effective_size = ring->size; | |
1564 | if (IS_I830(ring->dev)) | |
1565 | ring->effective_size -= 128; | |
1566 | ||
4225d0f2 DV |
1567 | ring->virtual_start = ioremap_wc(start, size); |
1568 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1569 | DRM_ERROR("can not ioremap virtual address for" |
1570 | " ring buffer\n"); | |
1571 | return -ENOMEM; | |
1572 | } | |
1573 | ||
e8616b6c CW |
1574 | return 0; |
1575 | } | |
1576 | ||
5c1143bb XH |
1577 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1578 | { | |
1579 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1580 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1581 | |
58fa3835 DV |
1582 | ring->name = "bsd ring"; |
1583 | ring->id = VCS; | |
1584 | ||
0fd2c201 | 1585 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1586 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1587 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1588 | /* gen6 bsd needs a special wa for tail updates */ |
1589 | if (IS_GEN6(dev)) | |
1590 | ring->write_tail = gen6_bsd_ring_write_tail; | |
58fa3835 DV |
1591 | ring->flush = gen6_ring_flush; |
1592 | ring->add_request = gen6_add_request; | |
1593 | ring->get_seqno = gen6_ring_get_seqno; | |
1594 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; | |
1595 | ring->irq_get = gen6_ring_get_irq; | |
1596 | ring->irq_put = gen6_ring_put_irq; | |
1597 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1598 | ring->sync_to = gen6_ring_sync; |
58fa3835 DV |
1599 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
1600 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; | |
1601 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; | |
1602 | ring->signal_mbox[0] = GEN6_RVSYNC; | |
1603 | ring->signal_mbox[1] = GEN6_BVSYNC; | |
1604 | } else { | |
1605 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1606 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1607 | ring->add_request = i9xx_add_request; |
58fa3835 | 1608 | ring->get_seqno = ring_get_seqno; |
e48d8634 | 1609 | if (IS_GEN5(dev)) { |
e3670319 | 1610 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
e48d8634 DV |
1611 | ring->irq_get = gen5_ring_get_irq; |
1612 | ring->irq_put = gen5_ring_put_irq; | |
1613 | } else { | |
e3670319 | 1614 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1615 | ring->irq_get = i9xx_ring_get_irq; |
1616 | ring->irq_put = i9xx_ring_put_irq; | |
1617 | } | |
fb3256da | 1618 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1619 | } |
1620 | ring->init = init_ring_common; | |
1621 | ||
5c1143bb | 1622 | |
1ec14ad3 | 1623 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1624 | } |
549f7365 CW |
1625 | |
1626 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1627 | { | |
1628 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1629 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1630 | |
3535d9dd DV |
1631 | ring->name = "blitter ring"; |
1632 | ring->id = BCS; | |
1633 | ||
1634 | ring->mmio_base = BLT_RING_BASE; | |
1635 | ring->write_tail = ring_write_tail; | |
1636 | ring->flush = blt_ring_flush; | |
1637 | ring->add_request = gen6_add_request; | |
1638 | ring->get_seqno = gen6_ring_get_seqno; | |
1639 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; | |
1640 | ring->irq_get = gen6_ring_get_irq; | |
1641 | ring->irq_put = gen6_ring_put_irq; | |
1642 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1643 | ring->sync_to = gen6_ring_sync; |
3535d9dd DV |
1644 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
1645 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; | |
1646 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; | |
1647 | ring->signal_mbox[0] = GEN6_RBSYNC; | |
1648 | ring->signal_mbox[1] = GEN6_VBSYNC; | |
1649 | ring->init = init_ring_common; | |
549f7365 | 1650 | |
1ec14ad3 | 1651 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1652 | } |
a7b9761d CW |
1653 | |
1654 | int | |
1655 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
1656 | { | |
1657 | int ret; | |
1658 | ||
1659 | if (!ring->gpu_caches_dirty) | |
1660 | return 0; | |
1661 | ||
1662 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1663 | if (ret) | |
1664 | return ret; | |
1665 | ||
1666 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1667 | ||
1668 | ring->gpu_caches_dirty = false; | |
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | int | |
1673 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
1674 | { | |
1675 | uint32_t flush_domains; | |
1676 | int ret; | |
1677 | ||
1678 | flush_domains = 0; | |
1679 | if (ring->gpu_caches_dirty) | |
1680 | flush_domains = I915_GEM_GPU_DOMAINS; | |
1681 | ||
1682 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1683 | if (ret) | |
1684 | return ret; | |
1685 | ||
1686 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1687 | ||
1688 | ring->gpu_caches_dirty = false; | |
1689 | return 0; | |
1690 | } |