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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
a4d8a0fe | 30 | #include <linux/log2.h> |
760285e7 | 31 | #include <drm/drmP.h> |
62fdfeaf | 32 | #include "i915_drv.h" |
760285e7 | 33 | #include <drm/i915_drm.h> |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
a0442461 CW |
37 | /* Rough estimate of the typical request size, performing a flush, |
38 | * set-context and then emitting the batch. | |
39 | */ | |
40 | #define LEGACY_REQUEST_SIZE 200 | |
41 | ||
82e104cc | 42 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 43 | { |
4f54741e DG |
44 | int space = head - tail; |
45 | if (space <= 0) | |
1cf0ba14 | 46 | space += size; |
4f54741e | 47 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
48 | } |
49 | ||
32c04f16 | 50 | void intel_ring_update_space(struct intel_ring *ring) |
ebd0fd4b | 51 | { |
32c04f16 CW |
52 | if (ring->last_retired_head != -1) { |
53 | ring->head = ring->last_retired_head; | |
54 | ring->last_retired_head = -1; | |
ebd0fd4b DG |
55 | } |
56 | ||
32c04f16 CW |
57 | ring->space = __intel_ring_space(ring->head & HEAD_ADDR, |
58 | ring->tail, ring->size); | |
ebd0fd4b DG |
59 | } |
60 | ||
b72f3acb | 61 | static int |
7c9cf4e3 | 62 | gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
46f0f8d1 | 63 | { |
7e37f889 | 64 | struct intel_ring *ring = req->ring; |
46f0f8d1 CW |
65 | u32 cmd; |
66 | int ret; | |
67 | ||
68 | cmd = MI_FLUSH; | |
46f0f8d1 | 69 | |
7c9cf4e3 | 70 | if (mode & EMIT_INVALIDATE) |
46f0f8d1 CW |
71 | cmd |= MI_READ_FLUSH; |
72 | ||
5fb9de1a | 73 | ret = intel_ring_begin(req, 2); |
46f0f8d1 CW |
74 | if (ret) |
75 | return ret; | |
76 | ||
b5321f30 CW |
77 | intel_ring_emit(ring, cmd); |
78 | intel_ring_emit(ring, MI_NOOP); | |
79 | intel_ring_advance(ring); | |
46f0f8d1 CW |
80 | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static int | |
7c9cf4e3 | 85 | gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
62fdfeaf | 86 | { |
7e37f889 | 87 | struct intel_ring *ring = req->ring; |
6f392d54 | 88 | u32 cmd; |
b72f3acb | 89 | int ret; |
6f392d54 | 90 | |
36d527de CW |
91 | /* |
92 | * read/write caches: | |
93 | * | |
94 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
95 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
96 | * also flushed at 2d versus 3d pipeline switches. | |
97 | * | |
98 | * read-only caches: | |
99 | * | |
100 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
101 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
102 | * | |
103 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
104 | * | |
105 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
106 | * invalidated when MI_EXE_FLUSH is set. | |
107 | * | |
108 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
109 | * invalidated with every MI_FLUSH. | |
110 | * | |
111 | * TLBs: | |
112 | * | |
113 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
114 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
115 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
116 | * are flushed at any MI_FLUSH. | |
117 | */ | |
118 | ||
b5321f30 | 119 | cmd = MI_FLUSH; |
7c9cf4e3 | 120 | if (mode & EMIT_INVALIDATE) { |
36d527de | 121 | cmd |= MI_EXE_FLUSH; |
b5321f30 CW |
122 | if (IS_G4X(req->i915) || IS_GEN5(req->i915)) |
123 | cmd |= MI_INVALIDATE_ISP; | |
124 | } | |
70eac33e | 125 | |
5fb9de1a | 126 | ret = intel_ring_begin(req, 2); |
36d527de CW |
127 | if (ret) |
128 | return ret; | |
b72f3acb | 129 | |
b5321f30 CW |
130 | intel_ring_emit(ring, cmd); |
131 | intel_ring_emit(ring, MI_NOOP); | |
132 | intel_ring_advance(ring); | |
b72f3acb CW |
133 | |
134 | return 0; | |
8187a2b7 ZN |
135 | } |
136 | ||
8d315287 JB |
137 | /** |
138 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
139 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
140 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
141 | * | |
142 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
143 | * produced by non-pipelined state commands), software needs to first | |
144 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
145 | * 0. | |
146 | * | |
147 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
148 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
149 | * | |
150 | * And the workaround for these two requires this workaround first: | |
151 | * | |
152 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
153 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
154 | * flushes. | |
155 | * | |
156 | * And this last workaround is tricky because of the requirements on | |
157 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
158 | * volume 2 part 1: | |
159 | * | |
160 | * "1 of the following must also be set: | |
161 | * - Render Target Cache Flush Enable ([12] of DW1) | |
162 | * - Depth Cache Flush Enable ([0] of DW1) | |
163 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
164 | * - Depth Stall ([13] of DW1) | |
165 | * - Post-Sync Operation ([13] of DW1) | |
166 | * - Notify Enable ([8] of DW1)" | |
167 | * | |
168 | * The cache flushes require the workaround flush that triggered this | |
169 | * one, so we can't use it. Depth stall would trigger the same. | |
170 | * Post-sync nonzero is what triggered this second workaround, so we | |
171 | * can't use that one either. Notify enable is IRQs, which aren't | |
172 | * really our business. That leaves only stall at scoreboard. | |
173 | */ | |
174 | static int | |
f2cf1fcc | 175 | intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) |
8d315287 | 176 | { |
7e37f889 | 177 | struct intel_ring *ring = req->ring; |
b5321f30 | 178 | u32 scratch_addr = |
bde13ebd | 179 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 JB |
180 | int ret; |
181 | ||
5fb9de1a | 182 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
183 | if (ret) |
184 | return ret; | |
185 | ||
b5321f30 CW |
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
8d315287 | 188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
b5321f30 CW |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
8d315287 | 194 | |
5fb9de1a | 195 | ret = intel_ring_begin(req, 6); |
8d315287 JB |
196 | if (ret) |
197 | return ret; | |
198 | ||
b5321f30 CW |
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
8d315287 JB |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
7c9cf4e3 | 211 | gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d315287 | 212 | { |
7e37f889 | 213 | struct intel_ring *ring = req->ring; |
b5321f30 | 214 | u32 scratch_addr = |
bde13ebd | 215 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
8d315287 | 216 | u32 flags = 0; |
8d315287 JB |
217 | int ret; |
218 | ||
b3111509 | 219 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
f2cf1fcc | 220 | ret = intel_emit_post_sync_nonzero_flush(req); |
b3111509 PZ |
221 | if (ret) |
222 | return ret; | |
223 | ||
8d315287 JB |
224 | /* Just flush everything. Experiments have shown that reducing the |
225 | * number of bits based on the write domains has little performance | |
226 | * impact. | |
227 | */ | |
7c9cf4e3 | 228 | if (mode & EMIT_FLUSH) { |
7d54a904 CW |
229 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
230 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
231 | /* | |
232 | * Ensure that any following seqno writes only happen | |
233 | * when the render cache is indeed flushed. | |
234 | */ | |
97f209bc | 235 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 | 236 | } |
7c9cf4e3 | 237 | if (mode & EMIT_INVALIDATE) { |
7d54a904 CW |
238 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
239 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
244 | /* | |
245 | * TLB invalidate requires a post-sync write. | |
246 | */ | |
3ac78313 | 247 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 248 | } |
8d315287 | 249 | |
5fb9de1a | 250 | ret = intel_ring_begin(req, 4); |
8d315287 JB |
251 | if (ret) |
252 | return ret; | |
253 | ||
b5321f30 CW |
254 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
255 | intel_ring_emit(ring, flags); | |
256 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | intel_ring_emit(ring, 0); | |
258 | intel_ring_advance(ring); | |
8d315287 JB |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
f3987631 | 263 | static int |
f2cf1fcc | 264 | gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) |
f3987631 | 265 | { |
7e37f889 | 266 | struct intel_ring *ring = req->ring; |
f3987631 PZ |
267 | int ret; |
268 | ||
5fb9de1a | 269 | ret = intel_ring_begin(req, 4); |
f3987631 PZ |
270 | if (ret) |
271 | return ret; | |
272 | ||
b5321f30 CW |
273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
274 | intel_ring_emit(ring, | |
275 | PIPE_CONTROL_CS_STALL | | |
276 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_emit(ring, 0); | |
279 | intel_ring_advance(ring); | |
f3987631 PZ |
280 | |
281 | return 0; | |
282 | } | |
283 | ||
4772eaeb | 284 | static int |
7c9cf4e3 | 285 | gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
4772eaeb | 286 | { |
7e37f889 | 287 | struct intel_ring *ring = req->ring; |
b5321f30 | 288 | u32 scratch_addr = |
bde13ebd | 289 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
4772eaeb | 290 | u32 flags = 0; |
4772eaeb PZ |
291 | int ret; |
292 | ||
f3987631 PZ |
293 | /* |
294 | * Ensure that any following seqno writes only happen when the render | |
295 | * cache is indeed flushed. | |
296 | * | |
297 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
298 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
299 | * don't try to be clever and just set it unconditionally. | |
300 | */ | |
301 | flags |= PIPE_CONTROL_CS_STALL; | |
302 | ||
4772eaeb PZ |
303 | /* Just flush everything. Experiments have shown that reducing the |
304 | * number of bits based on the write domains has little performance | |
305 | * impact. | |
306 | */ | |
7c9cf4e3 | 307 | if (mode & EMIT_FLUSH) { |
4772eaeb PZ |
308 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
309 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 310 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 311 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4772eaeb | 312 | } |
7c9cf4e3 | 313 | if (mode & EMIT_INVALIDATE) { |
4772eaeb PZ |
314 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
315 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
317 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
318 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
319 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 320 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
321 | /* |
322 | * TLB invalidate requires a post-sync write. | |
323 | */ | |
324 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 325 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 326 | |
add284a3 CW |
327 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
328 | ||
f3987631 PZ |
329 | /* Workaround: we must issue a pipe_control with CS-stall bit |
330 | * set before a pipe_control command that has the state cache | |
331 | * invalidate bit set. */ | |
f2cf1fcc | 332 | gen7_render_ring_cs_stall_wa(req); |
4772eaeb PZ |
333 | } |
334 | ||
5fb9de1a | 335 | ret = intel_ring_begin(req, 4); |
4772eaeb PZ |
336 | if (ret) |
337 | return ret; | |
338 | ||
b5321f30 CW |
339 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
340 | intel_ring_emit(ring, flags); | |
341 | intel_ring_emit(ring, scratch_addr); | |
342 | intel_ring_emit(ring, 0); | |
343 | intel_ring_advance(ring); | |
4772eaeb PZ |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
884ceace | 348 | static int |
f2cf1fcc | 349 | gen8_emit_pipe_control(struct drm_i915_gem_request *req, |
884ceace KG |
350 | u32 flags, u32 scratch_addr) |
351 | { | |
7e37f889 | 352 | struct intel_ring *ring = req->ring; |
884ceace KG |
353 | int ret; |
354 | ||
5fb9de1a | 355 | ret = intel_ring_begin(req, 6); |
884ceace KG |
356 | if (ret) |
357 | return ret; | |
358 | ||
b5321f30 CW |
359 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
360 | intel_ring_emit(ring, flags); | |
361 | intel_ring_emit(ring, scratch_addr); | |
362 | intel_ring_emit(ring, 0); | |
363 | intel_ring_emit(ring, 0); | |
364 | intel_ring_emit(ring, 0); | |
365 | intel_ring_advance(ring); | |
884ceace KG |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
a5f3d68e | 370 | static int |
7c9cf4e3 | 371 | gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
a5f3d68e | 372 | { |
56c0f1a7 | 373 | u32 scratch_addr = |
bde13ebd | 374 | i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; |
b5321f30 | 375 | u32 flags = 0; |
02c9f7e3 | 376 | int ret; |
a5f3d68e BW |
377 | |
378 | flags |= PIPE_CONTROL_CS_STALL; | |
379 | ||
7c9cf4e3 | 380 | if (mode & EMIT_FLUSH) { |
a5f3d68e BW |
381 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
382 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 383 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 384 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
a5f3d68e | 385 | } |
7c9cf4e3 | 386 | if (mode & EMIT_INVALIDATE) { |
a5f3d68e BW |
387 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
388 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
389 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
390 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
391 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
392 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
393 | flags |= PIPE_CONTROL_QW_WRITE; | |
394 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
395 | |
396 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
f2cf1fcc | 397 | ret = gen8_emit_pipe_control(req, |
02c9f7e3 KG |
398 | PIPE_CONTROL_CS_STALL | |
399 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
400 | 0); | |
401 | if (ret) | |
402 | return ret; | |
a5f3d68e BW |
403 | } |
404 | ||
f2cf1fcc | 405 | return gen8_emit_pipe_control(req, flags, scratch_addr); |
a5f3d68e BW |
406 | } |
407 | ||
0bc40be8 | 408 | static void ring_setup_phys_status_page(struct intel_engine_cs *engine) |
035dc1e0 | 409 | { |
c033666a | 410 | struct drm_i915_private *dev_priv = engine->i915; |
035dc1e0 DV |
411 | u32 addr; |
412 | ||
413 | addr = dev_priv->status_page_dmah->busaddr; | |
c033666a | 414 | if (INTEL_GEN(dev_priv) >= 4) |
035dc1e0 DV |
415 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; |
416 | I915_WRITE(HWS_PGA, addr); | |
417 | } | |
418 | ||
0bc40be8 | 419 | static void intel_ring_setup_status_page(struct intel_engine_cs *engine) |
af75f269 | 420 | { |
c033666a | 421 | struct drm_i915_private *dev_priv = engine->i915; |
f0f59a00 | 422 | i915_reg_t mmio; |
af75f269 DL |
423 | |
424 | /* The ring status page addresses are no longer next to the rest of | |
425 | * the ring registers as of gen7. | |
426 | */ | |
c033666a | 427 | if (IS_GEN7(dev_priv)) { |
0bc40be8 | 428 | switch (engine->id) { |
af75f269 DL |
429 | case RCS: |
430 | mmio = RENDER_HWS_PGA_GEN7; | |
431 | break; | |
432 | case BCS: | |
433 | mmio = BLT_HWS_PGA_GEN7; | |
434 | break; | |
435 | /* | |
436 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
437 | * gcc switch check warning | |
438 | */ | |
439 | case VCS2: | |
440 | case VCS: | |
441 | mmio = BSD_HWS_PGA_GEN7; | |
442 | break; | |
443 | case VECS: | |
444 | mmio = VEBOX_HWS_PGA_GEN7; | |
445 | break; | |
446 | } | |
c033666a | 447 | } else if (IS_GEN6(dev_priv)) { |
0bc40be8 | 448 | mmio = RING_HWS_PGA_GEN6(engine->mmio_base); |
af75f269 DL |
449 | } else { |
450 | /* XXX: gen8 returns to sanity */ | |
0bc40be8 | 451 | mmio = RING_HWS_PGA(engine->mmio_base); |
af75f269 DL |
452 | } |
453 | ||
57e88531 | 454 | I915_WRITE(mmio, engine->status_page.ggtt_offset); |
af75f269 DL |
455 | POSTING_READ(mmio); |
456 | ||
457 | /* | |
458 | * Flush the TLB for this page | |
459 | * | |
460 | * FIXME: These two bits have disappeared on gen8, so a question | |
461 | * arises: do we still need this and if so how should we go about | |
462 | * invalidating the TLB? | |
463 | */ | |
ac657f64 | 464 | if (IS_GEN(dev_priv, 6, 7)) { |
0bc40be8 | 465 | i915_reg_t reg = RING_INSTPM(engine->mmio_base); |
af75f269 DL |
466 | |
467 | /* ring should be idle before issuing a sync flush*/ | |
0bc40be8 | 468 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
af75f269 DL |
469 | |
470 | I915_WRITE(reg, | |
471 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
472 | INSTPM_SYNC_FLUSH)); | |
25ab57f4 CW |
473 | if (intel_wait_for_register(dev_priv, |
474 | reg, INSTPM_SYNC_FLUSH, 0, | |
475 | 1000)) | |
af75f269 | 476 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", |
0bc40be8 | 477 | engine->name); |
af75f269 DL |
478 | } |
479 | } | |
480 | ||
0bc40be8 | 481 | static bool stop_ring(struct intel_engine_cs *engine) |
8187a2b7 | 482 | { |
c033666a | 483 | struct drm_i915_private *dev_priv = engine->i915; |
8187a2b7 | 484 | |
21a2c58a | 485 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 | 486 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
3d808eb1 CW |
487 | if (intel_wait_for_register(dev_priv, |
488 | RING_MI_MODE(engine->mmio_base), | |
489 | MODE_IDLE, | |
490 | MODE_IDLE, | |
491 | 1000)) { | |
0bc40be8 TU |
492 | DRM_ERROR("%s : timed out trying to stop ring\n", |
493 | engine->name); | |
9bec9b13 CW |
494 | /* Sometimes we observe that the idle flag is not |
495 | * set even though the ring is empty. So double | |
496 | * check before giving up. | |
497 | */ | |
0bc40be8 | 498 | if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) |
9bec9b13 | 499 | return false; |
9991ae78 CW |
500 | } |
501 | } | |
b7884eb4 | 502 | |
0bc40be8 TU |
503 | I915_WRITE_CTL(engine, 0); |
504 | I915_WRITE_HEAD(engine, 0); | |
c5efa1ad | 505 | I915_WRITE_TAIL(engine, 0); |
8187a2b7 | 506 | |
21a2c58a | 507 | if (INTEL_GEN(dev_priv) > 2) { |
0bc40be8 TU |
508 | (void)I915_READ_CTL(engine); |
509 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); | |
9991ae78 | 510 | } |
a51435a3 | 511 | |
0bc40be8 | 512 | return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; |
9991ae78 | 513 | } |
8187a2b7 | 514 | |
0bc40be8 | 515 | static int init_ring_common(struct intel_engine_cs *engine) |
9991ae78 | 516 | { |
c033666a | 517 | struct drm_i915_private *dev_priv = engine->i915; |
7e37f889 | 518 | struct intel_ring *ring = engine->buffer; |
9991ae78 CW |
519 | int ret = 0; |
520 | ||
59bad947 | 521 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 | 522 | |
0bc40be8 | 523 | if (!stop_ring(engine)) { |
9991ae78 | 524 | /* G45 ring initialization often fails to reset head to zero */ |
6fd0d56e CW |
525 | DRM_DEBUG_KMS("%s head not reset to zero " |
526 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
527 | engine->name, |
528 | I915_READ_CTL(engine), | |
529 | I915_READ_HEAD(engine), | |
530 | I915_READ_TAIL(engine), | |
531 | I915_READ_START(engine)); | |
8187a2b7 | 532 | |
0bc40be8 | 533 | if (!stop_ring(engine)) { |
6fd0d56e CW |
534 | DRM_ERROR("failed to set %s head to zero " |
535 | "ctl %08x head %08x tail %08x start %08x\n", | |
0bc40be8 TU |
536 | engine->name, |
537 | I915_READ_CTL(engine), | |
538 | I915_READ_HEAD(engine), | |
539 | I915_READ_TAIL(engine), | |
540 | I915_READ_START(engine)); | |
9991ae78 CW |
541 | ret = -EIO; |
542 | goto out; | |
6fd0d56e | 543 | } |
8187a2b7 ZN |
544 | } |
545 | ||
3177659a | 546 | if (HWS_NEEDS_PHYSICAL(dev_priv)) |
0bc40be8 | 547 | ring_setup_phys_status_page(engine); |
3177659a CS |
548 | else |
549 | intel_ring_setup_status_page(engine); | |
9991ae78 | 550 | |
ad07dfcd | 551 | intel_engine_reset_breadcrumbs(engine); |
821ed7df | 552 | |
ece4a17d | 553 | /* Enforce ordering by reading HEAD register back */ |
0bc40be8 | 554 | I915_READ_HEAD(engine); |
ece4a17d | 555 | |
0d8957c8 DV |
556 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
557 | * registers with the above sequence (the readback of the HEAD registers | |
558 | * also enforces ordering), otherwise the hw might lose the new ring | |
559 | * register values. */ | |
bde13ebd | 560 | I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); |
95468892 CW |
561 | |
562 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
0bc40be8 | 563 | if (I915_READ_HEAD(engine)) |
95468892 | 564 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", |
0bc40be8 | 565 | engine->name, I915_READ_HEAD(engine)); |
821ed7df CW |
566 | |
567 | intel_ring_update_space(ring); | |
568 | I915_WRITE_HEAD(engine, ring->head); | |
569 | I915_WRITE_TAIL(engine, ring->tail); | |
570 | (void)I915_READ_TAIL(engine); | |
95468892 | 571 | |
62ae14b1 | 572 | I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); |
8187a2b7 | 573 | |
8187a2b7 | 574 | /* If the head is still not zero, the ring is dead */ |
821ed7df CW |
575 | if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base), |
576 | RING_VALID, RING_VALID, | |
577 | 50)) { | |
e74cfed5 | 578 | DRM_ERROR("%s initialization failed " |
821ed7df | 579 | "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n", |
0bc40be8 TU |
580 | engine->name, |
581 | I915_READ_CTL(engine), | |
582 | I915_READ_CTL(engine) & RING_VALID, | |
821ed7df CW |
583 | I915_READ_HEAD(engine), ring->head, |
584 | I915_READ_TAIL(engine), ring->tail, | |
0bc40be8 | 585 | I915_READ_START(engine), |
bde13ebd | 586 | i915_ggtt_offset(ring->vma)); |
b7884eb4 DV |
587 | ret = -EIO; |
588 | goto out; | |
8187a2b7 ZN |
589 | } |
590 | ||
fc0768ce | 591 | intel_engine_init_hangcheck(engine); |
50f018df | 592 | |
b7884eb4 | 593 | out: |
59bad947 | 594 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
595 | |
596 | return ret; | |
8187a2b7 ZN |
597 | } |
598 | ||
821ed7df CW |
599 | static void reset_ring_common(struct intel_engine_cs *engine, |
600 | struct drm_i915_gem_request *request) | |
601 | { | |
602 | struct intel_ring *ring = request->ring; | |
603 | ||
604 | ring->head = request->postfix; | |
605 | ring->last_retired_head = -1; | |
606 | } | |
607 | ||
e2be4faf | 608 | static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) |
86d7f238 | 609 | { |
7e37f889 | 610 | struct intel_ring *ring = req->ring; |
c033666a CW |
611 | struct i915_workarounds *w = &req->i915->workarounds; |
612 | int ret, i; | |
888b5995 | 613 | |
02235808 | 614 | if (w->count == 0) |
7225342a | 615 | return 0; |
888b5995 | 616 | |
7c9cf4e3 | 617 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
618 | if (ret) |
619 | return ret; | |
888b5995 | 620 | |
5fb9de1a | 621 | ret = intel_ring_begin(req, (w->count * 2 + 2)); |
7225342a MK |
622 | if (ret) |
623 | return ret; | |
624 | ||
b5321f30 | 625 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 626 | for (i = 0; i < w->count; i++) { |
b5321f30 CW |
627 | intel_ring_emit_reg(ring, w->reg[i].addr); |
628 | intel_ring_emit(ring, w->reg[i].value); | |
7225342a | 629 | } |
b5321f30 | 630 | intel_ring_emit(ring, MI_NOOP); |
7225342a | 631 | |
b5321f30 | 632 | intel_ring_advance(ring); |
7225342a | 633 | |
7c9cf4e3 | 634 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
7225342a MK |
635 | if (ret) |
636 | return ret; | |
888b5995 | 637 | |
7225342a | 638 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 639 | |
7225342a | 640 | return 0; |
86d7f238 AS |
641 | } |
642 | ||
8753181e | 643 | static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) |
8f0e2b9d DV |
644 | { |
645 | int ret; | |
646 | ||
e2be4faf | 647 | ret = intel_ring_workarounds_emit(req); |
8f0e2b9d DV |
648 | if (ret != 0) |
649 | return ret; | |
650 | ||
be01363f | 651 | ret = i915_gem_render_state_init(req); |
8f0e2b9d | 652 | if (ret) |
e26e1b97 | 653 | return ret; |
8f0e2b9d | 654 | |
e26e1b97 | 655 | return 0; |
8f0e2b9d DV |
656 | } |
657 | ||
7225342a | 658 | static int wa_add(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
659 | i915_reg_t addr, |
660 | const u32 mask, const u32 val) | |
7225342a MK |
661 | { |
662 | const u32 idx = dev_priv->workarounds.count; | |
663 | ||
664 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
665 | return -ENOSPC; | |
666 | ||
667 | dev_priv->workarounds.reg[idx].addr = addr; | |
668 | dev_priv->workarounds.reg[idx].value = val; | |
669 | dev_priv->workarounds.reg[idx].mask = mask; | |
670 | ||
671 | dev_priv->workarounds.count++; | |
672 | ||
673 | return 0; | |
86d7f238 AS |
674 | } |
675 | ||
ca5a0fbd | 676 | #define WA_REG(addr, mask, val) do { \ |
cf4b0de6 | 677 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ |
7225342a MK |
678 | if (r) \ |
679 | return r; \ | |
ca5a0fbd | 680 | } while (0) |
7225342a MK |
681 | |
682 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 683 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
684 | |
685 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 686 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 687 | |
98533251 | 688 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 689 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 690 | |
cf4b0de6 DL |
691 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
692 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 693 | |
cf4b0de6 | 694 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 695 | |
0bc40be8 TU |
696 | static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, |
697 | i915_reg_t reg) | |
33136b06 | 698 | { |
c033666a | 699 | struct drm_i915_private *dev_priv = engine->i915; |
33136b06 | 700 | struct i915_workarounds *wa = &dev_priv->workarounds; |
0bc40be8 | 701 | const uint32_t index = wa->hw_whitelist_count[engine->id]; |
33136b06 AS |
702 | |
703 | if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) | |
704 | return -EINVAL; | |
705 | ||
0bc40be8 | 706 | WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), |
33136b06 | 707 | i915_mmio_reg_offset(reg)); |
0bc40be8 | 708 | wa->hw_whitelist_count[engine->id]++; |
33136b06 AS |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
0bc40be8 | 713 | static int gen8_init_workarounds(struct intel_engine_cs *engine) |
e9a64ada | 714 | { |
c033666a | 715 | struct drm_i915_private *dev_priv = engine->i915; |
68c6198b AS |
716 | |
717 | WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); | |
e9a64ada | 718 | |
717d84d6 AS |
719 | /* WaDisableAsyncFlipPerfMode:bdw,chv */ |
720 | WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); | |
721 | ||
d0581194 AS |
722 | /* WaDisablePartialInstShootdown:bdw,chv */ |
723 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
724 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
725 | ||
a340af58 AS |
726 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
727 | * workaround for for a possible hang in the unlikely event a TLB | |
728 | * invalidation occurs during a PSD flush. | |
729 | */ | |
730 | /* WaForceEnableNonCoherent:bdw,chv */ | |
120f5d28 | 731 | /* WaHdcDisableFetchWhenMasked:bdw,chv */ |
a340af58 | 732 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
120f5d28 | 733 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
a340af58 AS |
734 | HDC_FORCE_NON_COHERENT); |
735 | ||
6def8fdd AS |
736 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
737 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
738 | * polygons in the same 8x4 pixel/sample area to be processed without | |
739 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
740 | * buffer." | |
741 | * | |
742 | * This optimization is off by default for BDW and CHV; turn it on. | |
743 | */ | |
744 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
745 | ||
48404636 AS |
746 | /* Wa4x4STCOptimizationDisable:bdw,chv */ |
747 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
748 | ||
7eebcde6 AS |
749 | /* |
750 | * BSpec recommends 8x4 when MSAA is used, | |
751 | * however in practice 16x4 seems fastest. | |
752 | * | |
753 | * Note that PS/WM thread counts depend on the WIZ hashing | |
754 | * disable bit, which we don't touch here, but it's good | |
755 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
756 | */ | |
757 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
758 | GEN6_WIZ_HASHING_MASK, | |
759 | GEN6_WIZ_HASHING_16x4); | |
760 | ||
e9a64ada AS |
761 | return 0; |
762 | } | |
763 | ||
0bc40be8 | 764 | static int bdw_init_workarounds(struct intel_engine_cs *engine) |
86d7f238 | 765 | { |
c033666a | 766 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 767 | int ret; |
86d7f238 | 768 | |
0bc40be8 | 769 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
770 | if (ret) |
771 | return ret; | |
772 | ||
101b376d | 773 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
d0581194 | 774 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
86d7f238 | 775 | |
101b376d | 776 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
777 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
778 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 779 | |
7225342a MK |
780 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
781 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 | 782 | |
7225342a | 783 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b DL |
784 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
785 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
35cb6f3b | 786 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
c033666a | 787 | (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 788 | |
86d7f238 AS |
789 | return 0; |
790 | } | |
791 | ||
0bc40be8 | 792 | static int chv_init_workarounds(struct intel_engine_cs *engine) |
00e1e623 | 793 | { |
c033666a | 794 | struct drm_i915_private *dev_priv = engine->i915; |
e9a64ada | 795 | int ret; |
00e1e623 | 796 | |
0bc40be8 | 797 | ret = gen8_init_workarounds(engine); |
e9a64ada AS |
798 | if (ret) |
799 | return ret; | |
800 | ||
00e1e623 | 801 | /* WaDisableThreadStallDopClockGating:chv */ |
d0581194 | 802 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); |
00e1e623 | 803 | |
d60de81d KG |
804 | /* Improve HiZ throughput on CHV. */ |
805 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
806 | ||
7225342a MK |
807 | return 0; |
808 | } | |
809 | ||
0bc40be8 | 810 | static int gen9_init_workarounds(struct intel_engine_cs *engine) |
3b106531 | 811 | { |
c033666a | 812 | struct drm_i915_private *dev_priv = engine->i915; |
e0f3fa09 | 813 | int ret; |
ab0dfafe | 814 | |
a8ab5ed5 TG |
815 | /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ |
816 | I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); | |
817 | ||
e5f81d65 | 818 | /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ |
9c4cbf82 MK |
819 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
820 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
821 | ||
e5f81d65 | 822 | /* WaDisableKillLogic:bxt,skl,kbl */ |
9c4cbf82 MK |
823 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | |
824 | ECOCHK_DIS_TLB); | |
825 | ||
e5f81d65 MK |
826 | /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ |
827 | /* WaDisablePartialInstShootdown:skl,bxt,kbl */ | |
ab0dfafe | 828 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
950b2aae | 829 | FLOW_CONTROL_ENABLE | |
ab0dfafe HN |
830 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); |
831 | ||
e5f81d65 | 832 | /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ |
8424171e NH |
833 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
834 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
835 | ||
a117f378 JN |
836 | /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */ |
837 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
a86eb582 DL |
838 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
839 | GEN9_DG_MIRROR_FIX_ENABLE); | |
1de4582f | 840 | |
a117f378 JN |
841 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */ |
842 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { | |
183c6dac DL |
843 | WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, |
844 | GEN9_RHWO_OPTIMIZATION_DISABLE); | |
9b01435d AS |
845 | /* |
846 | * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set | |
847 | * but we do that in per ctx batchbuffer as there is an issue | |
848 | * with this register not getting restored on ctx restore | |
849 | */ | |
183c6dac DL |
850 | } |
851 | ||
e5f81d65 MK |
852 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ |
853 | /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ | |
bfd8ad4e TG |
854 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, |
855 | GEN9_ENABLE_YV12_BUGFIX | | |
856 | GEN9_ENABLE_GPGPU_PREEMPTION); | |
cac23df4 | 857 | |
e5f81d65 MK |
858 | /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ |
859 | /* WaDisablePartialResolveInVc:skl,bxt,kbl */ | |
60294683 AS |
860 | WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | |
861 | GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); | |
9370cd98 | 862 | |
e5f81d65 | 863 | /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ |
e2db7071 DL |
864 | WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, |
865 | GEN9_CCS_TLB_PREFETCH_ENABLE); | |
866 | ||
0d0b8dcf JN |
867 | /* WaDisableMaskBasedCammingInRCC:bxt */ |
868 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
38a39a7b BW |
869 | WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, |
870 | PIXEL_MASK_CAMMING_DISABLE); | |
871 | ||
5b0e3659 MK |
872 | /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ |
873 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
874 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
875 | HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); | |
8ea6f892 | 876 | |
bbaefe72 MK |
877 | /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are |
878 | * both tied to WaForceContextSaveRestoreNonCoherent | |
879 | * in some hsds for skl. We keep the tie for all gen9. The | |
880 | * documentation is a bit hazy and so we want to get common behaviour, | |
881 | * even though there is no clear evidence we would need both on kbl/bxt. | |
882 | * This area has been source of system hangs so we play it safe | |
883 | * and mimic the skl regardless of what bspec says. | |
884 | * | |
885 | * Use Force Non-Coherent whenever executing a 3D context. This | |
886 | * is a workaround for a possible hang in the unlikely event | |
887 | * a TLB invalidation occurs during a PSD flush. | |
888 | */ | |
889 | ||
890 | /* WaForceEnableNonCoherent:skl,bxt,kbl */ | |
891 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
892 | HDC_FORCE_NON_COHERENT); | |
893 | ||
894 | /* WaDisableHDCInvalidation:skl,bxt,kbl */ | |
895 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
896 | BDW_DISABLE_HDC_INVALIDATION); | |
897 | ||
e5f81d65 MK |
898 | /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ |
899 | if (IS_SKYLAKE(dev_priv) || | |
900 | IS_KABYLAKE(dev_priv) || | |
901 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) | |
8c761609 AS |
902 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
903 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
8c761609 | 904 | |
e5f81d65 | 905 | /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ |
6b6d5626 RB |
906 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
907 | ||
e5f81d65 | 908 | /* WaOCLCoherentLineFlush:skl,bxt,kbl */ |
6ecf56ae AS |
909 | I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
910 | GEN8_LQSC_FLUSH_COHERENT_LINES)); | |
911 | ||
6bb62855 | 912 | /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ |
913 | ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); | |
914 | if (ret) | |
915 | return ret; | |
916 | ||
e5f81d65 | 917 | /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ |
0bc40be8 | 918 | ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); |
e0f3fa09 AS |
919 | if (ret) |
920 | return ret; | |
921 | ||
e5f81d65 | 922 | /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ |
0bc40be8 | 923 | ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); |
3669ab61 AS |
924 | if (ret) |
925 | return ret; | |
926 | ||
3b106531 HN |
927 | return 0; |
928 | } | |
929 | ||
0bc40be8 | 930 | static int skl_tune_iz_hashing(struct intel_engine_cs *engine) |
b7668791 | 931 | { |
c033666a | 932 | struct drm_i915_private *dev_priv = engine->i915; |
b7668791 DL |
933 | u8 vals[3] = { 0, 0, 0 }; |
934 | unsigned int i; | |
935 | ||
936 | for (i = 0; i < 3; i++) { | |
937 | u8 ss; | |
938 | ||
939 | /* | |
940 | * Only consider slices where one, and only one, subslice has 7 | |
941 | * EUs | |
942 | */ | |
43b67998 | 943 | if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i])) |
b7668791 DL |
944 | continue; |
945 | ||
946 | /* | |
947 | * subslice_7eu[i] != 0 (because of the check above) and | |
948 | * ss_max == 4 (maximum number of subslices possible per slice) | |
949 | * | |
950 | * -> 0 <= ss <= 3; | |
951 | */ | |
43b67998 | 952 | ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1; |
b7668791 DL |
953 | vals[i] = 3 - ss; |
954 | } | |
955 | ||
956 | if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) | |
957 | return 0; | |
958 | ||
959 | /* Tune IZ hashing. See intel_device_info_runtime_init() */ | |
960 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
961 | GEN9_IZ_HASHING_MASK(2) | | |
962 | GEN9_IZ_HASHING_MASK(1) | | |
963 | GEN9_IZ_HASHING_MASK(0), | |
964 | GEN9_IZ_HASHING(2, vals[2]) | | |
965 | GEN9_IZ_HASHING(1, vals[1]) | | |
966 | GEN9_IZ_HASHING(0, vals[0])); | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
0bc40be8 | 971 | static int skl_init_workarounds(struct intel_engine_cs *engine) |
8d205494 | 972 | { |
c033666a | 973 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 974 | int ret; |
d0bbbc4f | 975 | |
0bc40be8 | 976 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
977 | if (ret) |
978 | return ret; | |
8d205494 | 979 | |
a78536e7 AS |
980 | /* |
981 | * Actual WA is to disable percontext preemption granularity control | |
982 | * until D0 which is the default case so this is equivalent to | |
983 | * !WaDisablePerCtxtPreemptionGranularityControl:skl | |
984 | */ | |
9fc736e8 JN |
985 | I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
986 | _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); | |
a78536e7 | 987 | |
9c4cbf82 | 988 | /* WaEnableGapsTsvCreditFix:skl */ |
a117f378 JN |
989 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | |
990 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
d0bbbc4f | 991 | |
eee8efb0 MK |
992 | /* WaDisableGafsUnitClkGating:skl */ |
993 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
994 | ||
4ba9c1f7 MK |
995 | /* WaInPlaceDecompressionHang:skl */ |
996 | if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) | |
997 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
998 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
999 | ||
6107497e | 1000 | /* WaDisableLSQCROPERFforOCL:skl */ |
0bc40be8 | 1001 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
6107497e AS |
1002 | if (ret) |
1003 | return ret; | |
1004 | ||
0bc40be8 | 1005 | return skl_tune_iz_hashing(engine); |
7225342a MK |
1006 | } |
1007 | ||
0bc40be8 | 1008 | static int bxt_init_workarounds(struct intel_engine_cs *engine) |
cae0437f | 1009 | { |
c033666a | 1010 | struct drm_i915_private *dev_priv = engine->i915; |
aa0011a8 | 1011 | int ret; |
dfb601e6 | 1012 | |
0bc40be8 | 1013 | ret = gen9_init_workarounds(engine); |
aa0011a8 AS |
1014 | if (ret) |
1015 | return ret; | |
cae0437f | 1016 | |
9c4cbf82 MK |
1017 | /* WaStoreMultiplePTEenable:bxt */ |
1018 | /* This is a requirement according to Hardware specification */ | |
c033666a | 1019 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
9c4cbf82 MK |
1020 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); |
1021 | ||
1022 | /* WaSetClckGatingDisableMedia:bxt */ | |
c033666a | 1023 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
9c4cbf82 MK |
1024 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & |
1025 | ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); | |
1026 | } | |
1027 | ||
dfb601e6 NH |
1028 | /* WaDisableThreadStallDopClockGating:bxt */ |
1029 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
1030 | STALL_DOP_GATING_DISABLE); | |
1031 | ||
780f0aeb | 1032 | /* WaDisablePooledEuLoadBalancingFix:bxt */ |
1033 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { | |
1034 | WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, | |
1035 | GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); | |
1036 | } | |
1037 | ||
983b4b9d | 1038 | /* WaDisableSbeCacheDispatchPortSharing:bxt */ |
c033666a | 1039 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { |
983b4b9d NH |
1040 | WA_SET_BIT_MASKED( |
1041 | GEN7_HALF_SLICE_CHICKEN1, | |
1042 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1043 | } | |
1044 | ||
2c8580e4 AS |
1045 | /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
1046 | /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ | |
1047 | /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ | |
a786d53a | 1048 | /* WaDisableLSQCROPERFforOCL:bxt */ |
c033666a | 1049 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { |
0bc40be8 | 1050 | ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); |
2c8580e4 AS |
1051 | if (ret) |
1052 | return ret; | |
a786d53a | 1053 | |
0bc40be8 | 1054 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); |
a786d53a AS |
1055 | if (ret) |
1056 | return ret; | |
2c8580e4 AS |
1057 | } |
1058 | ||
050fc465 | 1059 | /* WaProgramL3SqcReg1DefaultForPerf:bxt */ |
c033666a | 1060 | if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) |
36579cb6 ID |
1061 | I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | |
1062 | L3_HIGH_PRIO_CREDITS(2)); | |
050fc465 | 1063 | |
575e3ccb MA |
1064 | /* WaToEnableHwFixForPushConstHWBug:bxt */ |
1065 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1066 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1067 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1068 | ||
4ba9c1f7 MK |
1069 | /* WaInPlaceDecompressionHang:bxt */ |
1070 | if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) | |
1071 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1072 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1073 | ||
cae0437f NH |
1074 | return 0; |
1075 | } | |
1076 | ||
e5f81d65 MK |
1077 | static int kbl_init_workarounds(struct intel_engine_cs *engine) |
1078 | { | |
e587f6cb | 1079 | struct drm_i915_private *dev_priv = engine->i915; |
e5f81d65 MK |
1080 | int ret; |
1081 | ||
1082 | ret = gen9_init_workarounds(engine); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
e587f6cb MK |
1086 | /* WaEnableGapsTsvCreditFix:kbl */ |
1087 | I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | | |
1088 | GEN9_GAPS_TSV_CREDIT_DISABLE)); | |
1089 | ||
c0b730d5 MK |
1090 | /* WaDisableDynamicCreditSharing:kbl */ |
1091 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
1092 | WA_SET_BIT(GAMT_CHKN_BIT_REG, | |
1093 | GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); | |
1094 | ||
8401d42f MK |
1095 | /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ |
1096 | if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) | |
1097 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
1098 | HDC_FENCE_DEST_SLM_DISABLE); | |
1099 | ||
fe905819 MK |
1100 | /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes |
1101 | * involving this register should also be added to WA batch as required. | |
1102 | */ | |
1103 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
1104 | /* WaDisableLSQCROPERFforOCL:kbl */ | |
1105 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
1106 | GEN8_LQSC_RO_PERF_DIS); | |
1107 | ||
575e3ccb MA |
1108 | /* WaToEnableHwFixForPushConstHWBug:kbl */ |
1109 | if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) | |
ad2bdb44 MK |
1110 | WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, |
1111 | GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); | |
1112 | ||
4de5d7cc MK |
1113 | /* WaDisableGafsUnitClkGating:kbl */ |
1114 | WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); | |
1115 | ||
954337aa MK |
1116 | /* WaDisableSbeCacheDispatchPortSharing:kbl */ |
1117 | WA_SET_BIT_MASKED( | |
1118 | GEN7_HALF_SLICE_CHICKEN1, | |
1119 | GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); | |
1120 | ||
4ba9c1f7 MK |
1121 | /* WaInPlaceDecompressionHang:kbl */ |
1122 | WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, | |
1123 | GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); | |
1124 | ||
fe905819 MK |
1125 | /* WaDisableLSQCROPERFforOCL:kbl */ |
1126 | ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); | |
1127 | if (ret) | |
1128 | return ret; | |
1129 | ||
e5f81d65 MK |
1130 | return 0; |
1131 | } | |
1132 | ||
0bc40be8 | 1133 | int init_workarounds_ring(struct intel_engine_cs *engine) |
7225342a | 1134 | { |
c033666a | 1135 | struct drm_i915_private *dev_priv = engine->i915; |
7225342a | 1136 | |
0bc40be8 | 1137 | WARN_ON(engine->id != RCS); |
7225342a MK |
1138 | |
1139 | dev_priv->workarounds.count = 0; | |
33136b06 | 1140 | dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
7225342a | 1141 | |
c033666a | 1142 | if (IS_BROADWELL(dev_priv)) |
0bc40be8 | 1143 | return bdw_init_workarounds(engine); |
7225342a | 1144 | |
c033666a | 1145 | if (IS_CHERRYVIEW(dev_priv)) |
0bc40be8 | 1146 | return chv_init_workarounds(engine); |
00e1e623 | 1147 | |
c033666a | 1148 | if (IS_SKYLAKE(dev_priv)) |
0bc40be8 | 1149 | return skl_init_workarounds(engine); |
cae0437f | 1150 | |
c033666a | 1151 | if (IS_BROXTON(dev_priv)) |
0bc40be8 | 1152 | return bxt_init_workarounds(engine); |
3b106531 | 1153 | |
e5f81d65 MK |
1154 | if (IS_KABYLAKE(dev_priv)) |
1155 | return kbl_init_workarounds(engine); | |
1156 | ||
00e1e623 VS |
1157 | return 0; |
1158 | } | |
1159 | ||
0bc40be8 | 1160 | static int init_render_ring(struct intel_engine_cs *engine) |
8187a2b7 | 1161 | { |
c033666a | 1162 | struct drm_i915_private *dev_priv = engine->i915; |
0bc40be8 | 1163 | int ret = init_ring_common(engine); |
9c33baa6 KZ |
1164 | if (ret) |
1165 | return ret; | |
a69ffdbf | 1166 | |
61a563a2 | 1167 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
ac657f64 | 1168 | if (IS_GEN(dev_priv, 4, 6)) |
6b26c86d | 1169 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1170 | |
1171 | /* We need to disable the AsyncFlip performance optimisations in order | |
1172 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1173 | * programmed to '1' on all products. | |
8693a824 | 1174 | * |
2441f877 | 1175 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv |
1c8c38c5 | 1176 | */ |
ac657f64 | 1177 | if (IS_GEN(dev_priv, 6, 7)) |
1c8c38c5 CW |
1178 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1179 | ||
f05bb0c7 | 1180 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1181 | /* WaEnableFlushTlbInvalidationMode:snb */ |
c033666a | 1182 | if (IS_GEN6(dev_priv)) |
f05bb0c7 | 1183 | I915_WRITE(GFX_MODE, |
aa83e30d | 1184 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1185 | |
01fa0302 | 1186 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
c033666a | 1187 | if (IS_GEN7(dev_priv)) |
1c8c38c5 | 1188 | I915_WRITE(GFX_MODE_GEN7, |
01fa0302 | 1189 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1190 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1191 | |
c033666a | 1192 | if (IS_GEN6(dev_priv)) { |
3a69ddd6 KG |
1193 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1194 | * "If this bit is set, STCunit will have LRA as replacement | |
1195 | * policy. [...] This bit must be reset. LRA replacement | |
1196 | * policy is not supported." | |
1197 | */ | |
1198 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1199 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1200 | } |
1201 | ||
ac657f64 | 1202 | if (IS_GEN(dev_priv, 6, 7)) |
6b26c86d | 1203 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
84f9f938 | 1204 | |
035ea405 VS |
1205 | if (INTEL_INFO(dev_priv)->gen >= 6) |
1206 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
15b9f80e | 1207 | |
0bc40be8 | 1208 | return init_workarounds_ring(engine); |
8187a2b7 ZN |
1209 | } |
1210 | ||
0bc40be8 | 1211 | static void render_ring_cleanup(struct intel_engine_cs *engine) |
c6df541c | 1212 | { |
c033666a | 1213 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 1214 | |
19880c4a | 1215 | i915_vma_unpin_and_release(&dev_priv->semaphore); |
c6df541c CW |
1216 | } |
1217 | ||
ad7bdb2b | 1218 | static int gen8_rcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1219 | { |
ad7bdb2b CW |
1220 | struct intel_ring *ring = req->ring; |
1221 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1222 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1223 | enum intel_engine_id id; |
1224 | int ret, num_rings; | |
3e78998a | 1225 | |
c1bb1145 | 1226 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1227 | ret = intel_ring_begin(req, (num_rings-1) * 8); |
3e78998a BW |
1228 | if (ret) |
1229 | return ret; | |
1230 | ||
c3232b18 | 1231 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1232 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1233 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1234 | continue; | |
1235 | ||
ad7bdb2b CW |
1236 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1237 | intel_ring_emit(ring, | |
b5321f30 CW |
1238 | PIPE_CONTROL_GLOBAL_GTT_IVB | |
1239 | PIPE_CONTROL_QW_WRITE | | |
1240 | PIPE_CONTROL_CS_STALL); | |
ad7bdb2b CW |
1241 | intel_ring_emit(ring, lower_32_bits(gtt_offset)); |
1242 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); | |
1243 | intel_ring_emit(ring, req->fence.seqno); | |
1244 | intel_ring_emit(ring, 0); | |
1245 | intel_ring_emit(ring, | |
b5321f30 CW |
1246 | MI_SEMAPHORE_SIGNAL | |
1247 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1248 | intel_ring_emit(ring, 0); |
3e78998a | 1249 | } |
ad7bdb2b | 1250 | intel_ring_advance(ring); |
3e78998a BW |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
ad7bdb2b | 1255 | static int gen8_xcs_signal(struct drm_i915_gem_request *req) |
3e78998a | 1256 | { |
ad7bdb2b CW |
1257 | struct intel_ring *ring = req->ring; |
1258 | struct drm_i915_private *dev_priv = req->i915; | |
3e78998a | 1259 | struct intel_engine_cs *waiter; |
c3232b18 DG |
1260 | enum intel_engine_id id; |
1261 | int ret, num_rings; | |
3e78998a | 1262 | |
c1bb1145 | 1263 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1264 | ret = intel_ring_begin(req, (num_rings-1) * 6); |
3e78998a BW |
1265 | if (ret) |
1266 | return ret; | |
1267 | ||
c3232b18 | 1268 | for_each_engine_id(waiter, dev_priv, id) { |
ad7bdb2b | 1269 | u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; |
3e78998a BW |
1270 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) |
1271 | continue; | |
1272 | ||
ad7bdb2b | 1273 | intel_ring_emit(ring, |
b5321f30 | 1274 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
ad7bdb2b | 1275 | intel_ring_emit(ring, |
b5321f30 CW |
1276 | lower_32_bits(gtt_offset) | |
1277 | MI_FLUSH_DW_USE_GTT); | |
ad7bdb2b CW |
1278 | intel_ring_emit(ring, upper_32_bits(gtt_offset)); |
1279 | intel_ring_emit(ring, req->fence.seqno); | |
1280 | intel_ring_emit(ring, | |
b5321f30 CW |
1281 | MI_SEMAPHORE_SIGNAL | |
1282 | MI_SEMAPHORE_TARGET(waiter->hw_id)); | |
ad7bdb2b | 1283 | intel_ring_emit(ring, 0); |
3e78998a | 1284 | } |
ad7bdb2b | 1285 | intel_ring_advance(ring); |
3e78998a BW |
1286 | |
1287 | return 0; | |
1288 | } | |
1289 | ||
ad7bdb2b | 1290 | static int gen6_signal(struct drm_i915_gem_request *req) |
1ec14ad3 | 1291 | { |
ad7bdb2b CW |
1292 | struct intel_ring *ring = req->ring; |
1293 | struct drm_i915_private *dev_priv = req->i915; | |
318f89ca | 1294 | struct intel_engine_cs *engine; |
c3232b18 | 1295 | int ret, num_rings; |
78325f2d | 1296 | |
c1bb1145 | 1297 | num_rings = INTEL_INFO(dev_priv)->num_rings; |
ad7bdb2b | 1298 | ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2)); |
024a43e1 BW |
1299 | if (ret) |
1300 | return ret; | |
024a43e1 | 1301 | |
318f89ca TU |
1302 | for_each_engine(engine, dev_priv) { |
1303 | i915_reg_t mbox_reg; | |
1304 | ||
1305 | if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) | |
1306 | continue; | |
f0f59a00 | 1307 | |
318f89ca | 1308 | mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id]; |
f0f59a00 | 1309 | if (i915_mmio_reg_valid(mbox_reg)) { |
ad7bdb2b CW |
1310 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
1311 | intel_ring_emit_reg(ring, mbox_reg); | |
1312 | intel_ring_emit(ring, req->fence.seqno); | |
78325f2d BW |
1313 | } |
1314 | } | |
024a43e1 | 1315 | |
a1444b79 BW |
1316 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1317 | if (num_rings % 2 == 0) | |
ad7bdb2b CW |
1318 | intel_ring_emit(ring, MI_NOOP); |
1319 | intel_ring_advance(ring); | |
a1444b79 | 1320 | |
024a43e1 | 1321 | return 0; |
1ec14ad3 CW |
1322 | } |
1323 | ||
b0411e7d CW |
1324 | static void i9xx_submit_request(struct drm_i915_gem_request *request) |
1325 | { | |
1326 | struct drm_i915_private *dev_priv = request->i915; | |
1327 | ||
1328 | I915_WRITE_TAIL(request->engine, | |
1329 | intel_ring_offset(request->ring, request->tail)); | |
1330 | } | |
1331 | ||
1332 | static int i9xx_emit_request(struct drm_i915_gem_request *req) | |
1ec14ad3 | 1333 | { |
7e37f889 | 1334 | struct intel_ring *ring = req->ring; |
024a43e1 | 1335 | int ret; |
52ed2325 | 1336 | |
9242f974 | 1337 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1338 | if (ret) |
1339 | return ret; | |
1340 | ||
b5321f30 CW |
1341 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1342 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1343 | intel_ring_emit(ring, req->fence.seqno); | |
1344 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
c5efa1ad CW |
1345 | intel_ring_advance(ring); |
1346 | ||
1347 | req->tail = ring->tail; | |
1ec14ad3 | 1348 | |
1ec14ad3 CW |
1349 | return 0; |
1350 | } | |
1351 | ||
b0411e7d | 1352 | /** |
618e4ca7 | 1353 | * gen6_sema_emit_request - Update the semaphore mailbox registers |
b0411e7d CW |
1354 | * |
1355 | * @request - request to write to the ring | |
1356 | * | |
1357 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1358 | * This acts like a signal in the canonical semaphore. | |
1359 | */ | |
618e4ca7 | 1360 | static int gen6_sema_emit_request(struct drm_i915_gem_request *req) |
b0411e7d | 1361 | { |
618e4ca7 | 1362 | int ret; |
b0411e7d | 1363 | |
618e4ca7 CW |
1364 | ret = req->engine->semaphore.signal(req); |
1365 | if (ret) | |
1366 | return ret; | |
b0411e7d CW |
1367 | |
1368 | return i9xx_emit_request(req); | |
1369 | } | |
1370 | ||
ddd66c51 | 1371 | static int gen8_render_emit_request(struct drm_i915_gem_request *req) |
a58c01aa CW |
1372 | { |
1373 | struct intel_engine_cs *engine = req->engine; | |
7e37f889 | 1374 | struct intel_ring *ring = req->ring; |
a58c01aa CW |
1375 | int ret; |
1376 | ||
9242f974 CW |
1377 | if (engine->semaphore.signal) { |
1378 | ret = engine->semaphore.signal(req); | |
1379 | if (ret) | |
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | ret = intel_ring_begin(req, 8); | |
a58c01aa CW |
1384 | if (ret) |
1385 | return ret; | |
1386 | ||
b5321f30 CW |
1387 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1388 | intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1389 | PIPE_CONTROL_CS_STALL | | |
1390 | PIPE_CONTROL_QW_WRITE)); | |
1391 | intel_ring_emit(ring, intel_hws_seqno_address(engine)); | |
1392 | intel_ring_emit(ring, 0); | |
1393 | intel_ring_emit(ring, i915_gem_request_get_seqno(req)); | |
a58c01aa | 1394 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1395 | intel_ring_emit(ring, 0); |
1396 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1397 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1398 | intel_ring_advance(ring); |
c5efa1ad CW |
1399 | |
1400 | req->tail = ring->tail; | |
a58c01aa CW |
1401 | |
1402 | return 0; | |
1403 | } | |
1404 | ||
c8c99b0f BW |
1405 | /** |
1406 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1407 | * | |
1408 | * @waiter - ring that is waiting | |
1409 | * @signaller - ring which has, or will signal | |
1410 | * @seqno - seqno which the waiter will block on | |
1411 | */ | |
5ee426ca BW |
1412 | |
1413 | static int | |
ad7bdb2b CW |
1414 | gen8_ring_sync_to(struct drm_i915_gem_request *req, |
1415 | struct drm_i915_gem_request *signal) | |
5ee426ca | 1416 | { |
ad7bdb2b CW |
1417 | struct intel_ring *ring = req->ring; |
1418 | struct drm_i915_private *dev_priv = req->i915; | |
1419 | u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); | |
6ef48d7f | 1420 | struct i915_hw_ppgtt *ppgtt; |
5ee426ca BW |
1421 | int ret; |
1422 | ||
ad7bdb2b | 1423 | ret = intel_ring_begin(req, 4); |
5ee426ca BW |
1424 | if (ret) |
1425 | return ret; | |
1426 | ||
ad7bdb2b CW |
1427 | intel_ring_emit(ring, |
1428 | MI_SEMAPHORE_WAIT | | |
1429 | MI_SEMAPHORE_GLOBAL_GTT | | |
1430 | MI_SEMAPHORE_SAD_GTE_SDD); | |
1431 | intel_ring_emit(ring, signal->fence.seqno); | |
1432 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1433 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1434 | intel_ring_advance(ring); | |
6ef48d7f CW |
1435 | |
1436 | /* When the !RCS engines idle waiting upon a semaphore, they lose their | |
1437 | * pagetables and we must reload them before executing the batch. | |
1438 | * We do this on the i915_switch_context() following the wait and | |
1439 | * before the dispatch. | |
1440 | */ | |
ad7bdb2b CW |
1441 | ppgtt = req->ctx->ppgtt; |
1442 | if (ppgtt && req->engine->id != RCS) | |
1443 | ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); | |
5ee426ca BW |
1444 | return 0; |
1445 | } | |
1446 | ||
c8c99b0f | 1447 | static int |
ad7bdb2b CW |
1448 | gen6_ring_sync_to(struct drm_i915_gem_request *req, |
1449 | struct drm_i915_gem_request *signal) | |
1ec14ad3 | 1450 | { |
ad7bdb2b | 1451 | struct intel_ring *ring = req->ring; |
c8c99b0f BW |
1452 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1453 | MI_SEMAPHORE_COMPARE | | |
1454 | MI_SEMAPHORE_REGISTER; | |
318f89ca | 1455 | u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id]; |
ebc348b2 | 1456 | int ret; |
1ec14ad3 | 1457 | |
ebc348b2 | 1458 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1459 | |
ad7bdb2b | 1460 | ret = intel_ring_begin(req, 4); |
1ec14ad3 CW |
1461 | if (ret) |
1462 | return ret; | |
1463 | ||
ad7bdb2b | 1464 | intel_ring_emit(ring, dw1 | wait_mbox); |
ddf07be7 CW |
1465 | /* Throughout all of the GEM code, seqno passed implies our current |
1466 | * seqno is >= the last seqno executed. However for hardware the | |
1467 | * comparison is strictly greater than. | |
1468 | */ | |
ad7bdb2b CW |
1469 | intel_ring_emit(ring, signal->fence.seqno - 1); |
1470 | intel_ring_emit(ring, 0); | |
1471 | intel_ring_emit(ring, MI_NOOP); | |
1472 | intel_ring_advance(ring); | |
1ec14ad3 CW |
1473 | |
1474 | return 0; | |
1475 | } | |
1476 | ||
f8973c21 | 1477 | static void |
38a0f2db | 1478 | gen5_seqno_barrier(struct intel_engine_cs *engine) |
c6df541c | 1479 | { |
f8973c21 CW |
1480 | /* MI_STORE are internally buffered by the GPU and not flushed |
1481 | * either by MI_FLUSH or SyncFlush or any other combination of | |
1482 | * MI commands. | |
c6df541c | 1483 | * |
f8973c21 CW |
1484 | * "Only the submission of the store operation is guaranteed. |
1485 | * The write result will be complete (coherent) some time later | |
1486 | * (this is practically a finite period but there is no guaranteed | |
1487 | * latency)." | |
1488 | * | |
1489 | * Empirically, we observe that we need a delay of at least 75us to | |
1490 | * be sure that the seqno write is visible by the CPU. | |
c6df541c | 1491 | */ |
f8973c21 | 1492 | usleep_range(125, 250); |
c6df541c CW |
1493 | } |
1494 | ||
c04e0f3b CW |
1495 | static void |
1496 | gen6_seqno_barrier(struct intel_engine_cs *engine) | |
4cd53c0c | 1497 | { |
c033666a | 1498 | struct drm_i915_private *dev_priv = engine->i915; |
bcbdb6d0 | 1499 | |
4cd53c0c DV |
1500 | /* Workaround to force correct ordering between irq and seqno writes on |
1501 | * ivb (and maybe also on snb) by reading from a CS register (like | |
9b9ed309 CW |
1502 | * ACTHD) before reading the status page. |
1503 | * | |
1504 | * Note that this effectively stalls the read by the time it takes to | |
1505 | * do a memory transaction, which more or less ensures that the write | |
1506 | * from the GPU has sufficient time to invalidate the CPU cacheline. | |
1507 | * Alternatively we could delay the interrupt from the CS ring to give | |
1508 | * the write time to land, but that would incur a delay after every | |
1509 | * batch i.e. much more frequent than a delay when waiting for the | |
1510 | * interrupt (with the same net latency). | |
bcbdb6d0 CW |
1511 | * |
1512 | * Also note that to prevent whole machine hangs on gen7, we have to | |
1513 | * take the spinlock to guard against concurrent cacheline access. | |
9b9ed309 | 1514 | */ |
bcbdb6d0 | 1515 | spin_lock_irq(&dev_priv->uncore.lock); |
c04e0f3b | 1516 | POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); |
bcbdb6d0 | 1517 | spin_unlock_irq(&dev_priv->uncore.lock); |
4cd53c0c DV |
1518 | } |
1519 | ||
31bb59cc CW |
1520 | static void |
1521 | gen5_irq_enable(struct intel_engine_cs *engine) | |
e48d8634 | 1522 | { |
31bb59cc | 1523 | gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1524 | } |
1525 | ||
1526 | static void | |
31bb59cc | 1527 | gen5_irq_disable(struct intel_engine_cs *engine) |
e48d8634 | 1528 | { |
31bb59cc | 1529 | gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); |
e48d8634 DV |
1530 | } |
1531 | ||
31bb59cc CW |
1532 | static void |
1533 | i9xx_irq_enable(struct intel_engine_cs *engine) | |
62fdfeaf | 1534 | { |
c033666a | 1535 | struct drm_i915_private *dev_priv = engine->i915; |
b13c2b96 | 1536 | |
31bb59cc CW |
1537 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1538 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1539 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
62fdfeaf EA |
1540 | } |
1541 | ||
8187a2b7 | 1542 | static void |
31bb59cc | 1543 | i9xx_irq_disable(struct intel_engine_cs *engine) |
62fdfeaf | 1544 | { |
c033666a | 1545 | struct drm_i915_private *dev_priv = engine->i915; |
62fdfeaf | 1546 | |
31bb59cc CW |
1547 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1548 | I915_WRITE(IMR, dev_priv->irq_mask); | |
62fdfeaf EA |
1549 | } |
1550 | ||
31bb59cc CW |
1551 | static void |
1552 | i8xx_irq_enable(struct intel_engine_cs *engine) | |
c2798b19 | 1553 | { |
c033666a | 1554 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1555 | |
31bb59cc CW |
1556 | dev_priv->irq_mask &= ~engine->irq_enable_mask; |
1557 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1558 | POSTING_READ16(RING_IMR(engine->mmio_base)); | |
c2798b19 CW |
1559 | } |
1560 | ||
1561 | static void | |
31bb59cc | 1562 | i8xx_irq_disable(struct intel_engine_cs *engine) |
c2798b19 | 1563 | { |
c033666a | 1564 | struct drm_i915_private *dev_priv = engine->i915; |
c2798b19 | 1565 | |
31bb59cc CW |
1566 | dev_priv->irq_mask |= engine->irq_enable_mask; |
1567 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
c2798b19 CW |
1568 | } |
1569 | ||
b72f3acb | 1570 | static int |
7c9cf4e3 | 1571 | bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
d1b851fc | 1572 | { |
7e37f889 | 1573 | struct intel_ring *ring = req->ring; |
b72f3acb CW |
1574 | int ret; |
1575 | ||
5fb9de1a | 1576 | ret = intel_ring_begin(req, 2); |
b72f3acb CW |
1577 | if (ret) |
1578 | return ret; | |
1579 | ||
b5321f30 CW |
1580 | intel_ring_emit(ring, MI_FLUSH); |
1581 | intel_ring_emit(ring, MI_NOOP); | |
1582 | intel_ring_advance(ring); | |
b72f3acb | 1583 | return 0; |
d1b851fc ZN |
1584 | } |
1585 | ||
31bb59cc CW |
1586 | static void |
1587 | gen6_irq_enable(struct intel_engine_cs *engine) | |
0f46832f | 1588 | { |
c033666a | 1589 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1590 | |
61ff75ac CW |
1591 | I915_WRITE_IMR(engine, |
1592 | ~(engine->irq_enable_mask | | |
1593 | engine->irq_keep_mask)); | |
31bb59cc | 1594 | gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); |
0f46832f CW |
1595 | } |
1596 | ||
1597 | static void | |
31bb59cc | 1598 | gen6_irq_disable(struct intel_engine_cs *engine) |
0f46832f | 1599 | { |
c033666a | 1600 | struct drm_i915_private *dev_priv = engine->i915; |
0f46832f | 1601 | |
61ff75ac | 1602 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
31bb59cc | 1603 | gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); |
d1b851fc ZN |
1604 | } |
1605 | ||
31bb59cc CW |
1606 | static void |
1607 | hsw_vebox_irq_enable(struct intel_engine_cs *engine) | |
a19d2933 | 1608 | { |
c033666a | 1609 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1610 | |
31bb59cc CW |
1611 | I915_WRITE_IMR(engine, ~engine->irq_enable_mask); |
1612 | gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1613 | } |
1614 | ||
1615 | static void | |
31bb59cc | 1616 | hsw_vebox_irq_disable(struct intel_engine_cs *engine) |
a19d2933 | 1617 | { |
c033666a | 1618 | struct drm_i915_private *dev_priv = engine->i915; |
a19d2933 | 1619 | |
31bb59cc CW |
1620 | I915_WRITE_IMR(engine, ~0); |
1621 | gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); | |
a19d2933 BW |
1622 | } |
1623 | ||
31bb59cc CW |
1624 | static void |
1625 | gen8_irq_enable(struct intel_engine_cs *engine) | |
abd58f01 | 1626 | { |
c033666a | 1627 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1628 | |
61ff75ac CW |
1629 | I915_WRITE_IMR(engine, |
1630 | ~(engine->irq_enable_mask | | |
1631 | engine->irq_keep_mask)); | |
31bb59cc | 1632 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); |
abd58f01 BW |
1633 | } |
1634 | ||
1635 | static void | |
31bb59cc | 1636 | gen8_irq_disable(struct intel_engine_cs *engine) |
abd58f01 | 1637 | { |
c033666a | 1638 | struct drm_i915_private *dev_priv = engine->i915; |
abd58f01 | 1639 | |
61ff75ac | 1640 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
abd58f01 BW |
1641 | } |
1642 | ||
d1b851fc | 1643 | static int |
803688ba CW |
1644 | i965_emit_bb_start(struct drm_i915_gem_request *req, |
1645 | u64 offset, u32 length, | |
1646 | unsigned int dispatch_flags) | |
d1b851fc | 1647 | { |
7e37f889 | 1648 | struct intel_ring *ring = req->ring; |
e1f99ce6 | 1649 | int ret; |
78501eac | 1650 | |
5fb9de1a | 1651 | ret = intel_ring_begin(req, 2); |
e1f99ce6 CW |
1652 | if (ret) |
1653 | return ret; | |
1654 | ||
b5321f30 | 1655 | intel_ring_emit(ring, |
65f56876 CW |
1656 | MI_BATCH_BUFFER_START | |
1657 | MI_BATCH_GTT | | |
8e004efc JH |
1658 | (dispatch_flags & I915_DISPATCH_SECURE ? |
1659 | 0 : MI_BATCH_NON_SECURE_I965)); | |
b5321f30 CW |
1660 | intel_ring_emit(ring, offset); |
1661 | intel_ring_advance(ring); | |
78501eac | 1662 | |
d1b851fc ZN |
1663 | return 0; |
1664 | } | |
1665 | ||
b45305fc DV |
1666 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1667 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1668 | #define I830_TLB_ENTRIES (2) |
1669 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1670 | static int |
803688ba CW |
1671 | i830_emit_bb_start(struct drm_i915_gem_request *req, |
1672 | u64 offset, u32 len, | |
1673 | unsigned int dispatch_flags) | |
62fdfeaf | 1674 | { |
7e37f889 | 1675 | struct intel_ring *ring = req->ring; |
bde13ebd | 1676 | u32 cs_offset = i915_ggtt_offset(req->engine->scratch); |
c4e7a414 | 1677 | int ret; |
62fdfeaf | 1678 | |
5fb9de1a | 1679 | ret = intel_ring_begin(req, 6); |
c4d69da1 CW |
1680 | if (ret) |
1681 | return ret; | |
62fdfeaf | 1682 | |
c4d69da1 | 1683 | /* Evict the invalid PTE TLBs */ |
b5321f30 CW |
1684 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); |
1685 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1686 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1687 | intel_ring_emit(ring, cs_offset); | |
1688 | intel_ring_emit(ring, 0xdeadbeef); | |
1689 | intel_ring_emit(ring, MI_NOOP); | |
1690 | intel_ring_advance(ring); | |
b45305fc | 1691 | |
8e004efc | 1692 | if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1693 | if (len > I830_BATCH_LIMIT) |
1694 | return -ENOSPC; | |
1695 | ||
5fb9de1a | 1696 | ret = intel_ring_begin(req, 6 + 2); |
b45305fc DV |
1697 | if (ret) |
1698 | return ret; | |
c4d69da1 CW |
1699 | |
1700 | /* Blit the batch (which has now all relocs applied) to the | |
1701 | * stable batch scratch bo area (so that the CS never | |
1702 | * stumbles over its tlb invalidation bug) ... | |
1703 | */ | |
b5321f30 CW |
1704 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); |
1705 | intel_ring_emit(ring, | |
e2f80391 | 1706 | BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); |
b5321f30 CW |
1707 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
1708 | intel_ring_emit(ring, cs_offset); | |
1709 | intel_ring_emit(ring, 4096); | |
1710 | intel_ring_emit(ring, offset); | |
e2f80391 | 1711 | |
b5321f30 CW |
1712 | intel_ring_emit(ring, MI_FLUSH); |
1713 | intel_ring_emit(ring, MI_NOOP); | |
1714 | intel_ring_advance(ring); | |
b45305fc DV |
1715 | |
1716 | /* ... and execute it. */ | |
c4d69da1 | 1717 | offset = cs_offset; |
b45305fc | 1718 | } |
e1f99ce6 | 1719 | |
9d611c03 | 1720 | ret = intel_ring_begin(req, 2); |
c4d69da1 CW |
1721 | if (ret) |
1722 | return ret; | |
1723 | ||
b5321f30 CW |
1724 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1725 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1726 | 0 : MI_BATCH_NON_SECURE)); | |
1727 | intel_ring_advance(ring); | |
c4d69da1 | 1728 | |
fb3256da DV |
1729 | return 0; |
1730 | } | |
1731 | ||
1732 | static int | |
803688ba CW |
1733 | i915_emit_bb_start(struct drm_i915_gem_request *req, |
1734 | u64 offset, u32 len, | |
1735 | unsigned int dispatch_flags) | |
fb3256da | 1736 | { |
7e37f889 | 1737 | struct intel_ring *ring = req->ring; |
fb3256da DV |
1738 | int ret; |
1739 | ||
5fb9de1a | 1740 | ret = intel_ring_begin(req, 2); |
fb3256da DV |
1741 | if (ret) |
1742 | return ret; | |
1743 | ||
b5321f30 CW |
1744 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
1745 | intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? | |
1746 | 0 : MI_BATCH_NON_SECURE)); | |
1747 | intel_ring_advance(ring); | |
62fdfeaf | 1748 | |
62fdfeaf EA |
1749 | return 0; |
1750 | } | |
1751 | ||
0bc40be8 | 1752 | static void cleanup_phys_status_page(struct intel_engine_cs *engine) |
7d3fdfff | 1753 | { |
c033666a | 1754 | struct drm_i915_private *dev_priv = engine->i915; |
7d3fdfff VS |
1755 | |
1756 | if (!dev_priv->status_page_dmah) | |
1757 | return; | |
1758 | ||
91c8a326 | 1759 | drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); |
0bc40be8 | 1760 | engine->status_page.page_addr = NULL; |
7d3fdfff VS |
1761 | } |
1762 | ||
0bc40be8 | 1763 | static void cleanup_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1764 | { |
57e88531 | 1765 | struct i915_vma *vma; |
62fdfeaf | 1766 | |
57e88531 CW |
1767 | vma = fetch_and_zero(&engine->status_page.vma); |
1768 | if (!vma) | |
62fdfeaf | 1769 | return; |
62fdfeaf | 1770 | |
57e88531 CW |
1771 | i915_vma_unpin(vma); |
1772 | i915_gem_object_unpin_map(vma->obj); | |
1773 | i915_vma_put(vma); | |
62fdfeaf EA |
1774 | } |
1775 | ||
0bc40be8 | 1776 | static int init_status_page(struct intel_engine_cs *engine) |
62fdfeaf | 1777 | { |
57e88531 CW |
1778 | struct drm_i915_gem_object *obj; |
1779 | struct i915_vma *vma; | |
1780 | unsigned int flags; | |
1781 | int ret; | |
e4ffd173 | 1782 | |
57e88531 CW |
1783 | obj = i915_gem_object_create(&engine->i915->drm, 4096); |
1784 | if (IS_ERR(obj)) { | |
1785 | DRM_ERROR("Failed to allocate status page\n"); | |
1786 | return PTR_ERR(obj); | |
1787 | } | |
62fdfeaf | 1788 | |
57e88531 CW |
1789 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1790 | if (ret) | |
1791 | goto err; | |
e3efda49 | 1792 | |
57e88531 CW |
1793 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1794 | if (IS_ERR(vma)) { | |
1795 | ret = PTR_ERR(vma); | |
1796 | goto err; | |
e3efda49 | 1797 | } |
62fdfeaf | 1798 | |
57e88531 CW |
1799 | flags = PIN_GLOBAL; |
1800 | if (!HAS_LLC(engine->i915)) | |
1801 | /* On g33, we cannot place HWS above 256MiB, so | |
1802 | * restrict its pinning to the low mappable arena. | |
1803 | * Though this restriction is not documented for | |
1804 | * gen4, gen5, or byt, they also behave similarly | |
1805 | * and hang if the HWS is placed at the top of the | |
1806 | * GTT. To generalise, it appears that all !llc | |
1807 | * platforms have issues with us placing the HWS | |
1808 | * above the mappable region (even though we never | |
1809 | * actualy map it). | |
1810 | */ | |
1811 | flags |= PIN_MAPPABLE; | |
1812 | ret = i915_vma_pin(vma, 0, 4096, flags); | |
1813 | if (ret) | |
1814 | goto err; | |
62fdfeaf | 1815 | |
57e88531 | 1816 | engine->status_page.vma = vma; |
bde13ebd | 1817 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma); |
57e88531 CW |
1818 | engine->status_page.page_addr = |
1819 | i915_gem_object_pin_map(obj, I915_MAP_WB); | |
62fdfeaf | 1820 | |
bde13ebd CW |
1821 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1822 | engine->name, i915_ggtt_offset(vma)); | |
62fdfeaf | 1823 | return 0; |
57e88531 CW |
1824 | |
1825 | err: | |
1826 | i915_gem_object_put(obj); | |
1827 | return ret; | |
62fdfeaf EA |
1828 | } |
1829 | ||
0bc40be8 | 1830 | static int init_phys_status_page(struct intel_engine_cs *engine) |
6b8294a4 | 1831 | { |
c033666a | 1832 | struct drm_i915_private *dev_priv = engine->i915; |
6b8294a4 | 1833 | |
57e88531 CW |
1834 | dev_priv->status_page_dmah = |
1835 | drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); | |
1836 | if (!dev_priv->status_page_dmah) | |
1837 | return -ENOMEM; | |
6b8294a4 | 1838 | |
0bc40be8 TU |
1839 | engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1840 | memset(engine->status_page.page_addr, 0, PAGE_SIZE); | |
6b8294a4 CW |
1841 | |
1842 | return 0; | |
1843 | } | |
1844 | ||
aad29fbb | 1845 | int intel_ring_pin(struct intel_ring *ring) |
7ba717cf | 1846 | { |
a687a43a | 1847 | /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ |
57e88531 | 1848 | unsigned int flags = PIN_GLOBAL | PIN_OFFSET_BIAS | 4096; |
9d80841e | 1849 | enum i915_map_type map; |
57e88531 | 1850 | struct i915_vma *vma = ring->vma; |
8305216f | 1851 | void *addr; |
7ba717cf TD |
1852 | int ret; |
1853 | ||
57e88531 | 1854 | GEM_BUG_ON(ring->vaddr); |
7ba717cf | 1855 | |
9d80841e CW |
1856 | map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC; |
1857 | ||
1858 | if (vma->obj->stolen) | |
57e88531 | 1859 | flags |= PIN_MAPPABLE; |
def0c5f6 | 1860 | |
57e88531 | 1861 | if (!(vma->flags & I915_VMA_GLOBAL_BIND)) { |
9d80841e | 1862 | if (flags & PIN_MAPPABLE || map == I915_MAP_WC) |
57e88531 CW |
1863 | ret = i915_gem_object_set_to_gtt_domain(vma->obj, true); |
1864 | else | |
1865 | ret = i915_gem_object_set_to_cpu_domain(vma->obj, true); | |
1866 | if (unlikely(ret)) | |
def0c5f6 | 1867 | return ret; |
57e88531 | 1868 | } |
7ba717cf | 1869 | |
57e88531 CW |
1870 | ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags); |
1871 | if (unlikely(ret)) | |
1872 | return ret; | |
def0c5f6 | 1873 | |
9d80841e | 1874 | if (i915_vma_is_map_and_fenceable(vma)) |
57e88531 CW |
1875 | addr = (void __force *)i915_vma_pin_iomap(vma); |
1876 | else | |
9d80841e | 1877 | addr = i915_gem_object_pin_map(vma->obj, map); |
57e88531 CW |
1878 | if (IS_ERR(addr)) |
1879 | goto err; | |
7ba717cf | 1880 | |
32c04f16 | 1881 | ring->vaddr = addr; |
7ba717cf | 1882 | return 0; |
d2cad535 | 1883 | |
57e88531 CW |
1884 | err: |
1885 | i915_vma_unpin(vma); | |
1886 | return PTR_ERR(addr); | |
7ba717cf TD |
1887 | } |
1888 | ||
aad29fbb CW |
1889 | void intel_ring_unpin(struct intel_ring *ring) |
1890 | { | |
1891 | GEM_BUG_ON(!ring->vma); | |
1892 | GEM_BUG_ON(!ring->vaddr); | |
1893 | ||
9d80841e | 1894 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
aad29fbb | 1895 | i915_vma_unpin_iomap(ring->vma); |
57e88531 CW |
1896 | else |
1897 | i915_gem_object_unpin_map(ring->vma->obj); | |
aad29fbb CW |
1898 | ring->vaddr = NULL; |
1899 | ||
57e88531 | 1900 | i915_vma_unpin(ring->vma); |
2919d291 OM |
1901 | } |
1902 | ||
57e88531 CW |
1903 | static struct i915_vma * |
1904 | intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) | |
62fdfeaf | 1905 | { |
05394f39 | 1906 | struct drm_i915_gem_object *obj; |
57e88531 | 1907 | struct i915_vma *vma; |
62fdfeaf | 1908 | |
c58b735f CW |
1909 | obj = i915_gem_object_create_stolen(&dev_priv->drm, size); |
1910 | if (!obj) | |
57e88531 CW |
1911 | obj = i915_gem_object_create(&dev_priv->drm, size); |
1912 | if (IS_ERR(obj)) | |
1913 | return ERR_CAST(obj); | |
8187a2b7 | 1914 | |
24f3a8cf AG |
1915 | /* mark ring buffers as read-only from GPU side by default */ |
1916 | obj->gt_ro = 1; | |
1917 | ||
57e88531 CW |
1918 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
1919 | if (IS_ERR(vma)) | |
1920 | goto err; | |
1921 | ||
1922 | return vma; | |
e3efda49 | 1923 | |
57e88531 CW |
1924 | err: |
1925 | i915_gem_object_put(obj); | |
1926 | return vma; | |
e3efda49 CW |
1927 | } |
1928 | ||
7e37f889 CW |
1929 | struct intel_ring * |
1930 | intel_engine_create_ring(struct intel_engine_cs *engine, int size) | |
01101fa7 | 1931 | { |
7e37f889 | 1932 | struct intel_ring *ring; |
57e88531 | 1933 | struct i915_vma *vma; |
01101fa7 | 1934 | |
8f942018 | 1935 | GEM_BUG_ON(!is_power_of_2(size)); |
62ae14b1 | 1936 | GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES); |
8f942018 | 1937 | |
01101fa7 | 1938 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
57e88531 | 1939 | if (!ring) |
01101fa7 CW |
1940 | return ERR_PTR(-ENOMEM); |
1941 | ||
4a570db5 | 1942 | ring->engine = engine; |
01101fa7 | 1943 | |
675d9ad7 CW |
1944 | INIT_LIST_HEAD(&ring->request_list); |
1945 | ||
01101fa7 CW |
1946 | ring->size = size; |
1947 | /* Workaround an erratum on the i830 which causes a hang if | |
1948 | * the TAIL pointer points to within the last 2 cachelines | |
1949 | * of the buffer. | |
1950 | */ | |
1951 | ring->effective_size = size; | |
c033666a | 1952 | if (IS_I830(engine->i915) || IS_845G(engine->i915)) |
01101fa7 CW |
1953 | ring->effective_size -= 2 * CACHELINE_BYTES; |
1954 | ||
1955 | ring->last_retired_head = -1; | |
1956 | intel_ring_update_space(ring); | |
1957 | ||
57e88531 CW |
1958 | vma = intel_ring_create_vma(engine->i915, size); |
1959 | if (IS_ERR(vma)) { | |
01101fa7 | 1960 | kfree(ring); |
57e88531 | 1961 | return ERR_CAST(vma); |
01101fa7 | 1962 | } |
57e88531 | 1963 | ring->vma = vma; |
01101fa7 CW |
1964 | |
1965 | return ring; | |
1966 | } | |
1967 | ||
1968 | void | |
7e37f889 | 1969 | intel_ring_free(struct intel_ring *ring) |
01101fa7 | 1970 | { |
57e88531 | 1971 | i915_vma_put(ring->vma); |
01101fa7 CW |
1972 | kfree(ring); |
1973 | } | |
1974 | ||
0cb26a8e CW |
1975 | static int intel_ring_context_pin(struct i915_gem_context *ctx, |
1976 | struct intel_engine_cs *engine) | |
1977 | { | |
1978 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1979 | int ret; | |
1980 | ||
91c8a326 | 1981 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
1982 | |
1983 | if (ce->pin_count++) | |
1984 | return 0; | |
1985 | ||
1986 | if (ce->state) { | |
7abc98fa CW |
1987 | ret = i915_gem_object_set_to_gtt_domain(ce->state->obj, false); |
1988 | if (ret) | |
1989 | goto error; | |
1990 | ||
bf3783e5 CW |
1991 | ret = i915_vma_pin(ce->state, 0, ctx->ggtt_alignment, |
1992 | PIN_GLOBAL | PIN_HIGH); | |
0cb26a8e CW |
1993 | if (ret) |
1994 | goto error; | |
1995 | } | |
1996 | ||
c7c3c07d CW |
1997 | /* The kernel context is only used as a placeholder for flushing the |
1998 | * active context. It is never used for submitting user rendering and | |
1999 | * as such never requires the golden render context, and so we can skip | |
2000 | * emitting it when we switch to the kernel context. This is required | |
2001 | * as during eviction we cannot allocate and pin the renderstate in | |
2002 | * order to initialise the context. | |
2003 | */ | |
2004 | if (ctx == ctx->i915->kernel_context) | |
2005 | ce->initialised = true; | |
2006 | ||
9a6feaf0 | 2007 | i915_gem_context_get(ctx); |
0cb26a8e CW |
2008 | return 0; |
2009 | ||
2010 | error: | |
2011 | ce->pin_count = 0; | |
2012 | return ret; | |
2013 | } | |
2014 | ||
2015 | static void intel_ring_context_unpin(struct i915_gem_context *ctx, | |
2016 | struct intel_engine_cs *engine) | |
2017 | { | |
2018 | struct intel_context *ce = &ctx->engine[engine->id]; | |
2019 | ||
91c8a326 | 2020 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
0cb26a8e CW |
2021 | |
2022 | if (--ce->pin_count) | |
2023 | return; | |
2024 | ||
2025 | if (ce->state) | |
bf3783e5 | 2026 | i915_vma_unpin(ce->state); |
0cb26a8e | 2027 | |
9a6feaf0 | 2028 | i915_gem_context_put(ctx); |
0cb26a8e CW |
2029 | } |
2030 | ||
acd27845 | 2031 | static int intel_init_ring_buffer(struct intel_engine_cs *engine) |
e3efda49 | 2032 | { |
acd27845 | 2033 | struct drm_i915_private *dev_priv = engine->i915; |
32c04f16 | 2034 | struct intel_ring *ring; |
e3efda49 CW |
2035 | int ret; |
2036 | ||
0bc40be8 | 2037 | WARN_ON(engine->buffer); |
bfc882b4 | 2038 | |
019bf277 TU |
2039 | intel_engine_setup_common(engine); |
2040 | ||
0bc40be8 TU |
2041 | memset(engine->semaphore.sync_seqno, 0, |
2042 | sizeof(engine->semaphore.sync_seqno)); | |
e3efda49 | 2043 | |
019bf277 | 2044 | ret = intel_engine_init_common(engine); |
688e6c72 CW |
2045 | if (ret) |
2046 | goto error; | |
e3efda49 | 2047 | |
0cb26a8e CW |
2048 | /* We may need to do things with the shrinker which |
2049 | * require us to immediately switch back to the default | |
2050 | * context. This can cause a problem as pinning the | |
2051 | * default context also requires GTT space which may not | |
2052 | * be available. To avoid this we always pin the default | |
2053 | * context. | |
2054 | */ | |
2055 | ret = intel_ring_context_pin(dev_priv->kernel_context, engine); | |
2056 | if (ret) | |
2057 | goto error; | |
2058 | ||
32c04f16 CW |
2059 | ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); |
2060 | if (IS_ERR(ring)) { | |
2061 | ret = PTR_ERR(ring); | |
b0366a54 DG |
2062 | goto error; |
2063 | } | |
01101fa7 | 2064 | |
3177659a CS |
2065 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
2066 | WARN_ON(engine->id != RCS); | |
2067 | ret = init_phys_status_page(engine); | |
e3efda49 | 2068 | if (ret) |
8ee14975 | 2069 | goto error; |
e3efda49 | 2070 | } else { |
3177659a | 2071 | ret = init_status_page(engine); |
e3efda49 | 2072 | if (ret) |
8ee14975 | 2073 | goto error; |
e3efda49 CW |
2074 | } |
2075 | ||
aad29fbb | 2076 | ret = intel_ring_pin(ring); |
bfc882b4 | 2077 | if (ret) { |
57e88531 | 2078 | intel_ring_free(ring); |
bfc882b4 | 2079 | goto error; |
e3efda49 | 2080 | } |
57e88531 | 2081 | engine->buffer = ring; |
62fdfeaf | 2082 | |
8ee14975 | 2083 | return 0; |
351e3db2 | 2084 | |
8ee14975 | 2085 | error: |
7e37f889 | 2086 | intel_engine_cleanup(engine); |
8ee14975 | 2087 | return ret; |
62fdfeaf EA |
2088 | } |
2089 | ||
7e37f889 | 2090 | void intel_engine_cleanup(struct intel_engine_cs *engine) |
62fdfeaf | 2091 | { |
6402c330 | 2092 | struct drm_i915_private *dev_priv; |
33626e6a | 2093 | |
117897f4 | 2094 | if (!intel_engine_initialized(engine)) |
62fdfeaf EA |
2095 | return; |
2096 | ||
c033666a | 2097 | dev_priv = engine->i915; |
6402c330 | 2098 | |
0bc40be8 | 2099 | if (engine->buffer) { |
21a2c58a CW |
2100 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
2101 | (I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
33626e6a | 2102 | |
aad29fbb | 2103 | intel_ring_unpin(engine->buffer); |
7e37f889 | 2104 | intel_ring_free(engine->buffer); |
0bc40be8 | 2105 | engine->buffer = NULL; |
b0366a54 | 2106 | } |
78501eac | 2107 | |
0bc40be8 TU |
2108 | if (engine->cleanup) |
2109 | engine->cleanup(engine); | |
8d19215b | 2110 | |
3177659a | 2111 | if (HWS_NEEDS_PHYSICAL(dev_priv)) { |
0bc40be8 TU |
2112 | WARN_ON(engine->id != RCS); |
2113 | cleanup_phys_status_page(engine); | |
3177659a CS |
2114 | } else { |
2115 | cleanup_status_page(engine); | |
7d3fdfff | 2116 | } |
44e895a8 | 2117 | |
96a945aa | 2118 | intel_engine_cleanup_common(engine); |
0cb26a8e CW |
2119 | |
2120 | intel_ring_context_unpin(dev_priv->kernel_context, engine); | |
2121 | ||
c033666a | 2122 | engine->i915 = NULL; |
62fdfeaf EA |
2123 | } |
2124 | ||
821ed7df CW |
2125 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv) |
2126 | { | |
2127 | struct intel_engine_cs *engine; | |
2128 | ||
2129 | for_each_engine(engine, dev_priv) { | |
2130 | engine->buffer->head = engine->buffer->tail; | |
2131 | engine->buffer->last_retired_head = -1; | |
2132 | } | |
2133 | } | |
2134 | ||
6689cb2b | 2135 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
9d773091 | 2136 | { |
6310346e CW |
2137 | int ret; |
2138 | ||
2139 | /* Flush enough space to reduce the likelihood of waiting after | |
2140 | * we start building the request - in which case we will just | |
2141 | * have to repeat work. | |
2142 | */ | |
a0442461 | 2143 | request->reserved_space += LEGACY_REQUEST_SIZE; |
6310346e | 2144 | |
1dae2dfb | 2145 | request->ring = request->engine->buffer; |
6310346e CW |
2146 | |
2147 | ret = intel_ring_begin(request, 0); | |
2148 | if (ret) | |
2149 | return ret; | |
2150 | ||
a0442461 | 2151 | request->reserved_space -= LEGACY_REQUEST_SIZE; |
6310346e | 2152 | return 0; |
9d773091 CW |
2153 | } |
2154 | ||
987046ad CW |
2155 | static int wait_for_space(struct drm_i915_gem_request *req, int bytes) |
2156 | { | |
7e37f889 | 2157 | struct intel_ring *ring = req->ring; |
987046ad | 2158 | struct drm_i915_gem_request *target; |
7da844c5 | 2159 | int ret; |
987046ad | 2160 | |
1dae2dfb CW |
2161 | intel_ring_update_space(ring); |
2162 | if (ring->space >= bytes) | |
987046ad CW |
2163 | return 0; |
2164 | ||
2165 | /* | |
2166 | * Space is reserved in the ringbuffer for finalising the request, | |
2167 | * as that cannot be allowed to fail. During request finalisation, | |
2168 | * reserved_space is set to 0 to stop the overallocation and the | |
2169 | * assumption is that then we never need to wait (which has the | |
2170 | * risk of failing with EINTR). | |
2171 | * | |
2172 | * See also i915_gem_request_alloc() and i915_add_request(). | |
2173 | */ | |
0251a963 | 2174 | GEM_BUG_ON(!req->reserved_space); |
987046ad | 2175 | |
675d9ad7 | 2176 | list_for_each_entry(target, &ring->request_list, ring_link) { |
987046ad CW |
2177 | unsigned space; |
2178 | ||
987046ad | 2179 | /* Would completion of this request free enough space? */ |
1dae2dfb CW |
2180 | space = __intel_ring_space(target->postfix, ring->tail, |
2181 | ring->size); | |
987046ad CW |
2182 | if (space >= bytes) |
2183 | break; | |
79bbcc29 | 2184 | } |
29b1b415 | 2185 | |
675d9ad7 | 2186 | if (WARN_ON(&target->ring_link == &ring->request_list)) |
987046ad CW |
2187 | return -ENOSPC; |
2188 | ||
22dd3bb9 CW |
2189 | ret = i915_wait_request(target, |
2190 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, | |
ea746f36 | 2191 | NULL, NO_WAITBOOST); |
7da844c5 CW |
2192 | if (ret) |
2193 | return ret; | |
2194 | ||
7da844c5 CW |
2195 | i915_gem_request_retire_upto(target); |
2196 | ||
2197 | intel_ring_update_space(ring); | |
2198 | GEM_BUG_ON(ring->space < bytes); | |
2199 | return 0; | |
29b1b415 JH |
2200 | } |
2201 | ||
987046ad | 2202 | int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
cbcc80df | 2203 | { |
7e37f889 | 2204 | struct intel_ring *ring = req->ring; |
1dae2dfb CW |
2205 | int remain_actual = ring->size - ring->tail; |
2206 | int remain_usable = ring->effective_size - ring->tail; | |
987046ad CW |
2207 | int bytes = num_dwords * sizeof(u32); |
2208 | int total_bytes, wait_bytes; | |
79bbcc29 | 2209 | bool need_wrap = false; |
29b1b415 | 2210 | |
0251a963 | 2211 | total_bytes = bytes + req->reserved_space; |
29b1b415 | 2212 | |
79bbcc29 JH |
2213 | if (unlikely(bytes > remain_usable)) { |
2214 | /* | |
2215 | * Not enough space for the basic request. So need to flush | |
2216 | * out the remainder and then wait for base + reserved. | |
2217 | */ | |
2218 | wait_bytes = remain_actual + total_bytes; | |
2219 | need_wrap = true; | |
987046ad CW |
2220 | } else if (unlikely(total_bytes > remain_usable)) { |
2221 | /* | |
2222 | * The base request will fit but the reserved space | |
2223 | * falls off the end. So we don't need an immediate wrap | |
2224 | * and only need to effectively wait for the reserved | |
2225 | * size space from the start of ringbuffer. | |
2226 | */ | |
0251a963 | 2227 | wait_bytes = remain_actual + req->reserved_space; |
79bbcc29 | 2228 | } else { |
987046ad CW |
2229 | /* No wrapping required, just waiting. */ |
2230 | wait_bytes = total_bytes; | |
cbcc80df MK |
2231 | } |
2232 | ||
1dae2dfb | 2233 | if (wait_bytes > ring->space) { |
987046ad | 2234 | int ret = wait_for_space(req, wait_bytes); |
cbcc80df MK |
2235 | if (unlikely(ret)) |
2236 | return ret; | |
2237 | } | |
2238 | ||
987046ad | 2239 | if (unlikely(need_wrap)) { |
1dae2dfb CW |
2240 | GEM_BUG_ON(remain_actual > ring->space); |
2241 | GEM_BUG_ON(ring->tail + remain_actual > ring->size); | |
78501eac | 2242 | |
987046ad | 2243 | /* Fill the tail with MI_NOOP */ |
1dae2dfb CW |
2244 | memset(ring->vaddr + ring->tail, 0, remain_actual); |
2245 | ring->tail = 0; | |
2246 | ring->space -= remain_actual; | |
987046ad | 2247 | } |
304d695c | 2248 | |
1dae2dfb CW |
2249 | ring->space -= bytes; |
2250 | GEM_BUG_ON(ring->space < 0); | |
304d695c | 2251 | return 0; |
8187a2b7 | 2252 | } |
78501eac | 2253 | |
753b1ad4 | 2254 | /* Align the ring tail to a cacheline boundary */ |
bba09b12 | 2255 | int intel_ring_cacheline_align(struct drm_i915_gem_request *req) |
753b1ad4 | 2256 | { |
7e37f889 | 2257 | struct intel_ring *ring = req->ring; |
b5321f30 CW |
2258 | int num_dwords = |
2259 | (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); | |
753b1ad4 VS |
2260 | int ret; |
2261 | ||
2262 | if (num_dwords == 0) | |
2263 | return 0; | |
2264 | ||
18393f63 | 2265 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
5fb9de1a | 2266 | ret = intel_ring_begin(req, num_dwords); |
753b1ad4 VS |
2267 | if (ret) |
2268 | return ret; | |
2269 | ||
2270 | while (num_dwords--) | |
b5321f30 | 2271 | intel_ring_emit(ring, MI_NOOP); |
753b1ad4 | 2272 | |
b5321f30 | 2273 | intel_ring_advance(ring); |
753b1ad4 VS |
2274 | |
2275 | return 0; | |
2276 | } | |
2277 | ||
c5efa1ad | 2278 | static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) |
881f47b6 | 2279 | { |
c5efa1ad | 2280 | struct drm_i915_private *dev_priv = request->i915; |
881f47b6 | 2281 | |
76f8421f CW |
2282 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2283 | ||
881f47b6 | 2284 | /* Every tail move must follow the sequence below */ |
12f55818 CW |
2285 | |
2286 | /* Disable notification that the ring is IDLE. The GT | |
2287 | * will then assume that it is busy and bring it out of rc6. | |
2288 | */ | |
76f8421f CW |
2289 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2290 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
12f55818 CW |
2291 | |
2292 | /* Clear the context id. Here be magic! */ | |
76f8421f | 2293 | I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); |
0206e353 | 2294 | |
12f55818 | 2295 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
76f8421f CW |
2296 | if (intel_wait_for_register_fw(dev_priv, |
2297 | GEN6_BSD_SLEEP_PSMI_CONTROL, | |
2298 | GEN6_BSD_SLEEP_INDICATOR, | |
2299 | 0, | |
2300 | 50)) | |
12f55818 | 2301 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); |
0206e353 | 2302 | |
12f55818 | 2303 | /* Now that the ring is fully powered up, update the tail */ |
b0411e7d | 2304 | i9xx_submit_request(request); |
12f55818 CW |
2305 | |
2306 | /* Let the ring send IDLE messages to the GT again, | |
2307 | * and so let it sleep to conserve power when idle. | |
2308 | */ | |
76f8421f CW |
2309 | I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, |
2310 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); | |
2311 | ||
2312 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
881f47b6 XH |
2313 | } |
2314 | ||
7c9cf4e3 | 2315 | static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
881f47b6 | 2316 | { |
7e37f889 | 2317 | struct intel_ring *ring = req->ring; |
71a77e07 | 2318 | uint32_t cmd; |
b72f3acb CW |
2319 | int ret; |
2320 | ||
5fb9de1a | 2321 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2322 | if (ret) |
2323 | return ret; | |
2324 | ||
71a77e07 | 2325 | cmd = MI_FLUSH_DW; |
c033666a | 2326 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2327 | cmd += 1; |
f0a1fb10 CW |
2328 | |
2329 | /* We always require a command barrier so that subsequent | |
2330 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2331 | * wrt the contents of the write cache being flushed to memory | |
2332 | * (and thus being coherent from the CPU). | |
2333 | */ | |
2334 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2335 | ||
9a289771 JB |
2336 | /* |
2337 | * Bspec vol 1c.5 - video engine command streamer: | |
2338 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2339 | * operation is complete. This bit is only valid when the | |
2340 | * Post-Sync Operation field is a value of 1h or 3h." | |
2341 | */ | |
7c9cf4e3 | 2342 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 CW |
2343 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
2344 | ||
b5321f30 CW |
2345 | intel_ring_emit(ring, cmd); |
2346 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); | |
c033666a | 2347 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2348 | intel_ring_emit(ring, 0); /* upper addr */ |
2349 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2350 | } else { |
b5321f30 CW |
2351 | intel_ring_emit(ring, 0); |
2352 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2353 | } |
b5321f30 | 2354 | intel_ring_advance(ring); |
b72f3acb | 2355 | return 0; |
881f47b6 XH |
2356 | } |
2357 | ||
1c7a0623 | 2358 | static int |
803688ba CW |
2359 | gen8_emit_bb_start(struct drm_i915_gem_request *req, |
2360 | u64 offset, u32 len, | |
2361 | unsigned int dispatch_flags) | |
1c7a0623 | 2362 | { |
7e37f889 | 2363 | struct intel_ring *ring = req->ring; |
b5321f30 | 2364 | bool ppgtt = USES_PPGTT(req->i915) && |
8e004efc | 2365 | !(dispatch_flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2366 | int ret; |
2367 | ||
5fb9de1a | 2368 | ret = intel_ring_begin(req, 4); |
1c7a0623 BW |
2369 | if (ret) |
2370 | return ret; | |
2371 | ||
2372 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 | 2373 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | |
919032ec AJ |
2374 | (dispatch_flags & I915_DISPATCH_RS ? |
2375 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
b5321f30 CW |
2376 | intel_ring_emit(ring, lower_32_bits(offset)); |
2377 | intel_ring_emit(ring, upper_32_bits(offset)); | |
2378 | intel_ring_emit(ring, MI_NOOP); | |
2379 | intel_ring_advance(ring); | |
1c7a0623 BW |
2380 | |
2381 | return 0; | |
2382 | } | |
2383 | ||
d7d4eedd | 2384 | static int |
803688ba CW |
2385 | hsw_emit_bb_start(struct drm_i915_gem_request *req, |
2386 | u64 offset, u32 len, | |
2387 | unsigned int dispatch_flags) | |
d7d4eedd | 2388 | { |
7e37f889 | 2389 | struct intel_ring *ring = req->ring; |
d7d4eedd CW |
2390 | int ret; |
2391 | ||
5fb9de1a | 2392 | ret = intel_ring_begin(req, 2); |
d7d4eedd CW |
2393 | if (ret) |
2394 | return ret; | |
2395 | ||
b5321f30 | 2396 | intel_ring_emit(ring, |
77072258 | 2397 | MI_BATCH_BUFFER_START | |
8e004efc | 2398 | (dispatch_flags & I915_DISPATCH_SECURE ? |
919032ec AJ |
2399 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | |
2400 | (dispatch_flags & I915_DISPATCH_RS ? | |
2401 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
d7d4eedd | 2402 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2403 | intel_ring_emit(ring, offset); |
2404 | intel_ring_advance(ring); | |
d7d4eedd CW |
2405 | |
2406 | return 0; | |
2407 | } | |
2408 | ||
881f47b6 | 2409 | static int |
803688ba CW |
2410 | gen6_emit_bb_start(struct drm_i915_gem_request *req, |
2411 | u64 offset, u32 len, | |
2412 | unsigned int dispatch_flags) | |
881f47b6 | 2413 | { |
7e37f889 | 2414 | struct intel_ring *ring = req->ring; |
0206e353 | 2415 | int ret; |
ab6f8e32 | 2416 | |
5fb9de1a | 2417 | ret = intel_ring_begin(req, 2); |
0206e353 AJ |
2418 | if (ret) |
2419 | return ret; | |
e1f99ce6 | 2420 | |
b5321f30 | 2421 | intel_ring_emit(ring, |
d7d4eedd | 2422 | MI_BATCH_BUFFER_START | |
8e004efc JH |
2423 | (dispatch_flags & I915_DISPATCH_SECURE ? |
2424 | 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 | 2425 | /* bit0-7 is the length on GEN6+ */ |
b5321f30 CW |
2426 | intel_ring_emit(ring, offset); |
2427 | intel_ring_advance(ring); | |
ab6f8e32 | 2428 | |
0206e353 | 2429 | return 0; |
881f47b6 XH |
2430 | } |
2431 | ||
549f7365 CW |
2432 | /* Blitter support (SandyBridge+) */ |
2433 | ||
7c9cf4e3 | 2434 | static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) |
8d19215b | 2435 | { |
7e37f889 | 2436 | struct intel_ring *ring = req->ring; |
71a77e07 | 2437 | uint32_t cmd; |
b72f3acb CW |
2438 | int ret; |
2439 | ||
5fb9de1a | 2440 | ret = intel_ring_begin(req, 4); |
b72f3acb CW |
2441 | if (ret) |
2442 | return ret; | |
2443 | ||
71a77e07 | 2444 | cmd = MI_FLUSH_DW; |
c033666a | 2445 | if (INTEL_GEN(req->i915) >= 8) |
075b3bba | 2446 | cmd += 1; |
f0a1fb10 CW |
2447 | |
2448 | /* We always require a command barrier so that subsequent | |
2449 | * commands, such as breadcrumb interrupts, are strictly ordered | |
2450 | * wrt the contents of the write cache being flushed to memory | |
2451 | * (and thus being coherent from the CPU). | |
2452 | */ | |
2453 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
2454 | ||
9a289771 JB |
2455 | /* |
2456 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2457 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2458 | * operation is complete. This bit is only valid when the | |
2459 | * Post-Sync Operation field is a value of 1h or 3h." | |
2460 | */ | |
7c9cf4e3 | 2461 | if (mode & EMIT_INVALIDATE) |
f0a1fb10 | 2462 | cmd |= MI_INVALIDATE_TLB; |
b5321f30 CW |
2463 | intel_ring_emit(ring, cmd); |
2464 | intel_ring_emit(ring, | |
e2f80391 | 2465 | I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
c033666a | 2466 | if (INTEL_GEN(req->i915) >= 8) { |
b5321f30 CW |
2467 | intel_ring_emit(ring, 0); /* upper addr */ |
2468 | intel_ring_emit(ring, 0); /* value */ | |
075b3bba | 2469 | } else { |
b5321f30 CW |
2470 | intel_ring_emit(ring, 0); |
2471 | intel_ring_emit(ring, MI_NOOP); | |
075b3bba | 2472 | } |
b5321f30 | 2473 | intel_ring_advance(ring); |
fd3da6c9 | 2474 | |
b72f3acb | 2475 | return 0; |
8d19215b ZN |
2476 | } |
2477 | ||
d9a64610 TU |
2478 | static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, |
2479 | struct intel_engine_cs *engine) | |
2480 | { | |
db3d4019 | 2481 | struct drm_i915_gem_object *obj; |
1b9e6650 | 2482 | int ret, i; |
db3d4019 | 2483 | |
39df9190 | 2484 | if (!i915.semaphores) |
db3d4019 TU |
2485 | return; |
2486 | ||
51d545d0 CW |
2487 | if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) { |
2488 | struct i915_vma *vma; | |
2489 | ||
91c8a326 | 2490 | obj = i915_gem_object_create(&dev_priv->drm, 4096); |
51d545d0 CW |
2491 | if (IS_ERR(obj)) |
2492 | goto err; | |
db3d4019 | 2493 | |
51d545d0 CW |
2494 | vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL); |
2495 | if (IS_ERR(vma)) | |
2496 | goto err_obj; | |
2497 | ||
2498 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
2499 | if (ret) | |
2500 | goto err_obj; | |
2501 | ||
2502 | ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH); | |
2503 | if (ret) | |
2504 | goto err_obj; | |
2505 | ||
2506 | dev_priv->semaphore = vma; | |
2507 | } | |
d9a64610 TU |
2508 | |
2509 | if (INTEL_GEN(dev_priv) >= 8) { | |
bde13ebd | 2510 | u32 offset = i915_ggtt_offset(dev_priv->semaphore); |
1b9e6650 | 2511 | |
ad7bdb2b | 2512 | engine->semaphore.sync_to = gen8_ring_sync_to; |
d9a64610 | 2513 | engine->semaphore.signal = gen8_xcs_signal; |
1b9e6650 TU |
2514 | |
2515 | for (i = 0; i < I915_NUM_ENGINES; i++) { | |
bde13ebd | 2516 | u32 ring_offset; |
1b9e6650 TU |
2517 | |
2518 | if (i != engine->id) | |
2519 | ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); | |
2520 | else | |
2521 | ring_offset = MI_SEMAPHORE_SYNC_INVALID; | |
2522 | ||
2523 | engine->semaphore.signal_ggtt[i] = ring_offset; | |
2524 | } | |
d9a64610 | 2525 | } else if (INTEL_GEN(dev_priv) >= 6) { |
ad7bdb2b | 2526 | engine->semaphore.sync_to = gen6_ring_sync_to; |
d9a64610 | 2527 | engine->semaphore.signal = gen6_signal; |
4b8e38a9 TU |
2528 | |
2529 | /* | |
2530 | * The current semaphore is only applied on pre-gen8 | |
2531 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2532 | * platform. So the semaphore between RCS and VCS2 is | |
2533 | * initialized as INVALID. Gen8 will initialize the | |
2534 | * sema between VCS2 and RCS later. | |
2535 | */ | |
318f89ca | 2536 | for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) { |
4b8e38a9 TU |
2537 | static const struct { |
2538 | u32 wait_mbox; | |
2539 | i915_reg_t mbox_reg; | |
318f89ca TU |
2540 | } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = { |
2541 | [RCS_HW] = { | |
2542 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, | |
2543 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, | |
2544 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, | |
4b8e38a9 | 2545 | }, |
318f89ca TU |
2546 | [VCS_HW] = { |
2547 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, | |
2548 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, | |
2549 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, | |
4b8e38a9 | 2550 | }, |
318f89ca TU |
2551 | [BCS_HW] = { |
2552 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, | |
2553 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, | |
2554 | [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, | |
4b8e38a9 | 2555 | }, |
318f89ca TU |
2556 | [VECS_HW] = { |
2557 | [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, | |
2558 | [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, | |
2559 | [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, | |
4b8e38a9 TU |
2560 | }, |
2561 | }; | |
2562 | u32 wait_mbox; | |
2563 | i915_reg_t mbox_reg; | |
2564 | ||
318f89ca | 2565 | if (i == engine->hw_id) { |
4b8e38a9 TU |
2566 | wait_mbox = MI_SEMAPHORE_SYNC_INVALID; |
2567 | mbox_reg = GEN6_NOSYNC; | |
2568 | } else { | |
318f89ca TU |
2569 | wait_mbox = sem_data[engine->hw_id][i].wait_mbox; |
2570 | mbox_reg = sem_data[engine->hw_id][i].mbox_reg; | |
4b8e38a9 TU |
2571 | } |
2572 | ||
2573 | engine->semaphore.mbox.wait[i] = wait_mbox; | |
2574 | engine->semaphore.mbox.signal[i] = mbox_reg; | |
2575 | } | |
d9a64610 | 2576 | } |
51d545d0 CW |
2577 | |
2578 | return; | |
2579 | ||
2580 | err_obj: | |
2581 | i915_gem_object_put(obj); | |
2582 | err: | |
2583 | DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n"); | |
2584 | i915.semaphores = 0; | |
d9a64610 TU |
2585 | } |
2586 | ||
ed003078 CW |
2587 | static void intel_ring_init_irq(struct drm_i915_private *dev_priv, |
2588 | struct intel_engine_cs *engine) | |
2589 | { | |
c78d6061 TU |
2590 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; |
2591 | ||
ed003078 | 2592 | if (INTEL_GEN(dev_priv) >= 8) { |
31bb59cc CW |
2593 | engine->irq_enable = gen8_irq_enable; |
2594 | engine->irq_disable = gen8_irq_disable; | |
ed003078 CW |
2595 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2596 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
31bb59cc CW |
2597 | engine->irq_enable = gen6_irq_enable; |
2598 | engine->irq_disable = gen6_irq_disable; | |
ed003078 CW |
2599 | engine->irq_seqno_barrier = gen6_seqno_barrier; |
2600 | } else if (INTEL_GEN(dev_priv) >= 5) { | |
31bb59cc CW |
2601 | engine->irq_enable = gen5_irq_enable; |
2602 | engine->irq_disable = gen5_irq_disable; | |
f8973c21 | 2603 | engine->irq_seqno_barrier = gen5_seqno_barrier; |
ed003078 | 2604 | } else if (INTEL_GEN(dev_priv) >= 3) { |
31bb59cc CW |
2605 | engine->irq_enable = i9xx_irq_enable; |
2606 | engine->irq_disable = i9xx_irq_disable; | |
ed003078 | 2607 | } else { |
31bb59cc CW |
2608 | engine->irq_enable = i8xx_irq_enable; |
2609 | engine->irq_disable = i8xx_irq_disable; | |
ed003078 CW |
2610 | } |
2611 | } | |
2612 | ||
06a2fe22 TU |
2613 | static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, |
2614 | struct intel_engine_cs *engine) | |
2615 | { | |
618e4ca7 CW |
2616 | intel_ring_init_irq(dev_priv, engine); |
2617 | intel_ring_init_semaphores(dev_priv, engine); | |
2618 | ||
1d8a1337 | 2619 | engine->init_hw = init_ring_common; |
821ed7df | 2620 | engine->reset_hw = reset_ring_common; |
7445a2a4 | 2621 | |
ddd66c51 | 2622 | engine->emit_request = i9xx_emit_request; |
618e4ca7 CW |
2623 | if (i915.semaphores) |
2624 | engine->emit_request = gen6_sema_emit_request; | |
ddd66c51 | 2625 | engine->submit_request = i9xx_submit_request; |
6f7bef75 CW |
2626 | |
2627 | if (INTEL_GEN(dev_priv) >= 8) | |
803688ba | 2628 | engine->emit_bb_start = gen8_emit_bb_start; |
6f7bef75 | 2629 | else if (INTEL_GEN(dev_priv) >= 6) |
803688ba | 2630 | engine->emit_bb_start = gen6_emit_bb_start; |
6f7bef75 | 2631 | else if (INTEL_GEN(dev_priv) >= 4) |
803688ba | 2632 | engine->emit_bb_start = i965_emit_bb_start; |
6f7bef75 | 2633 | else if (IS_I830(dev_priv) || IS_845G(dev_priv)) |
803688ba | 2634 | engine->emit_bb_start = i830_emit_bb_start; |
6f7bef75 | 2635 | else |
803688ba | 2636 | engine->emit_bb_start = i915_emit_bb_start; |
06a2fe22 TU |
2637 | } |
2638 | ||
8b3e2d36 | 2639 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2640 | { |
8b3e2d36 | 2641 | struct drm_i915_private *dev_priv = engine->i915; |
3e78998a | 2642 | int ret; |
5c1143bb | 2643 | |
06a2fe22 TU |
2644 | intel_ring_default_vfuncs(dev_priv, engine); |
2645 | ||
61ff75ac CW |
2646 | if (HAS_L3_DPF(dev_priv)) |
2647 | engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
f8973c21 | 2648 | |
c033666a | 2649 | if (INTEL_GEN(dev_priv) >= 8) { |
e2f80391 | 2650 | engine->init_context = intel_rcs_ctx_init; |
ddd66c51 | 2651 | engine->emit_request = gen8_render_emit_request; |
c7fe7d25 | 2652 | engine->emit_flush = gen8_render_ring_flush; |
39df9190 | 2653 | if (i915.semaphores) |
e2f80391 | 2654 | engine->semaphore.signal = gen8_rcs_signal; |
c033666a | 2655 | } else if (INTEL_GEN(dev_priv) >= 6) { |
e2f80391 | 2656 | engine->init_context = intel_rcs_ctx_init; |
c7fe7d25 | 2657 | engine->emit_flush = gen7_render_ring_flush; |
c033666a | 2658 | if (IS_GEN6(dev_priv)) |
c7fe7d25 | 2659 | engine->emit_flush = gen6_render_ring_flush; |
c033666a | 2660 | } else if (IS_GEN5(dev_priv)) { |
c7fe7d25 | 2661 | engine->emit_flush = gen4_render_ring_flush; |
59465b5f | 2662 | } else { |
c033666a | 2663 | if (INTEL_GEN(dev_priv) < 4) |
c7fe7d25 | 2664 | engine->emit_flush = gen2_render_ring_flush; |
46f0f8d1 | 2665 | else |
c7fe7d25 | 2666 | engine->emit_flush = gen4_render_ring_flush; |
e2f80391 | 2667 | engine->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2668 | } |
707d9cf9 | 2669 | |
c033666a | 2670 | if (IS_HASWELL(dev_priv)) |
803688ba | 2671 | engine->emit_bb_start = hsw_emit_bb_start; |
6f7bef75 | 2672 | |
e2f80391 TU |
2673 | engine->init_hw = init_render_ring; |
2674 | engine->cleanup = render_ring_cleanup; | |
59465b5f | 2675 | |
acd27845 | 2676 | ret = intel_init_ring_buffer(engine); |
99be1dfe DV |
2677 | if (ret) |
2678 | return ret; | |
2679 | ||
f8973c21 | 2680 | if (INTEL_GEN(dev_priv) >= 6) { |
56c0f1a7 | 2681 | ret = intel_engine_create_scratch(engine, 4096); |
7d5ea807 CW |
2682 | if (ret) |
2683 | return ret; | |
2684 | } else if (HAS_BROKEN_CS_TLB(dev_priv)) { | |
56c0f1a7 | 2685 | ret = intel_engine_create_scratch(engine, I830_WA_SIZE); |
99be1dfe DV |
2686 | if (ret) |
2687 | return ret; | |
2688 | } | |
2689 | ||
2690 | return 0; | |
5c1143bb XH |
2691 | } |
2692 | ||
8b3e2d36 | 2693 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) |
5c1143bb | 2694 | { |
8b3e2d36 | 2695 | struct drm_i915_private *dev_priv = engine->i915; |
58fa3835 | 2696 | |
06a2fe22 TU |
2697 | intel_ring_default_vfuncs(dev_priv, engine); |
2698 | ||
c033666a | 2699 | if (INTEL_GEN(dev_priv) >= 6) { |
0fd2c201 | 2700 | /* gen6 bsd needs a special wa for tail updates */ |
c033666a | 2701 | if (IS_GEN6(dev_priv)) |
c5efa1ad | 2702 | engine->submit_request = gen6_bsd_submit_request; |
c7fe7d25 | 2703 | engine->emit_flush = gen6_bsd_ring_flush; |
c78d6061 | 2704 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2705 | engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 | 2706 | } else { |
e2f80391 | 2707 | engine->mmio_base = BSD_RING_BASE; |
c7fe7d25 | 2708 | engine->emit_flush = bsd_ring_flush; |
8d228911 | 2709 | if (IS_GEN5(dev_priv)) |
e2f80391 | 2710 | engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
8d228911 | 2711 | else |
e2f80391 | 2712 | engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
58fa3835 | 2713 | } |
58fa3835 | 2714 | |
acd27845 | 2715 | return intel_init_ring_buffer(engine); |
5c1143bb | 2716 | } |
549f7365 | 2717 | |
845f74a7 | 2718 | /** |
62659920 | 2719 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 | 2720 | */ |
8b3e2d36 | 2721 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) |
845f74a7 | 2722 | { |
8b3e2d36 | 2723 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2724 | |
2725 | intel_ring_default_vfuncs(dev_priv, engine); | |
2726 | ||
c7fe7d25 | 2727 | engine->emit_flush = gen6_bsd_ring_flush; |
845f74a7 | 2728 | |
acd27845 | 2729 | return intel_init_ring_buffer(engine); |
845f74a7 ZY |
2730 | } |
2731 | ||
8b3e2d36 | 2732 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) |
549f7365 | 2733 | { |
8b3e2d36 | 2734 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2735 | |
2736 | intel_ring_default_vfuncs(dev_priv, engine); | |
2737 | ||
c7fe7d25 | 2738 | engine->emit_flush = gen6_ring_flush; |
c78d6061 | 2739 | if (INTEL_GEN(dev_priv) < 8) |
e2f80391 | 2740 | engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
549f7365 | 2741 | |
acd27845 | 2742 | return intel_init_ring_buffer(engine); |
549f7365 | 2743 | } |
a7b9761d | 2744 | |
8b3e2d36 | 2745 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) |
9a8a2213 | 2746 | { |
8b3e2d36 | 2747 | struct drm_i915_private *dev_priv = engine->i915; |
06a2fe22 TU |
2748 | |
2749 | intel_ring_default_vfuncs(dev_priv, engine); | |
2750 | ||
c7fe7d25 | 2751 | engine->emit_flush = gen6_ring_flush; |
abd58f01 | 2752 | |
c78d6061 | 2753 | if (INTEL_GEN(dev_priv) < 8) { |
e2f80391 | 2754 | engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
31bb59cc CW |
2755 | engine->irq_enable = hsw_vebox_irq_enable; |
2756 | engine->irq_disable = hsw_vebox_irq_disable; | |
abd58f01 | 2757 | } |
9a8a2213 | 2758 | |
acd27845 | 2759 | return intel_init_ring_buffer(engine); |
9a8a2213 | 2760 | } |