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drm/i915: add a new BSD ring buffer for Sandybridge
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
62fdfeaf 32#include "i915_drv.h"
8187a2b7 33#include "i915_drm.h"
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
6f392d54
CW		 37static u32 i915_gem_get_seqno(struct drm_device *dev)
38{
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 u32 seqno;
41
42 seqno = dev_priv->next_seqno;
43
44 /* reserve 0 for non-seqno */
45 if (++dev_priv->next_seqno == 0)
46 dev_priv->next_seqno = 1;
47
48 return seqno;
49}
50
8187a2b7
ZN		 51static void
52render_ring_flush(struct drm_device *dev,
53 struct intel_ring_buffer *ring,
54 u32 invalidate_domains,
55 u32 flush_domains)
62fdfeaf 56{
6f392d54
CW		 57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 cmd;
59
62fdfeaf
EA		 60#if WATCH_EXEC
61 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62 invalidate_domains, flush_domains);
63#endif
6f392d54
CW		 64
65 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
62fdfeaf
EA		 66 invalidate_domains, flush_domains);
67
62fdfeaf
EA		 68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69 /*
70 * read/write caches:
71 *
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */
96
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
a6c45cf0 101 if (INTEL_INFO(dev)->gen < 4) {
62fdfeaf
EA		 102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
112#if WATCH_EXEC
113 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
114#endif
be26a10b 115 intel_ring_begin(dev, ring, 2);
8187a2b7
ZN		 116 intel_ring_emit(dev, ring, cmd);
117 intel_ring_emit(dev, ring, MI_NOOP);
118 intel_ring_advance(dev, ring);
62fdfeaf 119 }
8187a2b7
ZN		 120}
121
122static unsigned int render_ring_get_head(struct drm_device *dev,
123 struct intel_ring_buffer *ring)
124{
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 return I915_READ(PRB0_HEAD) & HEAD_ADDR;
127}
62fdfeaf 128
8187a2b7
ZN		 129static unsigned int render_ring_get_tail(struct drm_device *dev,
130 struct intel_ring_buffer *ring)
131{
132 drm_i915_private_t *dev_priv = dev->dev_private;
133 return I915_READ(PRB0_TAIL) & TAIL_ADDR;
62fdfeaf 134}
8187a2b7 135
d46eefa2
XH		 136static inline void render_ring_set_tail(struct drm_device *dev, u32 value)
137{
138 drm_i915_private_t *dev_priv = dev->dev_private;
139 I915_WRITE(PRB0_TAIL, value);
140}
141
8187a2b7
ZN		 142static unsigned int render_ring_get_active_head(struct drm_device *dev,
143 struct intel_ring_buffer *ring)
144{
145 drm_i915_private_t *dev_priv = dev->dev_private;
a6c45cf0 146 u32 acthd_reg = INTEL_INFO(dev)->gen ? ACTHD_I965 : ACTHD;
8187a2b7
ZN		 147
148 return I915_READ(acthd_reg);
149}
150
8187a2b7
ZN		 151static int init_ring_common(struct drm_device *dev,
152 struct intel_ring_buffer *ring)
153{
154 u32 head;
155 drm_i915_private_t *dev_priv = dev->dev_private;
156 struct drm_i915_gem_object *obj_priv;
157 obj_priv = to_intel_bo(ring->gem_object);
158
159 /* Stop the ring if it's running. */
160 I915_WRITE(ring->regs.ctl, 0);
161 I915_WRITE(ring->regs.head, 0);
d46eefa2 162 ring->set_tail(dev, 0);
8187a2b7
ZN		 163
164 /* Initialize the ring. */
165 I915_WRITE(ring->regs.start, obj_priv->gtt_offset);
166 head = ring->get_head(dev, ring);
167
168 /* G45 ring initialization fails to reset head to zero */
169 if (head != 0) {
170 DRM_ERROR("%s head not reset to zero "
171 "ctl %08x head %08x tail %08x start %08x\n",
172 ring->name,
173 I915_READ(ring->regs.ctl),
174 I915_READ(ring->regs.head),
175 I915_READ(ring->regs.tail),
176 I915_READ(ring->regs.start));
177
178 I915_WRITE(ring->regs.head, 0);
179
180 DRM_ERROR("%s head forced to zero "
181 "ctl %08x head %08x tail %08x start %08x\n",
182 ring->name,
183 I915_READ(ring->regs.ctl),
184 I915_READ(ring->regs.head),
185 I915_READ(ring->regs.tail),
186 I915_READ(ring->regs.start));
187 }
188
189 I915_WRITE(ring->regs.ctl,
190 ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
191 | RING_NO_REPORT | RING_VALID);
192
193 head = I915_READ(ring->regs.head) & HEAD_ADDR;
194 /* If the head is still not zero, the ring is dead */
195 if (head != 0) {
196 DRM_ERROR("%s initialization failed "
197 "ctl %08x head %08x tail %08x start %08x\n",
198 ring->name,
199 I915_READ(ring->regs.ctl),
200 I915_READ(ring->regs.head),
201 I915_READ(ring->regs.tail),
202 I915_READ(ring->regs.start));
203 return -EIO;
204 }
205
206 if (!drm_core_check_feature(dev, DRIVER_MODESET))
207 i915_kernel_lost_context(dev);
208 else {
209 ring->head = ring->get_head(dev, ring);
210 ring->tail = ring->get_tail(dev, ring);
211 ring->space = ring->head - (ring->tail + 8);
212 if (ring->space < 0)
213 ring->space += ring->size;
214 }
215 return 0;
216}
217
218static int init_render_ring(struct drm_device *dev,
219 struct intel_ring_buffer *ring)
220{
221 drm_i915_private_t *dev_priv = dev->dev_private;
222 int ret = init_ring_common(dev, ring);
a69ffdbf
ZW		 223 int mode;
224
a6c45cf0 225 if (INTEL_INFO(dev)->gen > 3) {
a69ffdbf
ZW		 226 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
227 if (IS_GEN6(dev))
228 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
229 I915_WRITE(MI_MODE, mode);
8187a2b7
ZN		 230 }
231 return ret;
232}
233
62fdfeaf 234#define PIPE_CONTROL_FLUSH(addr) \
8187a2b7 235do { \
62fdfeaf 236 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
ca76482e 237 PIPE_CONTROL_DEPTH_STALL | 2); \
62fdfeaf
EA		 238 OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
239 OUT_RING(0); \
240 OUT_RING(0); \
8187a2b7 241} while (0)
62fdfeaf
EA		 242
243/**
244 * Creates a new sequence number, emitting a write of it to the status page
245 * plus an interrupt, which will trigger i915_user_interrupt_handler.
246 *
247 * Must be called with struct_lock held.
248 *
249 * Returned sequence numbers are nonzero on success.
250 */
8187a2b7
ZN		 251static u32
252render_ring_add_request(struct drm_device *dev,
253 struct intel_ring_buffer *ring,
254 struct drm_file *file_priv,
255 u32 flush_domains)
62fdfeaf
EA		 256{
257 drm_i915_private_t *dev_priv = dev->dev_private;
6f392d54
CW		 258 u32 seqno;
259
260 seqno = i915_gem_get_seqno(dev);
ca76482e
ZW		 261
262 if (IS_GEN6(dev)) {
263 BEGIN_LP_RING(6);
264 OUT_RING(GFX_OP_PIPE_CONTROL | 3);
265 OUT_RING(PIPE_CONTROL_QW_WRITE |
266 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
267 PIPE_CONTROL_NOTIFY);
268 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
269 OUT_RING(seqno);
270 OUT_RING(0);
271 OUT_RING(0);
272 ADVANCE_LP_RING();
273 } else if (HAS_PIPE_CONTROL(dev)) {
62fdfeaf
EA		 274 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
275
276 /*
277 * Workaround qword write incoherence by flushing the
278 * PIPE_NOTIFY buffers out to memory before requesting
279 * an interrupt.
280 */
281 BEGIN_LP_RING(32);
282 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
283 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
284 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
285 OUT_RING(seqno);
286 OUT_RING(0);
287 PIPE_CONTROL_FLUSH(scratch_addr);
288 scratch_addr += 128; /* write to separate cachelines */
289 PIPE_CONTROL_FLUSH(scratch_addr);
290 scratch_addr += 128;
291 PIPE_CONTROL_FLUSH(scratch_addr);
292 scratch_addr += 128;
293 PIPE_CONTROL_FLUSH(scratch_addr);
294 scratch_addr += 128;
295 PIPE_CONTROL_FLUSH(scratch_addr);
296 scratch_addr += 128;
297 PIPE_CONTROL_FLUSH(scratch_addr);
298 OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
299 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
300 PIPE_CONTROL_NOTIFY);
301 OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
302 OUT_RING(seqno);
303 OUT_RING(0);
304 ADVANCE_LP_RING();
305 } else {
306 BEGIN_LP_RING(4);
307 OUT_RING(MI_STORE_DWORD_INDEX);
308 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
309 OUT_RING(seqno);
310
311 OUT_RING(MI_USER_INTERRUPT);
312 ADVANCE_LP_RING();
313 }
314 return seqno;
315}
316
8187a2b7
ZN		 317static u32
318render_ring_get_gem_seqno(struct drm_device *dev,
319 struct intel_ring_buffer *ring)
320{
321 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
322 if (HAS_PIPE_CONTROL(dev))
323 return ((volatile u32 *)(dev_priv->seqno_page))[0];
324 else
325 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
326}
327
328static void
329render_ring_get_user_irq(struct drm_device *dev,
330 struct intel_ring_buffer *ring)
62fdfeaf
EA		 331{
332 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
333 unsigned long irqflags;
334
335 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
8187a2b7 336 if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
62fdfeaf
EA		 337 if (HAS_PCH_SPLIT(dev))
338 ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
339 else
340 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
341 }
342 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
343}
344
8187a2b7
ZN		 345static void
346render_ring_put_user_irq(struct drm_device *dev,
347 struct intel_ring_buffer *ring)
62fdfeaf
EA		 348{
349 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
350 unsigned long irqflags;
351
352 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
8187a2b7
ZN		 353 BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
354 if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
62fdfeaf
EA		 355 if (HAS_PCH_SPLIT(dev))
356 ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
357 else
358 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
359 }
360 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
361}
362
8187a2b7
ZN		 363static void render_setup_status_page(struct drm_device *dev,
364 struct intel_ring_buffer *ring)
365{
366 drm_i915_private_t *dev_priv = dev->dev_private;
367 if (IS_GEN6(dev)) {
368 I915_WRITE(HWS_PGA_GEN6, ring->status_page.gfx_addr);
369 I915_READ(HWS_PGA_GEN6); /* posting read */
370 } else {
371 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
372 I915_READ(HWS_PGA); /* posting read */
373 }
374
375}
376
d1b851fc
ZN		 377void
378bsd_ring_flush(struct drm_device *dev,
379 struct intel_ring_buffer *ring,
380 u32 invalidate_domains,
381 u32 flush_domains)
382{
be26a10b 383 intel_ring_begin(dev, ring, 2);
d1b851fc
ZN		 384 intel_ring_emit(dev, ring, MI_FLUSH);
385 intel_ring_emit(dev, ring, MI_NOOP);
386 intel_ring_advance(dev, ring);
387}
388
389static inline unsigned int bsd_ring_get_head(struct drm_device *dev,
390 struct intel_ring_buffer *ring)
391{
392 drm_i915_private_t *dev_priv = dev->dev_private;
393 return I915_READ(BSD_RING_HEAD) & HEAD_ADDR;
394}
395
396static inline unsigned int bsd_ring_get_tail(struct drm_device *dev,
397 struct intel_ring_buffer *ring)
398{
399 drm_i915_private_t *dev_priv = dev->dev_private;
400 return I915_READ(BSD_RING_TAIL) & TAIL_ADDR;
401}
402
d46eefa2
XH		 403static inline void bsd_ring_set_tail(struct drm_device *dev, u32 value)
404{
405 drm_i915_private_t *dev_priv = dev->dev_private;
406 I915_WRITE(BSD_RING_TAIL, value);
407}
408
d1b851fc
ZN		 409static inline unsigned int bsd_ring_get_active_head(struct drm_device *dev,
410 struct intel_ring_buffer *ring)
411{
412 drm_i915_private_t *dev_priv = dev->dev_private;
413 return I915_READ(BSD_RING_ACTHD);
414}
415
d1b851fc
ZN		 416static int init_bsd_ring(struct drm_device *dev,
417 struct intel_ring_buffer *ring)
418{
419 return init_ring_common(dev, ring);
420}
421
422static u32
423bsd_ring_add_request(struct drm_device *dev,
424 struct intel_ring_buffer *ring,
425 struct drm_file *file_priv,
426 u32 flush_domains)
427{
428 u32 seqno;
6f392d54
CW		 429
430 seqno = i915_gem_get_seqno(dev);
431
d1b851fc
ZN		 432 intel_ring_begin(dev, ring, 4);
433 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
434 intel_ring_emit(dev, ring,
435 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
436 intel_ring_emit(dev, ring, seqno);
437 intel_ring_emit(dev, ring, MI_USER_INTERRUPT);
438 intel_ring_advance(dev, ring);
439
440 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
441
442 return seqno;
443}
444
445static void bsd_setup_status_page(struct drm_device *dev,
446 struct intel_ring_buffer *ring)
447{
448 drm_i915_private_t *dev_priv = dev->dev_private;
449 I915_WRITE(BSD_HWS_PGA, ring->status_page.gfx_addr);
450 I915_READ(BSD_HWS_PGA);
451}
452
453static void
454bsd_ring_get_user_irq(struct drm_device *dev,
455 struct intel_ring_buffer *ring)
456{
457 /* do nothing */
458}
459static void
460bsd_ring_put_user_irq(struct drm_device *dev,
461 struct intel_ring_buffer *ring)
462{
463 /* do nothing */
464}
465
466static u32
467bsd_ring_get_gem_seqno(struct drm_device *dev,
468 struct intel_ring_buffer *ring)
469{
470 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
471}
472
473static int
474bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
475 struct intel_ring_buffer *ring,
476 struct drm_i915_gem_execbuffer2 *exec,
477 struct drm_clip_rect *cliprects,
478 uint64_t exec_offset)
479{
480 uint32_t exec_start;
481 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
482 intel_ring_begin(dev, ring, 2);
483 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START |
484 (2 << 6) | MI_BATCH_NON_SECURE_I965);
485 intel_ring_emit(dev, ring, exec_start);
486 intel_ring_advance(dev, ring);
487 return 0;
488}
489
490
8187a2b7
ZN		 491static int
492render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
493 struct intel_ring_buffer *ring,
494 struct drm_i915_gem_execbuffer2 *exec,
495 struct drm_clip_rect *cliprects,
496 uint64_t exec_offset)
62fdfeaf
EA		 497{
498 drm_i915_private_t *dev_priv = dev->dev_private;
499 int nbox = exec->num_cliprects;
500 int i = 0, count;
501 uint32_t exec_start, exec_len;
62fdfeaf
EA		 502 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
503 exec_len = (uint32_t) exec->batch_len;
504
6f392d54 505 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
62fdfeaf
EA		 506
507 count = nbox ? nbox : 1;
508
509 for (i = 0; i < count; i++) {
510 if (i < nbox) {
511 int ret = i915_emit_box(dev, cliprects, i,
512 exec->DR1, exec->DR4);
513 if (ret)
514 return ret;
515 }
516
517 if (IS_I830(dev) || IS_845G(dev)) {
8187a2b7
ZN		 518 intel_ring_begin(dev, ring, 4);
519 intel_ring_emit(dev, ring, MI_BATCH_BUFFER);
520 intel_ring_emit(dev, ring,
521 exec_start | MI_BATCH_NON_SECURE);
522 intel_ring_emit(dev, ring, exec_start + exec_len - 4);
523 intel_ring_emit(dev, ring, 0);
62fdfeaf 524 } else {
8187a2b7 525 intel_ring_begin(dev, ring, 4);
a6c45cf0 526 if (INTEL_INFO(dev)->gen >= 4) {
8187a2b7
ZN		 527 intel_ring_emit(dev, ring,
528 MI_BATCH_BUFFER_START | (2 << 6)
529 | MI_BATCH_NON_SECURE_I965);
530 intel_ring_emit(dev, ring, exec_start);
62fdfeaf 531 } else {
8187a2b7
ZN		 532 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START
533 | (2 << 6));
534 intel_ring_emit(dev, ring, exec_start |
535 MI_BATCH_NON_SECURE);
62fdfeaf 536 }
62fdfeaf 537 }
8187a2b7 538 intel_ring_advance(dev, ring);
62fdfeaf
EA		 539 }
540
1cafd347
ZN		 541 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
542 intel_ring_begin(dev, ring, 2);
543 intel_ring_emit(dev, ring, MI_FLUSH |
544 MI_NO_WRITE_FLUSH |
545 MI_INVALIDATE_ISP );
546 intel_ring_emit(dev, ring, MI_NOOP);
547 intel_ring_advance(dev, ring);
548 }
62fdfeaf 549 /* XXX breadcrumb */
1cafd347 550
62fdfeaf
EA		 551 return 0;
552}
553
8187a2b7
ZN		 554static void cleanup_status_page(struct drm_device *dev,
555 struct intel_ring_buffer *ring)
62fdfeaf
EA		 556{
557 drm_i915_private_t *dev_priv = dev->dev_private;
558 struct drm_gem_object *obj;
559 struct drm_i915_gem_object *obj_priv;
560
8187a2b7
ZN		 561 obj = ring->status_page.obj;
562 if (obj == NULL)
62fdfeaf 563 return;
62fdfeaf
EA		 564 obj_priv = to_intel_bo(obj);
565
566 kunmap(obj_priv->pages[0]);
567 i915_gem_object_unpin(obj);
568 drm_gem_object_unreference(obj);
8187a2b7 569 ring->status_page.obj = NULL;
62fdfeaf
EA		 570
571 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 572}
573
8187a2b7
ZN		 574static int init_status_page(struct drm_device *dev,
575 struct intel_ring_buffer *ring)
62fdfeaf
EA		 576{
577 drm_i915_private_t *dev_priv = dev->dev_private;
578 struct drm_gem_object *obj;
579 struct drm_i915_gem_object *obj_priv;
580 int ret;
581
62fdfeaf
EA		 582 obj = i915_gem_alloc_object(dev, 4096);
583 if (obj == NULL) {
584 DRM_ERROR("Failed to allocate status page\n");
585 ret = -ENOMEM;
586 goto err;
587 }
588 obj_priv = to_intel_bo(obj);
589 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
590
591 ret = i915_gem_object_pin(obj, 4096);
592 if (ret != 0) {
62fdfeaf
EA		 593 goto err_unref;
594 }
595
8187a2b7
ZN		 596 ring->status_page.gfx_addr = obj_priv->gtt_offset;
597 ring->status_page.page_addr = kmap(obj_priv->pages[0]);
598 if (ring->status_page.page_addr == NULL) {
62fdfeaf 599 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 600 goto err_unpin;
601 }
8187a2b7
ZN		 602 ring->status_page.obj = obj;
603 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 604
8187a2b7
ZN		 605 ring->setup_status_page(dev, ring);
606 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
607 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 608
609 return 0;
610
611err_unpin:
612 i915_gem_object_unpin(obj);
613err_unref:
614 drm_gem_object_unreference(obj);
615err:
8187a2b7 616 return ret;
62fdfeaf
EA		 617}
618
8187a2b7
ZN		 619
620int intel_init_ring_buffer(struct drm_device *dev,
621 struct intel_ring_buffer *ring)
62fdfeaf 622{
8187a2b7
ZN		 623 struct drm_i915_gem_object *obj_priv;
624 struct drm_gem_object *obj;
dd785e35
CW		 625 int ret;
626
8187a2b7 627 ring->dev = dev;
62fdfeaf 628
8187a2b7
ZN		 629 if (I915_NEED_GFX_HWS(dev)) {
630 ret = init_status_page(dev, ring);
631 if (ret)
632 return ret;
633 }
62fdfeaf 634
8187a2b7 635 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 636 if (obj == NULL) {
637 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 638 ret = -ENOMEM;
dd785e35 639 goto err_hws;
62fdfeaf 640 }
62fdfeaf 641
8187a2b7
ZN		 642 ring->gem_object = obj;
643
644 ret = i915_gem_object_pin(obj, ring->alignment);
dd785e35
CW		 645 if (ret)
646 goto err_unref;
62fdfeaf 647
8187a2b7
ZN		 648 obj_priv = to_intel_bo(obj);
649 ring->map.size = ring->size;
62fdfeaf 650 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
62fdfeaf
EA		 651 ring->map.type = 0;
652 ring->map.flags = 0;
653 ring->map.mtrr = 0;
654
655 drm_core_ioremap_wc(&ring->map, dev);
656 if (ring->map.handle == NULL) {
657 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 658 ret = -EINVAL;
dd785e35 659 goto err_unpin;
62fdfeaf
EA		 660 }
661
8187a2b7
ZN		 662 ring->virtual_start = ring->map.handle;
663 ret = ring->init(dev, ring);
dd785e35
CW		 664 if (ret)
665 goto err_unmap;
62fdfeaf 666
62fdfeaf
EA		 667 if (!drm_core_check_feature(dev, DRIVER_MODESET))
668 i915_kernel_lost_context(dev);
669 else {
8187a2b7
ZN		 670 ring->head = ring->get_head(dev, ring);
671 ring->tail = ring->get_tail(dev, ring);
62fdfeaf
EA		 672 ring->space = ring->head - (ring->tail + 8);
673 if (ring->space < 0)
8187a2b7 674 ring->space += ring->size;
62fdfeaf 675 }
8187a2b7
ZN		 676 INIT_LIST_HEAD(&ring->active_list);
677 INIT_LIST_HEAD(&ring->request_list);
678 return ret;
dd785e35
CW		 679
680err_unmap:
681 drm_core_ioremapfree(&ring->map, dev);
682err_unpin:
683 i915_gem_object_unpin(obj);
684err_unref:
685 drm_gem_object_unreference(obj);
686 ring->gem_object = NULL;
687err_hws:
8187a2b7
ZN		 688 cleanup_status_page(dev, ring);
689 return ret;
62fdfeaf
EA		 690}
691
8187a2b7
ZN		 692void intel_cleanup_ring_buffer(struct drm_device *dev,
693 struct intel_ring_buffer *ring)
62fdfeaf 694{
8187a2b7 695 if (ring->gem_object == NULL)
62fdfeaf
EA		 696 return;
697
8187a2b7 698 drm_core_ioremapfree(&ring->map, dev);
62fdfeaf 699
8187a2b7
ZN		 700 i915_gem_object_unpin(ring->gem_object);
701 drm_gem_object_unreference(ring->gem_object);
702 ring->gem_object = NULL;
703 cleanup_status_page(dev, ring);
62fdfeaf
EA		 704}
705
8187a2b7
ZN		 706int intel_wrap_ring_buffer(struct drm_device *dev,
707 struct intel_ring_buffer *ring)
62fdfeaf 708{
8187a2b7 709 unsigned int *virt;
62fdfeaf 710 int rem;
8187a2b7 711 rem = ring->size - ring->tail;
62fdfeaf 712
8187a2b7
ZN		 713 if (ring->space < rem) {
714 int ret = intel_wait_ring_buffer(dev, ring, rem);
62fdfeaf
EA		 715 if (ret)
716 return ret;
717 }
62fdfeaf 718
8187a2b7 719 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1741dd4a
CW		 720 rem /= 8;
721 while (rem--) {
62fdfeaf 722 *virt++ = MI_NOOP;
1741dd4a
CW		 723 *virt++ = MI_NOOP;
724 }
62fdfeaf 725
8187a2b7 726 ring->tail = 0;
43ed340a 727 ring->space = ring->head - 8;
62fdfeaf
EA		 728
729 return 0;
730}
731
8187a2b7
ZN		 732int intel_wait_ring_buffer(struct drm_device *dev,
733 struct intel_ring_buffer *ring, int n)
62fdfeaf 734{
8187a2b7 735 unsigned long end;
62fdfeaf
EA		 736
737 trace_i915_ring_wait_begin (dev);
8187a2b7
ZN		 738 end = jiffies + 3 * HZ;
739 do {
740 ring->head = ring->get_head(dev, ring);
62fdfeaf
EA		 741 ring->space = ring->head - (ring->tail + 8);
742 if (ring->space < 0)
8187a2b7 743 ring->space += ring->size;
62fdfeaf
EA		 744 if (ring->space >= n) {
745 trace_i915_ring_wait_end (dev);
746 return 0;
747 }
748
749 if (dev->primary->master) {
750 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
751 if (master_priv->sarea_priv)
752 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
753 }
d1b851fc 754
8187a2b7
ZN		 755 yield();
756 } while (!time_after(jiffies, end));
757 trace_i915_ring_wait_end (dev);
758 return -EBUSY;
759}
62fdfeaf 760
8187a2b7 761void intel_ring_begin(struct drm_device *dev,
be26a10b 762 struct intel_ring_buffer *ring, int num_dwords)
8187a2b7 763{
be26a10b 764 int n = 4*num_dwords;
8187a2b7
ZN		 765 if (unlikely(ring->tail + n > ring->size))
766 intel_wrap_ring_buffer(dev, ring);
767 if (unlikely(ring->space < n))
768 intel_wait_ring_buffer(dev, ring, n);
d97ed339
CW		 769
770 ring->space -= n;
8187a2b7 771}
62fdfeaf 772
8187a2b7
ZN		 773void intel_ring_advance(struct drm_device *dev,
774 struct intel_ring_buffer *ring)
775{
d97ed339 776 ring->tail &= ring->size - 1;
a3f07cd5 777 ring->set_tail(dev, ring->tail);
8187a2b7 778}
62fdfeaf 779
8187a2b7
ZN		 780void intel_fill_struct(struct drm_device *dev,
781 struct intel_ring_buffer *ring,
782 void *data,
783 unsigned int len)
784{
785 unsigned int *virt = ring->virtual_start + ring->tail;
786 BUG_ON((len&~(4-1)) != 0);
be26a10b 787 intel_ring_begin(dev, ring, len/4);
8187a2b7
ZN		 788 memcpy(virt, data, len);
789 ring->tail += len;
790 ring->tail &= ring->size - 1;
791 ring->space -= len;
792 intel_ring_advance(dev, ring);
793}
62fdfeaf 794
5c1143bb 795static struct intel_ring_buffer render_ring = {
8187a2b7 796 .name = "render ring",
9220434a 797 .id = RING_RENDER,
8187a2b7
ZN		 798 .regs = {
799 .ctl = PRB0_CTL,
800 .head = PRB0_HEAD,
801 .tail = PRB0_TAIL,
802 .start = PRB0_START
803 },
8187a2b7
ZN		 804 .size = 32 * PAGE_SIZE,
805 .alignment = PAGE_SIZE,
806 .virtual_start = NULL,
807 .dev = NULL,
808 .gem_object = NULL,
809 .head = 0,
810 .tail = 0,
811 .space = 0,
8187a2b7
ZN		 812 .user_irq_refcount = 0,
813 .irq_gem_seqno = 0,
814 .waiting_gem_seqno = 0,
815 .setup_status_page = render_setup_status_page,
816 .init = init_render_ring,
817 .get_head = render_ring_get_head,
818 .get_tail = render_ring_get_tail,
d46eefa2 819 .set_tail = render_ring_set_tail,
8187a2b7 820 .get_active_head = render_ring_get_active_head,
8187a2b7
ZN		 821 .flush = render_ring_flush,
822 .add_request = render_ring_add_request,
823 .get_gem_seqno = render_ring_get_gem_seqno,
824 .user_irq_get = render_ring_get_user_irq,
825 .user_irq_put = render_ring_put_user_irq,
826 .dispatch_gem_execbuffer = render_ring_dispatch_gem_execbuffer,
827 .status_page = {NULL, 0, NULL},
828 .map = {0,}
829};
d1b851fc
ZN		 830
831/* ring buffer for bit-stream decoder */
832
5c1143bb 833static struct intel_ring_buffer bsd_ring = {
d1b851fc 834 .name = "bsd ring",
9220434a 835 .id = RING_BSD,
d1b851fc
ZN		 836 .regs = {
837 .ctl = BSD_RING_CTL,
838 .head = BSD_RING_HEAD,
839 .tail = BSD_RING_TAIL,
840 .start = BSD_RING_START
841 },
d1b851fc
ZN		 842 .size = 32 * PAGE_SIZE,
843 .alignment = PAGE_SIZE,
844 .virtual_start = NULL,
845 .dev = NULL,
846 .gem_object = NULL,
847 .head = 0,
848 .tail = 0,
849 .space = 0,
d1b851fc
ZN		 850 .user_irq_refcount = 0,
851 .irq_gem_seqno = 0,
852 .waiting_gem_seqno = 0,
853 .setup_status_page = bsd_setup_status_page,
854 .init = init_bsd_ring,
855 .get_head = bsd_ring_get_head,
856 .get_tail = bsd_ring_get_tail,
d46eefa2 857 .set_tail = bsd_ring_set_tail,
d1b851fc 858 .get_active_head = bsd_ring_get_active_head,
d1b851fc
ZN		 859 .flush = bsd_ring_flush,
860 .add_request = bsd_ring_add_request,
861 .get_gem_seqno = bsd_ring_get_gem_seqno,
862 .user_irq_get = bsd_ring_get_user_irq,
863 .user_irq_put = bsd_ring_put_user_irq,
864 .dispatch_gem_execbuffer = bsd_ring_dispatch_gem_execbuffer,
865 .status_page = {NULL, 0, NULL},
866 .map = {0,}
867};
5c1143bb 868
881f47b6
XH		 869
870static void gen6_bsd_setup_status_page(struct drm_device *dev,
871 struct intel_ring_buffer *ring)
872{
873 drm_i915_private_t *dev_priv = dev->dev_private;
874 I915_WRITE(GEN6_BSD_HWS_PGA, ring->status_page.gfx_addr);
875 I915_READ(GEN6_BSD_HWS_PGA);
876}
877
878static inline unsigned int gen6_bsd_ring_get_head(struct drm_device *dev,
879 struct intel_ring_buffer *ring)
880{
881 drm_i915_private_t *dev_priv = dev->dev_private;
882 return I915_READ(GEN6_BSD_RING_HEAD) & HEAD_ADDR;
883}
884
885static inline unsigned int gen6_bsd_ring_get_tail(struct drm_device *dev,
886 struct intel_ring_buffer *ring)
887{
888 drm_i915_private_t *dev_priv = dev->dev_private;
889 return I915_READ(GEN6_BSD_RING_TAIL) & TAIL_ADDR;
890}
891
892static inline void gen6_bsd_ring_set_tail(struct drm_device *dev,
893 u32 value)
894{
895 drm_i915_private_t *dev_priv = dev->dev_private;
896
897 /* Every tail move must follow the sequence below */
898 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
899 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
900 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
901 I915_WRITE(GEN6_BSD_RNCID, 0x0);
902
903 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
904 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
905 50))
906 DRM_ERROR("timed out waiting for IDLE Indicator\n");
907
908 I915_WRITE(GEN6_BSD_RING_TAIL, value);
909 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
910 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
911 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
912}
913
914static inline unsigned int gen6_bsd_ring_get_active_head(struct drm_device *dev,
915 struct intel_ring_buffer *ring)
916{
917 drm_i915_private_t *dev_priv = dev->dev_private;
918 return I915_READ(GEN6_BSD_RING_ACTHD);
919}
920
921static void gen6_bsd_ring_flush(struct drm_device *dev,
922 struct intel_ring_buffer *ring,
923 u32 invalidate_domains,
924 u32 flush_domains)
925{
926 intel_ring_begin(dev, ring, 4);
927 intel_ring_emit(dev, ring, MI_FLUSH_DW);
928 intel_ring_emit(dev, ring, 0);
929 intel_ring_emit(dev, ring, 0);
930 intel_ring_emit(dev, ring, 0);
931 intel_ring_advance(dev, ring);
932}
933
934static int
935gen6_bsd_ring_dispatch_gem_execbuffer(struct drm_device *dev,
936 struct intel_ring_buffer *ring,
937 struct drm_i915_gem_execbuffer2 *exec,
938 struct drm_clip_rect *cliprects,
939 uint64_t exec_offset)
940{
941 uint32_t exec_start;
942 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
943 intel_ring_begin(dev, ring, 2);
944 intel_ring_emit(dev, ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); /* bit0-7 is the length on GEN6+ */
945 intel_ring_emit(dev, ring, exec_start);
946 intel_ring_advance(dev, ring);
947 return 0;
948}
949
950/* ring buffer for Video Codec for Gen6+ */
951static struct intel_ring_buffer gen6_bsd_ring = {
952 .name = "gen6 bsd ring",
953 .id = RING_BSD,
954 .regs = {
955 .ctl = GEN6_BSD_RING_CTL,
956 .head = GEN6_BSD_RING_HEAD,
957 .tail = GEN6_BSD_RING_TAIL,
958 .start = GEN6_BSD_RING_START
959 },
960 .size = 32 * PAGE_SIZE,
961 .alignment = PAGE_SIZE,
962 .virtual_start = NULL,
963 .dev = NULL,
964 .gem_object = NULL,
965 .head = 0,
966 .tail = 0,
967 .space = 0,
968 .user_irq_refcount = 0,
969 .irq_gem_seqno = 0,
970 .waiting_gem_seqno = 0,
971 .setup_status_page = gen6_bsd_setup_status_page,
972 .init = init_bsd_ring,
973 .get_head = gen6_bsd_ring_get_head,
974 .get_tail = gen6_bsd_ring_get_tail,
975 .set_tail = gen6_bsd_ring_set_tail,
976 .get_active_head = gen6_bsd_ring_get_active_head,
977 .flush = gen6_bsd_ring_flush,
978 .add_request = bsd_ring_add_request,
979 .get_gem_seqno = bsd_ring_get_gem_seqno,
980 .user_irq_get = bsd_ring_get_user_irq,
981 .user_irq_put = bsd_ring_put_user_irq,
982 .dispatch_gem_execbuffer = gen6_bsd_ring_dispatch_gem_execbuffer,
983 .status_page = {NULL, 0, NULL},
984 .map = {0,}
985};
986
5c1143bb
XH		 987int intel_init_render_ring_buffer(struct drm_device *dev)
988{
989 drm_i915_private_t *dev_priv = dev->dev_private;
990
991 dev_priv->render_ring = render_ring;
992
993 if (!I915_NEED_GFX_HWS(dev)) {
994 dev_priv->render_ring.status_page.page_addr
995 = dev_priv->status_page_dmah->vaddr;
996 memset(dev_priv->render_ring.status_page.page_addr,
997 0, PAGE_SIZE);
998 }
999
1000 return intel_init_ring_buffer(dev, &dev_priv->render_ring);
1001}
1002
1003int intel_init_bsd_ring_buffer(struct drm_device *dev)
1004{
1005 drm_i915_private_t *dev_priv = dev->dev_private;
1006
881f47b6
XH		 1007 if (IS_GEN6(dev))
1008 dev_priv->bsd_ring = gen6_bsd_ring;
1009 else
1010 dev_priv->bsd_ring = bsd_ring;
5c1143bb
XH		 1011
1012 return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
1013}
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