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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
c7dca47b CW |
36 | static inline int ring_space(struct intel_ring_buffer *ring) |
37 | { | |
633cf8f5 | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
39 | if (space < 0) |
40 | space += ring->size; | |
41 | return space; | |
42 | } | |
43 | ||
09246732 CW |
44 | void __intel_ring_advance(struct intel_ring_buffer *ring) |
45 | { | |
46 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
47 | ||
48 | ring->tail &= ring->size - 1; | |
49 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) | |
50 | return; | |
51 | ring->write_tail(ring, ring->tail); | |
52 | } | |
53 | ||
b72f3acb | 54 | static int |
46f0f8d1 CW |
55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
56 | u32 invalidate_domains, | |
57 | u32 flush_domains) | |
58 | { | |
59 | u32 cmd; | |
60 | int ret; | |
61 | ||
62 | cmd = MI_FLUSH; | |
31b14c9f | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
64 | cmd |= MI_NO_WRITE_FLUSH; |
65 | ||
66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
67 | cmd |= MI_READ_FLUSH; | |
68 | ||
69 | ret = intel_ring_begin(ring, 2); | |
70 | if (ret) | |
71 | return ret; | |
72 | ||
73 | intel_ring_emit(ring, cmd); | |
74 | intel_ring_emit(ring, MI_NOOP); | |
75 | intel_ring_advance(ring); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int | |
81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
82 | u32 invalidate_domains, | |
83 | u32 flush_domains) | |
62fdfeaf | 84 | { |
78501eac | 85 | struct drm_device *dev = ring->dev; |
6f392d54 | 86 | u32 cmd; |
b72f3acb | 87 | int ret; |
6f392d54 | 88 | |
36d527de CW |
89 | /* |
90 | * read/write caches: | |
91 | * | |
92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
94 | * also flushed at 2d versus 3d pipeline switches. | |
95 | * | |
96 | * read-only caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
99 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
100 | * | |
101 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
102 | * | |
103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
104 | * invalidated when MI_EXE_FLUSH is set. | |
105 | * | |
106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
107 | * invalidated with every MI_FLUSH. | |
108 | * | |
109 | * TLBs: | |
110 | * | |
111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
114 | * are flushed at any MI_FLUSH. | |
115 | */ | |
116 | ||
117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
121 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 122 | |
36d527de CW |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
124 | (IS_G4X(dev) || IS_GEN5(dev))) | |
125 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 126 | |
36d527de CW |
127 | ret = intel_ring_begin(ring, 2); |
128 | if (ret) | |
129 | return ret; | |
b72f3acb | 130 | |
36d527de CW |
131 | intel_ring_emit(ring, cmd); |
132 | intel_ring_emit(ring, MI_NOOP); | |
133 | intel_ring_advance(ring); | |
b72f3acb CW |
134 | |
135 | return 0; | |
8187a2b7 ZN |
136 | } |
137 | ||
8d315287 JB |
138 | /** |
139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
140 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
142 | * | |
143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
144 | * produced by non-pipelined state commands), software needs to first | |
145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
146 | * 0. | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
150 | * | |
151 | * And the workaround for these two requires this workaround first: | |
152 | * | |
153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
154 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
155 | * flushes. | |
156 | * | |
157 | * And this last workaround is tricky because of the requirements on | |
158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
159 | * volume 2 part 1: | |
160 | * | |
161 | * "1 of the following must also be set: | |
162 | * - Render Target Cache Flush Enable ([12] of DW1) | |
163 | * - Depth Cache Flush Enable ([0] of DW1) | |
164 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
165 | * - Depth Stall ([13] of DW1) | |
166 | * - Post-Sync Operation ([13] of DW1) | |
167 | * - Notify Enable ([8] of DW1)" | |
168 | * | |
169 | * The cache flushes require the workaround flush that triggered this | |
170 | * one, so we can't use it. Depth stall would trigger the same. | |
171 | * Post-sync nonzero is what triggered this second workaround, so we | |
172 | * can't use that one either. Notify enable is IRQs, which aren't | |
173 | * really our business. That leaves only stall at scoreboard. | |
174 | */ | |
175 | static int | |
176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
177 | { | |
0d1aacac | 178 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
179 | int ret; |
180 | ||
181 | ||
182 | ret = intel_ring_begin(ring, 6); | |
183 | if (ret) | |
184 | return ret; | |
185 | ||
186 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
187 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
188 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
189 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
190 | intel_ring_emit(ring, 0); /* low dword */ | |
191 | intel_ring_emit(ring, 0); /* high dword */ | |
192 | intel_ring_emit(ring, MI_NOOP); | |
193 | intel_ring_advance(ring); | |
194 | ||
195 | ret = intel_ring_begin(ring, 6); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
200 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
201 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
202 | intel_ring_emit(ring, 0); | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, MI_NOOP); | |
205 | intel_ring_advance(ring); | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static int | |
211 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
212 | u32 invalidate_domains, u32 flush_domains) | |
213 | { | |
214 | u32 flags = 0; | |
0d1aacac | 215 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
216 | int ret; |
217 | ||
b3111509 PZ |
218 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
219 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
220 | if (ret) | |
221 | return ret; | |
222 | ||
8d315287 JB |
223 | /* Just flush everything. Experiments have shown that reducing the |
224 | * number of bits based on the write domains has little performance | |
225 | * impact. | |
226 | */ | |
7d54a904 CW |
227 | if (flush_domains) { |
228 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
229 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
230 | /* | |
231 | * Ensure that any following seqno writes only happen | |
232 | * when the render cache is indeed flushed. | |
233 | */ | |
97f209bc | 234 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
235 | } |
236 | if (invalidate_domains) { | |
237 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
238 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
239 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
243 | /* | |
244 | * TLB invalidate requires a post-sync write. | |
245 | */ | |
3ac78313 | 246 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 247 | } |
8d315287 | 248 | |
6c6cf5aa | 249 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
250 | if (ret) |
251 | return ret; | |
252 | ||
6c6cf5aa | 253 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
254 | intel_ring_emit(ring, flags); |
255 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 256 | intel_ring_emit(ring, 0); |
8d315287 JB |
257 | intel_ring_advance(ring); |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
f3987631 PZ |
262 | static int |
263 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
264 | { | |
265 | int ret; | |
266 | ||
267 | ret = intel_ring_begin(ring, 4); | |
268 | if (ret) | |
269 | return ret; | |
270 | ||
271 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
272 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
273 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
274 | intel_ring_emit(ring, 0); | |
275 | intel_ring_emit(ring, 0); | |
276 | intel_ring_advance(ring); | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
fd3da6c9 RV |
281 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
282 | { | |
283 | int ret; | |
284 | ||
285 | if (!ring->fbc_dirty) | |
286 | return 0; | |
287 | ||
288 | ret = intel_ring_begin(ring, 4); | |
289 | if (ret) | |
290 | return ret; | |
291 | intel_ring_emit(ring, MI_NOOP); | |
292 | /* WaFbcNukeOn3DBlt:ivb/hsw */ | |
293 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
294 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
295 | intel_ring_emit(ring, value); | |
296 | intel_ring_advance(ring); | |
297 | ||
298 | ring->fbc_dirty = false; | |
299 | return 0; | |
300 | } | |
301 | ||
4772eaeb PZ |
302 | static int |
303 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
304 | u32 invalidate_domains, u32 flush_domains) | |
305 | { | |
306 | u32 flags = 0; | |
0d1aacac | 307 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
4772eaeb PZ |
308 | int ret; |
309 | ||
f3987631 PZ |
310 | /* |
311 | * Ensure that any following seqno writes only happen when the render | |
312 | * cache is indeed flushed. | |
313 | * | |
314 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
315 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
316 | * don't try to be clever and just set it unconditionally. | |
317 | */ | |
318 | flags |= PIPE_CONTROL_CS_STALL; | |
319 | ||
4772eaeb PZ |
320 | /* Just flush everything. Experiments have shown that reducing the |
321 | * number of bits based on the write domains has little performance | |
322 | * impact. | |
323 | */ | |
324 | if (flush_domains) { | |
325 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
326 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
327 | } |
328 | if (invalidate_domains) { | |
329 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
330 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
331 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
332 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
333 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
334 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
335 | /* | |
336 | * TLB invalidate requires a post-sync write. | |
337 | */ | |
338 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 339 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
340 | |
341 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
342 | * set before a pipe_control command that has the state cache | |
343 | * invalidate bit set. */ | |
344 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
345 | } |
346 | ||
347 | ret = intel_ring_begin(ring, 4); | |
348 | if (ret) | |
349 | return ret; | |
350 | ||
351 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
352 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 353 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
354 | intel_ring_emit(ring, 0); |
355 | intel_ring_advance(ring); | |
356 | ||
fd3da6c9 RV |
357 | if (flush_domains) |
358 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
359 | ||
4772eaeb PZ |
360 | return 0; |
361 | } | |
362 | ||
78501eac | 363 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 364 | u32 value) |
d46eefa2 | 365 | { |
78501eac | 366 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 367 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
368 | } |
369 | ||
78501eac | 370 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 371 | { |
78501eac CW |
372 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
373 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 374 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
375 | |
376 | return I915_READ(acthd_reg); | |
377 | } | |
378 | ||
035dc1e0 DV |
379 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
380 | { | |
381 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
382 | u32 addr; | |
383 | ||
384 | addr = dev_priv->status_page_dmah->busaddr; | |
385 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
386 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
387 | I915_WRITE(HWS_PGA, addr); | |
388 | } | |
389 | ||
78501eac | 390 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 391 | { |
b7884eb4 DV |
392 | struct drm_device *dev = ring->dev; |
393 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 394 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 395 | int ret = 0; |
8187a2b7 | 396 | u32 head; |
8187a2b7 | 397 | |
ab484f8f | 398 | gen6_gt_force_wake_get(dev_priv); |
b7884eb4 | 399 | |
035dc1e0 DV |
400 | if (I915_NEED_GFX_HWS(dev)) |
401 | intel_ring_setup_status_page(ring); | |
402 | else | |
403 | ring_setup_phys_status_page(ring); | |
404 | ||
8187a2b7 | 405 | /* Stop the ring if it's running. */ |
7f2ab699 | 406 | I915_WRITE_CTL(ring, 0); |
570ef608 | 407 | I915_WRITE_HEAD(ring, 0); |
78501eac | 408 | ring->write_tail(ring, 0); |
8187a2b7 | 409 | |
570ef608 | 410 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
411 | |
412 | /* G45 ring initialization fails to reset head to zero */ | |
413 | if (head != 0) { | |
6fd0d56e CW |
414 | DRM_DEBUG_KMS("%s head not reset to zero " |
415 | "ctl %08x head %08x tail %08x start %08x\n", | |
416 | ring->name, | |
417 | I915_READ_CTL(ring), | |
418 | I915_READ_HEAD(ring), | |
419 | I915_READ_TAIL(ring), | |
420 | I915_READ_START(ring)); | |
8187a2b7 | 421 | |
570ef608 | 422 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 423 | |
6fd0d56e CW |
424 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
425 | DRM_ERROR("failed to set %s head to zero " | |
426 | "ctl %08x head %08x tail %08x start %08x\n", | |
427 | ring->name, | |
428 | I915_READ_CTL(ring), | |
429 | I915_READ_HEAD(ring), | |
430 | I915_READ_TAIL(ring), | |
431 | I915_READ_START(ring)); | |
432 | } | |
8187a2b7 ZN |
433 | } |
434 | ||
0d8957c8 DV |
435 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
436 | * registers with the above sequence (the readback of the HEAD registers | |
437 | * also enforces ordering), otherwise the hw might lose the new ring | |
438 | * register values. */ | |
f343c5f6 | 439 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 440 | I915_WRITE_CTL(ring, |
ae69b42a | 441 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 442 | | RING_VALID); |
8187a2b7 | 443 | |
8187a2b7 | 444 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 445 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 446 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 447 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
448 | DRM_ERROR("%s initialization failed " |
449 | "ctl %08x head %08x tail %08x start %08x\n", | |
450 | ring->name, | |
451 | I915_READ_CTL(ring), | |
452 | I915_READ_HEAD(ring), | |
453 | I915_READ_TAIL(ring), | |
454 | I915_READ_START(ring)); | |
b7884eb4 DV |
455 | ret = -EIO; |
456 | goto out; | |
8187a2b7 ZN |
457 | } |
458 | ||
78501eac CW |
459 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
460 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 461 | else { |
c7dca47b | 462 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 463 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 464 | ring->space = ring_space(ring); |
c3b20037 | 465 | ring->last_retired_head = -1; |
8187a2b7 | 466 | } |
1ec14ad3 | 467 | |
50f018df CW |
468 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
469 | ||
b7884eb4 | 470 | out: |
ab484f8f | 471 | gen6_gt_force_wake_put(dev_priv); |
b7884eb4 DV |
472 | |
473 | return ret; | |
8187a2b7 ZN |
474 | } |
475 | ||
c6df541c CW |
476 | static int |
477 | init_pipe_control(struct intel_ring_buffer *ring) | |
478 | { | |
c6df541c CW |
479 | int ret; |
480 | ||
0d1aacac | 481 | if (ring->scratch.obj) |
c6df541c CW |
482 | return 0; |
483 | ||
0d1aacac CW |
484 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
485 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
486 | DRM_ERROR("Failed to allocate seqno page\n"); |
487 | ret = -ENOMEM; | |
488 | goto err; | |
489 | } | |
e4ffd173 | 490 | |
0d1aacac | 491 | i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
c6df541c | 492 | |
0d1aacac | 493 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); |
c6df541c CW |
494 | if (ret) |
495 | goto err_unref; | |
496 | ||
0d1aacac CW |
497 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
498 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
499 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 500 | ret = -ENOMEM; |
c6df541c | 501 | goto err_unpin; |
56b085a0 | 502 | } |
c6df541c | 503 | |
2b1086cc | 504 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 505 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
506 | return 0; |
507 | ||
508 | err_unpin: | |
0d1aacac | 509 | i915_gem_object_unpin(ring->scratch.obj); |
c6df541c | 510 | err_unref: |
0d1aacac | 511 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 512 | err: |
c6df541c CW |
513 | return ret; |
514 | } | |
515 | ||
78501eac | 516 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 517 | { |
78501eac | 518 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 519 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 520 | int ret = init_ring_common(ring); |
a69ffdbf | 521 | |
1c8c38c5 | 522 | if (INTEL_INFO(dev)->gen > 3) |
6b26c86d | 523 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
524 | |
525 | /* We need to disable the AsyncFlip performance optimisations in order | |
526 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
527 | * programmed to '1' on all products. | |
8693a824 DL |
528 | * |
529 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv | |
1c8c38c5 CW |
530 | */ |
531 | if (INTEL_INFO(dev)->gen >= 6) | |
532 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
533 | ||
f05bb0c7 CW |
534 | /* Required for the hardware to program scanline values for waiting */ |
535 | if (INTEL_INFO(dev)->gen == 6) | |
536 | I915_WRITE(GFX_MODE, | |
537 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); | |
538 | ||
1c8c38c5 CW |
539 | if (IS_GEN7(dev)) |
540 | I915_WRITE(GFX_MODE_GEN7, | |
541 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
542 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
78501eac | 543 | |
8d315287 | 544 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
545 | ret = init_pipe_control(ring); |
546 | if (ret) | |
547 | return ret; | |
548 | } | |
549 | ||
5e13a0c5 | 550 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
551 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
552 | * "If this bit is set, STCunit will have LRA as replacement | |
553 | * policy. [...] This bit must be reset. LRA replacement | |
554 | * policy is not supported." | |
555 | */ | |
556 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 557 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
558 | |
559 | /* This is not explicitly set for GEN6, so read the register. | |
560 | * see intel_ring_mi_set_context() for why we care. | |
561 | * TODO: consider explicitly setting the bit for GEN5 | |
562 | */ | |
563 | ring->itlb_before_ctx_switch = | |
564 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
565 | } |
566 | ||
6b26c86d DV |
567 | if (INTEL_INFO(dev)->gen >= 6) |
568 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 569 | |
040d2baa | 570 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 571 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 572 | |
8187a2b7 ZN |
573 | return ret; |
574 | } | |
575 | ||
c6df541c CW |
576 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
577 | { | |
b45305fc DV |
578 | struct drm_device *dev = ring->dev; |
579 | ||
0d1aacac | 580 | if (ring->scratch.obj == NULL) |
c6df541c CW |
581 | return; |
582 | ||
0d1aacac CW |
583 | if (INTEL_INFO(dev)->gen >= 5) { |
584 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
585 | i915_gem_object_unpin(ring->scratch.obj); | |
586 | } | |
aaf8a516 | 587 | |
0d1aacac CW |
588 | drm_gem_object_unreference(&ring->scratch.obj->base); |
589 | ring->scratch.obj = NULL; | |
c6df541c CW |
590 | } |
591 | ||
1ec14ad3 | 592 | static void |
c8c99b0f | 593 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 594 | u32 mmio_offset) |
1ec14ad3 | 595 | { |
ad776f8b BW |
596 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
597 | * of rings, it's easiest if we round up each individual update to a | |
598 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
599 | * even though the actual update only requires 3 dwords. | |
600 | */ | |
601 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 602 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 603 | intel_ring_emit(ring, mmio_offset); |
1823521d | 604 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 605 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
606 | } |
607 | ||
c8c99b0f BW |
608 | /** |
609 | * gen6_add_request - Update the semaphore mailbox registers | |
610 | * | |
611 | * @ring - ring that is adding a request | |
612 | * @seqno - return seqno stuck into the ring | |
613 | * | |
614 | * Update the mailbox registers in the *other* rings with the current seqno. | |
615 | * This acts like a signal in the canonical semaphore. | |
616 | */ | |
1ec14ad3 | 617 | static int |
9d773091 | 618 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 619 | { |
ad776f8b BW |
620 | struct drm_device *dev = ring->dev; |
621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
622 | struct intel_ring_buffer *useless; | |
623 | int i, ret; | |
1ec14ad3 | 624 | |
ad776f8b BW |
625 | ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) * |
626 | MBOX_UPDATE_DWORDS) + | |
627 | 4); | |
1ec14ad3 CW |
628 | if (ret) |
629 | return ret; | |
ad776f8b | 630 | #undef MBOX_UPDATE_DWORDS |
1ec14ad3 | 631 | |
ad776f8b BW |
632 | for_each_ring(useless, dev_priv, i) { |
633 | u32 mbox_reg = ring->signal_mbox[i]; | |
634 | if (mbox_reg != GEN6_NOSYNC) | |
635 | update_mboxes(ring, mbox_reg); | |
636 | } | |
1ec14ad3 CW |
637 | |
638 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
639 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 640 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 641 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 642 | __intel_ring_advance(ring); |
1ec14ad3 | 643 | |
1ec14ad3 CW |
644 | return 0; |
645 | } | |
646 | ||
f72b3435 MK |
647 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
648 | u32 seqno) | |
649 | { | |
650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
651 | return dev_priv->last_seqno < seqno; | |
652 | } | |
653 | ||
c8c99b0f BW |
654 | /** |
655 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
656 | * | |
657 | * @waiter - ring that is waiting | |
658 | * @signaller - ring which has, or will signal | |
659 | * @seqno - seqno which the waiter will block on | |
660 | */ | |
661 | static int | |
686cb5f9 DV |
662 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
663 | struct intel_ring_buffer *signaller, | |
664 | u32 seqno) | |
1ec14ad3 CW |
665 | { |
666 | int ret; | |
c8c99b0f BW |
667 | u32 dw1 = MI_SEMAPHORE_MBOX | |
668 | MI_SEMAPHORE_COMPARE | | |
669 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 670 | |
1500f7ea BW |
671 | /* Throughout all of the GEM code, seqno passed implies our current |
672 | * seqno is >= the last seqno executed. However for hardware the | |
673 | * comparison is strictly greater than. | |
674 | */ | |
675 | seqno -= 1; | |
676 | ||
686cb5f9 DV |
677 | WARN_ON(signaller->semaphore_register[waiter->id] == |
678 | MI_SEMAPHORE_SYNC_INVALID); | |
679 | ||
c8c99b0f | 680 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
681 | if (ret) |
682 | return ret; | |
683 | ||
f72b3435 MK |
684 | /* If seqno wrap happened, omit the wait with no-ops */ |
685 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
686 | intel_ring_emit(waiter, | |
687 | dw1 | | |
688 | signaller->semaphore_register[waiter->id]); | |
689 | intel_ring_emit(waiter, seqno); | |
690 | intel_ring_emit(waiter, 0); | |
691 | intel_ring_emit(waiter, MI_NOOP); | |
692 | } else { | |
693 | intel_ring_emit(waiter, MI_NOOP); | |
694 | intel_ring_emit(waiter, MI_NOOP); | |
695 | intel_ring_emit(waiter, MI_NOOP); | |
696 | intel_ring_emit(waiter, MI_NOOP); | |
697 | } | |
c8c99b0f | 698 | intel_ring_advance(waiter); |
1ec14ad3 CW |
699 | |
700 | return 0; | |
701 | } | |
702 | ||
c6df541c CW |
703 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
704 | do { \ | |
fcbc34e4 KG |
705 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
706 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
707 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
708 | intel_ring_emit(ring__, 0); \ | |
709 | intel_ring_emit(ring__, 0); \ | |
710 | } while (0) | |
711 | ||
712 | static int | |
9d773091 | 713 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 714 | { |
0d1aacac | 715 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
c6df541c CW |
716 | int ret; |
717 | ||
718 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
719 | * incoherent with writes to memory, i.e. completely fubar, | |
720 | * so we need to use PIPE_NOTIFY instead. | |
721 | * | |
722 | * However, we also need to workaround the qword write | |
723 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
724 | * memory before requesting an interrupt. | |
725 | */ | |
726 | ret = intel_ring_begin(ring, 32); | |
727 | if (ret) | |
728 | return ret; | |
729 | ||
fcbc34e4 | 730 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
731 | PIPE_CONTROL_WRITE_FLUSH | |
732 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 733 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 734 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
735 | intel_ring_emit(ring, 0); |
736 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
737 | scratch_addr += 128; /* write to separate cachelines */ | |
738 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
739 | scratch_addr += 128; | |
740 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
741 | scratch_addr += 128; | |
742 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
743 | scratch_addr += 128; | |
744 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
745 | scratch_addr += 128; | |
746 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 747 | |
fcbc34e4 | 748 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
749 | PIPE_CONTROL_WRITE_FLUSH | |
750 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 751 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 752 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 753 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 754 | intel_ring_emit(ring, 0); |
09246732 | 755 | __intel_ring_advance(ring); |
c6df541c | 756 | |
c6df541c CW |
757 | return 0; |
758 | } | |
759 | ||
4cd53c0c | 760 | static u32 |
b2eadbc8 | 761 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 762 | { |
4cd53c0c DV |
763 | /* Workaround to force correct ordering between irq and seqno writes on |
764 | * ivb (and maybe also on snb) by reading from a CS register (like | |
765 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 766 | if (!lazy_coherency) |
4cd53c0c DV |
767 | intel_ring_get_active_head(ring); |
768 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
769 | } | |
770 | ||
8187a2b7 | 771 | static u32 |
b2eadbc8 | 772 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 773 | { |
1ec14ad3 CW |
774 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
775 | } | |
776 | ||
b70ec5bf MK |
777 | static void |
778 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
779 | { | |
780 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
781 | } | |
782 | ||
c6df541c | 783 | static u32 |
b2eadbc8 | 784 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 785 | { |
0d1aacac | 786 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
787 | } |
788 | ||
b70ec5bf MK |
789 | static void |
790 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
791 | { | |
0d1aacac | 792 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
793 | } |
794 | ||
e48d8634 DV |
795 | static bool |
796 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
797 | { | |
798 | struct drm_device *dev = ring->dev; | |
799 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 800 | unsigned long flags; |
e48d8634 DV |
801 | |
802 | if (!dev->irq_enabled) | |
803 | return false; | |
804 | ||
7338aefa | 805 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
806 | if (ring->irq_refcount++ == 0) |
807 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 808 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
809 | |
810 | return true; | |
811 | } | |
812 | ||
813 | static void | |
814 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
815 | { | |
816 | struct drm_device *dev = ring->dev; | |
817 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 818 | unsigned long flags; |
e48d8634 | 819 | |
7338aefa | 820 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
821 | if (--ring->irq_refcount == 0) |
822 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 823 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
824 | } |
825 | ||
b13c2b96 | 826 | static bool |
e3670319 | 827 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 828 | { |
78501eac | 829 | struct drm_device *dev = ring->dev; |
01a03331 | 830 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 831 | unsigned long flags; |
62fdfeaf | 832 | |
b13c2b96 CW |
833 | if (!dev->irq_enabled) |
834 | return false; | |
835 | ||
7338aefa | 836 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 837 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
838 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
839 | I915_WRITE(IMR, dev_priv->irq_mask); | |
840 | POSTING_READ(IMR); | |
841 | } | |
7338aefa | 842 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
843 | |
844 | return true; | |
62fdfeaf EA |
845 | } |
846 | ||
8187a2b7 | 847 | static void |
e3670319 | 848 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 849 | { |
78501eac | 850 | struct drm_device *dev = ring->dev; |
01a03331 | 851 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 852 | unsigned long flags; |
62fdfeaf | 853 | |
7338aefa | 854 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 855 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
856 | dev_priv->irq_mask |= ring->irq_enable_mask; |
857 | I915_WRITE(IMR, dev_priv->irq_mask); | |
858 | POSTING_READ(IMR); | |
859 | } | |
7338aefa | 860 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
861 | } |
862 | ||
c2798b19 CW |
863 | static bool |
864 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
865 | { | |
866 | struct drm_device *dev = ring->dev; | |
867 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 868 | unsigned long flags; |
c2798b19 CW |
869 | |
870 | if (!dev->irq_enabled) | |
871 | return false; | |
872 | ||
7338aefa | 873 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 874 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
875 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
876 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
877 | POSTING_READ16(IMR); | |
878 | } | |
7338aefa | 879 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
880 | |
881 | return true; | |
882 | } | |
883 | ||
884 | static void | |
885 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
886 | { | |
887 | struct drm_device *dev = ring->dev; | |
888 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 889 | unsigned long flags; |
c2798b19 | 890 | |
7338aefa | 891 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 892 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
893 | dev_priv->irq_mask |= ring->irq_enable_mask; |
894 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
895 | POSTING_READ16(IMR); | |
896 | } | |
7338aefa | 897 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
898 | } |
899 | ||
78501eac | 900 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 901 | { |
4593010b | 902 | struct drm_device *dev = ring->dev; |
78501eac | 903 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
904 | u32 mmio = 0; |
905 | ||
906 | /* The ring status page addresses are no longer next to the rest of | |
907 | * the ring registers as of gen7. | |
908 | */ | |
909 | if (IS_GEN7(dev)) { | |
910 | switch (ring->id) { | |
96154f2f | 911 | case RCS: |
4593010b EA |
912 | mmio = RENDER_HWS_PGA_GEN7; |
913 | break; | |
96154f2f | 914 | case BCS: |
4593010b EA |
915 | mmio = BLT_HWS_PGA_GEN7; |
916 | break; | |
96154f2f | 917 | case VCS: |
4593010b EA |
918 | mmio = BSD_HWS_PGA_GEN7; |
919 | break; | |
4a3dd19d | 920 | case VECS: |
9a8a2213 BW |
921 | mmio = VEBOX_HWS_PGA_GEN7; |
922 | break; | |
4593010b EA |
923 | } |
924 | } else if (IS_GEN6(ring->dev)) { | |
925 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
926 | } else { | |
927 | mmio = RING_HWS_PGA(ring->mmio_base); | |
928 | } | |
929 | ||
78501eac CW |
930 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
931 | POSTING_READ(mmio); | |
884020bf CW |
932 | |
933 | /* Flush the TLB for this page */ | |
934 | if (INTEL_INFO(dev)->gen >= 6) { | |
935 | u32 reg = RING_INSTPM(ring->mmio_base); | |
936 | I915_WRITE(reg, | |
937 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
938 | INSTPM_SYNC_FLUSH)); | |
939 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
940 | 1000)) | |
941 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
942 | ring->name); | |
943 | } | |
8187a2b7 ZN |
944 | } |
945 | ||
b72f3acb | 946 | static int |
78501eac CW |
947 | bsd_ring_flush(struct intel_ring_buffer *ring, |
948 | u32 invalidate_domains, | |
949 | u32 flush_domains) | |
d1b851fc | 950 | { |
b72f3acb CW |
951 | int ret; |
952 | ||
b72f3acb CW |
953 | ret = intel_ring_begin(ring, 2); |
954 | if (ret) | |
955 | return ret; | |
956 | ||
957 | intel_ring_emit(ring, MI_FLUSH); | |
958 | intel_ring_emit(ring, MI_NOOP); | |
959 | intel_ring_advance(ring); | |
960 | return 0; | |
d1b851fc ZN |
961 | } |
962 | ||
3cce469c | 963 | static int |
9d773091 | 964 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 965 | { |
3cce469c CW |
966 | int ret; |
967 | ||
968 | ret = intel_ring_begin(ring, 4); | |
969 | if (ret) | |
970 | return ret; | |
6f392d54 | 971 | |
3cce469c CW |
972 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
973 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 974 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 975 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 976 | __intel_ring_advance(ring); |
d1b851fc | 977 | |
3cce469c | 978 | return 0; |
d1b851fc ZN |
979 | } |
980 | ||
0f46832f | 981 | static bool |
25c06300 | 982 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
983 | { |
984 | struct drm_device *dev = ring->dev; | |
01a03331 | 985 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 986 | unsigned long flags; |
0f46832f CW |
987 | |
988 | if (!dev->irq_enabled) | |
989 | return false; | |
990 | ||
4cd53c0c DV |
991 | /* It looks like we need to prevent the gt from suspending while waiting |
992 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
993 | * blt/bsd rings on ivb. */ | |
99ffa162 | 994 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 995 | |
7338aefa | 996 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 997 | if (ring->irq_refcount++ == 0) { |
040d2baa | 998 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
999 | I915_WRITE_IMR(ring, |
1000 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1001 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1002 | else |
1003 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 1004 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1005 | } |
7338aefa | 1006 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1007 | |
1008 | return true; | |
1009 | } | |
1010 | ||
1011 | static void | |
25c06300 | 1012 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1013 | { |
1014 | struct drm_device *dev = ring->dev; | |
01a03331 | 1015 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1016 | unsigned long flags; |
0f46832f | 1017 | |
7338aefa | 1018 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1019 | if (--ring->irq_refcount == 0) { |
040d2baa | 1020 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1021 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1022 | else |
1023 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1024 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1025 | } |
7338aefa | 1026 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 1027 | |
99ffa162 | 1028 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
1029 | } |
1030 | ||
a19d2933 BW |
1031 | static bool |
1032 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1033 | { | |
1034 | struct drm_device *dev = ring->dev; | |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | unsigned long flags; | |
1037 | ||
1038 | if (!dev->irq_enabled) | |
1039 | return false; | |
1040 | ||
59cdb63d | 1041 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1042 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1043 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1044 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1045 | } |
59cdb63d | 1046 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1047 | |
1048 | return true; | |
1049 | } | |
1050 | ||
1051 | static void | |
1052 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1053 | { | |
1054 | struct drm_device *dev = ring->dev; | |
1055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1056 | unsigned long flags; | |
1057 | ||
1058 | if (!dev->irq_enabled) | |
1059 | return; | |
1060 | ||
59cdb63d | 1061 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1062 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1063 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1064 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1065 | } |
59cdb63d | 1066 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1067 | } |
1068 | ||
abd58f01 BW |
1069 | static bool |
1070 | gen8_ring_get_irq(struct intel_ring_buffer *ring) | |
1071 | { | |
1072 | struct drm_device *dev = ring->dev; | |
1073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1074 | unsigned long flags; | |
1075 | ||
1076 | if (!dev->irq_enabled) | |
1077 | return false; | |
1078 | ||
1079 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1080 | if (ring->irq_refcount++ == 0) { | |
1081 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1082 | I915_WRITE_IMR(ring, | |
1083 | ~(ring->irq_enable_mask | | |
1084 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1085 | } else { | |
1086 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1087 | } | |
1088 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1089 | } | |
1090 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1091 | ||
1092 | return true; | |
1093 | } | |
1094 | ||
1095 | static void | |
1096 | gen8_ring_put_irq(struct intel_ring_buffer *ring) | |
1097 | { | |
1098 | struct drm_device *dev = ring->dev; | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1100 | unsigned long flags; | |
1101 | ||
1102 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1103 | if (--ring->irq_refcount == 0) { | |
1104 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1105 | I915_WRITE_IMR(ring, | |
1106 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1107 | } else { | |
1108 | I915_WRITE_IMR(ring, ~0); | |
1109 | } | |
1110 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1111 | } | |
1112 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1113 | } | |
1114 | ||
d1b851fc | 1115 | static int |
d7d4eedd CW |
1116 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1117 | u32 offset, u32 length, | |
1118 | unsigned flags) | |
d1b851fc | 1119 | { |
e1f99ce6 | 1120 | int ret; |
78501eac | 1121 | |
e1f99ce6 CW |
1122 | ret = intel_ring_begin(ring, 2); |
1123 | if (ret) | |
1124 | return ret; | |
1125 | ||
78501eac | 1126 | intel_ring_emit(ring, |
65f56876 CW |
1127 | MI_BATCH_BUFFER_START | |
1128 | MI_BATCH_GTT | | |
d7d4eedd | 1129 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1130 | intel_ring_emit(ring, offset); |
78501eac CW |
1131 | intel_ring_advance(ring); |
1132 | ||
d1b851fc ZN |
1133 | return 0; |
1134 | } | |
1135 | ||
b45305fc DV |
1136 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1137 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1138 | static int |
fb3256da | 1139 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1140 | u32 offset, u32 len, |
1141 | unsigned flags) | |
62fdfeaf | 1142 | { |
c4e7a414 | 1143 | int ret; |
62fdfeaf | 1144 | |
b45305fc DV |
1145 | if (flags & I915_DISPATCH_PINNED) { |
1146 | ret = intel_ring_begin(ring, 4); | |
1147 | if (ret) | |
1148 | return ret; | |
62fdfeaf | 1149 | |
b45305fc DV |
1150 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1151 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1152 | intel_ring_emit(ring, offset + len - 8); | |
1153 | intel_ring_emit(ring, MI_NOOP); | |
1154 | intel_ring_advance(ring); | |
1155 | } else { | |
0d1aacac | 1156 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1157 | |
1158 | if (len > I830_BATCH_LIMIT) | |
1159 | return -ENOSPC; | |
1160 | ||
1161 | ret = intel_ring_begin(ring, 9+3); | |
1162 | if (ret) | |
1163 | return ret; | |
1164 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1165 | * scratch bo area (so that the CS never stumbles over its tlb | |
1166 | * invalidation bug) ... */ | |
1167 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1168 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1169 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1170 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1171 | intel_ring_emit(ring, 0); | |
1172 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1173 | intel_ring_emit(ring, cs_offset); | |
1174 | intel_ring_emit(ring, 0); | |
1175 | intel_ring_emit(ring, 4096); | |
1176 | intel_ring_emit(ring, offset); | |
1177 | intel_ring_emit(ring, MI_FLUSH); | |
1178 | ||
1179 | /* ... and execute it. */ | |
1180 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1181 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1182 | intel_ring_emit(ring, cs_offset + len - 8); | |
1183 | intel_ring_advance(ring); | |
1184 | } | |
e1f99ce6 | 1185 | |
fb3256da DV |
1186 | return 0; |
1187 | } | |
1188 | ||
1189 | static int | |
1190 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1191 | u32 offset, u32 len, |
1192 | unsigned flags) | |
fb3256da DV |
1193 | { |
1194 | int ret; | |
1195 | ||
1196 | ret = intel_ring_begin(ring, 2); | |
1197 | if (ret) | |
1198 | return ret; | |
1199 | ||
65f56876 | 1200 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1201 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1202 | intel_ring_advance(ring); |
62fdfeaf | 1203 | |
62fdfeaf EA |
1204 | return 0; |
1205 | } | |
1206 | ||
78501eac | 1207 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1208 | { |
05394f39 | 1209 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1210 | |
8187a2b7 ZN |
1211 | obj = ring->status_page.obj; |
1212 | if (obj == NULL) | |
62fdfeaf | 1213 | return; |
62fdfeaf | 1214 | |
9da3da66 | 1215 | kunmap(sg_page(obj->pages->sgl)); |
62fdfeaf | 1216 | i915_gem_object_unpin(obj); |
05394f39 | 1217 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1218 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1219 | } |
1220 | ||
78501eac | 1221 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1222 | { |
78501eac | 1223 | struct drm_device *dev = ring->dev; |
05394f39 | 1224 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1225 | int ret; |
1226 | ||
62fdfeaf EA |
1227 | obj = i915_gem_alloc_object(dev, 4096); |
1228 | if (obj == NULL) { | |
1229 | DRM_ERROR("Failed to allocate status page\n"); | |
1230 | ret = -ENOMEM; | |
1231 | goto err; | |
1232 | } | |
e4ffd173 CW |
1233 | |
1234 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1235 | |
c37e2204 | 1236 | ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); |
62fdfeaf | 1237 | if (ret != 0) { |
62fdfeaf EA |
1238 | goto err_unref; |
1239 | } | |
1240 | ||
f343c5f6 | 1241 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1242 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1243 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1244 | ret = -ENOMEM; |
62fdfeaf EA |
1245 | goto err_unpin; |
1246 | } | |
8187a2b7 ZN |
1247 | ring->status_page.obj = obj; |
1248 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1249 | |
8187a2b7 ZN |
1250 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1251 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1252 | |
1253 | return 0; | |
1254 | ||
1255 | err_unpin: | |
1256 | i915_gem_object_unpin(obj); | |
1257 | err_unref: | |
05394f39 | 1258 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1259 | err: |
8187a2b7 | 1260 | return ret; |
62fdfeaf EA |
1261 | } |
1262 | ||
035dc1e0 | 1263 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1264 | { |
1265 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1266 | |
1267 | if (!dev_priv->status_page_dmah) { | |
1268 | dev_priv->status_page_dmah = | |
1269 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1270 | if (!dev_priv->status_page_dmah) | |
1271 | return -ENOMEM; | |
1272 | } | |
1273 | ||
6b8294a4 CW |
1274 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1275 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1276 | ||
1277 | return 0; | |
1278 | } | |
1279 | ||
c43b5634 BW |
1280 | static int intel_init_ring_buffer(struct drm_device *dev, |
1281 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1282 | { |
05394f39 | 1283 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1284 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1285 | int ret; |
1286 | ||
8187a2b7 | 1287 | ring->dev = dev; |
23bc5982 CW |
1288 | INIT_LIST_HEAD(&ring->active_list); |
1289 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1290 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1291 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1292 | |
b259f673 | 1293 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1294 | |
8187a2b7 | 1295 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1296 | ret = init_status_page(ring); |
8187a2b7 ZN |
1297 | if (ret) |
1298 | return ret; | |
6b8294a4 CW |
1299 | } else { |
1300 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1301 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1302 | if (ret) |
1303 | return ret; | |
8187a2b7 | 1304 | } |
62fdfeaf | 1305 | |
ebc052e0 CW |
1306 | obj = NULL; |
1307 | if (!HAS_LLC(dev)) | |
1308 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1309 | if (obj == NULL) | |
1310 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1311 | if (obj == NULL) { |
1312 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1313 | ret = -ENOMEM; |
dd785e35 | 1314 | goto err_hws; |
62fdfeaf | 1315 | } |
62fdfeaf | 1316 | |
05394f39 | 1317 | ring->obj = obj; |
8187a2b7 | 1318 | |
c37e2204 | 1319 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1320 | if (ret) |
1321 | goto err_unref; | |
62fdfeaf | 1322 | |
3eef8918 CW |
1323 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1324 | if (ret) | |
1325 | goto err_unpin; | |
1326 | ||
dd2757f8 | 1327 | ring->virtual_start = |
f343c5f6 | 1328 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1329 | ring->size); |
4225d0f2 | 1330 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1331 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1332 | ret = -EINVAL; |
dd785e35 | 1333 | goto err_unpin; |
62fdfeaf EA |
1334 | } |
1335 | ||
78501eac | 1336 | ret = ring->init(ring); |
dd785e35 CW |
1337 | if (ret) |
1338 | goto err_unmap; | |
62fdfeaf | 1339 | |
55249baa CW |
1340 | /* Workaround an erratum on the i830 which causes a hang if |
1341 | * the TAIL pointer points to within the last 2 cachelines | |
1342 | * of the buffer. | |
1343 | */ | |
1344 | ring->effective_size = ring->size; | |
27c1cbd0 | 1345 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1346 | ring->effective_size -= 128; |
1347 | ||
c584fe47 | 1348 | return 0; |
dd785e35 CW |
1349 | |
1350 | err_unmap: | |
4225d0f2 | 1351 | iounmap(ring->virtual_start); |
dd785e35 CW |
1352 | err_unpin: |
1353 | i915_gem_object_unpin(obj); | |
1354 | err_unref: | |
05394f39 CW |
1355 | drm_gem_object_unreference(&obj->base); |
1356 | ring->obj = NULL; | |
dd785e35 | 1357 | err_hws: |
78501eac | 1358 | cleanup_status_page(ring); |
8187a2b7 | 1359 | return ret; |
62fdfeaf EA |
1360 | } |
1361 | ||
78501eac | 1362 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1363 | { |
33626e6a CW |
1364 | struct drm_i915_private *dev_priv; |
1365 | int ret; | |
1366 | ||
05394f39 | 1367 | if (ring->obj == NULL) |
62fdfeaf EA |
1368 | return; |
1369 | ||
33626e6a CW |
1370 | /* Disable the ring buffer. The ring must be idle at this point */ |
1371 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1372 | ret = intel_ring_idle(ring); |
3d57e5bd | 1373 | if (ret && !i915_reset_in_progress(&dev_priv->gpu_error)) |
29ee3991 CW |
1374 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
1375 | ring->name, ret); | |
1376 | ||
33626e6a CW |
1377 | I915_WRITE_CTL(ring, 0); |
1378 | ||
4225d0f2 | 1379 | iounmap(ring->virtual_start); |
62fdfeaf | 1380 | |
05394f39 CW |
1381 | i915_gem_object_unpin(ring->obj); |
1382 | drm_gem_object_unreference(&ring->obj->base); | |
1383 | ring->obj = NULL; | |
3d57e5bd BW |
1384 | ring->preallocated_lazy_request = NULL; |
1385 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1386 | |
8d19215b ZN |
1387 | if (ring->cleanup) |
1388 | ring->cleanup(ring); | |
1389 | ||
78501eac | 1390 | cleanup_status_page(ring); |
62fdfeaf EA |
1391 | } |
1392 | ||
a71d8d94 CW |
1393 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1394 | { | |
a71d8d94 CW |
1395 | int ret; |
1396 | ||
199b2bc2 | 1397 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1398 | if (!ret) |
1399 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1400 | |
1401 | return ret; | |
1402 | } | |
1403 | ||
1404 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1405 | { | |
1406 | struct drm_i915_gem_request *request; | |
1407 | u32 seqno = 0; | |
1408 | int ret; | |
1409 | ||
1410 | i915_gem_retire_requests_ring(ring); | |
1411 | ||
1412 | if (ring->last_retired_head != -1) { | |
1413 | ring->head = ring->last_retired_head; | |
1414 | ring->last_retired_head = -1; | |
1415 | ring->space = ring_space(ring); | |
1416 | if (ring->space >= n) | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | list_for_each_entry(request, &ring->request_list, list) { | |
1421 | int space; | |
1422 | ||
1423 | if (request->tail == -1) | |
1424 | continue; | |
1425 | ||
633cf8f5 | 1426 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1427 | if (space < 0) |
1428 | space += ring->size; | |
1429 | if (space >= n) { | |
1430 | seqno = request->seqno; | |
1431 | break; | |
1432 | } | |
1433 | ||
1434 | /* Consume this request in case we need more space than | |
1435 | * is available and so need to prevent a race between | |
1436 | * updating last_retired_head and direct reads of | |
1437 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1438 | */ | |
1439 | request->tail = -1; | |
1440 | } | |
1441 | ||
1442 | if (seqno == 0) | |
1443 | return -ENOSPC; | |
1444 | ||
1445 | ret = intel_ring_wait_seqno(ring, seqno); | |
1446 | if (ret) | |
1447 | return ret; | |
1448 | ||
1449 | if (WARN_ON(ring->last_retired_head == -1)) | |
1450 | return -ENOSPC; | |
1451 | ||
1452 | ring->head = ring->last_retired_head; | |
1453 | ring->last_retired_head = -1; | |
1454 | ring->space = ring_space(ring); | |
1455 | if (WARN_ON(ring->space < n)) | |
1456 | return -ENOSPC; | |
1457 | ||
1458 | return 0; | |
1459 | } | |
1460 | ||
3e960501 | 1461 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1462 | { |
78501eac | 1463 | struct drm_device *dev = ring->dev; |
cae5852d | 1464 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1465 | unsigned long end; |
a71d8d94 | 1466 | int ret; |
c7dca47b | 1467 | |
a71d8d94 CW |
1468 | ret = intel_ring_wait_request(ring, n); |
1469 | if (ret != -ENOSPC) | |
1470 | return ret; | |
1471 | ||
09246732 CW |
1472 | /* force the tail write in case we have been skipping them */ |
1473 | __intel_ring_advance(ring); | |
1474 | ||
db53a302 | 1475 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1476 | /* With GEM the hangcheck timer should kick us out of the loop, |
1477 | * leaving it early runs the risk of corrupting GEM state (due | |
1478 | * to running on almost untested codepaths). But on resume | |
1479 | * timers don't work yet, so prevent a complete hang in that | |
1480 | * case by choosing an insanely large timeout. */ | |
1481 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1482 | |
8187a2b7 | 1483 | do { |
c7dca47b CW |
1484 | ring->head = I915_READ_HEAD(ring); |
1485 | ring->space = ring_space(ring); | |
62fdfeaf | 1486 | if (ring->space >= n) { |
db53a302 | 1487 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1488 | return 0; |
1489 | } | |
1490 | ||
1491 | if (dev->primary->master) { | |
1492 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1493 | if (master_priv->sarea_priv) | |
1494 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1495 | } | |
d1b851fc | 1496 | |
e60a0b10 | 1497 | msleep(1); |
d6b2c790 | 1498 | |
33196ded DV |
1499 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1500 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1501 | if (ret) |
1502 | return ret; | |
8187a2b7 | 1503 | } while (!time_after(jiffies, end)); |
db53a302 | 1504 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1505 | return -EBUSY; |
1506 | } | |
62fdfeaf | 1507 | |
3e960501 CW |
1508 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1509 | { | |
1510 | uint32_t __iomem *virt; | |
1511 | int rem = ring->size - ring->tail; | |
1512 | ||
1513 | if (ring->space < rem) { | |
1514 | int ret = ring_wait_for_space(ring, rem); | |
1515 | if (ret) | |
1516 | return ret; | |
1517 | } | |
1518 | ||
1519 | virt = ring->virtual_start + ring->tail; | |
1520 | rem /= 4; | |
1521 | while (rem--) | |
1522 | iowrite32(MI_NOOP, virt++); | |
1523 | ||
1524 | ring->tail = 0; | |
1525 | ring->space = ring_space(ring); | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1531 | { | |
1532 | u32 seqno; | |
1533 | int ret; | |
1534 | ||
1535 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1536 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1537 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1538 | if (ret) |
1539 | return ret; | |
1540 | } | |
1541 | ||
1542 | /* Wait upon the last request to be completed */ | |
1543 | if (list_empty(&ring->request_list)) | |
1544 | return 0; | |
1545 | ||
1546 | seqno = list_entry(ring->request_list.prev, | |
1547 | struct drm_i915_gem_request, | |
1548 | list)->seqno; | |
1549 | ||
1550 | return i915_wait_seqno(ring, seqno); | |
1551 | } | |
1552 | ||
9d773091 CW |
1553 | static int |
1554 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1555 | { | |
1823521d | 1556 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1557 | return 0; |
1558 | ||
3c0e234c CW |
1559 | if (ring->preallocated_lazy_request == NULL) { |
1560 | struct drm_i915_gem_request *request; | |
1561 | ||
1562 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1563 | if (request == NULL) | |
1564 | return -ENOMEM; | |
1565 | ||
1566 | ring->preallocated_lazy_request = request; | |
1567 | } | |
1568 | ||
1823521d | 1569 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1570 | } |
1571 | ||
cbcc80df MK |
1572 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
1573 | int bytes) | |
1574 | { | |
1575 | int ret; | |
1576 | ||
1577 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1578 | ret = intel_wrap_ring_buffer(ring); | |
1579 | if (unlikely(ret)) | |
1580 | return ret; | |
1581 | } | |
1582 | ||
1583 | if (unlikely(ring->space < bytes)) { | |
1584 | ret = ring_wait_for_space(ring, bytes); | |
1585 | if (unlikely(ret)) | |
1586 | return ret; | |
1587 | } | |
1588 | ||
1589 | ring->space -= bytes; | |
1590 | return 0; | |
1591 | } | |
1592 | ||
e1f99ce6 CW |
1593 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1594 | int num_dwords) | |
8187a2b7 | 1595 | { |
de2b9985 | 1596 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1597 | int ret; |
78501eac | 1598 | |
33196ded DV |
1599 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1600 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1601 | if (ret) |
1602 | return ret; | |
21dd3734 | 1603 | |
9d773091 CW |
1604 | /* Preallocate the olr before touching the ring */ |
1605 | ret = intel_ring_alloc_seqno(ring); | |
1606 | if (ret) | |
1607 | return ret; | |
1608 | ||
cbcc80df | 1609 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
8187a2b7 | 1610 | } |
78501eac | 1611 | |
f7e98ad4 | 1612 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1613 | { |
f7e98ad4 | 1614 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1615 | |
1823521d | 1616 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1617 | |
f7e98ad4 MK |
1618 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1619 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1620 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1621 | if (HAS_VEBOX(ring->dev)) |
1622 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1623 | } |
d97ed339 | 1624 | |
f7e98ad4 | 1625 | ring->set_seqno(ring, seqno); |
92cab734 | 1626 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1627 | } |
62fdfeaf | 1628 | |
78501eac | 1629 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1630 | u32 value) |
881f47b6 | 1631 | { |
0206e353 | 1632 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1633 | |
1634 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1635 | |
1636 | /* Disable notification that the ring is IDLE. The GT | |
1637 | * will then assume that it is busy and bring it out of rc6. | |
1638 | */ | |
0206e353 | 1639 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1640 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1641 | ||
1642 | /* Clear the context id. Here be magic! */ | |
1643 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1644 | |
12f55818 | 1645 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1646 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1647 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1648 | 50)) | |
1649 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1650 | |
12f55818 | 1651 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1652 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1653 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1654 | ||
1655 | /* Let the ring send IDLE messages to the GT again, | |
1656 | * and so let it sleep to conserve power when idle. | |
1657 | */ | |
0206e353 | 1658 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1659 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1660 | } |
1661 | ||
ea251324 BW |
1662 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1663 | u32 invalidate, u32 flush) | |
881f47b6 | 1664 | { |
71a77e07 | 1665 | uint32_t cmd; |
b72f3acb CW |
1666 | int ret; |
1667 | ||
b72f3acb CW |
1668 | ret = intel_ring_begin(ring, 4); |
1669 | if (ret) | |
1670 | return ret; | |
1671 | ||
71a77e07 | 1672 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1673 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1674 | cmd += 1; | |
9a289771 JB |
1675 | /* |
1676 | * Bspec vol 1c.5 - video engine command streamer: | |
1677 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1678 | * operation is complete. This bit is only valid when the | |
1679 | * Post-Sync Operation field is a value of 1h or 3h." | |
1680 | */ | |
71a77e07 | 1681 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1682 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1683 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1684 | intel_ring_emit(ring, cmd); |
9a289771 | 1685 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1686 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1687 | intel_ring_emit(ring, 0); /* upper addr */ | |
1688 | intel_ring_emit(ring, 0); /* value */ | |
1689 | } else { | |
1690 | intel_ring_emit(ring, 0); | |
1691 | intel_ring_emit(ring, MI_NOOP); | |
1692 | } | |
b72f3acb CW |
1693 | intel_ring_advance(ring); |
1694 | return 0; | |
881f47b6 XH |
1695 | } |
1696 | ||
1c7a0623 BW |
1697 | static int |
1698 | gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1699 | u32 offset, u32 len, | |
1700 | unsigned flags) | |
1701 | { | |
1702 | int ret; | |
1703 | ||
1704 | ret = intel_ring_begin(ring, 4); | |
1705 | if (ret) | |
1706 | return ret; | |
1707 | ||
1708 | /* FIXME(BDW): Address space and security selectors. */ | |
1709 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8); | |
1710 | intel_ring_emit(ring, offset); | |
1711 | intel_ring_emit(ring, 0); | |
1712 | intel_ring_emit(ring, MI_NOOP); | |
1713 | intel_ring_advance(ring); | |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
d7d4eedd CW |
1718 | static int |
1719 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1720 | u32 offset, u32 len, | |
1721 | unsigned flags) | |
1722 | { | |
1723 | int ret; | |
1724 | ||
1725 | ret = intel_ring_begin(ring, 2); | |
1726 | if (ret) | |
1727 | return ret; | |
1728 | ||
1729 | intel_ring_emit(ring, | |
1730 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1731 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1732 | /* bit0-7 is the length on GEN6+ */ | |
1733 | intel_ring_emit(ring, offset); | |
1734 | intel_ring_advance(ring); | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
881f47b6 | 1739 | static int |
78501eac | 1740 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1741 | u32 offset, u32 len, |
1742 | unsigned flags) | |
881f47b6 | 1743 | { |
0206e353 | 1744 | int ret; |
ab6f8e32 | 1745 | |
0206e353 AJ |
1746 | ret = intel_ring_begin(ring, 2); |
1747 | if (ret) | |
1748 | return ret; | |
e1f99ce6 | 1749 | |
d7d4eedd CW |
1750 | intel_ring_emit(ring, |
1751 | MI_BATCH_BUFFER_START | | |
1752 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1753 | /* bit0-7 is the length on GEN6+ */ |
1754 | intel_ring_emit(ring, offset); | |
1755 | intel_ring_advance(ring); | |
ab6f8e32 | 1756 | |
0206e353 | 1757 | return 0; |
881f47b6 XH |
1758 | } |
1759 | ||
549f7365 CW |
1760 | /* Blitter support (SandyBridge+) */ |
1761 | ||
ea251324 BW |
1762 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1763 | u32 invalidate, u32 flush) | |
8d19215b | 1764 | { |
fd3da6c9 | 1765 | struct drm_device *dev = ring->dev; |
71a77e07 | 1766 | uint32_t cmd; |
b72f3acb CW |
1767 | int ret; |
1768 | ||
6a233c78 | 1769 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1770 | if (ret) |
1771 | return ret; | |
1772 | ||
71a77e07 | 1773 | cmd = MI_FLUSH_DW; |
075b3bba BW |
1774 | if (INTEL_INFO(ring->dev)->gen >= 8) |
1775 | cmd += 1; | |
9a289771 JB |
1776 | /* |
1777 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1778 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1779 | * operation is complete. This bit is only valid when the | |
1780 | * Post-Sync Operation field is a value of 1h or 3h." | |
1781 | */ | |
71a77e07 | 1782 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1783 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1784 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1785 | intel_ring_emit(ring, cmd); |
9a289771 | 1786 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
1787 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
1788 | intel_ring_emit(ring, 0); /* upper addr */ | |
1789 | intel_ring_emit(ring, 0); /* value */ | |
1790 | } else { | |
1791 | intel_ring_emit(ring, 0); | |
1792 | intel_ring_emit(ring, MI_NOOP); | |
1793 | } | |
b72f3acb | 1794 | intel_ring_advance(ring); |
fd3da6c9 RV |
1795 | |
1796 | if (IS_GEN7(dev) && flush) | |
1797 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
1798 | ||
b72f3acb | 1799 | return 0; |
8d19215b ZN |
1800 | } |
1801 | ||
5c1143bb XH |
1802 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1803 | { | |
1804 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1805 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1806 | |
59465b5f DV |
1807 | ring->name = "render ring"; |
1808 | ring->id = RCS; | |
1809 | ring->mmio_base = RENDER_RING_BASE; | |
1810 | ||
1ec14ad3 CW |
1811 | if (INTEL_INFO(dev)->gen >= 6) { |
1812 | ring->add_request = gen6_add_request; | |
4772eaeb | 1813 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1814 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1815 | ring->flush = gen6_render_ring_flush; |
abd58f01 BW |
1816 | if (INTEL_INFO(dev)->gen >= 8) { |
1817 | ring->irq_get = gen8_ring_get_irq; | |
1818 | ring->irq_put = gen8_ring_put_irq; | |
1819 | } else { | |
1820 | ring->irq_get = gen6_ring_get_irq; | |
1821 | ring->irq_put = gen6_ring_put_irq; | |
1822 | } | |
cc609d5d | 1823 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1824 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1825 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1826 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1827 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1828 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1829 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1830 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1831 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1832 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1833 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1834 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1835 | } else if (IS_GEN5(dev)) { |
1836 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1837 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1838 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1839 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1840 | ring->irq_get = gen5_ring_get_irq; |
1841 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1842 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1843 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1844 | } else { |
8620a3a9 | 1845 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1846 | if (INTEL_INFO(dev)->gen < 4) |
1847 | ring->flush = gen2_render_ring_flush; | |
1848 | else | |
1849 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1850 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1851 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1852 | if (IS_GEN2(dev)) { |
1853 | ring->irq_get = i8xx_ring_get_irq; | |
1854 | ring->irq_put = i8xx_ring_put_irq; | |
1855 | } else { | |
1856 | ring->irq_get = i9xx_ring_get_irq; | |
1857 | ring->irq_put = i9xx_ring_put_irq; | |
1858 | } | |
e3670319 | 1859 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1860 | } |
59465b5f | 1861 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1862 | if (IS_HASWELL(dev)) |
1863 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
1864 | else if (IS_GEN8(dev)) |
1865 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 1866 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
1867 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1868 | else if (INTEL_INFO(dev)->gen >= 4) | |
1869 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1870 | else if (IS_I830(dev) || IS_845G(dev)) | |
1871 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1872 | else | |
1873 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1874 | ring->init = init_render_ring; |
1875 | ring->cleanup = render_ring_cleanup; | |
1876 | ||
b45305fc DV |
1877 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1878 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1879 | struct drm_i915_gem_object *obj; | |
1880 | int ret; | |
1881 | ||
1882 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1883 | if (obj == NULL) { | |
1884 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1885 | return -ENOMEM; | |
1886 | } | |
1887 | ||
c37e2204 | 1888 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
b45305fc DV |
1889 | if (ret != 0) { |
1890 | drm_gem_object_unreference(&obj->base); | |
1891 | DRM_ERROR("Failed to ping batch bo\n"); | |
1892 | return ret; | |
1893 | } | |
1894 | ||
0d1aacac CW |
1895 | ring->scratch.obj = obj; |
1896 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
1897 | } |
1898 | ||
1ec14ad3 | 1899 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1900 | } |
1901 | ||
e8616b6c CW |
1902 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1903 | { | |
1904 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1905 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
6b8294a4 | 1906 | int ret; |
e8616b6c | 1907 | |
59465b5f DV |
1908 | ring->name = "render ring"; |
1909 | ring->id = RCS; | |
1910 | ring->mmio_base = RENDER_RING_BASE; | |
1911 | ||
e8616b6c | 1912 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1913 | /* non-kms not supported on gen6+ */ |
1914 | return -ENODEV; | |
e8616b6c | 1915 | } |
28f0cbf7 DV |
1916 | |
1917 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1918 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1919 | * the special gen5 functions. */ | |
1920 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1921 | if (INTEL_INFO(dev)->gen < 4) |
1922 | ring->flush = gen2_render_ring_flush; | |
1923 | else | |
1924 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1925 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1926 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1927 | if (IS_GEN2(dev)) { |
1928 | ring->irq_get = i8xx_ring_get_irq; | |
1929 | ring->irq_put = i8xx_ring_put_irq; | |
1930 | } else { | |
1931 | ring->irq_get = i9xx_ring_get_irq; | |
1932 | ring->irq_put = i9xx_ring_put_irq; | |
1933 | } | |
28f0cbf7 | 1934 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1935 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1936 | if (INTEL_INFO(dev)->gen >= 4) |
1937 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1938 | else if (IS_I830(dev) || IS_845G(dev)) | |
1939 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1940 | else | |
1941 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1942 | ring->init = init_render_ring; |
1943 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
1944 | |
1945 | ring->dev = dev; | |
1946 | INIT_LIST_HEAD(&ring->active_list); | |
1947 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1948 | |
1949 | ring->size = size; | |
1950 | ring->effective_size = ring->size; | |
17f10fdc | 1951 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
1952 | ring->effective_size -= 128; |
1953 | ||
4225d0f2 DV |
1954 | ring->virtual_start = ioremap_wc(start, size); |
1955 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1956 | DRM_ERROR("can not ioremap virtual address for" |
1957 | " ring buffer\n"); | |
1958 | return -ENOMEM; | |
1959 | } | |
1960 | ||
6b8294a4 | 1961 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 1962 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1963 | if (ret) |
1964 | return ret; | |
1965 | } | |
1966 | ||
e8616b6c CW |
1967 | return 0; |
1968 | } | |
1969 | ||
5c1143bb XH |
1970 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1971 | { | |
1972 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1973 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1974 | |
58fa3835 DV |
1975 | ring->name = "bsd ring"; |
1976 | ring->id = VCS; | |
1977 | ||
0fd2c201 | 1978 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1979 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1980 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1981 | /* gen6 bsd needs a special wa for tail updates */ |
1982 | if (IS_GEN6(dev)) | |
1983 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 1984 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
1985 | ring->add_request = gen6_add_request; |
1986 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 1987 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
1988 | if (INTEL_INFO(dev)->gen >= 8) { |
1989 | ring->irq_enable_mask = | |
1990 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
1991 | ring->irq_get = gen8_ring_get_irq; | |
1992 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
1993 | ring->dispatch_execbuffer = |
1994 | gen8_ring_dispatch_execbuffer; | |
abd58f01 BW |
1995 | } else { |
1996 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
1997 | ring->irq_get = gen6_ring_get_irq; | |
1998 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
1999 | ring->dispatch_execbuffer = |
2000 | gen6_ring_dispatch_execbuffer; | |
abd58f01 | 2001 | } |
686cb5f9 | 2002 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2003 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
2004 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2005 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 2006 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
2007 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
2008 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
2009 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 2010 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
2011 | } else { |
2012 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2013 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2014 | ring->add_request = i9xx_add_request; |
58fa3835 | 2015 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2016 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2017 | if (IS_GEN5(dev)) { |
cc609d5d | 2018 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2019 | ring->irq_get = gen5_ring_get_irq; |
2020 | ring->irq_put = gen5_ring_put_irq; | |
2021 | } else { | |
e3670319 | 2022 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2023 | ring->irq_get = i9xx_ring_get_irq; |
2024 | ring->irq_put = i9xx_ring_put_irq; | |
2025 | } | |
fb3256da | 2026 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2027 | } |
2028 | ring->init = init_ring_common; | |
2029 | ||
1ec14ad3 | 2030 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2031 | } |
549f7365 CW |
2032 | |
2033 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
2034 | { | |
2035 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2036 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 2037 | |
3535d9dd DV |
2038 | ring->name = "blitter ring"; |
2039 | ring->id = BCS; | |
2040 | ||
2041 | ring->mmio_base = BLT_RING_BASE; | |
2042 | ring->write_tail = ring_write_tail; | |
ea251324 | 2043 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2044 | ring->add_request = gen6_add_request; |
2045 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2046 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2047 | if (INTEL_INFO(dev)->gen >= 8) { |
2048 | ring->irq_enable_mask = | |
2049 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2050 | ring->irq_get = gen8_ring_get_irq; | |
2051 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2052 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2053 | } else { |
2054 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2055 | ring->irq_get = gen6_ring_get_irq; | |
2056 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2057 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2058 | } |
686cb5f9 | 2059 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
2060 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
2061 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2062 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 2063 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
2064 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
2065 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
2066 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 2067 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 2068 | ring->init = init_ring_common; |
549f7365 | 2069 | |
1ec14ad3 | 2070 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2071 | } |
a7b9761d | 2072 | |
9a8a2213 BW |
2073 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2074 | { | |
2075 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2076 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; | |
2077 | ||
2078 | ring->name = "video enhancement ring"; | |
2079 | ring->id = VECS; | |
2080 | ||
2081 | ring->mmio_base = VEBOX_RING_BASE; | |
2082 | ring->write_tail = ring_write_tail; | |
2083 | ring->flush = gen6_ring_flush; | |
2084 | ring->add_request = gen6_add_request; | |
2085 | ring->get_seqno = gen6_ring_get_seqno; | |
2086 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2087 | |
2088 | if (INTEL_INFO(dev)->gen >= 8) { | |
2089 | ring->irq_enable_mask = | |
2090 | (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT) | | |
2091 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT; | |
2092 | ring->irq_get = gen8_ring_get_irq; | |
2093 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2094 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
abd58f01 BW |
2095 | } else { |
2096 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2097 | ring->irq_get = hsw_vebox_get_irq; | |
2098 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2099 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
abd58f01 | 2100 | } |
9a8a2213 BW |
2101 | ring->sync_to = gen6_ring_sync; |
2102 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2103 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2104 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2105 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2106 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
2107 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
2108 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
2109 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
2110 | ring->init = init_ring_common; | |
2111 | ||
2112 | return intel_init_ring_buffer(dev, ring); | |
2113 | } | |
2114 | ||
a7b9761d CW |
2115 | int |
2116 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2117 | { | |
2118 | int ret; | |
2119 | ||
2120 | if (!ring->gpu_caches_dirty) | |
2121 | return 0; | |
2122 | ||
2123 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2124 | if (ret) | |
2125 | return ret; | |
2126 | ||
2127 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2128 | ||
2129 | ring->gpu_caches_dirty = false; | |
2130 | return 0; | |
2131 | } | |
2132 | ||
2133 | int | |
2134 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2135 | { | |
2136 | uint32_t flush_domains; | |
2137 | int ret; | |
2138 | ||
2139 | flush_domains = 0; | |
2140 | if (ring->gpu_caches_dirty) | |
2141 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2142 | ||
2143 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2144 | if (ret) | |
2145 | return ret; | |
2146 | ||
2147 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2148 | ||
2149 | ring->gpu_caches_dirty = false; | |
2150 | return 0; | |
2151 | } |