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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
52 | ||
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
1cf0ba14 | 55 | int space = head - (tail + I915_RING_FREE_SPACE); |
c7dca47b | 56 | if (space < 0) |
1cf0ba14 | 57 | space += size; |
c7dca47b CW |
58 | return space; |
59 | } | |
60 | ||
82e104cc | 61 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 62 | { |
82e104cc OM |
63 | return __intel_ring_space(ringbuf->head & HEAD_ADDR, |
64 | ringbuf->tail, ringbuf->size); | |
1cf0ba14 CW |
65 | } |
66 | ||
82e104cc | 67 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
68 | { |
69 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
70 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
71 | } | |
09246732 | 72 | |
a4872ba6 | 73 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 74 | { |
93b0a4e0 OM |
75 | struct intel_ringbuffer *ringbuf = ring->buffer; |
76 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 77 | if (intel_ring_stopped(ring)) |
09246732 | 78 | return; |
93b0a4e0 | 79 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
80 | } |
81 | ||
b72f3acb | 82 | static int |
a4872ba6 | 83 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
84 | u32 invalidate_domains, |
85 | u32 flush_domains) | |
86 | { | |
87 | u32 cmd; | |
88 | int ret; | |
89 | ||
90 | cmd = MI_FLUSH; | |
31b14c9f | 91 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
92 | cmd |= MI_NO_WRITE_FLUSH; |
93 | ||
94 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
95 | cmd |= MI_READ_FLUSH; | |
96 | ||
97 | ret = intel_ring_begin(ring, 2); | |
98 | if (ret) | |
99 | return ret; | |
100 | ||
101 | intel_ring_emit(ring, cmd); | |
102 | intel_ring_emit(ring, MI_NOOP); | |
103 | intel_ring_advance(ring); | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
108 | static int | |
a4872ba6 | 109 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
110 | u32 invalidate_domains, |
111 | u32 flush_domains) | |
62fdfeaf | 112 | { |
78501eac | 113 | struct drm_device *dev = ring->dev; |
6f392d54 | 114 | u32 cmd; |
b72f3acb | 115 | int ret; |
6f392d54 | 116 | |
36d527de CW |
117 | /* |
118 | * read/write caches: | |
119 | * | |
120 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
121 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
122 | * also flushed at 2d versus 3d pipeline switches. | |
123 | * | |
124 | * read-only caches: | |
125 | * | |
126 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
127 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
128 | * | |
129 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
130 | * | |
131 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
132 | * invalidated when MI_EXE_FLUSH is set. | |
133 | * | |
134 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
135 | * invalidated with every MI_FLUSH. | |
136 | * | |
137 | * TLBs: | |
138 | * | |
139 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
140 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
141 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
142 | * are flushed at any MI_FLUSH. | |
143 | */ | |
144 | ||
145 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 146 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 147 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
148 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
149 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 150 | |
36d527de CW |
151 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
152 | (IS_G4X(dev) || IS_GEN5(dev))) | |
153 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 154 | |
36d527de CW |
155 | ret = intel_ring_begin(ring, 2); |
156 | if (ret) | |
157 | return ret; | |
b72f3acb | 158 | |
36d527de CW |
159 | intel_ring_emit(ring, cmd); |
160 | intel_ring_emit(ring, MI_NOOP); | |
161 | intel_ring_advance(ring); | |
b72f3acb CW |
162 | |
163 | return 0; | |
8187a2b7 ZN |
164 | } |
165 | ||
8d315287 JB |
166 | /** |
167 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
168 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
169 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
170 | * | |
171 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
172 | * produced by non-pipelined state commands), software needs to first | |
173 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
174 | * 0. | |
175 | * | |
176 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
177 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
178 | * | |
179 | * And the workaround for these two requires this workaround first: | |
180 | * | |
181 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
182 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
183 | * flushes. | |
184 | * | |
185 | * And this last workaround is tricky because of the requirements on | |
186 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
187 | * volume 2 part 1: | |
188 | * | |
189 | * "1 of the following must also be set: | |
190 | * - Render Target Cache Flush Enable ([12] of DW1) | |
191 | * - Depth Cache Flush Enable ([0] of DW1) | |
192 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
193 | * - Depth Stall ([13] of DW1) | |
194 | * - Post-Sync Operation ([13] of DW1) | |
195 | * - Notify Enable ([8] of DW1)" | |
196 | * | |
197 | * The cache flushes require the workaround flush that triggered this | |
198 | * one, so we can't use it. Depth stall would trigger the same. | |
199 | * Post-sync nonzero is what triggered this second workaround, so we | |
200 | * can't use that one either. Notify enable is IRQs, which aren't | |
201 | * really our business. That leaves only stall at scoreboard. | |
202 | */ | |
203 | static int | |
a4872ba6 | 204 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 205 | { |
18393f63 | 206 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
207 | int ret; |
208 | ||
209 | ||
210 | ret = intel_ring_begin(ring, 6); | |
211 | if (ret) | |
212 | return ret; | |
213 | ||
214 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
215 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
216 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
217 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
218 | intel_ring_emit(ring, 0); /* low dword */ | |
219 | intel_ring_emit(ring, 0); /* high dword */ | |
220 | intel_ring_emit(ring, MI_NOOP); | |
221 | intel_ring_advance(ring); | |
222 | ||
223 | ret = intel_ring_begin(ring, 6); | |
224 | if (ret) | |
225 | return ret; | |
226 | ||
227 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
228 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
229 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
230 | intel_ring_emit(ring, 0); | |
231 | intel_ring_emit(ring, 0); | |
232 | intel_ring_emit(ring, MI_NOOP); | |
233 | intel_ring_advance(ring); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static int | |
a4872ba6 | 239 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
240 | u32 invalidate_domains, u32 flush_domains) |
241 | { | |
242 | u32 flags = 0; | |
18393f63 | 243 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
244 | int ret; |
245 | ||
b3111509 PZ |
246 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
247 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
8d315287 JB |
251 | /* Just flush everything. Experiments have shown that reducing the |
252 | * number of bits based on the write domains has little performance | |
253 | * impact. | |
254 | */ | |
7d54a904 CW |
255 | if (flush_domains) { |
256 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
257 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
258 | /* | |
259 | * Ensure that any following seqno writes only happen | |
260 | * when the render cache is indeed flushed. | |
261 | */ | |
97f209bc | 262 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
263 | } |
264 | if (invalidate_domains) { | |
265 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
266 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
267 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
268 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
269 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
270 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
271 | /* | |
272 | * TLB invalidate requires a post-sync write. | |
273 | */ | |
3ac78313 | 274 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 275 | } |
8d315287 | 276 | |
6c6cf5aa | 277 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
278 | if (ret) |
279 | return ret; | |
280 | ||
6c6cf5aa | 281 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
282 | intel_ring_emit(ring, flags); |
283 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 284 | intel_ring_emit(ring, 0); |
8d315287 JB |
285 | intel_ring_advance(ring); |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
f3987631 | 290 | static int |
a4872ba6 | 291 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
292 | { |
293 | int ret; | |
294 | ||
295 | ret = intel_ring_begin(ring, 4); | |
296 | if (ret) | |
297 | return ret; | |
298 | ||
299 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
300 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
301 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
302 | intel_ring_emit(ring, 0); | |
303 | intel_ring_emit(ring, 0); | |
304 | intel_ring_advance(ring); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
a4872ba6 | 309 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
310 | { |
311 | int ret; | |
312 | ||
313 | if (!ring->fbc_dirty) | |
314 | return 0; | |
315 | ||
37c1d94f | 316 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
317 | if (ret) |
318 | return ret; | |
fd3da6c9 RV |
319 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
320 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
321 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
322 | intel_ring_emit(ring, value); | |
37c1d94f VS |
323 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
324 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
325 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
326 | intel_ring_advance(ring); |
327 | ||
328 | ring->fbc_dirty = false; | |
329 | return 0; | |
330 | } | |
331 | ||
4772eaeb | 332 | static int |
a4872ba6 | 333 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
334 | u32 invalidate_domains, u32 flush_domains) |
335 | { | |
336 | u32 flags = 0; | |
18393f63 | 337 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
338 | int ret; |
339 | ||
f3987631 PZ |
340 | /* |
341 | * Ensure that any following seqno writes only happen when the render | |
342 | * cache is indeed flushed. | |
343 | * | |
344 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
345 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
346 | * don't try to be clever and just set it unconditionally. | |
347 | */ | |
348 | flags |= PIPE_CONTROL_CS_STALL; | |
349 | ||
4772eaeb PZ |
350 | /* Just flush everything. Experiments have shown that reducing the |
351 | * number of bits based on the write domains has little performance | |
352 | * impact. | |
353 | */ | |
354 | if (flush_domains) { | |
355 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
356 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
357 | } |
358 | if (invalidate_domains) { | |
359 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
360 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
361 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
362 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
363 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
364 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
365 | /* | |
366 | * TLB invalidate requires a post-sync write. | |
367 | */ | |
368 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 369 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
370 | |
371 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
372 | * set before a pipe_control command that has the state cache | |
373 | * invalidate bit set. */ | |
374 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
375 | } |
376 | ||
377 | ret = intel_ring_begin(ring, 4); | |
378 | if (ret) | |
379 | return ret; | |
380 | ||
381 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
382 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 383 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
384 | intel_ring_emit(ring, 0); |
385 | intel_ring_advance(ring); | |
386 | ||
9688ecad | 387 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
388 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
389 | ||
4772eaeb PZ |
390 | return 0; |
391 | } | |
392 | ||
884ceace KG |
393 | static int |
394 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
395 | u32 flags, u32 scratch_addr) | |
396 | { | |
397 | int ret; | |
398 | ||
399 | ret = intel_ring_begin(ring, 6); | |
400 | if (ret) | |
401 | return ret; | |
402 | ||
403 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
404 | intel_ring_emit(ring, flags); | |
405 | intel_ring_emit(ring, scratch_addr); | |
406 | intel_ring_emit(ring, 0); | |
407 | intel_ring_emit(ring, 0); | |
408 | intel_ring_emit(ring, 0); | |
409 | intel_ring_advance(ring); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
a5f3d68e | 414 | static int |
a4872ba6 | 415 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
416 | u32 invalidate_domains, u32 flush_domains) |
417 | { | |
418 | u32 flags = 0; | |
18393f63 | 419 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 420 | int ret; |
a5f3d68e BW |
421 | |
422 | flags |= PIPE_CONTROL_CS_STALL; | |
423 | ||
424 | if (flush_domains) { | |
425 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
426 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
427 | } | |
428 | if (invalidate_domains) { | |
429 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
430 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
431 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
432 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
433 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
434 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
435 | flags |= PIPE_CONTROL_QW_WRITE; | |
436 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
437 | |
438 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
439 | ret = gen8_emit_pipe_control(ring, | |
440 | PIPE_CONTROL_CS_STALL | | |
441 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
442 | 0); | |
443 | if (ret) | |
444 | return ret; | |
a5f3d68e BW |
445 | } |
446 | ||
c5ad011d RV |
447 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
448 | if (ret) | |
449 | return ret; | |
450 | ||
451 | if (!invalidate_domains && flush_domains) | |
452 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
453 | ||
454 | return 0; | |
a5f3d68e BW |
455 | } |
456 | ||
a4872ba6 | 457 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 458 | u32 value) |
d46eefa2 | 459 | { |
4640c4ff | 460 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 461 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
462 | } |
463 | ||
a4872ba6 | 464 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 465 | { |
4640c4ff | 466 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 467 | u64 acthd; |
8187a2b7 | 468 | |
50877445 CW |
469 | if (INTEL_INFO(ring->dev)->gen >= 8) |
470 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
471 | RING_ACTHD_UDW(ring->mmio_base)); | |
472 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
473 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
474 | else | |
475 | acthd = I915_READ(ACTHD); | |
476 | ||
477 | return acthd; | |
8187a2b7 ZN |
478 | } |
479 | ||
a4872ba6 | 480 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
481 | { |
482 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
483 | u32 addr; | |
484 | ||
485 | addr = dev_priv->status_page_dmah->busaddr; | |
486 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
487 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
488 | I915_WRITE(HWS_PGA, addr); | |
489 | } | |
490 | ||
a4872ba6 | 491 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 492 | { |
9991ae78 | 493 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 494 | |
9991ae78 CW |
495 | if (!IS_GEN2(ring->dev)) { |
496 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
497 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
498 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
499 | /* Sometimes we observe that the idle flag is not |
500 | * set even though the ring is empty. So double | |
501 | * check before giving up. | |
502 | */ | |
503 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
504 | return false; | |
9991ae78 CW |
505 | } |
506 | } | |
b7884eb4 | 507 | |
7f2ab699 | 508 | I915_WRITE_CTL(ring, 0); |
570ef608 | 509 | I915_WRITE_HEAD(ring, 0); |
78501eac | 510 | ring->write_tail(ring, 0); |
8187a2b7 | 511 | |
9991ae78 CW |
512 | if (!IS_GEN2(ring->dev)) { |
513 | (void)I915_READ_CTL(ring); | |
514 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
515 | } | |
a51435a3 | 516 | |
9991ae78 CW |
517 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
518 | } | |
8187a2b7 | 519 | |
a4872ba6 | 520 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
521 | { |
522 | struct drm_device *dev = ring->dev; | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
524 | struct intel_ringbuffer *ringbuf = ring->buffer; |
525 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
526 | int ret = 0; |
527 | ||
528 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
529 | ||
530 | if (!stop_ring(ring)) { | |
531 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
532 | DRM_DEBUG_KMS("%s head not reset to zero " |
533 | "ctl %08x head %08x tail %08x start %08x\n", | |
534 | ring->name, | |
535 | I915_READ_CTL(ring), | |
536 | I915_READ_HEAD(ring), | |
537 | I915_READ_TAIL(ring), | |
538 | I915_READ_START(ring)); | |
8187a2b7 | 539 | |
9991ae78 | 540 | if (!stop_ring(ring)) { |
6fd0d56e CW |
541 | DRM_ERROR("failed to set %s head to zero " |
542 | "ctl %08x head %08x tail %08x start %08x\n", | |
543 | ring->name, | |
544 | I915_READ_CTL(ring), | |
545 | I915_READ_HEAD(ring), | |
546 | I915_READ_TAIL(ring), | |
547 | I915_READ_START(ring)); | |
9991ae78 CW |
548 | ret = -EIO; |
549 | goto out; | |
6fd0d56e | 550 | } |
8187a2b7 ZN |
551 | } |
552 | ||
9991ae78 CW |
553 | if (I915_NEED_GFX_HWS(dev)) |
554 | intel_ring_setup_status_page(ring); | |
555 | else | |
556 | ring_setup_phys_status_page(ring); | |
557 | ||
ece4a17d JK |
558 | /* Enforce ordering by reading HEAD register back */ |
559 | I915_READ_HEAD(ring); | |
560 | ||
0d8957c8 DV |
561 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
562 | * registers with the above sequence (the readback of the HEAD registers | |
563 | * also enforces ordering), otherwise the hw might lose the new ring | |
564 | * register values. */ | |
f343c5f6 | 565 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
566 | |
567 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
568 | if (I915_READ_HEAD(ring)) | |
569 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
570 | ring->name, I915_READ_HEAD(ring)); | |
571 | I915_WRITE_HEAD(ring, 0); | |
572 | (void)I915_READ_HEAD(ring); | |
573 | ||
7f2ab699 | 574 | I915_WRITE_CTL(ring, |
93b0a4e0 | 575 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 576 | | RING_VALID); |
8187a2b7 | 577 | |
8187a2b7 | 578 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 579 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 580 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 581 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 582 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
583 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
584 | ring->name, | |
585 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
586 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
587 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
588 | ret = -EIO; |
589 | goto out; | |
8187a2b7 ZN |
590 | } |
591 | ||
78501eac CW |
592 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
593 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 594 | else { |
93b0a4e0 OM |
595 | ringbuf->head = I915_READ_HEAD(ring); |
596 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
82e104cc | 597 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 598 | ringbuf->last_retired_head = -1; |
8187a2b7 | 599 | } |
1ec14ad3 | 600 | |
50f018df CW |
601 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
602 | ||
b7884eb4 | 603 | out: |
c8d9a590 | 604 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
605 | |
606 | return ret; | |
8187a2b7 ZN |
607 | } |
608 | ||
9b1136d5 OM |
609 | void |
610 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
611 | { | |
612 | struct drm_device *dev = ring->dev; | |
613 | ||
614 | if (ring->scratch.obj == NULL) | |
615 | return; | |
616 | ||
617 | if (INTEL_INFO(dev)->gen >= 5) { | |
618 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
619 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
620 | } | |
621 | ||
622 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
623 | ring->scratch.obj = NULL; | |
624 | } | |
625 | ||
626 | int | |
627 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 628 | { |
c6df541c CW |
629 | int ret; |
630 | ||
0d1aacac | 631 | if (ring->scratch.obj) |
c6df541c CW |
632 | return 0; |
633 | ||
0d1aacac CW |
634 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
635 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
636 | DRM_ERROR("Failed to allocate seqno page\n"); |
637 | ret = -ENOMEM; | |
638 | goto err; | |
639 | } | |
e4ffd173 | 640 | |
a9cc726c DV |
641 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
642 | if (ret) | |
643 | goto err_unref; | |
c6df541c | 644 | |
1ec9e26d | 645 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
646 | if (ret) |
647 | goto err_unref; | |
648 | ||
0d1aacac CW |
649 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
650 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
651 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 652 | ret = -ENOMEM; |
c6df541c | 653 | goto err_unpin; |
56b085a0 | 654 | } |
c6df541c | 655 | |
2b1086cc | 656 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 657 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
658 | return 0; |
659 | ||
660 | err_unpin: | |
d7f46fc4 | 661 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 662 | err_unref: |
0d1aacac | 663 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 664 | err: |
c6df541c CW |
665 | return ret; |
666 | } | |
667 | ||
86d7f238 AS |
668 | static inline void intel_ring_emit_wa(struct intel_engine_cs *ring, |
669 | u32 addr, u32 value) | |
670 | { | |
888b5995 AS |
671 | struct drm_device *dev = ring->dev; |
672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
673 | ||
04ad2dc7 | 674 | if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS)) |
888b5995 AS |
675 | return; |
676 | ||
86d7f238 AS |
677 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
678 | intel_ring_emit(ring, addr); | |
679 | intel_ring_emit(ring, value); | |
888b5995 AS |
680 | |
681 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr; | |
b07ba1dc | 682 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF; |
888b5995 AS |
683 | /* value is updated with the status of remaining bits of this |
684 | * register when it is read from debugfs file | |
685 | */ | |
686 | dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value; | |
687 | dev_priv->num_wa_regs++; | |
688 | ||
689 | return; | |
86d7f238 AS |
690 | } |
691 | ||
00e1e623 | 692 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 AS |
693 | { |
694 | int ret; | |
888b5995 AS |
695 | struct drm_device *dev = ring->dev; |
696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 AS |
697 | |
698 | /* | |
699 | * workarounds applied in this fn are part of register state context, | |
700 | * they need to be re-initialized followed by gpu reset, suspend/resume, | |
701 | * module reload. | |
702 | */ | |
888b5995 AS |
703 | dev_priv->num_wa_regs = 0; |
704 | memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); | |
86d7f238 AS |
705 | |
706 | /* | |
707 | * update the number of dwords required based on the | |
708 | * actual number of workarounds applied | |
709 | */ | |
710 | ret = intel_ring_begin(ring, 24); | |
711 | if (ret) | |
712 | return ret; | |
713 | ||
714 | /* WaDisablePartialInstShootdown:bdw */ | |
715 | /* WaDisableThreadStallDopClockGating:bdw */ | |
716 | /* FIXME: Unclear whether we really need this on production bdw. */ | |
717 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, | |
718 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
719 | | STALL_DOP_GATING_DISABLE)); | |
720 | ||
721 | /* WaDisableDopClockGating:bdw May not be needed for production */ | |
722 | intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, | |
723 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
724 | ||
725 | /* | |
726 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for | |
727 | * pre-production hardware | |
728 | */ | |
729 | intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, | |
730 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS | |
731 | | GEN8_SAMPLER_POWER_BYPASS_DIS)); | |
732 | ||
733 | intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, | |
734 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); | |
735 | ||
736 | intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, | |
737 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); | |
738 | ||
739 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
740 | * workaround for for a possible hang in the unlikely event a TLB | |
741 | * invalidation occurs during a PSD flush. | |
742 | */ | |
743 | intel_ring_emit_wa(ring, HDC_CHICKEN0, | |
744 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); | |
745 | ||
746 | /* Wa4x4STCOptimizationDisable:bdw */ | |
747 | intel_ring_emit_wa(ring, CACHE_MODE_1, | |
748 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); | |
749 | ||
750 | /* | |
751 | * BSpec recommends 8x4 when MSAA is used, | |
752 | * however in practice 16x4 seems fastest. | |
753 | * | |
754 | * Note that PS/WM thread counts depend on the WIZ hashing | |
755 | * disable bit, which we don't touch here, but it's good | |
756 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
757 | */ | |
758 | intel_ring_emit_wa(ring, GEN7_GT_MODE, | |
759 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
760 | ||
761 | intel_ring_advance(ring); | |
762 | ||
888b5995 AS |
763 | DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n", |
764 | dev_priv->num_wa_regs); | |
765 | ||
86d7f238 AS |
766 | return 0; |
767 | } | |
768 | ||
00e1e623 VS |
769 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
770 | { | |
771 | int ret; | |
772 | struct drm_device *dev = ring->dev; | |
773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
774 | ||
775 | /* | |
776 | * workarounds applied in this fn are part of register state context, | |
777 | * they need to be re-initialized followed by gpu reset, suspend/resume, | |
778 | * module reload. | |
779 | */ | |
780 | dev_priv->num_wa_regs = 0; | |
781 | memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs)); | |
782 | ||
783 | ret = intel_ring_begin(ring, 12); | |
784 | if (ret) | |
785 | return ret; | |
786 | ||
787 | /* WaDisablePartialInstShootdown:chv */ | |
788 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, | |
789 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); | |
790 | ||
791 | /* WaDisableThreadStallDopClockGating:chv */ | |
792 | intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN, | |
793 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); | |
794 | ||
795 | /* WaDisableDopClockGating:chv (pre-production hw) */ | |
796 | intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, | |
797 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
798 | ||
799 | /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ | |
800 | intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, | |
801 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); | |
802 | ||
803 | intel_ring_advance(ring); | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
a4872ba6 | 808 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 809 | { |
78501eac | 810 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 811 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 812 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
813 | if (ret) |
814 | return ret; | |
a69ffdbf | 815 | |
61a563a2 AG |
816 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
817 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 818 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
819 | |
820 | /* We need to disable the AsyncFlip performance optimisations in order | |
821 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
822 | * programmed to '1' on all products. | |
8693a824 | 823 | * |
b3f797ac | 824 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 CW |
825 | */ |
826 | if (INTEL_INFO(dev)->gen >= 6) | |
827 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
828 | ||
f05bb0c7 | 829 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 830 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
831 | if (INTEL_INFO(dev)->gen == 6) |
832 | I915_WRITE(GFX_MODE, | |
aa83e30d | 833 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 834 | |
01fa0302 | 835 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
836 | if (IS_GEN7(dev)) |
837 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 838 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 839 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 840 | |
8d315287 | 841 | if (INTEL_INFO(dev)->gen >= 5) { |
9b1136d5 | 842 | ret = intel_init_pipe_control(ring); |
c6df541c CW |
843 | if (ret) |
844 | return ret; | |
845 | } | |
846 | ||
5e13a0c5 | 847 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
848 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
849 | * "If this bit is set, STCunit will have LRA as replacement | |
850 | * policy. [...] This bit must be reset. LRA replacement | |
851 | * policy is not supported." | |
852 | */ | |
853 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 854 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
855 | } |
856 | ||
6b26c86d DV |
857 | if (INTEL_INFO(dev)->gen >= 6) |
858 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 859 | |
040d2baa | 860 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 861 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 862 | |
8187a2b7 ZN |
863 | return ret; |
864 | } | |
865 | ||
a4872ba6 | 866 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 867 | { |
b45305fc | 868 | struct drm_device *dev = ring->dev; |
3e78998a BW |
869 | struct drm_i915_private *dev_priv = dev->dev_private; |
870 | ||
871 | if (dev_priv->semaphore_obj) { | |
872 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
873 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
874 | dev_priv->semaphore_obj = NULL; | |
875 | } | |
b45305fc | 876 | |
9b1136d5 | 877 | intel_fini_pipe_control(ring); |
c6df541c CW |
878 | } |
879 | ||
3e78998a BW |
880 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
881 | unsigned int num_dwords) | |
882 | { | |
883 | #define MBOX_UPDATE_DWORDS 8 | |
884 | struct drm_device *dev = signaller->dev; | |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | struct intel_engine_cs *waiter; | |
887 | int i, ret, num_rings; | |
888 | ||
889 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
890 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
891 | #undef MBOX_UPDATE_DWORDS | |
892 | ||
893 | ret = intel_ring_begin(signaller, num_dwords); | |
894 | if (ret) | |
895 | return ret; | |
896 | ||
897 | for_each_ring(waiter, dev_priv, i) { | |
898 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
899 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
900 | continue; | |
901 | ||
902 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); | |
903 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
904 | PIPE_CONTROL_QW_WRITE | | |
905 | PIPE_CONTROL_FLUSH_ENABLE); | |
906 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
907 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
908 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
909 | intel_ring_emit(signaller, 0); | |
910 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
911 | MI_SEMAPHORE_TARGET(waiter->id)); | |
912 | intel_ring_emit(signaller, 0); | |
913 | } | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
919 | unsigned int num_dwords) | |
920 | { | |
921 | #define MBOX_UPDATE_DWORDS 6 | |
922 | struct drm_device *dev = signaller->dev; | |
923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
924 | struct intel_engine_cs *waiter; | |
925 | int i, ret, num_rings; | |
926 | ||
927 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
928 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
929 | #undef MBOX_UPDATE_DWORDS | |
930 | ||
931 | ret = intel_ring_begin(signaller, num_dwords); | |
932 | if (ret) | |
933 | return ret; | |
934 | ||
935 | for_each_ring(waiter, dev_priv, i) { | |
936 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; | |
937 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
938 | continue; | |
939 | ||
940 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | | |
941 | MI_FLUSH_DW_OP_STOREDW); | |
942 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
943 | MI_FLUSH_DW_USE_GTT); | |
944 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
945 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
946 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
947 | MI_SEMAPHORE_TARGET(waiter->id)); | |
948 | intel_ring_emit(signaller, 0); | |
949 | } | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
a4872ba6 | 954 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 955 | unsigned int num_dwords) |
1ec14ad3 | 956 | { |
024a43e1 BW |
957 | struct drm_device *dev = signaller->dev; |
958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 959 | struct intel_engine_cs *useless; |
a1444b79 | 960 | int i, ret, num_rings; |
78325f2d | 961 | |
a1444b79 BW |
962 | #define MBOX_UPDATE_DWORDS 3 |
963 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
964 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
965 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
966 | |
967 | ret = intel_ring_begin(signaller, num_dwords); | |
968 | if (ret) | |
969 | return ret; | |
024a43e1 | 970 | |
78325f2d BW |
971 | for_each_ring(useless, dev_priv, i) { |
972 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
973 | if (mbox_reg != GEN6_NOSYNC) { | |
974 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); | |
975 | intel_ring_emit(signaller, mbox_reg); | |
976 | intel_ring_emit(signaller, signaller->outstanding_lazy_seqno); | |
78325f2d BW |
977 | } |
978 | } | |
024a43e1 | 979 | |
a1444b79 BW |
980 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
981 | if (num_rings % 2 == 0) | |
982 | intel_ring_emit(signaller, MI_NOOP); | |
983 | ||
024a43e1 | 984 | return 0; |
1ec14ad3 CW |
985 | } |
986 | ||
c8c99b0f BW |
987 | /** |
988 | * gen6_add_request - Update the semaphore mailbox registers | |
989 | * | |
990 | * @ring - ring that is adding a request | |
991 | * @seqno - return seqno stuck into the ring | |
992 | * | |
993 | * Update the mailbox registers in the *other* rings with the current seqno. | |
994 | * This acts like a signal in the canonical semaphore. | |
995 | */ | |
1ec14ad3 | 996 | static int |
a4872ba6 | 997 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 998 | { |
024a43e1 | 999 | int ret; |
52ed2325 | 1000 | |
707d9cf9 BW |
1001 | if (ring->semaphore.signal) |
1002 | ret = ring->semaphore.signal(ring, 4); | |
1003 | else | |
1004 | ret = intel_ring_begin(ring, 4); | |
1005 | ||
1ec14ad3 CW |
1006 | if (ret) |
1007 | return ret; | |
1008 | ||
1ec14ad3 CW |
1009 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1010 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1011 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 | 1012 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1013 | __intel_ring_advance(ring); |
1ec14ad3 | 1014 | |
1ec14ad3 CW |
1015 | return 0; |
1016 | } | |
1017 | ||
f72b3435 MK |
1018 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1019 | u32 seqno) | |
1020 | { | |
1021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1022 | return dev_priv->last_seqno < seqno; | |
1023 | } | |
1024 | ||
c8c99b0f BW |
1025 | /** |
1026 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1027 | * | |
1028 | * @waiter - ring that is waiting | |
1029 | * @signaller - ring which has, or will signal | |
1030 | * @seqno - seqno which the waiter will block on | |
1031 | */ | |
5ee426ca BW |
1032 | |
1033 | static int | |
1034 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
1035 | struct intel_engine_cs *signaller, | |
1036 | u32 seqno) | |
1037 | { | |
1038 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
1039 | int ret; | |
1040 | ||
1041 | ret = intel_ring_begin(waiter, 4); | |
1042 | if (ret) | |
1043 | return ret; | |
1044 | ||
1045 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1046 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1047 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1048 | MI_SEMAPHORE_SAD_GTE_SDD); |
1049 | intel_ring_emit(waiter, seqno); | |
1050 | intel_ring_emit(waiter, | |
1051 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1052 | intel_ring_emit(waiter, | |
1053 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1054 | intel_ring_advance(waiter); | |
1055 | return 0; | |
1056 | } | |
1057 | ||
c8c99b0f | 1058 | static int |
a4872ba6 OM |
1059 | gen6_ring_sync(struct intel_engine_cs *waiter, |
1060 | struct intel_engine_cs *signaller, | |
686cb5f9 | 1061 | u32 seqno) |
1ec14ad3 | 1062 | { |
c8c99b0f BW |
1063 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1064 | MI_SEMAPHORE_COMPARE | | |
1065 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1066 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1067 | int ret; | |
1ec14ad3 | 1068 | |
1500f7ea BW |
1069 | /* Throughout all of the GEM code, seqno passed implies our current |
1070 | * seqno is >= the last seqno executed. However for hardware the | |
1071 | * comparison is strictly greater than. | |
1072 | */ | |
1073 | seqno -= 1; | |
1074 | ||
ebc348b2 | 1075 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1076 | |
c8c99b0f | 1077 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
1078 | if (ret) |
1079 | return ret; | |
1080 | ||
f72b3435 MK |
1081 | /* If seqno wrap happened, omit the wait with no-ops */ |
1082 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1083 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1084 | intel_ring_emit(waiter, seqno); |
1085 | intel_ring_emit(waiter, 0); | |
1086 | intel_ring_emit(waiter, MI_NOOP); | |
1087 | } else { | |
1088 | intel_ring_emit(waiter, MI_NOOP); | |
1089 | intel_ring_emit(waiter, MI_NOOP); | |
1090 | intel_ring_emit(waiter, MI_NOOP); | |
1091 | intel_ring_emit(waiter, MI_NOOP); | |
1092 | } | |
c8c99b0f | 1093 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1094 | |
1095 | return 0; | |
1096 | } | |
1097 | ||
c6df541c CW |
1098 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1099 | do { \ | |
fcbc34e4 KG |
1100 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1101 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1102 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1103 | intel_ring_emit(ring__, 0); \ | |
1104 | intel_ring_emit(ring__, 0); \ | |
1105 | } while (0) | |
1106 | ||
1107 | static int | |
a4872ba6 | 1108 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 1109 | { |
18393f63 | 1110 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1111 | int ret; |
1112 | ||
1113 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1114 | * incoherent with writes to memory, i.e. completely fubar, | |
1115 | * so we need to use PIPE_NOTIFY instead. | |
1116 | * | |
1117 | * However, we also need to workaround the qword write | |
1118 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1119 | * memory before requesting an interrupt. | |
1120 | */ | |
1121 | ret = intel_ring_begin(ring, 32); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
fcbc34e4 | 1125 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1126 | PIPE_CONTROL_WRITE_FLUSH | |
1127 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1128 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 1129 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
1130 | intel_ring_emit(ring, 0); |
1131 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1132 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1133 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1134 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1135 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1136 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1137 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1138 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1139 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1140 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1141 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1142 | |
fcbc34e4 | 1143 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1144 | PIPE_CONTROL_WRITE_FLUSH | |
1145 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1146 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1147 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 1148 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c | 1149 | intel_ring_emit(ring, 0); |
09246732 | 1150 | __intel_ring_advance(ring); |
c6df541c | 1151 | |
c6df541c CW |
1152 | return 0; |
1153 | } | |
1154 | ||
4cd53c0c | 1155 | static u32 |
a4872ba6 | 1156 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1157 | { |
4cd53c0c DV |
1158 | /* Workaround to force correct ordering between irq and seqno writes on |
1159 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1160 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1161 | if (!lazy_coherency) { |
1162 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1163 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1164 | } | |
1165 | ||
4cd53c0c DV |
1166 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1167 | } | |
1168 | ||
8187a2b7 | 1169 | static u32 |
a4872ba6 | 1170 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1171 | { |
1ec14ad3 CW |
1172 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1173 | } | |
1174 | ||
b70ec5bf | 1175 | static void |
a4872ba6 | 1176 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1177 | { |
1178 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1179 | } | |
1180 | ||
c6df541c | 1181 | static u32 |
a4872ba6 | 1182 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1183 | { |
0d1aacac | 1184 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1185 | } |
1186 | ||
b70ec5bf | 1187 | static void |
a4872ba6 | 1188 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1189 | { |
0d1aacac | 1190 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1191 | } |
1192 | ||
e48d8634 | 1193 | static bool |
a4872ba6 | 1194 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1195 | { |
1196 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1197 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1198 | unsigned long flags; |
e48d8634 DV |
1199 | |
1200 | if (!dev->irq_enabled) | |
1201 | return false; | |
1202 | ||
7338aefa | 1203 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1204 | if (ring->irq_refcount++ == 0) |
480c8033 | 1205 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1206 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1207 | |
1208 | return true; | |
1209 | } | |
1210 | ||
1211 | static void | |
a4872ba6 | 1212 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1213 | { |
1214 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1215 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1216 | unsigned long flags; |
e48d8634 | 1217 | |
7338aefa | 1218 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1219 | if (--ring->irq_refcount == 0) |
480c8033 | 1220 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1221 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1222 | } |
1223 | ||
b13c2b96 | 1224 | static bool |
a4872ba6 | 1225 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1226 | { |
78501eac | 1227 | struct drm_device *dev = ring->dev; |
4640c4ff | 1228 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1229 | unsigned long flags; |
62fdfeaf | 1230 | |
b13c2b96 CW |
1231 | if (!dev->irq_enabled) |
1232 | return false; | |
1233 | ||
7338aefa | 1234 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1235 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1236 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1237 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1238 | POSTING_READ(IMR); | |
1239 | } | |
7338aefa | 1240 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1241 | |
1242 | return true; | |
62fdfeaf EA |
1243 | } |
1244 | ||
8187a2b7 | 1245 | static void |
a4872ba6 | 1246 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1247 | { |
78501eac | 1248 | struct drm_device *dev = ring->dev; |
4640c4ff | 1249 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1250 | unsigned long flags; |
62fdfeaf | 1251 | |
7338aefa | 1252 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1253 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1254 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1255 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1256 | POSTING_READ(IMR); | |
1257 | } | |
7338aefa | 1258 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1259 | } |
1260 | ||
c2798b19 | 1261 | static bool |
a4872ba6 | 1262 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1263 | { |
1264 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1265 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1266 | unsigned long flags; |
c2798b19 CW |
1267 | |
1268 | if (!dev->irq_enabled) | |
1269 | return false; | |
1270 | ||
7338aefa | 1271 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1272 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1273 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1274 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1275 | POSTING_READ16(IMR); | |
1276 | } | |
7338aefa | 1277 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1278 | |
1279 | return true; | |
1280 | } | |
1281 | ||
1282 | static void | |
a4872ba6 | 1283 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1284 | { |
1285 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1286 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1287 | unsigned long flags; |
c2798b19 | 1288 | |
7338aefa | 1289 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1290 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1291 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1292 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1293 | POSTING_READ16(IMR); | |
1294 | } | |
7338aefa | 1295 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1296 | } |
1297 | ||
a4872ba6 | 1298 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1299 | { |
4593010b | 1300 | struct drm_device *dev = ring->dev; |
4640c4ff | 1301 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1302 | u32 mmio = 0; |
1303 | ||
1304 | /* The ring status page addresses are no longer next to the rest of | |
1305 | * the ring registers as of gen7. | |
1306 | */ | |
1307 | if (IS_GEN7(dev)) { | |
1308 | switch (ring->id) { | |
96154f2f | 1309 | case RCS: |
4593010b EA |
1310 | mmio = RENDER_HWS_PGA_GEN7; |
1311 | break; | |
96154f2f | 1312 | case BCS: |
4593010b EA |
1313 | mmio = BLT_HWS_PGA_GEN7; |
1314 | break; | |
77fe2ff3 ZY |
1315 | /* |
1316 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1317 | * gcc switch check warning | |
1318 | */ | |
1319 | case VCS2: | |
96154f2f | 1320 | case VCS: |
4593010b EA |
1321 | mmio = BSD_HWS_PGA_GEN7; |
1322 | break; | |
4a3dd19d | 1323 | case VECS: |
9a8a2213 BW |
1324 | mmio = VEBOX_HWS_PGA_GEN7; |
1325 | break; | |
4593010b EA |
1326 | } |
1327 | } else if (IS_GEN6(ring->dev)) { | |
1328 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1329 | } else { | |
eb0d4b75 | 1330 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1331 | mmio = RING_HWS_PGA(ring->mmio_base); |
1332 | } | |
1333 | ||
78501eac CW |
1334 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1335 | POSTING_READ(mmio); | |
884020bf | 1336 | |
dc616b89 DL |
1337 | /* |
1338 | * Flush the TLB for this page | |
1339 | * | |
1340 | * FIXME: These two bits have disappeared on gen8, so a question | |
1341 | * arises: do we still need this and if so how should we go about | |
1342 | * invalidating the TLB? | |
1343 | */ | |
1344 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1345 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1346 | |
1347 | /* ring should be idle before issuing a sync flush*/ | |
1348 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1349 | ||
884020bf CW |
1350 | I915_WRITE(reg, |
1351 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1352 | INSTPM_SYNC_FLUSH)); | |
1353 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1354 | 1000)) | |
1355 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1356 | ring->name); | |
1357 | } | |
8187a2b7 ZN |
1358 | } |
1359 | ||
b72f3acb | 1360 | static int |
a4872ba6 | 1361 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1362 | u32 invalidate_domains, |
1363 | u32 flush_domains) | |
d1b851fc | 1364 | { |
b72f3acb CW |
1365 | int ret; |
1366 | ||
b72f3acb CW |
1367 | ret = intel_ring_begin(ring, 2); |
1368 | if (ret) | |
1369 | return ret; | |
1370 | ||
1371 | intel_ring_emit(ring, MI_FLUSH); | |
1372 | intel_ring_emit(ring, MI_NOOP); | |
1373 | intel_ring_advance(ring); | |
1374 | return 0; | |
d1b851fc ZN |
1375 | } |
1376 | ||
3cce469c | 1377 | static int |
a4872ba6 | 1378 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1379 | { |
3cce469c CW |
1380 | int ret; |
1381 | ||
1382 | ret = intel_ring_begin(ring, 4); | |
1383 | if (ret) | |
1384 | return ret; | |
6f392d54 | 1385 | |
3cce469c CW |
1386 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1387 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 1388 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c | 1389 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1390 | __intel_ring_advance(ring); |
d1b851fc | 1391 | |
3cce469c | 1392 | return 0; |
d1b851fc ZN |
1393 | } |
1394 | ||
0f46832f | 1395 | static bool |
a4872ba6 | 1396 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1397 | { |
1398 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1399 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1400 | unsigned long flags; |
0f46832f CW |
1401 | |
1402 | if (!dev->irq_enabled) | |
1403 | return false; | |
1404 | ||
7338aefa | 1405 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1406 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1407 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1408 | I915_WRITE_IMR(ring, |
1409 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1410 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1411 | else |
1412 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1413 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1414 | } |
7338aefa | 1415 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1416 | |
1417 | return true; | |
1418 | } | |
1419 | ||
1420 | static void | |
a4872ba6 | 1421 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1422 | { |
1423 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1424 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1425 | unsigned long flags; |
0f46832f | 1426 | |
7338aefa | 1427 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1428 | if (--ring->irq_refcount == 0) { |
040d2baa | 1429 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1430 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1431 | else |
1432 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1433 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1434 | } |
7338aefa | 1435 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1436 | } |
1437 | ||
a19d2933 | 1438 | static bool |
a4872ba6 | 1439 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1440 | { |
1441 | struct drm_device *dev = ring->dev; | |
1442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1443 | unsigned long flags; | |
1444 | ||
1445 | if (!dev->irq_enabled) | |
1446 | return false; | |
1447 | ||
59cdb63d | 1448 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1449 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1450 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1451 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1452 | } |
59cdb63d | 1453 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1454 | |
1455 | return true; | |
1456 | } | |
1457 | ||
1458 | static void | |
a4872ba6 | 1459 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1460 | { |
1461 | struct drm_device *dev = ring->dev; | |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1463 | unsigned long flags; | |
1464 | ||
1465 | if (!dev->irq_enabled) | |
1466 | return; | |
1467 | ||
59cdb63d | 1468 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1469 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1470 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1471 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1472 | } |
59cdb63d | 1473 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1474 | } |
1475 | ||
abd58f01 | 1476 | static bool |
a4872ba6 | 1477 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1478 | { |
1479 | struct drm_device *dev = ring->dev; | |
1480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1481 | unsigned long flags; | |
1482 | ||
1483 | if (!dev->irq_enabled) | |
1484 | return false; | |
1485 | ||
1486 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1487 | if (ring->irq_refcount++ == 0) { | |
1488 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1489 | I915_WRITE_IMR(ring, | |
1490 | ~(ring->irq_enable_mask | | |
1491 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1492 | } else { | |
1493 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1494 | } | |
1495 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1496 | } | |
1497 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1498 | ||
1499 | return true; | |
1500 | } | |
1501 | ||
1502 | static void | |
a4872ba6 | 1503 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1504 | { |
1505 | struct drm_device *dev = ring->dev; | |
1506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1507 | unsigned long flags; | |
1508 | ||
1509 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1510 | if (--ring->irq_refcount == 0) { | |
1511 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1512 | I915_WRITE_IMR(ring, | |
1513 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1514 | } else { | |
1515 | I915_WRITE_IMR(ring, ~0); | |
1516 | } | |
1517 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1518 | } | |
1519 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1520 | } | |
1521 | ||
d1b851fc | 1522 | static int |
a4872ba6 | 1523 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1524 | u64 offset, u32 length, |
d7d4eedd | 1525 | unsigned flags) |
d1b851fc | 1526 | { |
e1f99ce6 | 1527 | int ret; |
78501eac | 1528 | |
e1f99ce6 CW |
1529 | ret = intel_ring_begin(ring, 2); |
1530 | if (ret) | |
1531 | return ret; | |
1532 | ||
78501eac | 1533 | intel_ring_emit(ring, |
65f56876 CW |
1534 | MI_BATCH_BUFFER_START | |
1535 | MI_BATCH_GTT | | |
d7d4eedd | 1536 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1537 | intel_ring_emit(ring, offset); |
78501eac CW |
1538 | intel_ring_advance(ring); |
1539 | ||
d1b851fc ZN |
1540 | return 0; |
1541 | } | |
1542 | ||
b45305fc DV |
1543 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1544 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1545 | static int |
a4872ba6 | 1546 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1547 | u64 offset, u32 len, |
d7d4eedd | 1548 | unsigned flags) |
62fdfeaf | 1549 | { |
c4e7a414 | 1550 | int ret; |
62fdfeaf | 1551 | |
b45305fc DV |
1552 | if (flags & I915_DISPATCH_PINNED) { |
1553 | ret = intel_ring_begin(ring, 4); | |
1554 | if (ret) | |
1555 | return ret; | |
62fdfeaf | 1556 | |
b45305fc DV |
1557 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1558 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1559 | intel_ring_emit(ring, offset + len - 8); | |
1560 | intel_ring_emit(ring, MI_NOOP); | |
1561 | intel_ring_advance(ring); | |
1562 | } else { | |
0d1aacac | 1563 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1564 | |
1565 | if (len > I830_BATCH_LIMIT) | |
1566 | return -ENOSPC; | |
1567 | ||
1568 | ret = intel_ring_begin(ring, 9+3); | |
1569 | if (ret) | |
1570 | return ret; | |
1571 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1572 | * scratch bo area (so that the CS never stumbles over its tlb | |
1573 | * invalidation bug) ... */ | |
1574 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1575 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1576 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1577 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1578 | intel_ring_emit(ring, 0); | |
1579 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1580 | intel_ring_emit(ring, cs_offset); | |
1581 | intel_ring_emit(ring, 0); | |
1582 | intel_ring_emit(ring, 4096); | |
1583 | intel_ring_emit(ring, offset); | |
1584 | intel_ring_emit(ring, MI_FLUSH); | |
1585 | ||
1586 | /* ... and execute it. */ | |
1587 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1588 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1589 | intel_ring_emit(ring, cs_offset + len - 8); | |
1590 | intel_ring_advance(ring); | |
1591 | } | |
e1f99ce6 | 1592 | |
fb3256da DV |
1593 | return 0; |
1594 | } | |
1595 | ||
1596 | static int | |
a4872ba6 | 1597 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1598 | u64 offset, u32 len, |
d7d4eedd | 1599 | unsigned flags) |
fb3256da DV |
1600 | { |
1601 | int ret; | |
1602 | ||
1603 | ret = intel_ring_begin(ring, 2); | |
1604 | if (ret) | |
1605 | return ret; | |
1606 | ||
65f56876 | 1607 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1608 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1609 | intel_ring_advance(ring); |
62fdfeaf | 1610 | |
62fdfeaf EA |
1611 | return 0; |
1612 | } | |
1613 | ||
a4872ba6 | 1614 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1615 | { |
05394f39 | 1616 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1617 | |
8187a2b7 ZN |
1618 | obj = ring->status_page.obj; |
1619 | if (obj == NULL) | |
62fdfeaf | 1620 | return; |
62fdfeaf | 1621 | |
9da3da66 | 1622 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1623 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1624 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1625 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1626 | } |
1627 | ||
a4872ba6 | 1628 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1629 | { |
05394f39 | 1630 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1631 | |
e3efda49 | 1632 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1633 | unsigned flags; |
e3efda49 | 1634 | int ret; |
e4ffd173 | 1635 | |
e3efda49 CW |
1636 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1637 | if (obj == NULL) { | |
1638 | DRM_ERROR("Failed to allocate status page\n"); | |
1639 | return -ENOMEM; | |
1640 | } | |
62fdfeaf | 1641 | |
e3efda49 CW |
1642 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1643 | if (ret) | |
1644 | goto err_unref; | |
1645 | ||
1f767e02 CW |
1646 | flags = 0; |
1647 | if (!HAS_LLC(ring->dev)) | |
1648 | /* On g33, we cannot place HWS above 256MiB, so | |
1649 | * restrict its pinning to the low mappable arena. | |
1650 | * Though this restriction is not documented for | |
1651 | * gen4, gen5, or byt, they also behave similarly | |
1652 | * and hang if the HWS is placed at the top of the | |
1653 | * GTT. To generalise, it appears that all !llc | |
1654 | * platforms have issues with us placing the HWS | |
1655 | * above the mappable region (even though we never | |
1656 | * actualy map it). | |
1657 | */ | |
1658 | flags |= PIN_MAPPABLE; | |
1659 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1660 | if (ret) { |
1661 | err_unref: | |
1662 | drm_gem_object_unreference(&obj->base); | |
1663 | return ret; | |
1664 | } | |
1665 | ||
1666 | ring->status_page.obj = obj; | |
1667 | } | |
62fdfeaf | 1668 | |
f343c5f6 | 1669 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1670 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1671 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1672 | |
8187a2b7 ZN |
1673 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1674 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1675 | |
1676 | return 0; | |
62fdfeaf EA |
1677 | } |
1678 | ||
a4872ba6 | 1679 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1680 | { |
1681 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1682 | |
1683 | if (!dev_priv->status_page_dmah) { | |
1684 | dev_priv->status_page_dmah = | |
1685 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1686 | if (!dev_priv->status_page_dmah) | |
1687 | return -ENOMEM; | |
1688 | } | |
1689 | ||
6b8294a4 CW |
1690 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1691 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
84c2377f | 1696 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 OM |
1697 | { |
1698 | if (!ringbuf->obj) | |
1699 | return; | |
1700 | ||
1701 | iounmap(ringbuf->virtual_start); | |
1702 | i915_gem_object_ggtt_unpin(ringbuf->obj); | |
1703 | drm_gem_object_unreference(&ringbuf->obj->base); | |
1704 | ringbuf->obj = NULL; | |
1705 | } | |
1706 | ||
84c2377f OM |
1707 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1708 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1709 | { |
e3efda49 | 1710 | struct drm_i915_private *dev_priv = to_i915(dev); |
05394f39 | 1711 | struct drm_i915_gem_object *obj; |
dd785e35 CW |
1712 | int ret; |
1713 | ||
2919d291 | 1714 | if (ringbuf->obj) |
e3efda49 | 1715 | return 0; |
62fdfeaf | 1716 | |
ebc052e0 CW |
1717 | obj = NULL; |
1718 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1719 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1720 | if (obj == NULL) |
93b0a4e0 | 1721 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1722 | if (obj == NULL) |
1723 | return -ENOMEM; | |
8187a2b7 | 1724 | |
24f3a8cf AG |
1725 | /* mark ring buffers as read-only from GPU side by default */ |
1726 | obj->gt_ro = 1; | |
1727 | ||
1ec9e26d | 1728 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
dd785e35 CW |
1729 | if (ret) |
1730 | goto err_unref; | |
62fdfeaf | 1731 | |
3eef8918 CW |
1732 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1733 | if (ret) | |
1734 | goto err_unpin; | |
1735 | ||
93b0a4e0 | 1736 | ringbuf->virtual_start = |
f343c5f6 | 1737 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
93b0a4e0 OM |
1738 | ringbuf->size); |
1739 | if (ringbuf->virtual_start == NULL) { | |
8187a2b7 | 1740 | ret = -EINVAL; |
dd785e35 | 1741 | goto err_unpin; |
62fdfeaf EA |
1742 | } |
1743 | ||
93b0a4e0 | 1744 | ringbuf->obj = obj; |
e3efda49 CW |
1745 | return 0; |
1746 | ||
1747 | err_unpin: | |
1748 | i915_gem_object_ggtt_unpin(obj); | |
1749 | err_unref: | |
1750 | drm_gem_object_unreference(&obj->base); | |
1751 | return ret; | |
1752 | } | |
1753 | ||
1754 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1755 | struct intel_engine_cs *ring) |
e3efda49 | 1756 | { |
8ee14975 | 1757 | struct intel_ringbuffer *ringbuf = ring->buffer; |
e3efda49 CW |
1758 | int ret; |
1759 | ||
8ee14975 OM |
1760 | if (ringbuf == NULL) { |
1761 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1762 | if (!ringbuf) | |
1763 | return -ENOMEM; | |
1764 | ring->buffer = ringbuf; | |
1765 | } | |
1766 | ||
e3efda49 CW |
1767 | ring->dev = dev; |
1768 | INIT_LIST_HEAD(&ring->active_list); | |
1769 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 1770 | INIT_LIST_HEAD(&ring->execlist_queue); |
93b0a4e0 | 1771 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1772 | ringbuf->ring = ring; |
ebc348b2 | 1773 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1774 | |
1775 | init_waitqueue_head(&ring->irq_queue); | |
1776 | ||
1777 | if (I915_NEED_GFX_HWS(dev)) { | |
1778 | ret = init_status_page(ring); | |
1779 | if (ret) | |
8ee14975 | 1780 | goto error; |
e3efda49 CW |
1781 | } else { |
1782 | BUG_ON(ring->id != RCS); | |
1783 | ret = init_phys_status_page(ring); | |
1784 | if (ret) | |
8ee14975 | 1785 | goto error; |
e3efda49 CW |
1786 | } |
1787 | ||
2919d291 | 1788 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
e3efda49 CW |
1789 | if (ret) { |
1790 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret); | |
8ee14975 | 1791 | goto error; |
e3efda49 | 1792 | } |
62fdfeaf | 1793 | |
55249baa CW |
1794 | /* Workaround an erratum on the i830 which causes a hang if |
1795 | * the TAIL pointer points to within the last 2 cachelines | |
1796 | * of the buffer. | |
1797 | */ | |
93b0a4e0 | 1798 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1799 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1800 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1801 | |
44e895a8 BV |
1802 | ret = i915_cmd_parser_init_ring(ring); |
1803 | if (ret) | |
8ee14975 OM |
1804 | goto error; |
1805 | ||
1806 | ret = ring->init(ring); | |
1807 | if (ret) | |
1808 | goto error; | |
1809 | ||
1810 | return 0; | |
351e3db2 | 1811 | |
8ee14975 OM |
1812 | error: |
1813 | kfree(ringbuf); | |
1814 | ring->buffer = NULL; | |
1815 | return ret; | |
62fdfeaf EA |
1816 | } |
1817 | ||
a4872ba6 | 1818 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1819 | { |
e3efda49 | 1820 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
93b0a4e0 | 1821 | struct intel_ringbuffer *ringbuf = ring->buffer; |
33626e6a | 1822 | |
93b0a4e0 | 1823 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1824 | return; |
1825 | ||
e3efda49 | 1826 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1827 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1828 | |
2919d291 | 1829 | intel_destroy_ringbuffer_obj(ringbuf); |
3d57e5bd BW |
1830 | ring->preallocated_lazy_request = NULL; |
1831 | ring->outstanding_lazy_seqno = 0; | |
78501eac | 1832 | |
8d19215b ZN |
1833 | if (ring->cleanup) |
1834 | ring->cleanup(ring); | |
1835 | ||
78501eac | 1836 | cleanup_status_page(ring); |
44e895a8 BV |
1837 | |
1838 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1839 | |
93b0a4e0 | 1840 | kfree(ringbuf); |
8ee14975 | 1841 | ring->buffer = NULL; |
62fdfeaf EA |
1842 | } |
1843 | ||
a4872ba6 | 1844 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1845 | { |
93b0a4e0 | 1846 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1847 | struct drm_i915_gem_request *request; |
1cf0ba14 | 1848 | u32 seqno = 0; |
a71d8d94 CW |
1849 | int ret; |
1850 | ||
93b0a4e0 OM |
1851 | if (ringbuf->last_retired_head != -1) { |
1852 | ringbuf->head = ringbuf->last_retired_head; | |
1853 | ringbuf->last_retired_head = -1; | |
1f70999f | 1854 | |
82e104cc | 1855 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1856 | if (ringbuf->space >= n) |
a71d8d94 CW |
1857 | return 0; |
1858 | } | |
1859 | ||
1860 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1861 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1862 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1863 | seqno = request->seqno; |
1864 | break; | |
1865 | } | |
a71d8d94 CW |
1866 | } |
1867 | ||
1868 | if (seqno == 0) | |
1869 | return -ENOSPC; | |
1870 | ||
1f70999f | 1871 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1872 | if (ret) |
1873 | return ret; | |
1874 | ||
1cf0ba14 | 1875 | i915_gem_retire_requests_ring(ring); |
93b0a4e0 OM |
1876 | ringbuf->head = ringbuf->last_retired_head; |
1877 | ringbuf->last_retired_head = -1; | |
a71d8d94 | 1878 | |
82e104cc | 1879 | ringbuf->space = intel_ring_space(ringbuf); |
a71d8d94 CW |
1880 | return 0; |
1881 | } | |
1882 | ||
a4872ba6 | 1883 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1884 | { |
78501eac | 1885 | struct drm_device *dev = ring->dev; |
cae5852d | 1886 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1887 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1888 | unsigned long end; |
a71d8d94 | 1889 | int ret; |
c7dca47b | 1890 | |
a71d8d94 CW |
1891 | ret = intel_ring_wait_request(ring, n); |
1892 | if (ret != -ENOSPC) | |
1893 | return ret; | |
1894 | ||
09246732 CW |
1895 | /* force the tail write in case we have been skipping them */ |
1896 | __intel_ring_advance(ring); | |
1897 | ||
63ed2cb2 DV |
1898 | /* With GEM the hangcheck timer should kick us out of the loop, |
1899 | * leaving it early runs the risk of corrupting GEM state (due | |
1900 | * to running on almost untested codepaths). But on resume | |
1901 | * timers don't work yet, so prevent a complete hang in that | |
1902 | * case by choosing an insanely large timeout. */ | |
1903 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1904 | |
dcfe0506 | 1905 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1906 | do { |
93b0a4e0 | 1907 | ringbuf->head = I915_READ_HEAD(ring); |
82e104cc | 1908 | ringbuf->space = intel_ring_space(ringbuf); |
93b0a4e0 | 1909 | if (ringbuf->space >= n) { |
dcfe0506 CW |
1910 | ret = 0; |
1911 | break; | |
62fdfeaf EA |
1912 | } |
1913 | ||
fb19e2ac DV |
1914 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && |
1915 | dev->primary->master) { | |
62fdfeaf EA |
1916 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1917 | if (master_priv->sarea_priv) | |
1918 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1919 | } | |
d1b851fc | 1920 | |
e60a0b10 | 1921 | msleep(1); |
d6b2c790 | 1922 | |
dcfe0506 CW |
1923 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1924 | ret = -ERESTARTSYS; | |
1925 | break; | |
1926 | } | |
1927 | ||
33196ded DV |
1928 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1929 | dev_priv->mm.interruptible); | |
d6b2c790 | 1930 | if (ret) |
dcfe0506 CW |
1931 | break; |
1932 | ||
1933 | if (time_after(jiffies, end)) { | |
1934 | ret = -EBUSY; | |
1935 | break; | |
1936 | } | |
1937 | } while (1); | |
db53a302 | 1938 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1939 | return ret; |
8187a2b7 | 1940 | } |
62fdfeaf | 1941 | |
a4872ba6 | 1942 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1943 | { |
1944 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1945 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1946 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1947 | |
93b0a4e0 | 1948 | if (ringbuf->space < rem) { |
3e960501 CW |
1949 | int ret = ring_wait_for_space(ring, rem); |
1950 | if (ret) | |
1951 | return ret; | |
1952 | } | |
1953 | ||
93b0a4e0 | 1954 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1955 | rem /= 4; |
1956 | while (rem--) | |
1957 | iowrite32(MI_NOOP, virt++); | |
1958 | ||
93b0a4e0 | 1959 | ringbuf->tail = 0; |
82e104cc | 1960 | ringbuf->space = intel_ring_space(ringbuf); |
3e960501 CW |
1961 | |
1962 | return 0; | |
1963 | } | |
1964 | ||
a4872ba6 | 1965 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 CW |
1966 | { |
1967 | u32 seqno; | |
1968 | int ret; | |
1969 | ||
1970 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1971 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1972 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1973 | if (ret) |
1974 | return ret; | |
1975 | } | |
1976 | ||
1977 | /* Wait upon the last request to be completed */ | |
1978 | if (list_empty(&ring->request_list)) | |
1979 | return 0; | |
1980 | ||
1981 | seqno = list_entry(ring->request_list.prev, | |
1982 | struct drm_i915_gem_request, | |
1983 | list)->seqno; | |
1984 | ||
1985 | return i915_wait_seqno(ring, seqno); | |
1986 | } | |
1987 | ||
9d773091 | 1988 | static int |
a4872ba6 | 1989 | intel_ring_alloc_seqno(struct intel_engine_cs *ring) |
9d773091 | 1990 | { |
1823521d | 1991 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1992 | return 0; |
1993 | ||
3c0e234c CW |
1994 | if (ring->preallocated_lazy_request == NULL) { |
1995 | struct drm_i915_gem_request *request; | |
1996 | ||
1997 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1998 | if (request == NULL) | |
1999 | return -ENOMEM; | |
2000 | ||
2001 | ring->preallocated_lazy_request = request; | |
2002 | } | |
2003 | ||
1823521d | 2004 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
2005 | } |
2006 | ||
a4872ba6 | 2007 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 2008 | int bytes) |
cbcc80df | 2009 | { |
93b0a4e0 | 2010 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
2011 | int ret; |
2012 | ||
93b0a4e0 | 2013 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
2014 | ret = intel_wrap_ring_buffer(ring); |
2015 | if (unlikely(ret)) | |
2016 | return ret; | |
2017 | } | |
2018 | ||
93b0a4e0 | 2019 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
2020 | ret = ring_wait_for_space(ring, bytes); |
2021 | if (unlikely(ret)) | |
2022 | return ret; | |
2023 | } | |
2024 | ||
cbcc80df MK |
2025 | return 0; |
2026 | } | |
2027 | ||
a4872ba6 | 2028 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 2029 | int num_dwords) |
8187a2b7 | 2030 | { |
4640c4ff | 2031 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 2032 | int ret; |
78501eac | 2033 | |
33196ded DV |
2034 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2035 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2036 | if (ret) |
2037 | return ret; | |
21dd3734 | 2038 | |
304d695c CW |
2039 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2040 | if (ret) | |
2041 | return ret; | |
2042 | ||
9d773091 CW |
2043 | /* Preallocate the olr before touching the ring */ |
2044 | ret = intel_ring_alloc_seqno(ring); | |
2045 | if (ret) | |
2046 | return ret; | |
2047 | ||
ee1b1e5e | 2048 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2049 | return 0; |
8187a2b7 | 2050 | } |
78501eac | 2051 | |
753b1ad4 | 2052 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 2053 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 2054 | { |
ee1b1e5e | 2055 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2056 | int ret; |
2057 | ||
2058 | if (num_dwords == 0) | |
2059 | return 0; | |
2060 | ||
18393f63 | 2061 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
2062 | ret = intel_ring_begin(ring, num_dwords); |
2063 | if (ret) | |
2064 | return ret; | |
2065 | ||
2066 | while (num_dwords--) | |
2067 | intel_ring_emit(ring, MI_NOOP); | |
2068 | ||
2069 | intel_ring_advance(ring); | |
2070 | ||
2071 | return 0; | |
2072 | } | |
2073 | ||
a4872ba6 | 2074 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2075 | { |
3b2cc8ab OM |
2076 | struct drm_device *dev = ring->dev; |
2077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2078 | |
1823521d | 2079 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 2080 | |
3b2cc8ab | 2081 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2082 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2083 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2084 | if (HAS_VEBOX(dev)) |
5020150b | 2085 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2086 | } |
d97ed339 | 2087 | |
f7e98ad4 | 2088 | ring->set_seqno(ring, seqno); |
92cab734 | 2089 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2090 | } |
62fdfeaf | 2091 | |
a4872ba6 | 2092 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2093 | u32 value) |
881f47b6 | 2094 | { |
4640c4ff | 2095 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2096 | |
2097 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2098 | |
2099 | /* Disable notification that the ring is IDLE. The GT | |
2100 | * will then assume that it is busy and bring it out of rc6. | |
2101 | */ | |
0206e353 | 2102 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2103 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2104 | ||
2105 | /* Clear the context id. Here be magic! */ | |
2106 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2107 | |
12f55818 | 2108 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2109 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2110 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2111 | 50)) | |
2112 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2113 | |
12f55818 | 2114 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2115 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2116 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2117 | ||
2118 | /* Let the ring send IDLE messages to the GT again, | |
2119 | * and so let it sleep to conserve power when idle. | |
2120 | */ | |
0206e353 | 2121 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2122 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2123 | } |
2124 | ||
a4872ba6 | 2125 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2126 | u32 invalidate, u32 flush) |
881f47b6 | 2127 | { |
71a77e07 | 2128 | uint32_t cmd; |
b72f3acb CW |
2129 | int ret; |
2130 | ||
b72f3acb CW |
2131 | ret = intel_ring_begin(ring, 4); |
2132 | if (ret) | |
2133 | return ret; | |
2134 | ||
71a77e07 | 2135 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2136 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2137 | cmd += 1; | |
9a289771 JB |
2138 | /* |
2139 | * Bspec vol 1c.5 - video engine command streamer: | |
2140 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2141 | * operation is complete. This bit is only valid when the | |
2142 | * Post-Sync Operation field is a value of 1h or 3h." | |
2143 | */ | |
71a77e07 | 2144 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
2145 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
2146 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 2147 | intel_ring_emit(ring, cmd); |
9a289771 | 2148 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2149 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2150 | intel_ring_emit(ring, 0); /* upper addr */ | |
2151 | intel_ring_emit(ring, 0); /* value */ | |
2152 | } else { | |
2153 | intel_ring_emit(ring, 0); | |
2154 | intel_ring_emit(ring, MI_NOOP); | |
2155 | } | |
b72f3acb CW |
2156 | intel_ring_advance(ring); |
2157 | return 0; | |
881f47b6 XH |
2158 | } |
2159 | ||
1c7a0623 | 2160 | static int |
a4872ba6 | 2161 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2162 | u64 offset, u32 len, |
1c7a0623 BW |
2163 | unsigned flags) |
2164 | { | |
896ab1a5 | 2165 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2166 | int ret; |
2167 | ||
2168 | ret = intel_ring_begin(ring, 4); | |
2169 | if (ret) | |
2170 | return ret; | |
2171 | ||
2172 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2173 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2174 | intel_ring_emit(ring, lower_32_bits(offset)); |
2175 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2176 | intel_ring_emit(ring, MI_NOOP); |
2177 | intel_ring_advance(ring); | |
2178 | ||
2179 | return 0; | |
2180 | } | |
2181 | ||
d7d4eedd | 2182 | static int |
a4872ba6 | 2183 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2184 | u64 offset, u32 len, |
d7d4eedd CW |
2185 | unsigned flags) |
2186 | { | |
2187 | int ret; | |
2188 | ||
2189 | ret = intel_ring_begin(ring, 2); | |
2190 | if (ret) | |
2191 | return ret; | |
2192 | ||
2193 | intel_ring_emit(ring, | |
2194 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
2195 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
2196 | /* bit0-7 is the length on GEN6+ */ | |
2197 | intel_ring_emit(ring, offset); | |
2198 | intel_ring_advance(ring); | |
2199 | ||
2200 | return 0; | |
2201 | } | |
2202 | ||
881f47b6 | 2203 | static int |
a4872ba6 | 2204 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2205 | u64 offset, u32 len, |
d7d4eedd | 2206 | unsigned flags) |
881f47b6 | 2207 | { |
0206e353 | 2208 | int ret; |
ab6f8e32 | 2209 | |
0206e353 AJ |
2210 | ret = intel_ring_begin(ring, 2); |
2211 | if (ret) | |
2212 | return ret; | |
e1f99ce6 | 2213 | |
d7d4eedd CW |
2214 | intel_ring_emit(ring, |
2215 | MI_BATCH_BUFFER_START | | |
2216 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2217 | /* bit0-7 is the length on GEN6+ */ |
2218 | intel_ring_emit(ring, offset); | |
2219 | intel_ring_advance(ring); | |
ab6f8e32 | 2220 | |
0206e353 | 2221 | return 0; |
881f47b6 XH |
2222 | } |
2223 | ||
549f7365 CW |
2224 | /* Blitter support (SandyBridge+) */ |
2225 | ||
a4872ba6 | 2226 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2227 | u32 invalidate, u32 flush) |
8d19215b | 2228 | { |
fd3da6c9 | 2229 | struct drm_device *dev = ring->dev; |
71a77e07 | 2230 | uint32_t cmd; |
b72f3acb CW |
2231 | int ret; |
2232 | ||
6a233c78 | 2233 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2234 | if (ret) |
2235 | return ret; | |
2236 | ||
71a77e07 | 2237 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2238 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2239 | cmd += 1; | |
9a289771 JB |
2240 | /* |
2241 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2242 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2243 | * operation is complete. This bit is only valid when the | |
2244 | * Post-Sync Operation field is a value of 1h or 3h." | |
2245 | */ | |
71a77e07 | 2246 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2247 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2248 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2249 | intel_ring_emit(ring, cmd); |
9a289771 | 2250 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2251 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2252 | intel_ring_emit(ring, 0); /* upper addr */ | |
2253 | intel_ring_emit(ring, 0); /* value */ | |
2254 | } else { | |
2255 | intel_ring_emit(ring, 0); | |
2256 | intel_ring_emit(ring, MI_NOOP); | |
2257 | } | |
b72f3acb | 2258 | intel_ring_advance(ring); |
fd3da6c9 | 2259 | |
9688ecad | 2260 | if (IS_GEN7(dev) && !invalidate && flush) |
fd3da6c9 RV |
2261 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); |
2262 | ||
b72f3acb | 2263 | return 0; |
8d19215b ZN |
2264 | } |
2265 | ||
5c1143bb XH |
2266 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2267 | { | |
4640c4ff | 2268 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2269 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2270 | struct drm_i915_gem_object *obj; |
2271 | int ret; | |
5c1143bb | 2272 | |
59465b5f DV |
2273 | ring->name = "render ring"; |
2274 | ring->id = RCS; | |
2275 | ring->mmio_base = RENDER_RING_BASE; | |
2276 | ||
707d9cf9 | 2277 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2278 | if (i915_semaphore_is_enabled(dev)) { |
2279 | obj = i915_gem_alloc_object(dev, 4096); | |
2280 | if (obj == NULL) { | |
2281 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2282 | i915.semaphores = 0; | |
2283 | } else { | |
2284 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2285 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2286 | if (ret != 0) { | |
2287 | drm_gem_object_unreference(&obj->base); | |
2288 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2289 | i915.semaphores = 0; | |
2290 | } else | |
2291 | dev_priv->semaphore_obj = obj; | |
2292 | } | |
2293 | } | |
00e1e623 VS |
2294 | if (IS_CHERRYVIEW(dev)) |
2295 | ring->init_context = chv_init_workarounds; | |
2296 | else | |
2297 | ring->init_context = bdw_init_workarounds; | |
707d9cf9 BW |
2298 | ring->add_request = gen6_add_request; |
2299 | ring->flush = gen8_render_ring_flush; | |
2300 | ring->irq_get = gen8_ring_get_irq; | |
2301 | ring->irq_put = gen8_ring_put_irq; | |
2302 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2303 | ring->get_seqno = gen6_ring_get_seqno; | |
2304 | ring->set_seqno = ring_set_seqno; | |
2305 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2306 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2307 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2308 | ring->semaphore.signal = gen8_rcs_signal; |
2309 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2310 | } |
2311 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2312 | ring->add_request = gen6_add_request; |
4772eaeb | 2313 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2314 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2315 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2316 | ring->irq_get = gen6_ring_get_irq; |
2317 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2318 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2319 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2320 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2321 | if (i915_semaphore_is_enabled(dev)) { |
2322 | ring->semaphore.sync_to = gen6_ring_sync; | |
2323 | ring->semaphore.signal = gen6_signal; | |
2324 | /* | |
2325 | * The current semaphore is only applied on pre-gen8 | |
2326 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2327 | * platform. So the semaphore between RCS and VCS2 is | |
2328 | * initialized as INVALID. Gen8 will initialize the | |
2329 | * sema between VCS2 and RCS later. | |
2330 | */ | |
2331 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2332 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2333 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2334 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2335 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2336 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2337 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2338 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2339 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2340 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2341 | } | |
c6df541c CW |
2342 | } else if (IS_GEN5(dev)) { |
2343 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2344 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2345 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2346 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2347 | ring->irq_get = gen5_ring_get_irq; |
2348 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2349 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2350 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2351 | } else { |
8620a3a9 | 2352 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2353 | if (INTEL_INFO(dev)->gen < 4) |
2354 | ring->flush = gen2_render_ring_flush; | |
2355 | else | |
2356 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2357 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2358 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2359 | if (IS_GEN2(dev)) { |
2360 | ring->irq_get = i8xx_ring_get_irq; | |
2361 | ring->irq_put = i8xx_ring_put_irq; | |
2362 | } else { | |
2363 | ring->irq_get = i9xx_ring_get_irq; | |
2364 | ring->irq_put = i9xx_ring_put_irq; | |
2365 | } | |
e3670319 | 2366 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2367 | } |
59465b5f | 2368 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2369 | |
d7d4eedd CW |
2370 | if (IS_HASWELL(dev)) |
2371 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2372 | else if (IS_GEN8(dev)) |
2373 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2374 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2375 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2376 | else if (INTEL_INFO(dev)->gen >= 4) | |
2377 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2378 | else if (IS_I830(dev) || IS_845G(dev)) | |
2379 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2380 | else | |
2381 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2382 | ring->init = init_render_ring; |
2383 | ring->cleanup = render_ring_cleanup; | |
2384 | ||
b45305fc DV |
2385 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2386 | if (HAS_BROKEN_CS_TLB(dev)) { | |
b45305fc DV |
2387 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); |
2388 | if (obj == NULL) { | |
2389 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2390 | return -ENOMEM; | |
2391 | } | |
2392 | ||
be1fa129 | 2393 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2394 | if (ret != 0) { |
2395 | drm_gem_object_unreference(&obj->base); | |
2396 | DRM_ERROR("Failed to ping batch bo\n"); | |
2397 | return ret; | |
2398 | } | |
2399 | ||
0d1aacac CW |
2400 | ring->scratch.obj = obj; |
2401 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2402 | } |
2403 | ||
1ec14ad3 | 2404 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
2405 | } |
2406 | ||
e8616b6c CW |
2407 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
2408 | { | |
4640c4ff | 2409 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2410 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
8ee14975 | 2411 | struct intel_ringbuffer *ringbuf = ring->buffer; |
6b8294a4 | 2412 | int ret; |
e8616b6c | 2413 | |
8ee14975 OM |
2414 | if (ringbuf == NULL) { |
2415 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
2416 | if (!ringbuf) | |
2417 | return -ENOMEM; | |
2418 | ring->buffer = ringbuf; | |
2419 | } | |
2420 | ||
59465b5f DV |
2421 | ring->name = "render ring"; |
2422 | ring->id = RCS; | |
2423 | ring->mmio_base = RENDER_RING_BASE; | |
2424 | ||
e8616b6c | 2425 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a | 2426 | /* non-kms not supported on gen6+ */ |
8ee14975 OM |
2427 | ret = -ENODEV; |
2428 | goto err_ringbuf; | |
e8616b6c | 2429 | } |
28f0cbf7 DV |
2430 | |
2431 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
2432 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
2433 | * the special gen5 functions. */ | |
2434 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
2435 | if (INTEL_INFO(dev)->gen < 4) |
2436 | ring->flush = gen2_render_ring_flush; | |
2437 | else | |
2438 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 2439 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2440 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2441 | if (IS_GEN2(dev)) { |
2442 | ring->irq_get = i8xx_ring_get_irq; | |
2443 | ring->irq_put = i8xx_ring_put_irq; | |
2444 | } else { | |
2445 | ring->irq_get = i9xx_ring_get_irq; | |
2446 | ring->irq_put = i9xx_ring_put_irq; | |
2447 | } | |
28f0cbf7 | 2448 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 2449 | ring->write_tail = ring_write_tail; |
fb3256da DV |
2450 | if (INTEL_INFO(dev)->gen >= 4) |
2451 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2452 | else if (IS_I830(dev) || IS_845G(dev)) | |
2453 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2454 | else | |
2455 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
2456 | ring->init = init_render_ring; |
2457 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
2458 | |
2459 | ring->dev = dev; | |
2460 | INIT_LIST_HEAD(&ring->active_list); | |
2461 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c | 2462 | |
93b0a4e0 OM |
2463 | ringbuf->size = size; |
2464 | ringbuf->effective_size = ringbuf->size; | |
17f10fdc | 2465 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
93b0a4e0 | 2466 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
e8616b6c | 2467 | |
93b0a4e0 OM |
2468 | ringbuf->virtual_start = ioremap_wc(start, size); |
2469 | if (ringbuf->virtual_start == NULL) { | |
e8616b6c CW |
2470 | DRM_ERROR("can not ioremap virtual address for" |
2471 | " ring buffer\n"); | |
8ee14975 OM |
2472 | ret = -ENOMEM; |
2473 | goto err_ringbuf; | |
e8616b6c CW |
2474 | } |
2475 | ||
6b8294a4 | 2476 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 2477 | ret = init_phys_status_page(ring); |
6b8294a4 | 2478 | if (ret) |
8ee14975 | 2479 | goto err_vstart; |
6b8294a4 CW |
2480 | } |
2481 | ||
e8616b6c | 2482 | return 0; |
8ee14975 OM |
2483 | |
2484 | err_vstart: | |
93b0a4e0 | 2485 | iounmap(ringbuf->virtual_start); |
8ee14975 OM |
2486 | err_ringbuf: |
2487 | kfree(ringbuf); | |
2488 | ring->buffer = NULL; | |
2489 | return ret; | |
e8616b6c CW |
2490 | } |
2491 | ||
5c1143bb XH |
2492 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
2493 | { | |
4640c4ff | 2494 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2495 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2496 | |
58fa3835 DV |
2497 | ring->name = "bsd ring"; |
2498 | ring->id = VCS; | |
2499 | ||
0fd2c201 | 2500 | ring->write_tail = ring_write_tail; |
780f18c8 | 2501 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2502 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2503 | /* gen6 bsd needs a special wa for tail updates */ |
2504 | if (IS_GEN6(dev)) | |
2505 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2506 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2507 | ring->add_request = gen6_add_request; |
2508 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2509 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2510 | if (INTEL_INFO(dev)->gen >= 8) { |
2511 | ring->irq_enable_mask = | |
2512 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2513 | ring->irq_get = gen8_ring_get_irq; | |
2514 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2515 | ring->dispatch_execbuffer = |
2516 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2517 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2518 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2519 | ring->semaphore.signal = gen8_xcs_signal; |
2520 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2521 | } |
abd58f01 BW |
2522 | } else { |
2523 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2524 | ring->irq_get = gen6_ring_get_irq; | |
2525 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2526 | ring->dispatch_execbuffer = |
2527 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2528 | if (i915_semaphore_is_enabled(dev)) { |
2529 | ring->semaphore.sync_to = gen6_ring_sync; | |
2530 | ring->semaphore.signal = gen6_signal; | |
2531 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2532 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2533 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2534 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2535 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2536 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2537 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2538 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2539 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2540 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2541 | } | |
abd58f01 | 2542 | } |
58fa3835 DV |
2543 | } else { |
2544 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2545 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2546 | ring->add_request = i9xx_add_request; |
58fa3835 | 2547 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2548 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2549 | if (IS_GEN5(dev)) { |
cc609d5d | 2550 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2551 | ring->irq_get = gen5_ring_get_irq; |
2552 | ring->irq_put = gen5_ring_put_irq; | |
2553 | } else { | |
e3670319 | 2554 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2555 | ring->irq_get = i9xx_ring_get_irq; |
2556 | ring->irq_put = i9xx_ring_put_irq; | |
2557 | } | |
fb3256da | 2558 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
2559 | } |
2560 | ring->init = init_ring_common; | |
2561 | ||
1ec14ad3 | 2562 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2563 | } |
549f7365 | 2564 | |
845f74a7 ZY |
2565 | /** |
2566 | * Initialize the second BSD ring for Broadwell GT3. | |
2567 | * It is noted that this only exists on Broadwell GT3. | |
2568 | */ | |
2569 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2570 | { | |
2571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2572 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2573 | |
2574 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2575 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2576 | return -EINVAL; | |
2577 | } | |
2578 | ||
f7b64236 | 2579 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2580 | ring->id = VCS2; |
2581 | ||
2582 | ring->write_tail = ring_write_tail; | |
2583 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2584 | ring->flush = gen6_bsd_ring_flush; | |
2585 | ring->add_request = gen6_add_request; | |
2586 | ring->get_seqno = gen6_ring_get_seqno; | |
2587 | ring->set_seqno = ring_set_seqno; | |
2588 | ring->irq_enable_mask = | |
2589 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2590 | ring->irq_get = gen8_ring_get_irq; | |
2591 | ring->irq_put = gen8_ring_put_irq; | |
2592 | ring->dispatch_execbuffer = | |
2593 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2594 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2595 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2596 | ring->semaphore.signal = gen8_xcs_signal; |
2597 | GEN8_RING_SEMAPHORE_INIT; | |
2598 | } | |
845f74a7 ZY |
2599 | ring->init = init_ring_common; |
2600 | ||
2601 | return intel_init_ring_buffer(dev, ring); | |
2602 | } | |
2603 | ||
549f7365 CW |
2604 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2605 | { | |
4640c4ff | 2606 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2607 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2608 | |
3535d9dd DV |
2609 | ring->name = "blitter ring"; |
2610 | ring->id = BCS; | |
2611 | ||
2612 | ring->mmio_base = BLT_RING_BASE; | |
2613 | ring->write_tail = ring_write_tail; | |
ea251324 | 2614 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2615 | ring->add_request = gen6_add_request; |
2616 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2617 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2618 | if (INTEL_INFO(dev)->gen >= 8) { |
2619 | ring->irq_enable_mask = | |
2620 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2621 | ring->irq_get = gen8_ring_get_irq; | |
2622 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2623 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2624 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2625 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2626 | ring->semaphore.signal = gen8_xcs_signal; |
2627 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2628 | } |
abd58f01 BW |
2629 | } else { |
2630 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2631 | ring->irq_get = gen6_ring_get_irq; | |
2632 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2633 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2634 | if (i915_semaphore_is_enabled(dev)) { |
2635 | ring->semaphore.signal = gen6_signal; | |
2636 | ring->semaphore.sync_to = gen6_ring_sync; | |
2637 | /* | |
2638 | * The current semaphore is only applied on pre-gen8 | |
2639 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2640 | * platform. So the semaphore between BCS and VCS2 is | |
2641 | * initialized as INVALID. Gen8 will initialize the | |
2642 | * sema between BCS and VCS2 later. | |
2643 | */ | |
2644 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2645 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2646 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2647 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2648 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2649 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2650 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2651 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2652 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2653 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2654 | } | |
abd58f01 | 2655 | } |
3535d9dd | 2656 | ring->init = init_ring_common; |
549f7365 | 2657 | |
1ec14ad3 | 2658 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2659 | } |
a7b9761d | 2660 | |
9a8a2213 BW |
2661 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2662 | { | |
4640c4ff | 2663 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2664 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2665 | |
2666 | ring->name = "video enhancement ring"; | |
2667 | ring->id = VECS; | |
2668 | ||
2669 | ring->mmio_base = VEBOX_RING_BASE; | |
2670 | ring->write_tail = ring_write_tail; | |
2671 | ring->flush = gen6_ring_flush; | |
2672 | ring->add_request = gen6_add_request; | |
2673 | ring->get_seqno = gen6_ring_get_seqno; | |
2674 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2675 | |
2676 | if (INTEL_INFO(dev)->gen >= 8) { | |
2677 | ring->irq_enable_mask = | |
40c499f9 | 2678 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2679 | ring->irq_get = gen8_ring_get_irq; |
2680 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2681 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2682 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2683 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2684 | ring->semaphore.signal = gen8_xcs_signal; |
2685 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2686 | } |
abd58f01 BW |
2687 | } else { |
2688 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2689 | ring->irq_get = hsw_vebox_get_irq; | |
2690 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2691 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2692 | if (i915_semaphore_is_enabled(dev)) { |
2693 | ring->semaphore.sync_to = gen6_ring_sync; | |
2694 | ring->semaphore.signal = gen6_signal; | |
2695 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2696 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2697 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2698 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2699 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2700 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2701 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2702 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2703 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2704 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2705 | } | |
abd58f01 | 2706 | } |
9a8a2213 BW |
2707 | ring->init = init_ring_common; |
2708 | ||
2709 | return intel_init_ring_buffer(dev, ring); | |
2710 | } | |
2711 | ||
a7b9761d | 2712 | int |
a4872ba6 | 2713 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2714 | { |
2715 | int ret; | |
2716 | ||
2717 | if (!ring->gpu_caches_dirty) | |
2718 | return 0; | |
2719 | ||
2720 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2721 | if (ret) | |
2722 | return ret; | |
2723 | ||
2724 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2725 | ||
2726 | ring->gpu_caches_dirty = false; | |
2727 | return 0; | |
2728 | } | |
2729 | ||
2730 | int | |
a4872ba6 | 2731 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2732 | { |
2733 | uint32_t flush_domains; | |
2734 | int ret; | |
2735 | ||
2736 | flush_domains = 0; | |
2737 | if (ring->gpu_caches_dirty) | |
2738 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2739 | ||
2740 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2741 | if (ret) | |
2742 | return ret; | |
2743 | ||
2744 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2745 | ||
2746 | ring->gpu_caches_dirty = false; | |
2747 | return 0; | |
2748 | } | |
e3efda49 CW |
2749 | |
2750 | void | |
a4872ba6 | 2751 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2752 | { |
2753 | int ret; | |
2754 | ||
2755 | if (!intel_ring_initialized(ring)) | |
2756 | return; | |
2757 | ||
2758 | ret = intel_ring_idle(ring); | |
2759 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2760 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2761 | ring->name, ret); | |
2762 | ||
2763 | stop_ring(ring); | |
2764 | } |