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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
c7dca47b CW |
36 | static inline int ring_space(struct intel_ring_buffer *ring) |
37 | { | |
633cf8f5 | 38 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
39 | if (space < 0) |
40 | space += ring->size; | |
41 | return space; | |
42 | } | |
43 | ||
b72f3acb | 44 | static int |
46f0f8d1 CW |
45 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
46 | u32 invalidate_domains, | |
47 | u32 flush_domains) | |
48 | { | |
49 | u32 cmd; | |
50 | int ret; | |
51 | ||
52 | cmd = MI_FLUSH; | |
31b14c9f | 53 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
54 | cmd |= MI_NO_WRITE_FLUSH; |
55 | ||
56 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
57 | cmd |= MI_READ_FLUSH; | |
58 | ||
59 | ret = intel_ring_begin(ring, 2); | |
60 | if (ret) | |
61 | return ret; | |
62 | ||
63 | intel_ring_emit(ring, cmd); | |
64 | intel_ring_emit(ring, MI_NOOP); | |
65 | intel_ring_advance(ring); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | static int | |
71 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
72 | u32 invalidate_domains, | |
73 | u32 flush_domains) | |
62fdfeaf | 74 | { |
78501eac | 75 | struct drm_device *dev = ring->dev; |
6f392d54 | 76 | u32 cmd; |
b72f3acb | 77 | int ret; |
6f392d54 | 78 | |
36d527de CW |
79 | /* |
80 | * read/write caches: | |
81 | * | |
82 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
83 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
84 | * also flushed at 2d versus 3d pipeline switches. | |
85 | * | |
86 | * read-only caches: | |
87 | * | |
88 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
89 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
90 | * | |
91 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
92 | * | |
93 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
94 | * invalidated when MI_EXE_FLUSH is set. | |
95 | * | |
96 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
97 | * invalidated with every MI_FLUSH. | |
98 | * | |
99 | * TLBs: | |
100 | * | |
101 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
102 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
103 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
104 | * are flushed at any MI_FLUSH. | |
105 | */ | |
106 | ||
107 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 108 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 109 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
110 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
111 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 112 | |
36d527de CW |
113 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
114 | (IS_G4X(dev) || IS_GEN5(dev))) | |
115 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 116 | |
36d527de CW |
117 | ret = intel_ring_begin(ring, 2); |
118 | if (ret) | |
119 | return ret; | |
b72f3acb | 120 | |
36d527de CW |
121 | intel_ring_emit(ring, cmd); |
122 | intel_ring_emit(ring, MI_NOOP); | |
123 | intel_ring_advance(ring); | |
b72f3acb CW |
124 | |
125 | return 0; | |
8187a2b7 ZN |
126 | } |
127 | ||
8d315287 JB |
128 | /** |
129 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
130 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
131 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
132 | * | |
133 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
134 | * produced by non-pipelined state commands), software needs to first | |
135 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
136 | * 0. | |
137 | * | |
138 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
139 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
140 | * | |
141 | * And the workaround for these two requires this workaround first: | |
142 | * | |
143 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
144 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
145 | * flushes. | |
146 | * | |
147 | * And this last workaround is tricky because of the requirements on | |
148 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
149 | * volume 2 part 1: | |
150 | * | |
151 | * "1 of the following must also be set: | |
152 | * - Render Target Cache Flush Enable ([12] of DW1) | |
153 | * - Depth Cache Flush Enable ([0] of DW1) | |
154 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
155 | * - Depth Stall ([13] of DW1) | |
156 | * - Post-Sync Operation ([13] of DW1) | |
157 | * - Notify Enable ([8] of DW1)" | |
158 | * | |
159 | * The cache flushes require the workaround flush that triggered this | |
160 | * one, so we can't use it. Depth stall would trigger the same. | |
161 | * Post-sync nonzero is what triggered this second workaround, so we | |
162 | * can't use that one either. Notify enable is IRQs, which aren't | |
163 | * really our business. That leaves only stall at scoreboard. | |
164 | */ | |
165 | static int | |
166 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
167 | { | |
0d1aacac | 168 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
169 | int ret; |
170 | ||
171 | ||
172 | ret = intel_ring_begin(ring, 6); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
176 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
177 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
178 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
179 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
180 | intel_ring_emit(ring, 0); /* low dword */ | |
181 | intel_ring_emit(ring, 0); /* high dword */ | |
182 | intel_ring_emit(ring, MI_NOOP); | |
183 | intel_ring_advance(ring); | |
184 | ||
185 | ret = intel_ring_begin(ring, 6); | |
186 | if (ret) | |
187 | return ret; | |
188 | ||
189 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
190 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
192 | intel_ring_emit(ring, 0); | |
193 | intel_ring_emit(ring, 0); | |
194 | intel_ring_emit(ring, MI_NOOP); | |
195 | intel_ring_advance(ring); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
200 | static int | |
201 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
202 | u32 invalidate_domains, u32 flush_domains) | |
203 | { | |
204 | u32 flags = 0; | |
0d1aacac | 205 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
8d315287 JB |
206 | int ret; |
207 | ||
b3111509 PZ |
208 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
209 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
210 | if (ret) | |
211 | return ret; | |
212 | ||
8d315287 JB |
213 | /* Just flush everything. Experiments have shown that reducing the |
214 | * number of bits based on the write domains has little performance | |
215 | * impact. | |
216 | */ | |
7d54a904 CW |
217 | if (flush_domains) { |
218 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
219 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
220 | /* | |
221 | * Ensure that any following seqno writes only happen | |
222 | * when the render cache is indeed flushed. | |
223 | */ | |
97f209bc | 224 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
225 | } |
226 | if (invalidate_domains) { | |
227 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
228 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
229 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
230 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
231 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
232 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
233 | /* | |
234 | * TLB invalidate requires a post-sync write. | |
235 | */ | |
3ac78313 | 236 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 237 | } |
8d315287 | 238 | |
6c6cf5aa | 239 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
240 | if (ret) |
241 | return ret; | |
242 | ||
6c6cf5aa | 243 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
244 | intel_ring_emit(ring, flags); |
245 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 246 | intel_ring_emit(ring, 0); |
8d315287 JB |
247 | intel_ring_advance(ring); |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
f3987631 PZ |
252 | static int |
253 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
254 | { | |
255 | int ret; | |
256 | ||
257 | ret = intel_ring_begin(ring, 4); | |
258 | if (ret) | |
259 | return ret; | |
260 | ||
261 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
262 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
263 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
264 | intel_ring_emit(ring, 0); | |
265 | intel_ring_emit(ring, 0); | |
266 | intel_ring_advance(ring); | |
267 | ||
268 | return 0; | |
269 | } | |
270 | ||
fd3da6c9 RV |
271 | static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) |
272 | { | |
273 | int ret; | |
274 | ||
275 | if (!ring->fbc_dirty) | |
276 | return 0; | |
277 | ||
278 | ret = intel_ring_begin(ring, 4); | |
279 | if (ret) | |
280 | return ret; | |
281 | intel_ring_emit(ring, MI_NOOP); | |
282 | /* WaFbcNukeOn3DBlt:ivb/hsw */ | |
283 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
284 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
285 | intel_ring_emit(ring, value); | |
286 | intel_ring_advance(ring); | |
287 | ||
288 | ring->fbc_dirty = false; | |
289 | return 0; | |
290 | } | |
291 | ||
4772eaeb PZ |
292 | static int |
293 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
294 | u32 invalidate_domains, u32 flush_domains) | |
295 | { | |
296 | u32 flags = 0; | |
0d1aacac | 297 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
4772eaeb PZ |
298 | int ret; |
299 | ||
f3987631 PZ |
300 | /* |
301 | * Ensure that any following seqno writes only happen when the render | |
302 | * cache is indeed flushed. | |
303 | * | |
304 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
305 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
306 | * don't try to be clever and just set it unconditionally. | |
307 | */ | |
308 | flags |= PIPE_CONTROL_CS_STALL; | |
309 | ||
4772eaeb PZ |
310 | /* Just flush everything. Experiments have shown that reducing the |
311 | * number of bits based on the write domains has little performance | |
312 | * impact. | |
313 | */ | |
314 | if (flush_domains) { | |
315 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
316 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
317 | } |
318 | if (invalidate_domains) { | |
319 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
320 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
321 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
322 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
323 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
324 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
325 | /* | |
326 | * TLB invalidate requires a post-sync write. | |
327 | */ | |
328 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 329 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
330 | |
331 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
332 | * set before a pipe_control command that has the state cache | |
333 | * invalidate bit set. */ | |
334 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
335 | } |
336 | ||
337 | ret = intel_ring_begin(ring, 4); | |
338 | if (ret) | |
339 | return ret; | |
340 | ||
341 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
342 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 343 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
344 | intel_ring_emit(ring, 0); |
345 | intel_ring_advance(ring); | |
346 | ||
fd3da6c9 RV |
347 | if (flush_domains) |
348 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
349 | ||
4772eaeb PZ |
350 | return 0; |
351 | } | |
352 | ||
78501eac | 353 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 354 | u32 value) |
d46eefa2 | 355 | { |
78501eac | 356 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 357 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
358 | } |
359 | ||
78501eac | 360 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 361 | { |
78501eac CW |
362 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
363 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 364 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
365 | |
366 | return I915_READ(acthd_reg); | |
367 | } | |
368 | ||
035dc1e0 DV |
369 | static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) |
370 | { | |
371 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
372 | u32 addr; | |
373 | ||
374 | addr = dev_priv->status_page_dmah->busaddr; | |
375 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
376 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
377 | I915_WRITE(HWS_PGA, addr); | |
378 | } | |
379 | ||
78501eac | 380 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 381 | { |
b7884eb4 DV |
382 | struct drm_device *dev = ring->dev; |
383 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 384 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 385 | int ret = 0; |
8187a2b7 | 386 | u32 head; |
8187a2b7 | 387 | |
b7884eb4 DV |
388 | if (HAS_FORCE_WAKE(dev)) |
389 | gen6_gt_force_wake_get(dev_priv); | |
390 | ||
035dc1e0 DV |
391 | if (I915_NEED_GFX_HWS(dev)) |
392 | intel_ring_setup_status_page(ring); | |
393 | else | |
394 | ring_setup_phys_status_page(ring); | |
395 | ||
8187a2b7 | 396 | /* Stop the ring if it's running. */ |
7f2ab699 | 397 | I915_WRITE_CTL(ring, 0); |
570ef608 | 398 | I915_WRITE_HEAD(ring, 0); |
78501eac | 399 | ring->write_tail(ring, 0); |
8187a2b7 | 400 | |
570ef608 | 401 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
402 | |
403 | /* G45 ring initialization fails to reset head to zero */ | |
404 | if (head != 0) { | |
6fd0d56e CW |
405 | DRM_DEBUG_KMS("%s head not reset to zero " |
406 | "ctl %08x head %08x tail %08x start %08x\n", | |
407 | ring->name, | |
408 | I915_READ_CTL(ring), | |
409 | I915_READ_HEAD(ring), | |
410 | I915_READ_TAIL(ring), | |
411 | I915_READ_START(ring)); | |
8187a2b7 | 412 | |
570ef608 | 413 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 414 | |
6fd0d56e CW |
415 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
416 | DRM_ERROR("failed to set %s head to zero " | |
417 | "ctl %08x head %08x tail %08x start %08x\n", | |
418 | ring->name, | |
419 | I915_READ_CTL(ring), | |
420 | I915_READ_HEAD(ring), | |
421 | I915_READ_TAIL(ring), | |
422 | I915_READ_START(ring)); | |
423 | } | |
8187a2b7 ZN |
424 | } |
425 | ||
0d8957c8 DV |
426 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
427 | * registers with the above sequence (the readback of the HEAD registers | |
428 | * also enforces ordering), otherwise the hw might lose the new ring | |
429 | * register values. */ | |
f343c5f6 | 430 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
7f2ab699 | 431 | I915_WRITE_CTL(ring, |
ae69b42a | 432 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 433 | | RING_VALID); |
8187a2b7 | 434 | |
8187a2b7 | 435 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 436 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 437 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 438 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 CW |
439 | DRM_ERROR("%s initialization failed " |
440 | "ctl %08x head %08x tail %08x start %08x\n", | |
441 | ring->name, | |
442 | I915_READ_CTL(ring), | |
443 | I915_READ_HEAD(ring), | |
444 | I915_READ_TAIL(ring), | |
445 | I915_READ_START(ring)); | |
b7884eb4 DV |
446 | ret = -EIO; |
447 | goto out; | |
8187a2b7 ZN |
448 | } |
449 | ||
78501eac CW |
450 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
451 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 452 | else { |
c7dca47b | 453 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 454 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 455 | ring->space = ring_space(ring); |
c3b20037 | 456 | ring->last_retired_head = -1; |
8187a2b7 | 457 | } |
1ec14ad3 | 458 | |
50f018df CW |
459 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
460 | ||
b7884eb4 DV |
461 | out: |
462 | if (HAS_FORCE_WAKE(dev)) | |
463 | gen6_gt_force_wake_put(dev_priv); | |
464 | ||
465 | return ret; | |
8187a2b7 ZN |
466 | } |
467 | ||
c6df541c CW |
468 | static int |
469 | init_pipe_control(struct intel_ring_buffer *ring) | |
470 | { | |
c6df541c CW |
471 | int ret; |
472 | ||
0d1aacac | 473 | if (ring->scratch.obj) |
c6df541c CW |
474 | return 0; |
475 | ||
0d1aacac CW |
476 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
477 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
478 | DRM_ERROR("Failed to allocate seqno page\n"); |
479 | ret = -ENOMEM; | |
480 | goto err; | |
481 | } | |
e4ffd173 | 482 | |
0d1aacac | 483 | i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
c6df541c | 484 | |
0d1aacac | 485 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); |
c6df541c CW |
486 | if (ret) |
487 | goto err_unref; | |
488 | ||
0d1aacac CW |
489 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
490 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
491 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 492 | ret = -ENOMEM; |
c6df541c | 493 | goto err_unpin; |
56b085a0 | 494 | } |
c6df541c | 495 | |
2b1086cc | 496 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 497 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
498 | return 0; |
499 | ||
500 | err_unpin: | |
0d1aacac | 501 | i915_gem_object_unpin(ring->scratch.obj); |
c6df541c | 502 | err_unref: |
0d1aacac | 503 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 504 | err: |
c6df541c CW |
505 | return ret; |
506 | } | |
507 | ||
78501eac | 508 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 509 | { |
78501eac | 510 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 511 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 512 | int ret = init_ring_common(ring); |
a69ffdbf | 513 | |
1c8c38c5 | 514 | if (INTEL_INFO(dev)->gen > 3) |
6b26c86d | 515 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
516 | |
517 | /* We need to disable the AsyncFlip performance optimisations in order | |
518 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
519 | * programmed to '1' on all products. | |
8693a824 DL |
520 | * |
521 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv | |
1c8c38c5 CW |
522 | */ |
523 | if (INTEL_INFO(dev)->gen >= 6) | |
524 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
525 | ||
f05bb0c7 CW |
526 | /* Required for the hardware to program scanline values for waiting */ |
527 | if (INTEL_INFO(dev)->gen == 6) | |
528 | I915_WRITE(GFX_MODE, | |
529 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); | |
530 | ||
1c8c38c5 CW |
531 | if (IS_GEN7(dev)) |
532 | I915_WRITE(GFX_MODE_GEN7, | |
533 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
534 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
78501eac | 535 | |
8d315287 | 536 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
537 | ret = init_pipe_control(ring); |
538 | if (ret) | |
539 | return ret; | |
540 | } | |
541 | ||
5e13a0c5 | 542 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
543 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
544 | * "If this bit is set, STCunit will have LRA as replacement | |
545 | * policy. [...] This bit must be reset. LRA replacement | |
546 | * policy is not supported." | |
547 | */ | |
548 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 549 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
550 | |
551 | /* This is not explicitly set for GEN6, so read the register. | |
552 | * see intel_ring_mi_set_context() for why we care. | |
553 | * TODO: consider explicitly setting the bit for GEN5 | |
554 | */ | |
555 | ring->itlb_before_ctx_switch = | |
556 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
557 | } |
558 | ||
6b26c86d DV |
559 | if (INTEL_INFO(dev)->gen >= 6) |
560 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 561 | |
e1ef7cc2 | 562 | if (HAS_L3_GPU_CACHE(dev)) |
cc609d5d | 563 | I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
15b9f80e | 564 | |
8187a2b7 ZN |
565 | return ret; |
566 | } | |
567 | ||
c6df541c CW |
568 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
569 | { | |
b45305fc DV |
570 | struct drm_device *dev = ring->dev; |
571 | ||
0d1aacac | 572 | if (ring->scratch.obj == NULL) |
c6df541c CW |
573 | return; |
574 | ||
0d1aacac CW |
575 | if (INTEL_INFO(dev)->gen >= 5) { |
576 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
577 | i915_gem_object_unpin(ring->scratch.obj); | |
578 | } | |
aaf8a516 | 579 | |
0d1aacac CW |
580 | drm_gem_object_unreference(&ring->scratch.obj->base); |
581 | ring->scratch.obj = NULL; | |
c6df541c CW |
582 | } |
583 | ||
1ec14ad3 | 584 | static void |
c8c99b0f | 585 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 586 | u32 mmio_offset) |
1ec14ad3 | 587 | { |
ad776f8b BW |
588 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
589 | * of rings, it's easiest if we round up each individual update to a | |
590 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
591 | * even though the actual update only requires 3 dwords. | |
592 | */ | |
593 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 594 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 595 | intel_ring_emit(ring, mmio_offset); |
1823521d | 596 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
ad776f8b | 597 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
598 | } |
599 | ||
c8c99b0f BW |
600 | /** |
601 | * gen6_add_request - Update the semaphore mailbox registers | |
602 | * | |
603 | * @ring - ring that is adding a request | |
604 | * @seqno - return seqno stuck into the ring | |
605 | * | |
606 | * Update the mailbox registers in the *other* rings with the current seqno. | |
607 | * This acts like a signal in the canonical semaphore. | |
608 | */ | |
1ec14ad3 | 609 | static int |
9d773091 | 610 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 611 | { |
ad776f8b BW |
612 | struct drm_device *dev = ring->dev; |
613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
614 | struct intel_ring_buffer *useless; | |
615 | int i, ret; | |
1ec14ad3 | 616 | |
ad776f8b BW |
617 | ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) * |
618 | MBOX_UPDATE_DWORDS) + | |
619 | 4); | |
1ec14ad3 CW |
620 | if (ret) |
621 | return ret; | |
ad776f8b | 622 | #undef MBOX_UPDATE_DWORDS |
1ec14ad3 | 623 | |
ad776f8b BW |
624 | for_each_ring(useless, dev_priv, i) { |
625 | u32 mbox_reg = ring->signal_mbox[i]; | |
626 | if (mbox_reg != GEN6_NOSYNC) | |
627 | update_mboxes(ring, mbox_reg); | |
628 | } | |
1ec14ad3 CW |
629 | |
630 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
631 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 632 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
1ec14ad3 CW |
633 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
634 | intel_ring_advance(ring); | |
635 | ||
1ec14ad3 CW |
636 | return 0; |
637 | } | |
638 | ||
f72b3435 MK |
639 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
640 | u32 seqno) | |
641 | { | |
642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
643 | return dev_priv->last_seqno < seqno; | |
644 | } | |
645 | ||
c8c99b0f BW |
646 | /** |
647 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
648 | * | |
649 | * @waiter - ring that is waiting | |
650 | * @signaller - ring which has, or will signal | |
651 | * @seqno - seqno which the waiter will block on | |
652 | */ | |
653 | static int | |
686cb5f9 DV |
654 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
655 | struct intel_ring_buffer *signaller, | |
656 | u32 seqno) | |
1ec14ad3 CW |
657 | { |
658 | int ret; | |
c8c99b0f BW |
659 | u32 dw1 = MI_SEMAPHORE_MBOX | |
660 | MI_SEMAPHORE_COMPARE | | |
661 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 662 | |
1500f7ea BW |
663 | /* Throughout all of the GEM code, seqno passed implies our current |
664 | * seqno is >= the last seqno executed. However for hardware the | |
665 | * comparison is strictly greater than. | |
666 | */ | |
667 | seqno -= 1; | |
668 | ||
686cb5f9 DV |
669 | WARN_ON(signaller->semaphore_register[waiter->id] == |
670 | MI_SEMAPHORE_SYNC_INVALID); | |
671 | ||
c8c99b0f | 672 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
673 | if (ret) |
674 | return ret; | |
675 | ||
f72b3435 MK |
676 | /* If seqno wrap happened, omit the wait with no-ops */ |
677 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
678 | intel_ring_emit(waiter, | |
679 | dw1 | | |
680 | signaller->semaphore_register[waiter->id]); | |
681 | intel_ring_emit(waiter, seqno); | |
682 | intel_ring_emit(waiter, 0); | |
683 | intel_ring_emit(waiter, MI_NOOP); | |
684 | } else { | |
685 | intel_ring_emit(waiter, MI_NOOP); | |
686 | intel_ring_emit(waiter, MI_NOOP); | |
687 | intel_ring_emit(waiter, MI_NOOP); | |
688 | intel_ring_emit(waiter, MI_NOOP); | |
689 | } | |
c8c99b0f | 690 | intel_ring_advance(waiter); |
1ec14ad3 CW |
691 | |
692 | return 0; | |
693 | } | |
694 | ||
c6df541c CW |
695 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
696 | do { \ | |
fcbc34e4 KG |
697 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
698 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
699 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
700 | intel_ring_emit(ring__, 0); \ | |
701 | intel_ring_emit(ring__, 0); \ | |
702 | } while (0) | |
703 | ||
704 | static int | |
9d773091 | 705 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 706 | { |
0d1aacac | 707 | u32 scratch_addr = ring->scratch.gtt_offset + 128; |
c6df541c CW |
708 | int ret; |
709 | ||
710 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
711 | * incoherent with writes to memory, i.e. completely fubar, | |
712 | * so we need to use PIPE_NOTIFY instead. | |
713 | * | |
714 | * However, we also need to workaround the qword write | |
715 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
716 | * memory before requesting an interrupt. | |
717 | */ | |
718 | ret = intel_ring_begin(ring, 32); | |
719 | if (ret) | |
720 | return ret; | |
721 | ||
fcbc34e4 | 722 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
723 | PIPE_CONTROL_WRITE_FLUSH | |
724 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 725 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 726 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
727 | intel_ring_emit(ring, 0); |
728 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
729 | scratch_addr += 128; /* write to separate cachelines */ | |
730 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
731 | scratch_addr += 128; | |
732 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
733 | scratch_addr += 128; | |
734 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
735 | scratch_addr += 128; | |
736 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
737 | scratch_addr += 128; | |
738 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 739 | |
fcbc34e4 | 740 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
741 | PIPE_CONTROL_WRITE_FLUSH | |
742 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 743 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 744 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
1823521d | 745 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
c6df541c CW |
746 | intel_ring_emit(ring, 0); |
747 | intel_ring_advance(ring); | |
748 | ||
c6df541c CW |
749 | return 0; |
750 | } | |
751 | ||
4cd53c0c | 752 | static u32 |
b2eadbc8 | 753 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 754 | { |
4cd53c0c DV |
755 | /* Workaround to force correct ordering between irq and seqno writes on |
756 | * ivb (and maybe also on snb) by reading from a CS register (like | |
757 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 758 | if (!lazy_coherency) |
4cd53c0c DV |
759 | intel_ring_get_active_head(ring); |
760 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
761 | } | |
762 | ||
8187a2b7 | 763 | static u32 |
b2eadbc8 | 764 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 765 | { |
1ec14ad3 CW |
766 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
767 | } | |
768 | ||
b70ec5bf MK |
769 | static void |
770 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
771 | { | |
772 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
773 | } | |
774 | ||
c6df541c | 775 | static u32 |
b2eadbc8 | 776 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c | 777 | { |
0d1aacac | 778 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
779 | } |
780 | ||
b70ec5bf MK |
781 | static void |
782 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
783 | { | |
0d1aacac | 784 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
785 | } |
786 | ||
e48d8634 DV |
787 | static bool |
788 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
789 | { | |
790 | struct drm_device *dev = ring->dev; | |
791 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 792 | unsigned long flags; |
e48d8634 DV |
793 | |
794 | if (!dev->irq_enabled) | |
795 | return false; | |
796 | ||
7338aefa | 797 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
798 | if (ring->irq_refcount++ == 0) |
799 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 800 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
801 | |
802 | return true; | |
803 | } | |
804 | ||
805 | static void | |
806 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
807 | { | |
808 | struct drm_device *dev = ring->dev; | |
809 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 810 | unsigned long flags; |
e48d8634 | 811 | |
7338aefa | 812 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 PZ |
813 | if (--ring->irq_refcount == 0) |
814 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); | |
7338aefa | 815 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
816 | } |
817 | ||
b13c2b96 | 818 | static bool |
e3670319 | 819 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 820 | { |
78501eac | 821 | struct drm_device *dev = ring->dev; |
01a03331 | 822 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 823 | unsigned long flags; |
62fdfeaf | 824 | |
b13c2b96 CW |
825 | if (!dev->irq_enabled) |
826 | return false; | |
827 | ||
7338aefa | 828 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 829 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
830 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
831 | I915_WRITE(IMR, dev_priv->irq_mask); | |
832 | POSTING_READ(IMR); | |
833 | } | |
7338aefa | 834 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
835 | |
836 | return true; | |
62fdfeaf EA |
837 | } |
838 | ||
8187a2b7 | 839 | static void |
e3670319 | 840 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 841 | { |
78501eac | 842 | struct drm_device *dev = ring->dev; |
01a03331 | 843 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 844 | unsigned long flags; |
62fdfeaf | 845 | |
7338aefa | 846 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 847 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
848 | dev_priv->irq_mask |= ring->irq_enable_mask; |
849 | I915_WRITE(IMR, dev_priv->irq_mask); | |
850 | POSTING_READ(IMR); | |
851 | } | |
7338aefa | 852 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
853 | } |
854 | ||
c2798b19 CW |
855 | static bool |
856 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
857 | { | |
858 | struct drm_device *dev = ring->dev; | |
859 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 860 | unsigned long flags; |
c2798b19 CW |
861 | |
862 | if (!dev->irq_enabled) | |
863 | return false; | |
864 | ||
7338aefa | 865 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 866 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
867 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
868 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
869 | POSTING_READ16(IMR); | |
870 | } | |
7338aefa | 871 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
872 | |
873 | return true; | |
874 | } | |
875 | ||
876 | static void | |
877 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
878 | { | |
879 | struct drm_device *dev = ring->dev; | |
880 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 881 | unsigned long flags; |
c2798b19 | 882 | |
7338aefa | 883 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 884 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
885 | dev_priv->irq_mask |= ring->irq_enable_mask; |
886 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
887 | POSTING_READ16(IMR); | |
888 | } | |
7338aefa | 889 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
890 | } |
891 | ||
78501eac | 892 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 893 | { |
4593010b | 894 | struct drm_device *dev = ring->dev; |
78501eac | 895 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
896 | u32 mmio = 0; |
897 | ||
898 | /* The ring status page addresses are no longer next to the rest of | |
899 | * the ring registers as of gen7. | |
900 | */ | |
901 | if (IS_GEN7(dev)) { | |
902 | switch (ring->id) { | |
96154f2f | 903 | case RCS: |
4593010b EA |
904 | mmio = RENDER_HWS_PGA_GEN7; |
905 | break; | |
96154f2f | 906 | case BCS: |
4593010b EA |
907 | mmio = BLT_HWS_PGA_GEN7; |
908 | break; | |
96154f2f | 909 | case VCS: |
4593010b EA |
910 | mmio = BSD_HWS_PGA_GEN7; |
911 | break; | |
4a3dd19d | 912 | case VECS: |
9a8a2213 BW |
913 | mmio = VEBOX_HWS_PGA_GEN7; |
914 | break; | |
4593010b EA |
915 | } |
916 | } else if (IS_GEN6(ring->dev)) { | |
917 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
918 | } else { | |
919 | mmio = RING_HWS_PGA(ring->mmio_base); | |
920 | } | |
921 | ||
78501eac CW |
922 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
923 | POSTING_READ(mmio); | |
884020bf CW |
924 | |
925 | /* Flush the TLB for this page */ | |
926 | if (INTEL_INFO(dev)->gen >= 6) { | |
927 | u32 reg = RING_INSTPM(ring->mmio_base); | |
928 | I915_WRITE(reg, | |
929 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
930 | INSTPM_SYNC_FLUSH)); | |
931 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
932 | 1000)) | |
933 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
934 | ring->name); | |
935 | } | |
8187a2b7 ZN |
936 | } |
937 | ||
b72f3acb | 938 | static int |
78501eac CW |
939 | bsd_ring_flush(struct intel_ring_buffer *ring, |
940 | u32 invalidate_domains, | |
941 | u32 flush_domains) | |
d1b851fc | 942 | { |
b72f3acb CW |
943 | int ret; |
944 | ||
b72f3acb CW |
945 | ret = intel_ring_begin(ring, 2); |
946 | if (ret) | |
947 | return ret; | |
948 | ||
949 | intel_ring_emit(ring, MI_FLUSH); | |
950 | intel_ring_emit(ring, MI_NOOP); | |
951 | intel_ring_advance(ring); | |
952 | return 0; | |
d1b851fc ZN |
953 | } |
954 | ||
3cce469c | 955 | static int |
9d773091 | 956 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 957 | { |
3cce469c CW |
958 | int ret; |
959 | ||
960 | ret = intel_ring_begin(ring, 4); | |
961 | if (ret) | |
962 | return ret; | |
6f392d54 | 963 | |
3cce469c CW |
964 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
965 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1823521d | 966 | intel_ring_emit(ring, ring->outstanding_lazy_seqno); |
3cce469c CW |
967 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
968 | intel_ring_advance(ring); | |
d1b851fc | 969 | |
3cce469c | 970 | return 0; |
d1b851fc ZN |
971 | } |
972 | ||
0f46832f | 973 | static bool |
25c06300 | 974 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
975 | { |
976 | struct drm_device *dev = ring->dev; | |
01a03331 | 977 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 978 | unsigned long flags; |
0f46832f CW |
979 | |
980 | if (!dev->irq_enabled) | |
981 | return false; | |
982 | ||
4cd53c0c DV |
983 | /* It looks like we need to prevent the gt from suspending while waiting |
984 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
985 | * blt/bsd rings on ivb. */ | |
99ffa162 | 986 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 987 | |
7338aefa | 988 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 989 | if (ring->irq_refcount++ == 0) { |
e1ef7cc2 | 990 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
cc609d5d BW |
991 | I915_WRITE_IMR(ring, |
992 | ~(ring->irq_enable_mask | | |
993 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
15b9f80e BW |
994 | else |
995 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
43eaea13 | 996 | ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 997 | } |
7338aefa | 998 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
999 | |
1000 | return true; | |
1001 | } | |
1002 | ||
1003 | static void | |
25c06300 | 1004 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1005 | { |
1006 | struct drm_device *dev = ring->dev; | |
01a03331 | 1007 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1008 | unsigned long flags; |
0f46832f | 1009 | |
7338aefa | 1010 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1011 | if (--ring->irq_refcount == 0) { |
e1ef7cc2 | 1012 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
cc609d5d BW |
1013 | I915_WRITE_IMR(ring, |
1014 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
15b9f80e BW |
1015 | else |
1016 | I915_WRITE_IMR(ring, ~0); | |
43eaea13 | 1017 | ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1018 | } |
7338aefa | 1019 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 1020 | |
99ffa162 | 1021 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
1022 | } |
1023 | ||
a19d2933 BW |
1024 | static bool |
1025 | hsw_vebox_get_irq(struct intel_ring_buffer *ring) | |
1026 | { | |
1027 | struct drm_device *dev = ring->dev; | |
1028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1029 | unsigned long flags; | |
1030 | ||
1031 | if (!dev->irq_enabled) | |
1032 | return false; | |
1033 | ||
59cdb63d | 1034 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1035 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1036 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
edbfdb45 | 1037 | snb_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1038 | } |
59cdb63d | 1039 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1040 | |
1041 | return true; | |
1042 | } | |
1043 | ||
1044 | static void | |
1045 | hsw_vebox_put_irq(struct intel_ring_buffer *ring) | |
1046 | { | |
1047 | struct drm_device *dev = ring->dev; | |
1048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1049 | unsigned long flags; | |
1050 | ||
1051 | if (!dev->irq_enabled) | |
1052 | return; | |
1053 | ||
59cdb63d | 1054 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1055 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1056 | I915_WRITE_IMR(ring, ~0); |
edbfdb45 | 1057 | snb_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1058 | } |
59cdb63d | 1059 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1060 | } |
1061 | ||
d1b851fc | 1062 | static int |
d7d4eedd CW |
1063 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1064 | u32 offset, u32 length, | |
1065 | unsigned flags) | |
d1b851fc | 1066 | { |
e1f99ce6 | 1067 | int ret; |
78501eac | 1068 | |
e1f99ce6 CW |
1069 | ret = intel_ring_begin(ring, 2); |
1070 | if (ret) | |
1071 | return ret; | |
1072 | ||
78501eac | 1073 | intel_ring_emit(ring, |
65f56876 CW |
1074 | MI_BATCH_BUFFER_START | |
1075 | MI_BATCH_GTT | | |
d7d4eedd | 1076 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1077 | intel_ring_emit(ring, offset); |
78501eac CW |
1078 | intel_ring_advance(ring); |
1079 | ||
d1b851fc ZN |
1080 | return 0; |
1081 | } | |
1082 | ||
b45305fc DV |
1083 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1084 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1085 | static int |
fb3256da | 1086 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1087 | u32 offset, u32 len, |
1088 | unsigned flags) | |
62fdfeaf | 1089 | { |
c4e7a414 | 1090 | int ret; |
62fdfeaf | 1091 | |
b45305fc DV |
1092 | if (flags & I915_DISPATCH_PINNED) { |
1093 | ret = intel_ring_begin(ring, 4); | |
1094 | if (ret) | |
1095 | return ret; | |
62fdfeaf | 1096 | |
b45305fc DV |
1097 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1098 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1099 | intel_ring_emit(ring, offset + len - 8); | |
1100 | intel_ring_emit(ring, MI_NOOP); | |
1101 | intel_ring_advance(ring); | |
1102 | } else { | |
0d1aacac | 1103 | u32 cs_offset = ring->scratch.gtt_offset; |
b45305fc DV |
1104 | |
1105 | if (len > I830_BATCH_LIMIT) | |
1106 | return -ENOSPC; | |
1107 | ||
1108 | ret = intel_ring_begin(ring, 9+3); | |
1109 | if (ret) | |
1110 | return ret; | |
1111 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1112 | * scratch bo area (so that the CS never stumbles over its tlb | |
1113 | * invalidation bug) ... */ | |
1114 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1115 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1116 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1117 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1118 | intel_ring_emit(ring, 0); | |
1119 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1120 | intel_ring_emit(ring, cs_offset); | |
1121 | intel_ring_emit(ring, 0); | |
1122 | intel_ring_emit(ring, 4096); | |
1123 | intel_ring_emit(ring, offset); | |
1124 | intel_ring_emit(ring, MI_FLUSH); | |
1125 | ||
1126 | /* ... and execute it. */ | |
1127 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1128 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1129 | intel_ring_emit(ring, cs_offset + len - 8); | |
1130 | intel_ring_advance(ring); | |
1131 | } | |
e1f99ce6 | 1132 | |
fb3256da DV |
1133 | return 0; |
1134 | } | |
1135 | ||
1136 | static int | |
1137 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1138 | u32 offset, u32 len, |
1139 | unsigned flags) | |
fb3256da DV |
1140 | { |
1141 | int ret; | |
1142 | ||
1143 | ret = intel_ring_begin(ring, 2); | |
1144 | if (ret) | |
1145 | return ret; | |
1146 | ||
65f56876 | 1147 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1148 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1149 | intel_ring_advance(ring); |
62fdfeaf | 1150 | |
62fdfeaf EA |
1151 | return 0; |
1152 | } | |
1153 | ||
78501eac | 1154 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1155 | { |
05394f39 | 1156 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1157 | |
8187a2b7 ZN |
1158 | obj = ring->status_page.obj; |
1159 | if (obj == NULL) | |
62fdfeaf | 1160 | return; |
62fdfeaf | 1161 | |
9da3da66 | 1162 | kunmap(sg_page(obj->pages->sgl)); |
62fdfeaf | 1163 | i915_gem_object_unpin(obj); |
05394f39 | 1164 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1165 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1166 | } |
1167 | ||
78501eac | 1168 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1169 | { |
78501eac | 1170 | struct drm_device *dev = ring->dev; |
05394f39 | 1171 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1172 | int ret; |
1173 | ||
62fdfeaf EA |
1174 | obj = i915_gem_alloc_object(dev, 4096); |
1175 | if (obj == NULL) { | |
1176 | DRM_ERROR("Failed to allocate status page\n"); | |
1177 | ret = -ENOMEM; | |
1178 | goto err; | |
1179 | } | |
e4ffd173 CW |
1180 | |
1181 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1182 | |
c37e2204 | 1183 | ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); |
62fdfeaf | 1184 | if (ret != 0) { |
62fdfeaf EA |
1185 | goto err_unref; |
1186 | } | |
1187 | ||
f343c5f6 | 1188 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1189 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1190 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1191 | ret = -ENOMEM; |
62fdfeaf EA |
1192 | goto err_unpin; |
1193 | } | |
8187a2b7 ZN |
1194 | ring->status_page.obj = obj; |
1195 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1196 | |
8187a2b7 ZN |
1197 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1198 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1199 | |
1200 | return 0; | |
1201 | ||
1202 | err_unpin: | |
1203 | i915_gem_object_unpin(obj); | |
1204 | err_unref: | |
05394f39 | 1205 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1206 | err: |
8187a2b7 | 1207 | return ret; |
62fdfeaf EA |
1208 | } |
1209 | ||
035dc1e0 | 1210 | static int init_phys_status_page(struct intel_ring_buffer *ring) |
6b8294a4 CW |
1211 | { |
1212 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1213 | |
1214 | if (!dev_priv->status_page_dmah) { | |
1215 | dev_priv->status_page_dmah = | |
1216 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1217 | if (!dev_priv->status_page_dmah) | |
1218 | return -ENOMEM; | |
1219 | } | |
1220 | ||
6b8294a4 CW |
1221 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1222 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
c43b5634 BW |
1227 | static int intel_init_ring_buffer(struct drm_device *dev, |
1228 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1229 | { |
05394f39 | 1230 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1231 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1232 | int ret; |
1233 | ||
8187a2b7 | 1234 | ring->dev = dev; |
23bc5982 CW |
1235 | INIT_LIST_HEAD(&ring->active_list); |
1236 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1237 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1238 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1239 | |
b259f673 | 1240 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1241 | |
8187a2b7 | 1242 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1243 | ret = init_status_page(ring); |
8187a2b7 ZN |
1244 | if (ret) |
1245 | return ret; | |
6b8294a4 CW |
1246 | } else { |
1247 | BUG_ON(ring->id != RCS); | |
035dc1e0 | 1248 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1249 | if (ret) |
1250 | return ret; | |
8187a2b7 | 1251 | } |
62fdfeaf | 1252 | |
ebc052e0 CW |
1253 | obj = NULL; |
1254 | if (!HAS_LLC(dev)) | |
1255 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1256 | if (obj == NULL) | |
1257 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1258 | if (obj == NULL) { |
1259 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1260 | ret = -ENOMEM; |
dd785e35 | 1261 | goto err_hws; |
62fdfeaf | 1262 | } |
62fdfeaf | 1263 | |
05394f39 | 1264 | ring->obj = obj; |
8187a2b7 | 1265 | |
c37e2204 | 1266 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1267 | if (ret) |
1268 | goto err_unref; | |
62fdfeaf | 1269 | |
3eef8918 CW |
1270 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1271 | if (ret) | |
1272 | goto err_unpin; | |
1273 | ||
dd2757f8 | 1274 | ring->virtual_start = |
f343c5f6 | 1275 | ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), |
dd2757f8 | 1276 | ring->size); |
4225d0f2 | 1277 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1278 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1279 | ret = -EINVAL; |
dd785e35 | 1280 | goto err_unpin; |
62fdfeaf EA |
1281 | } |
1282 | ||
78501eac | 1283 | ret = ring->init(ring); |
dd785e35 CW |
1284 | if (ret) |
1285 | goto err_unmap; | |
62fdfeaf | 1286 | |
55249baa CW |
1287 | /* Workaround an erratum on the i830 which causes a hang if |
1288 | * the TAIL pointer points to within the last 2 cachelines | |
1289 | * of the buffer. | |
1290 | */ | |
1291 | ring->effective_size = ring->size; | |
27c1cbd0 | 1292 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1293 | ring->effective_size -= 128; |
1294 | ||
c584fe47 | 1295 | return 0; |
dd785e35 CW |
1296 | |
1297 | err_unmap: | |
4225d0f2 | 1298 | iounmap(ring->virtual_start); |
dd785e35 CW |
1299 | err_unpin: |
1300 | i915_gem_object_unpin(obj); | |
1301 | err_unref: | |
05394f39 CW |
1302 | drm_gem_object_unreference(&obj->base); |
1303 | ring->obj = NULL; | |
dd785e35 | 1304 | err_hws: |
78501eac | 1305 | cleanup_status_page(ring); |
8187a2b7 | 1306 | return ret; |
62fdfeaf EA |
1307 | } |
1308 | ||
78501eac | 1309 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1310 | { |
33626e6a CW |
1311 | struct drm_i915_private *dev_priv; |
1312 | int ret; | |
1313 | ||
05394f39 | 1314 | if (ring->obj == NULL) |
62fdfeaf EA |
1315 | return; |
1316 | ||
33626e6a CW |
1317 | /* Disable the ring buffer. The ring must be idle at this point */ |
1318 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1319 | ret = intel_ring_idle(ring); |
29ee3991 CW |
1320 | if (ret) |
1321 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1322 | ring->name, ret); | |
1323 | ||
33626e6a CW |
1324 | I915_WRITE_CTL(ring, 0); |
1325 | ||
4225d0f2 | 1326 | iounmap(ring->virtual_start); |
62fdfeaf | 1327 | |
05394f39 CW |
1328 | i915_gem_object_unpin(ring->obj); |
1329 | drm_gem_object_unreference(&ring->obj->base); | |
1330 | ring->obj = NULL; | |
78501eac | 1331 | |
8d19215b ZN |
1332 | if (ring->cleanup) |
1333 | ring->cleanup(ring); | |
1334 | ||
78501eac | 1335 | cleanup_status_page(ring); |
62fdfeaf EA |
1336 | } |
1337 | ||
a71d8d94 CW |
1338 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1339 | { | |
a71d8d94 CW |
1340 | int ret; |
1341 | ||
199b2bc2 | 1342 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1343 | if (!ret) |
1344 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1345 | |
1346 | return ret; | |
1347 | } | |
1348 | ||
1349 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1350 | { | |
1351 | struct drm_i915_gem_request *request; | |
1352 | u32 seqno = 0; | |
1353 | int ret; | |
1354 | ||
1355 | i915_gem_retire_requests_ring(ring); | |
1356 | ||
1357 | if (ring->last_retired_head != -1) { | |
1358 | ring->head = ring->last_retired_head; | |
1359 | ring->last_retired_head = -1; | |
1360 | ring->space = ring_space(ring); | |
1361 | if (ring->space >= n) | |
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | list_for_each_entry(request, &ring->request_list, list) { | |
1366 | int space; | |
1367 | ||
1368 | if (request->tail == -1) | |
1369 | continue; | |
1370 | ||
633cf8f5 | 1371 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1372 | if (space < 0) |
1373 | space += ring->size; | |
1374 | if (space >= n) { | |
1375 | seqno = request->seqno; | |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | /* Consume this request in case we need more space than | |
1380 | * is available and so need to prevent a race between | |
1381 | * updating last_retired_head and direct reads of | |
1382 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1383 | */ | |
1384 | request->tail = -1; | |
1385 | } | |
1386 | ||
1387 | if (seqno == 0) | |
1388 | return -ENOSPC; | |
1389 | ||
1390 | ret = intel_ring_wait_seqno(ring, seqno); | |
1391 | if (ret) | |
1392 | return ret; | |
1393 | ||
1394 | if (WARN_ON(ring->last_retired_head == -1)) | |
1395 | return -ENOSPC; | |
1396 | ||
1397 | ring->head = ring->last_retired_head; | |
1398 | ring->last_retired_head = -1; | |
1399 | ring->space = ring_space(ring); | |
1400 | if (WARN_ON(ring->space < n)) | |
1401 | return -ENOSPC; | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
3e960501 | 1406 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1407 | { |
78501eac | 1408 | struct drm_device *dev = ring->dev; |
cae5852d | 1409 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1410 | unsigned long end; |
a71d8d94 | 1411 | int ret; |
c7dca47b | 1412 | |
a71d8d94 CW |
1413 | ret = intel_ring_wait_request(ring, n); |
1414 | if (ret != -ENOSPC) | |
1415 | return ret; | |
1416 | ||
db53a302 | 1417 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1418 | /* With GEM the hangcheck timer should kick us out of the loop, |
1419 | * leaving it early runs the risk of corrupting GEM state (due | |
1420 | * to running on almost untested codepaths). But on resume | |
1421 | * timers don't work yet, so prevent a complete hang in that | |
1422 | * case by choosing an insanely large timeout. */ | |
1423 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1424 | |
8187a2b7 | 1425 | do { |
c7dca47b CW |
1426 | ring->head = I915_READ_HEAD(ring); |
1427 | ring->space = ring_space(ring); | |
62fdfeaf | 1428 | if (ring->space >= n) { |
db53a302 | 1429 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1430 | return 0; |
1431 | } | |
1432 | ||
1433 | if (dev->primary->master) { | |
1434 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1435 | if (master_priv->sarea_priv) | |
1436 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1437 | } | |
d1b851fc | 1438 | |
e60a0b10 | 1439 | msleep(1); |
d6b2c790 | 1440 | |
33196ded DV |
1441 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1442 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1443 | if (ret) |
1444 | return ret; | |
8187a2b7 | 1445 | } while (!time_after(jiffies, end)); |
db53a302 | 1446 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1447 | return -EBUSY; |
1448 | } | |
62fdfeaf | 1449 | |
3e960501 CW |
1450 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1451 | { | |
1452 | uint32_t __iomem *virt; | |
1453 | int rem = ring->size - ring->tail; | |
1454 | ||
1455 | if (ring->space < rem) { | |
1456 | int ret = ring_wait_for_space(ring, rem); | |
1457 | if (ret) | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | virt = ring->virtual_start + ring->tail; | |
1462 | rem /= 4; | |
1463 | while (rem--) | |
1464 | iowrite32(MI_NOOP, virt++); | |
1465 | ||
1466 | ring->tail = 0; | |
1467 | ring->space = ring_space(ring); | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1473 | { | |
1474 | u32 seqno; | |
1475 | int ret; | |
1476 | ||
1477 | /* We need to add any requests required to flush the objects and ring */ | |
1823521d | 1478 | if (ring->outstanding_lazy_seqno) { |
0025c077 | 1479 | ret = i915_add_request(ring, NULL); |
3e960501 CW |
1480 | if (ret) |
1481 | return ret; | |
1482 | } | |
1483 | ||
1484 | /* Wait upon the last request to be completed */ | |
1485 | if (list_empty(&ring->request_list)) | |
1486 | return 0; | |
1487 | ||
1488 | seqno = list_entry(ring->request_list.prev, | |
1489 | struct drm_i915_gem_request, | |
1490 | list)->seqno; | |
1491 | ||
1492 | return i915_wait_seqno(ring, seqno); | |
1493 | } | |
1494 | ||
9d773091 CW |
1495 | static int |
1496 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1497 | { | |
1823521d | 1498 | if (ring->outstanding_lazy_seqno) |
9d773091 CW |
1499 | return 0; |
1500 | ||
3c0e234c CW |
1501 | if (ring->preallocated_lazy_request == NULL) { |
1502 | struct drm_i915_gem_request *request; | |
1503 | ||
1504 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1505 | if (request == NULL) | |
1506 | return -ENOMEM; | |
1507 | ||
1508 | ring->preallocated_lazy_request = request; | |
1509 | } | |
1510 | ||
1823521d | 1511 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); |
9d773091 CW |
1512 | } |
1513 | ||
cbcc80df MK |
1514 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
1515 | int bytes) | |
1516 | { | |
1517 | int ret; | |
1518 | ||
1519 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1520 | ret = intel_wrap_ring_buffer(ring); | |
1521 | if (unlikely(ret)) | |
1522 | return ret; | |
1523 | } | |
1524 | ||
1525 | if (unlikely(ring->space < bytes)) { | |
1526 | ret = ring_wait_for_space(ring, bytes); | |
1527 | if (unlikely(ret)) | |
1528 | return ret; | |
1529 | } | |
1530 | ||
1531 | ring->space -= bytes; | |
1532 | return 0; | |
1533 | } | |
1534 | ||
e1f99ce6 CW |
1535 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1536 | int num_dwords) | |
8187a2b7 | 1537 | { |
de2b9985 | 1538 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1539 | int ret; |
78501eac | 1540 | |
33196ded DV |
1541 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1542 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1543 | if (ret) |
1544 | return ret; | |
21dd3734 | 1545 | |
9d773091 CW |
1546 | /* Preallocate the olr before touching the ring */ |
1547 | ret = intel_ring_alloc_seqno(ring); | |
1548 | if (ret) | |
1549 | return ret; | |
1550 | ||
cbcc80df | 1551 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
8187a2b7 | 1552 | } |
78501eac | 1553 | |
f7e98ad4 | 1554 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1555 | { |
f7e98ad4 | 1556 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 | 1557 | |
1823521d | 1558 | BUG_ON(ring->outstanding_lazy_seqno); |
498d2ac1 | 1559 | |
f7e98ad4 MK |
1560 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1561 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1562 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
5020150b BW |
1563 | if (HAS_VEBOX(ring->dev)) |
1564 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); | |
e1f99ce6 | 1565 | } |
d97ed339 | 1566 | |
f7e98ad4 | 1567 | ring->set_seqno(ring, seqno); |
92cab734 | 1568 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1569 | } |
62fdfeaf | 1570 | |
78501eac | 1571 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1572 | { |
e5eb3d63 DV |
1573 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1574 | ||
d97ed339 | 1575 | ring->tail &= ring->size - 1; |
99584db3 | 1576 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
e5eb3d63 | 1577 | return; |
78501eac | 1578 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1579 | } |
62fdfeaf | 1580 | |
881f47b6 | 1581 | |
78501eac | 1582 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1583 | u32 value) |
881f47b6 | 1584 | { |
0206e353 | 1585 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1586 | |
1587 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1588 | |
1589 | /* Disable notification that the ring is IDLE. The GT | |
1590 | * will then assume that it is busy and bring it out of rc6. | |
1591 | */ | |
0206e353 | 1592 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1593 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1594 | ||
1595 | /* Clear the context id. Here be magic! */ | |
1596 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1597 | |
12f55818 | 1598 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1599 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1600 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1601 | 50)) | |
1602 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1603 | |
12f55818 | 1604 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1605 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1606 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1607 | ||
1608 | /* Let the ring send IDLE messages to the GT again, | |
1609 | * and so let it sleep to conserve power when idle. | |
1610 | */ | |
0206e353 | 1611 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1612 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1613 | } |
1614 | ||
ea251324 BW |
1615 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1616 | u32 invalidate, u32 flush) | |
881f47b6 | 1617 | { |
71a77e07 | 1618 | uint32_t cmd; |
b72f3acb CW |
1619 | int ret; |
1620 | ||
b72f3acb CW |
1621 | ret = intel_ring_begin(ring, 4); |
1622 | if (ret) | |
1623 | return ret; | |
1624 | ||
71a77e07 | 1625 | cmd = MI_FLUSH_DW; |
9a289771 JB |
1626 | /* |
1627 | * Bspec vol 1c.5 - video engine command streamer: | |
1628 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1629 | * operation is complete. This bit is only valid when the | |
1630 | * Post-Sync Operation field is a value of 1h or 3h." | |
1631 | */ | |
71a77e07 | 1632 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1633 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1634 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1635 | intel_ring_emit(ring, cmd); |
9a289771 | 1636 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
b72f3acb | 1637 | intel_ring_emit(ring, 0); |
71a77e07 | 1638 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1639 | intel_ring_advance(ring); |
1640 | return 0; | |
881f47b6 XH |
1641 | } |
1642 | ||
d7d4eedd CW |
1643 | static int |
1644 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1645 | u32 offset, u32 len, | |
1646 | unsigned flags) | |
1647 | { | |
1648 | int ret; | |
1649 | ||
1650 | ret = intel_ring_begin(ring, 2); | |
1651 | if (ret) | |
1652 | return ret; | |
1653 | ||
1654 | intel_ring_emit(ring, | |
1655 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1656 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1657 | /* bit0-7 is the length on GEN6+ */ | |
1658 | intel_ring_emit(ring, offset); | |
1659 | intel_ring_advance(ring); | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
881f47b6 | 1664 | static int |
78501eac | 1665 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1666 | u32 offset, u32 len, |
1667 | unsigned flags) | |
881f47b6 | 1668 | { |
0206e353 | 1669 | int ret; |
ab6f8e32 | 1670 | |
0206e353 AJ |
1671 | ret = intel_ring_begin(ring, 2); |
1672 | if (ret) | |
1673 | return ret; | |
e1f99ce6 | 1674 | |
d7d4eedd CW |
1675 | intel_ring_emit(ring, |
1676 | MI_BATCH_BUFFER_START | | |
1677 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1678 | /* bit0-7 is the length on GEN6+ */ |
1679 | intel_ring_emit(ring, offset); | |
1680 | intel_ring_advance(ring); | |
ab6f8e32 | 1681 | |
0206e353 | 1682 | return 0; |
881f47b6 XH |
1683 | } |
1684 | ||
549f7365 CW |
1685 | /* Blitter support (SandyBridge+) */ |
1686 | ||
ea251324 BW |
1687 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1688 | u32 invalidate, u32 flush) | |
8d19215b | 1689 | { |
fd3da6c9 | 1690 | struct drm_device *dev = ring->dev; |
71a77e07 | 1691 | uint32_t cmd; |
b72f3acb CW |
1692 | int ret; |
1693 | ||
6a233c78 | 1694 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1695 | if (ret) |
1696 | return ret; | |
1697 | ||
71a77e07 | 1698 | cmd = MI_FLUSH_DW; |
9a289771 JB |
1699 | /* |
1700 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1701 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1702 | * operation is complete. This bit is only valid when the | |
1703 | * Post-Sync Operation field is a value of 1h or 3h." | |
1704 | */ | |
71a77e07 | 1705 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1706 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1707 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1708 | intel_ring_emit(ring, cmd); |
9a289771 | 1709 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
b72f3acb | 1710 | intel_ring_emit(ring, 0); |
71a77e07 | 1711 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb | 1712 | intel_ring_advance(ring); |
fd3da6c9 RV |
1713 | |
1714 | if (IS_GEN7(dev) && flush) | |
1715 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
1716 | ||
b72f3acb | 1717 | return 0; |
8d19215b ZN |
1718 | } |
1719 | ||
5c1143bb XH |
1720 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1721 | { | |
1722 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1723 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1724 | |
59465b5f DV |
1725 | ring->name = "render ring"; |
1726 | ring->id = RCS; | |
1727 | ring->mmio_base = RENDER_RING_BASE; | |
1728 | ||
1ec14ad3 CW |
1729 | if (INTEL_INFO(dev)->gen >= 6) { |
1730 | ring->add_request = gen6_add_request; | |
4772eaeb | 1731 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1732 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1733 | ring->flush = gen6_render_ring_flush; |
25c06300 BW |
1734 | ring->irq_get = gen6_ring_get_irq; |
1735 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 1736 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1737 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1738 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1739 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1740 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1741 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1742 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1743 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1744 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1745 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1746 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1747 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1748 | } else if (IS_GEN5(dev)) { |
1749 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1750 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1751 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1752 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1753 | ring->irq_get = gen5_ring_get_irq; |
1754 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1755 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1756 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1757 | } else { |
8620a3a9 | 1758 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1759 | if (INTEL_INFO(dev)->gen < 4) |
1760 | ring->flush = gen2_render_ring_flush; | |
1761 | else | |
1762 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1763 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1764 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1765 | if (IS_GEN2(dev)) { |
1766 | ring->irq_get = i8xx_ring_get_irq; | |
1767 | ring->irq_put = i8xx_ring_put_irq; | |
1768 | } else { | |
1769 | ring->irq_get = i9xx_ring_get_irq; | |
1770 | ring->irq_put = i9xx_ring_put_irq; | |
1771 | } | |
e3670319 | 1772 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1773 | } |
59465b5f | 1774 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1775 | if (IS_HASWELL(dev)) |
1776 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1777 | else if (INTEL_INFO(dev)->gen >= 6) | |
fb3256da DV |
1778 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1779 | else if (INTEL_INFO(dev)->gen >= 4) | |
1780 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1781 | else if (IS_I830(dev) || IS_845G(dev)) | |
1782 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1783 | else | |
1784 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1785 | ring->init = init_render_ring; |
1786 | ring->cleanup = render_ring_cleanup; | |
1787 | ||
b45305fc DV |
1788 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1789 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1790 | struct drm_i915_gem_object *obj; | |
1791 | int ret; | |
1792 | ||
1793 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1794 | if (obj == NULL) { | |
1795 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1796 | return -ENOMEM; | |
1797 | } | |
1798 | ||
c37e2204 | 1799 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
b45305fc DV |
1800 | if (ret != 0) { |
1801 | drm_gem_object_unreference(&obj->base); | |
1802 | DRM_ERROR("Failed to ping batch bo\n"); | |
1803 | return ret; | |
1804 | } | |
1805 | ||
0d1aacac CW |
1806 | ring->scratch.obj = obj; |
1807 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
1808 | } |
1809 | ||
1ec14ad3 | 1810 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1811 | } |
1812 | ||
e8616b6c CW |
1813 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1814 | { | |
1815 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1816 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
6b8294a4 | 1817 | int ret; |
e8616b6c | 1818 | |
59465b5f DV |
1819 | ring->name = "render ring"; |
1820 | ring->id = RCS; | |
1821 | ring->mmio_base = RENDER_RING_BASE; | |
1822 | ||
e8616b6c | 1823 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1824 | /* non-kms not supported on gen6+ */ |
1825 | return -ENODEV; | |
e8616b6c | 1826 | } |
28f0cbf7 DV |
1827 | |
1828 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1829 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1830 | * the special gen5 functions. */ | |
1831 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1832 | if (INTEL_INFO(dev)->gen < 4) |
1833 | ring->flush = gen2_render_ring_flush; | |
1834 | else | |
1835 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1836 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1837 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1838 | if (IS_GEN2(dev)) { |
1839 | ring->irq_get = i8xx_ring_get_irq; | |
1840 | ring->irq_put = i8xx_ring_put_irq; | |
1841 | } else { | |
1842 | ring->irq_get = i9xx_ring_get_irq; | |
1843 | ring->irq_put = i9xx_ring_put_irq; | |
1844 | } | |
28f0cbf7 | 1845 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1846 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1847 | if (INTEL_INFO(dev)->gen >= 4) |
1848 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1849 | else if (IS_I830(dev) || IS_845G(dev)) | |
1850 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1851 | else | |
1852 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1853 | ring->init = init_render_ring; |
1854 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
1855 | |
1856 | ring->dev = dev; | |
1857 | INIT_LIST_HEAD(&ring->active_list); | |
1858 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1859 | |
1860 | ring->size = size; | |
1861 | ring->effective_size = ring->size; | |
17f10fdc | 1862 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
1863 | ring->effective_size -= 128; |
1864 | ||
4225d0f2 DV |
1865 | ring->virtual_start = ioremap_wc(start, size); |
1866 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1867 | DRM_ERROR("can not ioremap virtual address for" |
1868 | " ring buffer\n"); | |
1869 | return -ENOMEM; | |
1870 | } | |
1871 | ||
6b8294a4 | 1872 | if (!I915_NEED_GFX_HWS(dev)) { |
035dc1e0 | 1873 | ret = init_phys_status_page(ring); |
6b8294a4 CW |
1874 | if (ret) |
1875 | return ret; | |
1876 | } | |
1877 | ||
e8616b6c CW |
1878 | return 0; |
1879 | } | |
1880 | ||
5c1143bb XH |
1881 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1882 | { | |
1883 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1884 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1885 | |
58fa3835 DV |
1886 | ring->name = "bsd ring"; |
1887 | ring->id = VCS; | |
1888 | ||
0fd2c201 | 1889 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1890 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1891 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1892 | /* gen6 bsd needs a special wa for tail updates */ |
1893 | if (IS_GEN6(dev)) | |
1894 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 1895 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
1896 | ring->add_request = gen6_add_request; |
1897 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 1898 | ring->set_seqno = ring_set_seqno; |
cc609d5d | 1899 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 DV |
1900 | ring->irq_get = gen6_ring_get_irq; |
1901 | ring->irq_put = gen6_ring_put_irq; | |
1902 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1903 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1904 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
1905 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1906 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 1907 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
1908 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
1909 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
1910 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 1911 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
1912 | } else { |
1913 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1914 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1915 | ring->add_request = i9xx_add_request; |
58fa3835 | 1916 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1917 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 1918 | if (IS_GEN5(dev)) { |
cc609d5d | 1919 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
1920 | ring->irq_get = gen5_ring_get_irq; |
1921 | ring->irq_put = gen5_ring_put_irq; | |
1922 | } else { | |
e3670319 | 1923 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1924 | ring->irq_get = i9xx_ring_get_irq; |
1925 | ring->irq_put = i9xx_ring_put_irq; | |
1926 | } | |
fb3256da | 1927 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1928 | } |
1929 | ring->init = init_ring_common; | |
1930 | ||
1ec14ad3 | 1931 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1932 | } |
549f7365 CW |
1933 | |
1934 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1935 | { | |
1936 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1937 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1938 | |
3535d9dd DV |
1939 | ring->name = "blitter ring"; |
1940 | ring->id = BCS; | |
1941 | ||
1942 | ring->mmio_base = BLT_RING_BASE; | |
1943 | ring->write_tail = ring_write_tail; | |
ea251324 | 1944 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
1945 | ring->add_request = gen6_add_request; |
1946 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 1947 | ring->set_seqno = ring_set_seqno; |
cc609d5d | 1948 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3535d9dd DV |
1949 | ring->irq_get = gen6_ring_get_irq; |
1950 | ring->irq_put = gen6_ring_put_irq; | |
1951 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1952 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1953 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
1954 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
1955 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 1956 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
1957 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
1958 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
1959 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 1960 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 1961 | ring->init = init_ring_common; |
549f7365 | 1962 | |
1ec14ad3 | 1963 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1964 | } |
a7b9761d | 1965 | |
9a8a2213 BW |
1966 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
1967 | { | |
1968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1969 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; | |
1970 | ||
1971 | ring->name = "video enhancement ring"; | |
1972 | ring->id = VECS; | |
1973 | ||
1974 | ring->mmio_base = VEBOX_RING_BASE; | |
1975 | ring->write_tail = ring_write_tail; | |
1976 | ring->flush = gen6_ring_flush; | |
1977 | ring->add_request = gen6_add_request; | |
1978 | ring->get_seqno = gen6_ring_get_seqno; | |
1979 | ring->set_seqno = ring_set_seqno; | |
c0d6a3dd | 1980 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; |
a19d2933 BW |
1981 | ring->irq_get = hsw_vebox_get_irq; |
1982 | ring->irq_put = hsw_vebox_put_irq; | |
9a8a2213 BW |
1983 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1984 | ring->sync_to = gen6_ring_sync; | |
1985 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
1986 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
1987 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
1988 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
1989 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
1990 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
1991 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
1992 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
1993 | ring->init = init_ring_common; | |
1994 | ||
1995 | return intel_init_ring_buffer(dev, ring); | |
1996 | } | |
1997 | ||
a7b9761d CW |
1998 | int |
1999 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
2000 | { | |
2001 | int ret; | |
2002 | ||
2003 | if (!ring->gpu_caches_dirty) | |
2004 | return 0; | |
2005 | ||
2006 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2007 | if (ret) | |
2008 | return ret; | |
2009 | ||
2010 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2011 | ||
2012 | ring->gpu_caches_dirty = false; | |
2013 | return 0; | |
2014 | } | |
2015 | ||
2016 | int | |
2017 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
2018 | { | |
2019 | uint32_t flush_domains; | |
2020 | int ret; | |
2021 | ||
2022 | flush_domains = 0; | |
2023 | if (ring->gpu_caches_dirty) | |
2024 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2025 | ||
2026 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2027 | if (ret) | |
2028 | return ret; | |
2029 | ||
2030 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2031 | ||
2032 | ring->gpu_caches_dirty = false; | |
2033 | return 0; | |
2034 | } |