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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
18393f63 | 52 | |
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
4f54741e DG |
55 | int space = head - tail; |
56 | if (space <= 0) | |
1cf0ba14 | 57 | space += size; |
4f54741e | 58 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
59 | } |
60 | ||
ebd0fd4b DG |
61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
62 | { | |
63 | if (ringbuf->last_retired_head != -1) { | |
64 | ringbuf->head = ringbuf->last_retired_head; | |
65 | ringbuf->last_retired_head = -1; | |
66 | } | |
67 | ||
68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
69 | ringbuf->tail, ringbuf->size); | |
70 | } | |
71 | ||
82e104cc | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 73 | { |
ebd0fd4b DG |
74 | intel_ring_update_space(ringbuf); |
75 | return ringbuf->space; | |
1cf0ba14 CW |
76 | } |
77 | ||
82e104cc | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
82 | } | |
09246732 | 83 | |
a4872ba6 | 84 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 85 | { |
93b0a4e0 OM |
86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
87 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 88 | if (intel_ring_stopped(ring)) |
09246732 | 89 | return; |
93b0a4e0 | 90 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
91 | } |
92 | ||
b72f3acb | 93 | static int |
a4872ba6 | 94 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
95 | u32 invalidate_domains, |
96 | u32 flush_domains) | |
97 | { | |
98 | u32 cmd; | |
99 | int ret; | |
100 | ||
101 | cmd = MI_FLUSH; | |
31b14c9f | 102 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
103 | cmd |= MI_NO_WRITE_FLUSH; |
104 | ||
105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
106 | cmd |= MI_READ_FLUSH; | |
107 | ||
108 | ret = intel_ring_begin(ring, 2); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
112 | intel_ring_emit(ring, cmd); | |
113 | intel_ring_emit(ring, MI_NOOP); | |
114 | intel_ring_advance(ring); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | static int | |
a4872ba6 | 120 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
121 | u32 invalidate_domains, |
122 | u32 flush_domains) | |
62fdfeaf | 123 | { |
78501eac | 124 | struct drm_device *dev = ring->dev; |
6f392d54 | 125 | u32 cmd; |
b72f3acb | 126 | int ret; |
6f392d54 | 127 | |
36d527de CW |
128 | /* |
129 | * read/write caches: | |
130 | * | |
131 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
132 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
133 | * also flushed at 2d versus 3d pipeline switches. | |
134 | * | |
135 | * read-only caches: | |
136 | * | |
137 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
138 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
139 | * | |
140 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
141 | * | |
142 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
143 | * invalidated when MI_EXE_FLUSH is set. | |
144 | * | |
145 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
146 | * invalidated with every MI_FLUSH. | |
147 | * | |
148 | * TLBs: | |
149 | * | |
150 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
151 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
152 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
153 | * are flushed at any MI_FLUSH. | |
154 | */ | |
155 | ||
156 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 157 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 158 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
159 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
160 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 161 | |
36d527de CW |
162 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
163 | (IS_G4X(dev) || IS_GEN5(dev))) | |
164 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 165 | |
36d527de CW |
166 | ret = intel_ring_begin(ring, 2); |
167 | if (ret) | |
168 | return ret; | |
b72f3acb | 169 | |
36d527de CW |
170 | intel_ring_emit(ring, cmd); |
171 | intel_ring_emit(ring, MI_NOOP); | |
172 | intel_ring_advance(ring); | |
b72f3acb CW |
173 | |
174 | return 0; | |
8187a2b7 ZN |
175 | } |
176 | ||
8d315287 JB |
177 | /** |
178 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
179 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
180 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
181 | * | |
182 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
183 | * produced by non-pipelined state commands), software needs to first | |
184 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
185 | * 0. | |
186 | * | |
187 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
188 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
189 | * | |
190 | * And the workaround for these two requires this workaround first: | |
191 | * | |
192 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
193 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
194 | * flushes. | |
195 | * | |
196 | * And this last workaround is tricky because of the requirements on | |
197 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
198 | * volume 2 part 1: | |
199 | * | |
200 | * "1 of the following must also be set: | |
201 | * - Render Target Cache Flush Enable ([12] of DW1) | |
202 | * - Depth Cache Flush Enable ([0] of DW1) | |
203 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
204 | * - Depth Stall ([13] of DW1) | |
205 | * - Post-Sync Operation ([13] of DW1) | |
206 | * - Notify Enable ([8] of DW1)" | |
207 | * | |
208 | * The cache flushes require the workaround flush that triggered this | |
209 | * one, so we can't use it. Depth stall would trigger the same. | |
210 | * Post-sync nonzero is what triggered this second workaround, so we | |
211 | * can't use that one either. Notify enable is IRQs, which aren't | |
212 | * really our business. That leaves only stall at scoreboard. | |
213 | */ | |
214 | static int | |
a4872ba6 | 215 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 216 | { |
18393f63 | 217 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
218 | int ret; |
219 | ||
220 | ||
221 | ret = intel_ring_begin(ring, 6); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
226 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
227 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
228 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
229 | intel_ring_emit(ring, 0); /* low dword */ | |
230 | intel_ring_emit(ring, 0); /* high dword */ | |
231 | intel_ring_emit(ring, MI_NOOP); | |
232 | intel_ring_advance(ring); | |
233 | ||
234 | ret = intel_ring_begin(ring, 6); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
239 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
240 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
241 | intel_ring_emit(ring, 0); | |
242 | intel_ring_emit(ring, 0); | |
243 | intel_ring_emit(ring, MI_NOOP); | |
244 | intel_ring_advance(ring); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static int | |
a4872ba6 | 250 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
251 | u32 invalidate_domains, u32 flush_domains) |
252 | { | |
253 | u32 flags = 0; | |
18393f63 | 254 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
255 | int ret; |
256 | ||
b3111509 PZ |
257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
258 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
259 | if (ret) | |
260 | return ret; | |
261 | ||
8d315287 JB |
262 | /* Just flush everything. Experiments have shown that reducing the |
263 | * number of bits based on the write domains has little performance | |
264 | * impact. | |
265 | */ | |
7d54a904 CW |
266 | if (flush_domains) { |
267 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
268 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
269 | /* | |
270 | * Ensure that any following seqno writes only happen | |
271 | * when the render cache is indeed flushed. | |
272 | */ | |
97f209bc | 273 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
274 | } |
275 | if (invalidate_domains) { | |
276 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
278 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
279 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
282 | /* | |
283 | * TLB invalidate requires a post-sync write. | |
284 | */ | |
3ac78313 | 285 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 286 | } |
8d315287 | 287 | |
6c6cf5aa | 288 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
289 | if (ret) |
290 | return ret; | |
291 | ||
6c6cf5aa | 292 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
293 | intel_ring_emit(ring, flags); |
294 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 295 | intel_ring_emit(ring, 0); |
8d315287 JB |
296 | intel_ring_advance(ring); |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
f3987631 | 301 | static int |
a4872ba6 | 302 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
303 | { |
304 | int ret; | |
305 | ||
306 | ret = intel_ring_begin(ring, 4); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
311 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
312 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
313 | intel_ring_emit(ring, 0); | |
314 | intel_ring_emit(ring, 0); | |
315 | intel_ring_advance(ring); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
a4872ba6 | 320 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
321 | { |
322 | int ret; | |
323 | ||
324 | if (!ring->fbc_dirty) | |
325 | return 0; | |
326 | ||
37c1d94f | 327 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
328 | if (ret) |
329 | return ret; | |
fd3da6c9 RV |
330 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
331 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
332 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
333 | intel_ring_emit(ring, value); | |
37c1d94f VS |
334 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
335 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
336 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
337 | intel_ring_advance(ring); |
338 | ||
339 | ring->fbc_dirty = false; | |
340 | return 0; | |
341 | } | |
342 | ||
4772eaeb | 343 | static int |
a4872ba6 | 344 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
345 | u32 invalidate_domains, u32 flush_domains) |
346 | { | |
347 | u32 flags = 0; | |
18393f63 | 348 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
349 | int ret; |
350 | ||
f3987631 PZ |
351 | /* |
352 | * Ensure that any following seqno writes only happen when the render | |
353 | * cache is indeed flushed. | |
354 | * | |
355 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
356 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
357 | * don't try to be clever and just set it unconditionally. | |
358 | */ | |
359 | flags |= PIPE_CONTROL_CS_STALL; | |
360 | ||
4772eaeb PZ |
361 | /* Just flush everything. Experiments have shown that reducing the |
362 | * number of bits based on the write domains has little performance | |
363 | * impact. | |
364 | */ | |
365 | if (flush_domains) { | |
366 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
367 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
368 | } |
369 | if (invalidate_domains) { | |
370 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
372 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
373 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
375 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
376 | /* | |
377 | * TLB invalidate requires a post-sync write. | |
378 | */ | |
379 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 380 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
381 | |
382 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
383 | * set before a pipe_control command that has the state cache | |
384 | * invalidate bit set. */ | |
385 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
386 | } |
387 | ||
388 | ret = intel_ring_begin(ring, 4); | |
389 | if (ret) | |
390 | return ret; | |
391 | ||
392 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
393 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 394 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
395 | intel_ring_emit(ring, 0); |
396 | intel_ring_advance(ring); | |
397 | ||
9688ecad | 398 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
399 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
400 | ||
4772eaeb PZ |
401 | return 0; |
402 | } | |
403 | ||
884ceace KG |
404 | static int |
405 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
406 | u32 flags, u32 scratch_addr) | |
407 | { | |
408 | int ret; | |
409 | ||
410 | ret = intel_ring_begin(ring, 6); | |
411 | if (ret) | |
412 | return ret; | |
413 | ||
414 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
415 | intel_ring_emit(ring, flags); | |
416 | intel_ring_emit(ring, scratch_addr); | |
417 | intel_ring_emit(ring, 0); | |
418 | intel_ring_emit(ring, 0); | |
419 | intel_ring_emit(ring, 0); | |
420 | intel_ring_advance(ring); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
a5f3d68e | 425 | static int |
a4872ba6 | 426 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
427 | u32 invalidate_domains, u32 flush_domains) |
428 | { | |
429 | u32 flags = 0; | |
18393f63 | 430 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 431 | int ret; |
a5f3d68e BW |
432 | |
433 | flags |= PIPE_CONTROL_CS_STALL; | |
434 | ||
435 | if (flush_domains) { | |
436 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
437 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
438 | } | |
439 | if (invalidate_domains) { | |
440 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
441 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
442 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
443 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
444 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
445 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
446 | flags |= PIPE_CONTROL_QW_WRITE; | |
447 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
448 | |
449 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
450 | ret = gen8_emit_pipe_control(ring, | |
451 | PIPE_CONTROL_CS_STALL | | |
452 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
453 | 0); | |
454 | if (ret) | |
455 | return ret; | |
a5f3d68e BW |
456 | } |
457 | ||
c5ad011d RV |
458 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
459 | if (ret) | |
460 | return ret; | |
461 | ||
462 | if (!invalidate_domains && flush_domains) | |
463 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
464 | ||
465 | return 0; | |
a5f3d68e BW |
466 | } |
467 | ||
a4872ba6 | 468 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 469 | u32 value) |
d46eefa2 | 470 | { |
4640c4ff | 471 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 472 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
473 | } |
474 | ||
a4872ba6 | 475 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 476 | { |
4640c4ff | 477 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 478 | u64 acthd; |
8187a2b7 | 479 | |
50877445 CW |
480 | if (INTEL_INFO(ring->dev)->gen >= 8) |
481 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
482 | RING_ACTHD_UDW(ring->mmio_base)); | |
483 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
484 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
485 | else | |
486 | acthd = I915_READ(ACTHD); | |
487 | ||
488 | return acthd; | |
8187a2b7 ZN |
489 | } |
490 | ||
a4872ba6 | 491 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
492 | { |
493 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
494 | u32 addr; | |
495 | ||
496 | addr = dev_priv->status_page_dmah->busaddr; | |
497 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
498 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
499 | I915_WRITE(HWS_PGA, addr); | |
500 | } | |
501 | ||
a4872ba6 | 502 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 503 | { |
9991ae78 | 504 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 505 | |
9991ae78 CW |
506 | if (!IS_GEN2(ring->dev)) { |
507 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
508 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
509 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
510 | /* Sometimes we observe that the idle flag is not |
511 | * set even though the ring is empty. So double | |
512 | * check before giving up. | |
513 | */ | |
514 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
515 | return false; | |
9991ae78 CW |
516 | } |
517 | } | |
b7884eb4 | 518 | |
7f2ab699 | 519 | I915_WRITE_CTL(ring, 0); |
570ef608 | 520 | I915_WRITE_HEAD(ring, 0); |
78501eac | 521 | ring->write_tail(ring, 0); |
8187a2b7 | 522 | |
9991ae78 CW |
523 | if (!IS_GEN2(ring->dev)) { |
524 | (void)I915_READ_CTL(ring); | |
525 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
526 | } | |
a51435a3 | 527 | |
9991ae78 CW |
528 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
529 | } | |
8187a2b7 | 530 | |
a4872ba6 | 531 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
532 | { |
533 | struct drm_device *dev = ring->dev; | |
534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
535 | struct intel_ringbuffer *ringbuf = ring->buffer; |
536 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
537 | int ret = 0; |
538 | ||
539 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
540 | ||
541 | if (!stop_ring(ring)) { | |
542 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
543 | DRM_DEBUG_KMS("%s head not reset to zero " |
544 | "ctl %08x head %08x tail %08x start %08x\n", | |
545 | ring->name, | |
546 | I915_READ_CTL(ring), | |
547 | I915_READ_HEAD(ring), | |
548 | I915_READ_TAIL(ring), | |
549 | I915_READ_START(ring)); | |
8187a2b7 | 550 | |
9991ae78 | 551 | if (!stop_ring(ring)) { |
6fd0d56e CW |
552 | DRM_ERROR("failed to set %s head to zero " |
553 | "ctl %08x head %08x tail %08x start %08x\n", | |
554 | ring->name, | |
555 | I915_READ_CTL(ring), | |
556 | I915_READ_HEAD(ring), | |
557 | I915_READ_TAIL(ring), | |
558 | I915_READ_START(ring)); | |
9991ae78 CW |
559 | ret = -EIO; |
560 | goto out; | |
6fd0d56e | 561 | } |
8187a2b7 ZN |
562 | } |
563 | ||
9991ae78 CW |
564 | if (I915_NEED_GFX_HWS(dev)) |
565 | intel_ring_setup_status_page(ring); | |
566 | else | |
567 | ring_setup_phys_status_page(ring); | |
568 | ||
ece4a17d JK |
569 | /* Enforce ordering by reading HEAD register back */ |
570 | I915_READ_HEAD(ring); | |
571 | ||
0d8957c8 DV |
572 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
573 | * registers with the above sequence (the readback of the HEAD registers | |
574 | * also enforces ordering), otherwise the hw might lose the new ring | |
575 | * register values. */ | |
f343c5f6 | 576 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
577 | |
578 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
579 | if (I915_READ_HEAD(ring)) | |
580 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
581 | ring->name, I915_READ_HEAD(ring)); | |
582 | I915_WRITE_HEAD(ring, 0); | |
583 | (void)I915_READ_HEAD(ring); | |
584 | ||
7f2ab699 | 585 | I915_WRITE_CTL(ring, |
93b0a4e0 | 586 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 587 | | RING_VALID); |
8187a2b7 | 588 | |
8187a2b7 | 589 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 590 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 591 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 592 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 593 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
594 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
595 | ring->name, | |
596 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
597 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
598 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
599 | ret = -EIO; |
600 | goto out; | |
8187a2b7 ZN |
601 | } |
602 | ||
ebd0fd4b | 603 | ringbuf->last_retired_head = -1; |
5c6c6003 CW |
604 | ringbuf->head = I915_READ_HEAD(ring); |
605 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
ebd0fd4b | 606 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 607 | |
50f018df CW |
608 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
609 | ||
b7884eb4 | 610 | out: |
c8d9a590 | 611 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
612 | |
613 | return ret; | |
8187a2b7 ZN |
614 | } |
615 | ||
9b1136d5 OM |
616 | void |
617 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
618 | { | |
619 | struct drm_device *dev = ring->dev; | |
620 | ||
621 | if (ring->scratch.obj == NULL) | |
622 | return; | |
623 | ||
624 | if (INTEL_INFO(dev)->gen >= 5) { | |
625 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
626 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
627 | } | |
628 | ||
629 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
630 | ring->scratch.obj = NULL; | |
631 | } | |
632 | ||
633 | int | |
634 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 635 | { |
c6df541c CW |
636 | int ret; |
637 | ||
bfc882b4 | 638 | WARN_ON(ring->scratch.obj); |
c6df541c | 639 | |
0d1aacac CW |
640 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
641 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
642 | DRM_ERROR("Failed to allocate seqno page\n"); |
643 | ret = -ENOMEM; | |
644 | goto err; | |
645 | } | |
e4ffd173 | 646 | |
a9cc726c DV |
647 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
648 | if (ret) | |
649 | goto err_unref; | |
c6df541c | 650 | |
1ec9e26d | 651 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
652 | if (ret) |
653 | goto err_unref; | |
654 | ||
0d1aacac CW |
655 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
656 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
657 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 658 | ret = -ENOMEM; |
c6df541c | 659 | goto err_unpin; |
56b085a0 | 660 | } |
c6df541c | 661 | |
2b1086cc | 662 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 663 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
664 | return 0; |
665 | ||
666 | err_unpin: | |
d7f46fc4 | 667 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 668 | err_unref: |
0d1aacac | 669 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 670 | err: |
c6df541c CW |
671 | return ret; |
672 | } | |
673 | ||
771b9a53 MT |
674 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
675 | struct intel_context *ctx) | |
86d7f238 | 676 | { |
7225342a | 677 | int ret, i; |
888b5995 AS |
678 | struct drm_device *dev = ring->dev; |
679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7225342a | 680 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 681 | |
7225342a MK |
682 | if (WARN_ON(w->count == 0)) |
683 | return 0; | |
888b5995 | 684 | |
7225342a MK |
685 | ring->gpu_caches_dirty = true; |
686 | ret = intel_ring_flush_all_caches(ring); | |
687 | if (ret) | |
688 | return ret; | |
888b5995 | 689 | |
22a916aa | 690 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
7225342a MK |
691 | if (ret) |
692 | return ret; | |
693 | ||
22a916aa | 694 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 695 | for (i = 0; i < w->count; i++) { |
7225342a MK |
696 | intel_ring_emit(ring, w->reg[i].addr); |
697 | intel_ring_emit(ring, w->reg[i].value); | |
698 | } | |
22a916aa | 699 | intel_ring_emit(ring, MI_NOOP); |
7225342a MK |
700 | |
701 | intel_ring_advance(ring); | |
702 | ||
703 | ring->gpu_caches_dirty = true; | |
704 | ret = intel_ring_flush_all_caches(ring); | |
705 | if (ret) | |
706 | return ret; | |
888b5995 | 707 | |
7225342a | 708 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 709 | |
7225342a | 710 | return 0; |
86d7f238 AS |
711 | } |
712 | ||
7225342a MK |
713 | static int wa_add(struct drm_i915_private *dev_priv, |
714 | const u32 addr, const u32 val, const u32 mask) | |
715 | { | |
716 | const u32 idx = dev_priv->workarounds.count; | |
717 | ||
718 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
719 | return -ENOSPC; | |
720 | ||
721 | dev_priv->workarounds.reg[idx].addr = addr; | |
722 | dev_priv->workarounds.reg[idx].value = val; | |
723 | dev_priv->workarounds.reg[idx].mask = mask; | |
724 | ||
725 | dev_priv->workarounds.count++; | |
726 | ||
727 | return 0; | |
86d7f238 AS |
728 | } |
729 | ||
7225342a MK |
730 | #define WA_REG(addr, val, mask) { \ |
731 | const int r = wa_add(dev_priv, (addr), (val), (mask)); \ | |
732 | if (r) \ | |
733 | return r; \ | |
734 | } | |
735 | ||
736 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
737 | WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff) | |
738 | ||
739 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
740 | WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff) | |
741 | ||
742 | #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask) | |
743 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask) | |
744 | ||
745 | #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff) | |
746 | ||
00e1e623 | 747 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 | 748 | { |
888b5995 AS |
749 | struct drm_device *dev = ring->dev; |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 | 751 | |
86d7f238 | 752 | /* WaDisablePartialInstShootdown:bdw */ |
101b376d | 753 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
7225342a MK |
754 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
755 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | | |
756 | STALL_DOP_GATING_DISABLE); | |
86d7f238 | 757 | |
101b376d | 758 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
759 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
760 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 761 | |
7225342a MK |
762 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
763 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 AS |
764 | |
765 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
766 | * workaround for for a possible hang in the unlikely event a TLB | |
767 | * invalidation occurs during a PSD flush. | |
768 | */ | |
f3f32360 | 769 | /* WaHdcDisableFetchWhenMasked:bdw */ |
da09654d | 770 | /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ |
7225342a MK |
771 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
772 | HDC_FORCE_NON_COHERENT | | |
f3f32360 | 773 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
7225342a | 774 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 AS |
775 | |
776 | /* Wa4x4STCOptimizationDisable:bdw */ | |
7225342a MK |
777 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
778 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
86d7f238 AS |
779 | |
780 | /* | |
781 | * BSpec recommends 8x4 when MSAA is used, | |
782 | * however in practice 16x4 seems fastest. | |
783 | * | |
784 | * Note that PS/WM thread counts depend on the WIZ hashing | |
785 | * disable bit, which we don't touch here, but it's good | |
786 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
787 | */ | |
7225342a MK |
788 | WA_SET_BIT_MASKED(GEN7_GT_MODE, |
789 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
888b5995 | 790 | |
86d7f238 AS |
791 | return 0; |
792 | } | |
793 | ||
00e1e623 VS |
794 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
795 | { | |
00e1e623 VS |
796 | struct drm_device *dev = ring->dev; |
797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
798 | ||
00e1e623 | 799 | /* WaDisablePartialInstShootdown:chv */ |
00e1e623 | 800 | /* WaDisableThreadStallDopClockGating:chv */ |
7225342a | 801 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
605f1433 AS |
802 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
803 | STALL_DOP_GATING_DISABLE); | |
00e1e623 | 804 | |
95289009 AS |
805 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
806 | * workaround for a possible hang in the unlikely event a TLB | |
807 | * invalidation occurs during a PSD flush. | |
808 | */ | |
809 | /* WaForceEnableNonCoherent:chv */ | |
810 | /* WaHdcDisableFetchWhenMasked:chv */ | |
811 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
812 | HDC_FORCE_NON_COHERENT | | |
813 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); | |
814 | ||
7225342a MK |
815 | return 0; |
816 | } | |
817 | ||
771b9a53 | 818 | int init_workarounds_ring(struct intel_engine_cs *ring) |
7225342a MK |
819 | { |
820 | struct drm_device *dev = ring->dev; | |
821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
822 | ||
823 | WARN_ON(ring->id != RCS); | |
824 | ||
825 | dev_priv->workarounds.count = 0; | |
826 | ||
827 | if (IS_BROADWELL(dev)) | |
828 | return bdw_init_workarounds(ring); | |
829 | ||
830 | if (IS_CHERRYVIEW(dev)) | |
831 | return chv_init_workarounds(ring); | |
00e1e623 VS |
832 | |
833 | return 0; | |
834 | } | |
835 | ||
a4872ba6 | 836 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 837 | { |
78501eac | 838 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 839 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 840 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
841 | if (ret) |
842 | return ret; | |
a69ffdbf | 843 | |
61a563a2 AG |
844 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
845 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 846 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
847 | |
848 | /* We need to disable the AsyncFlip performance optimisations in order | |
849 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
850 | * programmed to '1' on all products. | |
8693a824 | 851 | * |
b3f797ac | 852 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 | 853 | */ |
fbdcb068 | 854 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
1c8c38c5 CW |
855 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
856 | ||
f05bb0c7 | 857 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 858 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
859 | if (INTEL_INFO(dev)->gen == 6) |
860 | I915_WRITE(GFX_MODE, | |
aa83e30d | 861 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 862 | |
01fa0302 | 863 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
864 | if (IS_GEN7(dev)) |
865 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 866 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 867 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 868 | |
5e13a0c5 | 869 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
870 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
871 | * "If this bit is set, STCunit will have LRA as replacement | |
872 | * policy. [...] This bit must be reset. LRA replacement | |
873 | * policy is not supported." | |
874 | */ | |
875 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 876 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
877 | } |
878 | ||
6b26c86d DV |
879 | if (INTEL_INFO(dev)->gen >= 6) |
880 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 881 | |
040d2baa | 882 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 883 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 884 | |
7225342a | 885 | return init_workarounds_ring(ring); |
8187a2b7 ZN |
886 | } |
887 | ||
a4872ba6 | 888 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 889 | { |
b45305fc | 890 | struct drm_device *dev = ring->dev; |
3e78998a BW |
891 | struct drm_i915_private *dev_priv = dev->dev_private; |
892 | ||
893 | if (dev_priv->semaphore_obj) { | |
894 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
895 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
896 | dev_priv->semaphore_obj = NULL; | |
897 | } | |
b45305fc | 898 | |
9b1136d5 | 899 | intel_fini_pipe_control(ring); |
c6df541c CW |
900 | } |
901 | ||
3e78998a BW |
902 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
903 | unsigned int num_dwords) | |
904 | { | |
905 | #define MBOX_UPDATE_DWORDS 8 | |
906 | struct drm_device *dev = signaller->dev; | |
907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
908 | struct intel_engine_cs *waiter; | |
909 | int i, ret, num_rings; | |
910 | ||
911 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
912 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
913 | #undef MBOX_UPDATE_DWORDS | |
914 | ||
915 | ret = intel_ring_begin(signaller, num_dwords); | |
916 | if (ret) | |
917 | return ret; | |
918 | ||
919 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 920 | u32 seqno; |
3e78998a BW |
921 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
922 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
923 | continue; | |
924 | ||
6259cead JH |
925 | seqno = i915_gem_request_get_seqno( |
926 | signaller->outstanding_lazy_request); | |
3e78998a BW |
927 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
928 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
929 | PIPE_CONTROL_QW_WRITE | | |
930 | PIPE_CONTROL_FLUSH_ENABLE); | |
931 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
932 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 933 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
934 | intel_ring_emit(signaller, 0); |
935 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
936 | MI_SEMAPHORE_TARGET(waiter->id)); | |
937 | intel_ring_emit(signaller, 0); | |
938 | } | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
943 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
944 | unsigned int num_dwords) | |
945 | { | |
946 | #define MBOX_UPDATE_DWORDS 6 | |
947 | struct drm_device *dev = signaller->dev; | |
948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
949 | struct intel_engine_cs *waiter; | |
950 | int i, ret, num_rings; | |
951 | ||
952 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
953 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
954 | #undef MBOX_UPDATE_DWORDS | |
955 | ||
956 | ret = intel_ring_begin(signaller, num_dwords); | |
957 | if (ret) | |
958 | return ret; | |
959 | ||
960 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 961 | u32 seqno; |
3e78998a BW |
962 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
963 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
964 | continue; | |
965 | ||
6259cead JH |
966 | seqno = i915_gem_request_get_seqno( |
967 | signaller->outstanding_lazy_request); | |
3e78998a BW |
968 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
969 | MI_FLUSH_DW_OP_STOREDW); | |
970 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
971 | MI_FLUSH_DW_USE_GTT); | |
972 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 973 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
974 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
975 | MI_SEMAPHORE_TARGET(waiter->id)); | |
976 | intel_ring_emit(signaller, 0); | |
977 | } | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
a4872ba6 | 982 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 983 | unsigned int num_dwords) |
1ec14ad3 | 984 | { |
024a43e1 BW |
985 | struct drm_device *dev = signaller->dev; |
986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 987 | struct intel_engine_cs *useless; |
a1444b79 | 988 | int i, ret, num_rings; |
78325f2d | 989 | |
a1444b79 BW |
990 | #define MBOX_UPDATE_DWORDS 3 |
991 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
992 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
993 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
994 | |
995 | ret = intel_ring_begin(signaller, num_dwords); | |
996 | if (ret) | |
997 | return ret; | |
024a43e1 | 998 | |
78325f2d BW |
999 | for_each_ring(useless, dev_priv, i) { |
1000 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
1001 | if (mbox_reg != GEN6_NOSYNC) { | |
6259cead JH |
1002 | u32 seqno = i915_gem_request_get_seqno( |
1003 | signaller->outstanding_lazy_request); | |
78325f2d BW |
1004 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
1005 | intel_ring_emit(signaller, mbox_reg); | |
6259cead | 1006 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1007 | } |
1008 | } | |
024a43e1 | 1009 | |
a1444b79 BW |
1010 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1011 | if (num_rings % 2 == 0) | |
1012 | intel_ring_emit(signaller, MI_NOOP); | |
1013 | ||
024a43e1 | 1014 | return 0; |
1ec14ad3 CW |
1015 | } |
1016 | ||
c8c99b0f BW |
1017 | /** |
1018 | * gen6_add_request - Update the semaphore mailbox registers | |
1019 | * | |
1020 | * @ring - ring that is adding a request | |
1021 | * @seqno - return seqno stuck into the ring | |
1022 | * | |
1023 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1024 | * This acts like a signal in the canonical semaphore. | |
1025 | */ | |
1ec14ad3 | 1026 | static int |
a4872ba6 | 1027 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 1028 | { |
024a43e1 | 1029 | int ret; |
52ed2325 | 1030 | |
707d9cf9 BW |
1031 | if (ring->semaphore.signal) |
1032 | ret = ring->semaphore.signal(ring, 4); | |
1033 | else | |
1034 | ret = intel_ring_begin(ring, 4); | |
1035 | ||
1ec14ad3 CW |
1036 | if (ret) |
1037 | return ret; | |
1038 | ||
1ec14ad3 CW |
1039 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1040 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1041 | intel_ring_emit(ring, |
1042 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
1ec14ad3 | 1043 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1044 | __intel_ring_advance(ring); |
1ec14ad3 | 1045 | |
1ec14ad3 CW |
1046 | return 0; |
1047 | } | |
1048 | ||
f72b3435 MK |
1049 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1050 | u32 seqno) | |
1051 | { | |
1052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1053 | return dev_priv->last_seqno < seqno; | |
1054 | } | |
1055 | ||
c8c99b0f BW |
1056 | /** |
1057 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1058 | * | |
1059 | * @waiter - ring that is waiting | |
1060 | * @signaller - ring which has, or will signal | |
1061 | * @seqno - seqno which the waiter will block on | |
1062 | */ | |
5ee426ca BW |
1063 | |
1064 | static int | |
1065 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
1066 | struct intel_engine_cs *signaller, | |
1067 | u32 seqno) | |
1068 | { | |
1069 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
1070 | int ret; | |
1071 | ||
1072 | ret = intel_ring_begin(waiter, 4); | |
1073 | if (ret) | |
1074 | return ret; | |
1075 | ||
1076 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1077 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1078 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1079 | MI_SEMAPHORE_SAD_GTE_SDD); |
1080 | intel_ring_emit(waiter, seqno); | |
1081 | intel_ring_emit(waiter, | |
1082 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1083 | intel_ring_emit(waiter, | |
1084 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1085 | intel_ring_advance(waiter); | |
1086 | return 0; | |
1087 | } | |
1088 | ||
c8c99b0f | 1089 | static int |
a4872ba6 OM |
1090 | gen6_ring_sync(struct intel_engine_cs *waiter, |
1091 | struct intel_engine_cs *signaller, | |
686cb5f9 | 1092 | u32 seqno) |
1ec14ad3 | 1093 | { |
c8c99b0f BW |
1094 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1095 | MI_SEMAPHORE_COMPARE | | |
1096 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1097 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1098 | int ret; | |
1ec14ad3 | 1099 | |
1500f7ea BW |
1100 | /* Throughout all of the GEM code, seqno passed implies our current |
1101 | * seqno is >= the last seqno executed. However for hardware the | |
1102 | * comparison is strictly greater than. | |
1103 | */ | |
1104 | seqno -= 1; | |
1105 | ||
ebc348b2 | 1106 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1107 | |
c8c99b0f | 1108 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
1109 | if (ret) |
1110 | return ret; | |
1111 | ||
f72b3435 MK |
1112 | /* If seqno wrap happened, omit the wait with no-ops */ |
1113 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1114 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1115 | intel_ring_emit(waiter, seqno); |
1116 | intel_ring_emit(waiter, 0); | |
1117 | intel_ring_emit(waiter, MI_NOOP); | |
1118 | } else { | |
1119 | intel_ring_emit(waiter, MI_NOOP); | |
1120 | intel_ring_emit(waiter, MI_NOOP); | |
1121 | intel_ring_emit(waiter, MI_NOOP); | |
1122 | intel_ring_emit(waiter, MI_NOOP); | |
1123 | } | |
c8c99b0f | 1124 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1125 | |
1126 | return 0; | |
1127 | } | |
1128 | ||
c6df541c CW |
1129 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1130 | do { \ | |
fcbc34e4 KG |
1131 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1132 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1133 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1134 | intel_ring_emit(ring__, 0); \ | |
1135 | intel_ring_emit(ring__, 0); \ | |
1136 | } while (0) | |
1137 | ||
1138 | static int | |
a4872ba6 | 1139 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 1140 | { |
18393f63 | 1141 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1142 | int ret; |
1143 | ||
1144 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1145 | * incoherent with writes to memory, i.e. completely fubar, | |
1146 | * so we need to use PIPE_NOTIFY instead. | |
1147 | * | |
1148 | * However, we also need to workaround the qword write | |
1149 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1150 | * memory before requesting an interrupt. | |
1151 | */ | |
1152 | ret = intel_ring_begin(ring, 32); | |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
fcbc34e4 | 1156 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1157 | PIPE_CONTROL_WRITE_FLUSH | |
1158 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1159 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1160 | intel_ring_emit(ring, |
1161 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c CW |
1162 | intel_ring_emit(ring, 0); |
1163 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1164 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1165 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1166 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1167 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1168 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1169 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1170 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1171 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1172 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1173 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1174 | |
fcbc34e4 | 1175 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1176 | PIPE_CONTROL_WRITE_FLUSH | |
1177 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1178 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1179 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1180 | intel_ring_emit(ring, |
1181 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c | 1182 | intel_ring_emit(ring, 0); |
09246732 | 1183 | __intel_ring_advance(ring); |
c6df541c | 1184 | |
c6df541c CW |
1185 | return 0; |
1186 | } | |
1187 | ||
4cd53c0c | 1188 | static u32 |
a4872ba6 | 1189 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1190 | { |
4cd53c0c DV |
1191 | /* Workaround to force correct ordering between irq and seqno writes on |
1192 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1193 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1194 | if (!lazy_coherency) { |
1195 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1196 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1197 | } | |
1198 | ||
4cd53c0c DV |
1199 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1200 | } | |
1201 | ||
8187a2b7 | 1202 | static u32 |
a4872ba6 | 1203 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1204 | { |
1ec14ad3 CW |
1205 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1206 | } | |
1207 | ||
b70ec5bf | 1208 | static void |
a4872ba6 | 1209 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1210 | { |
1211 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1212 | } | |
1213 | ||
c6df541c | 1214 | static u32 |
a4872ba6 | 1215 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1216 | { |
0d1aacac | 1217 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1218 | } |
1219 | ||
b70ec5bf | 1220 | static void |
a4872ba6 | 1221 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1222 | { |
0d1aacac | 1223 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1224 | } |
1225 | ||
e48d8634 | 1226 | static bool |
a4872ba6 | 1227 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1228 | { |
1229 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1230 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1231 | unsigned long flags; |
e48d8634 | 1232 | |
7cd512f1 | 1233 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1234 | return false; |
1235 | ||
7338aefa | 1236 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1237 | if (ring->irq_refcount++ == 0) |
480c8033 | 1238 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1239 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1240 | |
1241 | return true; | |
1242 | } | |
1243 | ||
1244 | static void | |
a4872ba6 | 1245 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1246 | { |
1247 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1249 | unsigned long flags; |
e48d8634 | 1250 | |
7338aefa | 1251 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1252 | if (--ring->irq_refcount == 0) |
480c8033 | 1253 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1254 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1255 | } |
1256 | ||
b13c2b96 | 1257 | static bool |
a4872ba6 | 1258 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1259 | { |
78501eac | 1260 | struct drm_device *dev = ring->dev; |
4640c4ff | 1261 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1262 | unsigned long flags; |
62fdfeaf | 1263 | |
7cd512f1 | 1264 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1265 | return false; |
1266 | ||
7338aefa | 1267 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1268 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1269 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1270 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1271 | POSTING_READ(IMR); | |
1272 | } | |
7338aefa | 1273 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1274 | |
1275 | return true; | |
62fdfeaf EA |
1276 | } |
1277 | ||
8187a2b7 | 1278 | static void |
a4872ba6 | 1279 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1280 | { |
78501eac | 1281 | struct drm_device *dev = ring->dev; |
4640c4ff | 1282 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1283 | unsigned long flags; |
62fdfeaf | 1284 | |
7338aefa | 1285 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1286 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1287 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1288 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1289 | POSTING_READ(IMR); | |
1290 | } | |
7338aefa | 1291 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1292 | } |
1293 | ||
c2798b19 | 1294 | static bool |
a4872ba6 | 1295 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1296 | { |
1297 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1298 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1299 | unsigned long flags; |
c2798b19 | 1300 | |
7cd512f1 | 1301 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1302 | return false; |
1303 | ||
7338aefa | 1304 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1305 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1306 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1307 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1308 | POSTING_READ16(IMR); | |
1309 | } | |
7338aefa | 1310 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1311 | |
1312 | return true; | |
1313 | } | |
1314 | ||
1315 | static void | |
a4872ba6 | 1316 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1317 | { |
1318 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1319 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1320 | unsigned long flags; |
c2798b19 | 1321 | |
7338aefa | 1322 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1323 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1324 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1325 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1326 | POSTING_READ16(IMR); | |
1327 | } | |
7338aefa | 1328 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1329 | } |
1330 | ||
a4872ba6 | 1331 | void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
8187a2b7 | 1332 | { |
4593010b | 1333 | struct drm_device *dev = ring->dev; |
4640c4ff | 1334 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
4593010b EA |
1335 | u32 mmio = 0; |
1336 | ||
1337 | /* The ring status page addresses are no longer next to the rest of | |
1338 | * the ring registers as of gen7. | |
1339 | */ | |
1340 | if (IS_GEN7(dev)) { | |
1341 | switch (ring->id) { | |
96154f2f | 1342 | case RCS: |
4593010b EA |
1343 | mmio = RENDER_HWS_PGA_GEN7; |
1344 | break; | |
96154f2f | 1345 | case BCS: |
4593010b EA |
1346 | mmio = BLT_HWS_PGA_GEN7; |
1347 | break; | |
77fe2ff3 ZY |
1348 | /* |
1349 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
1350 | * gcc switch check warning | |
1351 | */ | |
1352 | case VCS2: | |
96154f2f | 1353 | case VCS: |
4593010b EA |
1354 | mmio = BSD_HWS_PGA_GEN7; |
1355 | break; | |
4a3dd19d | 1356 | case VECS: |
9a8a2213 BW |
1357 | mmio = VEBOX_HWS_PGA_GEN7; |
1358 | break; | |
4593010b EA |
1359 | } |
1360 | } else if (IS_GEN6(ring->dev)) { | |
1361 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
1362 | } else { | |
eb0d4b75 | 1363 | /* XXX: gen8 returns to sanity */ |
4593010b EA |
1364 | mmio = RING_HWS_PGA(ring->mmio_base); |
1365 | } | |
1366 | ||
78501eac CW |
1367 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
1368 | POSTING_READ(mmio); | |
884020bf | 1369 | |
dc616b89 DL |
1370 | /* |
1371 | * Flush the TLB for this page | |
1372 | * | |
1373 | * FIXME: These two bits have disappeared on gen8, so a question | |
1374 | * arises: do we still need this and if so how should we go about | |
1375 | * invalidating the TLB? | |
1376 | */ | |
1377 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
884020bf | 1378 | u32 reg = RING_INSTPM(ring->mmio_base); |
02f6a1e7 NKK |
1379 | |
1380 | /* ring should be idle before issuing a sync flush*/ | |
1381 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
1382 | ||
884020bf CW |
1383 | I915_WRITE(reg, |
1384 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
1385 | INSTPM_SYNC_FLUSH)); | |
1386 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
1387 | 1000)) | |
1388 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
1389 | ring->name); | |
1390 | } | |
8187a2b7 ZN |
1391 | } |
1392 | ||
b72f3acb | 1393 | static int |
a4872ba6 | 1394 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1395 | u32 invalidate_domains, |
1396 | u32 flush_domains) | |
d1b851fc | 1397 | { |
b72f3acb CW |
1398 | int ret; |
1399 | ||
b72f3acb CW |
1400 | ret = intel_ring_begin(ring, 2); |
1401 | if (ret) | |
1402 | return ret; | |
1403 | ||
1404 | intel_ring_emit(ring, MI_FLUSH); | |
1405 | intel_ring_emit(ring, MI_NOOP); | |
1406 | intel_ring_advance(ring); | |
1407 | return 0; | |
d1b851fc ZN |
1408 | } |
1409 | ||
3cce469c | 1410 | static int |
a4872ba6 | 1411 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1412 | { |
3cce469c CW |
1413 | int ret; |
1414 | ||
1415 | ret = intel_ring_begin(ring, 4); | |
1416 | if (ret) | |
1417 | return ret; | |
6f392d54 | 1418 | |
3cce469c CW |
1419 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1420 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1421 | intel_ring_emit(ring, |
1422 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
3cce469c | 1423 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1424 | __intel_ring_advance(ring); |
d1b851fc | 1425 | |
3cce469c | 1426 | return 0; |
d1b851fc ZN |
1427 | } |
1428 | ||
0f46832f | 1429 | static bool |
a4872ba6 | 1430 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1431 | { |
1432 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1433 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1434 | unsigned long flags; |
0f46832f | 1435 | |
7cd512f1 DV |
1436 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1437 | return false; | |
0f46832f | 1438 | |
7338aefa | 1439 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1440 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1441 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1442 | I915_WRITE_IMR(ring, |
1443 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1444 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1445 | else |
1446 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1447 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1448 | } |
7338aefa | 1449 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1450 | |
1451 | return true; | |
1452 | } | |
1453 | ||
1454 | static void | |
a4872ba6 | 1455 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1456 | { |
1457 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1458 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1459 | unsigned long flags; |
0f46832f | 1460 | |
7338aefa | 1461 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1462 | if (--ring->irq_refcount == 0) { |
040d2baa | 1463 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1464 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1465 | else |
1466 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1467 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1468 | } |
7338aefa | 1469 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1470 | } |
1471 | ||
a19d2933 | 1472 | static bool |
a4872ba6 | 1473 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1474 | { |
1475 | struct drm_device *dev = ring->dev; | |
1476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1477 | unsigned long flags; | |
1478 | ||
7cd512f1 | 1479 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1480 | return false; |
1481 | ||
59cdb63d | 1482 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1483 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1484 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1485 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1486 | } |
59cdb63d | 1487 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1488 | |
1489 | return true; | |
1490 | } | |
1491 | ||
1492 | static void | |
a4872ba6 | 1493 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1494 | { |
1495 | struct drm_device *dev = ring->dev; | |
1496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1497 | unsigned long flags; | |
1498 | ||
59cdb63d | 1499 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1500 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1501 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1502 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1503 | } |
59cdb63d | 1504 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1505 | } |
1506 | ||
abd58f01 | 1507 | static bool |
a4872ba6 | 1508 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1509 | { |
1510 | struct drm_device *dev = ring->dev; | |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | unsigned long flags; | |
1513 | ||
7cd512f1 | 1514 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1515 | return false; |
1516 | ||
1517 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1518 | if (ring->irq_refcount++ == 0) { | |
1519 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1520 | I915_WRITE_IMR(ring, | |
1521 | ~(ring->irq_enable_mask | | |
1522 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1523 | } else { | |
1524 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1525 | } | |
1526 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1527 | } | |
1528 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1529 | ||
1530 | return true; | |
1531 | } | |
1532 | ||
1533 | static void | |
a4872ba6 | 1534 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1535 | { |
1536 | struct drm_device *dev = ring->dev; | |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1538 | unsigned long flags; | |
1539 | ||
1540 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1541 | if (--ring->irq_refcount == 0) { | |
1542 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1543 | I915_WRITE_IMR(ring, | |
1544 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1545 | } else { | |
1546 | I915_WRITE_IMR(ring, ~0); | |
1547 | } | |
1548 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1549 | } | |
1550 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1551 | } | |
1552 | ||
d1b851fc | 1553 | static int |
a4872ba6 | 1554 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1555 | u64 offset, u32 length, |
d7d4eedd | 1556 | unsigned flags) |
d1b851fc | 1557 | { |
e1f99ce6 | 1558 | int ret; |
78501eac | 1559 | |
e1f99ce6 CW |
1560 | ret = intel_ring_begin(ring, 2); |
1561 | if (ret) | |
1562 | return ret; | |
1563 | ||
78501eac | 1564 | intel_ring_emit(ring, |
65f56876 CW |
1565 | MI_BATCH_BUFFER_START | |
1566 | MI_BATCH_GTT | | |
d7d4eedd | 1567 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1568 | intel_ring_emit(ring, offset); |
78501eac CW |
1569 | intel_ring_advance(ring); |
1570 | ||
d1b851fc ZN |
1571 | return 0; |
1572 | } | |
1573 | ||
b45305fc DV |
1574 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1575 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1576 | #define I830_TLB_ENTRIES (2) |
1577 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1578 | static int |
a4872ba6 | 1579 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1580 | u64 offset, u32 len, |
d7d4eedd | 1581 | unsigned flags) |
62fdfeaf | 1582 | { |
c4d69da1 | 1583 | u32 cs_offset = ring->scratch.gtt_offset; |
c4e7a414 | 1584 | int ret; |
62fdfeaf | 1585 | |
c4d69da1 CW |
1586 | ret = intel_ring_begin(ring, 6); |
1587 | if (ret) | |
1588 | return ret; | |
62fdfeaf | 1589 | |
c4d69da1 CW |
1590 | /* Evict the invalid PTE TLBs */ |
1591 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); | |
1592 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1593 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1594 | intel_ring_emit(ring, cs_offset); | |
1595 | intel_ring_emit(ring, 0xdeadbeef); | |
1596 | intel_ring_emit(ring, MI_NOOP); | |
1597 | intel_ring_advance(ring); | |
b45305fc | 1598 | |
c4d69da1 | 1599 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1600 | if (len > I830_BATCH_LIMIT) |
1601 | return -ENOSPC; | |
1602 | ||
c4d69da1 | 1603 | ret = intel_ring_begin(ring, 6 + 2); |
b45305fc DV |
1604 | if (ret) |
1605 | return ret; | |
c4d69da1 CW |
1606 | |
1607 | /* Blit the batch (which has now all relocs applied) to the | |
1608 | * stable batch scratch bo area (so that the CS never | |
1609 | * stumbles over its tlb invalidation bug) ... | |
1610 | */ | |
1611 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); | |
1612 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
611a7a4f | 1613 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
b45305fc | 1614 | intel_ring_emit(ring, cs_offset); |
b45305fc DV |
1615 | intel_ring_emit(ring, 4096); |
1616 | intel_ring_emit(ring, offset); | |
c4d69da1 | 1617 | |
b45305fc | 1618 | intel_ring_emit(ring, MI_FLUSH); |
c4d69da1 CW |
1619 | intel_ring_emit(ring, MI_NOOP); |
1620 | intel_ring_advance(ring); | |
b45305fc DV |
1621 | |
1622 | /* ... and execute it. */ | |
c4d69da1 | 1623 | offset = cs_offset; |
b45305fc | 1624 | } |
e1f99ce6 | 1625 | |
c4d69da1 CW |
1626 | ret = intel_ring_begin(ring, 4); |
1627 | if (ret) | |
1628 | return ret; | |
1629 | ||
1630 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1631 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1632 | intel_ring_emit(ring, offset + len - 8); | |
1633 | intel_ring_emit(ring, MI_NOOP); | |
1634 | intel_ring_advance(ring); | |
1635 | ||
fb3256da DV |
1636 | return 0; |
1637 | } | |
1638 | ||
1639 | static int | |
a4872ba6 | 1640 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1641 | u64 offset, u32 len, |
d7d4eedd | 1642 | unsigned flags) |
fb3256da DV |
1643 | { |
1644 | int ret; | |
1645 | ||
1646 | ret = intel_ring_begin(ring, 2); | |
1647 | if (ret) | |
1648 | return ret; | |
1649 | ||
65f56876 | 1650 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1651 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1652 | intel_ring_advance(ring); |
62fdfeaf | 1653 | |
62fdfeaf EA |
1654 | return 0; |
1655 | } | |
1656 | ||
a4872ba6 | 1657 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1658 | { |
05394f39 | 1659 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1660 | |
8187a2b7 ZN |
1661 | obj = ring->status_page.obj; |
1662 | if (obj == NULL) | |
62fdfeaf | 1663 | return; |
62fdfeaf | 1664 | |
9da3da66 | 1665 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1666 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1667 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1668 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1669 | } |
1670 | ||
a4872ba6 | 1671 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1672 | { |
05394f39 | 1673 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1674 | |
e3efda49 | 1675 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1676 | unsigned flags; |
e3efda49 | 1677 | int ret; |
e4ffd173 | 1678 | |
e3efda49 CW |
1679 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1680 | if (obj == NULL) { | |
1681 | DRM_ERROR("Failed to allocate status page\n"); | |
1682 | return -ENOMEM; | |
1683 | } | |
62fdfeaf | 1684 | |
e3efda49 CW |
1685 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1686 | if (ret) | |
1687 | goto err_unref; | |
1688 | ||
1f767e02 CW |
1689 | flags = 0; |
1690 | if (!HAS_LLC(ring->dev)) | |
1691 | /* On g33, we cannot place HWS above 256MiB, so | |
1692 | * restrict its pinning to the low mappable arena. | |
1693 | * Though this restriction is not documented for | |
1694 | * gen4, gen5, or byt, they also behave similarly | |
1695 | * and hang if the HWS is placed at the top of the | |
1696 | * GTT. To generalise, it appears that all !llc | |
1697 | * platforms have issues with us placing the HWS | |
1698 | * above the mappable region (even though we never | |
1699 | * actualy map it). | |
1700 | */ | |
1701 | flags |= PIN_MAPPABLE; | |
1702 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1703 | if (ret) { |
1704 | err_unref: | |
1705 | drm_gem_object_unreference(&obj->base); | |
1706 | return ret; | |
1707 | } | |
1708 | ||
1709 | ring->status_page.obj = obj; | |
1710 | } | |
62fdfeaf | 1711 | |
f343c5f6 | 1712 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1713 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1714 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1715 | |
8187a2b7 ZN |
1716 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1717 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1718 | |
1719 | return 0; | |
62fdfeaf EA |
1720 | } |
1721 | ||
a4872ba6 | 1722 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1723 | { |
1724 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1725 | |
1726 | if (!dev_priv->status_page_dmah) { | |
1727 | dev_priv->status_page_dmah = | |
1728 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1729 | if (!dev_priv->status_page_dmah) | |
1730 | return -ENOMEM; | |
1731 | } | |
1732 | ||
6b8294a4 CW |
1733 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1734 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
7ba717cf | 1739 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 1740 | { |
2919d291 | 1741 | iounmap(ringbuf->virtual_start); |
7ba717cf | 1742 | ringbuf->virtual_start = NULL; |
2919d291 | 1743 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
1744 | } |
1745 | ||
1746 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
1747 | struct intel_ringbuffer *ringbuf) | |
1748 | { | |
1749 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1750 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
1751 | int ret; | |
1752 | ||
1753 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
1754 | if (ret) | |
1755 | return ret; | |
1756 | ||
1757 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1758 | if (ret) { | |
1759 | i915_gem_object_ggtt_unpin(obj); | |
1760 | return ret; | |
1761 | } | |
1762 | ||
1763 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + | |
1764 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
1765 | if (ringbuf->virtual_start == NULL) { | |
1766 | i915_gem_object_ggtt_unpin(obj); | |
1767 | return -EINVAL; | |
1768 | } | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) | |
1774 | { | |
2919d291 OM |
1775 | drm_gem_object_unreference(&ringbuf->obj->base); |
1776 | ringbuf->obj = NULL; | |
1777 | } | |
1778 | ||
84c2377f OM |
1779 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1780 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1781 | { |
05394f39 | 1782 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1783 | |
ebc052e0 CW |
1784 | obj = NULL; |
1785 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1786 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1787 | if (obj == NULL) |
93b0a4e0 | 1788 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1789 | if (obj == NULL) |
1790 | return -ENOMEM; | |
8187a2b7 | 1791 | |
24f3a8cf AG |
1792 | /* mark ring buffers as read-only from GPU side by default */ |
1793 | obj->gt_ro = 1; | |
1794 | ||
93b0a4e0 | 1795 | ringbuf->obj = obj; |
e3efda49 | 1796 | |
7ba717cf | 1797 | return 0; |
e3efda49 CW |
1798 | } |
1799 | ||
1800 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1801 | struct intel_engine_cs *ring) |
e3efda49 | 1802 | { |
bfc882b4 | 1803 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
1804 | int ret; |
1805 | ||
bfc882b4 DV |
1806 | WARN_ON(ring->buffer); |
1807 | ||
1808 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1809 | if (!ringbuf) | |
1810 | return -ENOMEM; | |
1811 | ring->buffer = ringbuf; | |
8ee14975 | 1812 | |
e3efda49 CW |
1813 | ring->dev = dev; |
1814 | INIT_LIST_HEAD(&ring->active_list); | |
1815 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 1816 | INIT_LIST_HEAD(&ring->execlist_queue); |
93b0a4e0 | 1817 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1818 | ringbuf->ring = ring; |
ebc348b2 | 1819 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1820 | |
1821 | init_waitqueue_head(&ring->irq_queue); | |
1822 | ||
1823 | if (I915_NEED_GFX_HWS(dev)) { | |
1824 | ret = init_status_page(ring); | |
1825 | if (ret) | |
8ee14975 | 1826 | goto error; |
e3efda49 CW |
1827 | } else { |
1828 | BUG_ON(ring->id != RCS); | |
1829 | ret = init_phys_status_page(ring); | |
1830 | if (ret) | |
8ee14975 | 1831 | goto error; |
e3efda49 CW |
1832 | } |
1833 | ||
bfc882b4 | 1834 | WARN_ON(ringbuf->obj); |
7ba717cf | 1835 | |
bfc882b4 DV |
1836 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
1837 | if (ret) { | |
1838 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", | |
1839 | ring->name, ret); | |
1840 | goto error; | |
1841 | } | |
1842 | ||
1843 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
1844 | if (ret) { | |
1845 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
1846 | ring->name, ret); | |
1847 | intel_destroy_ringbuffer_obj(ringbuf); | |
1848 | goto error; | |
e3efda49 | 1849 | } |
62fdfeaf | 1850 | |
55249baa CW |
1851 | /* Workaround an erratum on the i830 which causes a hang if |
1852 | * the TAIL pointer points to within the last 2 cachelines | |
1853 | * of the buffer. | |
1854 | */ | |
93b0a4e0 | 1855 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1856 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1857 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1858 | |
44e895a8 BV |
1859 | ret = i915_cmd_parser_init_ring(ring); |
1860 | if (ret) | |
8ee14975 OM |
1861 | goto error; |
1862 | ||
8ee14975 | 1863 | return 0; |
351e3db2 | 1864 | |
8ee14975 OM |
1865 | error: |
1866 | kfree(ringbuf); | |
1867 | ring->buffer = NULL; | |
1868 | return ret; | |
62fdfeaf EA |
1869 | } |
1870 | ||
a4872ba6 | 1871 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1872 | { |
6402c330 JH |
1873 | struct drm_i915_private *dev_priv; |
1874 | struct intel_ringbuffer *ringbuf; | |
33626e6a | 1875 | |
93b0a4e0 | 1876 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1877 | return; |
1878 | ||
6402c330 JH |
1879 | dev_priv = to_i915(ring->dev); |
1880 | ringbuf = ring->buffer; | |
1881 | ||
e3efda49 | 1882 | intel_stop_ring_buffer(ring); |
de8f0a50 | 1883 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 1884 | |
7ba717cf | 1885 | intel_unpin_ringbuffer_obj(ringbuf); |
2919d291 | 1886 | intel_destroy_ringbuffer_obj(ringbuf); |
6259cead | 1887 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
78501eac | 1888 | |
8d19215b ZN |
1889 | if (ring->cleanup) |
1890 | ring->cleanup(ring); | |
1891 | ||
78501eac | 1892 | cleanup_status_page(ring); |
44e895a8 BV |
1893 | |
1894 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 1895 | |
93b0a4e0 | 1896 | kfree(ringbuf); |
8ee14975 | 1897 | ring->buffer = NULL; |
62fdfeaf EA |
1898 | } |
1899 | ||
a4872ba6 | 1900 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 1901 | { |
93b0a4e0 | 1902 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 1903 | struct drm_i915_gem_request *request; |
a71d8d94 CW |
1904 | int ret; |
1905 | ||
ebd0fd4b DG |
1906 | if (intel_ring_space(ringbuf) >= n) |
1907 | return 0; | |
a71d8d94 CW |
1908 | |
1909 | list_for_each_entry(request, &ring->request_list, list) { | |
82e104cc OM |
1910 | if (__intel_ring_space(request->tail, ringbuf->tail, |
1911 | ringbuf->size) >= n) { | |
a71d8d94 CW |
1912 | break; |
1913 | } | |
a71d8d94 CW |
1914 | } |
1915 | ||
a4b3a571 | 1916 | if (&request->list == &ring->request_list) |
a71d8d94 CW |
1917 | return -ENOSPC; |
1918 | ||
a4b3a571 | 1919 | ret = i915_wait_request(request); |
a71d8d94 CW |
1920 | if (ret) |
1921 | return ret; | |
1922 | ||
1cf0ba14 | 1923 | i915_gem_retire_requests_ring(ring); |
a71d8d94 CW |
1924 | |
1925 | return 0; | |
1926 | } | |
1927 | ||
a4872ba6 | 1928 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 1929 | { |
78501eac | 1930 | struct drm_device *dev = ring->dev; |
cae5852d | 1931 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 1932 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 1933 | unsigned long end; |
a71d8d94 | 1934 | int ret; |
c7dca47b | 1935 | |
a71d8d94 CW |
1936 | ret = intel_ring_wait_request(ring, n); |
1937 | if (ret != -ENOSPC) | |
1938 | return ret; | |
1939 | ||
09246732 CW |
1940 | /* force the tail write in case we have been skipping them */ |
1941 | __intel_ring_advance(ring); | |
1942 | ||
63ed2cb2 DV |
1943 | /* With GEM the hangcheck timer should kick us out of the loop, |
1944 | * leaving it early runs the risk of corrupting GEM state (due | |
1945 | * to running on almost untested codepaths). But on resume | |
1946 | * timers don't work yet, so prevent a complete hang in that | |
1947 | * case by choosing an insanely large timeout. */ | |
1948 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1949 | |
ebd0fd4b | 1950 | ret = 0; |
dcfe0506 | 1951 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 1952 | do { |
ebd0fd4b DG |
1953 | if (intel_ring_space(ringbuf) >= n) |
1954 | break; | |
93b0a4e0 | 1955 | ringbuf->head = I915_READ_HEAD(ring); |
ebd0fd4b | 1956 | if (intel_ring_space(ringbuf) >= n) |
dcfe0506 | 1957 | break; |
62fdfeaf | 1958 | |
e60a0b10 | 1959 | msleep(1); |
d6b2c790 | 1960 | |
dcfe0506 CW |
1961 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
1962 | ret = -ERESTARTSYS; | |
1963 | break; | |
1964 | } | |
1965 | ||
33196ded DV |
1966 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1967 | dev_priv->mm.interruptible); | |
d6b2c790 | 1968 | if (ret) |
dcfe0506 CW |
1969 | break; |
1970 | ||
1971 | if (time_after(jiffies, end)) { | |
1972 | ret = -EBUSY; | |
1973 | break; | |
1974 | } | |
1975 | } while (1); | |
db53a302 | 1976 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 1977 | return ret; |
8187a2b7 | 1978 | } |
62fdfeaf | 1979 | |
a4872ba6 | 1980 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
1981 | { |
1982 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
1983 | struct intel_ringbuffer *ringbuf = ring->buffer; |
1984 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 1985 | |
93b0a4e0 | 1986 | if (ringbuf->space < rem) { |
3e960501 CW |
1987 | int ret = ring_wait_for_space(ring, rem); |
1988 | if (ret) | |
1989 | return ret; | |
1990 | } | |
1991 | ||
93b0a4e0 | 1992 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
1993 | rem /= 4; |
1994 | while (rem--) | |
1995 | iowrite32(MI_NOOP, virt++); | |
1996 | ||
93b0a4e0 | 1997 | ringbuf->tail = 0; |
ebd0fd4b | 1998 | intel_ring_update_space(ringbuf); |
3e960501 CW |
1999 | |
2000 | return 0; | |
2001 | } | |
2002 | ||
a4872ba6 | 2003 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 | 2004 | { |
a4b3a571 | 2005 | struct drm_i915_gem_request *req; |
3e960501 CW |
2006 | int ret; |
2007 | ||
2008 | /* We need to add any requests required to flush the objects and ring */ | |
6259cead | 2009 | if (ring->outstanding_lazy_request) { |
9400ae5c | 2010 | ret = i915_add_request(ring); |
3e960501 CW |
2011 | if (ret) |
2012 | return ret; | |
2013 | } | |
2014 | ||
2015 | /* Wait upon the last request to be completed */ | |
2016 | if (list_empty(&ring->request_list)) | |
2017 | return 0; | |
2018 | ||
a4b3a571 | 2019 | req = list_entry(ring->request_list.prev, |
3e960501 | 2020 | struct drm_i915_gem_request, |
a4b3a571 | 2021 | list); |
3e960501 | 2022 | |
a4b3a571 | 2023 | return i915_wait_request(req); |
3e960501 CW |
2024 | } |
2025 | ||
9d773091 | 2026 | static int |
6259cead | 2027 | intel_ring_alloc_request(struct intel_engine_cs *ring) |
9d773091 | 2028 | { |
9eba5d4a JH |
2029 | int ret; |
2030 | struct drm_i915_gem_request *request; | |
67e2937b | 2031 | struct drm_i915_private *dev_private = ring->dev->dev_private; |
9eba5d4a | 2032 | |
6259cead | 2033 | if (ring->outstanding_lazy_request) |
9d773091 | 2034 | return 0; |
3c0e234c | 2035 | |
aaeb1ba0 | 2036 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
9eba5d4a JH |
2037 | if (request == NULL) |
2038 | return -ENOMEM; | |
3c0e234c | 2039 | |
abfe262a | 2040 | kref_init(&request->ref); |
ff79e857 | 2041 | request->ring = ring; |
67e2937b | 2042 | request->uniq = dev_private->request_uniq++; |
abfe262a | 2043 | |
6259cead | 2044 | ret = i915_gem_get_seqno(ring->dev, &request->seqno); |
9eba5d4a JH |
2045 | if (ret) { |
2046 | kfree(request); | |
2047 | return ret; | |
3c0e234c CW |
2048 | } |
2049 | ||
6259cead | 2050 | ring->outstanding_lazy_request = request; |
9eba5d4a | 2051 | return 0; |
9d773091 CW |
2052 | } |
2053 | ||
a4872ba6 | 2054 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 2055 | int bytes) |
cbcc80df | 2056 | { |
93b0a4e0 | 2057 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
2058 | int ret; |
2059 | ||
93b0a4e0 | 2060 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
2061 | ret = intel_wrap_ring_buffer(ring); |
2062 | if (unlikely(ret)) | |
2063 | return ret; | |
2064 | } | |
2065 | ||
93b0a4e0 | 2066 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
2067 | ret = ring_wait_for_space(ring, bytes); |
2068 | if (unlikely(ret)) | |
2069 | return ret; | |
2070 | } | |
2071 | ||
cbcc80df MK |
2072 | return 0; |
2073 | } | |
2074 | ||
a4872ba6 | 2075 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 2076 | int num_dwords) |
8187a2b7 | 2077 | { |
4640c4ff | 2078 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 2079 | int ret; |
78501eac | 2080 | |
33196ded DV |
2081 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2082 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2083 | if (ret) |
2084 | return ret; | |
21dd3734 | 2085 | |
304d695c CW |
2086 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2087 | if (ret) | |
2088 | return ret; | |
2089 | ||
9d773091 | 2090 | /* Preallocate the olr before touching the ring */ |
6259cead | 2091 | ret = intel_ring_alloc_request(ring); |
9d773091 CW |
2092 | if (ret) |
2093 | return ret; | |
2094 | ||
ee1b1e5e | 2095 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2096 | return 0; |
8187a2b7 | 2097 | } |
78501eac | 2098 | |
753b1ad4 | 2099 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 2100 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 2101 | { |
ee1b1e5e | 2102 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2103 | int ret; |
2104 | ||
2105 | if (num_dwords == 0) | |
2106 | return 0; | |
2107 | ||
18393f63 | 2108 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
2109 | ret = intel_ring_begin(ring, num_dwords); |
2110 | if (ret) | |
2111 | return ret; | |
2112 | ||
2113 | while (num_dwords--) | |
2114 | intel_ring_emit(ring, MI_NOOP); | |
2115 | ||
2116 | intel_ring_advance(ring); | |
2117 | ||
2118 | return 0; | |
2119 | } | |
2120 | ||
a4872ba6 | 2121 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2122 | { |
3b2cc8ab OM |
2123 | struct drm_device *dev = ring->dev; |
2124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2125 | |
6259cead | 2126 | BUG_ON(ring->outstanding_lazy_request); |
498d2ac1 | 2127 | |
3b2cc8ab | 2128 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2129 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2130 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2131 | if (HAS_VEBOX(dev)) |
5020150b | 2132 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2133 | } |
d97ed339 | 2134 | |
f7e98ad4 | 2135 | ring->set_seqno(ring, seqno); |
92cab734 | 2136 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2137 | } |
62fdfeaf | 2138 | |
a4872ba6 | 2139 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2140 | u32 value) |
881f47b6 | 2141 | { |
4640c4ff | 2142 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2143 | |
2144 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2145 | |
2146 | /* Disable notification that the ring is IDLE. The GT | |
2147 | * will then assume that it is busy and bring it out of rc6. | |
2148 | */ | |
0206e353 | 2149 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2150 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2151 | ||
2152 | /* Clear the context id. Here be magic! */ | |
2153 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2154 | |
12f55818 | 2155 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2156 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2157 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2158 | 50)) | |
2159 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2160 | |
12f55818 | 2161 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2162 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2163 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2164 | ||
2165 | /* Let the ring send IDLE messages to the GT again, | |
2166 | * and so let it sleep to conserve power when idle. | |
2167 | */ | |
0206e353 | 2168 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2169 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2170 | } |
2171 | ||
a4872ba6 | 2172 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2173 | u32 invalidate, u32 flush) |
881f47b6 | 2174 | { |
71a77e07 | 2175 | uint32_t cmd; |
b72f3acb CW |
2176 | int ret; |
2177 | ||
b72f3acb CW |
2178 | ret = intel_ring_begin(ring, 4); |
2179 | if (ret) | |
2180 | return ret; | |
2181 | ||
71a77e07 | 2182 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2183 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2184 | cmd += 1; | |
9a289771 JB |
2185 | /* |
2186 | * Bspec vol 1c.5 - video engine command streamer: | |
2187 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2188 | * operation is complete. This bit is only valid when the | |
2189 | * Post-Sync Operation field is a value of 1h or 3h." | |
2190 | */ | |
71a77e07 | 2191 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
2192 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
2193 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 2194 | intel_ring_emit(ring, cmd); |
9a289771 | 2195 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2196 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2197 | intel_ring_emit(ring, 0); /* upper addr */ | |
2198 | intel_ring_emit(ring, 0); /* value */ | |
2199 | } else { | |
2200 | intel_ring_emit(ring, 0); | |
2201 | intel_ring_emit(ring, MI_NOOP); | |
2202 | } | |
b72f3acb CW |
2203 | intel_ring_advance(ring); |
2204 | return 0; | |
881f47b6 XH |
2205 | } |
2206 | ||
1c7a0623 | 2207 | static int |
a4872ba6 | 2208 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2209 | u64 offset, u32 len, |
1c7a0623 BW |
2210 | unsigned flags) |
2211 | { | |
896ab1a5 | 2212 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2213 | int ret; |
2214 | ||
2215 | ret = intel_ring_begin(ring, 4); | |
2216 | if (ret) | |
2217 | return ret; | |
2218 | ||
2219 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2220 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2221 | intel_ring_emit(ring, lower_32_bits(offset)); |
2222 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2223 | intel_ring_emit(ring, MI_NOOP); |
2224 | intel_ring_advance(ring); | |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
d7d4eedd | 2229 | static int |
a4872ba6 | 2230 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2231 | u64 offset, u32 len, |
d7d4eedd CW |
2232 | unsigned flags) |
2233 | { | |
2234 | int ret; | |
2235 | ||
2236 | ret = intel_ring_begin(ring, 2); | |
2237 | if (ret) | |
2238 | return ret; | |
2239 | ||
2240 | intel_ring_emit(ring, | |
77072258 CW |
2241 | MI_BATCH_BUFFER_START | |
2242 | (flags & I915_DISPATCH_SECURE ? | |
2243 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); | |
d7d4eedd CW |
2244 | /* bit0-7 is the length on GEN6+ */ |
2245 | intel_ring_emit(ring, offset); | |
2246 | intel_ring_advance(ring); | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
881f47b6 | 2251 | static int |
a4872ba6 | 2252 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2253 | u64 offset, u32 len, |
d7d4eedd | 2254 | unsigned flags) |
881f47b6 | 2255 | { |
0206e353 | 2256 | int ret; |
ab6f8e32 | 2257 | |
0206e353 AJ |
2258 | ret = intel_ring_begin(ring, 2); |
2259 | if (ret) | |
2260 | return ret; | |
e1f99ce6 | 2261 | |
d7d4eedd CW |
2262 | intel_ring_emit(ring, |
2263 | MI_BATCH_BUFFER_START | | |
2264 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2265 | /* bit0-7 is the length on GEN6+ */ |
2266 | intel_ring_emit(ring, offset); | |
2267 | intel_ring_advance(ring); | |
ab6f8e32 | 2268 | |
0206e353 | 2269 | return 0; |
881f47b6 XH |
2270 | } |
2271 | ||
549f7365 CW |
2272 | /* Blitter support (SandyBridge+) */ |
2273 | ||
a4872ba6 | 2274 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2275 | u32 invalidate, u32 flush) |
8d19215b | 2276 | { |
fd3da6c9 | 2277 | struct drm_device *dev = ring->dev; |
1d73c2a8 | 2278 | struct drm_i915_private *dev_priv = dev->dev_private; |
71a77e07 | 2279 | uint32_t cmd; |
b72f3acb CW |
2280 | int ret; |
2281 | ||
6a233c78 | 2282 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2283 | if (ret) |
2284 | return ret; | |
2285 | ||
71a77e07 | 2286 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2287 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2288 | cmd += 1; | |
9a289771 JB |
2289 | /* |
2290 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2291 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2292 | * operation is complete. This bit is only valid when the | |
2293 | * Post-Sync Operation field is a value of 1h or 3h." | |
2294 | */ | |
71a77e07 | 2295 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2296 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2297 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2298 | intel_ring_emit(ring, cmd); |
9a289771 | 2299 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2300 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2301 | intel_ring_emit(ring, 0); /* upper addr */ | |
2302 | intel_ring_emit(ring, 0); /* value */ | |
2303 | } else { | |
2304 | intel_ring_emit(ring, 0); | |
2305 | intel_ring_emit(ring, MI_NOOP); | |
2306 | } | |
b72f3acb | 2307 | intel_ring_advance(ring); |
fd3da6c9 | 2308 | |
1d73c2a8 RV |
2309 | if (!invalidate && flush) { |
2310 | if (IS_GEN7(dev)) | |
2311 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
2312 | else if (IS_BROADWELL(dev)) | |
2313 | dev_priv->fbc.need_sw_cache_clean = true; | |
2314 | } | |
fd3da6c9 | 2315 | |
b72f3acb | 2316 | return 0; |
8d19215b ZN |
2317 | } |
2318 | ||
5c1143bb XH |
2319 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2320 | { | |
4640c4ff | 2321 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2322 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2323 | struct drm_i915_gem_object *obj; |
2324 | int ret; | |
5c1143bb | 2325 | |
59465b5f DV |
2326 | ring->name = "render ring"; |
2327 | ring->id = RCS; | |
2328 | ring->mmio_base = RENDER_RING_BASE; | |
2329 | ||
707d9cf9 | 2330 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2331 | if (i915_semaphore_is_enabled(dev)) { |
2332 | obj = i915_gem_alloc_object(dev, 4096); | |
2333 | if (obj == NULL) { | |
2334 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2335 | i915.semaphores = 0; | |
2336 | } else { | |
2337 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2338 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2339 | if (ret != 0) { | |
2340 | drm_gem_object_unreference(&obj->base); | |
2341 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2342 | i915.semaphores = 0; | |
2343 | } else | |
2344 | dev_priv->semaphore_obj = obj; | |
2345 | } | |
2346 | } | |
7225342a MK |
2347 | |
2348 | ring->init_context = intel_ring_workarounds_emit; | |
707d9cf9 BW |
2349 | ring->add_request = gen6_add_request; |
2350 | ring->flush = gen8_render_ring_flush; | |
2351 | ring->irq_get = gen8_ring_get_irq; | |
2352 | ring->irq_put = gen8_ring_put_irq; | |
2353 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2354 | ring->get_seqno = gen6_ring_get_seqno; | |
2355 | ring->set_seqno = ring_set_seqno; | |
2356 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2357 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2358 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2359 | ring->semaphore.signal = gen8_rcs_signal; |
2360 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2361 | } |
2362 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2363 | ring->add_request = gen6_add_request; |
4772eaeb | 2364 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2365 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2366 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2367 | ring->irq_get = gen6_ring_get_irq; |
2368 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2369 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2370 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2371 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2372 | if (i915_semaphore_is_enabled(dev)) { |
2373 | ring->semaphore.sync_to = gen6_ring_sync; | |
2374 | ring->semaphore.signal = gen6_signal; | |
2375 | /* | |
2376 | * The current semaphore is only applied on pre-gen8 | |
2377 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2378 | * platform. So the semaphore between RCS and VCS2 is | |
2379 | * initialized as INVALID. Gen8 will initialize the | |
2380 | * sema between VCS2 and RCS later. | |
2381 | */ | |
2382 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2383 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2384 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2385 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2386 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2387 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2388 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2389 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2390 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2391 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2392 | } | |
c6df541c CW |
2393 | } else if (IS_GEN5(dev)) { |
2394 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2395 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2396 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2397 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2398 | ring->irq_get = gen5_ring_get_irq; |
2399 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2400 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2401 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2402 | } else { |
8620a3a9 | 2403 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2404 | if (INTEL_INFO(dev)->gen < 4) |
2405 | ring->flush = gen2_render_ring_flush; | |
2406 | else | |
2407 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2408 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2409 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2410 | if (IS_GEN2(dev)) { |
2411 | ring->irq_get = i8xx_ring_get_irq; | |
2412 | ring->irq_put = i8xx_ring_put_irq; | |
2413 | } else { | |
2414 | ring->irq_get = i9xx_ring_get_irq; | |
2415 | ring->irq_put = i9xx_ring_put_irq; | |
2416 | } | |
e3670319 | 2417 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2418 | } |
59465b5f | 2419 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2420 | |
d7d4eedd CW |
2421 | if (IS_HASWELL(dev)) |
2422 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2423 | else if (IS_GEN8(dev)) |
2424 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2425 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2426 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2427 | else if (INTEL_INFO(dev)->gen >= 4) | |
2428 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2429 | else if (IS_I830(dev) || IS_845G(dev)) | |
2430 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2431 | else | |
2432 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
ecfe00d8 | 2433 | ring->init_hw = init_render_ring; |
59465b5f DV |
2434 | ring->cleanup = render_ring_cleanup; |
2435 | ||
b45305fc DV |
2436 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2437 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2438 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2439 | if (obj == NULL) { |
2440 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2441 | return -ENOMEM; | |
2442 | } | |
2443 | ||
be1fa129 | 2444 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2445 | if (ret != 0) { |
2446 | drm_gem_object_unreference(&obj->base); | |
2447 | DRM_ERROR("Failed to ping batch bo\n"); | |
2448 | return ret; | |
2449 | } | |
2450 | ||
0d1aacac CW |
2451 | ring->scratch.obj = obj; |
2452 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2453 | } |
2454 | ||
99be1dfe DV |
2455 | ret = intel_init_ring_buffer(dev, ring); |
2456 | if (ret) | |
2457 | return ret; | |
2458 | ||
2459 | if (INTEL_INFO(dev)->gen >= 5) { | |
2460 | ret = intel_init_pipe_control(ring); | |
2461 | if (ret) | |
2462 | return ret; | |
2463 | } | |
2464 | ||
2465 | return 0; | |
5c1143bb XH |
2466 | } |
2467 | ||
2468 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2469 | { | |
4640c4ff | 2470 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2471 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2472 | |
58fa3835 DV |
2473 | ring->name = "bsd ring"; |
2474 | ring->id = VCS; | |
2475 | ||
0fd2c201 | 2476 | ring->write_tail = ring_write_tail; |
780f18c8 | 2477 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2478 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2479 | /* gen6 bsd needs a special wa for tail updates */ |
2480 | if (IS_GEN6(dev)) | |
2481 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2482 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2483 | ring->add_request = gen6_add_request; |
2484 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2485 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2486 | if (INTEL_INFO(dev)->gen >= 8) { |
2487 | ring->irq_enable_mask = | |
2488 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2489 | ring->irq_get = gen8_ring_get_irq; | |
2490 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2491 | ring->dispatch_execbuffer = |
2492 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2493 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2494 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2495 | ring->semaphore.signal = gen8_xcs_signal; |
2496 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2497 | } |
abd58f01 BW |
2498 | } else { |
2499 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2500 | ring->irq_get = gen6_ring_get_irq; | |
2501 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2502 | ring->dispatch_execbuffer = |
2503 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2504 | if (i915_semaphore_is_enabled(dev)) { |
2505 | ring->semaphore.sync_to = gen6_ring_sync; | |
2506 | ring->semaphore.signal = gen6_signal; | |
2507 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2508 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2509 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2510 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2511 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2512 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2513 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2514 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2515 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2516 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2517 | } | |
abd58f01 | 2518 | } |
58fa3835 DV |
2519 | } else { |
2520 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2521 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2522 | ring->add_request = i9xx_add_request; |
58fa3835 | 2523 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2524 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2525 | if (IS_GEN5(dev)) { |
cc609d5d | 2526 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2527 | ring->irq_get = gen5_ring_get_irq; |
2528 | ring->irq_put = gen5_ring_put_irq; | |
2529 | } else { | |
e3670319 | 2530 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2531 | ring->irq_get = i9xx_ring_get_irq; |
2532 | ring->irq_put = i9xx_ring_put_irq; | |
2533 | } | |
fb3256da | 2534 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2535 | } |
ecfe00d8 | 2536 | ring->init_hw = init_ring_common; |
58fa3835 | 2537 | |
1ec14ad3 | 2538 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2539 | } |
549f7365 | 2540 | |
845f74a7 ZY |
2541 | /** |
2542 | * Initialize the second BSD ring for Broadwell GT3. | |
2543 | * It is noted that this only exists on Broadwell GT3. | |
2544 | */ | |
2545 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2546 | { | |
2547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2548 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 ZY |
2549 | |
2550 | if ((INTEL_INFO(dev)->gen != 8)) { | |
2551 | DRM_ERROR("No dual-BSD ring on non-BDW machine\n"); | |
2552 | return -EINVAL; | |
2553 | } | |
2554 | ||
f7b64236 | 2555 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2556 | ring->id = VCS2; |
2557 | ||
2558 | ring->write_tail = ring_write_tail; | |
2559 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2560 | ring->flush = gen6_bsd_ring_flush; | |
2561 | ring->add_request = gen6_add_request; | |
2562 | ring->get_seqno = gen6_ring_get_seqno; | |
2563 | ring->set_seqno = ring_set_seqno; | |
2564 | ring->irq_enable_mask = | |
2565 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2566 | ring->irq_get = gen8_ring_get_irq; | |
2567 | ring->irq_put = gen8_ring_put_irq; | |
2568 | ring->dispatch_execbuffer = | |
2569 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2570 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2571 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2572 | ring->semaphore.signal = gen8_xcs_signal; |
2573 | GEN8_RING_SEMAPHORE_INIT; | |
2574 | } | |
ecfe00d8 | 2575 | ring->init_hw = init_ring_common; |
845f74a7 ZY |
2576 | |
2577 | return intel_init_ring_buffer(dev, ring); | |
2578 | } | |
2579 | ||
549f7365 CW |
2580 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2581 | { | |
4640c4ff | 2582 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2583 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2584 | |
3535d9dd DV |
2585 | ring->name = "blitter ring"; |
2586 | ring->id = BCS; | |
2587 | ||
2588 | ring->mmio_base = BLT_RING_BASE; | |
2589 | ring->write_tail = ring_write_tail; | |
ea251324 | 2590 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2591 | ring->add_request = gen6_add_request; |
2592 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2593 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2594 | if (INTEL_INFO(dev)->gen >= 8) { |
2595 | ring->irq_enable_mask = | |
2596 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2597 | ring->irq_get = gen8_ring_get_irq; | |
2598 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2599 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2600 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2601 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2602 | ring->semaphore.signal = gen8_xcs_signal; |
2603 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2604 | } |
abd58f01 BW |
2605 | } else { |
2606 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2607 | ring->irq_get = gen6_ring_get_irq; | |
2608 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2609 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2610 | if (i915_semaphore_is_enabled(dev)) { |
2611 | ring->semaphore.signal = gen6_signal; | |
2612 | ring->semaphore.sync_to = gen6_ring_sync; | |
2613 | /* | |
2614 | * The current semaphore is only applied on pre-gen8 | |
2615 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2616 | * platform. So the semaphore between BCS and VCS2 is | |
2617 | * initialized as INVALID. Gen8 will initialize the | |
2618 | * sema between BCS and VCS2 later. | |
2619 | */ | |
2620 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2621 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2622 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2623 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2624 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2625 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2626 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2627 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2628 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2629 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2630 | } | |
abd58f01 | 2631 | } |
ecfe00d8 | 2632 | ring->init_hw = init_ring_common; |
549f7365 | 2633 | |
1ec14ad3 | 2634 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2635 | } |
a7b9761d | 2636 | |
9a8a2213 BW |
2637 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2638 | { | |
4640c4ff | 2639 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2640 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2641 | |
2642 | ring->name = "video enhancement ring"; | |
2643 | ring->id = VECS; | |
2644 | ||
2645 | ring->mmio_base = VEBOX_RING_BASE; | |
2646 | ring->write_tail = ring_write_tail; | |
2647 | ring->flush = gen6_ring_flush; | |
2648 | ring->add_request = gen6_add_request; | |
2649 | ring->get_seqno = gen6_ring_get_seqno; | |
2650 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2651 | |
2652 | if (INTEL_INFO(dev)->gen >= 8) { | |
2653 | ring->irq_enable_mask = | |
40c499f9 | 2654 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2655 | ring->irq_get = gen8_ring_get_irq; |
2656 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2657 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2658 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2659 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2660 | ring->semaphore.signal = gen8_xcs_signal; |
2661 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2662 | } |
abd58f01 BW |
2663 | } else { |
2664 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2665 | ring->irq_get = hsw_vebox_get_irq; | |
2666 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2667 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2668 | if (i915_semaphore_is_enabled(dev)) { |
2669 | ring->semaphore.sync_to = gen6_ring_sync; | |
2670 | ring->semaphore.signal = gen6_signal; | |
2671 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2672 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2673 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2674 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2675 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2676 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2677 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2678 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2679 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2680 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2681 | } | |
abd58f01 | 2682 | } |
ecfe00d8 | 2683 | ring->init_hw = init_ring_common; |
9a8a2213 BW |
2684 | |
2685 | return intel_init_ring_buffer(dev, ring); | |
2686 | } | |
2687 | ||
a7b9761d | 2688 | int |
a4872ba6 | 2689 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2690 | { |
2691 | int ret; | |
2692 | ||
2693 | if (!ring->gpu_caches_dirty) | |
2694 | return 0; | |
2695 | ||
2696 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2697 | if (ret) | |
2698 | return ret; | |
2699 | ||
2700 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2701 | ||
2702 | ring->gpu_caches_dirty = false; | |
2703 | return 0; | |
2704 | } | |
2705 | ||
2706 | int | |
a4872ba6 | 2707 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2708 | { |
2709 | uint32_t flush_domains; | |
2710 | int ret; | |
2711 | ||
2712 | flush_domains = 0; | |
2713 | if (ring->gpu_caches_dirty) | |
2714 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2715 | ||
2716 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2717 | if (ret) | |
2718 | return ret; | |
2719 | ||
2720 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2721 | ||
2722 | ring->gpu_caches_dirty = false; | |
2723 | return 0; | |
2724 | } | |
e3efda49 CW |
2725 | |
2726 | void | |
a4872ba6 | 2727 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2728 | { |
2729 | int ret; | |
2730 | ||
2731 | if (!intel_ring_initialized(ring)) | |
2732 | return; | |
2733 | ||
2734 | ret = intel_ring_idle(ring); | |
2735 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2736 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2737 | ring->name, ret); | |
2738 | ||
2739 | stop_ring(ring); | |
2740 | } |