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drm/i915: Do not call API requiring struct_mutex where it is not available
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
82e104cc 37int __intel_ring_space(int head, int tail, int size)
c7dca47b 38{
4f54741e
DG		 39 int space = head - tail;
40 if (space <= 0)
1cf0ba14 41 space += size;
4f54741e 42 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 43}
44
ebd0fd4b
DG		 45void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46{
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54}
55
82e104cc 56int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 57{
ebd0fd4b
DG		 58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
1cf0ba14
CW		 60}
61
82e104cc 62bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 63{
64 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 65 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
66}
09246732 67
6258fbe2 68static void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 69{
93b0a4e0
OM		 70 struct intel_ringbuffer *ringbuf = ring->buffer;
71 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 72 if (intel_ring_stopped(ring))
09246732 73 return;
93b0a4e0 74 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 75}
76
b72f3acb 77static int
a84c3ae1 78gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 79 u32 invalidate_domains,
80 u32 flush_domains)
81{
a84c3ae1 82 struct intel_engine_cs *ring = req->ring;
46f0f8d1
CW		 83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
31b14c9f 87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
5fb9de1a 93 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 94 if (ret)
95 return ret;
96
97 intel_ring_emit(ring, cmd);
98 intel_ring_emit(ring, MI_NOOP);
99 intel_ring_advance(ring);
100
101 return 0;
102}
103
104static int
a84c3ae1 105gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 106 u32 invalidate_domains,
107 u32 flush_domains)
62fdfeaf 108{
a84c3ae1 109 struct intel_engine_cs *ring = req->ring;
78501eac 110 struct drm_device *dev = ring->dev;
6f392d54 111 u32 cmd;
b72f3acb 112 int ret;
6f392d54 113
36d527de
CW		 114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 144 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
62fdfeaf 147
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
70eac33e 151
5fb9de1a 152 ret = intel_ring_begin(req, 2);
36d527de
CW		 153 if (ret)
154 return ret;
b72f3acb 155
36d527de
CW		 156 intel_ring_emit(ring, cmd);
157 intel_ring_emit(ring, MI_NOOP);
158 intel_ring_advance(ring);
b72f3acb
CW		 159
160 return 0;
8187a2b7
ZN		 161}
162
8d315287
JB		 163/**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200static int
f2cf1fcc 201intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 202{
f2cf1fcc 203 struct intel_engine_cs *ring = req->ring;
18393f63 204 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 205 int ret;
206
5fb9de1a 207 ret = intel_ring_begin(req, 6);
8d315287
JB		 208 if (ret)
209 return ret;
210
211 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
214 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(ring, 0); /* low dword */
216 intel_ring_emit(ring, 0); /* high dword */
217 intel_ring_emit(ring, MI_NOOP);
218 intel_ring_advance(ring);
219
5fb9de1a 220 ret = intel_ring_begin(req, 6);
8d315287
JB		 221 if (ret)
222 return ret;
223
224 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(ring, 0);
228 intel_ring_emit(ring, 0);
229 intel_ring_emit(ring, MI_NOOP);
230 intel_ring_advance(ring);
231
232 return 0;
233}
234
235static int
a84c3ae1
JH		 236gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
8d315287 238{
a84c3ae1 239 struct intel_engine_cs *ring = req->ring;
8d315287 240 u32 flags = 0;
18393f63 241 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 242 int ret;
243
b3111509 244 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 245 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 246 if (ret)
247 return ret;
248
8d315287
JB		 249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
7d54a904
CW		 253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
97f209bc 260 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
3ac78313 272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 273 }
8d315287 274
5fb9de1a 275 ret = intel_ring_begin(req, 4);
8d315287
JB		 276 if (ret)
277 return ret;
278
6c6cf5aa 279 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 280 intel_ring_emit(ring, flags);
281 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 282 intel_ring_emit(ring, 0);
8d315287
JB		 283 intel_ring_advance(ring);
284
285 return 0;
286}
287
f3987631 288static int
f2cf1fcc 289gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 290{
f2cf1fcc 291 struct intel_engine_cs *ring = req->ring;
f3987631
PZ		 292 int ret;
293
5fb9de1a 294 ret = intel_ring_begin(req, 4);
f3987631
PZ		 295 if (ret)
296 return ret;
297
298 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
301 intel_ring_emit(ring, 0);
302 intel_ring_emit(ring, 0);
303 intel_ring_advance(ring);
304
305 return 0;
306}
307
4772eaeb 308static int
a84c3ae1 309gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 310 u32 invalidate_domains, u32 flush_domains)
311{
a84c3ae1 312 struct intel_engine_cs *ring = req->ring;
4772eaeb 313 u32 flags = 0;
18393f63 314 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 315 int ret;
316
f3987631
PZ		 317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
4772eaeb
PZ		 327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 350
add284a3
CW		 351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
f3987631
PZ		 353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
f2cf1fcc 356 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 357 }
358
5fb9de1a 359 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 360 if (ret)
361 return ret;
362
363 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(ring, flags);
b9e1faa7 365 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 366 intel_ring_emit(ring, 0);
367 intel_ring_advance(ring);
368
369 return 0;
370}
371
884ceace 372static int
f2cf1fcc 373gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 374 u32 flags, u32 scratch_addr)
375{
f2cf1fcc 376 struct intel_engine_cs *ring = req->ring;
884ceace
KG		 377 int ret;
378
5fb9de1a 379 ret = intel_ring_begin(req, 6);
884ceace
KG		 380 if (ret)
381 return ret;
382
383 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(ring, flags);
385 intel_ring_emit(ring, scratch_addr);
386 intel_ring_emit(ring, 0);
387 intel_ring_emit(ring, 0);
388 intel_ring_emit(ring, 0);
389 intel_ring_advance(ring);
390
391 return 0;
392}
393
a5f3d68e 394static int
a84c3ae1 395gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 396 u32 invalidate_domains, u32 flush_domains)
397{
398 u32 flags = 0;
f2cf1fcc 399 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 400 int ret;
a5f3d68e
BW		 401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 421 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
a5f3d68e
BW		 427 }
428
f2cf1fcc 429 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 430}
431
a4872ba6 432static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 433 u32 value)
d46eefa2 434{
4640c4ff 435 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 436 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 437}
438
a4872ba6 439u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 440{
4640c4ff 441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 442 u64 acthd;
8187a2b7 443
50877445
CW		 444 if (INTEL_INFO(ring->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
446 RING_ACTHD_UDW(ring->mmio_base));
447 else if (INTEL_INFO(ring->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
8187a2b7
ZN		 453}
454
a4872ba6 455static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 456{
457 struct drm_i915_private *dev_priv = ring->dev->dev_private;
458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
461 if (INTEL_INFO(ring->dev)->gen >= 4)
462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464}
465
af75f269
DL		 466static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
467{
468 struct drm_device *dev = ring->dev;
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
f0f59a00 470 i915_reg_t mmio;
af75f269
DL		 471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
476 switch (ring->id) {
477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
495 } else if (IS_GEN6(ring->dev)) {
496 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
497 } else {
498 /* XXX: gen8 returns to sanity */
499 mmio = RING_HWS_PGA(ring->mmio_base);
500 }
501
502 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
f0f59a00 513 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
af75f269
DL		 514
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
524 ring->name);
525 }
526}
527
a4872ba6 528static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 529{
9991ae78 530 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 531
9991ae78
CW		 532 if (!IS_GEN2(ring->dev)) {
533 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 534 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 536 /* Sometimes we observe that the idle flag is not
537 * set even though the ring is empty. So double
538 * check before giving up.
539 */
540 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
541 return false;
9991ae78
CW		 542 }
543 }
b7884eb4 544
7f2ab699 545 I915_WRITE_CTL(ring, 0);
570ef608 546 I915_WRITE_HEAD(ring, 0);
78501eac 547 ring->write_tail(ring, 0);
8187a2b7 548
9991ae78
CW		 549 if (!IS_GEN2(ring->dev)) {
550 (void)I915_READ_CTL(ring);
551 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
552 }
a51435a3 553
9991ae78
CW		 554 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
555}
8187a2b7 556
a4872ba6 557static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 558{
559 struct drm_device *dev = ring->dev;
560 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 561 struct intel_ringbuffer *ringbuf = ring->buffer;
562 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 563 int ret = 0;
564
59bad947 565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 566
567 if (!stop_ring(ring)) {
568 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
571 ring->name,
572 I915_READ_CTL(ring),
573 I915_READ_HEAD(ring),
574 I915_READ_TAIL(ring),
575 I915_READ_START(ring));
8187a2b7 576
9991ae78 577 if (!stop_ring(ring)) {
6fd0d56e
CW		 578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
580 ring->name,
581 I915_READ_CTL(ring),
582 I915_READ_HEAD(ring),
583 I915_READ_TAIL(ring),
584 I915_READ_START(ring));
9991ae78
CW		 585 ret = -EIO;
586 goto out;
6fd0d56e 587 }
8187a2b7
ZN		 588 }
589
9991ae78
CW		 590 if (I915_NEED_GFX_HWS(dev))
591 intel_ring_setup_status_page(ring);
592 else
593 ring_setup_phys_status_page(ring);
594
ece4a17d
JK		 595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(ring);
597
0d8957c8
DV		 598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
f343c5f6 602 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 603
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(ring))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 ring->name, I915_READ_HEAD(ring));
608 I915_WRITE_HEAD(ring, 0);
609 (void)I915_READ_HEAD(ring);
610
7f2ab699 611 I915_WRITE_CTL(ring,
93b0a4e0 612 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 613 | RING_VALID);
8187a2b7 614
8187a2b7 615 /* If the head is still not zero, the ring is dead */
f01db988 616 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 617 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 618 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 619 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
621 ring->name,
622 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
623 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
624 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 625 ret = -EIO;
626 goto out;
8187a2b7
ZN		 627 }
628
ebd0fd4b 629 ringbuf->last_retired_head = -1;
5c6c6003
CW		 630 ringbuf->head = I915_READ_HEAD(ring);
631 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 632 intel_ring_update_space(ringbuf);
1ec14ad3 633
50f018df
CW		 634 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
635
b7884eb4 636out:
59bad947 637 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 638
639 return ret;
8187a2b7
ZN		 640}
641
9b1136d5
OM		 642void
643intel_fini_pipe_control(struct intel_engine_cs *ring)
644{
645 struct drm_device *dev = ring->dev;
646
647 if (ring->scratch.obj == NULL)
648 return;
649
650 if (INTEL_INFO(dev)->gen >= 5) {
651 kunmap(sg_page(ring->scratch.obj->pages->sgl));
652 i915_gem_object_ggtt_unpin(ring->scratch.obj);
653 }
654
655 drm_gem_object_unreference(&ring->scratch.obj->base);
656 ring->scratch.obj = NULL;
657}
658
659int
660intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 661{
c6df541c
CW		 662 int ret;
663
bfc882b4 664 WARN_ON(ring->scratch.obj);
c6df541c 665
0d1aacac
CW		 666 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
667 if (ring->scratch.obj == NULL) {
c6df541c
CW		 668 DRM_ERROR("Failed to allocate seqno page\n");
669 ret = -ENOMEM;
670 goto err;
671 }
e4ffd173 672
a9cc726c
DV		 673 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
674 if (ret)
675 goto err_unref;
c6df541c 676
1ec9e26d 677 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 678 if (ret)
679 goto err_unref;
680
0d1aacac
CW		 681 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
682 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
683 if (ring->scratch.cpu_page == NULL) {
56b085a0 684 ret = -ENOMEM;
c6df541c 685 goto err_unpin;
56b085a0 686 }
c6df541c 687
2b1086cc 688 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 689 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 690 return 0;
691
692err_unpin:
d7f46fc4 693 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 694err_unref:
0d1aacac 695 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 696err:
c6df541c
CW		 697 return ret;
698}
699
e2be4faf 700static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 701{
7225342a 702 int ret, i;
e2be4faf 703 struct intel_engine_cs *ring = req->ring;
888b5995
AS		 704 struct drm_device *dev = ring->dev;
705 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 706 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 707
02235808 708 if (w->count == 0)
7225342a 709 return 0;
888b5995 710
7225342a 711 ring->gpu_caches_dirty = true;
4866d729 712 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 713 if (ret)
714 return ret;
888b5995 715
5fb9de1a 716 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 717 if (ret)
718 return ret;
719
22a916aa 720 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 721 for (i = 0; i < w->count; i++) {
f92a9162 722 intel_ring_emit_reg(ring, w->reg[i].addr);
7225342a
MK		 723 intel_ring_emit(ring, w->reg[i].value);
724 }
22a916aa 725 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 726
727 intel_ring_advance(ring);
728
729 ring->gpu_caches_dirty = true;
4866d729 730 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 731 if (ret)
732 return ret;
888b5995 733
7225342a 734 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 735
7225342a 736 return 0;
86d7f238
AS		 737}
738
8753181e 739static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 740{
741 int ret;
742
e2be4faf 743 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 744 if (ret != 0)
745 return ret;
746
be01363f 747 ret = i915_gem_render_state_init(req);
8f0e2b9d
DV		 748 if (ret)
749 DRM_ERROR("init render state: %d\n", ret);
750
751 return ret;
752}
753
7225342a 754static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 755 i915_reg_t addr,
756 const u32 mask, const u32 val)
7225342a
MK		 757{
758 const u32 idx = dev_priv->workarounds.count;
759
760 if (WARN_ON(idx >= I915_MAX_WA_REGS))
761 return -ENOSPC;
762
763 dev_priv->workarounds.reg[idx].addr = addr;
764 dev_priv->workarounds.reg[idx].value = val;
765 dev_priv->workarounds.reg[idx].mask = mask;
766
767 dev_priv->workarounds.count++;
768
769 return 0;
86d7f238
AS		 770}
771
ca5a0fbd 772#define WA_REG(addr, mask, val) do { \
cf4b0de6 773 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 774 if (r) \
775 return r; \
ca5a0fbd 776 } while (0)
7225342a
MK		 777
778#define WA_SET_BIT_MASKED(addr, mask) \
26459343 779 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 780
781#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 782 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 783
98533251 784#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 785 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 786
cf4b0de6
DL		 787#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
788#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 789
cf4b0de6 790#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 791
e9a64ada
AS		 792static int gen8_init_workarounds(struct intel_engine_cs *ring)
793{
68c6198b
AS		 794 struct drm_device *dev = ring->dev;
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 798
717d84d6
AS		 799 /* WaDisableAsyncFlipPerfMode:bdw,chv */
800 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
801
d0581194
AS		 802 /* WaDisablePartialInstShootdown:bdw,chv */
803 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
804 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
805
a340af58
AS		 806 /* Use Force Non-Coherent whenever executing a 3D context. This is a
807 * workaround for for a possible hang in the unlikely event a TLB
808 * invalidation occurs during a PSD flush.
809 */
810 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 811 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 812 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 813 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 814 HDC_FORCE_NON_COHERENT);
815
6def8fdd
AS		 816 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
817 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
818 * polygons in the same 8x4 pixel/sample area to be processed without
819 * stalling waiting for the earlier ones to write to Hierarchical Z
820 * buffer."
821 *
822 * This optimization is off by default for BDW and CHV; turn it on.
823 */
824 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
825
48404636
AS		 826 /* Wa4x4STCOptimizationDisable:bdw,chv */
827 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
828
7eebcde6
AS		 829 /*
830 * BSpec recommends 8x4 when MSAA is used,
831 * however in practice 16x4 seems fastest.
832 *
833 * Note that PS/WM thread counts depend on the WIZ hashing
834 * disable bit, which we don't touch here, but it's good
835 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
836 */
837 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
838 GEN6_WIZ_HASHING_MASK,
839 GEN6_WIZ_HASHING_16x4);
840
e9a64ada
AS		 841 return 0;
842}
843
00e1e623 844static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 845{
e9a64ada 846 int ret;
888b5995
AS		 847 struct drm_device *dev = ring->dev;
848 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 849
e9a64ada
AS		 850 ret = gen8_init_workarounds(ring);
851 if (ret)
852 return ret;
853
101b376d 854 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 855 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 856
101b376d 857 /* WaDisableDopClockGating:bdw */
7225342a
MK		 858 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
859 DOP_CLOCK_GATING_DISABLE);
86d7f238 860
7225342a
MK		 861 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
862 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 863
7225342a 864 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 865 /* WaForceContextSaveRestoreNonCoherent:bdw */
866 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 867 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 868 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 869
86d7f238
AS		 870 return 0;
871}
872
00e1e623
VS		 873static int chv_init_workarounds(struct intel_engine_cs *ring)
874{
e9a64ada 875 int ret;
00e1e623
VS		 876 struct drm_device *dev = ring->dev;
877 struct drm_i915_private *dev_priv = dev->dev_private;
878
e9a64ada
AS		 879 ret = gen8_init_workarounds(ring);
880 if (ret)
881 return ret;
882
00e1e623 883 /* WaDisableThreadStallDopClockGating:chv */
d0581194 884 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 885
d60de81d
KG		 886 /* Improve HiZ throughput on CHV. */
887 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
888
7225342a
MK		 889 return 0;
890}
891
3b106531
HN		 892static int gen9_init_workarounds(struct intel_engine_cs *ring)
893{
ab0dfafe
HN		 894 struct drm_device *dev = ring->dev;
895 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 896 uint32_t tmp;
ab0dfafe 897
9c4cbf82
MK		 898 /* WaEnableLbsSlaRetryTimerDecrement:skl */
899 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
900 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
901
902 /* WaDisableKillLogic:bxt,skl */
903 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
904 ECOCHK_DIS_TLB);
905
b0e6f6d4 906 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 907 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
908 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
909
a119a6e6 910 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 911 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
912 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
913
e87a005d
JN		 914 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
915 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
916 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
a86eb582
DL		 917 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
918 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 919
e87a005d
JN		 920 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
921 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
922 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
183c6dac
DL		 923 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
924 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 925 /*
926 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
927 * but we do that in per ctx batchbuffer as there is an issue
928 * with this register not getting restored on ctx restore
929 */
183c6dac
DL		 930 }
931
e87a005d
JN		 932 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
933 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
cac23df4
NH		 934 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
935 GEN9_ENABLE_YV12_BUGFIX);
cac23df4 936
5068368c 937 /* Wa4x4STCOptimizationDisable:skl,bxt */
27160c96 938 /* WaDisablePartialResolveInVc:skl,bxt */
60294683
AS		 939 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
940 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 941
16be17af 942 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 943 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
944 GEN9_CCS_TLB_PREFETCH_ENABLE);
945
5a2ae95e 946 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
e87a005d
JN		 947 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
948 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
38a39a7b
BW		 949 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
950 PIXEL_MASK_CAMMING_DISABLE);
951
8ea6f892
ID		 952 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
953 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
e87a005d
JN		 954 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
955 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
8ea6f892
ID		 956 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
957 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
958
8c761609 959 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
e87a005d 960 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
8c761609
AS		 961 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
962 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 963
6b6d5626
RB		 964 /* WaDisableSTUnitPowerOptimization:skl,bxt */
965 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
966
3b106531
HN		 967 return 0;
968}
969
b7668791
DL		 970static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
971{
972 struct drm_device *dev = ring->dev;
973 struct drm_i915_private *dev_priv = dev->dev_private;
974 u8 vals[3] = { 0, 0, 0 };
975 unsigned int i;
976
977 for (i = 0; i < 3; i++) {
978 u8 ss;
979
980 /*
981 * Only consider slices where one, and only one, subslice has 7
982 * EUs
983 */
a4d8a0fe 984 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 985 continue;
986
987 /*
988 * subslice_7eu[i] != 0 (because of the check above) and
989 * ss_max == 4 (maximum number of subslices possible per slice)
990 *
991 * -> 0 <= ss <= 3;
992 */
993 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
994 vals[i] = 3 - ss;
995 }
996
997 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
998 return 0;
999
1000 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1001 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1002 GEN9_IZ_HASHING_MASK(2) |
1003 GEN9_IZ_HASHING_MASK(1) |
1004 GEN9_IZ_HASHING_MASK(0),
1005 GEN9_IZ_HASHING(2, vals[2]) |
1006 GEN9_IZ_HASHING(1, vals[1]) |
1007 GEN9_IZ_HASHING(0, vals[0]));
1008
1009 return 0;
1010}
1011
8d205494
DL		 1012static int skl_init_workarounds(struct intel_engine_cs *ring)
1013{
aa0011a8 1014 int ret;
d0bbbc4f
DL		 1015 struct drm_device *dev = ring->dev;
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017
aa0011a8
AS		 1018 ret = gen9_init_workarounds(ring);
1019 if (ret)
1020 return ret;
8d205494 1021
e87a005d 1022 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
9c4cbf82
MK		 1023 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1024 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1025 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1026 }
1027
1028 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1029 * involving this register should also be added to WA batch as required.
1030 */
e87a005d 1031 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
9c4cbf82
MK		 1032 /* WaDisableLSQCROPERFforOCL:skl */
1033 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1034 GEN8_LQSC_RO_PERF_DIS);
1035
1036 /* WaEnableGapsTsvCreditFix:skl */
e87a005d 1037 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1038 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1039 GEN9_GAPS_TSV_CREDIT_DISABLE));
1040 }
1041
d0bbbc4f 1042 /* WaDisablePowerCompilerClockGating:skl */
e87a005d 1043 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1044 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1045 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1046
e238659d 1047 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
b62adbd1
NH		 1048 /*
1049 *Use Force Non-Coherent whenever executing a 3D context. This
1050 * is a workaround for a possible hang in the unlikely event
1051 * a TLB invalidation occurs during a PSD flush.
1052 */
1053 /* WaForceEnableNonCoherent:skl */
1054 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1055 HDC_FORCE_NON_COHERENT);
e238659d
MK		 1056
1057 /* WaDisableHDCInvalidation:skl */
1058 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1059 BDW_DISABLE_HDC_INVALIDATION);
b62adbd1
NH		 1060 }
1061
e87a005d
JN		 1062 /* WaBarrierPerformanceFixDisable:skl */
1063 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1064 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1065 HDC_FENCE_DEST_SLM_DISABLE |
1066 HDC_BARRIER_PERFORMANCE_DISABLE);
1067
9bd9dfb4 1068 /* WaDisableSbeCacheDispatchPortSharing:skl */
e87a005d 1069 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1070 WA_SET_BIT_MASKED(
1071 GEN7_HALF_SLICE_CHICKEN1,
1072 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1073
b7668791 1074 return skl_tune_iz_hashing(ring);
7225342a
MK		 1075}
1076
cae0437f
NH		 1077static int bxt_init_workarounds(struct intel_engine_cs *ring)
1078{
aa0011a8 1079 int ret;
dfb601e6
NH		 1080 struct drm_device *dev = ring->dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082
aa0011a8
AS		 1083 ret = gen9_init_workarounds(ring);
1084 if (ret)
1085 return ret;
cae0437f 1086
9c4cbf82
MK		 1087 /* WaStoreMultiplePTEenable:bxt */
1088 /* This is a requirement according to Hardware specification */
cbdc12a9 1089 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
9c4cbf82
MK		 1090 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1091
1092 /* WaSetClckGatingDisableMedia:bxt */
cbdc12a9 1093 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1094 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1095 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1096 }
1097
dfb601e6
NH		 1098 /* WaDisableThreadStallDopClockGating:bxt */
1099 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1100 STALL_DOP_GATING_DISABLE);
1101
983b4b9d 1102 /* WaDisableSbeCacheDispatchPortSharing:bxt */
e87a005d 1103 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1104 WA_SET_BIT_MASKED(
1105 GEN7_HALF_SLICE_CHICKEN1,
1106 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1107 }
1108
cae0437f
NH		 1109 return 0;
1110}
1111
771b9a53 1112int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1113{
1114 struct drm_device *dev = ring->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116
1117 WARN_ON(ring->id != RCS);
1118
1119 dev_priv->workarounds.count = 0;
1120
1121 if (IS_BROADWELL(dev))
1122 return bdw_init_workarounds(ring);
1123
1124 if (IS_CHERRYVIEW(dev))
1125 return chv_init_workarounds(ring);
00e1e623 1126
8d205494
DL		 1127 if (IS_SKYLAKE(dev))
1128 return skl_init_workarounds(ring);
cae0437f
NH		 1129
1130 if (IS_BROXTON(dev))
1131 return bxt_init_workarounds(ring);
3b106531 1132
00e1e623
VS		 1133 return 0;
1134}
1135
a4872ba6 1136static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1137{
78501eac 1138 struct drm_device *dev = ring->dev;
1ec14ad3 1139 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1140 int ret = init_ring_common(ring);
9c33baa6
KZ		 1141 if (ret)
1142 return ret;
a69ffdbf 1143
61a563a2
AG		 1144 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1145 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1146 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1147
1148 /* We need to disable the AsyncFlip performance optimisations in order
1149 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1150 * programmed to '1' on all products.
8693a824 1151 *
2441f877 1152 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1153 */
2441f877 1154 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1155 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1156
f05bb0c7 1157 /* Required for the hardware to program scanline values for waiting */
01fa0302 1158 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1159 if (INTEL_INFO(dev)->gen == 6)
1160 I915_WRITE(GFX_MODE,
aa83e30d 1161 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1162
01fa0302 1163 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1164 if (IS_GEN7(dev))
1165 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1166 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1167 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1168
5e13a0c5 1169 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1170 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1171 * "If this bit is set, STCunit will have LRA as replacement
1172 * policy. [...] This bit must be reset. LRA replacement
1173 * policy is not supported."
1174 */
1175 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1176 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1177 }
1178
9cc83020 1179 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1180 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1181
040d2baa 1182 if (HAS_L3_DPF(dev))
35a85ac6 1183 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1184
7225342a 1185 return init_workarounds_ring(ring);
8187a2b7
ZN		 1186}
1187
a4872ba6 1188static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1189{
b45305fc 1190 struct drm_device *dev = ring->dev;
3e78998a
BW		 1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192
1193 if (dev_priv->semaphore_obj) {
1194 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1195 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1196 dev_priv->semaphore_obj = NULL;
1197 }
b45305fc 1198
9b1136d5 1199 intel_fini_pipe_control(ring);
c6df541c
CW		 1200}
1201
f7169687 1202static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1203 unsigned int num_dwords)
1204{
1205#define MBOX_UPDATE_DWORDS 8
f7169687 1206 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1207 struct drm_device *dev = signaller->dev;
1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 struct intel_engine_cs *waiter;
1210 int i, ret, num_rings;
1211
1212 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1213 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1214#undef MBOX_UPDATE_DWORDS
1215
5fb9de1a 1216 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1217 if (ret)
1218 return ret;
1219
1220 for_each_ring(waiter, dev_priv, i) {
6259cead 1221 u32 seqno;
3e78998a
BW		 1222 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1223 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1224 continue;
1225
f7169687 1226 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1227 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1228 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1229 PIPE_CONTROL_QW_WRITE |
1230 PIPE_CONTROL_FLUSH_ENABLE);
1231 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1232 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1233 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1234 intel_ring_emit(signaller, 0);
1235 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1236 MI_SEMAPHORE_TARGET(waiter->id));
1237 intel_ring_emit(signaller, 0);
1238 }
1239
1240 return 0;
1241}
1242
f7169687 1243static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1244 unsigned int num_dwords)
1245{
1246#define MBOX_UPDATE_DWORDS 6
f7169687 1247 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1248 struct drm_device *dev = signaller->dev;
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 struct intel_engine_cs *waiter;
1251 int i, ret, num_rings;
1252
1253 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1254 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1255#undef MBOX_UPDATE_DWORDS
1256
5fb9de1a 1257 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1258 if (ret)
1259 return ret;
1260
1261 for_each_ring(waiter, dev_priv, i) {
6259cead 1262 u32 seqno;
3e78998a
BW		 1263 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1264 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1265 continue;
1266
f7169687 1267 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1268 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1269 MI_FLUSH_DW_OP_STOREDW);
1270 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1271 MI_FLUSH_DW_USE_GTT);
1272 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1273 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1274 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1275 MI_SEMAPHORE_TARGET(waiter->id));
1276 intel_ring_emit(signaller, 0);
1277 }
1278
1279 return 0;
1280}
1281
f7169687 1282static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1283 unsigned int num_dwords)
1ec14ad3 1284{
f7169687 1285 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1286 struct drm_device *dev = signaller->dev;
1287 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1288 struct intel_engine_cs *useless;
a1444b79 1289 int i, ret, num_rings;
78325f2d 1290
a1444b79
BW		 1291#define MBOX_UPDATE_DWORDS 3
1292 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1293 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1294#undef MBOX_UPDATE_DWORDS
024a43e1 1295
5fb9de1a 1296 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1297 if (ret)
1298 return ret;
024a43e1 1299
78325f2d 1300 for_each_ring(useless, dev_priv, i) {
f0f59a00
VS		 1301 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1302
1303 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1304 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1305
78325f2d 1306 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1307 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1308 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1309 }
1310 }
024a43e1 1311
a1444b79
BW		 1312 /* If num_dwords was rounded, make sure the tail pointer is correct */
1313 if (num_rings % 2 == 0)
1314 intel_ring_emit(signaller, MI_NOOP);
1315
024a43e1 1316 return 0;
1ec14ad3
CW		 1317}
1318
c8c99b0f
BW		 1319/**
1320 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1321 *
1322 * @request - request to write to the ring
c8c99b0f
BW		 1323 *
1324 * Update the mailbox registers in the *other* rings with the current seqno.
1325 * This acts like a signal in the canonical semaphore.
1326 */
1ec14ad3 1327static int
ee044a88 1328gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1329{
ee044a88 1330 struct intel_engine_cs *ring = req->ring;
024a43e1 1331 int ret;
52ed2325 1332
707d9cf9 1333 if (ring->semaphore.signal)
f7169687 1334 ret = ring->semaphore.signal(req, 4);
707d9cf9 1335 else
5fb9de1a 1336 ret = intel_ring_begin(req, 4);
707d9cf9 1337
1ec14ad3
CW		 1338 if (ret)
1339 return ret;
1340
1ec14ad3
CW		 1341 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1342 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1343 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1ec14ad3 1344 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1345 __intel_ring_advance(ring);
1ec14ad3 1346
1ec14ad3
CW		 1347 return 0;
1348}
1349
f72b3435
MK		 1350static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1351 u32 seqno)
1352{
1353 struct drm_i915_private *dev_priv = dev->dev_private;
1354 return dev_priv->last_seqno < seqno;
1355}
1356
c8c99b0f
BW		 1357/**
1358 * intel_ring_sync - sync the waiter to the signaller on seqno
1359 *
1360 * @waiter - ring that is waiting
1361 * @signaller - ring which has, or will signal
1362 * @seqno - seqno which the waiter will block on
1363 */
5ee426ca
BW		 1364
1365static int
599d924c 1366gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1367 struct intel_engine_cs *signaller,
1368 u32 seqno)
1369{
599d924c 1370 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1371 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1372 int ret;
1373
5fb9de1a 1374 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1375 if (ret)
1376 return ret;
1377
1378 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1379 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1380 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1381 MI_SEMAPHORE_SAD_GTE_SDD);
1382 intel_ring_emit(waiter, seqno);
1383 intel_ring_emit(waiter,
1384 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1385 intel_ring_emit(waiter,
1386 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1387 intel_ring_advance(waiter);
1388 return 0;
1389}
1390
c8c99b0f 1391static int
599d924c 1392gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1393 struct intel_engine_cs *signaller,
686cb5f9 1394 u32 seqno)
1ec14ad3 1395{
599d924c 1396 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1397 u32 dw1 = MI_SEMAPHORE_MBOX |
1398 MI_SEMAPHORE_COMPARE |
1399 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1400 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1401 int ret;
1ec14ad3 1402
1500f7ea
BW		 1403 /* Throughout all of the GEM code, seqno passed implies our current
1404 * seqno is >= the last seqno executed. However for hardware the
1405 * comparison is strictly greater than.
1406 */
1407 seqno -= 1;
1408
ebc348b2 1409 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1410
5fb9de1a 1411 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1412 if (ret)
1413 return ret;
1414
f72b3435
MK		 1415 /* If seqno wrap happened, omit the wait with no-ops */
1416 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1417 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1418 intel_ring_emit(waiter, seqno);
1419 intel_ring_emit(waiter, 0);
1420 intel_ring_emit(waiter, MI_NOOP);
1421 } else {
1422 intel_ring_emit(waiter, MI_NOOP);
1423 intel_ring_emit(waiter, MI_NOOP);
1424 intel_ring_emit(waiter, MI_NOOP);
1425 intel_ring_emit(waiter, MI_NOOP);
1426 }
c8c99b0f 1427 intel_ring_advance(waiter);
1ec14ad3
CW		 1428
1429 return 0;
1430}
1431
c6df541c
CW		 1432#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1433do { \
fcbc34e4
KG		 1434 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1435 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1436 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1437 intel_ring_emit(ring__, 0); \
1438 intel_ring_emit(ring__, 0); \
1439} while (0)
1440
1441static int
ee044a88 1442pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1443{
ee044a88 1444 struct intel_engine_cs *ring = req->ring;
18393f63 1445 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1446 int ret;
1447
1448 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1449 * incoherent with writes to memory, i.e. completely fubar,
1450 * so we need to use PIPE_NOTIFY instead.
1451 *
1452 * However, we also need to workaround the qword write
1453 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1454 * memory before requesting an interrupt.
1455 */
5fb9de1a 1456 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1457 if (ret)
1458 return ret;
1459
fcbc34e4 1460 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1461 PIPE_CONTROL_WRITE_FLUSH |
1462 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1463 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1464 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c
CW		 1465 intel_ring_emit(ring, 0);
1466 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1467 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1468 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1469 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1470 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1471 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1472 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1473 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1474 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1475 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1476 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1477
fcbc34e4 1478 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1479 PIPE_CONTROL_WRITE_FLUSH |
1480 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1481 PIPE_CONTROL_NOTIFY);
0d1aacac 1482 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
ee044a88 1483 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
c6df541c 1484 intel_ring_emit(ring, 0);
09246732 1485 __intel_ring_advance(ring);
c6df541c 1486
c6df541c
CW		 1487 return 0;
1488}
1489
4cd53c0c 1490static u32
a4872ba6 1491gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1492{
4cd53c0c
DV		 1493 /* Workaround to force correct ordering between irq and seqno writes on
1494 * ivb (and maybe also on snb) by reading from a CS register (like
1495 * ACTHD) before reading the status page. */
50877445
CW		 1496 if (!lazy_coherency) {
1497 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1498 POSTING_READ(RING_ACTHD(ring->mmio_base));
1499 }
1500
4cd53c0c
DV		 1501 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1502}
1503
8187a2b7 1504static u32
a4872ba6 1505ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1506{
1ec14ad3
CW		 1507 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1508}
1509
b70ec5bf 1510static void
a4872ba6 1511ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1512{
1513 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1514}
1515
c6df541c 1516static u32
a4872ba6 1517pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1518{
0d1aacac 1519 return ring->scratch.cpu_page[0];
c6df541c
CW		 1520}
1521
b70ec5bf 1522static void
a4872ba6 1523pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1524{
0d1aacac 1525 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1526}
1527
e48d8634 1528static bool
a4872ba6 1529gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1530{
1531 struct drm_device *dev = ring->dev;
4640c4ff 1532 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1533 unsigned long flags;
e48d8634 1534
7cd512f1 1535 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1536 return false;
1537
7338aefa 1538 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1539 if (ring->irq_refcount++ == 0)
480c8033 1540 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1541 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1542
1543 return true;
1544}
1545
1546static void
a4872ba6 1547gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1548{
1549 struct drm_device *dev = ring->dev;
4640c4ff 1550 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1551 unsigned long flags;
e48d8634 1552
7338aefa 1553 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1554 if (--ring->irq_refcount == 0)
480c8033 1555 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1556 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1557}
1558
b13c2b96 1559static bool
a4872ba6 1560i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1561{
78501eac 1562 struct drm_device *dev = ring->dev;
4640c4ff 1563 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1564 unsigned long flags;
62fdfeaf 1565
7cd512f1 1566 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1567 return false;
1568
7338aefa 1569 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1570 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1571 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1572 I915_WRITE(IMR, dev_priv->irq_mask);
1573 POSTING_READ(IMR);
1574 }
7338aefa 1575 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1576
1577 return true;
62fdfeaf
EA		 1578}
1579
8187a2b7 1580static void
a4872ba6 1581i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1582{
78501eac 1583 struct drm_device *dev = ring->dev;
4640c4ff 1584 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1585 unsigned long flags;
62fdfeaf 1586
7338aefa 1587 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1588 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1589 dev_priv->irq_mask |= ring->irq_enable_mask;
1590 I915_WRITE(IMR, dev_priv->irq_mask);
1591 POSTING_READ(IMR);
1592 }
7338aefa 1593 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1594}
1595
c2798b19 1596static bool
a4872ba6 1597i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1598{
1599 struct drm_device *dev = ring->dev;
4640c4ff 1600 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1601 unsigned long flags;
c2798b19 1602
7cd512f1 1603 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1604 return false;
1605
7338aefa 1606 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1607 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1608 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1609 I915_WRITE16(IMR, dev_priv->irq_mask);
1610 POSTING_READ16(IMR);
1611 }
7338aefa 1612 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1613
1614 return true;
1615}
1616
1617static void
a4872ba6 1618i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1619{
1620 struct drm_device *dev = ring->dev;
4640c4ff 1621 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1622 unsigned long flags;
c2798b19 1623
7338aefa 1624 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1625 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1626 dev_priv->irq_mask |= ring->irq_enable_mask;
1627 I915_WRITE16(IMR, dev_priv->irq_mask);
1628 POSTING_READ16(IMR);
1629 }
7338aefa 1630 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1631}
1632
b72f3acb 1633static int
a84c3ae1 1634bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1635 u32 invalidate_domains,
1636 u32 flush_domains)
d1b851fc 1637{
a84c3ae1 1638 struct intel_engine_cs *ring = req->ring;
b72f3acb
CW		 1639 int ret;
1640
5fb9de1a 1641 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1642 if (ret)
1643 return ret;
1644
1645 intel_ring_emit(ring, MI_FLUSH);
1646 intel_ring_emit(ring, MI_NOOP);
1647 intel_ring_advance(ring);
1648 return 0;
d1b851fc
ZN		 1649}
1650
3cce469c 1651static int
ee044a88 1652i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1653{
ee044a88 1654 struct intel_engine_cs *ring = req->ring;
3cce469c
CW		 1655 int ret;
1656
5fb9de1a 1657 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1658 if (ret)
1659 return ret;
6f392d54 1660
3cce469c
CW		 1661 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1662 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
ee044a88 1663 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
3cce469c 1664 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1665 __intel_ring_advance(ring);
d1b851fc 1666
3cce469c 1667 return 0;
d1b851fc
ZN		 1668}
1669
0f46832f 1670static bool
a4872ba6 1671gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1672{
1673 struct drm_device *dev = ring->dev;
4640c4ff 1674 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1675 unsigned long flags;
0f46832f 1676
7cd512f1
DV		 1677 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1678 return false;
0f46832f 1679
7338aefa 1680 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1681 if (ring->irq_refcount++ == 0) {
040d2baa 1682 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1683 I915_WRITE_IMR(ring,
1684 ~(ring->irq_enable_mask |
35a85ac6 1685 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1686 else
1687 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1688 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1689 }
7338aefa 1690 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1691
1692 return true;
1693}
1694
1695static void
a4872ba6 1696gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1697{
1698 struct drm_device *dev = ring->dev;
4640c4ff 1699 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1700 unsigned long flags;
0f46832f 1701
7338aefa 1702 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1703 if (--ring->irq_refcount == 0) {
040d2baa 1704 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1705 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1706 else
1707 I915_WRITE_IMR(ring, ~0);
480c8033 1708 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1709 }
7338aefa 1710 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1711}
1712
a19d2933 1713static bool
a4872ba6 1714hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1715{
1716 struct drm_device *dev = ring->dev;
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 unsigned long flags;
1719
7cd512f1 1720 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1721 return false;
1722
59cdb63d 1723 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1724 if (ring->irq_refcount++ == 0) {
a19d2933 1725 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1726 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1727 }
59cdb63d 1728 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1729
1730 return true;
1731}
1732
1733static void
a4872ba6 1734hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1735{
1736 struct drm_device *dev = ring->dev;
1737 struct drm_i915_private *dev_priv = dev->dev_private;
1738 unsigned long flags;
1739
59cdb63d 1740 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1741 if (--ring->irq_refcount == 0) {
a19d2933 1742 I915_WRITE_IMR(ring, ~0);
480c8033 1743 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1744 }
59cdb63d 1745 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1746}
1747
abd58f01 1748static bool
a4872ba6 1749gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1750{
1751 struct drm_device *dev = ring->dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 unsigned long flags;
1754
7cd512f1 1755 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1756 return false;
1757
1758 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1759 if (ring->irq_refcount++ == 0) {
1760 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1761 I915_WRITE_IMR(ring,
1762 ~(ring->irq_enable_mask |
1763 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1764 } else {
1765 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1766 }
1767 POSTING_READ(RING_IMR(ring->mmio_base));
1768 }
1769 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1770
1771 return true;
1772}
1773
1774static void
a4872ba6 1775gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1776{
1777 struct drm_device *dev = ring->dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 unsigned long flags;
1780
1781 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1782 if (--ring->irq_refcount == 0) {
1783 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1784 I915_WRITE_IMR(ring,
1785 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1786 } else {
1787 I915_WRITE_IMR(ring, ~0);
1788 }
1789 POSTING_READ(RING_IMR(ring->mmio_base));
1790 }
1791 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1792}
1793
d1b851fc 1794static int
53fddaf7 1795i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1796 u64 offset, u32 length,
8e004efc 1797 unsigned dispatch_flags)
d1b851fc 1798{
53fddaf7 1799 struct intel_engine_cs *ring = req->ring;
e1f99ce6 1800 int ret;
78501eac 1801
5fb9de1a 1802 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1803 if (ret)
1804 return ret;
1805
78501eac 1806 intel_ring_emit(ring,
65f56876
CW		 1807 MI_BATCH_BUFFER_START |
1808 MI_BATCH_GTT |
8e004efc
JH		 1809 (dispatch_flags & I915_DISPATCH_SECURE ?
1810 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1811 intel_ring_emit(ring, offset);
78501eac
CW		 1812 intel_ring_advance(ring);
1813
d1b851fc
ZN		 1814 return 0;
1815}
1816
b45305fc
DV		 1817/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1818#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1819#define I830_TLB_ENTRIES (2)
1820#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1821static int
53fddaf7 1822i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1823 u64 offset, u32 len,
1824 unsigned dispatch_flags)
62fdfeaf 1825{
53fddaf7 1826 struct intel_engine_cs *ring = req->ring;
c4d69da1 1827 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1828 int ret;
62fdfeaf 1829
5fb9de1a 1830 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1831 if (ret)
1832 return ret;
62fdfeaf 1833
c4d69da1
CW		 1834 /* Evict the invalid PTE TLBs */
1835 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1836 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1837 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1838 intel_ring_emit(ring, cs_offset);
1839 intel_ring_emit(ring, 0xdeadbeef);
1840 intel_ring_emit(ring, MI_NOOP);
1841 intel_ring_advance(ring);
b45305fc 1842
8e004efc 1843 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1844 if (len > I830_BATCH_LIMIT)
1845 return -ENOSPC;
1846
5fb9de1a 1847 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1848 if (ret)
1849 return ret;
c4d69da1
CW		 1850
1851 /* Blit the batch (which has now all relocs applied) to the
1852 * stable batch scratch bo area (so that the CS never
1853 * stumbles over its tlb invalidation bug) ...
1854 */
1855 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1856 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1857 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1858 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1859 intel_ring_emit(ring, 4096);
1860 intel_ring_emit(ring, offset);
c4d69da1 1861
b45305fc 1862 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1863 intel_ring_emit(ring, MI_NOOP);
1864 intel_ring_advance(ring);
b45305fc
DV		 1865
1866 /* ... and execute it. */
c4d69da1 1867 offset = cs_offset;
b45305fc 1868 }
e1f99ce6 1869
9d611c03 1870 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 1871 if (ret)
1872 return ret;
1873
9d611c03 1874 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1875 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1876 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1877 intel_ring_advance(ring);
1878
fb3256da
DV		 1879 return 0;
1880}
1881
1882static int
53fddaf7 1883i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1884 u64 offset, u32 len,
8e004efc 1885 unsigned dispatch_flags)
fb3256da 1886{
53fddaf7 1887 struct intel_engine_cs *ring = req->ring;
fb3256da
DV		 1888 int ret;
1889
5fb9de1a 1890 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1891 if (ret)
1892 return ret;
1893
65f56876 1894 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1895 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1896 0 : MI_BATCH_NON_SECURE));
c4e7a414 1897 intel_ring_advance(ring);
62fdfeaf 1898
62fdfeaf
EA		 1899 return 0;
1900}
1901
7d3fdfff
VS		 1902static void cleanup_phys_status_page(struct intel_engine_cs *ring)
1903{
1904 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1905
1906 if (!dev_priv->status_page_dmah)
1907 return;
1908
1909 drm_pci_free(ring->dev, dev_priv->status_page_dmah);
1910 ring->status_page.page_addr = NULL;
1911}
1912
a4872ba6 1913static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1914{
05394f39 1915 struct drm_i915_gem_object *obj;
62fdfeaf 1916
8187a2b7
ZN		 1917 obj = ring->status_page.obj;
1918 if (obj == NULL)
62fdfeaf 1919 return;
62fdfeaf 1920
9da3da66 1921 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1922 i915_gem_object_ggtt_unpin(obj);
05394f39 1923 drm_gem_object_unreference(&obj->base);
8187a2b7 1924 ring->status_page.obj = NULL;
62fdfeaf
EA		 1925}
1926
a4872ba6 1927static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1928{
7d3fdfff 1929 struct drm_i915_gem_object *obj = ring->status_page.obj;
62fdfeaf 1930
7d3fdfff 1931 if (obj == NULL) {
1f767e02 1932 unsigned flags;
e3efda49 1933 int ret;
e4ffd173 1934
e3efda49
CW		 1935 obj = i915_gem_alloc_object(ring->dev, 4096);
1936 if (obj == NULL) {
1937 DRM_ERROR("Failed to allocate status page\n");
1938 return -ENOMEM;
1939 }
62fdfeaf 1940
e3efda49
CW		 1941 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1942 if (ret)
1943 goto err_unref;
1944
1f767e02
CW		 1945 flags = 0;
1946 if (!HAS_LLC(ring->dev))
1947 /* On g33, we cannot place HWS above 256MiB, so
1948 * restrict its pinning to the low mappable arena.
1949 * Though this restriction is not documented for
1950 * gen4, gen5, or byt, they also behave similarly
1951 * and hang if the HWS is placed at the top of the
1952 * GTT. To generalise, it appears that all !llc
1953 * platforms have issues with us placing the HWS
1954 * above the mappable region (even though we never
1955 * actualy map it).
1956 */
1957 flags |= PIN_MAPPABLE;
1958 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1959 if (ret) {
1960err_unref:
1961 drm_gem_object_unreference(&obj->base);
1962 return ret;
1963 }
1964
1965 ring->status_page.obj = obj;
1966 }
62fdfeaf 1967
f343c5f6 1968 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1969 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1970 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1971
8187a2b7
ZN		 1972 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1973 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1974
1975 return 0;
62fdfeaf
EA		 1976}
1977
a4872ba6 1978static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1979{
1980 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1981
1982 if (!dev_priv->status_page_dmah) {
1983 dev_priv->status_page_dmah =
1984 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1985 if (!dev_priv->status_page_dmah)
1986 return -ENOMEM;
1987 }
1988
6b8294a4
CW		 1989 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1990 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1991
1992 return 0;
1993}
1994
7ba717cf 1995void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1996{
def0c5f6
CW		 1997 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
1998 vunmap(ringbuf->virtual_start);
1999 else
2000 iounmap(ringbuf->virtual_start);
7ba717cf 2001 ringbuf->virtual_start = NULL;
2919d291 2002 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 2003}
2004
def0c5f6
CW		 2005static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2006{
2007 struct sg_page_iter sg_iter;
2008 struct page **pages;
2009 void *addr;
2010 int i;
2011
2012 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2013 if (pages == NULL)
2014 return NULL;
2015
2016 i = 0;
2017 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2018 pages[i++] = sg_page_iter_page(&sg_iter);
2019
2020 addr = vmap(pages, i, 0, PAGE_KERNEL);
2021 drm_free_large(pages);
2022
2023 return addr;
2024}
2025
7ba717cf
TD		 2026int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2027 struct intel_ringbuffer *ringbuf)
2028{
2029 struct drm_i915_private *dev_priv = to_i915(dev);
2030 struct drm_i915_gem_object *obj = ringbuf->obj;
2031 int ret;
2032
def0c5f6
CW		 2033 if (HAS_LLC(dev_priv) && !obj->stolen) {
2034 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2035 if (ret)
2036 return ret;
7ba717cf 2037
def0c5f6
CW		 2038 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2039 if (ret) {
2040 i915_gem_object_ggtt_unpin(obj);
2041 return ret;
2042 }
2043
2044 ringbuf->virtual_start = vmap_obj(obj);
2045 if (ringbuf->virtual_start == NULL) {
2046 i915_gem_object_ggtt_unpin(obj);
2047 return -ENOMEM;
2048 }
2049 } else {
2050 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2051 if (ret)
2052 return ret;
7ba717cf 2053
def0c5f6
CW		 2054 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2055 if (ret) {
2056 i915_gem_object_ggtt_unpin(obj);
2057 return ret;
2058 }
2059
2060 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2061 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2062 if (ringbuf->virtual_start == NULL) {
2063 i915_gem_object_ggtt_unpin(obj);
2064 return -EINVAL;
2065 }
7ba717cf
TD		 2066 }
2067
2068 return 0;
2069}
2070
01101fa7 2071static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2072{
2919d291
OM		 2073 drm_gem_object_unreference(&ringbuf->obj->base);
2074 ringbuf->obj = NULL;
2075}
2076
01101fa7
CW		 2077static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2078 struct intel_ringbuffer *ringbuf)
62fdfeaf 2079{
05394f39 2080 struct drm_i915_gem_object *obj;
62fdfeaf 2081
ebc052e0
CW		 2082 obj = NULL;
2083 if (!HAS_LLC(dev))
93b0a4e0 2084 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2085 if (obj == NULL)
93b0a4e0 2086 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2087 if (obj == NULL)
2088 return -ENOMEM;
8187a2b7 2089
24f3a8cf
AG		 2090 /* mark ring buffers as read-only from GPU side by default */
2091 obj->gt_ro = 1;
2092
93b0a4e0 2093 ringbuf->obj = obj;
e3efda49 2094
7ba717cf 2095 return 0;
e3efda49
CW		 2096}
2097
01101fa7
CW		 2098struct intel_ringbuffer *
2099intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2100{
2101 struct intel_ringbuffer *ring;
2102 int ret;
2103
2104 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2105 if (ring == NULL) {
2106 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2107 engine->name);
01101fa7 2108 return ERR_PTR(-ENOMEM);
608c1a52 2109 }
01101fa7
CW		 2110
2111 ring->ring = engine;
608c1a52 2112 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2113
2114 ring->size = size;
2115 /* Workaround an erratum on the i830 which causes a hang if
2116 * the TAIL pointer points to within the last 2 cachelines
2117 * of the buffer.
2118 */
2119 ring->effective_size = size;
2120 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2121 ring->effective_size -= 2 * CACHELINE_BYTES;
2122
2123 ring->last_retired_head = -1;
2124 intel_ring_update_space(ring);
2125
2126 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2127 if (ret) {
608c1a52
CW		 2128 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2129 engine->name, ret);
2130 list_del(&ring->link);
01101fa7
CW		 2131 kfree(ring);
2132 return ERR_PTR(ret);
2133 }
2134
2135 return ring;
2136}
2137
2138void
2139intel_ringbuffer_free(struct intel_ringbuffer *ring)
2140{
2141 intel_destroy_ringbuffer_obj(ring);
608c1a52 2142 list_del(&ring->link);
01101fa7
CW		 2143 kfree(ring);
2144}
2145
e3efda49 2146static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2147 struct intel_engine_cs *ring)
e3efda49 2148{
bfc882b4 2149 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2150 int ret;
2151
bfc882b4
DV		 2152 WARN_ON(ring->buffer);
2153
e3efda49
CW		 2154 ring->dev = dev;
2155 INIT_LIST_HEAD(&ring->active_list);
2156 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2157 INIT_LIST_HEAD(&ring->execlist_queue);
608c1a52 2158 INIT_LIST_HEAD(&ring->buffers);
06fbca71 2159 i915_gem_batch_pool_init(dev, &ring->batch_pool);
ebc348b2 2160 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2161
2162 init_waitqueue_head(&ring->irq_queue);
2163
01101fa7 2164 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
b0366a54
DG		 2165 if (IS_ERR(ringbuf)) {
2166 ret = PTR_ERR(ringbuf);
2167 goto error;
2168 }
01101fa7
CW		 2169 ring->buffer = ringbuf;
2170
e3efda49
CW		 2171 if (I915_NEED_GFX_HWS(dev)) {
2172 ret = init_status_page(ring);
2173 if (ret)
8ee14975 2174 goto error;
e3efda49 2175 } else {
7d3fdfff 2176 WARN_ON(ring->id != RCS);
e3efda49
CW		 2177 ret = init_phys_status_page(ring);
2178 if (ret)
8ee14975 2179 goto error;
e3efda49
CW		 2180 }
2181
bfc882b4
DV		 2182 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2183 if (ret) {
2184 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2185 ring->name, ret);
2186 intel_destroy_ringbuffer_obj(ringbuf);
2187 goto error;
e3efda49 2188 }
62fdfeaf 2189
44e895a8
BV		 2190 ret = i915_cmd_parser_init_ring(ring);
2191 if (ret)
8ee14975
OM		 2192 goto error;
2193
8ee14975 2194 return 0;
351e3db2 2195
8ee14975 2196error:
b0366a54 2197 intel_cleanup_ring_buffer(ring);
8ee14975 2198 return ret;
62fdfeaf
EA		 2199}
2200
a4872ba6 2201void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2202{
6402c330 2203 struct drm_i915_private *dev_priv;
33626e6a 2204
93b0a4e0 2205 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2206 return;
2207
6402c330 2208 dev_priv = to_i915(ring->dev);
6402c330 2209
b0366a54
DG		 2210 if (ring->buffer) {
2211 intel_stop_ring_buffer(ring);
2212 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2213
b0366a54
DG		 2214 intel_unpin_ringbuffer_obj(ring->buffer);
2215 intel_ringbuffer_free(ring->buffer);
2216 ring->buffer = NULL;
2217 }
78501eac 2218
8d19215b
ZN		 2219 if (ring->cleanup)
2220 ring->cleanup(ring);
2221
7d3fdfff
VS		 2222 if (I915_NEED_GFX_HWS(ring->dev)) {
2223 cleanup_status_page(ring);
2224 } else {
2225 WARN_ON(ring->id != RCS);
2226 cleanup_phys_status_page(ring);
2227 }
44e895a8
BV		 2228
2229 i915_cmd_parser_fini_ring(ring);
06fbca71 2230 i915_gem_batch_pool_fini(&ring->batch_pool);
b0366a54 2231 ring->dev = NULL;
62fdfeaf
EA		 2232}
2233
595e1eeb 2234static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2235{
93b0a4e0 2236 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2237 struct drm_i915_gem_request *request;
b4716185
CW		 2238 unsigned space;
2239 int ret;
a71d8d94 2240
ebd0fd4b
DG		 2241 if (intel_ring_space(ringbuf) >= n)
2242 return 0;
a71d8d94 2243
79bbcc29
JH		 2244 /* The whole point of reserving space is to not wait! */
2245 WARN_ON(ringbuf->reserved_in_use);
2246
a71d8d94 2247 list_for_each_entry(request, &ring->request_list, list) {
b4716185
CW		 2248 space = __intel_ring_space(request->postfix, ringbuf->tail,
2249 ringbuf->size);
2250 if (space >= n)
a71d8d94 2251 break;
a71d8d94
CW		 2252 }
2253
595e1eeb 2254 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2255 return -ENOSPC;
2256
a4b3a571 2257 ret = i915_wait_request(request);
a71d8d94
CW		 2258 if (ret)
2259 return ret;
2260
b4716185 2261 ringbuf->space = space;
a71d8d94
CW		 2262 return 0;
2263}
2264
79bbcc29 2265static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2266{
2267 uint32_t __iomem *virt;
93b0a4e0 2268 int rem = ringbuf->size - ringbuf->tail;
3e960501 2269
93b0a4e0 2270 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2271 rem /= 4;
2272 while (rem--)
2273 iowrite32(MI_NOOP, virt++);
2274
93b0a4e0 2275 ringbuf->tail = 0;
ebd0fd4b 2276 intel_ring_update_space(ringbuf);
3e960501
CW		 2277}
2278
a4872ba6 2279int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2280{
a4b3a571 2281 struct drm_i915_gem_request *req;
3e960501 2282
3e960501
CW		 2283 /* Wait upon the last request to be completed */
2284 if (list_empty(&ring->request_list))
2285 return 0;
2286
a4b3a571 2287 req = list_entry(ring->request_list.prev,
b4716185
CW		 2288 struct drm_i915_gem_request,
2289 list);
2290
2291 /* Make sure we do not trigger any retires */
2292 return __i915_wait_request(req,
2293 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2294 to_i915(ring->dev)->mm.interruptible,
2295 NULL, NULL);
3e960501
CW		 2296}
2297
6689cb2b 2298int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2299{
6689cb2b 2300 request->ringbuf = request->ring->buffer;
9eba5d4a 2301 return 0;
9d773091
CW		 2302}
2303
ccd98fe4
JH		 2304int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2305{
2306 /*
2307 * The first call merely notes the reserve request and is common for
2308 * all back ends. The subsequent localised _begin() call actually
2309 * ensures that the reservation is available. Without the begin, if
2310 * the request creator immediately submitted the request without
2311 * adding any commands to it then there might not actually be
2312 * sufficient room for the submission commands.
2313 */
2314 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2315
2316 return intel_ring_begin(request, 0);
2317}
2318
29b1b415
JH		 2319void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2320{
ccd98fe4 2321 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2322 WARN_ON(ringbuf->reserved_in_use);
2323
2324 ringbuf->reserved_size = size;
29b1b415
JH		 2325}
2326
2327void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2328{
2329 WARN_ON(ringbuf->reserved_in_use);
2330
2331 ringbuf->reserved_size = 0;
2332 ringbuf->reserved_in_use = false;
2333}
2334
2335void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2336{
2337 WARN_ON(ringbuf->reserved_in_use);
2338
2339 ringbuf->reserved_in_use = true;
2340 ringbuf->reserved_tail = ringbuf->tail;
2341}
2342
2343void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2344{
2345 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2346 if (ringbuf->tail > ringbuf->reserved_tail) {
2347 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2348 "request reserved size too small: %d vs %d!\n",
2349 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2350 } else {
2351 /*
2352 * The ring was wrapped while the reserved space was in use.
2353 * That means that some unknown amount of the ring tail was
2354 * no-op filled and skipped. Thus simply adding the ring size
2355 * to the tail and doing the above space check will not work.
2356 * Rather than attempt to track how much tail was skipped,
2357 * it is much simpler to say that also skipping the sanity
2358 * check every once in a while is not a big issue.
2359 */
2360 }
29b1b415
JH		 2361
2362 ringbuf->reserved_size = 0;
2363 ringbuf->reserved_in_use = false;
2364}
2365
2366static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
cbcc80df 2367{
93b0a4e0 2368 struct intel_ringbuffer *ringbuf = ring->buffer;
79bbcc29
JH		 2369 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2370 int remain_actual = ringbuf->size - ringbuf->tail;
2371 int ret, total_bytes, wait_bytes = 0;
2372 bool need_wrap = false;
29b1b415 2373
79bbcc29
JH		 2374 if (ringbuf->reserved_in_use)
2375 total_bytes = bytes;
2376 else
2377 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2378
79bbcc29
JH		 2379 if (unlikely(bytes > remain_usable)) {
2380 /*
2381 * Not enough space for the basic request. So need to flush
2382 * out the remainder and then wait for base + reserved.
2383 */
2384 wait_bytes = remain_actual + total_bytes;
2385 need_wrap = true;
2386 } else {
2387 if (unlikely(total_bytes > remain_usable)) {
2388 /*
2389 * The base request will fit but the reserved space
2390 * falls off the end. So only need to to wait for the
2391 * reserved size after flushing out the remainder.
2392 */
2393 wait_bytes = remain_actual + ringbuf->reserved_size;
2394 need_wrap = true;
2395 } else if (total_bytes > ringbuf->space) {
2396 /* No wrapping required, just waiting. */
2397 wait_bytes = total_bytes;
29b1b415 2398 }
cbcc80df
MK		 2399 }
2400
79bbcc29
JH		 2401 if (wait_bytes) {
2402 ret = ring_wait_for_space(ring, wait_bytes);
cbcc80df
MK		 2403 if (unlikely(ret))
2404 return ret;
79bbcc29
JH		 2405
2406 if (need_wrap)
2407 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2408 }
2409
cbcc80df
MK		 2410 return 0;
2411}
2412
5fb9de1a 2413int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2414 int num_dwords)
8187a2b7 2415{
5fb9de1a
JH		 2416 struct intel_engine_cs *ring;
2417 struct drm_i915_private *dev_priv;
e1f99ce6 2418 int ret;
78501eac 2419
5fb9de1a
JH		 2420 WARN_ON(req == NULL);
2421 ring = req->ring;
2422 dev_priv = ring->dev->dev_private;
2423
33196ded
DV		 2424 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2425 dev_priv->mm.interruptible);
de2b9985
DV		 2426 if (ret)
2427 return ret;
21dd3734 2428
304d695c
CW		 2429 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2430 if (ret)
2431 return ret;
2432
ee1b1e5e 2433 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2434 return 0;
8187a2b7 2435}
78501eac 2436
753b1ad4 2437/* Align the ring tail to a cacheline boundary */
bba09b12 2438int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2439{
bba09b12 2440 struct intel_engine_cs *ring = req->ring;
ee1b1e5e 2441 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2442 int ret;
2443
2444 if (num_dwords == 0)
2445 return 0;
2446
18393f63 2447 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2448 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2449 if (ret)
2450 return ret;
2451
2452 while (num_dwords--)
2453 intel_ring_emit(ring, MI_NOOP);
2454
2455 intel_ring_advance(ring);
2456
2457 return 0;
2458}
2459
a4872ba6 2460void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2461{
3b2cc8ab
OM		 2462 struct drm_device *dev = ring->dev;
2463 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2464
3b2cc8ab 2465 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2466 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2467 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2468 if (HAS_VEBOX(dev))
5020150b 2469 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2470 }
d97ed339 2471
f7e98ad4 2472 ring->set_seqno(ring, seqno);
92cab734 2473 ring->hangcheck.seqno = seqno;
8187a2b7 2474}
62fdfeaf 2475
a4872ba6 2476static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2477 u32 value)
881f47b6 2478{
4640c4ff 2479 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2480
2481 /* Every tail move must follow the sequence below */
12f55818
CW		 2482
2483 /* Disable notification that the ring is IDLE. The GT
2484 * will then assume that it is busy and bring it out of rc6.
2485 */
0206e353 2486 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2487 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2488
2489 /* Clear the context id. Here be magic! */
2490 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2491
12f55818 2492 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2493 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2494 GEN6_BSD_SLEEP_INDICATOR) == 0,
2495 50))
2496 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2497
12f55818 2498 /* Now that the ring is fully powered up, update the tail */
0206e353 2499 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2500 POSTING_READ(RING_TAIL(ring->mmio_base));
2501
2502 /* Let the ring send IDLE messages to the GT again,
2503 * and so let it sleep to conserve power when idle.
2504 */
0206e353 2505 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2506 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2507}
2508
a84c3ae1 2509static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2510 u32 invalidate, u32 flush)
881f47b6 2511{
a84c3ae1 2512 struct intel_engine_cs *ring = req->ring;
71a77e07 2513 uint32_t cmd;
b72f3acb
CW		 2514 int ret;
2515
5fb9de1a 2516 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2517 if (ret)
2518 return ret;
2519
71a77e07 2520 cmd = MI_FLUSH_DW;
075b3bba
BW		 2521 if (INTEL_INFO(ring->dev)->gen >= 8)
2522 cmd += 1;
f0a1fb10
CW		 2523
2524 /* We always require a command barrier so that subsequent
2525 * commands, such as breadcrumb interrupts, are strictly ordered
2526 * wrt the contents of the write cache being flushed to memory
2527 * (and thus being coherent from the CPU).
2528 */
2529 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2530
9a289771
JB		 2531 /*
2532 * Bspec vol 1c.5 - video engine command streamer:
2533 * "If ENABLED, all TLBs will be invalidated once the flush
2534 * operation is complete. This bit is only valid when the
2535 * Post-Sync Operation field is a value of 1h or 3h."
2536 */
71a77e07 2537 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2538 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2539
71a77e07 2540 intel_ring_emit(ring, cmd);
9a289771 2541 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2542 if (INTEL_INFO(ring->dev)->gen >= 8) {
2543 intel_ring_emit(ring, 0); /* upper addr */
2544 intel_ring_emit(ring, 0); /* value */
2545 } else {
2546 intel_ring_emit(ring, 0);
2547 intel_ring_emit(ring, MI_NOOP);
2548 }
b72f3acb
CW		 2549 intel_ring_advance(ring);
2550 return 0;
881f47b6
XH		 2551}
2552
1c7a0623 2553static int
53fddaf7 2554gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2555 u64 offset, u32 len,
8e004efc 2556 unsigned dispatch_flags)
1c7a0623 2557{
53fddaf7 2558 struct intel_engine_cs *ring = req->ring;
8e004efc
JH		 2559 bool ppgtt = USES_PPGTT(ring->dev) &&
2560 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2561 int ret;
2562
5fb9de1a 2563 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2564 if (ret)
2565 return ret;
2566
2567 /* FIXME(BDW): Address space and security selectors. */
919032ec
AJ		 2568 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2569 (dispatch_flags & I915_DISPATCH_RS ?
2570 MI_BATCH_RESOURCE_STREAMER : 0));
9bcb144c
BW		 2571 intel_ring_emit(ring, lower_32_bits(offset));
2572 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2573 intel_ring_emit(ring, MI_NOOP);
2574 intel_ring_advance(ring);
2575
2576 return 0;
2577}
2578
d7d4eedd 2579static int
53fddaf7 2580hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2581 u64 offset, u32 len,
2582 unsigned dispatch_flags)
d7d4eedd 2583{
53fddaf7 2584 struct intel_engine_cs *ring = req->ring;
d7d4eedd
CW		 2585 int ret;
2586
5fb9de1a 2587 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2588 if (ret)
2589 return ret;
2590
2591 intel_ring_emit(ring,
77072258 2592 MI_BATCH_BUFFER_START |
8e004efc 2593 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2594 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2595 (dispatch_flags & I915_DISPATCH_RS ?
2596 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd
CW		 2597 /* bit0-7 is the length on GEN6+ */
2598 intel_ring_emit(ring, offset);
2599 intel_ring_advance(ring);
2600
2601 return 0;
2602}
2603
881f47b6 2604static int
53fddaf7 2605gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2606 u64 offset, u32 len,
8e004efc 2607 unsigned dispatch_flags)
881f47b6 2608{
53fddaf7 2609 struct intel_engine_cs *ring = req->ring;
0206e353 2610 int ret;
ab6f8e32 2611
5fb9de1a 2612 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2613 if (ret)
2614 return ret;
e1f99ce6 2615
d7d4eedd
CW		 2616 intel_ring_emit(ring,
2617 MI_BATCH_BUFFER_START |
8e004efc
JH		 2618 (dispatch_flags & I915_DISPATCH_SECURE ?
2619 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2620 /* bit0-7 is the length on GEN6+ */
2621 intel_ring_emit(ring, offset);
2622 intel_ring_advance(ring);
ab6f8e32 2623
0206e353 2624 return 0;
881f47b6
XH		 2625}
2626
549f7365
CW		 2627/* Blitter support (SandyBridge+) */
2628
a84c3ae1 2629static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2630 u32 invalidate, u32 flush)
8d19215b 2631{
a84c3ae1 2632 struct intel_engine_cs *ring = req->ring;
fd3da6c9 2633 struct drm_device *dev = ring->dev;
71a77e07 2634 uint32_t cmd;
b72f3acb
CW		 2635 int ret;
2636
5fb9de1a 2637 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2638 if (ret)
2639 return ret;
2640
71a77e07 2641 cmd = MI_FLUSH_DW;
dbef0f15 2642 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2643 cmd += 1;
f0a1fb10
CW		 2644
2645 /* We always require a command barrier so that subsequent
2646 * commands, such as breadcrumb interrupts, are strictly ordered
2647 * wrt the contents of the write cache being flushed to memory
2648 * (and thus being coherent from the CPU).
2649 */
2650 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2651
9a289771
JB		 2652 /*
2653 * Bspec vol 1c.3 - blitter engine command streamer:
2654 * "If ENABLED, all TLBs will be invalidated once the flush
2655 * operation is complete. This bit is only valid when the
2656 * Post-Sync Operation field is a value of 1h or 3h."
2657 */
71a77e07 2658 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2659 cmd |= MI_INVALIDATE_TLB;
71a77e07 2660 intel_ring_emit(ring, cmd);
9a289771 2661 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2662 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2663 intel_ring_emit(ring, 0); /* upper addr */
2664 intel_ring_emit(ring, 0); /* value */
2665 } else {
2666 intel_ring_emit(ring, 0);
2667 intel_ring_emit(ring, MI_NOOP);
2668 }
b72f3acb 2669 intel_ring_advance(ring);
fd3da6c9 2670
b72f3acb 2671 return 0;
8d19215b
ZN		 2672}
2673
5c1143bb
XH		 2674int intel_init_render_ring_buffer(struct drm_device *dev)
2675{
4640c4ff 2676 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2677 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2678 struct drm_i915_gem_object *obj;
2679 int ret;
5c1143bb 2680
59465b5f
DV		 2681 ring->name = "render ring";
2682 ring->id = RCS;
2683 ring->mmio_base = RENDER_RING_BASE;
2684
707d9cf9 2685 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2686 if (i915_semaphore_is_enabled(dev)) {
2687 obj = i915_gem_alloc_object(dev, 4096);
2688 if (obj == NULL) {
2689 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2690 i915.semaphores = 0;
2691 } else {
2692 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2693 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2694 if (ret != 0) {
2695 drm_gem_object_unreference(&obj->base);
2696 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2697 i915.semaphores = 0;
2698 } else
2699 dev_priv->semaphore_obj = obj;
2700 }
2701 }
7225342a 2702
8f0e2b9d 2703 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2704 ring->add_request = gen6_add_request;
2705 ring->flush = gen8_render_ring_flush;
2706 ring->irq_get = gen8_ring_get_irq;
2707 ring->irq_put = gen8_ring_put_irq;
2708 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2709 ring->get_seqno = gen6_ring_get_seqno;
2710 ring->set_seqno = ring_set_seqno;
2711 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2712 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2713 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2714 ring->semaphore.signal = gen8_rcs_signal;
2715 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2716 }
2717 } else if (INTEL_INFO(dev)->gen >= 6) {
4f91fc6d 2718 ring->init_context = intel_rcs_ctx_init;
1ec14ad3 2719 ring->add_request = gen6_add_request;
4772eaeb 2720 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2721 if (INTEL_INFO(dev)->gen == 6)
b3111509 2722 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2723 ring->irq_get = gen6_ring_get_irq;
2724 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2725 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2726 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2727 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2728 if (i915_semaphore_is_enabled(dev)) {
2729 ring->semaphore.sync_to = gen6_ring_sync;
2730 ring->semaphore.signal = gen6_signal;
2731 /*
2732 * The current semaphore is only applied on pre-gen8
2733 * platform. And there is no VCS2 ring on the pre-gen8
2734 * platform. So the semaphore between RCS and VCS2 is
2735 * initialized as INVALID. Gen8 will initialize the
2736 * sema between VCS2 and RCS later.
2737 */
2738 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2739 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2740 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2741 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2742 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2743 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2744 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2745 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2746 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2747 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2748 }
c6df541c
CW		 2749 } else if (IS_GEN5(dev)) {
2750 ring->add_request = pc_render_add_request;
46f0f8d1 2751 ring->flush = gen4_render_ring_flush;
c6df541c 2752 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2753 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2754 ring->irq_get = gen5_ring_get_irq;
2755 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2756 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2757 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2758 } else {
8620a3a9 2759 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2760 if (INTEL_INFO(dev)->gen < 4)
2761 ring->flush = gen2_render_ring_flush;
2762 else
2763 ring->flush = gen4_render_ring_flush;
59465b5f 2764 ring->get_seqno = ring_get_seqno;
b70ec5bf 2765 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2766 if (IS_GEN2(dev)) {
2767 ring->irq_get = i8xx_ring_get_irq;
2768 ring->irq_put = i8xx_ring_put_irq;
2769 } else {
2770 ring->irq_get = i9xx_ring_get_irq;
2771 ring->irq_put = i9xx_ring_put_irq;
2772 }
e3670319 2773 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2774 }
59465b5f 2775 ring->write_tail = ring_write_tail;
707d9cf9 2776
d7d4eedd
CW		 2777 if (IS_HASWELL(dev))
2778 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2779 else if (IS_GEN8(dev))
2780 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2781 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2782 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2783 else if (INTEL_INFO(dev)->gen >= 4)
2784 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2785 else if (IS_I830(dev) || IS_845G(dev))
2786 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2787 else
2788 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2789 ring->init_hw = init_render_ring;
59465b5f
DV		 2790 ring->cleanup = render_ring_cleanup;
2791
b45305fc
DV		 2792 /* Workaround batchbuffer to combat CS tlb bug. */
2793 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2794 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2795 if (obj == NULL) {
2796 DRM_ERROR("Failed to allocate batch bo\n");
2797 return -ENOMEM;
2798 }
2799
be1fa129 2800 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2801 if (ret != 0) {
2802 drm_gem_object_unreference(&obj->base);
2803 DRM_ERROR("Failed to ping batch bo\n");
2804 return ret;
2805 }
2806
0d1aacac
CW		 2807 ring->scratch.obj = obj;
2808 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2809 }
2810
99be1dfe
DV		 2811 ret = intel_init_ring_buffer(dev, ring);
2812 if (ret)
2813 return ret;
2814
2815 if (INTEL_INFO(dev)->gen >= 5) {
2816 ret = intel_init_pipe_control(ring);
2817 if (ret)
2818 return ret;
2819 }
2820
2821 return 0;
5c1143bb
XH		 2822}
2823
2824int intel_init_bsd_ring_buffer(struct drm_device *dev)
2825{
4640c4ff 2826 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2827 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2828
58fa3835
DV		 2829 ring->name = "bsd ring";
2830 ring->id = VCS;
2831
0fd2c201 2832 ring->write_tail = ring_write_tail;
780f18c8 2833 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2834 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2835 /* gen6 bsd needs a special wa for tail updates */
2836 if (IS_GEN6(dev))
2837 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2838 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2839 ring->add_request = gen6_add_request;
2840 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2841 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2842 if (INTEL_INFO(dev)->gen >= 8) {
2843 ring->irq_enable_mask =
2844 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2845 ring->irq_get = gen8_ring_get_irq;
2846 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2847 ring->dispatch_execbuffer =
2848 gen8_ring_dispatch_execbuffer;
707d9cf9 2849 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2850 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2851 ring->semaphore.signal = gen8_xcs_signal;
2852 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2853 }
abd58f01
BW		 2854 } else {
2855 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2856 ring->irq_get = gen6_ring_get_irq;
2857 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2858 ring->dispatch_execbuffer =
2859 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2860 if (i915_semaphore_is_enabled(dev)) {
2861 ring->semaphore.sync_to = gen6_ring_sync;
2862 ring->semaphore.signal = gen6_signal;
2863 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2864 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2865 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2866 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2867 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2868 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2869 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2870 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2871 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2872 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2873 }
abd58f01 2874 }
58fa3835
DV		 2875 } else {
2876 ring->mmio_base = BSD_RING_BASE;
58fa3835 2877 ring->flush = bsd_ring_flush;
8620a3a9 2878 ring->add_request = i9xx_add_request;
58fa3835 2879 ring->get_seqno = ring_get_seqno;
b70ec5bf 2880 ring->set_seqno = ring_set_seqno;
e48d8634 2881 if (IS_GEN5(dev)) {
cc609d5d 2882 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2883 ring->irq_get = gen5_ring_get_irq;
2884 ring->irq_put = gen5_ring_put_irq;
2885 } else {
e3670319 2886 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2887 ring->irq_get = i9xx_ring_get_irq;
2888 ring->irq_put = i9xx_ring_put_irq;
2889 }
fb3256da 2890 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2891 }
ecfe00d8 2892 ring->init_hw = init_ring_common;
58fa3835 2893
1ec14ad3 2894 return intel_init_ring_buffer(dev, ring);
5c1143bb 2895}
549f7365 2896
845f74a7 2897/**
62659920 2898 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2899 */
2900int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2901{
2902 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2903 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2904
f7b64236 2905 ring->name = "bsd2 ring";
845f74a7
ZY		 2906 ring->id = VCS2;
2907
2908 ring->write_tail = ring_write_tail;
2909 ring->mmio_base = GEN8_BSD2_RING_BASE;
2910 ring->flush = gen6_bsd_ring_flush;
2911 ring->add_request = gen6_add_request;
2912 ring->get_seqno = gen6_ring_get_seqno;
2913 ring->set_seqno = ring_set_seqno;
2914 ring->irq_enable_mask =
2915 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2916 ring->irq_get = gen8_ring_get_irq;
2917 ring->irq_put = gen8_ring_put_irq;
2918 ring->dispatch_execbuffer =
2919 gen8_ring_dispatch_execbuffer;
3e78998a 2920 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2921 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2922 ring->semaphore.signal = gen8_xcs_signal;
2923 GEN8_RING_SEMAPHORE_INIT;
2924 }
ecfe00d8 2925 ring->init_hw = init_ring_common;
845f74a7
ZY		 2926
2927 return intel_init_ring_buffer(dev, ring);
2928}
2929
549f7365
CW		 2930int intel_init_blt_ring_buffer(struct drm_device *dev)
2931{
4640c4ff 2932 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2933 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2934
3535d9dd
DV		 2935 ring->name = "blitter ring";
2936 ring->id = BCS;
2937
2938 ring->mmio_base = BLT_RING_BASE;
2939 ring->write_tail = ring_write_tail;
ea251324 2940 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2941 ring->add_request = gen6_add_request;
2942 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2943 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2944 if (INTEL_INFO(dev)->gen >= 8) {
2945 ring->irq_enable_mask =
2946 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2947 ring->irq_get = gen8_ring_get_irq;
2948 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2949 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2950 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2951 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2952 ring->semaphore.signal = gen8_xcs_signal;
2953 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2954 }
abd58f01
BW		 2955 } else {
2956 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2957 ring->irq_get = gen6_ring_get_irq;
2958 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2959 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2960 if (i915_semaphore_is_enabled(dev)) {
2961 ring->semaphore.signal = gen6_signal;
2962 ring->semaphore.sync_to = gen6_ring_sync;
2963 /*
2964 * The current semaphore is only applied on pre-gen8
2965 * platform. And there is no VCS2 ring on the pre-gen8
2966 * platform. So the semaphore between BCS and VCS2 is
2967 * initialized as INVALID. Gen8 will initialize the
2968 * sema between BCS and VCS2 later.
2969 */
2970 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2971 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2972 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2973 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2974 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2975 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2976 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2977 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2978 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2979 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2980 }
abd58f01 2981 }
ecfe00d8 2982 ring->init_hw = init_ring_common;
549f7365 2983
1ec14ad3 2984 return intel_init_ring_buffer(dev, ring);
549f7365 2985}
a7b9761d 2986
9a8a2213
BW		 2987int intel_init_vebox_ring_buffer(struct drm_device *dev)
2988{
4640c4ff 2989 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2990 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2991
2992 ring->name = "video enhancement ring";
2993 ring->id = VECS;
2994
2995 ring->mmio_base = VEBOX_RING_BASE;
2996 ring->write_tail = ring_write_tail;
2997 ring->flush = gen6_ring_flush;
2998 ring->add_request = gen6_add_request;
2999 ring->get_seqno = gen6_ring_get_seqno;
3000 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 3001
3002 if (INTEL_INFO(dev)->gen >= 8) {
3003 ring->irq_enable_mask =
40c499f9 3004 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 3005 ring->irq_get = gen8_ring_get_irq;
3006 ring->irq_put = gen8_ring_put_irq;
1c7a0623 3007 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 3008 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 3009 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 3010 ring->semaphore.signal = gen8_xcs_signal;
3011 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 3012 }
abd58f01
BW		 3013 } else {
3014 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3015 ring->irq_get = hsw_vebox_get_irq;
3016 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 3017 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 3018 if (i915_semaphore_is_enabled(dev)) {
3019 ring->semaphore.sync_to = gen6_ring_sync;
3020 ring->semaphore.signal = gen6_signal;
3021 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3022 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3023 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3024 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3025 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3026 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3027 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3028 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3029 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3030 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3031 }
abd58f01 3032 }
ecfe00d8 3033 ring->init_hw = init_ring_common;
9a8a2213
BW		 3034
3035 return intel_init_ring_buffer(dev, ring);
3036}
3037
a7b9761d 3038int
4866d729 3039intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3040{
4866d729 3041 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 3042 int ret;
3043
3044 if (!ring->gpu_caches_dirty)
3045 return 0;
3046
a84c3ae1 3047 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3048 if (ret)
3049 return ret;
3050
a84c3ae1 3051 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3052
3053 ring->gpu_caches_dirty = false;
3054 return 0;
3055}
3056
3057int
2f20055d 3058intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3059{
2f20055d 3060 struct intel_engine_cs *ring = req->ring;
a7b9761d
CW		 3061 uint32_t flush_domains;
3062 int ret;
3063
3064 flush_domains = 0;
3065 if (ring->gpu_caches_dirty)
3066 flush_domains = I915_GEM_GPU_DOMAINS;
3067
a84c3ae1 3068 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3069 if (ret)
3070 return ret;
3071
a84c3ae1 3072 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3073
3074 ring->gpu_caches_dirty = false;
3075 return 0;
3076}
e3efda49
CW		 3077
3078void
a4872ba6 3079intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 3080{
3081 int ret;
3082
3083 if (!intel_ring_initialized(ring))
3084 return;
3085
3086 ret = intel_ring_idle(ring);
3087 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3088 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3089 ring->name, ret);
3090
3091 stop_ring(ring);
3092}
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