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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
8d315287 JB |
36 | /* |
37 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
38 | * over cache flushing. | |
39 | */ | |
40 | struct pipe_control { | |
41 | struct drm_i915_gem_object *obj; | |
42 | volatile u32 *cpu_page; | |
43 | u32 gtt_offset; | |
44 | }; | |
45 | ||
c7dca47b CW |
46 | static inline int ring_space(struct intel_ring_buffer *ring) |
47 | { | |
633cf8f5 | 48 | int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE); |
c7dca47b CW |
49 | if (space < 0) |
50 | space += ring->size; | |
51 | return space; | |
52 | } | |
53 | ||
b72f3acb | 54 | static int |
46f0f8d1 CW |
55 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
56 | u32 invalidate_domains, | |
57 | u32 flush_domains) | |
58 | { | |
59 | u32 cmd; | |
60 | int ret; | |
61 | ||
62 | cmd = MI_FLUSH; | |
31b14c9f | 63 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
64 | cmd |= MI_NO_WRITE_FLUSH; |
65 | ||
66 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
67 | cmd |= MI_READ_FLUSH; | |
68 | ||
69 | ret = intel_ring_begin(ring, 2); | |
70 | if (ret) | |
71 | return ret; | |
72 | ||
73 | intel_ring_emit(ring, cmd); | |
74 | intel_ring_emit(ring, MI_NOOP); | |
75 | intel_ring_advance(ring); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int | |
81 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
82 | u32 invalidate_domains, | |
83 | u32 flush_domains) | |
62fdfeaf | 84 | { |
78501eac | 85 | struct drm_device *dev = ring->dev; |
6f392d54 | 86 | u32 cmd; |
b72f3acb | 87 | int ret; |
6f392d54 | 88 | |
36d527de CW |
89 | /* |
90 | * read/write caches: | |
91 | * | |
92 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
93 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
94 | * also flushed at 2d versus 3d pipeline switches. | |
95 | * | |
96 | * read-only caches: | |
97 | * | |
98 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
99 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
100 | * | |
101 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
102 | * | |
103 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
104 | * invalidated when MI_EXE_FLUSH is set. | |
105 | * | |
106 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
107 | * invalidated with every MI_FLUSH. | |
108 | * | |
109 | * TLBs: | |
110 | * | |
111 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
112 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
113 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
114 | * are flushed at any MI_FLUSH. | |
115 | */ | |
116 | ||
117 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 118 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 119 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
120 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
121 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 122 | |
36d527de CW |
123 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
124 | (IS_G4X(dev) || IS_GEN5(dev))) | |
125 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 126 | |
36d527de CW |
127 | ret = intel_ring_begin(ring, 2); |
128 | if (ret) | |
129 | return ret; | |
b72f3acb | 130 | |
36d527de CW |
131 | intel_ring_emit(ring, cmd); |
132 | intel_ring_emit(ring, MI_NOOP); | |
133 | intel_ring_advance(ring); | |
b72f3acb CW |
134 | |
135 | return 0; | |
8187a2b7 ZN |
136 | } |
137 | ||
8d315287 JB |
138 | /** |
139 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
140 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
141 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
142 | * | |
143 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
144 | * produced by non-pipelined state commands), software needs to first | |
145 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
146 | * 0. | |
147 | * | |
148 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
149 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
150 | * | |
151 | * And the workaround for these two requires this workaround first: | |
152 | * | |
153 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
154 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
155 | * flushes. | |
156 | * | |
157 | * And this last workaround is tricky because of the requirements on | |
158 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
159 | * volume 2 part 1: | |
160 | * | |
161 | * "1 of the following must also be set: | |
162 | * - Render Target Cache Flush Enable ([12] of DW1) | |
163 | * - Depth Cache Flush Enable ([0] of DW1) | |
164 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
165 | * - Depth Stall ([13] of DW1) | |
166 | * - Post-Sync Operation ([13] of DW1) | |
167 | * - Notify Enable ([8] of DW1)" | |
168 | * | |
169 | * The cache flushes require the workaround flush that triggered this | |
170 | * one, so we can't use it. Depth stall would trigger the same. | |
171 | * Post-sync nonzero is what triggered this second workaround, so we | |
172 | * can't use that one either. Notify enable is IRQs, which aren't | |
173 | * really our business. That leaves only stall at scoreboard. | |
174 | */ | |
175 | static int | |
176 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
177 | { | |
178 | struct pipe_control *pc = ring->private; | |
179 | u32 scratch_addr = pc->gtt_offset + 128; | |
180 | int ret; | |
181 | ||
182 | ||
183 | ret = intel_ring_begin(ring, 6); | |
184 | if (ret) | |
185 | return ret; | |
186 | ||
187 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
188 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
189 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
190 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
191 | intel_ring_emit(ring, 0); /* low dword */ | |
192 | intel_ring_emit(ring, 0); /* high dword */ | |
193 | intel_ring_emit(ring, MI_NOOP); | |
194 | intel_ring_advance(ring); | |
195 | ||
196 | ret = intel_ring_begin(ring, 6); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
201 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
202 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
203 | intel_ring_emit(ring, 0); | |
204 | intel_ring_emit(ring, 0); | |
205 | intel_ring_emit(ring, MI_NOOP); | |
206 | intel_ring_advance(ring); | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
211 | static int | |
212 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
213 | u32 invalidate_domains, u32 flush_domains) | |
214 | { | |
215 | u32 flags = 0; | |
216 | struct pipe_control *pc = ring->private; | |
217 | u32 scratch_addr = pc->gtt_offset + 128; | |
218 | int ret; | |
219 | ||
b3111509 PZ |
220 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
221 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
8d315287 JB |
225 | /* Just flush everything. Experiments have shown that reducing the |
226 | * number of bits based on the write domains has little performance | |
227 | * impact. | |
228 | */ | |
7d54a904 CW |
229 | if (flush_domains) { |
230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
231 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
232 | /* | |
233 | * Ensure that any following seqno writes only happen | |
234 | * when the render cache is indeed flushed. | |
235 | */ | |
97f209bc | 236 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
237 | } |
238 | if (invalidate_domains) { | |
239 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
240 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
241 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
242 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
243 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
244 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
245 | /* | |
246 | * TLB invalidate requires a post-sync write. | |
247 | */ | |
3ac78313 | 248 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 249 | } |
8d315287 | 250 | |
6c6cf5aa | 251 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
252 | if (ret) |
253 | return ret; | |
254 | ||
6c6cf5aa | 255 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
256 | intel_ring_emit(ring, flags); |
257 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 258 | intel_ring_emit(ring, 0); |
8d315287 JB |
259 | intel_ring_advance(ring); |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
f3987631 PZ |
264 | static int |
265 | gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring) | |
266 | { | |
267 | int ret; | |
268 | ||
269 | ret = intel_ring_begin(ring, 4); | |
270 | if (ret) | |
271 | return ret; | |
272 | ||
273 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
274 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
275 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
276 | intel_ring_emit(ring, 0); | |
277 | intel_ring_emit(ring, 0); | |
278 | intel_ring_advance(ring); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
4772eaeb PZ |
283 | static int |
284 | gen7_render_ring_flush(struct intel_ring_buffer *ring, | |
285 | u32 invalidate_domains, u32 flush_domains) | |
286 | { | |
287 | u32 flags = 0; | |
288 | struct pipe_control *pc = ring->private; | |
289 | u32 scratch_addr = pc->gtt_offset + 128; | |
290 | int ret; | |
291 | ||
f3987631 PZ |
292 | /* |
293 | * Ensure that any following seqno writes only happen when the render | |
294 | * cache is indeed flushed. | |
295 | * | |
296 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
297 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
298 | * don't try to be clever and just set it unconditionally. | |
299 | */ | |
300 | flags |= PIPE_CONTROL_CS_STALL; | |
301 | ||
4772eaeb PZ |
302 | /* Just flush everything. Experiments have shown that reducing the |
303 | * number of bits based on the write domains has little performance | |
304 | * impact. | |
305 | */ | |
306 | if (flush_domains) { | |
307 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
308 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
309 | } |
310 | if (invalidate_domains) { | |
311 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
312 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
313 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
314 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
315 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
316 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
317 | /* | |
318 | * TLB invalidate requires a post-sync write. | |
319 | */ | |
320 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 321 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 PZ |
322 | |
323 | /* Workaround: we must issue a pipe_control with CS-stall bit | |
324 | * set before a pipe_control command that has the state cache | |
325 | * invalidate bit set. */ | |
326 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
327 | } |
328 | ||
329 | ret = intel_ring_begin(ring, 4); | |
330 | if (ret) | |
331 | return ret; | |
332 | ||
333 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
334 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 335 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
336 | intel_ring_emit(ring, 0); |
337 | intel_ring_advance(ring); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
78501eac | 342 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 343 | u32 value) |
d46eefa2 | 344 | { |
78501eac | 345 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 346 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
347 | } |
348 | ||
78501eac | 349 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 350 | { |
78501eac CW |
351 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
352 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 353 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
354 | |
355 | return I915_READ(acthd_reg); | |
356 | } | |
357 | ||
78501eac | 358 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 359 | { |
b7884eb4 DV |
360 | struct drm_device *dev = ring->dev; |
361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 362 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 363 | int ret = 0; |
8187a2b7 | 364 | u32 head; |
8187a2b7 | 365 | |
b7884eb4 DV |
366 | if (HAS_FORCE_WAKE(dev)) |
367 | gen6_gt_force_wake_get(dev_priv); | |
368 | ||
8187a2b7 | 369 | /* Stop the ring if it's running. */ |
7f2ab699 | 370 | I915_WRITE_CTL(ring, 0); |
570ef608 | 371 | I915_WRITE_HEAD(ring, 0); |
78501eac | 372 | ring->write_tail(ring, 0); |
8187a2b7 | 373 | |
570ef608 | 374 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
375 | |
376 | /* G45 ring initialization fails to reset head to zero */ | |
377 | if (head != 0) { | |
6fd0d56e CW |
378 | DRM_DEBUG_KMS("%s head not reset to zero " |
379 | "ctl %08x head %08x tail %08x start %08x\n", | |
380 | ring->name, | |
381 | I915_READ_CTL(ring), | |
382 | I915_READ_HEAD(ring), | |
383 | I915_READ_TAIL(ring), | |
384 | I915_READ_START(ring)); | |
8187a2b7 | 385 | |
570ef608 | 386 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 387 | |
6fd0d56e CW |
388 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
389 | DRM_ERROR("failed to set %s head to zero " | |
390 | "ctl %08x head %08x tail %08x start %08x\n", | |
391 | ring->name, | |
392 | I915_READ_CTL(ring), | |
393 | I915_READ_HEAD(ring), | |
394 | I915_READ_TAIL(ring), | |
395 | I915_READ_START(ring)); | |
396 | } | |
8187a2b7 ZN |
397 | } |
398 | ||
0d8957c8 DV |
399 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
400 | * registers with the above sequence (the readback of the HEAD registers | |
401 | * also enforces ordering), otherwise the hw might lose the new ring | |
402 | * register values. */ | |
403 | I915_WRITE_START(ring, obj->gtt_offset); | |
7f2ab699 | 404 | I915_WRITE_CTL(ring, |
ae69b42a | 405 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 406 | | RING_VALID); |
8187a2b7 | 407 | |
8187a2b7 | 408 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
409 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
410 | I915_READ_START(ring) == obj->gtt_offset && | |
411 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
412 | DRM_ERROR("%s initialization failed " |
413 | "ctl %08x head %08x tail %08x start %08x\n", | |
414 | ring->name, | |
415 | I915_READ_CTL(ring), | |
416 | I915_READ_HEAD(ring), | |
417 | I915_READ_TAIL(ring), | |
418 | I915_READ_START(ring)); | |
b7884eb4 DV |
419 | ret = -EIO; |
420 | goto out; | |
8187a2b7 ZN |
421 | } |
422 | ||
78501eac CW |
423 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
424 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 425 | else { |
c7dca47b | 426 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 427 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 428 | ring->space = ring_space(ring); |
c3b20037 | 429 | ring->last_retired_head = -1; |
8187a2b7 | 430 | } |
1ec14ad3 | 431 | |
b7884eb4 DV |
432 | out: |
433 | if (HAS_FORCE_WAKE(dev)) | |
434 | gen6_gt_force_wake_put(dev_priv); | |
435 | ||
436 | return ret; | |
8187a2b7 ZN |
437 | } |
438 | ||
c6df541c CW |
439 | static int |
440 | init_pipe_control(struct intel_ring_buffer *ring) | |
441 | { | |
442 | struct pipe_control *pc; | |
443 | struct drm_i915_gem_object *obj; | |
444 | int ret; | |
445 | ||
446 | if (ring->private) | |
447 | return 0; | |
448 | ||
449 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
450 | if (!pc) | |
451 | return -ENOMEM; | |
452 | ||
453 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
454 | if (obj == NULL) { | |
455 | DRM_ERROR("Failed to allocate seqno page\n"); | |
456 | ret = -ENOMEM; | |
457 | goto err; | |
458 | } | |
e4ffd173 CW |
459 | |
460 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c | 461 | |
86a1ee26 | 462 | ret = i915_gem_object_pin(obj, 4096, true, false); |
c6df541c CW |
463 | if (ret) |
464 | goto err_unref; | |
465 | ||
466 | pc->gtt_offset = obj->gtt_offset; | |
56b085a0 WY |
467 | pc->cpu_page = kmap(sg_page(obj->pages->sgl)); |
468 | if (pc->cpu_page == NULL) { | |
469 | ret = -ENOMEM; | |
c6df541c | 470 | goto err_unpin; |
56b085a0 | 471 | } |
c6df541c | 472 | |
2b1086cc VS |
473 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
474 | ring->name, pc->gtt_offset); | |
475 | ||
c6df541c CW |
476 | pc->obj = obj; |
477 | ring->private = pc; | |
478 | return 0; | |
479 | ||
480 | err_unpin: | |
481 | i915_gem_object_unpin(obj); | |
482 | err_unref: | |
483 | drm_gem_object_unreference(&obj->base); | |
484 | err: | |
485 | kfree(pc); | |
486 | return ret; | |
487 | } | |
488 | ||
489 | static void | |
490 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
491 | { | |
492 | struct pipe_control *pc = ring->private; | |
493 | struct drm_i915_gem_object *obj; | |
494 | ||
495 | if (!ring->private) | |
496 | return; | |
497 | ||
498 | obj = pc->obj; | |
9da3da66 CW |
499 | |
500 | kunmap(sg_page(obj->pages->sgl)); | |
c6df541c CW |
501 | i915_gem_object_unpin(obj); |
502 | drm_gem_object_unreference(&obj->base); | |
503 | ||
504 | kfree(pc); | |
505 | ring->private = NULL; | |
506 | } | |
507 | ||
78501eac | 508 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 509 | { |
78501eac | 510 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 511 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 512 | int ret = init_ring_common(ring); |
a69ffdbf | 513 | |
1c8c38c5 | 514 | if (INTEL_INFO(dev)->gen > 3) |
6b26c86d | 515 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
516 | |
517 | /* We need to disable the AsyncFlip performance optimisations in order | |
518 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
519 | * programmed to '1' on all products. | |
8693a824 DL |
520 | * |
521 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv | |
1c8c38c5 CW |
522 | */ |
523 | if (INTEL_INFO(dev)->gen >= 6) | |
524 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
525 | ||
f05bb0c7 CW |
526 | /* Required for the hardware to program scanline values for waiting */ |
527 | if (INTEL_INFO(dev)->gen == 6) | |
528 | I915_WRITE(GFX_MODE, | |
529 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS)); | |
530 | ||
1c8c38c5 CW |
531 | if (IS_GEN7(dev)) |
532 | I915_WRITE(GFX_MODE_GEN7, | |
533 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | | |
534 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
78501eac | 535 | |
8d315287 | 536 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
537 | ret = init_pipe_control(ring); |
538 | if (ret) | |
539 | return ret; | |
540 | } | |
541 | ||
5e13a0c5 | 542 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
543 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
544 | * "If this bit is set, STCunit will have LRA as replacement | |
545 | * policy. [...] This bit must be reset. LRA replacement | |
546 | * policy is not supported." | |
547 | */ | |
548 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 549 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
550 | |
551 | /* This is not explicitly set for GEN6, so read the register. | |
552 | * see intel_ring_mi_set_context() for why we care. | |
553 | * TODO: consider explicitly setting the bit for GEN5 | |
554 | */ | |
555 | ring->itlb_before_ctx_switch = | |
556 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
557 | } |
558 | ||
6b26c86d DV |
559 | if (INTEL_INFO(dev)->gen >= 6) |
560 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 561 | |
e1ef7cc2 | 562 | if (HAS_L3_GPU_CACHE(dev)) |
cc609d5d | 563 | I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); |
15b9f80e | 564 | |
8187a2b7 ZN |
565 | return ret; |
566 | } | |
567 | ||
c6df541c CW |
568 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
569 | { | |
b45305fc DV |
570 | struct drm_device *dev = ring->dev; |
571 | ||
c6df541c CW |
572 | if (!ring->private) |
573 | return; | |
574 | ||
b45305fc DV |
575 | if (HAS_BROKEN_CS_TLB(dev)) |
576 | drm_gem_object_unreference(to_gem_object(ring->private)); | |
577 | ||
c6df541c CW |
578 | cleanup_pipe_control(ring); |
579 | } | |
580 | ||
1ec14ad3 | 581 | static void |
c8c99b0f | 582 | update_mboxes(struct intel_ring_buffer *ring, |
9d773091 | 583 | u32 mmio_offset) |
1ec14ad3 | 584 | { |
ad776f8b BW |
585 | /* NB: In order to be able to do semaphore MBOX updates for varying number |
586 | * of rings, it's easiest if we round up each individual update to a | |
587 | * multiple of 2 (since ring updates must always be a multiple of 2) | |
588 | * even though the actual update only requires 3 dwords. | |
589 | */ | |
590 | #define MBOX_UPDATE_DWORDS 4 | |
1c8b46fc | 591 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
c8c99b0f | 592 | intel_ring_emit(ring, mmio_offset); |
9d773091 | 593 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
ad776f8b | 594 | intel_ring_emit(ring, MI_NOOP); |
1ec14ad3 CW |
595 | } |
596 | ||
c8c99b0f BW |
597 | /** |
598 | * gen6_add_request - Update the semaphore mailbox registers | |
599 | * | |
600 | * @ring - ring that is adding a request | |
601 | * @seqno - return seqno stuck into the ring | |
602 | * | |
603 | * Update the mailbox registers in the *other* rings with the current seqno. | |
604 | * This acts like a signal in the canonical semaphore. | |
605 | */ | |
1ec14ad3 | 606 | static int |
9d773091 | 607 | gen6_add_request(struct intel_ring_buffer *ring) |
1ec14ad3 | 608 | { |
ad776f8b BW |
609 | struct drm_device *dev = ring->dev; |
610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
611 | struct intel_ring_buffer *useless; | |
612 | int i, ret; | |
1ec14ad3 | 613 | |
ad776f8b BW |
614 | ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) * |
615 | MBOX_UPDATE_DWORDS) + | |
616 | 4); | |
1ec14ad3 CW |
617 | if (ret) |
618 | return ret; | |
ad776f8b | 619 | #undef MBOX_UPDATE_DWORDS |
1ec14ad3 | 620 | |
ad776f8b BW |
621 | for_each_ring(useless, dev_priv, i) { |
622 | u32 mbox_reg = ring->signal_mbox[i]; | |
623 | if (mbox_reg != GEN6_NOSYNC) | |
624 | update_mboxes(ring, mbox_reg); | |
625 | } | |
1ec14ad3 CW |
626 | |
627 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
628 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
9d773091 | 629 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
1ec14ad3 CW |
630 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
631 | intel_ring_advance(ring); | |
632 | ||
1ec14ad3 CW |
633 | return 0; |
634 | } | |
635 | ||
f72b3435 MK |
636 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
637 | u32 seqno) | |
638 | { | |
639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
640 | return dev_priv->last_seqno < seqno; | |
641 | } | |
642 | ||
c8c99b0f BW |
643 | /** |
644 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
645 | * | |
646 | * @waiter - ring that is waiting | |
647 | * @signaller - ring which has, or will signal | |
648 | * @seqno - seqno which the waiter will block on | |
649 | */ | |
650 | static int | |
686cb5f9 DV |
651 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
652 | struct intel_ring_buffer *signaller, | |
653 | u32 seqno) | |
1ec14ad3 CW |
654 | { |
655 | int ret; | |
c8c99b0f BW |
656 | u32 dw1 = MI_SEMAPHORE_MBOX | |
657 | MI_SEMAPHORE_COMPARE | | |
658 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 659 | |
1500f7ea BW |
660 | /* Throughout all of the GEM code, seqno passed implies our current |
661 | * seqno is >= the last seqno executed. However for hardware the | |
662 | * comparison is strictly greater than. | |
663 | */ | |
664 | seqno -= 1; | |
665 | ||
686cb5f9 DV |
666 | WARN_ON(signaller->semaphore_register[waiter->id] == |
667 | MI_SEMAPHORE_SYNC_INVALID); | |
668 | ||
c8c99b0f | 669 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
670 | if (ret) |
671 | return ret; | |
672 | ||
f72b3435 MK |
673 | /* If seqno wrap happened, omit the wait with no-ops */ |
674 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
675 | intel_ring_emit(waiter, | |
676 | dw1 | | |
677 | signaller->semaphore_register[waiter->id]); | |
678 | intel_ring_emit(waiter, seqno); | |
679 | intel_ring_emit(waiter, 0); | |
680 | intel_ring_emit(waiter, MI_NOOP); | |
681 | } else { | |
682 | intel_ring_emit(waiter, MI_NOOP); | |
683 | intel_ring_emit(waiter, MI_NOOP); | |
684 | intel_ring_emit(waiter, MI_NOOP); | |
685 | intel_ring_emit(waiter, MI_NOOP); | |
686 | } | |
c8c99b0f | 687 | intel_ring_advance(waiter); |
1ec14ad3 CW |
688 | |
689 | return 0; | |
690 | } | |
691 | ||
c6df541c CW |
692 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
693 | do { \ | |
fcbc34e4 KG |
694 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
695 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
696 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
697 | intel_ring_emit(ring__, 0); \ | |
698 | intel_ring_emit(ring__, 0); \ | |
699 | } while (0) | |
700 | ||
701 | static int | |
9d773091 | 702 | pc_render_add_request(struct intel_ring_buffer *ring) |
c6df541c | 703 | { |
c6df541c CW |
704 | struct pipe_control *pc = ring->private; |
705 | u32 scratch_addr = pc->gtt_offset + 128; | |
706 | int ret; | |
707 | ||
708 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
709 | * incoherent with writes to memory, i.e. completely fubar, | |
710 | * so we need to use PIPE_NOTIFY instead. | |
711 | * | |
712 | * However, we also need to workaround the qword write | |
713 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
714 | * memory before requesting an interrupt. | |
715 | */ | |
716 | ret = intel_ring_begin(ring, 32); | |
717 | if (ret) | |
718 | return ret; | |
719 | ||
fcbc34e4 | 720 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
721 | PIPE_CONTROL_WRITE_FLUSH | |
722 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c | 723 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
9d773091 | 724 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
c6df541c CW |
725 | intel_ring_emit(ring, 0); |
726 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
727 | scratch_addr += 128; /* write to separate cachelines */ | |
728 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
729 | scratch_addr += 128; | |
730 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
731 | scratch_addr += 128; | |
732 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
733 | scratch_addr += 128; | |
734 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
735 | scratch_addr += 128; | |
736 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 737 | |
fcbc34e4 | 738 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
739 | PIPE_CONTROL_WRITE_FLUSH | |
740 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
741 | PIPE_CONTROL_NOTIFY); |
742 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
9d773091 | 743 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
c6df541c CW |
744 | intel_ring_emit(ring, 0); |
745 | intel_ring_advance(ring); | |
746 | ||
c6df541c CW |
747 | return 0; |
748 | } | |
749 | ||
4cd53c0c | 750 | static u32 |
b2eadbc8 | 751 | gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
4cd53c0c | 752 | { |
4cd53c0c DV |
753 | /* Workaround to force correct ordering between irq and seqno writes on |
754 | * ivb (and maybe also on snb) by reading from a CS register (like | |
755 | * ACTHD) before reading the status page. */ | |
b2eadbc8 | 756 | if (!lazy_coherency) |
4cd53c0c DV |
757 | intel_ring_get_active_head(ring); |
758 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
759 | } | |
760 | ||
8187a2b7 | 761 | static u32 |
b2eadbc8 | 762 | ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
8187a2b7 | 763 | { |
1ec14ad3 CW |
764 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
765 | } | |
766 | ||
b70ec5bf MK |
767 | static void |
768 | ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
769 | { | |
770 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
771 | } | |
772 | ||
c6df541c | 773 | static u32 |
b2eadbc8 | 774 | pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency) |
c6df541c CW |
775 | { |
776 | struct pipe_control *pc = ring->private; | |
777 | return pc->cpu_page[0]; | |
778 | } | |
779 | ||
b70ec5bf MK |
780 | static void |
781 | pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno) | |
782 | { | |
783 | struct pipe_control *pc = ring->private; | |
784 | pc->cpu_page[0] = seqno; | |
785 | } | |
786 | ||
e48d8634 DV |
787 | static bool |
788 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
789 | { | |
790 | struct drm_device *dev = ring->dev; | |
791 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 792 | unsigned long flags; |
e48d8634 DV |
793 | |
794 | if (!dev->irq_enabled) | |
795 | return false; | |
796 | ||
7338aefa | 797 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 798 | if (ring->irq_refcount.gt++ == 0) { |
f637fde4 DV |
799 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
800 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
801 | POSTING_READ(GTIMR); | |
802 | } | |
7338aefa | 803 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
804 | |
805 | return true; | |
806 | } | |
807 | ||
808 | static void | |
809 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
810 | { | |
811 | struct drm_device *dev = ring->dev; | |
812 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 813 | unsigned long flags; |
e48d8634 | 814 | |
7338aefa | 815 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 816 | if (--ring->irq_refcount.gt == 0) { |
f637fde4 DV |
817 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
818 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
819 | POSTING_READ(GTIMR); | |
820 | } | |
7338aefa | 821 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
822 | } |
823 | ||
b13c2b96 | 824 | static bool |
e3670319 | 825 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 826 | { |
78501eac | 827 | struct drm_device *dev = ring->dev; |
01a03331 | 828 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 829 | unsigned long flags; |
62fdfeaf | 830 | |
b13c2b96 CW |
831 | if (!dev->irq_enabled) |
832 | return false; | |
833 | ||
7338aefa | 834 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 835 | if (ring->irq_refcount.gt++ == 0) { |
f637fde4 DV |
836 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
837 | I915_WRITE(IMR, dev_priv->irq_mask); | |
838 | POSTING_READ(IMR); | |
839 | } | |
7338aefa | 840 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
841 | |
842 | return true; | |
62fdfeaf EA |
843 | } |
844 | ||
8187a2b7 | 845 | static void |
e3670319 | 846 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 847 | { |
78501eac | 848 | struct drm_device *dev = ring->dev; |
01a03331 | 849 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 850 | unsigned long flags; |
62fdfeaf | 851 | |
7338aefa | 852 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 853 | if (--ring->irq_refcount.gt == 0) { |
f637fde4 DV |
854 | dev_priv->irq_mask |= ring->irq_enable_mask; |
855 | I915_WRITE(IMR, dev_priv->irq_mask); | |
856 | POSTING_READ(IMR); | |
857 | } | |
7338aefa | 858 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
859 | } |
860 | ||
c2798b19 CW |
861 | static bool |
862 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
863 | { | |
864 | struct drm_device *dev = ring->dev; | |
865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 866 | unsigned long flags; |
c2798b19 CW |
867 | |
868 | if (!dev->irq_enabled) | |
869 | return false; | |
870 | ||
7338aefa | 871 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 872 | if (ring->irq_refcount.gt++ == 0) { |
c2798b19 CW |
873 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
874 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
875 | POSTING_READ16(IMR); | |
876 | } | |
7338aefa | 877 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
878 | |
879 | return true; | |
880 | } | |
881 | ||
882 | static void | |
883 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
884 | { | |
885 | struct drm_device *dev = ring->dev; | |
886 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 887 | unsigned long flags; |
c2798b19 | 888 | |
7338aefa | 889 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 890 | if (--ring->irq_refcount.gt == 0) { |
c2798b19 CW |
891 | dev_priv->irq_mask |= ring->irq_enable_mask; |
892 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
893 | POSTING_READ16(IMR); | |
894 | } | |
7338aefa | 895 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
896 | } |
897 | ||
78501eac | 898 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 899 | { |
4593010b | 900 | struct drm_device *dev = ring->dev; |
78501eac | 901 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
902 | u32 mmio = 0; |
903 | ||
904 | /* The ring status page addresses are no longer next to the rest of | |
905 | * the ring registers as of gen7. | |
906 | */ | |
907 | if (IS_GEN7(dev)) { | |
908 | switch (ring->id) { | |
96154f2f | 909 | case RCS: |
4593010b EA |
910 | mmio = RENDER_HWS_PGA_GEN7; |
911 | break; | |
96154f2f | 912 | case BCS: |
4593010b EA |
913 | mmio = BLT_HWS_PGA_GEN7; |
914 | break; | |
96154f2f | 915 | case VCS: |
4593010b EA |
916 | mmio = BSD_HWS_PGA_GEN7; |
917 | break; | |
4a3dd19d | 918 | case VECS: |
9a8a2213 BW |
919 | mmio = VEBOX_HWS_PGA_GEN7; |
920 | break; | |
4593010b EA |
921 | } |
922 | } else if (IS_GEN6(ring->dev)) { | |
923 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
924 | } else { | |
925 | mmio = RING_HWS_PGA(ring->mmio_base); | |
926 | } | |
927 | ||
78501eac CW |
928 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
929 | POSTING_READ(mmio); | |
8187a2b7 ZN |
930 | } |
931 | ||
b72f3acb | 932 | static int |
78501eac CW |
933 | bsd_ring_flush(struct intel_ring_buffer *ring, |
934 | u32 invalidate_domains, | |
935 | u32 flush_domains) | |
d1b851fc | 936 | { |
b72f3acb CW |
937 | int ret; |
938 | ||
b72f3acb CW |
939 | ret = intel_ring_begin(ring, 2); |
940 | if (ret) | |
941 | return ret; | |
942 | ||
943 | intel_ring_emit(ring, MI_FLUSH); | |
944 | intel_ring_emit(ring, MI_NOOP); | |
945 | intel_ring_advance(ring); | |
946 | return 0; | |
d1b851fc ZN |
947 | } |
948 | ||
3cce469c | 949 | static int |
9d773091 | 950 | i9xx_add_request(struct intel_ring_buffer *ring) |
d1b851fc | 951 | { |
3cce469c CW |
952 | int ret; |
953 | ||
954 | ret = intel_ring_begin(ring, 4); | |
955 | if (ret) | |
956 | return ret; | |
6f392d54 | 957 | |
3cce469c CW |
958 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
959 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
9d773091 | 960 | intel_ring_emit(ring, ring->outstanding_lazy_request); |
3cce469c CW |
961 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
962 | intel_ring_advance(ring); | |
d1b851fc | 963 | |
3cce469c | 964 | return 0; |
d1b851fc ZN |
965 | } |
966 | ||
0f46832f | 967 | static bool |
25c06300 | 968 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
969 | { |
970 | struct drm_device *dev = ring->dev; | |
01a03331 | 971 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 972 | unsigned long flags; |
0f46832f CW |
973 | |
974 | if (!dev->irq_enabled) | |
975 | return false; | |
976 | ||
4cd53c0c DV |
977 | /* It looks like we need to prevent the gt from suspending while waiting |
978 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
979 | * blt/bsd rings on ivb. */ | |
99ffa162 | 980 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 981 | |
7338aefa | 982 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 983 | if (ring->irq_refcount.gt++ == 0) { |
e1ef7cc2 | 984 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
cc609d5d BW |
985 | I915_WRITE_IMR(ring, |
986 | ~(ring->irq_enable_mask | | |
987 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
15b9f80e BW |
988 | else |
989 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
f637fde4 DV |
990 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
991 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
992 | POSTING_READ(GTIMR); | |
0f46832f | 993 | } |
7338aefa | 994 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
995 | |
996 | return true; | |
997 | } | |
998 | ||
999 | static void | |
25c06300 | 1000 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
1001 | { |
1002 | struct drm_device *dev = ring->dev; | |
01a03331 | 1003 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 1004 | unsigned long flags; |
0f46832f | 1005 | |
7338aefa | 1006 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
aeb06593 | 1007 | if (--ring->irq_refcount.gt == 0) { |
e1ef7cc2 | 1008 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
cc609d5d BW |
1009 | I915_WRITE_IMR(ring, |
1010 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
15b9f80e BW |
1011 | else |
1012 | I915_WRITE_IMR(ring, ~0); | |
f637fde4 DV |
1013 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
1014 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
1015 | POSTING_READ(GTIMR); | |
1ec14ad3 | 1016 | } |
7338aefa | 1017 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 1018 | |
99ffa162 | 1019 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
1020 | } |
1021 | ||
d1b851fc | 1022 | static int |
d7d4eedd CW |
1023 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, |
1024 | u32 offset, u32 length, | |
1025 | unsigned flags) | |
d1b851fc | 1026 | { |
e1f99ce6 | 1027 | int ret; |
78501eac | 1028 | |
e1f99ce6 CW |
1029 | ret = intel_ring_begin(ring, 2); |
1030 | if (ret) | |
1031 | return ret; | |
1032 | ||
78501eac | 1033 | intel_ring_emit(ring, |
65f56876 CW |
1034 | MI_BATCH_BUFFER_START | |
1035 | MI_BATCH_GTT | | |
d7d4eedd | 1036 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1037 | intel_ring_emit(ring, offset); |
78501eac CW |
1038 | intel_ring_advance(ring); |
1039 | ||
d1b851fc ZN |
1040 | return 0; |
1041 | } | |
1042 | ||
b45305fc DV |
1043 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1044 | #define I830_BATCH_LIMIT (256*1024) | |
8187a2b7 | 1045 | static int |
fb3256da | 1046 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1047 | u32 offset, u32 len, |
1048 | unsigned flags) | |
62fdfeaf | 1049 | { |
c4e7a414 | 1050 | int ret; |
62fdfeaf | 1051 | |
b45305fc DV |
1052 | if (flags & I915_DISPATCH_PINNED) { |
1053 | ret = intel_ring_begin(ring, 4); | |
1054 | if (ret) | |
1055 | return ret; | |
62fdfeaf | 1056 | |
b45305fc DV |
1057 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
1058 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1059 | intel_ring_emit(ring, offset + len - 8); | |
1060 | intel_ring_emit(ring, MI_NOOP); | |
1061 | intel_ring_advance(ring); | |
1062 | } else { | |
1063 | struct drm_i915_gem_object *obj = ring->private; | |
1064 | u32 cs_offset = obj->gtt_offset; | |
1065 | ||
1066 | if (len > I830_BATCH_LIMIT) | |
1067 | return -ENOSPC; | |
1068 | ||
1069 | ret = intel_ring_begin(ring, 9+3); | |
1070 | if (ret) | |
1071 | return ret; | |
1072 | /* Blit the batch (which has now all relocs applied) to the stable batch | |
1073 | * scratch bo area (so that the CS never stumbles over its tlb | |
1074 | * invalidation bug) ... */ | |
1075 | intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | | |
1076 | XY_SRC_COPY_BLT_WRITE_ALPHA | | |
1077 | XY_SRC_COPY_BLT_WRITE_RGB); | |
1078 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); | |
1079 | intel_ring_emit(ring, 0); | |
1080 | intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); | |
1081 | intel_ring_emit(ring, cs_offset); | |
1082 | intel_ring_emit(ring, 0); | |
1083 | intel_ring_emit(ring, 4096); | |
1084 | intel_ring_emit(ring, offset); | |
1085 | intel_ring_emit(ring, MI_FLUSH); | |
1086 | ||
1087 | /* ... and execute it. */ | |
1088 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1089 | intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1090 | intel_ring_emit(ring, cs_offset + len - 8); | |
1091 | intel_ring_advance(ring); | |
1092 | } | |
e1f99ce6 | 1093 | |
fb3256da DV |
1094 | return 0; |
1095 | } | |
1096 | ||
1097 | static int | |
1098 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
d7d4eedd CW |
1099 | u32 offset, u32 len, |
1100 | unsigned flags) | |
fb3256da DV |
1101 | { |
1102 | int ret; | |
1103 | ||
1104 | ret = intel_ring_begin(ring, 2); | |
1105 | if (ret) | |
1106 | return ret; | |
1107 | ||
65f56876 | 1108 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1109 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1110 | intel_ring_advance(ring); |
62fdfeaf | 1111 | |
62fdfeaf EA |
1112 | return 0; |
1113 | } | |
1114 | ||
78501eac | 1115 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1116 | { |
05394f39 | 1117 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1118 | |
8187a2b7 ZN |
1119 | obj = ring->status_page.obj; |
1120 | if (obj == NULL) | |
62fdfeaf | 1121 | return; |
62fdfeaf | 1122 | |
9da3da66 | 1123 | kunmap(sg_page(obj->pages->sgl)); |
62fdfeaf | 1124 | i915_gem_object_unpin(obj); |
05394f39 | 1125 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1126 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1127 | } |
1128 | ||
78501eac | 1129 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 1130 | { |
78501eac | 1131 | struct drm_device *dev = ring->dev; |
05394f39 | 1132 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
1133 | int ret; |
1134 | ||
62fdfeaf EA |
1135 | obj = i915_gem_alloc_object(dev, 4096); |
1136 | if (obj == NULL) { | |
1137 | DRM_ERROR("Failed to allocate status page\n"); | |
1138 | ret = -ENOMEM; | |
1139 | goto err; | |
1140 | } | |
e4ffd173 CW |
1141 | |
1142 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 1143 | |
86a1ee26 | 1144 | ret = i915_gem_object_pin(obj, 4096, true, false); |
62fdfeaf | 1145 | if (ret != 0) { |
62fdfeaf EA |
1146 | goto err_unref; |
1147 | } | |
1148 | ||
05394f39 | 1149 | ring->status_page.gfx_addr = obj->gtt_offset; |
9da3da66 | 1150 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1151 | if (ring->status_page.page_addr == NULL) { |
2e6c21ed | 1152 | ret = -ENOMEM; |
62fdfeaf EA |
1153 | goto err_unpin; |
1154 | } | |
8187a2b7 ZN |
1155 | ring->status_page.obj = obj; |
1156 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 1157 | |
78501eac | 1158 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
1159 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1160 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1161 | |
1162 | return 0; | |
1163 | ||
1164 | err_unpin: | |
1165 | i915_gem_object_unpin(obj); | |
1166 | err_unref: | |
05394f39 | 1167 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 1168 | err: |
8187a2b7 | 1169 | return ret; |
62fdfeaf EA |
1170 | } |
1171 | ||
6b8294a4 CW |
1172 | static int init_phys_hws_pga(struct intel_ring_buffer *ring) |
1173 | { | |
1174 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1175 | u32 addr; | |
1176 | ||
1177 | if (!dev_priv->status_page_dmah) { | |
1178 | dev_priv->status_page_dmah = | |
1179 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1180 | if (!dev_priv->status_page_dmah) | |
1181 | return -ENOMEM; | |
1182 | } | |
1183 | ||
1184 | addr = dev_priv->status_page_dmah->busaddr; | |
1185 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
1186 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
1187 | I915_WRITE(HWS_PGA, addr); | |
1188 | ||
1189 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1190 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
c43b5634 BW |
1195 | static int intel_init_ring_buffer(struct drm_device *dev, |
1196 | struct intel_ring_buffer *ring) | |
62fdfeaf | 1197 | { |
05394f39 | 1198 | struct drm_i915_gem_object *obj; |
dd2757f8 | 1199 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
1200 | int ret; |
1201 | ||
8187a2b7 | 1202 | ring->dev = dev; |
23bc5982 CW |
1203 | INIT_LIST_HEAD(&ring->active_list); |
1204 | INIT_LIST_HEAD(&ring->request_list); | |
dfc9ef2f | 1205 | ring->size = 32 * PAGE_SIZE; |
9d773091 | 1206 | memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno)); |
0dc79fb2 | 1207 | |
b259f673 | 1208 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1209 | |
8187a2b7 | 1210 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1211 | ret = init_status_page(ring); |
8187a2b7 ZN |
1212 | if (ret) |
1213 | return ret; | |
6b8294a4 CW |
1214 | } else { |
1215 | BUG_ON(ring->id != RCS); | |
1216 | ret = init_phys_hws_pga(ring); | |
1217 | if (ret) | |
1218 | return ret; | |
8187a2b7 | 1219 | } |
62fdfeaf | 1220 | |
ebc052e0 CW |
1221 | obj = NULL; |
1222 | if (!HAS_LLC(dev)) | |
1223 | obj = i915_gem_object_create_stolen(dev, ring->size); | |
1224 | if (obj == NULL) | |
1225 | obj = i915_gem_alloc_object(dev, ring->size); | |
62fdfeaf EA |
1226 | if (obj == NULL) { |
1227 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1228 | ret = -ENOMEM; |
dd785e35 | 1229 | goto err_hws; |
62fdfeaf | 1230 | } |
62fdfeaf | 1231 | |
05394f39 | 1232 | ring->obj = obj; |
8187a2b7 | 1233 | |
86a1ee26 | 1234 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
1235 | if (ret) |
1236 | goto err_unref; | |
62fdfeaf | 1237 | |
3eef8918 CW |
1238 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1239 | if (ret) | |
1240 | goto err_unpin; | |
1241 | ||
dd2757f8 | 1242 | ring->virtual_start = |
dabb7a91 | 1243 | ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset, |
dd2757f8 | 1244 | ring->size); |
4225d0f2 | 1245 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1246 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1247 | ret = -EINVAL; |
dd785e35 | 1248 | goto err_unpin; |
62fdfeaf EA |
1249 | } |
1250 | ||
78501eac | 1251 | ret = ring->init(ring); |
dd785e35 CW |
1252 | if (ret) |
1253 | goto err_unmap; | |
62fdfeaf | 1254 | |
55249baa CW |
1255 | /* Workaround an erratum on the i830 which causes a hang if |
1256 | * the TAIL pointer points to within the last 2 cachelines | |
1257 | * of the buffer. | |
1258 | */ | |
1259 | ring->effective_size = ring->size; | |
27c1cbd0 | 1260 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1261 | ring->effective_size -= 128; |
1262 | ||
c584fe47 | 1263 | return 0; |
dd785e35 CW |
1264 | |
1265 | err_unmap: | |
4225d0f2 | 1266 | iounmap(ring->virtual_start); |
dd785e35 CW |
1267 | err_unpin: |
1268 | i915_gem_object_unpin(obj); | |
1269 | err_unref: | |
05394f39 CW |
1270 | drm_gem_object_unreference(&obj->base); |
1271 | ring->obj = NULL; | |
dd785e35 | 1272 | err_hws: |
78501eac | 1273 | cleanup_status_page(ring); |
8187a2b7 | 1274 | return ret; |
62fdfeaf EA |
1275 | } |
1276 | ||
78501eac | 1277 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1278 | { |
33626e6a CW |
1279 | struct drm_i915_private *dev_priv; |
1280 | int ret; | |
1281 | ||
05394f39 | 1282 | if (ring->obj == NULL) |
62fdfeaf EA |
1283 | return; |
1284 | ||
33626e6a CW |
1285 | /* Disable the ring buffer. The ring must be idle at this point */ |
1286 | dev_priv = ring->dev->dev_private; | |
3e960501 | 1287 | ret = intel_ring_idle(ring); |
29ee3991 CW |
1288 | if (ret) |
1289 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1290 | ring->name, ret); | |
1291 | ||
33626e6a CW |
1292 | I915_WRITE_CTL(ring, 0); |
1293 | ||
4225d0f2 | 1294 | iounmap(ring->virtual_start); |
62fdfeaf | 1295 | |
05394f39 CW |
1296 | i915_gem_object_unpin(ring->obj); |
1297 | drm_gem_object_unreference(&ring->obj->base); | |
1298 | ring->obj = NULL; | |
78501eac | 1299 | |
8d19215b ZN |
1300 | if (ring->cleanup) |
1301 | ring->cleanup(ring); | |
1302 | ||
78501eac | 1303 | cleanup_status_page(ring); |
62fdfeaf EA |
1304 | } |
1305 | ||
a71d8d94 CW |
1306 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1307 | { | |
a71d8d94 CW |
1308 | int ret; |
1309 | ||
199b2bc2 | 1310 | ret = i915_wait_seqno(ring, seqno); |
b2da9fe5 BW |
1311 | if (!ret) |
1312 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1313 | |
1314 | return ret; | |
1315 | } | |
1316 | ||
1317 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1318 | { | |
1319 | struct drm_i915_gem_request *request; | |
1320 | u32 seqno = 0; | |
1321 | int ret; | |
1322 | ||
1323 | i915_gem_retire_requests_ring(ring); | |
1324 | ||
1325 | if (ring->last_retired_head != -1) { | |
1326 | ring->head = ring->last_retired_head; | |
1327 | ring->last_retired_head = -1; | |
1328 | ring->space = ring_space(ring); | |
1329 | if (ring->space >= n) | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | list_for_each_entry(request, &ring->request_list, list) { | |
1334 | int space; | |
1335 | ||
1336 | if (request->tail == -1) | |
1337 | continue; | |
1338 | ||
633cf8f5 | 1339 | space = request->tail - (ring->tail + I915_RING_FREE_SPACE); |
a71d8d94 CW |
1340 | if (space < 0) |
1341 | space += ring->size; | |
1342 | if (space >= n) { | |
1343 | seqno = request->seqno; | |
1344 | break; | |
1345 | } | |
1346 | ||
1347 | /* Consume this request in case we need more space than | |
1348 | * is available and so need to prevent a race between | |
1349 | * updating last_retired_head and direct reads of | |
1350 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1351 | */ | |
1352 | request->tail = -1; | |
1353 | } | |
1354 | ||
1355 | if (seqno == 0) | |
1356 | return -ENOSPC; | |
1357 | ||
1358 | ret = intel_ring_wait_seqno(ring, seqno); | |
1359 | if (ret) | |
1360 | return ret; | |
1361 | ||
1362 | if (WARN_ON(ring->last_retired_head == -1)) | |
1363 | return -ENOSPC; | |
1364 | ||
1365 | ring->head = ring->last_retired_head; | |
1366 | ring->last_retired_head = -1; | |
1367 | ring->space = ring_space(ring); | |
1368 | if (WARN_ON(ring->space < n)) | |
1369 | return -ENOSPC; | |
1370 | ||
1371 | return 0; | |
1372 | } | |
1373 | ||
3e960501 | 1374 | static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1375 | { |
78501eac | 1376 | struct drm_device *dev = ring->dev; |
cae5852d | 1377 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1378 | unsigned long end; |
a71d8d94 | 1379 | int ret; |
c7dca47b | 1380 | |
a71d8d94 CW |
1381 | ret = intel_ring_wait_request(ring, n); |
1382 | if (ret != -ENOSPC) | |
1383 | return ret; | |
1384 | ||
db53a302 | 1385 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1386 | /* With GEM the hangcheck timer should kick us out of the loop, |
1387 | * leaving it early runs the risk of corrupting GEM state (due | |
1388 | * to running on almost untested codepaths). But on resume | |
1389 | * timers don't work yet, so prevent a complete hang in that | |
1390 | * case by choosing an insanely large timeout. */ | |
1391 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1392 | |
8187a2b7 | 1393 | do { |
c7dca47b CW |
1394 | ring->head = I915_READ_HEAD(ring); |
1395 | ring->space = ring_space(ring); | |
62fdfeaf | 1396 | if (ring->space >= n) { |
db53a302 | 1397 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1398 | return 0; |
1399 | } | |
1400 | ||
1401 | if (dev->primary->master) { | |
1402 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1403 | if (master_priv->sarea_priv) | |
1404 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1405 | } | |
d1b851fc | 1406 | |
e60a0b10 | 1407 | msleep(1); |
d6b2c790 | 1408 | |
33196ded DV |
1409 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1410 | dev_priv->mm.interruptible); | |
d6b2c790 DV |
1411 | if (ret) |
1412 | return ret; | |
8187a2b7 | 1413 | } while (!time_after(jiffies, end)); |
db53a302 | 1414 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1415 | return -EBUSY; |
1416 | } | |
62fdfeaf | 1417 | |
3e960501 CW |
1418 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
1419 | { | |
1420 | uint32_t __iomem *virt; | |
1421 | int rem = ring->size - ring->tail; | |
1422 | ||
1423 | if (ring->space < rem) { | |
1424 | int ret = ring_wait_for_space(ring, rem); | |
1425 | if (ret) | |
1426 | return ret; | |
1427 | } | |
1428 | ||
1429 | virt = ring->virtual_start + ring->tail; | |
1430 | rem /= 4; | |
1431 | while (rem--) | |
1432 | iowrite32(MI_NOOP, virt++); | |
1433 | ||
1434 | ring->tail = 0; | |
1435 | ring->space = ring_space(ring); | |
1436 | ||
1437 | return 0; | |
1438 | } | |
1439 | ||
1440 | int intel_ring_idle(struct intel_ring_buffer *ring) | |
1441 | { | |
1442 | u32 seqno; | |
1443 | int ret; | |
1444 | ||
1445 | /* We need to add any requests required to flush the objects and ring */ | |
1446 | if (ring->outstanding_lazy_request) { | |
1447 | ret = i915_add_request(ring, NULL, NULL); | |
1448 | if (ret) | |
1449 | return ret; | |
1450 | } | |
1451 | ||
1452 | /* Wait upon the last request to be completed */ | |
1453 | if (list_empty(&ring->request_list)) | |
1454 | return 0; | |
1455 | ||
1456 | seqno = list_entry(ring->request_list.prev, | |
1457 | struct drm_i915_gem_request, | |
1458 | list)->seqno; | |
1459 | ||
1460 | return i915_wait_seqno(ring, seqno); | |
1461 | } | |
1462 | ||
9d773091 CW |
1463 | static int |
1464 | intel_ring_alloc_seqno(struct intel_ring_buffer *ring) | |
1465 | { | |
1466 | if (ring->outstanding_lazy_request) | |
1467 | return 0; | |
1468 | ||
1469 | return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request); | |
1470 | } | |
1471 | ||
cbcc80df MK |
1472 | static int __intel_ring_begin(struct intel_ring_buffer *ring, |
1473 | int bytes) | |
1474 | { | |
1475 | int ret; | |
1476 | ||
1477 | if (unlikely(ring->tail + bytes > ring->effective_size)) { | |
1478 | ret = intel_wrap_ring_buffer(ring); | |
1479 | if (unlikely(ret)) | |
1480 | return ret; | |
1481 | } | |
1482 | ||
1483 | if (unlikely(ring->space < bytes)) { | |
1484 | ret = ring_wait_for_space(ring, bytes); | |
1485 | if (unlikely(ret)) | |
1486 | return ret; | |
1487 | } | |
1488 | ||
1489 | ring->space -= bytes; | |
1490 | return 0; | |
1491 | } | |
1492 | ||
e1f99ce6 CW |
1493 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1494 | int num_dwords) | |
8187a2b7 | 1495 | { |
de2b9985 | 1496 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 1497 | int ret; |
78501eac | 1498 | |
33196ded DV |
1499 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
1500 | dev_priv->mm.interruptible); | |
de2b9985 DV |
1501 | if (ret) |
1502 | return ret; | |
21dd3734 | 1503 | |
9d773091 CW |
1504 | /* Preallocate the olr before touching the ring */ |
1505 | ret = intel_ring_alloc_seqno(ring); | |
1506 | if (ret) | |
1507 | return ret; | |
1508 | ||
cbcc80df | 1509 | return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t)); |
8187a2b7 | 1510 | } |
78501eac | 1511 | |
f7e98ad4 | 1512 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno) |
498d2ac1 | 1513 | { |
f7e98ad4 | 1514 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
498d2ac1 MK |
1515 | |
1516 | BUG_ON(ring->outstanding_lazy_request); | |
1517 | ||
f7e98ad4 MK |
1518 | if (INTEL_INFO(ring->dev)->gen >= 6) { |
1519 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); | |
1520 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
e1f99ce6 | 1521 | } |
d97ed339 | 1522 | |
f7e98ad4 | 1523 | ring->set_seqno(ring, seqno); |
92cab734 | 1524 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 1525 | } |
62fdfeaf | 1526 | |
78501eac | 1527 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1528 | { |
e5eb3d63 DV |
1529 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1530 | ||
d97ed339 | 1531 | ring->tail &= ring->size - 1; |
99584db3 | 1532 | if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring)) |
e5eb3d63 | 1533 | return; |
78501eac | 1534 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1535 | } |
62fdfeaf | 1536 | |
881f47b6 | 1537 | |
78501eac | 1538 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1539 | u32 value) |
881f47b6 | 1540 | { |
0206e353 | 1541 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1542 | |
1543 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
1544 | |
1545 | /* Disable notification that the ring is IDLE. The GT | |
1546 | * will then assume that it is busy and bring it out of rc6. | |
1547 | */ | |
0206e353 | 1548 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
1549 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
1550 | ||
1551 | /* Clear the context id. Here be magic! */ | |
1552 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 1553 | |
12f55818 | 1554 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 1555 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
1556 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
1557 | 50)) | |
1558 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 1559 | |
12f55818 | 1560 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 1561 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
1562 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
1563 | ||
1564 | /* Let the ring send IDLE messages to the GT again, | |
1565 | * and so let it sleep to conserve power when idle. | |
1566 | */ | |
0206e353 | 1567 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 1568 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
1569 | } |
1570 | ||
ea251324 BW |
1571 | static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring, |
1572 | u32 invalidate, u32 flush) | |
881f47b6 | 1573 | { |
71a77e07 | 1574 | uint32_t cmd; |
b72f3acb CW |
1575 | int ret; |
1576 | ||
b72f3acb CW |
1577 | ret = intel_ring_begin(ring, 4); |
1578 | if (ret) | |
1579 | return ret; | |
1580 | ||
71a77e07 | 1581 | cmd = MI_FLUSH_DW; |
9a289771 JB |
1582 | /* |
1583 | * Bspec vol 1c.5 - video engine command streamer: | |
1584 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1585 | * operation is complete. This bit is only valid when the | |
1586 | * Post-Sync Operation field is a value of 1h or 3h." | |
1587 | */ | |
71a77e07 | 1588 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
1589 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
1590 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 1591 | intel_ring_emit(ring, cmd); |
9a289771 | 1592 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
b72f3acb | 1593 | intel_ring_emit(ring, 0); |
71a77e07 | 1594 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1595 | intel_ring_advance(ring); |
1596 | return 0; | |
881f47b6 XH |
1597 | } |
1598 | ||
d7d4eedd CW |
1599 | static int |
1600 | hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
1601 | u32 offset, u32 len, | |
1602 | unsigned flags) | |
1603 | { | |
1604 | int ret; | |
1605 | ||
1606 | ret = intel_ring_begin(ring, 2); | |
1607 | if (ret) | |
1608 | return ret; | |
1609 | ||
1610 | intel_ring_emit(ring, | |
1611 | MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | | |
1612 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); | |
1613 | /* bit0-7 is the length on GEN6+ */ | |
1614 | intel_ring_emit(ring, offset); | |
1615 | intel_ring_advance(ring); | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
881f47b6 | 1620 | static int |
78501eac | 1621 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
d7d4eedd CW |
1622 | u32 offset, u32 len, |
1623 | unsigned flags) | |
881f47b6 | 1624 | { |
0206e353 | 1625 | int ret; |
ab6f8e32 | 1626 | |
0206e353 AJ |
1627 | ret = intel_ring_begin(ring, 2); |
1628 | if (ret) | |
1629 | return ret; | |
e1f99ce6 | 1630 | |
d7d4eedd CW |
1631 | intel_ring_emit(ring, |
1632 | MI_BATCH_BUFFER_START | | |
1633 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
1634 | /* bit0-7 is the length on GEN6+ */ |
1635 | intel_ring_emit(ring, offset); | |
1636 | intel_ring_advance(ring); | |
ab6f8e32 | 1637 | |
0206e353 | 1638 | return 0; |
881f47b6 XH |
1639 | } |
1640 | ||
549f7365 CW |
1641 | /* Blitter support (SandyBridge+) */ |
1642 | ||
ea251324 BW |
1643 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
1644 | u32 invalidate, u32 flush) | |
8d19215b | 1645 | { |
71a77e07 | 1646 | uint32_t cmd; |
b72f3acb CW |
1647 | int ret; |
1648 | ||
6a233c78 | 1649 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1650 | if (ret) |
1651 | return ret; | |
1652 | ||
71a77e07 | 1653 | cmd = MI_FLUSH_DW; |
9a289771 JB |
1654 | /* |
1655 | * Bspec vol 1c.3 - blitter engine command streamer: | |
1656 | * "If ENABLED, all TLBs will be invalidated once the flush | |
1657 | * operation is complete. This bit is only valid when the | |
1658 | * Post-Sync Operation field is a value of 1h or 3h." | |
1659 | */ | |
71a77e07 | 1660 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 1661 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 1662 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 1663 | intel_ring_emit(ring, cmd); |
9a289771 | 1664 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
b72f3acb | 1665 | intel_ring_emit(ring, 0); |
71a77e07 | 1666 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1667 | intel_ring_advance(ring); |
1668 | return 0; | |
8d19215b ZN |
1669 | } |
1670 | ||
5c1143bb XH |
1671 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1672 | { | |
1673 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1674 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1675 | |
59465b5f DV |
1676 | ring->name = "render ring"; |
1677 | ring->id = RCS; | |
1678 | ring->mmio_base = RENDER_RING_BASE; | |
1679 | ||
1ec14ad3 CW |
1680 | if (INTEL_INFO(dev)->gen >= 6) { |
1681 | ring->add_request = gen6_add_request; | |
4772eaeb | 1682 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 1683 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 1684 | ring->flush = gen6_render_ring_flush; |
25c06300 BW |
1685 | ring->irq_get = gen6_ring_get_irq; |
1686 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 1687 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 1688 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 1689 | ring->set_seqno = ring_set_seqno; |
686cb5f9 | 1690 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1691 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; |
1692 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV; | |
1693 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB; | |
1950de14 | 1694 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; |
ad776f8b BW |
1695 | ring->signal_mbox[RCS] = GEN6_NOSYNC; |
1696 | ring->signal_mbox[VCS] = GEN6_VRSYNC; | |
1697 | ring->signal_mbox[BCS] = GEN6_BRSYNC; | |
1950de14 | 1698 | ring->signal_mbox[VECS] = GEN6_VERSYNC; |
c6df541c CW |
1699 | } else if (IS_GEN5(dev)) { |
1700 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1701 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1702 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 1703 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
1704 | ring->irq_get = gen5_ring_get_irq; |
1705 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
1706 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
1707 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 1708 | } else { |
8620a3a9 | 1709 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1710 | if (INTEL_INFO(dev)->gen < 4) |
1711 | ring->flush = gen2_render_ring_flush; | |
1712 | else | |
1713 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1714 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1715 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1716 | if (IS_GEN2(dev)) { |
1717 | ring->irq_get = i8xx_ring_get_irq; | |
1718 | ring->irq_put = i8xx_ring_put_irq; | |
1719 | } else { | |
1720 | ring->irq_get = i9xx_ring_get_irq; | |
1721 | ring->irq_put = i9xx_ring_put_irq; | |
1722 | } | |
e3670319 | 1723 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1724 | } |
59465b5f | 1725 | ring->write_tail = ring_write_tail; |
d7d4eedd CW |
1726 | if (IS_HASWELL(dev)) |
1727 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1728 | else if (INTEL_INFO(dev)->gen >= 6) | |
fb3256da DV |
1729 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
1730 | else if (INTEL_INFO(dev)->gen >= 4) | |
1731 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1732 | else if (IS_I830(dev) || IS_845G(dev)) | |
1733 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1734 | else | |
1735 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1736 | ring->init = init_render_ring; |
1737 | ring->cleanup = render_ring_cleanup; | |
1738 | ||
b45305fc DV |
1739 | /* Workaround batchbuffer to combat CS tlb bug. */ |
1740 | if (HAS_BROKEN_CS_TLB(dev)) { | |
1741 | struct drm_i915_gem_object *obj; | |
1742 | int ret; | |
1743 | ||
1744 | obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); | |
1745 | if (obj == NULL) { | |
1746 | DRM_ERROR("Failed to allocate batch bo\n"); | |
1747 | return -ENOMEM; | |
1748 | } | |
1749 | ||
1750 | ret = i915_gem_object_pin(obj, 0, true, false); | |
1751 | if (ret != 0) { | |
1752 | drm_gem_object_unreference(&obj->base); | |
1753 | DRM_ERROR("Failed to ping batch bo\n"); | |
1754 | return ret; | |
1755 | } | |
1756 | ||
1757 | ring->private = obj; | |
1758 | } | |
1759 | ||
1ec14ad3 | 1760 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1761 | } |
1762 | ||
e8616b6c CW |
1763 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1764 | { | |
1765 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1766 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
6b8294a4 | 1767 | int ret; |
e8616b6c | 1768 | |
59465b5f DV |
1769 | ring->name = "render ring"; |
1770 | ring->id = RCS; | |
1771 | ring->mmio_base = RENDER_RING_BASE; | |
1772 | ||
e8616b6c | 1773 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1774 | /* non-kms not supported on gen6+ */ |
1775 | return -ENODEV; | |
e8616b6c | 1776 | } |
28f0cbf7 DV |
1777 | |
1778 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1779 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1780 | * the special gen5 functions. */ | |
1781 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1782 | if (INTEL_INFO(dev)->gen < 4) |
1783 | ring->flush = gen2_render_ring_flush; | |
1784 | else | |
1785 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1786 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1787 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
1788 | if (IS_GEN2(dev)) { |
1789 | ring->irq_get = i8xx_ring_get_irq; | |
1790 | ring->irq_put = i8xx_ring_put_irq; | |
1791 | } else { | |
1792 | ring->irq_get = i9xx_ring_get_irq; | |
1793 | ring->irq_put = i9xx_ring_put_irq; | |
1794 | } | |
28f0cbf7 | 1795 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1796 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1797 | if (INTEL_INFO(dev)->gen >= 4) |
1798 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1799 | else if (IS_I830(dev) || IS_845G(dev)) | |
1800 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1801 | else | |
1802 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1803 | ring->init = init_render_ring; |
1804 | ring->cleanup = render_ring_cleanup; | |
e8616b6c CW |
1805 | |
1806 | ring->dev = dev; | |
1807 | INIT_LIST_HEAD(&ring->active_list); | |
1808 | INIT_LIST_HEAD(&ring->request_list); | |
e8616b6c CW |
1809 | |
1810 | ring->size = size; | |
1811 | ring->effective_size = ring->size; | |
17f10fdc | 1812 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
e8616b6c CW |
1813 | ring->effective_size -= 128; |
1814 | ||
4225d0f2 DV |
1815 | ring->virtual_start = ioremap_wc(start, size); |
1816 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1817 | DRM_ERROR("can not ioremap virtual address for" |
1818 | " ring buffer\n"); | |
1819 | return -ENOMEM; | |
1820 | } | |
1821 | ||
6b8294a4 CW |
1822 | if (!I915_NEED_GFX_HWS(dev)) { |
1823 | ret = init_phys_hws_pga(ring); | |
1824 | if (ret) | |
1825 | return ret; | |
1826 | } | |
1827 | ||
e8616b6c CW |
1828 | return 0; |
1829 | } | |
1830 | ||
5c1143bb XH |
1831 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1832 | { | |
1833 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1834 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1835 | |
58fa3835 DV |
1836 | ring->name = "bsd ring"; |
1837 | ring->id = VCS; | |
1838 | ||
0fd2c201 | 1839 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1840 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1841 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1842 | /* gen6 bsd needs a special wa for tail updates */ |
1843 | if (IS_GEN6(dev)) | |
1844 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 1845 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
1846 | ring->add_request = gen6_add_request; |
1847 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 1848 | ring->set_seqno = ring_set_seqno; |
cc609d5d | 1849 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
58fa3835 DV |
1850 | ring->irq_get = gen6_ring_get_irq; |
1851 | ring->irq_put = gen6_ring_put_irq; | |
1852 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1853 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1854 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR; |
1855 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1856 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB; | |
1950de14 | 1857 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE; |
ad776f8b BW |
1858 | ring->signal_mbox[RCS] = GEN6_RVSYNC; |
1859 | ring->signal_mbox[VCS] = GEN6_NOSYNC; | |
1860 | ring->signal_mbox[BCS] = GEN6_BVSYNC; | |
1950de14 | 1861 | ring->signal_mbox[VECS] = GEN6_VEVSYNC; |
58fa3835 DV |
1862 | } else { |
1863 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1864 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1865 | ring->add_request = i9xx_add_request; |
58fa3835 | 1866 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 1867 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 1868 | if (IS_GEN5(dev)) { |
cc609d5d | 1869 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
1870 | ring->irq_get = gen5_ring_get_irq; |
1871 | ring->irq_put = gen5_ring_put_irq; | |
1872 | } else { | |
e3670319 | 1873 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1874 | ring->irq_get = i9xx_ring_get_irq; |
1875 | ring->irq_put = i9xx_ring_put_irq; | |
1876 | } | |
fb3256da | 1877 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1878 | } |
1879 | ring->init = init_ring_common; | |
1880 | ||
1ec14ad3 | 1881 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1882 | } |
549f7365 CW |
1883 | |
1884 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1885 | { | |
1886 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1887 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1888 | |
3535d9dd DV |
1889 | ring->name = "blitter ring"; |
1890 | ring->id = BCS; | |
1891 | ||
1892 | ring->mmio_base = BLT_RING_BASE; | |
1893 | ring->write_tail = ring_write_tail; | |
ea251324 | 1894 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
1895 | ring->add_request = gen6_add_request; |
1896 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 1897 | ring->set_seqno = ring_set_seqno; |
cc609d5d | 1898 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; |
3535d9dd DV |
1899 | ring->irq_get = gen6_ring_get_irq; |
1900 | ring->irq_put = gen6_ring_put_irq; | |
1901 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1902 | ring->sync_to = gen6_ring_sync; |
5586181f BW |
1903 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR; |
1904 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV; | |
1905 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
1950de14 | 1906 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE; |
ad776f8b BW |
1907 | ring->signal_mbox[RCS] = GEN6_RBSYNC; |
1908 | ring->signal_mbox[VCS] = GEN6_VBSYNC; | |
1909 | ring->signal_mbox[BCS] = GEN6_NOSYNC; | |
1950de14 | 1910 | ring->signal_mbox[VECS] = GEN6_VEBSYNC; |
3535d9dd | 1911 | ring->init = init_ring_common; |
549f7365 | 1912 | |
1ec14ad3 | 1913 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1914 | } |
a7b9761d | 1915 | |
9a8a2213 BW |
1916 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
1917 | { | |
1918 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1919 | struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; | |
1920 | ||
1921 | ring->name = "video enhancement ring"; | |
1922 | ring->id = VECS; | |
1923 | ||
1924 | ring->mmio_base = VEBOX_RING_BASE; | |
1925 | ring->write_tail = ring_write_tail; | |
1926 | ring->flush = gen6_ring_flush; | |
1927 | ring->add_request = gen6_add_request; | |
1928 | ring->get_seqno = gen6_ring_get_seqno; | |
1929 | ring->set_seqno = ring_set_seqno; | |
1930 | ring->irq_enable_mask = 0; | |
1931 | ring->irq_get = NULL; | |
1932 | ring->irq_put = NULL; | |
1933 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1934 | ring->sync_to = gen6_ring_sync; | |
1935 | ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER; | |
1936 | ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
1937 | ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
1938 | ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
1939 | ring->signal_mbox[RCS] = GEN6_RVESYNC; | |
1940 | ring->signal_mbox[VCS] = GEN6_VVESYNC; | |
1941 | ring->signal_mbox[BCS] = GEN6_BVESYNC; | |
1942 | ring->signal_mbox[VECS] = GEN6_NOSYNC; | |
1943 | ring->init = init_ring_common; | |
1944 | ||
1945 | return intel_init_ring_buffer(dev, ring); | |
1946 | } | |
1947 | ||
a7b9761d CW |
1948 | int |
1949 | intel_ring_flush_all_caches(struct intel_ring_buffer *ring) | |
1950 | { | |
1951 | int ret; | |
1952 | ||
1953 | if (!ring->gpu_caches_dirty) | |
1954 | return 0; | |
1955 | ||
1956 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1957 | if (ret) | |
1958 | return ret; | |
1959 | ||
1960 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
1961 | ||
1962 | ring->gpu_caches_dirty = false; | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | int | |
1967 | intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring) | |
1968 | { | |
1969 | uint32_t flush_domains; | |
1970 | int ret; | |
1971 | ||
1972 | flush_domains = 0; | |
1973 | if (ring->gpu_caches_dirty) | |
1974 | flush_domains = I915_GEM_GPU_DOMAINS; | |
1975 | ||
1976 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1977 | if (ret) | |
1978 | return ret; | |
1979 | ||
1980 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
1981 | ||
1982 | ring->gpu_caches_dirty = false; | |
1983 | return 0; | |
1984 | } |