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drm/i915: Refine tracepoints
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
62fdfeaf 32#include "i915_drv.h"
8187a2b7 33#include "i915_drm.h"
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
c7dca47b
CW		 37static inline int ring_space(struct intel_ring_buffer *ring)
38{
39 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
40 if (space < 0)
41 space += ring->size;
42 return space;
43}
44
6f392d54
CW		 45static u32 i915_gem_get_seqno(struct drm_device *dev)
46{
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 u32 seqno;
49
50 seqno = dev_priv->next_seqno;
51
52 /* reserve 0 for non-seqno */
53 if (++dev_priv->next_seqno == 0)
54 dev_priv->next_seqno = 1;
55
56 return seqno;
57}
58
b72f3acb 59static int
78501eac 60render_ring_flush(struct intel_ring_buffer *ring,
ab6f8e32
CW		 61 u32 invalidate_domains,
62 u32 flush_domains)
62fdfeaf 63{
78501eac 64 struct drm_device *dev = ring->dev;
6f392d54 65 u32 cmd;
b72f3acb 66 int ret;
6f392d54 67
62fdfeaf
EA		 68 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69 /*
70 * read/write caches:
71 *
72 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
74 * also flushed at 2d versus 3d pipeline switches.
75 *
76 * read-only caches:
77 *
78 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79 * MI_READ_FLUSH is set, and is always flushed on 965.
80 *
81 * I915_GEM_DOMAIN_COMMAND may not exist?
82 *
83 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84 * invalidated when MI_EXE_FLUSH is set.
85 *
86 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87 * invalidated with every MI_FLUSH.
88 *
89 * TLBs:
90 *
91 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94 * are flushed at any MI_FLUSH.
95 */
96
97 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98 if ((invalidate_domains|flush_domains) &
99 I915_GEM_DOMAIN_RENDER)
100 cmd &= ~MI_NO_WRITE_FLUSH;
a6c45cf0 101 if (INTEL_INFO(dev)->gen < 4) {
62fdfeaf
EA		 102 /*
103 * On the 965, the sampler cache always gets flushed
104 * and this bit is reserved.
105 */
106 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107 cmd |= MI_READ_FLUSH;
108 }
109 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110 cmd |= MI_EXE_FLUSH;
111
70eac33e
CW		 112 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
113 (IS_G4X(dev) || IS_GEN5(dev)))
114 cmd |= MI_INVALIDATE_ISP;
115
b72f3acb
CW		 116 ret = intel_ring_begin(ring, 2);
117 if (ret)
118 return ret;
119
120 intel_ring_emit(ring, cmd);
121 intel_ring_emit(ring, MI_NOOP);
122 intel_ring_advance(ring);
62fdfeaf 123 }
b72f3acb
CW		 124
125 return 0;
8187a2b7
ZN		 126}
127
78501eac 128static void ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 129 u32 value)
d46eefa2 130{
78501eac 131 drm_i915_private_t *dev_priv = ring->dev->dev_private;
297b0c5b 132 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 133}
134
78501eac 135u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
8187a2b7 136{
78501eac
CW		 137 drm_i915_private_t *dev_priv = ring->dev->dev_private;
138 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
3d281d8c 139 RING_ACTHD(ring->mmio_base) : ACTHD;
8187a2b7
ZN		 140
141 return I915_READ(acthd_reg);
142}
143
78501eac 144static int init_ring_common(struct intel_ring_buffer *ring)
8187a2b7 145{
78501eac 146 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 147 struct drm_i915_gem_object *obj = ring->obj;
8187a2b7 148 u32 head;
8187a2b7
ZN		 149
150 /* Stop the ring if it's running. */
7f2ab699 151 I915_WRITE_CTL(ring, 0);
570ef608 152 I915_WRITE_HEAD(ring, 0);
78501eac 153 ring->write_tail(ring, 0);
8187a2b7
ZN		 154
155 /* Initialize the ring. */
05394f39 156 I915_WRITE_START(ring, obj->gtt_offset);
570ef608 157 head = I915_READ_HEAD(ring) & HEAD_ADDR;
8187a2b7
ZN		 158
159 /* G45 ring initialization fails to reset head to zero */
160 if (head != 0) {
6fd0d56e
CW		 161 DRM_DEBUG_KMS("%s head not reset to zero "
162 "ctl %08x head %08x tail %08x start %08x\n",
163 ring->name,
164 I915_READ_CTL(ring),
165 I915_READ_HEAD(ring),
166 I915_READ_TAIL(ring),
167 I915_READ_START(ring));
8187a2b7 168
570ef608 169 I915_WRITE_HEAD(ring, 0);
8187a2b7 170
6fd0d56e
CW		 171 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
172 DRM_ERROR("failed to set %s head to zero "
173 "ctl %08x head %08x tail %08x start %08x\n",
174 ring->name,
175 I915_READ_CTL(ring),
176 I915_READ_HEAD(ring),
177 I915_READ_TAIL(ring),
178 I915_READ_START(ring));
179 }
8187a2b7
ZN		 180 }
181
7f2ab699 182 I915_WRITE_CTL(ring,
ae69b42a 183 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
6aa56062 184 | RING_REPORT_64K | RING_VALID);
8187a2b7 185
8187a2b7 186 /* If the head is still not zero, the ring is dead */
176f28eb 187 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
05394f39 188 I915_READ_START(ring) != obj->gtt_offset ||
176f28eb 189 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
e74cfed5
CW		 190 DRM_ERROR("%s initialization failed "
191 "ctl %08x head %08x tail %08x start %08x\n",
192 ring->name,
193 I915_READ_CTL(ring),
194 I915_READ_HEAD(ring),
195 I915_READ_TAIL(ring),
196 I915_READ_START(ring));
197 return -EIO;
8187a2b7
ZN		 198 }
199
78501eac
CW		 200 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
201 i915_kernel_lost_context(ring->dev);
8187a2b7 202 else {
c7dca47b 203 ring->head = I915_READ_HEAD(ring);
870e86dd 204 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
c7dca47b 205 ring->space = ring_space(ring);
8187a2b7 206 }
1ec14ad3 207
8187a2b7
ZN		 208 return 0;
209}
210
c6df541c
CW		 211/*
212 * 965+ support PIPE_CONTROL commands, which provide finer grained control
213 * over cache flushing.
214 */
215struct pipe_control {
216 struct drm_i915_gem_object *obj;
217 volatile u32 *cpu_page;
218 u32 gtt_offset;
219};
220
221static int
222init_pipe_control(struct intel_ring_buffer *ring)
223{
224 struct pipe_control *pc;
225 struct drm_i915_gem_object *obj;
226 int ret;
227
228 if (ring->private)
229 return 0;
230
231 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
232 if (!pc)
233 return -ENOMEM;
234
235 obj = i915_gem_alloc_object(ring->dev, 4096);
236 if (obj == NULL) {
237 DRM_ERROR("Failed to allocate seqno page\n");
238 ret = -ENOMEM;
239 goto err;
240 }
241 obj->agp_type = AGP_USER_CACHED_MEMORY;
242
243 ret = i915_gem_object_pin(obj, 4096, true);
244 if (ret)
245 goto err_unref;
246
247 pc->gtt_offset = obj->gtt_offset;
248 pc->cpu_page = kmap(obj->pages[0]);
249 if (pc->cpu_page == NULL)
250 goto err_unpin;
251
252 pc->obj = obj;
253 ring->private = pc;
254 return 0;
255
256err_unpin:
257 i915_gem_object_unpin(obj);
258err_unref:
259 drm_gem_object_unreference(&obj->base);
260err:
261 kfree(pc);
262 return ret;
263}
264
265static void
266cleanup_pipe_control(struct intel_ring_buffer *ring)
267{
268 struct pipe_control *pc = ring->private;
269 struct drm_i915_gem_object *obj;
270
271 if (!ring->private)
272 return;
273
274 obj = pc->obj;
275 kunmap(obj->pages[0]);
276 i915_gem_object_unpin(obj);
277 drm_gem_object_unreference(&obj->base);
278
279 kfree(pc);
280 ring->private = NULL;
281}
282
78501eac 283static int init_render_ring(struct intel_ring_buffer *ring)
8187a2b7 284{
78501eac 285 struct drm_device *dev = ring->dev;
1ec14ad3 286 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 287 int ret = init_ring_common(ring);
a69ffdbf 288
a6c45cf0 289 if (INTEL_INFO(dev)->gen > 3) {
78501eac 290 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
a69ffdbf
ZW		 291 if (IS_GEN6(dev))
292 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
293 I915_WRITE(MI_MODE, mode);
8187a2b7 294 }
78501eac 295
c6df541c
CW		 296 if (INTEL_INFO(dev)->gen >= 6) {
297 } else if (IS_GEN5(dev)) {
298 ret = init_pipe_control(ring);
299 if (ret)
300 return ret;
301 }
302
8187a2b7
ZN		 303 return ret;
304}
305
c6df541c
CW		 306static void render_ring_cleanup(struct intel_ring_buffer *ring)
307{
308 if (!ring->private)
309 return;
310
311 cleanup_pipe_control(ring);
312}
313
1ec14ad3
CW		 314static void
315update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
316{
317 struct drm_device *dev = ring->dev;
318 struct drm_i915_private *dev_priv = dev->dev_private;
319 int id;
320
321 /*
322 * cs -> 1 = vcs, 0 = bcs
323 * vcs -> 1 = bcs, 0 = cs,
324 * bcs -> 1 = cs, 0 = vcs.
325 */
326 id = ring - dev_priv->ring;
327 id += 2 - i;
328 id %= 3;
329
330 intel_ring_emit(ring,
331 MI_SEMAPHORE_MBOX |
332 MI_SEMAPHORE_REGISTER |
333 MI_SEMAPHORE_UPDATE);
334 intel_ring_emit(ring, seqno);
335 intel_ring_emit(ring,
336 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
337}
338
339static int
340gen6_add_request(struct intel_ring_buffer *ring,
341 u32 *result)
342{
343 u32 seqno;
344 int ret;
345
346 ret = intel_ring_begin(ring, 10);
347 if (ret)
348 return ret;
349
350 seqno = i915_gem_get_seqno(ring->dev);
351 update_semaphore(ring, 0, seqno);
352 update_semaphore(ring, 1, seqno);
353
354 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
355 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
356 intel_ring_emit(ring, seqno);
357 intel_ring_emit(ring, MI_USER_INTERRUPT);
358 intel_ring_advance(ring);
359
360 *result = seqno;
361 return 0;
362}
363
364int
365intel_ring_sync(struct intel_ring_buffer *ring,
366 struct intel_ring_buffer *to,
367 u32 seqno)
368{
369 int ret;
370
371 ret = intel_ring_begin(ring, 4);
372 if (ret)
373 return ret;
374
375 intel_ring_emit(ring,
376 MI_SEMAPHORE_MBOX |
377 MI_SEMAPHORE_REGISTER |
378 intel_ring_sync_index(ring, to) << 17 |
379 MI_SEMAPHORE_COMPARE);
380 intel_ring_emit(ring, seqno);
381 intel_ring_emit(ring, 0);
382 intel_ring_emit(ring, MI_NOOP);
383 intel_ring_advance(ring);
384
385 return 0;
386}
387
c6df541c
CW		 388#define PIPE_CONTROL_FLUSH(ring__, addr__) \
389do { \
390 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
391 PIPE_CONTROL_DEPTH_STALL | 2); \
392 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
393 intel_ring_emit(ring__, 0); \
394 intel_ring_emit(ring__, 0); \
395} while (0)
396
397static int
398pc_render_add_request(struct intel_ring_buffer *ring,
399 u32 *result)
400{
401 struct drm_device *dev = ring->dev;
402 u32 seqno = i915_gem_get_seqno(dev);
403 struct pipe_control *pc = ring->private;
404 u32 scratch_addr = pc->gtt_offset + 128;
405 int ret;
406
407 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
408 * incoherent with writes to memory, i.e. completely fubar,
409 * so we need to use PIPE_NOTIFY instead.
410 *
411 * However, we also need to workaround the qword write
412 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
413 * memory before requesting an interrupt.
414 */
415 ret = intel_ring_begin(ring, 32);
416 if (ret)
417 return ret;
418
419 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
420 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
421 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
422 intel_ring_emit(ring, seqno);
423 intel_ring_emit(ring, 0);
424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
425 scratch_addr += 128; /* write to separate cachelines */
426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
427 scratch_addr += 128;
428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
429 scratch_addr += 128;
430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
431 scratch_addr += 128;
432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
433 scratch_addr += 128;
434 PIPE_CONTROL_FLUSH(ring, scratch_addr);
435 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
436 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
437 PIPE_CONTROL_NOTIFY);
438 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
439 intel_ring_emit(ring, seqno);
440 intel_ring_emit(ring, 0);
441 intel_ring_advance(ring);
442
443 *result = seqno;
444 return 0;
445}
446
1ec14ad3
CW		 447static int
448render_ring_add_request(struct intel_ring_buffer *ring,
449 u32 *result)
450{
451 struct drm_device *dev = ring->dev;
452 u32 seqno = i915_gem_get_seqno(dev);
453 int ret;
3cce469c 454
1ec14ad3
CW		 455 ret = intel_ring_begin(ring, 4);
456 if (ret)
457 return ret;
3cce469c 458
1ec14ad3
CW		 459 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
460 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
461 intel_ring_emit(ring, seqno);
462 intel_ring_emit(ring, MI_USER_INTERRUPT);
3cce469c 463 intel_ring_advance(ring);
1ec14ad3 464
3cce469c
CW		 465 *result = seqno;
466 return 0;
62fdfeaf
EA		 467}
468
8187a2b7 469static u32
1ec14ad3 470ring_get_seqno(struct intel_ring_buffer *ring)
8187a2b7 471{
1ec14ad3
CW		 472 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
473}
474
c6df541c
CW		 475static u32
476pc_render_get_seqno(struct intel_ring_buffer *ring)
477{
478 struct pipe_control *pc = ring->private;
479 return pc->cpu_page[0];
480}
481
0f46832f
CW		 482static void
483ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
484{
485 dev_priv->gt_irq_mask &= ~mask;
486 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
487 POSTING_READ(GTIMR);
488}
489
490static void
491ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
492{
493 dev_priv->gt_irq_mask |= mask;
494 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
495 POSTING_READ(GTIMR);
496}
497
498static void
499i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
500{
501 dev_priv->irq_mask &= ~mask;
502 I915_WRITE(IMR, dev_priv->irq_mask);
503 POSTING_READ(IMR);
504}
505
506static void
507i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
508{
509 dev_priv->irq_mask |= mask;
510 I915_WRITE(IMR, dev_priv->irq_mask);
511 POSTING_READ(IMR);
512}
513
b13c2b96 514static bool
1ec14ad3 515render_ring_get_irq(struct intel_ring_buffer *ring)
62fdfeaf 516{
78501eac 517 struct drm_device *dev = ring->dev;
01a03331 518 drm_i915_private_t *dev_priv = dev->dev_private;
62fdfeaf 519
b13c2b96
CW		 520 if (!dev->irq_enabled)
521 return false;
522
0dc79fb2 523 spin_lock(&ring->irq_lock);
01a03331 524 if (ring->irq_refcount++ == 0) {
62fdfeaf 525 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 526 ironlake_enable_irq(dev_priv,
527 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
62fdfeaf
EA		 528 else
529 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
530 }
0dc79fb2 531 spin_unlock(&ring->irq_lock);
b13c2b96
CW		 532
533 return true;
62fdfeaf
EA		 534}
535
8187a2b7 536static void
1ec14ad3 537render_ring_put_irq(struct intel_ring_buffer *ring)
62fdfeaf 538{
78501eac 539 struct drm_device *dev = ring->dev;
01a03331 540 drm_i915_private_t *dev_priv = dev->dev_private;
62fdfeaf 541
0dc79fb2 542 spin_lock(&ring->irq_lock);
01a03331 543 if (--ring->irq_refcount == 0) {
62fdfeaf 544 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 545 ironlake_disable_irq(dev_priv,
546 GT_USER_INTERRUPT |
547 GT_PIPE_NOTIFY);
62fdfeaf
EA		 548 else
549 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
550 }
0dc79fb2 551 spin_unlock(&ring->irq_lock);
62fdfeaf
EA		 552}
553
78501eac 554void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
8187a2b7 555{
78501eac
CW		 556 drm_i915_private_t *dev_priv = ring->dev->dev_private;
557 u32 mmio = IS_GEN6(ring->dev) ?
558 RING_HWS_PGA_GEN6(ring->mmio_base) :
559 RING_HWS_PGA(ring->mmio_base);
560 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
561 POSTING_READ(mmio);
8187a2b7
ZN		 562}
563
b72f3acb 564static int
78501eac
CW		 565bsd_ring_flush(struct intel_ring_buffer *ring,
566 u32 invalidate_domains,
567 u32 flush_domains)
d1b851fc 568{
b72f3acb
CW		 569 int ret;
570
1ec14ad3 571 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 572 return 0;
1ec14ad3 573
b72f3acb
CW		 574 ret = intel_ring_begin(ring, 2);
575 if (ret)
576 return ret;
577
578 intel_ring_emit(ring, MI_FLUSH);
579 intel_ring_emit(ring, MI_NOOP);
580 intel_ring_advance(ring);
581 return 0;
d1b851fc
ZN		 582}
583
3cce469c 584static int
78501eac 585ring_add_request(struct intel_ring_buffer *ring,
3cce469c 586 u32 *result)
d1b851fc
ZN		 587{
588 u32 seqno;
3cce469c
CW		 589 int ret;
590
591 ret = intel_ring_begin(ring, 4);
592 if (ret)
593 return ret;
6f392d54 594
78501eac 595 seqno = i915_gem_get_seqno(ring->dev);
6f392d54 596
3cce469c
CW		 597 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
598 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
599 intel_ring_emit(ring, seqno);
600 intel_ring_emit(ring, MI_USER_INTERRUPT);
601 intel_ring_advance(ring);
d1b851fc 602
3cce469c
CW		 603 *result = seqno;
604 return 0;
d1b851fc
ZN		 605}
606
b13c2b96 607static bool
1ec14ad3 608ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
d1b851fc 609{
1ec14ad3 610 struct drm_device *dev = ring->dev;
01a03331 611 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 612
b13c2b96
CW		 613 if (!dev->irq_enabled)
614 return false;
615
0dc79fb2 616 spin_lock(&ring->irq_lock);
01a03331 617 if (ring->irq_refcount++ == 0)
0f46832f 618 ironlake_enable_irq(dev_priv, flag);
0dc79fb2 619 spin_unlock(&ring->irq_lock);
b13c2b96
CW		 620
621 return true;
d1b851fc 622}
1ec14ad3 623
d1b851fc 624static void
1ec14ad3 625ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
d1b851fc 626{
1ec14ad3 627 struct drm_device *dev = ring->dev;
01a03331 628 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 629
0dc79fb2 630 spin_lock(&ring->irq_lock);
01a03331 631 if (--ring->irq_refcount == 0)
0f46832f 632 ironlake_disable_irq(dev_priv, flag);
0dc79fb2 633 spin_unlock(&ring->irq_lock);
0f46832f
CW		 634}
635
636static bool
637gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
638{
639 struct drm_device *dev = ring->dev;
01a03331 640 drm_i915_private_t *dev_priv = dev->dev_private;
0f46832f
CW		 641
642 if (!dev->irq_enabled)
643 return false;
644
0dc79fb2 645 spin_lock(&ring->irq_lock);
01a03331 646 if (ring->irq_refcount++ == 0) {
0f46832f
CW		 647 ring->irq_mask &= ~rflag;
648 I915_WRITE_IMR(ring, ring->irq_mask);
649 ironlake_enable_irq(dev_priv, gflag);
0f46832f 650 }
0dc79fb2 651 spin_unlock(&ring->irq_lock);
0f46832f
CW		 652
653 return true;
654}
655
656static void
657gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
658{
659 struct drm_device *dev = ring->dev;
01a03331 660 drm_i915_private_t *dev_priv = dev->dev_private;
0f46832f 661
0dc79fb2 662 spin_lock(&ring->irq_lock);
01a03331 663 if (--ring->irq_refcount == 0) {
0f46832f
CW		 664 ring->irq_mask |= rflag;
665 I915_WRITE_IMR(ring, ring->irq_mask);
666 ironlake_disable_irq(dev_priv, gflag);
1ec14ad3 667 }
0dc79fb2 668 spin_unlock(&ring->irq_lock);
d1b851fc
ZN		 669}
670
b13c2b96 671static bool
1ec14ad3 672bsd_ring_get_irq(struct intel_ring_buffer *ring)
d1b851fc 673{
b13c2b96 674 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
1ec14ad3
CW		 675}
676static void
677bsd_ring_put_irq(struct intel_ring_buffer *ring)
678{
b13c2b96 679 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
d1b851fc
ZN		 680}
681
682static int
c4e7a414 683ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
d1b851fc 684{
e1f99ce6 685 int ret;
78501eac 686
e1f99ce6
CW		 687 ret = intel_ring_begin(ring, 2);
688 if (ret)
689 return ret;
690
78501eac 691 intel_ring_emit(ring,
c4e7a414 692 MI_BATCH_BUFFER_START | (2 << 6) |
78501eac 693 MI_BATCH_NON_SECURE_I965);
c4e7a414 694 intel_ring_emit(ring, offset);
78501eac
CW		 695 intel_ring_advance(ring);
696
d1b851fc
ZN		 697 return 0;
698}
699
8187a2b7 700static int
78501eac 701render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 702 u32 offset, u32 len)
62fdfeaf 703{
78501eac 704 struct drm_device *dev = ring->dev;
c4e7a414 705 int ret;
62fdfeaf 706
c4e7a414
CW		 707 if (IS_I830(dev) || IS_845G(dev)) {
708 ret = intel_ring_begin(ring, 4);
709 if (ret)
710 return ret;
62fdfeaf 711
c4e7a414
CW		 712 intel_ring_emit(ring, MI_BATCH_BUFFER);
713 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
714 intel_ring_emit(ring, offset + len - 8);
715 intel_ring_emit(ring, 0);
716 } else {
717 ret = intel_ring_begin(ring, 2);
718 if (ret)
719 return ret;
e1f99ce6 720
c4e7a414
CW		 721 if (INTEL_INFO(dev)->gen >= 4) {
722 intel_ring_emit(ring,
723 MI_BATCH_BUFFER_START | (2 << 6) |
724 MI_BATCH_NON_SECURE_I965);
725 intel_ring_emit(ring, offset);
62fdfeaf 726 } else {
c4e7a414
CW		 727 intel_ring_emit(ring,
728 MI_BATCH_BUFFER_START | (2 << 6));
729 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
62fdfeaf
EA		 730 }
731 }
c4e7a414 732 intel_ring_advance(ring);
62fdfeaf 733
62fdfeaf
EA		 734 return 0;
735}
736
78501eac 737static void cleanup_status_page(struct intel_ring_buffer *ring)
62fdfeaf 738{
78501eac 739 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 740 struct drm_i915_gem_object *obj;
62fdfeaf 741
8187a2b7
ZN		 742 obj = ring->status_page.obj;
743 if (obj == NULL)
62fdfeaf 744 return;
62fdfeaf 745
05394f39 746 kunmap(obj->pages[0]);
62fdfeaf 747 i915_gem_object_unpin(obj);
05394f39 748 drm_gem_object_unreference(&obj->base);
8187a2b7 749 ring->status_page.obj = NULL;
62fdfeaf
EA		 750
751 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 752}
753
78501eac 754static int init_status_page(struct intel_ring_buffer *ring)
62fdfeaf 755{
78501eac 756 struct drm_device *dev = ring->dev;
62fdfeaf 757 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 758 struct drm_i915_gem_object *obj;
62fdfeaf
EA		 759 int ret;
760
62fdfeaf
EA		 761 obj = i915_gem_alloc_object(dev, 4096);
762 if (obj == NULL) {
763 DRM_ERROR("Failed to allocate status page\n");
764 ret = -ENOMEM;
765 goto err;
766 }
05394f39 767 obj->agp_type = AGP_USER_CACHED_MEMORY;
62fdfeaf 768
75e9e915 769 ret = i915_gem_object_pin(obj, 4096, true);
62fdfeaf 770 if (ret != 0) {
62fdfeaf
EA		 771 goto err_unref;
772 }
773
05394f39
CW		 774 ring->status_page.gfx_addr = obj->gtt_offset;
775 ring->status_page.page_addr = kmap(obj->pages[0]);
8187a2b7 776 if (ring->status_page.page_addr == NULL) {
62fdfeaf 777 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 778 goto err_unpin;
779 }
8187a2b7
ZN		 780 ring->status_page.obj = obj;
781 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 782
78501eac 783 intel_ring_setup_status_page(ring);
8187a2b7
ZN		 784 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
785 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 786
787 return 0;
788
789err_unpin:
790 i915_gem_object_unpin(obj);
791err_unref:
05394f39 792 drm_gem_object_unreference(&obj->base);
62fdfeaf 793err:
8187a2b7 794 return ret;
62fdfeaf
EA		 795}
796
8187a2b7 797int intel_init_ring_buffer(struct drm_device *dev,
ab6f8e32 798 struct intel_ring_buffer *ring)
62fdfeaf 799{
05394f39 800 struct drm_i915_gem_object *obj;
dd785e35
CW		 801 int ret;
802
8187a2b7 803 ring->dev = dev;
23bc5982
CW		 804 INIT_LIST_HEAD(&ring->active_list);
805 INIT_LIST_HEAD(&ring->request_list);
64193406 806 INIT_LIST_HEAD(&ring->gpu_write_list);
0dc79fb2
CW		 807
808 spin_lock_init(&ring->irq_lock);
0f46832f 809 ring->irq_mask = ~0;
62fdfeaf 810
8187a2b7 811 if (I915_NEED_GFX_HWS(dev)) {
78501eac 812 ret = init_status_page(ring);
8187a2b7
ZN		 813 if (ret)
814 return ret;
815 }
62fdfeaf 816
8187a2b7 817 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 818 if (obj == NULL) {
819 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 820 ret = -ENOMEM;
dd785e35 821 goto err_hws;
62fdfeaf 822 }
62fdfeaf 823
05394f39 824 ring->obj = obj;
8187a2b7 825
75e9e915 826 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
dd785e35
CW		 827 if (ret)
828 goto err_unref;
62fdfeaf 829
8187a2b7 830 ring->map.size = ring->size;
05394f39 831 ring->map.offset = dev->agp->base + obj->gtt_offset;
62fdfeaf
EA		 832 ring->map.type = 0;
833 ring->map.flags = 0;
834 ring->map.mtrr = 0;
835
836 drm_core_ioremap_wc(&ring->map, dev);
837 if (ring->map.handle == NULL) {
838 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 839 ret = -EINVAL;
dd785e35 840 goto err_unpin;
62fdfeaf
EA		 841 }
842
8187a2b7 843 ring->virtual_start = ring->map.handle;
78501eac 844 ret = ring->init(ring);
dd785e35
CW		 845 if (ret)
846 goto err_unmap;
62fdfeaf 847
55249baa
CW		 848 /* Workaround an erratum on the i830 which causes a hang if
849 * the TAIL pointer points to within the last 2 cachelines
850 * of the buffer.
851 */
852 ring->effective_size = ring->size;
853 if (IS_I830(ring->dev))
854 ring->effective_size -= 128;
855
c584fe47 856 return 0;
dd785e35
CW		 857
858err_unmap:
859 drm_core_ioremapfree(&ring->map, dev);
860err_unpin:
861 i915_gem_object_unpin(obj);
862err_unref:
05394f39
CW		 863 drm_gem_object_unreference(&obj->base);
864 ring->obj = NULL;
dd785e35 865err_hws:
78501eac 866 cleanup_status_page(ring);
8187a2b7 867 return ret;
62fdfeaf
EA		 868}
869
78501eac 870void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 871{
33626e6a
CW		 872 struct drm_i915_private *dev_priv;
873 int ret;
874
05394f39 875 if (ring->obj == NULL)
62fdfeaf
EA		 876 return;
877
33626e6a
CW		 878 /* Disable the ring buffer. The ring must be idle at this point */
879 dev_priv = ring->dev->dev_private;
880 ret = intel_wait_ring_buffer(ring, ring->size - 8);
29ee3991
CW		 881 if (ret)
882 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
883 ring->name, ret);
884
33626e6a
CW		 885 I915_WRITE_CTL(ring, 0);
886
78501eac 887 drm_core_ioremapfree(&ring->map, ring->dev);
62fdfeaf 888
05394f39
CW		 889 i915_gem_object_unpin(ring->obj);
890 drm_gem_object_unreference(&ring->obj->base);
891 ring->obj = NULL;
78501eac 892
8d19215b
ZN		 893 if (ring->cleanup)
894 ring->cleanup(ring);
895
78501eac 896 cleanup_status_page(ring);
62fdfeaf
EA		 897}
898
78501eac 899static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 900{
8187a2b7 901 unsigned int *virt;
55249baa 902 int rem = ring->size - ring->tail;
62fdfeaf 903
8187a2b7 904 if (ring->space < rem) {
78501eac 905 int ret = intel_wait_ring_buffer(ring, rem);
62fdfeaf
EA		 906 if (ret)
907 return ret;
908 }
62fdfeaf 909
8187a2b7 910 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1741dd4a
CW		 911 rem /= 8;
912 while (rem--) {
62fdfeaf 913 *virt++ = MI_NOOP;
1741dd4a
CW		 914 *virt++ = MI_NOOP;
915 }
62fdfeaf 916
8187a2b7 917 ring->tail = 0;
c7dca47b 918 ring->space = ring_space(ring);
62fdfeaf
EA		 919
920 return 0;
921}
922
78501eac 923int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
62fdfeaf 924{
78501eac 925 struct drm_device *dev = ring->dev;
cae5852d 926 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 927 unsigned long end;
6aa56062
CW		 928 u32 head;
929
c7dca47b
CW		 930 /* If the reported head position has wrapped or hasn't advanced,
931 * fallback to the slow and accurate path.
932 */
933 head = intel_read_status_page(ring, 4);
934 if (head > ring->head) {
935 ring->head = head;
936 ring->space = ring_space(ring);
937 if (ring->space >= n)
938 return 0;
939 }
940
db53a302 941 trace_i915_ring_wait_begin(ring);
8187a2b7
ZN		 942 end = jiffies + 3 * HZ;
943 do {
c7dca47b
CW		 944 ring->head = I915_READ_HEAD(ring);
945 ring->space = ring_space(ring);
62fdfeaf 946 if (ring->space >= n) {
db53a302 947 trace_i915_ring_wait_end(ring);
62fdfeaf
EA		 948 return 0;
949 }
950
951 if (dev->primary->master) {
952 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
953 if (master_priv->sarea_priv)
954 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
955 }
d1b851fc 956
e60a0b10 957 msleep(1);
f4e0b29b
CW		 958 if (atomic_read(&dev_priv->mm.wedged))
959 return -EAGAIN;
8187a2b7 960 } while (!time_after(jiffies, end));
db53a302 961 trace_i915_ring_wait_end(ring);
8187a2b7
ZN		 962 return -EBUSY;
963}
62fdfeaf 964
e1f99ce6
CW		 965int intel_ring_begin(struct intel_ring_buffer *ring,
966 int num_dwords)
8187a2b7 967{
21dd3734 968 struct drm_i915_private *dev_priv = ring->dev->dev_private;
be26a10b 969 int n = 4*num_dwords;
e1f99ce6 970 int ret;
78501eac 971
21dd3734
CW		 972 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
973 return -EIO;
974
55249baa 975 if (unlikely(ring->tail + n > ring->effective_size)) {
e1f99ce6
CW		 976 ret = intel_wrap_ring_buffer(ring);
977 if (unlikely(ret))
978 return ret;
979 }
78501eac 980
e1f99ce6
CW		 981 if (unlikely(ring->space < n)) {
982 ret = intel_wait_ring_buffer(ring, n);
983 if (unlikely(ret))
984 return ret;
985 }
d97ed339
CW		 986
987 ring->space -= n;
e1f99ce6 988 return 0;
8187a2b7 989}
62fdfeaf 990
78501eac 991void intel_ring_advance(struct intel_ring_buffer *ring)
8187a2b7 992{
d97ed339 993 ring->tail &= ring->size - 1;
78501eac 994 ring->write_tail(ring, ring->tail);
8187a2b7 995}
62fdfeaf 996
e070868e 997static const struct intel_ring_buffer render_ring = {
8187a2b7 998 .name = "render ring",
9220434a 999 .id = RING_RENDER,
333e9fe9 1000 .mmio_base = RENDER_RING_BASE,
8187a2b7 1001 .size = 32 * PAGE_SIZE,
8187a2b7 1002 .init = init_render_ring,
297b0c5b 1003 .write_tail = ring_write_tail,
8187a2b7
ZN		 1004 .flush = render_ring_flush,
1005 .add_request = render_ring_add_request,
1ec14ad3
CW		 1006 .get_seqno = ring_get_seqno,
1007 .irq_get = render_ring_get_irq,
1008 .irq_put = render_ring_put_irq,
78501eac 1009 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
c6df541c 1010 .cleanup = render_ring_cleanup,
8187a2b7 1011};
d1b851fc
ZN		 1012
1013/* ring buffer for bit-stream decoder */
1014
e070868e 1015static const struct intel_ring_buffer bsd_ring = {
d1b851fc 1016 .name = "bsd ring",
9220434a 1017 .id = RING_BSD,
333e9fe9 1018 .mmio_base = BSD_RING_BASE,
d1b851fc 1019 .size = 32 * PAGE_SIZE,
78501eac 1020 .init = init_ring_common,
297b0c5b 1021 .write_tail = ring_write_tail,
d1b851fc 1022 .flush = bsd_ring_flush,
549f7365 1023 .add_request = ring_add_request,
1ec14ad3
CW		 1024 .get_seqno = ring_get_seqno,
1025 .irq_get = bsd_ring_get_irq,
1026 .irq_put = bsd_ring_put_irq,
78501eac 1027 .dispatch_execbuffer = ring_dispatch_execbuffer,
d1b851fc 1028};
5c1143bb 1029
881f47b6 1030
78501eac 1031static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 1032 u32 value)
881f47b6 1033{
78501eac 1034 drm_i915_private_t *dev_priv = ring->dev->dev_private;
881f47b6
XH		 1035
1036 /* Every tail move must follow the sequence below */
1037 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1038 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1039 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1040 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1041
1042 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1043 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1044 50))
1045 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1046
870e86dd 1047 I915_WRITE_TAIL(ring, value);
881f47b6
XH		 1048 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1049 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1050 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1051}
1052
b72f3acb
CW		 1053static int gen6_ring_flush(struct intel_ring_buffer *ring,
1054 u32 invalidate_domains,
1055 u32 flush_domains)
881f47b6 1056{
b72f3acb
CW		 1057 int ret;
1058
1ec14ad3 1059 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 1060 return 0;
1ec14ad3 1061
b72f3acb
CW		 1062 ret = intel_ring_begin(ring, 4);
1063 if (ret)
1064 return ret;
1065
1066 intel_ring_emit(ring, MI_FLUSH_DW);
1067 intel_ring_emit(ring, 0);
1068 intel_ring_emit(ring, 0);
1069 intel_ring_emit(ring, 0);
1070 intel_ring_advance(ring);
1071 return 0;
881f47b6
XH		 1072}
1073
1074static int
78501eac 1075gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 1076 u32 offset, u32 len)
881f47b6 1077{
e1f99ce6 1078 int ret;
ab6f8e32 1079
e1f99ce6
CW		 1080 ret = intel_ring_begin(ring, 2);
1081 if (ret)
1082 return ret;
1083
78501eac 1084 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
ab6f8e32 1085 /* bit0-7 is the length on GEN6+ */
c4e7a414 1086 intel_ring_emit(ring, offset);
78501eac 1087 intel_ring_advance(ring);
ab6f8e32 1088
881f47b6
XH		 1089 return 0;
1090}
1091
0f46832f
CW		 1092static bool
1093gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1094{
1095 return gen6_ring_get_irq(ring,
1096 GT_USER_INTERRUPT,
1097 GEN6_RENDER_USER_INTERRUPT);
1098}
1099
1100static void
1101gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1102{
1103 return gen6_ring_put_irq(ring,
1104 GT_USER_INTERRUPT,
1105 GEN6_RENDER_USER_INTERRUPT);
1106}
1107
b13c2b96 1108static bool
1ec14ad3
CW		 1109gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1110{
0f46832f
CW		 1111 return gen6_ring_get_irq(ring,
1112 GT_GEN6_BSD_USER_INTERRUPT,
1113 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1114}
1115
1116static void
1117gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1118{
0f46832f
CW		 1119 return gen6_ring_put_irq(ring,
1120 GT_GEN6_BSD_USER_INTERRUPT,
1121 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1122}
1123
881f47b6 1124/* ring buffer for Video Codec for Gen6+ */
e070868e 1125static const struct intel_ring_buffer gen6_bsd_ring = {
1ec14ad3
CW		 1126 .name = "gen6 bsd ring",
1127 .id = RING_BSD,
1128 .mmio_base = GEN6_BSD_RING_BASE,
1129 .size = 32 * PAGE_SIZE,
1130 .init = init_ring_common,
1131 .write_tail = gen6_bsd_ring_write_tail,
1132 .flush = gen6_ring_flush,
1133 .add_request = gen6_add_request,
1134 .get_seqno = ring_get_seqno,
1135 .irq_get = gen6_bsd_ring_get_irq,
1136 .irq_put = gen6_bsd_ring_put_irq,
1137 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
549f7365
CW		 1138};
1139
1140/* Blitter support (SandyBridge+) */
1141
b13c2b96 1142static bool
1ec14ad3 1143blt_ring_get_irq(struct intel_ring_buffer *ring)
549f7365 1144{
0f46832f
CW		 1145 return gen6_ring_get_irq(ring,
1146 GT_BLT_USER_INTERRUPT,
1147 GEN6_BLITTER_USER_INTERRUPT);
549f7365 1148}
1ec14ad3 1149
549f7365 1150static void
1ec14ad3 1151blt_ring_put_irq(struct intel_ring_buffer *ring)
549f7365 1152{
0f46832f
CW		 1153 gen6_ring_put_irq(ring,
1154 GT_BLT_USER_INTERRUPT,
1155 GEN6_BLITTER_USER_INTERRUPT);
549f7365
CW		 1156}
1157
8d19215b
ZN		 1158
1159/* Workaround for some stepping of SNB,
1160 * each time when BLT engine ring tail moved,
1161 * the first command in the ring to be parsed
1162 * should be MI_BATCH_BUFFER_START
1163 */
1164#define NEED_BLT_WORKAROUND(dev) \
1165 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1166
1167static inline struct drm_i915_gem_object *
1168to_blt_workaround(struct intel_ring_buffer *ring)
1169{
1170 return ring->private;
1171}
1172
1173static int blt_ring_init(struct intel_ring_buffer *ring)
1174{
1175 if (NEED_BLT_WORKAROUND(ring->dev)) {
1176 struct drm_i915_gem_object *obj;
27153f72 1177 u32 *ptr;
8d19215b
ZN		 1178 int ret;
1179
05394f39 1180 obj = i915_gem_alloc_object(ring->dev, 4096);
8d19215b
ZN		 1181 if (obj == NULL)
1182 return -ENOMEM;
1183
05394f39 1184 ret = i915_gem_object_pin(obj, 4096, true);
8d19215b
ZN		 1185 if (ret) {
1186 drm_gem_object_unreference(&obj->base);
1187 return ret;
1188 }
1189
1190 ptr = kmap(obj->pages[0]);
27153f72
CW		 1191 *ptr++ = MI_BATCH_BUFFER_END;
1192 *ptr++ = MI_NOOP;
8d19215b
ZN		 1193 kunmap(obj->pages[0]);
1194
05394f39 1195 ret = i915_gem_object_set_to_gtt_domain(obj, false);
8d19215b 1196 if (ret) {
05394f39 1197 i915_gem_object_unpin(obj);
8d19215b
ZN		 1198 drm_gem_object_unreference(&obj->base);
1199 return ret;
1200 }
1201
1202 ring->private = obj;
1203 }
1204
1205 return init_ring_common(ring);
1206}
1207
1208static int blt_ring_begin(struct intel_ring_buffer *ring,
1209 int num_dwords)
1210{
1211 if (ring->private) {
1212 int ret = intel_ring_begin(ring, num_dwords+2);
1213 if (ret)
1214 return ret;
1215
1216 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1217 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1218
1219 return 0;
1220 } else
1221 return intel_ring_begin(ring, 4);
1222}
1223
b72f3acb 1224static int blt_ring_flush(struct intel_ring_buffer *ring,
8d19215b
ZN		 1225 u32 invalidate_domains,
1226 u32 flush_domains)
1227{
b72f3acb
CW		 1228 int ret;
1229
1ec14ad3 1230 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 1231 return 0;
1ec14ad3 1232
b72f3acb
CW		 1233 ret = blt_ring_begin(ring, 4);
1234 if (ret)
1235 return ret;
1236
1237 intel_ring_emit(ring, MI_FLUSH_DW);
1238 intel_ring_emit(ring, 0);
1239 intel_ring_emit(ring, 0);
1240 intel_ring_emit(ring, 0);
1241 intel_ring_advance(ring);
1242 return 0;
8d19215b
ZN		 1243}
1244
8d19215b
ZN		 1245static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1246{
1247 if (!ring->private)
1248 return;
1249
1250 i915_gem_object_unpin(ring->private);
1251 drm_gem_object_unreference(ring->private);
1252 ring->private = NULL;
1253}
1254
549f7365
CW		 1255static const struct intel_ring_buffer gen6_blt_ring = {
1256 .name = "blt ring",
1257 .id = RING_BLT,
1258 .mmio_base = BLT_RING_BASE,
1259 .size = 32 * PAGE_SIZE,
8d19215b 1260 .init = blt_ring_init,
297b0c5b 1261 .write_tail = ring_write_tail,
8d19215b 1262 .flush = blt_ring_flush,
1ec14ad3
CW		 1263 .add_request = gen6_add_request,
1264 .get_seqno = ring_get_seqno,
1265 .irq_get = blt_ring_get_irq,
1266 .irq_put = blt_ring_put_irq,
78501eac 1267 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
8d19215b 1268 .cleanup = blt_ring_cleanup,
881f47b6
XH		 1269};
1270
5c1143bb
XH		 1271int intel_init_render_ring_buffer(struct drm_device *dev)
1272{
1273 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5c1143bb 1275
1ec14ad3
CW		 1276 *ring = render_ring;
1277 if (INTEL_INFO(dev)->gen >= 6) {
1278 ring->add_request = gen6_add_request;
0f46832f
CW		 1279 ring->irq_get = gen6_render_ring_get_irq;
1280 ring->irq_put = gen6_render_ring_put_irq;
c6df541c
CW		 1281 } else if (IS_GEN5(dev)) {
1282 ring->add_request = pc_render_add_request;
1283 ring->get_seqno = pc_render_get_seqno;
1ec14ad3 1284 }
5c1143bb
XH		 1285
1286 if (!I915_NEED_GFX_HWS(dev)) {
1ec14ad3
CW		 1287 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1288 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
5c1143bb
XH		 1289 }
1290
1ec14ad3 1291 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 1292}
1293
e8616b6c
CW		 1294int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1295{
1296 drm_i915_private_t *dev_priv = dev->dev_private;
1297 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1298
1299 *ring = render_ring;
1300 if (INTEL_INFO(dev)->gen >= 6) {
1301 ring->add_request = gen6_add_request;
1302 ring->irq_get = gen6_render_ring_get_irq;
1303 ring->irq_put = gen6_render_ring_put_irq;
1304 } else if (IS_GEN5(dev)) {
1305 ring->add_request = pc_render_add_request;
1306 ring->get_seqno = pc_render_get_seqno;
1307 }
1308
1309 ring->dev = dev;
1310 INIT_LIST_HEAD(&ring->active_list);
1311 INIT_LIST_HEAD(&ring->request_list);
1312 INIT_LIST_HEAD(&ring->gpu_write_list);
1313
1314 ring->size = size;
1315 ring->effective_size = ring->size;
1316 if (IS_I830(ring->dev))
1317 ring->effective_size -= 128;
1318
1319 ring->map.offset = start;
1320 ring->map.size = size;
1321 ring->map.type = 0;
1322 ring->map.flags = 0;
1323 ring->map.mtrr = 0;
1324
1325 drm_core_ioremap_wc(&ring->map, dev);
1326 if (ring->map.handle == NULL) {
1327 DRM_ERROR("can not ioremap virtual address for"
1328 " ring buffer\n");
1329 return -ENOMEM;
1330 }
1331
1332 ring->virtual_start = (void __force __iomem *)ring->map.handle;
1333 return 0;
1334}
1335
5c1143bb
XH		 1336int intel_init_bsd_ring_buffer(struct drm_device *dev)
1337{
1338 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1339 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
5c1143bb 1340
881f47b6 1341 if (IS_GEN6(dev))
1ec14ad3 1342 *ring = gen6_bsd_ring;
881f47b6 1343 else
1ec14ad3 1344 *ring = bsd_ring;
5c1143bb 1345
1ec14ad3 1346 return intel_init_ring_buffer(dev, ring);
5c1143bb 1347}
549f7365
CW		 1348
1349int intel_init_blt_ring_buffer(struct drm_device *dev)
1350{
1351 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1352 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
549f7365 1353
1ec14ad3 1354 *ring = gen6_blt_ring;
549f7365 1355
1ec14ad3 1356 return intel_init_ring_buffer(dev, ring);
549f7365 1357}
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