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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
760285e7 30#include <drm/drmP.h>
62fdfeaf 31#include "i915_drv.h"
760285e7 32#include <drm/i915_drm.h>
62fdfeaf 33#include "i915_trace.h"
881f47b6 34#include "intel_drv.h"
62fdfeaf 35
48d82387
OM		 36bool
37intel_ring_initialized(struct intel_engine_cs *ring)
38{
39 struct drm_device *dev = ring->dev;
40
41 if (!dev)
42 return false;
43
44 if (i915.enable_execlists) {
45 struct intel_context *dctx = ring->default_context;
46 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
47
48 return ringbuf->obj;
49 } else
50 return ring->buffer && ring->buffer->obj;
51}
18393f63 52
82e104cc 53int __intel_ring_space(int head, int tail, int size)
c7dca47b 54{
4f54741e
DG		 55 int space = head - tail;
56 if (space <= 0)
1cf0ba14 57 space += size;
4f54741e 58 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 59}
60
ebd0fd4b
DG		 61void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
62{
63 if (ringbuf->last_retired_head != -1) {
64 ringbuf->head = ringbuf->last_retired_head;
65 ringbuf->last_retired_head = -1;
66 }
67
68 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
69 ringbuf->tail, ringbuf->size);
70}
71
82e104cc 72int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 73{
ebd0fd4b
DG		 74 intel_ring_update_space(ringbuf);
75 return ringbuf->space;
1cf0ba14
CW		 76}
77
82e104cc 78bool intel_ring_stopped(struct intel_engine_cs *ring)
09246732
CW		 79{
80 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88b4aa87
MK		 81 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
82}
09246732 83
a4872ba6 84void __intel_ring_advance(struct intel_engine_cs *ring)
88b4aa87 85{
93b0a4e0
OM		 86 struct intel_ringbuffer *ringbuf = ring->buffer;
87 ringbuf->tail &= ringbuf->size - 1;
88b4aa87 88 if (intel_ring_stopped(ring))
09246732 89 return;
93b0a4e0 90 ring->write_tail(ring, ringbuf->tail);
09246732
CW		 91}
92
b72f3acb 93static int
a4872ba6 94gen2_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 95 u32 invalidate_domains,
96 u32 flush_domains)
97{
98 u32 cmd;
99 int ret;
100
101 cmd = MI_FLUSH;
31b14c9f 102 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 103 cmd |= MI_NO_WRITE_FLUSH;
104
105 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
106 cmd |= MI_READ_FLUSH;
107
108 ret = intel_ring_begin(ring, 2);
109 if (ret)
110 return ret;
111
112 intel_ring_emit(ring, cmd);
113 intel_ring_emit(ring, MI_NOOP);
114 intel_ring_advance(ring);
115
116 return 0;
117}
118
119static int
a4872ba6 120gen4_render_ring_flush(struct intel_engine_cs *ring,
46f0f8d1
CW		 121 u32 invalidate_domains,
122 u32 flush_domains)
62fdfeaf 123{
78501eac 124 struct drm_device *dev = ring->dev;
6f392d54 125 u32 cmd;
b72f3acb 126 int ret;
6f392d54 127
36d527de
CW		 128 /*
129 * read/write caches:
130 *
131 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
132 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
133 * also flushed at 2d versus 3d pipeline switches.
134 *
135 * read-only caches:
136 *
137 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
138 * MI_READ_FLUSH is set, and is always flushed on 965.
139 *
140 * I915_GEM_DOMAIN_COMMAND may not exist?
141 *
142 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
143 * invalidated when MI_EXE_FLUSH is set.
144 *
145 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
146 * invalidated with every MI_FLUSH.
147 *
148 * TLBs:
149 *
150 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
151 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
152 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
153 * are flushed at any MI_FLUSH.
154 */
155
156 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 157 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 158 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 159 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
160 cmd |= MI_EXE_FLUSH;
62fdfeaf 161
36d527de
CW		 162 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
163 (IS_G4X(dev) || IS_GEN5(dev)))
164 cmd |= MI_INVALIDATE_ISP;
70eac33e 165
36d527de
CW		 166 ret = intel_ring_begin(ring, 2);
167 if (ret)
168 return ret;
b72f3acb 169
36d527de
CW		 170 intel_ring_emit(ring, cmd);
171 intel_ring_emit(ring, MI_NOOP);
172 intel_ring_advance(ring);
b72f3acb
CW		 173
174 return 0;
8187a2b7
ZN		 175}
176
8d315287
JB		 177/**
178 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
179 * implementing two workarounds on gen6. From section 1.4.7.1
180 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
181 *
182 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
183 * produced by non-pipelined state commands), software needs to first
184 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
185 * 0.
186 *
187 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
188 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
189 *
190 * And the workaround for these two requires this workaround first:
191 *
192 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
193 * BEFORE the pipe-control with a post-sync op and no write-cache
194 * flushes.
195 *
196 * And this last workaround is tricky because of the requirements on
197 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
198 * volume 2 part 1:
199 *
200 * "1 of the following must also be set:
201 * - Render Target Cache Flush Enable ([12] of DW1)
202 * - Depth Cache Flush Enable ([0] of DW1)
203 * - Stall at Pixel Scoreboard ([1] of DW1)
204 * - Depth Stall ([13] of DW1)
205 * - Post-Sync Operation ([13] of DW1)
206 * - Notify Enable ([8] of DW1)"
207 *
208 * The cache flushes require the workaround flush that triggered this
209 * one, so we can't use it. Depth stall would trigger the same.
210 * Post-sync nonzero is what triggered this second workaround, so we
211 * can't use that one either. Notify enable is IRQs, which aren't
212 * really our business. That leaves only stall at scoreboard.
213 */
214static int
a4872ba6 215intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
8d315287 216{
18393f63 217 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 218 int ret;
219
220
221 ret = intel_ring_begin(ring, 6);
222 if (ret)
223 return ret;
224
225 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
226 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
227 PIPE_CONTROL_STALL_AT_SCOREBOARD);
228 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
229 intel_ring_emit(ring, 0); /* low dword */
230 intel_ring_emit(ring, 0); /* high dword */
231 intel_ring_emit(ring, MI_NOOP);
232 intel_ring_advance(ring);
233
234 ret = intel_ring_begin(ring, 6);
235 if (ret)
236 return ret;
237
238 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
239 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
240 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
241 intel_ring_emit(ring, 0);
242 intel_ring_emit(ring, 0);
243 intel_ring_emit(ring, MI_NOOP);
244 intel_ring_advance(ring);
245
246 return 0;
247}
248
249static int
a4872ba6 250gen6_render_ring_flush(struct intel_engine_cs *ring,
8d315287
JB		 251 u32 invalidate_domains, u32 flush_domains)
252{
253 u32 flags = 0;
18393f63 254 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 255 int ret;
256
b3111509
PZ		 257 /* Force SNB workarounds for PIPE_CONTROL flushes */
258 ret = intel_emit_post_sync_nonzero_flush(ring);
259 if (ret)
260 return ret;
261
8d315287
JB		 262 /* Just flush everything. Experiments have shown that reducing the
263 * number of bits based on the write domains has little performance
264 * impact.
265 */
7d54a904
CW		 266 if (flush_domains) {
267 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
268 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
269 /*
270 * Ensure that any following seqno writes only happen
271 * when the render cache is indeed flushed.
272 */
97f209bc 273 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 274 }
275 if (invalidate_domains) {
276 flags |= PIPE_CONTROL_TLB_INVALIDATE;
277 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
278 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
279 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
282 /*
283 * TLB invalidate requires a post-sync write.
284 */
3ac78313 285 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 286 }
8d315287 287
6c6cf5aa 288 ret = intel_ring_begin(ring, 4);
8d315287
JB		 289 if (ret)
290 return ret;
291
6c6cf5aa 292 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
8d315287
JB		 293 intel_ring_emit(ring, flags);
294 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
6c6cf5aa 295 intel_ring_emit(ring, 0);
8d315287
JB		 296 intel_ring_advance(ring);
297
298 return 0;
299}
300
f3987631 301static int
a4872ba6 302gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
f3987631
PZ		 303{
304 int ret;
305
306 ret = intel_ring_begin(ring, 4);
307 if (ret)
308 return ret;
309
310 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
311 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
312 PIPE_CONTROL_STALL_AT_SCOREBOARD);
313 intel_ring_emit(ring, 0);
314 intel_ring_emit(ring, 0);
315 intel_ring_advance(ring);
316
317 return 0;
318}
319
4772eaeb 320static int
a4872ba6 321gen7_render_ring_flush(struct intel_engine_cs *ring,
4772eaeb
PZ		 322 u32 invalidate_domains, u32 flush_domains)
323{
324 u32 flags = 0;
18393f63 325 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 326 int ret;
327
f3987631
PZ		 328 /*
329 * Ensure that any following seqno writes only happen when the render
330 * cache is indeed flushed.
331 *
332 * Workaround: 4th PIPE_CONTROL command (except the ones with only
333 * read-cache invalidate bits set) must have the CS_STALL bit set. We
334 * don't try to be clever and just set it unconditionally.
335 */
336 flags |= PIPE_CONTROL_CS_STALL;
337
4772eaeb
PZ		 338 /* Just flush everything. Experiments have shown that reducing the
339 * number of bits based on the write domains has little performance
340 * impact.
341 */
342 if (flush_domains) {
343 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
344 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
4772eaeb
PZ		 345 }
346 if (invalidate_domains) {
347 flags |= PIPE_CONTROL_TLB_INVALIDATE;
348 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
349 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
350 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
351 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
352 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 353 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 354 /*
355 * TLB invalidate requires a post-sync write.
356 */
357 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 358 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 359
add284a3
CW		 360 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
361
f3987631
PZ		 362 /* Workaround: we must issue a pipe_control with CS-stall bit
363 * set before a pipe_control command that has the state cache
364 * invalidate bit set. */
365 gen7_render_ring_cs_stall_wa(ring);
4772eaeb
PZ		 366 }
367
368 ret = intel_ring_begin(ring, 4);
369 if (ret)
370 return ret;
371
372 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
373 intel_ring_emit(ring, flags);
b9e1faa7 374 intel_ring_emit(ring, scratch_addr);
4772eaeb
PZ		 375 intel_ring_emit(ring, 0);
376 intel_ring_advance(ring);
377
378 return 0;
379}
380
884ceace
KG		 381static int
382gen8_emit_pipe_control(struct intel_engine_cs *ring,
383 u32 flags, u32 scratch_addr)
384{
385 int ret;
386
387 ret = intel_ring_begin(ring, 6);
388 if (ret)
389 return ret;
390
391 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
392 intel_ring_emit(ring, flags);
393 intel_ring_emit(ring, scratch_addr);
394 intel_ring_emit(ring, 0);
395 intel_ring_emit(ring, 0);
396 intel_ring_emit(ring, 0);
397 intel_ring_advance(ring);
398
399 return 0;
400}
401
a5f3d68e 402static int
a4872ba6 403gen8_render_ring_flush(struct intel_engine_cs *ring,
a5f3d68e
BW		 404 u32 invalidate_domains, u32 flush_domains)
405{
406 u32 flags = 0;
18393f63 407 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 408 int ret;
a5f3d68e
BW		 409
410 flags |= PIPE_CONTROL_CS_STALL;
411
412 if (flush_domains) {
413 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
414 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
415 }
416 if (invalidate_domains) {
417 flags |= PIPE_CONTROL_TLB_INVALIDATE;
418 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
419 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
420 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
421 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
422 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
423 flags |= PIPE_CONTROL_QW_WRITE;
424 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 425
426 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
427 ret = gen8_emit_pipe_control(ring,
428 PIPE_CONTROL_CS_STALL |
429 PIPE_CONTROL_STALL_AT_SCOREBOARD,
430 0);
431 if (ret)
432 return ret;
a5f3d68e
BW		 433 }
434
6e0b3f8d 435 return gen8_emit_pipe_control(ring, flags, scratch_addr);
a5f3d68e
BW		 436}
437
a4872ba6 438static void ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 439 u32 value)
d46eefa2 440{
4640c4ff 441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
297b0c5b 442 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 443}
444
a4872ba6 445u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
8187a2b7 446{
4640c4ff 447 struct drm_i915_private *dev_priv = ring->dev->dev_private;
50877445 448 u64 acthd;
8187a2b7 449
50877445
CW		 450 if (INTEL_INFO(ring->dev)->gen >= 8)
451 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
452 RING_ACTHD_UDW(ring->mmio_base));
453 else if (INTEL_INFO(ring->dev)->gen >= 4)
454 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
455 else
456 acthd = I915_READ(ACTHD);
457
458 return acthd;
8187a2b7
ZN		 459}
460
a4872ba6 461static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
035dc1e0
DV		 462{
463 struct drm_i915_private *dev_priv = ring->dev->dev_private;
464 u32 addr;
465
466 addr = dev_priv->status_page_dmah->busaddr;
467 if (INTEL_INFO(ring->dev)->gen >= 4)
468 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
469 I915_WRITE(HWS_PGA, addr);
470}
471
af75f269
DL		 472static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
473{
474 struct drm_device *dev = ring->dev;
475 struct drm_i915_private *dev_priv = ring->dev->dev_private;
476 u32 mmio = 0;
477
478 /* The ring status page addresses are no longer next to the rest of
479 * the ring registers as of gen7.
480 */
481 if (IS_GEN7(dev)) {
482 switch (ring->id) {
483 case RCS:
484 mmio = RENDER_HWS_PGA_GEN7;
485 break;
486 case BCS:
487 mmio = BLT_HWS_PGA_GEN7;
488 break;
489 /*
490 * VCS2 actually doesn't exist on Gen7. Only shut up
491 * gcc switch check warning
492 */
493 case VCS2:
494 case VCS:
495 mmio = BSD_HWS_PGA_GEN7;
496 break;
497 case VECS:
498 mmio = VEBOX_HWS_PGA_GEN7;
499 break;
500 }
501 } else if (IS_GEN6(ring->dev)) {
502 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
503 } else {
504 /* XXX: gen8 returns to sanity */
505 mmio = RING_HWS_PGA(ring->mmio_base);
506 }
507
508 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
509 POSTING_READ(mmio);
510
511 /*
512 * Flush the TLB for this page
513 *
514 * FIXME: These two bits have disappeared on gen8, so a question
515 * arises: do we still need this and if so how should we go about
516 * invalidating the TLB?
517 */
518 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
519 u32 reg = RING_INSTPM(ring->mmio_base);
520
521 /* ring should be idle before issuing a sync flush*/
522 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
523
524 I915_WRITE(reg,
525 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
526 INSTPM_SYNC_FLUSH));
527 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
528 1000))
529 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
530 ring->name);
531 }
532}
533
a4872ba6 534static bool stop_ring(struct intel_engine_cs *ring)
8187a2b7 535{
9991ae78 536 struct drm_i915_private *dev_priv = to_i915(ring->dev);
8187a2b7 537
9991ae78
CW		 538 if (!IS_GEN2(ring->dev)) {
539 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
403bdd10
DV		 540 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
541 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
9bec9b13
CW		 542 /* Sometimes we observe that the idle flag is not
543 * set even though the ring is empty. So double
544 * check before giving up.
545 */
546 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
547 return false;
9991ae78
CW		 548 }
549 }
b7884eb4 550
7f2ab699 551 I915_WRITE_CTL(ring, 0);
570ef608 552 I915_WRITE_HEAD(ring, 0);
78501eac 553 ring->write_tail(ring, 0);
8187a2b7 554
9991ae78
CW		 555 if (!IS_GEN2(ring->dev)) {
556 (void)I915_READ_CTL(ring);
557 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
558 }
a51435a3 559
9991ae78
CW		 560 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
561}
8187a2b7 562
a4872ba6 563static int init_ring_common(struct intel_engine_cs *ring)
9991ae78
CW		 564{
565 struct drm_device *dev = ring->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
93b0a4e0
OM		 567 struct intel_ringbuffer *ringbuf = ring->buffer;
568 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 569 int ret = 0;
570
59bad947 571 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78
CW		 572
573 if (!stop_ring(ring)) {
574 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 575 DRM_DEBUG_KMS("%s head not reset to zero "
576 "ctl %08x head %08x tail %08x start %08x\n",
577 ring->name,
578 I915_READ_CTL(ring),
579 I915_READ_HEAD(ring),
580 I915_READ_TAIL(ring),
581 I915_READ_START(ring));
8187a2b7 582
9991ae78 583 if (!stop_ring(ring)) {
6fd0d56e
CW		 584 DRM_ERROR("failed to set %s head to zero "
585 "ctl %08x head %08x tail %08x start %08x\n",
586 ring->name,
587 I915_READ_CTL(ring),
588 I915_READ_HEAD(ring),
589 I915_READ_TAIL(ring),
590 I915_READ_START(ring));
9991ae78
CW		 591 ret = -EIO;
592 goto out;
6fd0d56e 593 }
8187a2b7
ZN		 594 }
595
9991ae78
CW		 596 if (I915_NEED_GFX_HWS(dev))
597 intel_ring_setup_status_page(ring);
598 else
599 ring_setup_phys_status_page(ring);
600
ece4a17d
JK		 601 /* Enforce ordering by reading HEAD register back */
602 I915_READ_HEAD(ring);
603
0d8957c8
DV		 604 /* Initialize the ring. This must happen _after_ we've cleared the ring
605 * registers with the above sequence (the readback of the HEAD registers
606 * also enforces ordering), otherwise the hw might lose the new ring
607 * register values. */
f343c5f6 608 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 609
610 /* WaClearRingBufHeadRegAtInit:ctg,elk */
611 if (I915_READ_HEAD(ring))
612 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
613 ring->name, I915_READ_HEAD(ring));
614 I915_WRITE_HEAD(ring, 0);
615 (void)I915_READ_HEAD(ring);
616
7f2ab699 617 I915_WRITE_CTL(ring,
93b0a4e0 618 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 619 | RING_VALID);
8187a2b7 620
8187a2b7 621 /* If the head is still not zero, the ring is dead */
f01db988 622 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
f343c5f6 623 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
f01db988 624 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
e74cfed5 625 DRM_ERROR("%s initialization failed "
48e48a0b
CW		 626 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
627 ring->name,
628 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
629 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
630 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 631 ret = -EIO;
632 goto out;
8187a2b7
ZN		 633 }
634
ebd0fd4b 635 ringbuf->last_retired_head = -1;
5c6c6003
CW		 636 ringbuf->head = I915_READ_HEAD(ring);
637 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
ebd0fd4b 638 intel_ring_update_space(ringbuf);
1ec14ad3 639
50f018df
CW		 640 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
641
b7884eb4 642out:
59bad947 643 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 644
645 return ret;
8187a2b7
ZN		 646}
647
9b1136d5
OM		 648void
649intel_fini_pipe_control(struct intel_engine_cs *ring)
650{
651 struct drm_device *dev = ring->dev;
652
653 if (ring->scratch.obj == NULL)
654 return;
655
656 if (INTEL_INFO(dev)->gen >= 5) {
657 kunmap(sg_page(ring->scratch.obj->pages->sgl));
658 i915_gem_object_ggtt_unpin(ring->scratch.obj);
659 }
660
661 drm_gem_object_unreference(&ring->scratch.obj->base);
662 ring->scratch.obj = NULL;
663}
664
665int
666intel_init_pipe_control(struct intel_engine_cs *ring)
c6df541c 667{
c6df541c
CW		 668 int ret;
669
bfc882b4 670 WARN_ON(ring->scratch.obj);
c6df541c 671
0d1aacac
CW		 672 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
673 if (ring->scratch.obj == NULL) {
c6df541c
CW		 674 DRM_ERROR("Failed to allocate seqno page\n");
675 ret = -ENOMEM;
676 goto err;
677 }
e4ffd173 678
a9cc726c
DV		 679 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
680 if (ret)
681 goto err_unref;
c6df541c 682
1ec9e26d 683 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
c6df541c
CW		 684 if (ret)
685 goto err_unref;
686
0d1aacac
CW		 687 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
688 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
689 if (ring->scratch.cpu_page == NULL) {
56b085a0 690 ret = -ENOMEM;
c6df541c 691 goto err_unpin;
56b085a0 692 }
c6df541c 693
2b1086cc 694 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0d1aacac 695 ring->name, ring->scratch.gtt_offset);
c6df541c
CW		 696 return 0;
697
698err_unpin:
d7f46fc4 699 i915_gem_object_ggtt_unpin(ring->scratch.obj);
c6df541c 700err_unref:
0d1aacac 701 drm_gem_object_unreference(&ring->scratch.obj->base);
c6df541c 702err:
c6df541c
CW		 703 return ret;
704}
705
771b9a53
MT		 706static int intel_ring_workarounds_emit(struct intel_engine_cs *ring,
707 struct intel_context *ctx)
86d7f238 708{
7225342a 709 int ret, i;
888b5995
AS		 710 struct drm_device *dev = ring->dev;
711 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 712 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 713
e6c1abb7 714 if (WARN_ON_ONCE(w->count == 0))
7225342a 715 return 0;
888b5995 716
7225342a
MK		 717 ring->gpu_caches_dirty = true;
718 ret = intel_ring_flush_all_caches(ring);
719 if (ret)
720 return ret;
888b5995 721
22a916aa 722 ret = intel_ring_begin(ring, (w->count * 2 + 2));
7225342a
MK		 723 if (ret)
724 return ret;
725
22a916aa 726 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
7225342a 727 for (i = 0; i < w->count; i++) {
7225342a
MK		 728 intel_ring_emit(ring, w->reg[i].addr);
729 intel_ring_emit(ring, w->reg[i].value);
730 }
22a916aa 731 intel_ring_emit(ring, MI_NOOP);
7225342a
MK		 732
733 intel_ring_advance(ring);
734
735 ring->gpu_caches_dirty = true;
736 ret = intel_ring_flush_all_caches(ring);
737 if (ret)
738 return ret;
888b5995 739
7225342a 740 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 741
7225342a 742 return 0;
86d7f238
AS		 743}
744
8f0e2b9d
DV		 745static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
746 struct intel_context *ctx)
747{
748 int ret;
749
750 ret = intel_ring_workarounds_emit(ring, ctx);
751 if (ret != 0)
752 return ret;
753
754 ret = i915_gem_render_state_init(ring);
755 if (ret)
756 DRM_ERROR("init render state: %d\n", ret);
757
758 return ret;
759}
760
7225342a 761static int wa_add(struct drm_i915_private *dev_priv,
cf4b0de6 762 const u32 addr, const u32 mask, const u32 val)
7225342a
MK		 763{
764 const u32 idx = dev_priv->workarounds.count;
765
766 if (WARN_ON(idx >= I915_MAX_WA_REGS))
767 return -ENOSPC;
768
769 dev_priv->workarounds.reg[idx].addr = addr;
770 dev_priv->workarounds.reg[idx].value = val;
771 dev_priv->workarounds.reg[idx].mask = mask;
772
773 dev_priv->workarounds.count++;
774
775 return 0;
86d7f238
AS		 776}
777
cf4b0de6
DL		 778#define WA_REG(addr, mask, val) { \
779 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 780 if (r) \
781 return r; \
782 }
783
784#define WA_SET_BIT_MASKED(addr, mask) \
26459343 785 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 786
787#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 788 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 789
98533251 790#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 791 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 792
cf4b0de6
DL		 793#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
794#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 795
cf4b0de6 796#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 797
00e1e623 798static int bdw_init_workarounds(struct intel_engine_cs *ring)
86d7f238 799{
888b5995
AS		 800 struct drm_device *dev = ring->dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 802
86d7f238 803 /* WaDisablePartialInstShootdown:bdw */
101b376d 804 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
7225342a
MK		 805 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
806 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
807 STALL_DOP_GATING_DISABLE);
86d7f238 808
101b376d 809 /* WaDisableDopClockGating:bdw */
7225342a
MK		 810 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
811 DOP_CLOCK_GATING_DISABLE);
86d7f238 812
7225342a
MK		 813 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
814 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238
AS		 815
816 /* Use Force Non-Coherent whenever executing a 3D context. This is a
817 * workaround for for a possible hang in the unlikely event a TLB
818 * invalidation occurs during a PSD flush.
819 */
7225342a 820 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b 821 /* WaForceEnableNonCoherent:bdw */
7225342a 822 HDC_FORCE_NON_COHERENT |
35cb6f3b
DL		 823 /* WaForceContextSaveRestoreNonCoherent:bdw */
824 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
825 /* WaHdcDisableFetchWhenMasked:bdw */
f3f32360 826 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
35cb6f3b 827 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 828 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 829
2701fc43
KG		 830 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
831 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
832 * polygons in the same 8x4 pixel/sample area to be processed without
833 * stalling waiting for the earlier ones to write to Hierarchical Z
834 * buffer."
835 *
836 * This optimization is off by default for Broadwell; turn it on.
837 */
838 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
839
86d7f238 840 /* Wa4x4STCOptimizationDisable:bdw */
7225342a
MK		 841 WA_SET_BIT_MASKED(CACHE_MODE_1,
842 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
86d7f238
AS		 843
844 /*
845 * BSpec recommends 8x4 when MSAA is used,
846 * however in practice 16x4 seems fastest.
847 *
848 * Note that PS/WM thread counts depend on the WIZ hashing
849 * disable bit, which we don't touch here, but it's good
850 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
851 */
98533251
DL		 852 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
853 GEN6_WIZ_HASHING_MASK,
854 GEN6_WIZ_HASHING_16x4);
888b5995 855
51ce4db1
RV		 856 /* WaProgramL3SqcReg1Default:bdw */
857 WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
858
86d7f238
AS		 859 return 0;
860}
861
00e1e623
VS		 862static int chv_init_workarounds(struct intel_engine_cs *ring)
863{
00e1e623
VS		 864 struct drm_device *dev = ring->dev;
865 struct drm_i915_private *dev_priv = dev->dev_private;
866
00e1e623 867 /* WaDisablePartialInstShootdown:chv */
00e1e623 868 /* WaDisableThreadStallDopClockGating:chv */
7225342a 869 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
605f1433
AS		 870 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
871 STALL_DOP_GATING_DISABLE);
00e1e623 872
95289009
AS		 873 /* Use Force Non-Coherent whenever executing a 3D context. This is a
874 * workaround for a possible hang in the unlikely event a TLB
875 * invalidation occurs during a PSD flush.
876 */
877 /* WaForceEnableNonCoherent:chv */
878 /* WaHdcDisableFetchWhenMasked:chv */
879 WA_SET_BIT_MASKED(HDC_CHICKEN0,
880 HDC_FORCE_NON_COHERENT |
881 HDC_DONOT_FETCH_MEM_WHEN_MASKED);
882
973a5b06
KG		 883 /* According to the CACHE_MODE_0 default value documentation, some
884 * CHV platforms disable this optimization by default. Turn it on.
885 */
886 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
887
14bc16e3
VS		 888 /* Wa4x4STCOptimizationDisable:chv */
889 WA_SET_BIT_MASKED(CACHE_MODE_1,
890 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
891
d60de81d
KG		 892 /* Improve HiZ throughput on CHV. */
893 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
894
e7fc2436
VS		 895 /*
896 * BSpec recommends 8x4 when MSAA is used,
897 * however in practice 16x4 seems fastest.
898 *
899 * Note that PS/WM thread counts depend on the WIZ hashing
900 * disable bit, which we don't touch here, but it's good
901 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
902 */
903 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
904 GEN6_WIZ_HASHING_MASK,
905 GEN6_WIZ_HASHING_16x4);
906
65ca7514
DL		 907 if (INTEL_REVID(dev) == SKL_REVID_C0 ||
908 INTEL_REVID(dev) == SKL_REVID_D0)
909 /* WaBarrierPerformanceFixDisable:skl */
910 WA_SET_BIT_MASKED(HDC_CHICKEN0,
911 HDC_FENCE_DEST_SLM_DISABLE |
912 HDC_BARRIER_PERFORMANCE_DISABLE);
913
7225342a
MK		 914 return 0;
915}
916
3b106531
HN		 917static int gen9_init_workarounds(struct intel_engine_cs *ring)
918{
ab0dfafe
HN		 919 struct drm_device *dev = ring->dev;
920 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 921 uint32_t tmp;
ab0dfafe 922
b0e6f6d4 923 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
926
a119a6e6 927 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
930
d2a31dbd
NH		 931 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
932 INTEL_REVID(dev) == SKL_REVID_B0)) ||
933 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
934 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
a86eb582
DL		 935 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
936 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f
NH		 937 }
938
a13d215f
NH		 939 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
940 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
941 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
183c6dac
DL		 942 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
943 GEN9_RHWO_OPTIMIZATION_DISABLE);
944 WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
945 DISABLE_PIXEL_MASK_CAMMING);
946 }
947
27a1b688
NH		 948 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
949 IS_BROXTON(dev)) {
950 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
cac23df4
NH		 951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX);
953 }
954
5068368c 955 /* Wa4x4STCOptimizationDisable:skl,bxt */
1840481f
HN		 956 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
957
27160c96 958 /* WaDisablePartialResolveInVc:skl,bxt */
9370cd98
DL		 959 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
960
16be17af 961 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 962 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
963 GEN9_CCS_TLB_PREFETCH_ENABLE);
964
5a2ae95e
ID		 965 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
966 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_C0) ||
967 (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0))
38a39a7b
BW		 968 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
969 PIXEL_MASK_CAMMING_DISABLE);
970
8ea6f892
ID		 971 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
972 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
973 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
974 (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
975 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
976 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
977
3b106531
HN		 978 return 0;
979}
980
b7668791
DL		 981static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
982{
983 struct drm_device *dev = ring->dev;
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u8 vals[3] = { 0, 0, 0 };
986 unsigned int i;
987
988 for (i = 0; i < 3; i++) {
989 u8 ss;
990
991 /*
992 * Only consider slices where one, and only one, subslice has 7
993 * EUs
994 */
995 if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
996 continue;
997
998 /*
999 * subslice_7eu[i] != 0 (because of the check above) and
1000 * ss_max == 4 (maximum number of subslices possible per slice)
1001 *
1002 * -> 0 <= ss <= 3;
1003 */
1004 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1005 vals[i] = 3 - ss;
1006 }
1007
1008 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1009 return 0;
1010
1011 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1012 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1013 GEN9_IZ_HASHING_MASK(2) |
1014 GEN9_IZ_HASHING_MASK(1) |
1015 GEN9_IZ_HASHING_MASK(0),
1016 GEN9_IZ_HASHING(2, vals[2]) |
1017 GEN9_IZ_HASHING(1, vals[1]) |
1018 GEN9_IZ_HASHING(0, vals[0]));
1019
1020 return 0;
1021}
1022
1023
8d205494
DL		 1024static int skl_init_workarounds(struct intel_engine_cs *ring)
1025{
d0bbbc4f
DL		 1026 struct drm_device *dev = ring->dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028
8d205494
DL		 1029 gen9_init_workarounds(ring);
1030
d0bbbc4f
DL		 1031 /* WaDisablePowerCompilerClockGating:skl */
1032 if (INTEL_REVID(dev) == SKL_REVID_B0)
1033 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1034 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1035
b62adbd1
NH		 1036 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
1037 /*
1038 *Use Force Non-Coherent whenever executing a 3D context. This
1039 * is a workaround for a possible hang in the unlikely event
1040 * a TLB invalidation occurs during a PSD flush.
1041 */
1042 /* WaForceEnableNonCoherent:skl */
1043 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1044 HDC_FORCE_NON_COHERENT);
1045 }
1046
b7668791 1047 return skl_tune_iz_hashing(ring);
7225342a
MK		 1048}
1049
cae0437f
NH		 1050static int bxt_init_workarounds(struct intel_engine_cs *ring)
1051{
dfb601e6
NH		 1052 struct drm_device *dev = ring->dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054
cae0437f
NH		 1055 gen9_init_workarounds(ring);
1056
dfb601e6
NH		 1057 /* WaDisableThreadStallDopClockGating:bxt */
1058 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1059 STALL_DOP_GATING_DISABLE);
1060
983b4b9d
NH		 1061 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1062 if (INTEL_REVID(dev) <= BXT_REVID_B0) {
1063 WA_SET_BIT_MASKED(
1064 GEN7_HALF_SLICE_CHICKEN1,
1065 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1066 }
1067
cae0437f
NH		 1068 return 0;
1069}
1070
771b9a53 1071int init_workarounds_ring(struct intel_engine_cs *ring)
7225342a
MK		 1072{
1073 struct drm_device *dev = ring->dev;
1074 struct drm_i915_private *dev_priv = dev->dev_private;
1075
1076 WARN_ON(ring->id != RCS);
1077
1078 dev_priv->workarounds.count = 0;
1079
1080 if (IS_BROADWELL(dev))
1081 return bdw_init_workarounds(ring);
1082
1083 if (IS_CHERRYVIEW(dev))
1084 return chv_init_workarounds(ring);
00e1e623 1085
8d205494
DL		 1086 if (IS_SKYLAKE(dev))
1087 return skl_init_workarounds(ring);
cae0437f
NH		 1088
1089 if (IS_BROXTON(dev))
1090 return bxt_init_workarounds(ring);
3b106531 1091
00e1e623
VS		 1092 return 0;
1093}
1094
a4872ba6 1095static int init_render_ring(struct intel_engine_cs *ring)
8187a2b7 1096{
78501eac 1097 struct drm_device *dev = ring->dev;
1ec14ad3 1098 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 1099 int ret = init_ring_common(ring);
9c33baa6
KZ		 1100 if (ret)
1101 return ret;
a69ffdbf 1102
61a563a2
AG		 1103 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1104 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1105 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1106
1107 /* We need to disable the AsyncFlip performance optimisations in order
1108 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1109 * programmed to '1' on all products.
8693a824 1110 *
b3f797ac 1111 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1c8c38c5 1112 */
fbdcb068 1113 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
1c8c38c5
CW		 1114 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1115
f05bb0c7 1116 /* Required for the hardware to program scanline values for waiting */
01fa0302 1117 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1118 if (INTEL_INFO(dev)->gen == 6)
1119 I915_WRITE(GFX_MODE,
aa83e30d 1120 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1121
01fa0302 1122 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1123 if (IS_GEN7(dev))
1124 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1125 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1126 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1127
5e13a0c5 1128 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1129 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1130 * "If this bit is set, STCunit will have LRA as replacement
1131 * policy. [...] This bit must be reset. LRA replacement
1132 * policy is not supported."
1133 */
1134 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1135 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1136 }
1137
6b26c86d
DV		 1138 if (INTEL_INFO(dev)->gen >= 6)
1139 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1140
040d2baa 1141 if (HAS_L3_DPF(dev))
35a85ac6 1142 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e 1143
7225342a 1144 return init_workarounds_ring(ring);
8187a2b7
ZN		 1145}
1146
a4872ba6 1147static void render_ring_cleanup(struct intel_engine_cs *ring)
c6df541c 1148{
b45305fc 1149 struct drm_device *dev = ring->dev;
3e78998a
BW		 1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151
1152 if (dev_priv->semaphore_obj) {
1153 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1154 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1155 dev_priv->semaphore_obj = NULL;
1156 }
b45305fc 1157
9b1136d5 1158 intel_fini_pipe_control(ring);
c6df541c
CW		 1159}
1160
3e78998a
BW		 1161static int gen8_rcs_signal(struct intel_engine_cs *signaller,
1162 unsigned int num_dwords)
1163{
1164#define MBOX_UPDATE_DWORDS 8
1165 struct drm_device *dev = signaller->dev;
1166 struct drm_i915_private *dev_priv = dev->dev_private;
1167 struct intel_engine_cs *waiter;
1168 int i, ret, num_rings;
1169
1170 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1171 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1172#undef MBOX_UPDATE_DWORDS
1173
1174 ret = intel_ring_begin(signaller, num_dwords);
1175 if (ret)
1176 return ret;
1177
1178 for_each_ring(waiter, dev_priv, i) {
6259cead 1179 u32 seqno;
3e78998a
BW		 1180 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1181 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1182 continue;
1183
6259cead
JH		 1184 seqno = i915_gem_request_get_seqno(
1185 signaller->outstanding_lazy_request);
3e78998a
BW		 1186 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1187 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1188 PIPE_CONTROL_QW_WRITE |
1189 PIPE_CONTROL_FLUSH_ENABLE);
1190 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1191 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1192 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1193 intel_ring_emit(signaller, 0);
1194 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1195 MI_SEMAPHORE_TARGET(waiter->id));
1196 intel_ring_emit(signaller, 0);
1197 }
1198
1199 return 0;
1200}
1201
1202static int gen8_xcs_signal(struct intel_engine_cs *signaller,
1203 unsigned int num_dwords)
1204{
1205#define MBOX_UPDATE_DWORDS 6
1206 struct drm_device *dev = signaller->dev;
1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 struct intel_engine_cs *waiter;
1209 int i, ret, num_rings;
1210
1211 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1212 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1213#undef MBOX_UPDATE_DWORDS
1214
1215 ret = intel_ring_begin(signaller, num_dwords);
1216 if (ret)
1217 return ret;
1218
1219 for_each_ring(waiter, dev_priv, i) {
6259cead 1220 u32 seqno;
3e78998a
BW		 1221 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1222 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1223 continue;
1224
6259cead
JH		 1225 seqno = i915_gem_request_get_seqno(
1226 signaller->outstanding_lazy_request);
3e78998a
BW		 1227 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1228 MI_FLUSH_DW_OP_STOREDW);
1229 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1230 MI_FLUSH_DW_USE_GTT);
1231 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1232 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1233 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1234 MI_SEMAPHORE_TARGET(waiter->id));
1235 intel_ring_emit(signaller, 0);
1236 }
1237
1238 return 0;
1239}
1240
a4872ba6 1241static int gen6_signal(struct intel_engine_cs *signaller,
024a43e1 1242 unsigned int num_dwords)
1ec14ad3 1243{
024a43e1
BW		 1244 struct drm_device *dev = signaller->dev;
1245 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1246 struct intel_engine_cs *useless;
a1444b79 1247 int i, ret, num_rings;
78325f2d 1248
a1444b79
BW		 1249#define MBOX_UPDATE_DWORDS 3
1250 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1251 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1252#undef MBOX_UPDATE_DWORDS
024a43e1
BW		 1253
1254 ret = intel_ring_begin(signaller, num_dwords);
1255 if (ret)
1256 return ret;
024a43e1 1257
78325f2d
BW		 1258 for_each_ring(useless, dev_priv, i) {
1259 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
1260 if (mbox_reg != GEN6_NOSYNC) {
6259cead
JH		 1261 u32 seqno = i915_gem_request_get_seqno(
1262 signaller->outstanding_lazy_request);
78325f2d
BW		 1263 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1264 intel_ring_emit(signaller, mbox_reg);
6259cead 1265 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1266 }
1267 }
024a43e1 1268
a1444b79
BW		 1269 /* If num_dwords was rounded, make sure the tail pointer is correct */
1270 if (num_rings % 2 == 0)
1271 intel_ring_emit(signaller, MI_NOOP);
1272
024a43e1 1273 return 0;
1ec14ad3
CW		 1274}
1275
c8c99b0f
BW		 1276/**
1277 * gen6_add_request - Update the semaphore mailbox registers
1278 *
1279 * @ring - ring that is adding a request
1280 * @seqno - return seqno stuck into the ring
1281 *
1282 * Update the mailbox registers in the *other* rings with the current seqno.
1283 * This acts like a signal in the canonical semaphore.
1284 */
1ec14ad3 1285static int
a4872ba6 1286gen6_add_request(struct intel_engine_cs *ring)
1ec14ad3 1287{
024a43e1 1288 int ret;
52ed2325 1289
707d9cf9
BW		 1290 if (ring->semaphore.signal)
1291 ret = ring->semaphore.signal(ring, 4);
1292 else
1293 ret = intel_ring_begin(ring, 4);
1294
1ec14ad3
CW		 1295 if (ret)
1296 return ret;
1297
1ec14ad3
CW		 1298 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1299 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1300 intel_ring_emit(ring,
1301 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1ec14ad3 1302 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1303 __intel_ring_advance(ring);
1ec14ad3 1304
1ec14ad3
CW		 1305 return 0;
1306}
1307
f72b3435
MK		 1308static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1309 u32 seqno)
1310{
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 return dev_priv->last_seqno < seqno;
1313}
1314
c8c99b0f
BW		 1315/**
1316 * intel_ring_sync - sync the waiter to the signaller on seqno
1317 *
1318 * @waiter - ring that is waiting
1319 * @signaller - ring which has, or will signal
1320 * @seqno - seqno which the waiter will block on
1321 */
5ee426ca
BW		 1322
1323static int
1324gen8_ring_sync(struct intel_engine_cs *waiter,
1325 struct intel_engine_cs *signaller,
1326 u32 seqno)
1327{
1328 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1329 int ret;
1330
1331 ret = intel_ring_begin(waiter, 4);
1332 if (ret)
1333 return ret;
1334
1335 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1336 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1337 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1338 MI_SEMAPHORE_SAD_GTE_SDD);
1339 intel_ring_emit(waiter, seqno);
1340 intel_ring_emit(waiter,
1341 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1342 intel_ring_emit(waiter,
1343 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1344 intel_ring_advance(waiter);
1345 return 0;
1346}
1347
c8c99b0f 1348static int
a4872ba6
OM		 1349gen6_ring_sync(struct intel_engine_cs *waiter,
1350 struct intel_engine_cs *signaller,
686cb5f9 1351 u32 seqno)
1ec14ad3 1352{
c8c99b0f
BW		 1353 u32 dw1 = MI_SEMAPHORE_MBOX |
1354 MI_SEMAPHORE_COMPARE |
1355 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1356 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1357 int ret;
1ec14ad3 1358
1500f7ea
BW		 1359 /* Throughout all of the GEM code, seqno passed implies our current
1360 * seqno is >= the last seqno executed. However for hardware the
1361 * comparison is strictly greater than.
1362 */
1363 seqno -= 1;
1364
ebc348b2 1365 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1366
c8c99b0f 1367 ret = intel_ring_begin(waiter, 4);
1ec14ad3
CW		 1368 if (ret)
1369 return ret;
1370
f72b3435
MK		 1371 /* If seqno wrap happened, omit the wait with no-ops */
1372 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1373 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1374 intel_ring_emit(waiter, seqno);
1375 intel_ring_emit(waiter, 0);
1376 intel_ring_emit(waiter, MI_NOOP);
1377 } else {
1378 intel_ring_emit(waiter, MI_NOOP);
1379 intel_ring_emit(waiter, MI_NOOP);
1380 intel_ring_emit(waiter, MI_NOOP);
1381 intel_ring_emit(waiter, MI_NOOP);
1382 }
c8c99b0f 1383 intel_ring_advance(waiter);
1ec14ad3
CW		 1384
1385 return 0;
1386}
1387
c6df541c
CW		 1388#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1389do { \
fcbc34e4
KG		 1390 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1391 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1392 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1393 intel_ring_emit(ring__, 0); \
1394 intel_ring_emit(ring__, 0); \
1395} while (0)
1396
1397static int
a4872ba6 1398pc_render_add_request(struct intel_engine_cs *ring)
c6df541c 1399{
18393f63 1400 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1401 int ret;
1402
1403 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1404 * incoherent with writes to memory, i.e. completely fubar,
1405 * so we need to use PIPE_NOTIFY instead.
1406 *
1407 * However, we also need to workaround the qword write
1408 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1409 * memory before requesting an interrupt.
1410 */
1411 ret = intel_ring_begin(ring, 32);
1412 if (ret)
1413 return ret;
1414
fcbc34e4 1415 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1416 PIPE_CONTROL_WRITE_FLUSH |
1417 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
0d1aacac 1418 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1419 intel_ring_emit(ring,
1420 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c
CW		 1421 intel_ring_emit(ring, 0);
1422 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1423 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
c6df541c 1424 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1425 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1426 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1427 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1428 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1429 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
18393f63 1431 scratch_addr += 2 * CACHELINE_BYTES;
c6df541c 1432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
a71d8d94 1433
fcbc34e4 1434 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1435 PIPE_CONTROL_WRITE_FLUSH |
1436 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1437 PIPE_CONTROL_NOTIFY);
0d1aacac 1438 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
6259cead
JH		 1439 intel_ring_emit(ring,
1440 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
c6df541c 1441 intel_ring_emit(ring, 0);
09246732 1442 __intel_ring_advance(ring);
c6df541c 1443
c6df541c
CW		 1444 return 0;
1445}
1446
4cd53c0c 1447static u32
a4872ba6 1448gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
4cd53c0c 1449{
4cd53c0c
DV		 1450 /* Workaround to force correct ordering between irq and seqno writes on
1451 * ivb (and maybe also on snb) by reading from a CS register (like
1452 * ACTHD) before reading the status page. */
50877445
CW		 1453 if (!lazy_coherency) {
1454 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1455 POSTING_READ(RING_ACTHD(ring->mmio_base));
1456 }
1457
4cd53c0c
DV		 1458 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1459}
1460
8187a2b7 1461static u32
a4872ba6 1462ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
8187a2b7 1463{
1ec14ad3
CW		 1464 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1465}
1466
b70ec5bf 1467static void
a4872ba6 1468ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf
MK		 1469{
1470 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1471}
1472
c6df541c 1473static u32
a4872ba6 1474pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
c6df541c 1475{
0d1aacac 1476 return ring->scratch.cpu_page[0];
c6df541c
CW		 1477}
1478
b70ec5bf 1479static void
a4872ba6 1480pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
b70ec5bf 1481{
0d1aacac 1482 ring->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1483}
1484
e48d8634 1485static bool
a4872ba6 1486gen5_ring_get_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1487{
1488 struct drm_device *dev = ring->dev;
4640c4ff 1489 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1490 unsigned long flags;
e48d8634 1491
7cd512f1 1492 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1493 return false;
1494
7338aefa 1495 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1496 if (ring->irq_refcount++ == 0)
480c8033 1497 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1498 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1499
1500 return true;
1501}
1502
1503static void
a4872ba6 1504gen5_ring_put_irq(struct intel_engine_cs *ring)
e48d8634
DV		 1505{
1506 struct drm_device *dev = ring->dev;
4640c4ff 1507 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1508 unsigned long flags;
e48d8634 1509
7338aefa 1510 spin_lock_irqsave(&dev_priv->irq_lock, flags);
43eaea13 1511 if (--ring->irq_refcount == 0)
480c8033 1512 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
7338aefa 1513 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1514}
1515
b13c2b96 1516static bool
a4872ba6 1517i9xx_ring_get_irq(struct intel_engine_cs *ring)
62fdfeaf 1518{
78501eac 1519 struct drm_device *dev = ring->dev;
4640c4ff 1520 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1521 unsigned long flags;
62fdfeaf 1522
7cd512f1 1523 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1524 return false;
1525
7338aefa 1526 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1527 if (ring->irq_refcount++ == 0) {
f637fde4
DV		 1528 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1529 I915_WRITE(IMR, dev_priv->irq_mask);
1530 POSTING_READ(IMR);
1531 }
7338aefa 1532 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1533
1534 return true;
62fdfeaf
EA		 1535}
1536
8187a2b7 1537static void
a4872ba6 1538i9xx_ring_put_irq(struct intel_engine_cs *ring)
62fdfeaf 1539{
78501eac 1540 struct drm_device *dev = ring->dev;
4640c4ff 1541 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1542 unsigned long flags;
62fdfeaf 1543
7338aefa 1544 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1545 if (--ring->irq_refcount == 0) {
f637fde4
DV		 1546 dev_priv->irq_mask |= ring->irq_enable_mask;
1547 I915_WRITE(IMR, dev_priv->irq_mask);
1548 POSTING_READ(IMR);
1549 }
7338aefa 1550 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1551}
1552
c2798b19 1553static bool
a4872ba6 1554i8xx_ring_get_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1555{
1556 struct drm_device *dev = ring->dev;
4640c4ff 1557 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1558 unsigned long flags;
c2798b19 1559
7cd512f1 1560 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1561 return false;
1562
7338aefa 1563 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1564 if (ring->irq_refcount++ == 0) {
c2798b19
CW		 1565 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1566 I915_WRITE16(IMR, dev_priv->irq_mask);
1567 POSTING_READ16(IMR);
1568 }
7338aefa 1569 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1570
1571 return true;
1572}
1573
1574static void
a4872ba6 1575i8xx_ring_put_irq(struct intel_engine_cs *ring)
c2798b19
CW		 1576{
1577 struct drm_device *dev = ring->dev;
4640c4ff 1578 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1579 unsigned long flags;
c2798b19 1580
7338aefa 1581 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1582 if (--ring->irq_refcount == 0) {
c2798b19
CW		 1583 dev_priv->irq_mask |= ring->irq_enable_mask;
1584 I915_WRITE16(IMR, dev_priv->irq_mask);
1585 POSTING_READ16(IMR);
1586 }
7338aefa 1587 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1588}
1589
b72f3acb 1590static int
a4872ba6 1591bsd_ring_flush(struct intel_engine_cs *ring,
78501eac
CW		 1592 u32 invalidate_domains,
1593 u32 flush_domains)
d1b851fc 1594{
b72f3acb
CW		 1595 int ret;
1596
b72f3acb
CW		 1597 ret = intel_ring_begin(ring, 2);
1598 if (ret)
1599 return ret;
1600
1601 intel_ring_emit(ring, MI_FLUSH);
1602 intel_ring_emit(ring, MI_NOOP);
1603 intel_ring_advance(ring);
1604 return 0;
d1b851fc
ZN		 1605}
1606
3cce469c 1607static int
a4872ba6 1608i9xx_add_request(struct intel_engine_cs *ring)
d1b851fc 1609{
3cce469c
CW		 1610 int ret;
1611
1612 ret = intel_ring_begin(ring, 4);
1613 if (ret)
1614 return ret;
6f392d54 1615
3cce469c
CW		 1616 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1617 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
6259cead
JH		 1618 intel_ring_emit(ring,
1619 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
3cce469c 1620 intel_ring_emit(ring, MI_USER_INTERRUPT);
09246732 1621 __intel_ring_advance(ring);
d1b851fc 1622
3cce469c 1623 return 0;
d1b851fc
ZN		 1624}
1625
0f46832f 1626static bool
a4872ba6 1627gen6_ring_get_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1628{
1629 struct drm_device *dev = ring->dev;
4640c4ff 1630 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1631 unsigned long flags;
0f46832f 1632
7cd512f1
DV		 1633 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1634 return false;
0f46832f 1635
7338aefa 1636 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1637 if (ring->irq_refcount++ == 0) {
040d2baa 1638 if (HAS_L3_DPF(dev) && ring->id == RCS)
cc609d5d
BW		 1639 I915_WRITE_IMR(ring,
1640 ~(ring->irq_enable_mask |
35a85ac6 1641 GT_PARITY_ERROR(dev)));
15b9f80e
BW		 1642 else
1643 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1644 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
0f46832f 1645 }
7338aefa 1646 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1647
1648 return true;
1649}
1650
1651static void
a4872ba6 1652gen6_ring_put_irq(struct intel_engine_cs *ring)
0f46832f
CW		 1653{
1654 struct drm_device *dev = ring->dev;
4640c4ff 1655 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1656 unsigned long flags;
0f46832f 1657
7338aefa 1658 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1659 if (--ring->irq_refcount == 0) {
040d2baa 1660 if (HAS_L3_DPF(dev) && ring->id == RCS)
35a85ac6 1661 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
15b9f80e
BW		 1662 else
1663 I915_WRITE_IMR(ring, ~0);
480c8033 1664 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1ec14ad3 1665 }
7338aefa 1666 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1667}
1668
a19d2933 1669static bool
a4872ba6 1670hsw_vebox_get_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1671{
1672 struct drm_device *dev = ring->dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 unsigned long flags;
1675
7cd512f1 1676 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1677 return false;
1678
59cdb63d 1679 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1680 if (ring->irq_refcount++ == 0) {
a19d2933 1681 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
480c8033 1682 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1683 }
59cdb63d 1684 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1685
1686 return true;
1687}
1688
1689static void
a4872ba6 1690hsw_vebox_put_irq(struct intel_engine_cs *ring)
a19d2933
BW		 1691{
1692 struct drm_device *dev = ring->dev;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 unsigned long flags;
1695
59cdb63d 1696 spin_lock_irqsave(&dev_priv->irq_lock, flags);
c7113cc3 1697 if (--ring->irq_refcount == 0) {
a19d2933 1698 I915_WRITE_IMR(ring, ~0);
480c8033 1699 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
a19d2933 1700 }
59cdb63d 1701 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1702}
1703
abd58f01 1704static bool
a4872ba6 1705gen8_ring_get_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1706{
1707 struct drm_device *dev = ring->dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709 unsigned long flags;
1710
7cd512f1 1711 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1712 return false;
1713
1714 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1715 if (ring->irq_refcount++ == 0) {
1716 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1717 I915_WRITE_IMR(ring,
1718 ~(ring->irq_enable_mask |
1719 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1720 } else {
1721 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1722 }
1723 POSTING_READ(RING_IMR(ring->mmio_base));
1724 }
1725 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1726
1727 return true;
1728}
1729
1730static void
a4872ba6 1731gen8_ring_put_irq(struct intel_engine_cs *ring)
abd58f01
BW		 1732{
1733 struct drm_device *dev = ring->dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 unsigned long flags;
1736
1737 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1738 if (--ring->irq_refcount == 0) {
1739 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1740 I915_WRITE_IMR(ring,
1741 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1742 } else {
1743 I915_WRITE_IMR(ring, ~0);
1744 }
1745 POSTING_READ(RING_IMR(ring->mmio_base));
1746 }
1747 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1748}
1749
d1b851fc 1750static int
a4872ba6 1751i965_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1752 u64 offset, u32 length,
8e004efc 1753 unsigned dispatch_flags)
d1b851fc 1754{
e1f99ce6 1755 int ret;
78501eac 1756
e1f99ce6
CW		 1757 ret = intel_ring_begin(ring, 2);
1758 if (ret)
1759 return ret;
1760
78501eac 1761 intel_ring_emit(ring,
65f56876
CW		 1762 MI_BATCH_BUFFER_START |
1763 MI_BATCH_GTT |
8e004efc
JH		 1764 (dispatch_flags & I915_DISPATCH_SECURE ?
1765 0 : MI_BATCH_NON_SECURE_I965));
c4e7a414 1766 intel_ring_emit(ring, offset);
78501eac
CW		 1767 intel_ring_advance(ring);
1768
d1b851fc
ZN		 1769 return 0;
1770}
1771
b45305fc
DV		 1772/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1773#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1774#define I830_TLB_ENTRIES (2)
1775#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1776static int
a4872ba6 1777i830_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 1778 u64 offset, u32 len,
1779 unsigned dispatch_flags)
62fdfeaf 1780{
c4d69da1 1781 u32 cs_offset = ring->scratch.gtt_offset;
c4e7a414 1782 int ret;
62fdfeaf 1783
c4d69da1
CW		 1784 ret = intel_ring_begin(ring, 6);
1785 if (ret)
1786 return ret;
62fdfeaf 1787
c4d69da1
CW		 1788 /* Evict the invalid PTE TLBs */
1789 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1790 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1791 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1792 intel_ring_emit(ring, cs_offset);
1793 intel_ring_emit(ring, 0xdeadbeef);
1794 intel_ring_emit(ring, MI_NOOP);
1795 intel_ring_advance(ring);
b45305fc 1796
8e004efc 1797 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1798 if (len > I830_BATCH_LIMIT)
1799 return -ENOSPC;
1800
c4d69da1 1801 ret = intel_ring_begin(ring, 6 + 2);
b45305fc
DV		 1802 if (ret)
1803 return ret;
c4d69da1
CW		 1804
1805 /* Blit the batch (which has now all relocs applied) to the
1806 * stable batch scratch bo area (so that the CS never
1807 * stumbles over its tlb invalidation bug) ...
1808 */
1809 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1810 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
611a7a4f 1811 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
b45305fc 1812 intel_ring_emit(ring, cs_offset);
b45305fc
DV		 1813 intel_ring_emit(ring, 4096);
1814 intel_ring_emit(ring, offset);
c4d69da1 1815
b45305fc 1816 intel_ring_emit(ring, MI_FLUSH);
c4d69da1
CW		 1817 intel_ring_emit(ring, MI_NOOP);
1818 intel_ring_advance(ring);
b45305fc
DV		 1819
1820 /* ... and execute it. */
c4d69da1 1821 offset = cs_offset;
b45305fc 1822 }
e1f99ce6 1823
c4d69da1
CW		 1824 ret = intel_ring_begin(ring, 4);
1825 if (ret)
1826 return ret;
1827
1828 intel_ring_emit(ring, MI_BATCH_BUFFER);
8e004efc
JH		 1829 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1830 0 : MI_BATCH_NON_SECURE));
c4d69da1
CW		 1831 intel_ring_emit(ring, offset + len - 8);
1832 intel_ring_emit(ring, MI_NOOP);
1833 intel_ring_advance(ring);
1834
fb3256da
DV		 1835 return 0;
1836}
1837
1838static int
a4872ba6 1839i915_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 1840 u64 offset, u32 len,
8e004efc 1841 unsigned dispatch_flags)
fb3256da
DV		 1842{
1843 int ret;
1844
1845 ret = intel_ring_begin(ring, 2);
1846 if (ret)
1847 return ret;
1848
65f56876 1849 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
8e004efc
JH		 1850 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1851 0 : MI_BATCH_NON_SECURE));
c4e7a414 1852 intel_ring_advance(ring);
62fdfeaf 1853
62fdfeaf
EA		 1854 return 0;
1855}
1856
a4872ba6 1857static void cleanup_status_page(struct intel_engine_cs *ring)
62fdfeaf 1858{
05394f39 1859 struct drm_i915_gem_object *obj;
62fdfeaf 1860
8187a2b7
ZN		 1861 obj = ring->status_page.obj;
1862 if (obj == NULL)
62fdfeaf 1863 return;
62fdfeaf 1864
9da3da66 1865 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1866 i915_gem_object_ggtt_unpin(obj);
05394f39 1867 drm_gem_object_unreference(&obj->base);
8187a2b7 1868 ring->status_page.obj = NULL;
62fdfeaf
EA		 1869}
1870
a4872ba6 1871static int init_status_page(struct intel_engine_cs *ring)
62fdfeaf 1872{
05394f39 1873 struct drm_i915_gem_object *obj;
62fdfeaf 1874
e3efda49 1875 if ((obj = ring->status_page.obj) == NULL) {
1f767e02 1876 unsigned flags;
e3efda49 1877 int ret;
e4ffd173 1878
e3efda49
CW		 1879 obj = i915_gem_alloc_object(ring->dev, 4096);
1880 if (obj == NULL) {
1881 DRM_ERROR("Failed to allocate status page\n");
1882 return -ENOMEM;
1883 }
62fdfeaf 1884
e3efda49
CW		 1885 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1886 if (ret)
1887 goto err_unref;
1888
1f767e02
CW		 1889 flags = 0;
1890 if (!HAS_LLC(ring->dev))
1891 /* On g33, we cannot place HWS above 256MiB, so
1892 * restrict its pinning to the low mappable arena.
1893 * Though this restriction is not documented for
1894 * gen4, gen5, or byt, they also behave similarly
1895 * and hang if the HWS is placed at the top of the
1896 * GTT. To generalise, it appears that all !llc
1897 * platforms have issues with us placing the HWS
1898 * above the mappable region (even though we never
1899 * actualy map it).
1900 */
1901 flags |= PIN_MAPPABLE;
1902 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 1903 if (ret) {
1904err_unref:
1905 drm_gem_object_unreference(&obj->base);
1906 return ret;
1907 }
1908
1909 ring->status_page.obj = obj;
1910 }
62fdfeaf 1911
f343c5f6 1912 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
9da3da66 1913 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
8187a2b7 1914 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 1915
8187a2b7
ZN		 1916 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1917 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 1918
1919 return 0;
62fdfeaf
EA		 1920}
1921
a4872ba6 1922static int init_phys_status_page(struct intel_engine_cs *ring)
6b8294a4
CW		 1923{
1924 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6b8294a4
CW		 1925
1926 if (!dev_priv->status_page_dmah) {
1927 dev_priv->status_page_dmah =
1928 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1929 if (!dev_priv->status_page_dmah)
1930 return -ENOMEM;
1931 }
1932
6b8294a4
CW		 1933 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1934 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1935
1936 return 0;
1937}
1938
7ba717cf 1939void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 1940{
2919d291 1941 iounmap(ringbuf->virtual_start);
7ba717cf 1942 ringbuf->virtual_start = NULL;
2919d291 1943 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 1944}
1945
1946int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
1947 struct intel_ringbuffer *ringbuf)
1948{
1949 struct drm_i915_private *dev_priv = to_i915(dev);
1950 struct drm_i915_gem_object *obj = ringbuf->obj;
1951 int ret;
1952
1953 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1954 if (ret)
1955 return ret;
1956
1957 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1958 if (ret) {
1959 i915_gem_object_ggtt_unpin(obj);
1960 return ret;
1961 }
1962
1963 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
1964 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
1965 if (ringbuf->virtual_start == NULL) {
1966 i915_gem_object_ggtt_unpin(obj);
1967 return -EINVAL;
1968 }
1969
1970 return 0;
1971}
1972
1973void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1974{
2919d291
OM		 1975 drm_gem_object_unreference(&ringbuf->obj->base);
1976 ringbuf->obj = NULL;
1977}
1978
84c2377f
OM		 1979int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1980 struct intel_ringbuffer *ringbuf)
62fdfeaf 1981{
05394f39 1982 struct drm_i915_gem_object *obj;
62fdfeaf 1983
ebc052e0
CW		 1984 obj = NULL;
1985 if (!HAS_LLC(dev))
93b0a4e0 1986 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 1987 if (obj == NULL)
93b0a4e0 1988 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 1989 if (obj == NULL)
1990 return -ENOMEM;
8187a2b7 1991
24f3a8cf
AG		 1992 /* mark ring buffers as read-only from GPU side by default */
1993 obj->gt_ro = 1;
1994
93b0a4e0 1995 ringbuf->obj = obj;
e3efda49 1996
7ba717cf 1997 return 0;
e3efda49
CW		 1998}
1999
2000static int intel_init_ring_buffer(struct drm_device *dev,
a4872ba6 2001 struct intel_engine_cs *ring)
e3efda49 2002{
bfc882b4 2003 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2004 int ret;
2005
bfc882b4
DV		 2006 WARN_ON(ring->buffer);
2007
2008 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2009 if (!ringbuf)
2010 return -ENOMEM;
2011 ring->buffer = ringbuf;
8ee14975 2012
e3efda49
CW		 2013 ring->dev = dev;
2014 INIT_LIST_HEAD(&ring->active_list);
2015 INIT_LIST_HEAD(&ring->request_list);
cc9130be 2016 INIT_LIST_HEAD(&ring->execlist_queue);
06fbca71 2017 i915_gem_batch_pool_init(dev, &ring->batch_pool);
93b0a4e0 2018 ringbuf->size = 32 * PAGE_SIZE;
0c7dd53b 2019 ringbuf->ring = ring;
ebc348b2 2020 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
e3efda49
CW		 2021
2022 init_waitqueue_head(&ring->irq_queue);
2023
2024 if (I915_NEED_GFX_HWS(dev)) {
2025 ret = init_status_page(ring);
2026 if (ret)
8ee14975 2027 goto error;
e3efda49
CW		 2028 } else {
2029 BUG_ON(ring->id != RCS);
2030 ret = init_phys_status_page(ring);
2031 if (ret)
8ee14975 2032 goto error;
e3efda49
CW		 2033 }
2034
bfc882b4 2035 WARN_ON(ringbuf->obj);
7ba717cf 2036
bfc882b4
DV		 2037 ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
2038 if (ret) {
2039 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
2040 ring->name, ret);
2041 goto error;
2042 }
2043
2044 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2045 if (ret) {
2046 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2047 ring->name, ret);
2048 intel_destroy_ringbuffer_obj(ringbuf);
2049 goto error;
e3efda49 2050 }
62fdfeaf 2051
55249baa
CW		 2052 /* Workaround an erratum on the i830 which causes a hang if
2053 * the TAIL pointer points to within the last 2 cachelines
2054 * of the buffer.
2055 */
93b0a4e0 2056 ringbuf->effective_size = ringbuf->size;
e3efda49 2057 if (IS_I830(dev) || IS_845G(dev))
93b0a4e0 2058 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
55249baa 2059
44e895a8
BV		 2060 ret = i915_cmd_parser_init_ring(ring);
2061 if (ret)
8ee14975
OM		 2062 goto error;
2063
8ee14975 2064 return 0;
351e3db2 2065
8ee14975
OM		 2066error:
2067 kfree(ringbuf);
2068 ring->buffer = NULL;
2069 return ret;
62fdfeaf
EA		 2070}
2071
a4872ba6 2072void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
62fdfeaf 2073{
6402c330
JH		 2074 struct drm_i915_private *dev_priv;
2075 struct intel_ringbuffer *ringbuf;
33626e6a 2076
93b0a4e0 2077 if (!intel_ring_initialized(ring))
62fdfeaf
EA		 2078 return;
2079
6402c330
JH		 2080 dev_priv = to_i915(ring->dev);
2081 ringbuf = ring->buffer;
2082
e3efda49 2083 intel_stop_ring_buffer(ring);
de8f0a50 2084 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
33626e6a 2085
7ba717cf 2086 intel_unpin_ringbuffer_obj(ringbuf);
2919d291 2087 intel_destroy_ringbuffer_obj(ringbuf);
6259cead 2088 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL);
78501eac 2089
8d19215b
ZN		 2090 if (ring->cleanup)
2091 ring->cleanup(ring);
2092
78501eac 2093 cleanup_status_page(ring);
44e895a8
BV		 2094
2095 i915_cmd_parser_fini_ring(ring);
06fbca71 2096 i915_gem_batch_pool_fini(&ring->batch_pool);
8ee14975 2097
93b0a4e0 2098 kfree(ringbuf);
8ee14975 2099 ring->buffer = NULL;
62fdfeaf
EA		 2100}
2101
595e1eeb 2102static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
a71d8d94 2103{
93b0a4e0 2104 struct intel_ringbuffer *ringbuf = ring->buffer;
a71d8d94 2105 struct drm_i915_gem_request *request;
dbe4646d 2106 int ret, new_space;
a71d8d94 2107
ebd0fd4b
DG		 2108 if (intel_ring_space(ringbuf) >= n)
2109 return 0;
a71d8d94
CW		 2110
2111 list_for_each_entry(request, &ring->request_list, list) {
dbe4646d
JH		 2112 new_space = __intel_ring_space(request->postfix, ringbuf->tail,
2113 ringbuf->size);
2114 if (new_space >= n)
a71d8d94 2115 break;
a71d8d94
CW		 2116 }
2117
595e1eeb 2118 if (WARN_ON(&request->list == &ring->request_list))
a71d8d94
CW		 2119 return -ENOSPC;
2120
a4b3a571 2121 ret = i915_wait_request(request);
a71d8d94
CW		 2122 if (ret)
2123 return ret;
2124
1cf0ba14 2125 i915_gem_retire_requests_ring(ring);
a71d8d94 2126
dbe4646d
JH		 2127 WARN_ON(intel_ring_space(ringbuf) < new_space);
2128
a71d8d94
CW		 2129 return 0;
2130}
2131
a4872ba6 2132static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
3e960501
CW		 2133{
2134 uint32_t __iomem *virt;
93b0a4e0
OM		 2135 struct intel_ringbuffer *ringbuf = ring->buffer;
2136 int rem = ringbuf->size - ringbuf->tail;
3e960501 2137
93b0a4e0 2138 if (ringbuf->space < rem) {
3e960501
CW		 2139 int ret = ring_wait_for_space(ring, rem);
2140 if (ret)
2141 return ret;
2142 }
2143
93b0a4e0 2144 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2145 rem /= 4;
2146 while (rem--)
2147 iowrite32(MI_NOOP, virt++);
2148
93b0a4e0 2149 ringbuf->tail = 0;
ebd0fd4b 2150 intel_ring_update_space(ringbuf);
3e960501
CW		 2151
2152 return 0;
2153}
2154
a4872ba6 2155int intel_ring_idle(struct intel_engine_cs *ring)
3e960501 2156{
a4b3a571 2157 struct drm_i915_gem_request *req;
3e960501
CW		 2158 int ret;
2159
2160 /* We need to add any requests required to flush the objects and ring */
6259cead 2161 if (ring->outstanding_lazy_request) {
9400ae5c 2162 ret = i915_add_request(ring);
3e960501
CW		 2163 if (ret)
2164 return ret;
2165 }
2166
2167 /* Wait upon the last request to be completed */
2168 if (list_empty(&ring->request_list))
2169 return 0;
2170
a4b3a571 2171 req = list_entry(ring->request_list.prev,
3e960501 2172 struct drm_i915_gem_request,
a4b3a571 2173 list);
3e960501 2174
a4b3a571 2175 return i915_wait_request(req);
3e960501
CW		 2176}
2177
6689cb2b 2178int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2179{
6689cb2b 2180 request->ringbuf = request->ring->buffer;
9eba5d4a 2181 return 0;
9d773091
CW		 2182}
2183
a4872ba6 2184static int __intel_ring_prepare(struct intel_engine_cs *ring,
304d695c 2185 int bytes)
cbcc80df 2186{
93b0a4e0 2187 struct intel_ringbuffer *ringbuf = ring->buffer;
cbcc80df
MK		 2188 int ret;
2189
93b0a4e0 2190 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
cbcc80df
MK		 2191 ret = intel_wrap_ring_buffer(ring);
2192 if (unlikely(ret))
2193 return ret;
2194 }
2195
93b0a4e0 2196 if (unlikely(ringbuf->space < bytes)) {
cbcc80df
MK		 2197 ret = ring_wait_for_space(ring, bytes);
2198 if (unlikely(ret))
2199 return ret;
2200 }
2201
cbcc80df
MK		 2202 return 0;
2203}
2204
a4872ba6 2205int intel_ring_begin(struct intel_engine_cs *ring,
e1f99ce6 2206 int num_dwords)
8187a2b7 2207{
4640c4ff 2208 struct drm_i915_private *dev_priv = ring->dev->dev_private;
e1f99ce6 2209 int ret;
78501eac 2210
33196ded
DV		 2211 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2212 dev_priv->mm.interruptible);
de2b9985
DV		 2213 if (ret)
2214 return ret;
21dd3734 2215
304d695c
CW		 2216 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2217 if (ret)
2218 return ret;
2219
9d773091 2220 /* Preallocate the olr before touching the ring */
6689cb2b 2221 ret = i915_gem_request_alloc(ring, ring->default_context);
9d773091
CW		 2222 if (ret)
2223 return ret;
2224
ee1b1e5e 2225 ring->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2226 return 0;
8187a2b7 2227}
78501eac 2228
753b1ad4 2229/* Align the ring tail to a cacheline boundary */
a4872ba6 2230int intel_ring_cacheline_align(struct intel_engine_cs *ring)
753b1ad4 2231{
ee1b1e5e 2232 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2233 int ret;
2234
2235 if (num_dwords == 0)
2236 return 0;
2237
18393f63 2238 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
753b1ad4
VS		 2239 ret = intel_ring_begin(ring, num_dwords);
2240 if (ret)
2241 return ret;
2242
2243 while (num_dwords--)
2244 intel_ring_emit(ring, MI_NOOP);
2245
2246 intel_ring_advance(ring);
2247
2248 return 0;
2249}
2250
a4872ba6 2251void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
498d2ac1 2252{
3b2cc8ab
OM		 2253 struct drm_device *dev = ring->dev;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2255
6259cead 2256 BUG_ON(ring->outstanding_lazy_request);
498d2ac1 2257
3b2cc8ab 2258 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
f7e98ad4
MK		 2259 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2260 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
3b2cc8ab 2261 if (HAS_VEBOX(dev))
5020150b 2262 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
e1f99ce6 2263 }
d97ed339 2264
f7e98ad4 2265 ring->set_seqno(ring, seqno);
92cab734 2266 ring->hangcheck.seqno = seqno;
8187a2b7 2267}
62fdfeaf 2268
a4872ba6 2269static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
297b0c5b 2270 u32 value)
881f47b6 2271{
4640c4ff 2272 struct drm_i915_private *dev_priv = ring->dev->dev_private;
881f47b6
XH		 2273
2274 /* Every tail move must follow the sequence below */
12f55818
CW		 2275
2276 /* Disable notification that the ring is IDLE. The GT
2277 * will then assume that it is busy and bring it out of rc6.
2278 */
0206e353 2279 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2280 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2281
2282 /* Clear the context id. Here be magic! */
2283 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2284
12f55818 2285 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2286 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2287 GEN6_BSD_SLEEP_INDICATOR) == 0,
2288 50))
2289 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2290
12f55818 2291 /* Now that the ring is fully powered up, update the tail */
0206e353 2292 I915_WRITE_TAIL(ring, value);
12f55818
CW		 2293 POSTING_READ(RING_TAIL(ring->mmio_base));
2294
2295 /* Let the ring send IDLE messages to the GT again,
2296 * and so let it sleep to conserve power when idle.
2297 */
0206e353 2298 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2299 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2300}
2301
a4872ba6 2302static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
ea251324 2303 u32 invalidate, u32 flush)
881f47b6 2304{
71a77e07 2305 uint32_t cmd;
b72f3acb
CW		 2306 int ret;
2307
b72f3acb
CW		 2308 ret = intel_ring_begin(ring, 4);
2309 if (ret)
2310 return ret;
2311
71a77e07 2312 cmd = MI_FLUSH_DW;
075b3bba
BW		 2313 if (INTEL_INFO(ring->dev)->gen >= 8)
2314 cmd += 1;
f0a1fb10
CW		 2315
2316 /* We always require a command barrier so that subsequent
2317 * commands, such as breadcrumb interrupts, are strictly ordered
2318 * wrt the contents of the write cache being flushed to memory
2319 * (and thus being coherent from the CPU).
2320 */
2321 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2322
9a289771
JB		 2323 /*
2324 * Bspec vol 1c.5 - video engine command streamer:
2325 * "If ENABLED, all TLBs will be invalidated once the flush
2326 * operation is complete. This bit is only valid when the
2327 * Post-Sync Operation field is a value of 1h or 3h."
2328 */
71a77e07 2329 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2330 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2331
71a77e07 2332 intel_ring_emit(ring, cmd);
9a289771 2333 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
075b3bba
BW		 2334 if (INTEL_INFO(ring->dev)->gen >= 8) {
2335 intel_ring_emit(ring, 0); /* upper addr */
2336 intel_ring_emit(ring, 0); /* value */
2337 } else {
2338 intel_ring_emit(ring, 0);
2339 intel_ring_emit(ring, MI_NOOP);
2340 }
b72f3acb
CW		 2341 intel_ring_advance(ring);
2342 return 0;
881f47b6
XH		 2343}
2344
1c7a0623 2345static int
a4872ba6 2346gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2347 u64 offset, u32 len,
8e004efc 2348 unsigned dispatch_flags)
1c7a0623 2349{
8e004efc
JH		 2350 bool ppgtt = USES_PPGTT(ring->dev) &&
2351 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2352 int ret;
2353
2354 ret = intel_ring_begin(ring, 4);
2355 if (ret)
2356 return ret;
2357
2358 /* FIXME(BDW): Address space and security selectors. */
28cf5415 2359 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
9bcb144c
BW		 2360 intel_ring_emit(ring, lower_32_bits(offset));
2361 intel_ring_emit(ring, upper_32_bits(offset));
1c7a0623
BW		 2362 intel_ring_emit(ring, MI_NOOP);
2363 intel_ring_advance(ring);
2364
2365 return 0;
2366}
2367
d7d4eedd 2368static int
a4872ba6 2369hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
8e004efc
JH		 2370 u64 offset, u32 len,
2371 unsigned dispatch_flags)
d7d4eedd
CW		 2372{
2373 int ret;
2374
2375 ret = intel_ring_begin(ring, 2);
2376 if (ret)
2377 return ret;
2378
2379 intel_ring_emit(ring,
77072258 2380 MI_BATCH_BUFFER_START |
8e004efc 2381 (dispatch_flags & I915_DISPATCH_SECURE ?
77072258 2382 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
d7d4eedd
CW		 2383 /* bit0-7 is the length on GEN6+ */
2384 intel_ring_emit(ring, offset);
2385 intel_ring_advance(ring);
2386
2387 return 0;
2388}
2389
881f47b6 2390static int
a4872ba6 2391gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
9bcb144c 2392 u64 offset, u32 len,
8e004efc 2393 unsigned dispatch_flags)
881f47b6 2394{
0206e353 2395 int ret;
ab6f8e32 2396
0206e353
AJ		 2397 ret = intel_ring_begin(ring, 2);
2398 if (ret)
2399 return ret;
e1f99ce6 2400
d7d4eedd
CW		 2401 intel_ring_emit(ring,
2402 MI_BATCH_BUFFER_START |
8e004efc
JH		 2403 (dispatch_flags & I915_DISPATCH_SECURE ?
2404 0 : MI_BATCH_NON_SECURE_I965));
0206e353
AJ		 2405 /* bit0-7 is the length on GEN6+ */
2406 intel_ring_emit(ring, offset);
2407 intel_ring_advance(ring);
ab6f8e32 2408
0206e353 2409 return 0;
881f47b6
XH		 2410}
2411
549f7365
CW		 2412/* Blitter support (SandyBridge+) */
2413
a4872ba6 2414static int gen6_ring_flush(struct intel_engine_cs *ring,
ea251324 2415 u32 invalidate, u32 flush)
8d19215b 2416{
fd3da6c9 2417 struct drm_device *dev = ring->dev;
71a77e07 2418 uint32_t cmd;
b72f3acb
CW		 2419 int ret;
2420
6a233c78 2421 ret = intel_ring_begin(ring, 4);
b72f3acb
CW		 2422 if (ret)
2423 return ret;
2424
71a77e07 2425 cmd = MI_FLUSH_DW;
dbef0f15 2426 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2427 cmd += 1;
f0a1fb10
CW		 2428
2429 /* We always require a command barrier so that subsequent
2430 * commands, such as breadcrumb interrupts, are strictly ordered
2431 * wrt the contents of the write cache being flushed to memory
2432 * (and thus being coherent from the CPU).
2433 */
2434 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2435
9a289771
JB		 2436 /*
2437 * Bspec vol 1c.3 - blitter engine command streamer:
2438 * "If ENABLED, all TLBs will be invalidated once the flush
2439 * operation is complete. This bit is only valid when the
2440 * Post-Sync Operation field is a value of 1h or 3h."
2441 */
71a77e07 2442 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2443 cmd |= MI_INVALIDATE_TLB;
71a77e07 2444 intel_ring_emit(ring, cmd);
9a289771 2445 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2446 if (INTEL_INFO(dev)->gen >= 8) {
075b3bba
BW		 2447 intel_ring_emit(ring, 0); /* upper addr */
2448 intel_ring_emit(ring, 0); /* value */
2449 } else {
2450 intel_ring_emit(ring, 0);
2451 intel_ring_emit(ring, MI_NOOP);
2452 }
b72f3acb 2453 intel_ring_advance(ring);
fd3da6c9 2454
b72f3acb 2455 return 0;
8d19215b
ZN		 2456}
2457
5c1143bb
XH		 2458int intel_init_render_ring_buffer(struct drm_device *dev)
2459{
4640c4ff 2460 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2461 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e78998a
BW		 2462 struct drm_i915_gem_object *obj;
2463 int ret;
5c1143bb 2464
59465b5f
DV		 2465 ring->name = "render ring";
2466 ring->id = RCS;
2467 ring->mmio_base = RENDER_RING_BASE;
2468
707d9cf9 2469 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2470 if (i915_semaphore_is_enabled(dev)) {
2471 obj = i915_gem_alloc_object(dev, 4096);
2472 if (obj == NULL) {
2473 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2474 i915.semaphores = 0;
2475 } else {
2476 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2477 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2478 if (ret != 0) {
2479 drm_gem_object_unreference(&obj->base);
2480 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2481 i915.semaphores = 0;
2482 } else
2483 dev_priv->semaphore_obj = obj;
2484 }
2485 }
7225342a 2486
8f0e2b9d 2487 ring->init_context = intel_rcs_ctx_init;
707d9cf9
BW		 2488 ring->add_request = gen6_add_request;
2489 ring->flush = gen8_render_ring_flush;
2490 ring->irq_get = gen8_ring_get_irq;
2491 ring->irq_put = gen8_ring_put_irq;
2492 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2493 ring->get_seqno = gen6_ring_get_seqno;
2494 ring->set_seqno = ring_set_seqno;
2495 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2496 WARN_ON(!dev_priv->semaphore_obj);
5ee426ca 2497 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2498 ring->semaphore.signal = gen8_rcs_signal;
2499 GEN8_RING_SEMAPHORE_INIT;
707d9cf9
BW		 2500 }
2501 } else if (INTEL_INFO(dev)->gen >= 6) {
1ec14ad3 2502 ring->add_request = gen6_add_request;
4772eaeb 2503 ring->flush = gen7_render_ring_flush;
6c6cf5aa 2504 if (INTEL_INFO(dev)->gen == 6)
b3111509 2505 ring->flush = gen6_render_ring_flush;
707d9cf9
BW		 2506 ring->irq_get = gen6_ring_get_irq;
2507 ring->irq_put = gen6_ring_put_irq;
cc609d5d 2508 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
4cd53c0c 2509 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2510 ring->set_seqno = ring_set_seqno;
707d9cf9
BW		 2511 if (i915_semaphore_is_enabled(dev)) {
2512 ring->semaphore.sync_to = gen6_ring_sync;
2513 ring->semaphore.signal = gen6_signal;
2514 /*
2515 * The current semaphore is only applied on pre-gen8
2516 * platform. And there is no VCS2 ring on the pre-gen8
2517 * platform. So the semaphore between RCS and VCS2 is
2518 * initialized as INVALID. Gen8 will initialize the
2519 * sema between VCS2 and RCS later.
2520 */
2521 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2522 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2523 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2524 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2525 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2526 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2527 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2528 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2529 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2530 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2531 }
c6df541c
CW		 2532 } else if (IS_GEN5(dev)) {
2533 ring->add_request = pc_render_add_request;
46f0f8d1 2534 ring->flush = gen4_render_ring_flush;
c6df541c 2535 ring->get_seqno = pc_render_get_seqno;
b70ec5bf 2536 ring->set_seqno = pc_render_set_seqno;
e48d8634
DV		 2537 ring->irq_get = gen5_ring_get_irq;
2538 ring->irq_put = gen5_ring_put_irq;
cc609d5d
BW		 2539 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2540 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2541 } else {
8620a3a9 2542 ring->add_request = i9xx_add_request;
46f0f8d1
CW		 2543 if (INTEL_INFO(dev)->gen < 4)
2544 ring->flush = gen2_render_ring_flush;
2545 else
2546 ring->flush = gen4_render_ring_flush;
59465b5f 2547 ring->get_seqno = ring_get_seqno;
b70ec5bf 2548 ring->set_seqno = ring_set_seqno;
c2798b19
CW		 2549 if (IS_GEN2(dev)) {
2550 ring->irq_get = i8xx_ring_get_irq;
2551 ring->irq_put = i8xx_ring_put_irq;
2552 } else {
2553 ring->irq_get = i9xx_ring_get_irq;
2554 ring->irq_put = i9xx_ring_put_irq;
2555 }
e3670319 2556 ring->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2557 }
59465b5f 2558 ring->write_tail = ring_write_tail;
707d9cf9 2559
d7d4eedd
CW		 2560 if (IS_HASWELL(dev))
2561 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623
BW		 2562 else if (IS_GEN8(dev))
2563 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2564 else if (INTEL_INFO(dev)->gen >= 6)
fb3256da
DV		 2565 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2566 else if (INTEL_INFO(dev)->gen >= 4)
2567 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2568 else if (IS_I830(dev) || IS_845G(dev))
2569 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2570 else
2571 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
ecfe00d8 2572 ring->init_hw = init_render_ring;
59465b5f
DV		 2573 ring->cleanup = render_ring_cleanup;
2574
b45305fc
DV		 2575 /* Workaround batchbuffer to combat CS tlb bug. */
2576 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2577 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2578 if (obj == NULL) {
2579 DRM_ERROR("Failed to allocate batch bo\n");
2580 return -ENOMEM;
2581 }
2582
be1fa129 2583 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2584 if (ret != 0) {
2585 drm_gem_object_unreference(&obj->base);
2586 DRM_ERROR("Failed to ping batch bo\n");
2587 return ret;
2588 }
2589
0d1aacac
CW		 2590 ring->scratch.obj = obj;
2591 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2592 }
2593
99be1dfe
DV		 2594 ret = intel_init_ring_buffer(dev, ring);
2595 if (ret)
2596 return ret;
2597
2598 if (INTEL_INFO(dev)->gen >= 5) {
2599 ret = intel_init_pipe_control(ring);
2600 if (ret)
2601 return ret;
2602 }
2603
2604 return 0;
5c1143bb
XH		 2605}
2606
2607int intel_init_bsd_ring_buffer(struct drm_device *dev)
2608{
4640c4ff 2609 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2610 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
5c1143bb 2611
58fa3835
DV		 2612 ring->name = "bsd ring";
2613 ring->id = VCS;
2614
0fd2c201 2615 ring->write_tail = ring_write_tail;
780f18c8 2616 if (INTEL_INFO(dev)->gen >= 6) {
58fa3835 2617 ring->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2618 /* gen6 bsd needs a special wa for tail updates */
2619 if (IS_GEN6(dev))
2620 ring->write_tail = gen6_bsd_ring_write_tail;
ea251324 2621 ring->flush = gen6_bsd_ring_flush;
58fa3835
DV		 2622 ring->add_request = gen6_add_request;
2623 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2624 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2625 if (INTEL_INFO(dev)->gen >= 8) {
2626 ring->irq_enable_mask =
2627 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2628 ring->irq_get = gen8_ring_get_irq;
2629 ring->irq_put = gen8_ring_put_irq;
1c7a0623
BW		 2630 ring->dispatch_execbuffer =
2631 gen8_ring_dispatch_execbuffer;
707d9cf9 2632 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2633 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2634 ring->semaphore.signal = gen8_xcs_signal;
2635 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2636 }
abd58f01
BW		 2637 } else {
2638 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2639 ring->irq_get = gen6_ring_get_irq;
2640 ring->irq_put = gen6_ring_put_irq;
1c7a0623
BW		 2641 ring->dispatch_execbuffer =
2642 gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2643 if (i915_semaphore_is_enabled(dev)) {
2644 ring->semaphore.sync_to = gen6_ring_sync;
2645 ring->semaphore.signal = gen6_signal;
2646 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2647 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2648 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2649 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2650 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2651 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2652 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2653 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2654 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2655 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2656 }
abd58f01 2657 }
58fa3835
DV		 2658 } else {
2659 ring->mmio_base = BSD_RING_BASE;
58fa3835 2660 ring->flush = bsd_ring_flush;
8620a3a9 2661 ring->add_request = i9xx_add_request;
58fa3835 2662 ring->get_seqno = ring_get_seqno;
b70ec5bf 2663 ring->set_seqno = ring_set_seqno;
e48d8634 2664 if (IS_GEN5(dev)) {
cc609d5d 2665 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
e48d8634
DV		 2666 ring->irq_get = gen5_ring_get_irq;
2667 ring->irq_put = gen5_ring_put_irq;
2668 } else {
e3670319 2669 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
e48d8634
DV		 2670 ring->irq_get = i9xx_ring_get_irq;
2671 ring->irq_put = i9xx_ring_put_irq;
2672 }
fb3256da 2673 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2674 }
ecfe00d8 2675 ring->init_hw = init_ring_common;
58fa3835 2676
1ec14ad3 2677 return intel_init_ring_buffer(dev, ring);
5c1143bb 2678}
549f7365 2679
845f74a7 2680/**
62659920 2681 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2682 */
2683int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2684{
2685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2686 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
845f74a7 2687
f7b64236 2688 ring->name = "bsd2 ring";
845f74a7
ZY		 2689 ring->id = VCS2;
2690
2691 ring->write_tail = ring_write_tail;
2692 ring->mmio_base = GEN8_BSD2_RING_BASE;
2693 ring->flush = gen6_bsd_ring_flush;
2694 ring->add_request = gen6_add_request;
2695 ring->get_seqno = gen6_ring_get_seqno;
2696 ring->set_seqno = ring_set_seqno;
2697 ring->irq_enable_mask =
2698 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2699 ring->irq_get = gen8_ring_get_irq;
2700 ring->irq_put = gen8_ring_put_irq;
2701 ring->dispatch_execbuffer =
2702 gen8_ring_dispatch_execbuffer;
3e78998a 2703 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2704 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2705 ring->semaphore.signal = gen8_xcs_signal;
2706 GEN8_RING_SEMAPHORE_INIT;
2707 }
ecfe00d8 2708 ring->init_hw = init_ring_common;
845f74a7
ZY		 2709
2710 return intel_init_ring_buffer(dev, ring);
2711}
2712
549f7365
CW		 2713int intel_init_blt_ring_buffer(struct drm_device *dev)
2714{
4640c4ff 2715 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2716 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
549f7365 2717
3535d9dd
DV		 2718 ring->name = "blitter ring";
2719 ring->id = BCS;
2720
2721 ring->mmio_base = BLT_RING_BASE;
2722 ring->write_tail = ring_write_tail;
ea251324 2723 ring->flush = gen6_ring_flush;
3535d9dd
DV		 2724 ring->add_request = gen6_add_request;
2725 ring->get_seqno = gen6_ring_get_seqno;
b70ec5bf 2726 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2727 if (INTEL_INFO(dev)->gen >= 8) {
2728 ring->irq_enable_mask =
2729 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2730 ring->irq_get = gen8_ring_get_irq;
2731 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2732 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2733 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2734 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2735 ring->semaphore.signal = gen8_xcs_signal;
2736 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2737 }
abd58f01
BW		 2738 } else {
2739 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2740 ring->irq_get = gen6_ring_get_irq;
2741 ring->irq_put = gen6_ring_put_irq;
1c7a0623 2742 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2743 if (i915_semaphore_is_enabled(dev)) {
2744 ring->semaphore.signal = gen6_signal;
2745 ring->semaphore.sync_to = gen6_ring_sync;
2746 /*
2747 * The current semaphore is only applied on pre-gen8
2748 * platform. And there is no VCS2 ring on the pre-gen8
2749 * platform. So the semaphore between BCS and VCS2 is
2750 * initialized as INVALID. Gen8 will initialize the
2751 * sema between BCS and VCS2 later.
2752 */
2753 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2754 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2755 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2756 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2757 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2758 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2759 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2760 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2761 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2762 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2763 }
abd58f01 2764 }
ecfe00d8 2765 ring->init_hw = init_ring_common;
549f7365 2766
1ec14ad3 2767 return intel_init_ring_buffer(dev, ring);
549f7365 2768}
a7b9761d 2769
9a8a2213
BW		 2770int intel_init_vebox_ring_buffer(struct drm_device *dev)
2771{
4640c4ff 2772 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2773 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
9a8a2213
BW		 2774
2775 ring->name = "video enhancement ring";
2776 ring->id = VECS;
2777
2778 ring->mmio_base = VEBOX_RING_BASE;
2779 ring->write_tail = ring_write_tail;
2780 ring->flush = gen6_ring_flush;
2781 ring->add_request = gen6_add_request;
2782 ring->get_seqno = gen6_ring_get_seqno;
2783 ring->set_seqno = ring_set_seqno;
abd58f01
BW		 2784
2785 if (INTEL_INFO(dev)->gen >= 8) {
2786 ring->irq_enable_mask =
40c499f9 2787 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
abd58f01
BW		 2788 ring->irq_get = gen8_ring_get_irq;
2789 ring->irq_put = gen8_ring_put_irq;
1c7a0623 2790 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 2791 if (i915_semaphore_is_enabled(dev)) {
5ee426ca 2792 ring->semaphore.sync_to = gen8_ring_sync;
3e78998a
BW		 2793 ring->semaphore.signal = gen8_xcs_signal;
2794 GEN8_RING_SEMAPHORE_INIT;
707d9cf9 2795 }
abd58f01
BW		 2796 } else {
2797 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2798 ring->irq_get = hsw_vebox_get_irq;
2799 ring->irq_put = hsw_vebox_put_irq;
1c7a0623 2800 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9
BW		 2801 if (i915_semaphore_is_enabled(dev)) {
2802 ring->semaphore.sync_to = gen6_ring_sync;
2803 ring->semaphore.signal = gen6_signal;
2804 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2805 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2806 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2807 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2808 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2809 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2810 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2811 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2812 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2813 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2814 }
abd58f01 2815 }
ecfe00d8 2816 ring->init_hw = init_ring_common;
9a8a2213
BW		 2817
2818 return intel_init_ring_buffer(dev, ring);
2819}
2820
a7b9761d 2821int
a4872ba6 2822intel_ring_flush_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2823{
2824 int ret;
2825
2826 if (!ring->gpu_caches_dirty)
2827 return 0;
2828
2829 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2830 if (ret)
2831 return ret;
2832
2833 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2834
2835 ring->gpu_caches_dirty = false;
2836 return 0;
2837}
2838
2839int
a4872ba6 2840intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
a7b9761d
CW		 2841{
2842 uint32_t flush_domains;
2843 int ret;
2844
2845 flush_domains = 0;
2846 if (ring->gpu_caches_dirty)
2847 flush_domains = I915_GEM_GPU_DOMAINS;
2848
2849 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2850 if (ret)
2851 return ret;
2852
2853 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2854
2855 ring->gpu_caches_dirty = false;
2856 return 0;
2857}
e3efda49
CW		 2858
2859void
a4872ba6 2860intel_stop_ring_buffer(struct intel_engine_cs *ring)
e3efda49
CW		 2861{
2862 int ret;
2863
2864 if (!intel_ring_initialized(ring))
2865 return;
2866
2867 ret = intel_ring_idle(ring);
2868 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2869 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2870 ring->name, ret);
2871
2872 stop_ring(ring);
2873}
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