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Commit | Line | Data |
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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
1ec14ad3 CW |
4 | enum { |
5 | RCS = 0x0, | |
6 | VCS, | |
7 | BCS, | |
8 | I915_NUM_RINGS, | |
9 | }; | |
10 | ||
8187a2b7 | 11 | struct intel_hw_status_page { |
78501eac | 12 | u32 __iomem *page_addr; |
8187a2b7 | 13 | unsigned int gfx_addr; |
05394f39 | 14 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
15 | }; |
16 | ||
cae5852d ZN |
17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) |
18 | ||
19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base)) | |
870e86dd | 20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val) |
cae5852d ZN |
21 | |
22 | #define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base)) | |
6c0e1c55 | 23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) |
cae5852d ZN |
24 | |
25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base)) | |
570ef608 | 26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) |
cae5852d ZN |
27 | |
28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base)) | |
7f2ab699 | 29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) |
870e86dd | 30 | |
1ec14ad3 CW |
31 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base)) |
32 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base)) | |
33 | #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base)) | |
34 | ||
8187a2b7 ZN |
35 | struct intel_ring_buffer { |
36 | const char *name; | |
9220434a CW |
37 | enum intel_ring_id { |
38 | RING_RENDER = 0x1, | |
39 | RING_BSD = 0x2, | |
549f7365 | 40 | RING_BLT = 0x4, |
9220434a | 41 | } id; |
333e9fe9 | 42 | u32 mmio_base; |
8187a2b7 ZN |
43 | void *virtual_start; |
44 | struct drm_device *dev; | |
05394f39 | 45 | struct drm_i915_gem_object *obj; |
8187a2b7 | 46 | |
8c0a6bfe CW |
47 | u32 actual_head; |
48 | u32 head; | |
49 | u32 tail; | |
780f0ca3 | 50 | int space; |
c2c347a9 | 51 | int size; |
8187a2b7 ZN |
52 | struct intel_hw_status_page status_page; |
53 | ||
b2223497 CW |
54 | u32 irq_seqno; /* last seq seem at irq time */ |
55 | u32 waiting_seqno; | |
1ec14ad3 | 56 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 CW |
57 | atomic_t irq_refcount; |
58 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); | |
1ec14ad3 | 59 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 60 | |
78501eac | 61 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 62 | |
78501eac | 63 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 64 | u32 value); |
78501eac CW |
65 | void (*flush)(struct intel_ring_buffer *ring, |
66 | u32 invalidate_domains, | |
67 | u32 flush_domains); | |
3cce469c CW |
68 | int (*add_request)(struct intel_ring_buffer *ring, |
69 | u32 *seqno); | |
78501eac CW |
70 | u32 (*get_seqno)(struct intel_ring_buffer *ring); |
71 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, | |
c4e7a414 | 72 | u32 offset, u32 length); |
8d19215b | 73 | void (*cleanup)(struct intel_ring_buffer *ring); |
8187a2b7 ZN |
74 | |
75 | /** | |
76 | * List of objects currently involved in rendering from the | |
77 | * ringbuffer. | |
78 | * | |
79 | * Includes buffers having the contents of their GPU caches | |
80 | * flushed, not necessarily primitives. last_rendering_seqno | |
81 | * represents when the rendering involved will be completed. | |
82 | * | |
83 | * A reference is held on the buffer while on this list. | |
84 | */ | |
85 | struct list_head active_list; | |
86 | ||
87 | /** | |
88 | * List of breadcrumbs associated with GPU requests currently | |
89 | * outstanding. | |
90 | */ | |
91 | struct list_head request_list; | |
92 | ||
64193406 CW |
93 | /** |
94 | * List of objects currently pending a GPU write flush. | |
95 | * | |
96 | * All elements on this list will belong to either the | |
97 | * active_list or flushing_list, last_rendering_seqno can | |
98 | * be used to differentiate between the two elements. | |
99 | */ | |
100 | struct list_head gpu_write_list; | |
101 | ||
a56ba56c CW |
102 | /** |
103 | * Do we have some not yet emitted requests outstanding? | |
104 | */ | |
5d97eb69 | 105 | u32 outstanding_lazy_request; |
a56ba56c | 106 | |
8187a2b7 ZN |
107 | wait_queue_head_t irq_queue; |
108 | drm_local_map_t map; | |
8d19215b ZN |
109 | |
110 | void *private; | |
8187a2b7 ZN |
111 | }; |
112 | ||
1ec14ad3 CW |
113 | static inline u32 |
114 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
115 | struct intel_ring_buffer *other) | |
116 | { | |
117 | int idx; | |
118 | ||
119 | /* | |
120 | * cs -> 0 = vcs, 1 = bcs | |
121 | * vcs -> 0 = bcs, 1 = cs, | |
122 | * bcs -> 0 = cs, 1 = vcs. | |
123 | */ | |
124 | ||
125 | idx = (other - ring) - 1; | |
126 | if (idx < 0) | |
127 | idx += I915_NUM_RINGS; | |
128 | ||
129 | return idx; | |
130 | } | |
131 | ||
8187a2b7 ZN |
132 | static inline u32 |
133 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 134 | int reg) |
8187a2b7 | 135 | { |
78501eac | 136 | return ioread32(ring->status_page.page_addr + reg); |
8187a2b7 ZN |
137 | } |
138 | ||
78501eac | 139 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
e1f99ce6 CW |
140 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
141 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); | |
78501eac CW |
142 | |
143 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, | |
144 | u32 data) | |
e898cd22 | 145 | { |
78501eac | 146 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
147 | ring->tail += 4; |
148 | } | |
149 | ||
78501eac | 150 | void intel_ring_advance(struct intel_ring_buffer *ring); |
8187a2b7 | 151 | |
78501eac | 152 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
1ec14ad3 CW |
153 | int intel_ring_sync(struct intel_ring_buffer *ring, |
154 | struct intel_ring_buffer *to, | |
155 | u32 seqno); | |
8187a2b7 | 156 | |
5c1143bb XH |
157 | int intel_init_render_ring_buffer(struct drm_device *dev); |
158 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 159 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
8187a2b7 | 160 | |
78501eac CW |
161 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
162 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 163 | |
8187a2b7 | 164 | #endif /* _INTEL_RINGBUFFER_H_ */ |