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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
44e895a8 BV |
4 | #include <linux/hashtable.h> |
5 | ||
6 | #define I915_CMD_HASH_ORDER 9 | |
7 | ||
633cf8f5 VS |
8 | /* |
9 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
10 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
11 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
12 | * | |
13 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
14 | * cacheline, the Head Pointer must not be greater than the Tail | |
15 | * Pointer." | |
16 | */ | |
17 | #define I915_RING_FREE_SPACE 64 | |
18 | ||
8187a2b7 | 19 | struct intel_hw_status_page { |
4225d0f2 | 20 | u32 *page_addr; |
8187a2b7 | 21 | unsigned int gfx_addr; |
05394f39 | 22 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
23 | }; |
24 | ||
b7287d80 BW |
25 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
26 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 27 | |
b7287d80 BW |
28 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
29 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 30 | |
b7287d80 BW |
31 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
32 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 33 | |
b7287d80 BW |
34 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
35 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 36 | |
b7287d80 BW |
37 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
38 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 39 | |
e9fea574 | 40 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
9991ae78 | 41 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) |
e9fea574 | 42 | |
3e78998a BW |
43 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
44 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. | |
45 | */ | |
46 | #define i915_semaphore_seqno_size sizeof(uint64_t) | |
47 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ | |
48 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
49 | ((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ | |
50 | (i915_semaphore_seqno_size * (to))) | |
51 | ||
52 | #define GEN8_WAIT_OFFSET(__ring, from) \ | |
53 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ | |
54 | ((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \ | |
55 | (i915_semaphore_seqno_size * (__ring)->id)) | |
56 | ||
57 | #define GEN8_RING_SEMAPHORE_INIT do { \ | |
58 | if (!dev_priv->semaphore_obj) { \ | |
59 | break; \ | |
60 | } \ | |
61 | ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \ | |
62 | ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \ | |
63 | ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \ | |
64 | ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \ | |
65 | ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \ | |
66 | ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \ | |
67 | } while(0) | |
68 | ||
f2f4d82f | 69 | enum intel_ring_hangcheck_action { |
da661464 | 70 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
71 | HANGCHECK_WAIT, |
72 | HANGCHECK_ACTIVE, | |
f260fe7b | 73 | HANGCHECK_ACTIVE_LOOP, |
f2f4d82f JN |
74 | HANGCHECK_KICK, |
75 | HANGCHECK_HUNG, | |
76 | }; | |
ad8beaea | 77 | |
b6b0fac0 MK |
78 | #define HANGCHECK_SCORE_RING_HUNG 31 |
79 | ||
92cab734 | 80 | struct intel_ring_hangcheck { |
50877445 | 81 | u64 acthd; |
f260fe7b | 82 | u64 max_acthd; |
92cab734 | 83 | u32 seqno; |
05407ff8 | 84 | int score; |
ad8beaea | 85 | enum intel_ring_hangcheck_action action; |
4be17381 | 86 | int deadlock; |
92cab734 MK |
87 | }; |
88 | ||
8ee14975 OM |
89 | struct intel_ringbuffer { |
90 | struct drm_i915_gem_object *obj; | |
91 | void __iomem *virtual_start; | |
92 | ||
0c7dd53b DV |
93 | struct intel_engine_cs *ring; |
94 | ||
8ee14975 OM |
95 | u32 head; |
96 | u32 tail; | |
97 | int space; | |
98 | int size; | |
99 | int effective_size; | |
100 | ||
101 | /** We track the position of the requests in the ring buffer, and | |
102 | * when each is retired we increment last_retired_head as the GPU | |
103 | * must have finished processing the request and so we know we | |
104 | * can advance the ringbuffer up to that position. | |
105 | * | |
106 | * last_retired_head is set to -1 after the value is consumed so | |
107 | * we can detect new retirements. | |
108 | */ | |
109 | u32 last_retired_head; | |
110 | }; | |
111 | ||
a4872ba6 | 112 | struct intel_engine_cs { |
8187a2b7 | 113 | const char *name; |
9220434a | 114 | enum intel_ring_id { |
96154f2f DV |
115 | RCS = 0x0, |
116 | VCS, | |
117 | BCS, | |
4a3dd19d | 118 | VECS, |
845f74a7 | 119 | VCS2 |
9220434a | 120 | } id; |
845f74a7 | 121 | #define I915_NUM_RINGS 5 |
b1a93306 | 122 | #define LAST_USER_RING (VECS + 1) |
333e9fe9 | 123 | u32 mmio_base; |
8187a2b7 | 124 | struct drm_device *dev; |
8ee14975 | 125 | struct intel_ringbuffer *buffer; |
8187a2b7 | 126 | |
8187a2b7 ZN |
127 | struct intel_hw_status_page status_page; |
128 | ||
c7113cc3 | 129 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 130 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 131 | u32 trace_irq_seqno; |
a4872ba6 OM |
132 | bool __must_check (*irq_get)(struct intel_engine_cs *ring); |
133 | void (*irq_put)(struct intel_engine_cs *ring); | |
8187a2b7 | 134 | |
a4872ba6 | 135 | int (*init)(struct intel_engine_cs *ring); |
8187a2b7 | 136 | |
a4872ba6 | 137 | void (*write_tail)(struct intel_engine_cs *ring, |
297b0c5b | 138 | u32 value); |
a4872ba6 | 139 | int __must_check (*flush)(struct intel_engine_cs *ring, |
b72f3acb CW |
140 | u32 invalidate_domains, |
141 | u32 flush_domains); | |
a4872ba6 | 142 | int (*add_request)(struct intel_engine_cs *ring); |
b2eadbc8 CW |
143 | /* Some chipsets are not quite as coherent as advertised and need |
144 | * an expensive kick to force a true read of the up-to-date seqno. | |
145 | * However, the up-to-date seqno is not always required and the last | |
146 | * seen value is good enough. Note that the seqno will always be | |
147 | * monotonic, even if not coherent. | |
148 | */ | |
a4872ba6 | 149 | u32 (*get_seqno)(struct intel_engine_cs *ring, |
b2eadbc8 | 150 | bool lazy_coherency); |
a4872ba6 | 151 | void (*set_seqno)(struct intel_engine_cs *ring, |
b70ec5bf | 152 | u32 seqno); |
a4872ba6 | 153 | int (*dispatch_execbuffer)(struct intel_engine_cs *ring, |
9bcb144c | 154 | u64 offset, u32 length, |
d7d4eedd CW |
155 | unsigned flags); |
156 | #define I915_DISPATCH_SECURE 0x1 | |
b45305fc | 157 | #define I915_DISPATCH_PINNED 0x2 |
a4872ba6 | 158 | void (*cleanup)(struct intel_engine_cs *ring); |
ebc348b2 | 159 | |
3e78998a BW |
160 | /* GEN8 signal/wait table - never trust comments! |
161 | * signal to signal to signal to signal to signal to | |
162 | * RCS VCS BCS VECS VCS2 | |
163 | * -------------------------------------------------------------------- | |
164 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | | |
165 | * |------------------------------------------------------------------- | |
166 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | | |
167 | * |------------------------------------------------------------------- | |
168 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | | |
169 | * |------------------------------------------------------------------- | |
170 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | | |
171 | * |------------------------------------------------------------------- | |
172 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | | |
173 | * |------------------------------------------------------------------- | |
174 | * | |
175 | * Generalization: | |
176 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) | |
177 | * ie. transpose of g(x, y) | |
178 | * | |
179 | * sync from sync from sync from sync from sync from | |
180 | * RCS VCS BCS VECS VCS2 | |
181 | * -------------------------------------------------------------------- | |
182 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | | |
183 | * |------------------------------------------------------------------- | |
184 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | | |
185 | * |------------------------------------------------------------------- | |
186 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | | |
187 | * |------------------------------------------------------------------- | |
188 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | | |
189 | * |------------------------------------------------------------------- | |
190 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | | |
191 | * |------------------------------------------------------------------- | |
192 | * | |
193 | * Generalization: | |
194 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) | |
195 | * ie. transpose of f(x, y) | |
196 | */ | |
ebc348b2 BW |
197 | struct { |
198 | u32 sync_seqno[I915_NUM_RINGS-1]; | |
78325f2d | 199 | |
3e78998a BW |
200 | union { |
201 | struct { | |
202 | /* our mbox written by others */ | |
203 | u32 wait[I915_NUM_RINGS]; | |
204 | /* mboxes this ring signals to */ | |
205 | u32 signal[I915_NUM_RINGS]; | |
206 | } mbox; | |
207 | u64 signal_ggtt[I915_NUM_RINGS]; | |
208 | }; | |
78325f2d BW |
209 | |
210 | /* AKA wait() */ | |
a4872ba6 OM |
211 | int (*sync_to)(struct intel_engine_cs *ring, |
212 | struct intel_engine_cs *to, | |
78325f2d | 213 | u32 seqno); |
a4872ba6 | 214 | int (*signal)(struct intel_engine_cs *signaller, |
024a43e1 BW |
215 | /* num_dwords needed by caller */ |
216 | unsigned int num_dwords); | |
ebc348b2 | 217 | } semaphore; |
ad776f8b | 218 | |
8187a2b7 ZN |
219 | /** |
220 | * List of objects currently involved in rendering from the | |
221 | * ringbuffer. | |
222 | * | |
223 | * Includes buffers having the contents of their GPU caches | |
224 | * flushed, not necessarily primitives. last_rendering_seqno | |
225 | * represents when the rendering involved will be completed. | |
226 | * | |
227 | * A reference is held on the buffer while on this list. | |
228 | */ | |
229 | struct list_head active_list; | |
230 | ||
231 | /** | |
232 | * List of breadcrumbs associated with GPU requests currently | |
233 | * outstanding. | |
234 | */ | |
235 | struct list_head request_list; | |
236 | ||
a56ba56c CW |
237 | /** |
238 | * Do we have some not yet emitted requests outstanding? | |
239 | */ | |
3c0e234c | 240 | struct drm_i915_gem_request *preallocated_lazy_request; |
1823521d | 241 | u32 outstanding_lazy_seqno; |
cc889e0f | 242 | bool gpu_caches_dirty; |
c65355bb | 243 | bool fbc_dirty; |
a56ba56c | 244 | |
8187a2b7 | 245 | wait_queue_head_t irq_queue; |
8d19215b | 246 | |
273497e5 OM |
247 | struct intel_context *default_context; |
248 | struct intel_context *last_context; | |
40521054 | 249 | |
92cab734 MK |
250 | struct intel_ring_hangcheck hangcheck; |
251 | ||
0d1aacac CW |
252 | struct { |
253 | struct drm_i915_gem_object *obj; | |
254 | u32 gtt_offset; | |
255 | volatile u32 *cpu_page; | |
256 | } scratch; | |
351e3db2 | 257 | |
44e895a8 BV |
258 | bool needs_cmd_parser; |
259 | ||
351e3db2 | 260 | /* |
44e895a8 | 261 | * Table of commands the command parser needs to know about |
351e3db2 BV |
262 | * for this ring. |
263 | */ | |
44e895a8 | 264 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
265 | |
266 | /* | |
267 | * Table of registers allowed in commands that read/write registers. | |
268 | */ | |
269 | const u32 *reg_table; | |
270 | int reg_count; | |
271 | ||
272 | /* | |
273 | * Table of registers allowed in commands that read/write registers, but | |
274 | * only from the DRM master. | |
275 | */ | |
276 | const u32 *master_reg_table; | |
277 | int master_reg_count; | |
278 | ||
279 | /* | |
280 | * Returns the bitmask for the length field of the specified command. | |
281 | * Return 0 for an unrecognized/invalid command. | |
282 | * | |
283 | * If the command parser finds an entry for a command in the ring's | |
284 | * cmd_tables, it gets the command's length based on the table entry. | |
285 | * If not, it calls this function to determine the per-ring length field | |
286 | * encoding for the command (i.e. certain opcode ranges use certain bits | |
287 | * to encode the command length in the header). | |
288 | */ | |
289 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
290 | }; |
291 | ||
b4519513 | 292 | static inline bool |
a4872ba6 | 293 | intel_ring_initialized(struct intel_engine_cs *ring) |
b4519513 | 294 | { |
ee1b1e5e | 295 | return ring->buffer && ring->buffer->obj; |
b4519513 CW |
296 | } |
297 | ||
96154f2f | 298 | static inline unsigned |
a4872ba6 | 299 | intel_ring_flag(struct intel_engine_cs *ring) |
96154f2f DV |
300 | { |
301 | return 1 << ring->id; | |
302 | } | |
303 | ||
1ec14ad3 | 304 | static inline u32 |
a4872ba6 OM |
305 | intel_ring_sync_index(struct intel_engine_cs *ring, |
306 | struct intel_engine_cs *other) | |
1ec14ad3 CW |
307 | { |
308 | int idx; | |
309 | ||
310 | /* | |
ddd4dbc6 RV |
311 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
312 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; | |
313 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; | |
314 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; | |
315 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; | |
1ec14ad3 CW |
316 | */ |
317 | ||
318 | idx = (other - ring) - 1; | |
319 | if (idx < 0) | |
320 | idx += I915_NUM_RINGS; | |
321 | ||
322 | return idx; | |
323 | } | |
324 | ||
8187a2b7 | 325 | static inline u32 |
a4872ba6 | 326 | intel_read_status_page(struct intel_engine_cs *ring, |
78501eac | 327 | int reg) |
8187a2b7 | 328 | { |
4225d0f2 DV |
329 | /* Ensure that the compiler doesn't optimize away the load. */ |
330 | barrier(); | |
331 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
332 | } |
333 | ||
b70ec5bf | 334 | static inline void |
a4872ba6 | 335 | intel_write_status_page(struct intel_engine_cs *ring, |
b70ec5bf MK |
336 | int reg, u32 value) |
337 | { | |
338 | ring->status_page.page_addr[reg] = value; | |
339 | } | |
340 | ||
311bd68e CW |
341 | /** |
342 | * Reads a dword out of the status page, which is written to from the command | |
343 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
344 | * MI_STORE_DATA_IMM. | |
345 | * | |
346 | * The following dwords have a reserved meaning: | |
347 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
348 | * 0x04: ring 0 head pointer | |
349 | * 0x05: ring 1 head pointer (915-class) | |
350 | * 0x06: ring 2 head pointer (915-class) | |
351 | * 0x10-0x1b: Context status DWords (GM45) | |
352 | * 0x1f: Last written status offset. (GM45) | |
353 | * | |
354 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
355 | */ | |
311bd68e | 356 | #define I915_GEM_HWS_INDEX 0x20 |
9a289771 JB |
357 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
358 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) | |
311bd68e | 359 | |
84c2377f OM |
360 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf); |
361 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, | |
362 | struct intel_ringbuffer *ringbuf); | |
363 | ||
a4872ba6 OM |
364 | void intel_stop_ring_buffer(struct intel_engine_cs *ring); |
365 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring); | |
96f298aa | 366 | |
a4872ba6 OM |
367 | int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n); |
368 | int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring); | |
369 | static inline void intel_ring_emit(struct intel_engine_cs *ring, | |
78501eac | 370 | u32 data) |
e898cd22 | 371 | { |
93b0a4e0 OM |
372 | struct intel_ringbuffer *ringbuf = ring->buffer; |
373 | iowrite32(data, ringbuf->virtual_start + ringbuf->tail); | |
374 | ringbuf->tail += 4; | |
e898cd22 | 375 | } |
a4872ba6 | 376 | static inline void intel_ring_advance(struct intel_engine_cs *ring) |
09246732 | 377 | { |
93b0a4e0 OM |
378 | struct intel_ringbuffer *ringbuf = ring->buffer; |
379 | ringbuf->tail &= ringbuf->size - 1; | |
09246732 | 380 | } |
a4872ba6 | 381 | void __intel_ring_advance(struct intel_engine_cs *ring); |
09246732 | 382 | |
a4872ba6 OM |
383 | int __must_check intel_ring_idle(struct intel_engine_cs *ring); |
384 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno); | |
385 | int intel_ring_flush_all_caches(struct intel_engine_cs *ring); | |
386 | int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring); | |
8187a2b7 | 387 | |
5c1143bb XH |
388 | int intel_init_render_ring_buffer(struct drm_device *dev); |
389 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
845f74a7 | 390 | int intel_init_bsd2_ring_buffer(struct drm_device *dev); |
549f7365 | 391 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 392 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 393 | |
a4872ba6 OM |
394 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring); |
395 | void intel_ring_setup_status_page(struct intel_engine_cs *ring); | |
79f321b7 | 396 | |
1b5d063f | 397 | static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) |
a71d8d94 | 398 | { |
1b5d063f | 399 | return ringbuf->tail; |
a71d8d94 CW |
400 | } |
401 | ||
a4872ba6 | 402 | static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring) |
9d773091 | 403 | { |
1823521d CW |
404 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
405 | return ring->outstanding_lazy_seqno; | |
9d773091 CW |
406 | } |
407 | ||
a4872ba6 | 408 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno) |
db53a302 CW |
409 | { |
410 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
411 | ring->trace_irq_seqno = seqno; | |
412 | } | |
413 | ||
e8616b6c CW |
414 | /* DRI warts */ |
415 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
416 | ||
8187a2b7 | 417 | #endif /* _INTEL_RINGBUFFER_H_ */ |