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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
4 | struct intel_hw_status_page { | |
78501eac | 5 | u32 __iomem *page_addr; |
8187a2b7 | 6 | unsigned int gfx_addr; |
05394f39 | 7 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
8 | }; |
9 | ||
b7287d80 BW |
10 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
11 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 12 | |
b7287d80 BW |
13 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
14 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 15 | |
b7287d80 BW |
16 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
17 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 18 | |
b7287d80 BW |
19 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
20 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 21 | |
b7287d80 BW |
22 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
23 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 24 | |
b7287d80 BW |
25 | #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) |
26 | #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) | |
27 | #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) | |
1ec14ad3 | 28 | |
8187a2b7 ZN |
29 | struct intel_ring_buffer { |
30 | const char *name; | |
9220434a | 31 | enum intel_ring_id { |
96154f2f DV |
32 | RCS = 0x0, |
33 | VCS, | |
34 | BCS, | |
9220434a | 35 | } id; |
96154f2f | 36 | #define I915_NUM_RINGS 3 |
333e9fe9 | 37 | u32 mmio_base; |
311bd68e | 38 | void __iomem *virtual_start; |
8187a2b7 | 39 | struct drm_device *dev; |
05394f39 | 40 | struct drm_i915_gem_object *obj; |
8187a2b7 | 41 | |
8c0a6bfe CW |
42 | u32 head; |
43 | u32 tail; | |
780f0ca3 | 44 | int space; |
c2c347a9 | 45 | int size; |
55249baa | 46 | int effective_size; |
8187a2b7 ZN |
47 | struct intel_hw_status_page status_page; |
48 | ||
0dc79fb2 | 49 | spinlock_t irq_lock; |
01a03331 | 50 | u32 irq_refcount; |
0f46832f | 51 | u32 irq_mask; |
b2223497 | 52 | u32 irq_seqno; /* last seq seem at irq time */ |
db53a302 | 53 | u32 trace_irq_seqno; |
b2223497 | 54 | u32 waiting_seqno; |
1ec14ad3 | 55 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 56 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 57 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 58 | |
78501eac | 59 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 60 | |
78501eac | 61 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 62 | u32 value); |
b72f3acb CW |
63 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
64 | u32 invalidate_domains, | |
65 | u32 flush_domains); | |
3cce469c CW |
66 | int (*add_request)(struct intel_ring_buffer *ring, |
67 | u32 *seqno); | |
78501eac CW |
68 | u32 (*get_seqno)(struct intel_ring_buffer *ring); |
69 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, | |
c4e7a414 | 70 | u32 offset, u32 length); |
8d19215b | 71 | void (*cleanup)(struct intel_ring_buffer *ring); |
c8c99b0f BW |
72 | int (*sync_to)(struct intel_ring_buffer *ring, |
73 | struct intel_ring_buffer *to, | |
74 | u32 seqno); | |
8187a2b7 | 75 | |
c8c99b0f BW |
76 | u32 semaphore_register[3]; /*our mbox written by others */ |
77 | u32 signal_mbox[2]; /* mboxes this ring signals to */ | |
8187a2b7 ZN |
78 | /** |
79 | * List of objects currently involved in rendering from the | |
80 | * ringbuffer. | |
81 | * | |
82 | * Includes buffers having the contents of their GPU caches | |
83 | * flushed, not necessarily primitives. last_rendering_seqno | |
84 | * represents when the rendering involved will be completed. | |
85 | * | |
86 | * A reference is held on the buffer while on this list. | |
87 | */ | |
88 | struct list_head active_list; | |
89 | ||
90 | /** | |
91 | * List of breadcrumbs associated with GPU requests currently | |
92 | * outstanding. | |
93 | */ | |
94 | struct list_head request_list; | |
95 | ||
64193406 CW |
96 | /** |
97 | * List of objects currently pending a GPU write flush. | |
98 | * | |
99 | * All elements on this list will belong to either the | |
100 | * active_list or flushing_list, last_rendering_seqno can | |
101 | * be used to differentiate between the two elements. | |
102 | */ | |
103 | struct list_head gpu_write_list; | |
104 | ||
a56ba56c CW |
105 | /** |
106 | * Do we have some not yet emitted requests outstanding? | |
107 | */ | |
5d97eb69 | 108 | u32 outstanding_lazy_request; |
a56ba56c | 109 | |
8187a2b7 ZN |
110 | wait_queue_head_t irq_queue; |
111 | drm_local_map_t map; | |
8d19215b ZN |
112 | |
113 | void *private; | |
8187a2b7 ZN |
114 | }; |
115 | ||
96154f2f DV |
116 | static inline unsigned |
117 | intel_ring_flag(struct intel_ring_buffer *ring) | |
118 | { | |
119 | return 1 << ring->id; | |
120 | } | |
121 | ||
1ec14ad3 CW |
122 | static inline u32 |
123 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
124 | struct intel_ring_buffer *other) | |
125 | { | |
126 | int idx; | |
127 | ||
128 | /* | |
129 | * cs -> 0 = vcs, 1 = bcs | |
130 | * vcs -> 0 = bcs, 1 = cs, | |
131 | * bcs -> 0 = cs, 1 = vcs. | |
132 | */ | |
133 | ||
134 | idx = (other - ring) - 1; | |
135 | if (idx < 0) | |
136 | idx += I915_NUM_RINGS; | |
137 | ||
138 | return idx; | |
139 | } | |
140 | ||
8187a2b7 ZN |
141 | static inline u32 |
142 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 143 | int reg) |
8187a2b7 | 144 | { |
78501eac | 145 | return ioread32(ring->status_page.page_addr + reg); |
8187a2b7 ZN |
146 | } |
147 | ||
311bd68e CW |
148 | /** |
149 | * Reads a dword out of the status page, which is written to from the command | |
150 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
151 | * MI_STORE_DATA_IMM. | |
152 | * | |
153 | * The following dwords have a reserved meaning: | |
154 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
155 | * 0x04: ring 0 head pointer | |
156 | * 0x05: ring 1 head pointer (915-class) | |
157 | * 0x06: ring 2 head pointer (915-class) | |
158 | * 0x10-0x1b: Context status DWords (GM45) | |
159 | * 0x1f: Last written status offset. (GM45) | |
160 | * | |
161 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
162 | */ | |
163 | #define READ_HWSP(dev_priv, reg) intel_read_status_page(LP_RING(dev_priv), reg) | |
164 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) | |
165 | #define I915_GEM_HWS_INDEX 0x20 | |
166 | #define I915_BREADCRUMB_INDEX 0x21 | |
167 | ||
78501eac | 168 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 169 | |
e1f99ce6 | 170 | int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
96f298aa BW |
171 | static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) |
172 | { | |
a94919ea | 173 | return intel_wait_ring_buffer(ring, ring->size - 8); |
96f298aa BW |
174 | } |
175 | ||
e1f99ce6 | 176 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
78501eac CW |
177 | |
178 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, | |
179 | u32 data) | |
e898cd22 | 180 | { |
78501eac | 181 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
182 | ring->tail += 4; |
183 | } | |
184 | ||
78501eac | 185 | void intel_ring_advance(struct intel_ring_buffer *ring); |
8187a2b7 | 186 | |
78501eac | 187 | u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
8187a2b7 | 188 | |
5c1143bb XH |
189 | int intel_init_render_ring_buffer(struct drm_device *dev); |
190 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 191 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
8187a2b7 | 192 | |
78501eac CW |
193 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
194 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 195 | |
db53a302 CW |
196 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
197 | { | |
198 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
199 | ring->trace_irq_seqno = seqno; | |
200 | } | |
201 | ||
e8616b6c CW |
202 | /* DRI warts */ |
203 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
204 | ||
8187a2b7 | 205 | #endif /* _INTEL_RINGBUFFER_H_ */ |