[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.h

#ifndef _INTEL_RINGBUFFER_H_
#define _INTEL_RINGBUFFER_H_

#include <linux/hashtable.h>

#define I915_CMD_HASH_ORDER 9

/*
 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
 *
 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
 * cacheline, the Head Pointer must not be greater than the Tail
 * Pointer."
 */
#define I915_RING_FREE_SPACE 64

struct  intel_hw_status_page {
	u32		*page_addr;
	unsigned int	gfx_addr;
	struct		drm_i915_gem_object *obj;
};

#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)

#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)

#define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)

#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)

#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)

#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)

enum intel_ring_hangcheck_action {
	HANGCHECK_IDLE = 0,
	HANGCHECK_WAIT,
	HANGCHECK_ACTIVE,
	HANGCHECK_KICK,
	HANGCHECK_HUNG,
};

#define HANGCHECK_SCORE_RING_HUNG 31

struct intel_ring_hangcheck {
	u64 acthd;
	u32 seqno;
	int score;
	enum intel_ring_hangcheck_action action;
	bool deadlock;
};

struct  intel_engine_cs {
	const char	*name;
	enum intel_ring_id {
		RCS = 0x0,
		VCS,
		BCS,
		VECS,
		VCS2
	} id;
#define I915_NUM_RINGS 5
#define LAST_USER_RING (VECS + 1)
	u32		mmio_base;
	void		__iomem *virtual_start;
	struct		drm_device *dev;
	struct		drm_i915_gem_object *obj;

	u32		head;
	u32		tail;
	int		space;
	int		size;
	int		effective_size;
	struct intel_hw_status_page status_page;

	/** We track the position of the requests in the ring buffer, and
	 * when each is retired we increment last_retired_head as the GPU
	 * must have finished processing the request and so we know we
	 * can advance the ringbuffer up to that position.
	 *
	 * last_retired_head is set to -1 after the value is consumed so
	 * we can detect new retirements.
	 */
	u32		last_retired_head;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */
	u32		trace_irq_seqno;
	bool __must_check (*irq_get)(struct intel_engine_cs *ring);
	void		(*irq_put)(struct intel_engine_cs *ring);

	int		(*init)(struct intel_engine_cs *ring);

	void		(*write_tail)(struct intel_engine_cs *ring,
				      u32 value);
	int __must_check (*flush)(struct intel_engine_cs *ring,
				  u32	invalidate_domains,
				  u32	flush_domains);
	int		(*add_request)(struct intel_engine_cs *ring);
	/* Some chipsets are not quite as coherent as advertised and need
	 * an expensive kick to force a true read of the up-to-date seqno.
	 * However, the up-to-date seqno is not always required and the last
	 * seen value is good enough. Note that the seqno will always be
	 * monotonic, even if not coherent.
	 */
	u32		(*get_seqno)(struct intel_engine_cs *ring,
				     bool lazy_coherency);
	void		(*set_seqno)(struct intel_engine_cs *ring,
				     u32 seqno);
	int		(*dispatch_execbuffer)(struct intel_engine_cs *ring,
					       u64 offset, u32 length,
					       unsigned flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
	void		(*cleanup)(struct intel_engine_cs *ring);

	struct {
		u32	sync_seqno[I915_NUM_RINGS-1];

		struct {
			/* our mbox written by others */
			u32		wait[I915_NUM_RINGS];
			/* mboxes this ring signals to */
			u32		signal[I915_NUM_RINGS];
		} mbox;

		/* AKA wait() */
		int	(*sync_to)(struct intel_engine_cs *ring,
				   struct intel_engine_cs *to,
				   u32 seqno);
		int	(*signal)(struct intel_engine_cs *signaller,
				  /* num_dwords needed by caller */
				  unsigned int num_dwords);
	} semaphore;

	/**
	 * List of objects currently involved in rendering from the
	 * ringbuffer.
	 *
	 * Includes buffers having the contents of their GPU caches
	 * flushed, not necessarily primitives.  last_rendering_seqno
	 * represents when the rendering involved will be completed.
	 *
	 * A reference is held on the buffer while on this list.
	 */
	struct list_head active_list;

	/**
	 * List of breadcrumbs associated with GPU requests currently
	 * outstanding.
	 */
	struct list_head request_list;

	/**
	 * Do we have some not yet emitted requests outstanding?
	 */
	struct drm_i915_gem_request *preallocated_lazy_request;
	u32 outstanding_lazy_seqno;
	bool gpu_caches_dirty;
	bool fbc_dirty;

	wait_queue_head_t irq_queue;

	struct i915_hw_context *default_context;
	struct i915_hw_context *last_context;

	struct intel_ring_hangcheck hangcheck;

	struct {
		struct drm_i915_gem_object *obj;
		u32 gtt_offset;
		volatile u32 *cpu_page;
	} scratch;

	bool needs_cmd_parser;

	/*
	 * Table of commands the command parser needs to know about
	 * for this ring.
	 */
	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);

	/*
	 * Table of registers allowed in commands that read/write registers.
	 */
	const u32 *reg_table;
	int reg_count;

	/*
	 * Table of registers allowed in commands that read/write registers, but
	 * only from the DRM master.
	 */
	const u32 *master_reg_table;
	int master_reg_count;

	/*
	 * Returns the bitmask for the length field of the specified command.
	 * Return 0 for an unrecognized/invalid command.
	 *
	 * If the command parser finds an entry for a command in the ring's
	 * cmd_tables, it gets the command's length based on the table entry.
	 * If not, it calls this function to determine the per-ring length field
	 * encoding for the command (i.e. certain opcode ranges use certain bits
	 * to encode the command length in the header).
	 */
	u32 (*get_cmd_length_mask)(u32 cmd_header);
};

static inline bool
intel_ring_initialized(struct intel_engine_cs *ring)
{
	return ring->obj != NULL;
}

static inline unsigned
intel_ring_flag(struct intel_engine_cs *ring)
{
	return 1 << ring->id;
}

static inline u32
intel_ring_sync_index(struct intel_engine_cs *ring,
		      struct intel_engine_cs *other)
{
	int idx;

	/*
	 * cs -> 0 = vcs, 1 = bcs
	 * vcs -> 0 = bcs, 1 = cs,
	 * bcs -> 0 = cs, 1 = vcs.
	 */

	idx = (other - ring) - 1;
	if (idx < 0)
		idx += I915_NUM_RINGS;

	return idx;
}

static inline u32
intel_read_status_page(struct intel_engine_cs *ring,
		       int reg)
{
	/* Ensure that the compiler doesn't optimize away the load. */
	barrier();
	return ring->status_page.page_addr[reg];
}

static inline void
intel_write_status_page(struct intel_engine_cs *ring,
			int reg, u32 value)
{
	ring->status_page.page_addr[reg] = value;
}

/**
 * Reads a dword out of the status page, which is written to from the command
 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 * MI_STORE_DATA_IMM.
 *
 * The following dwords have a reserved meaning:
 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 * 0x04: ring 0 head pointer
 * 0x05: ring 1 head pointer (915-class)
 * 0x06: ring 2 head pointer (915-class)
 * 0x10-0x1b: Context status DWords (GM45)
 * 0x1f: Last written status offset. (GM45)
 *
 * The area from dword 0x20 to 0x3ff is available for driver usage.
 */
#define I915_GEM_HWS_INDEX		0x20
#define I915_GEM_HWS_SCRATCH_INDEX	0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)

void intel_stop_ring_buffer(struct intel_engine_cs *ring);
void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);

int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
static inline void intel_ring_emit(struct intel_engine_cs *ring,
				   u32 data)
{
	iowrite32(data, ring->virtual_start + ring->tail);
	ring->tail += 4;
}
static inline void intel_ring_advance(struct intel_engine_cs *ring)
{
	ring->tail &= ring->size - 1;
}
void __intel_ring_advance(struct intel_engine_cs *ring);

int __must_check intel_ring_idle(struct intel_engine_cs *ring);
void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);

int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_bsd2_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
int intel_init_vebox_ring_buffer(struct drm_device *dev);

u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
void intel_ring_setup_status_page(struct intel_engine_cs *ring);

static inline u32 intel_ring_get_tail(struct intel_engine_cs *ring)
{
	return ring->tail;
}

static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
{
	BUG_ON(ring->outstanding_lazy_seqno == 0);
	return ring->outstanding_lazy_seqno;
}

static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
{
	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
		ring->trace_irq_seqno = seqno;
}

/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);

#endif /* _INTEL_RINGBUFFER_H_ */
Commit	Line	Data
8187a2b7 ZN	1	#ifndef _INTEL_RINGBUFFER_H_
	2	#define _INTEL_RINGBUFFER_H_
	3
44e895a8 BV	4	#include <linux/hashtable.h>
	5
	6	#define I915_CMD_HASH_ORDER 9
	7
633cf8f5 VS	8	/*
	9	* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
	10	* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
	11	* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
	12	*
	13	* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
	14	* cacheline, the Head Pointer must not be greater than the Tail
	15	* Pointer."
	16	*/
	17	#define I915_RING_FREE_SPACE 64
	18
8187a2b7	19	struct intel_hw_status_page {
4225d0f2	20	u32 *page_addr;
8187a2b7	21	unsigned int gfx_addr;
05394f39	22	struct drm_i915_gem_object *obj;
8187a2b7 ZN	23	};
8187a2b7 ZN	24
b7287d80 BW	25	#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
b7287d80 BW	26	#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
cae5852d	27
b7287d80 BW	28	#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
b7287d80 BW	29	#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
cae5852d	30
b7287d80 BW	31	#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
b7287d80 BW	32	#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
cae5852d	33
b7287d80 BW	34	#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
b7287d80 BW	35	#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
cae5852d	36
b7287d80 BW	37	#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
b7287d80 BW	38	#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
870e86dd	39
e9fea574	40	#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
9991ae78	41	#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
e9fea574	42
f2f4d82f	43	enum intel_ring_hangcheck_action {
da661464	44	HANGCHECK_IDLE = 0,
f2f4d82f JN	45	HANGCHECK_WAIT,
	46	HANGCHECK_ACTIVE,
	47	HANGCHECK_KICK,
	48	HANGCHECK_HUNG,
	49	};
ad8beaea	50
b6b0fac0 MK	51	#define HANGCHECK_SCORE_RING_HUNG 31
b6b0fac0 MK	52
92cab734	53	struct intel_ring_hangcheck {
50877445	54	u64 acthd;
92cab734	55	u32 seqno;
05407ff8	56	int score;
ad8beaea	57	enum intel_ring_hangcheck_action action;
50877445	58	bool deadlock;
92cab734 MK	59	};
92cab734 MK	60
a4872ba6	61	struct intel_engine_cs {
8187a2b7	62	const char *name;
9220434a	63	enum intel_ring_id {
96154f2f DV	64	RCS = 0x0,
	65	VCS,
	66	BCS,
4a3dd19d	67	VECS,
845f74a7	68	VCS2
9220434a	69	} id;
845f74a7	70	#define I915_NUM_RINGS 5
b1a93306	71	#define LAST_USER_RING (VECS + 1)
333e9fe9	72	u32 mmio_base;
311bd68e	73	void __iomem *virtual_start;
8187a2b7	74	struct drm_device *dev;
05394f39	75	struct drm_i915_gem_object *obj;
8187a2b7	76
8c0a6bfe CW	77	u32 head;
8c0a6bfe CW	78	u32 tail;
780f0ca3	79	int space;
c2c347a9	80	int size;
55249baa	81	int effective_size;
8187a2b7 ZN	82	struct intel_hw_status_page status_page;
8187a2b7 ZN	83
a71d8d94 CW	84	/** We track the position of the requests in the ring buffer, and
	85	* when each is retired we increment last_retired_head as the GPU
	86	* must have finished processing the request and so we know we
	87	* can advance the ringbuffer up to that position.
	88	*
	89	* last_retired_head is set to -1 after the value is consumed so
	90	* we can detect new retirements.
	91	*/
	92	u32 last_retired_head;
	93
c7113cc3	94	unsigned irq_refcount; /* protected by dev_priv->irq_lock */
6a848ccb	95	u32 irq_enable_mask; /* bitmask to enable ring interrupt */
db53a302	96	u32 trace_irq_seqno;
a4872ba6 OM	97	bool __must_check (irq_get)(struct intel_engine_cs ring);
a4872ba6 OM	98	void (irq_put)(struct intel_engine_cs ring);
8187a2b7	99
a4872ba6	100	int (init)(struct intel_engine_cs ring);
8187a2b7	101
a4872ba6	102	void (write_tail)(struct intel_engine_cs ring,
297b0c5b	103	u32 value);
a4872ba6	104	int __must_check (flush)(struct intel_engine_cs ring,
b72f3acb CW	105	u32 invalidate_domains,
b72f3acb CW	106	u32 flush_domains);
a4872ba6	107	int (add_request)(struct intel_engine_cs ring);
b2eadbc8 CW	108	/* Some chipsets are not quite as coherent as advertised and need
	109	* an expensive kick to force a true read of the up-to-date seqno.
	110	* However, the up-to-date seqno is not always required and the last
	111	* seen value is good enough. Note that the seqno will always be
	112	* monotonic, even if not coherent.
	113	*/
a4872ba6	114	u32 (get_seqno)(struct intel_engine_cs ring,
b2eadbc8	115	bool lazy_coherency);
a4872ba6	116	void (set_seqno)(struct intel_engine_cs ring,
b70ec5bf	117	u32 seqno);
a4872ba6	118	int (dispatch_execbuffer)(struct intel_engine_cs ring,
9bcb144c	119	u64 offset, u32 length,
d7d4eedd CW	120	unsigned flags);
d7d4eedd CW	121	#define I915_DISPATCH_SECURE 0x1
b45305fc	122	#define I915_DISPATCH_PINNED 0x2
a4872ba6	123	void (cleanup)(struct intel_engine_cs ring);
ebc348b2 BW	124
	125	struct {
	126	u32 sync_seqno[I915_NUM_RINGS-1];
78325f2d	127
ebc348b2 BW	128	struct {
	129	/* our mbox written by others */
	130	u32 wait[I915_NUM_RINGS];
	131	/* mboxes this ring signals to */
	132	u32 signal[I915_NUM_RINGS];
	133	} mbox;
78325f2d BW	134
78325f2d BW	135	/* AKA wait() */
a4872ba6 OM	136	int (sync_to)(struct intel_engine_cs ring,
a4872ba6 OM	137	struct intel_engine_cs *to,
78325f2d	138	u32 seqno);
a4872ba6	139	int (signal)(struct intel_engine_cs signaller,
024a43e1 BW	140	/* num_dwords needed by caller */
024a43e1 BW	141	unsigned int num_dwords);
ebc348b2	142	} semaphore;
ad776f8b	143
8187a2b7 ZN	144	/**
	145	* List of objects currently involved in rendering from the
	146	* ringbuffer.
	147	*
	148	* Includes buffers having the contents of their GPU caches
	149	* flushed, not necessarily primitives. last_rendering_seqno
	150	* represents when the rendering involved will be completed.
	151	*
	152	* A reference is held on the buffer while on this list.
	153	*/
	154	struct list_head active_list;
	155
	156	/**
	157	* List of breadcrumbs associated with GPU requests currently
	158	* outstanding.
	159	*/
	160	struct list_head request_list;
	161
a56ba56c CW	162	/**
	163	* Do we have some not yet emitted requests outstanding?
	164	*/
3c0e234c	165	struct drm_i915_gem_request *preallocated_lazy_request;
1823521d	166	u32 outstanding_lazy_seqno;
cc889e0f	167	bool gpu_caches_dirty;
c65355bb	168	bool fbc_dirty;
a56ba56c	169
8187a2b7	170	wait_queue_head_t irq_queue;
8d19215b	171
40521054	172	struct i915_hw_context *default_context;
112522f6	173	struct i915_hw_context *last_context;
40521054	174
92cab734 MK	175	struct intel_ring_hangcheck hangcheck;
92cab734 MK	176
0d1aacac CW	177	struct {
	178	struct drm_i915_gem_object *obj;
	179	u32 gtt_offset;
	180	volatile u32 *cpu_page;
	181	} scratch;
351e3db2	182
44e895a8 BV	183	bool needs_cmd_parser;
44e895a8 BV	184
351e3db2	185	/*
44e895a8	186	* Table of commands the command parser needs to know about
351e3db2 BV	187	* for this ring.
351e3db2 BV	188	*/
44e895a8	189	DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
351e3db2 BV	190
	191	/*
	192	* Table of registers allowed in commands that read/write registers.
	193	*/
	194	const u32 *reg_table;
	195	int reg_count;
	196
	197	/*
	198	* Table of registers allowed in commands that read/write registers, but
	199	* only from the DRM master.
	200	*/
	201	const u32 *master_reg_table;
	202	int master_reg_count;
	203
	204	/*
	205	* Returns the bitmask for the length field of the specified command.
	206	* Return 0 for an unrecognized/invalid command.
	207	*
	208	* If the command parser finds an entry for a command in the ring's
	209	* cmd_tables, it gets the command's length based on the table entry.
	210	* If not, it calls this function to determine the per-ring length field
	211	* encoding for the command (i.e. certain opcode ranges use certain bits
	212	* to encode the command length in the header).
	213	*/
	214	u32 (*get_cmd_length_mask)(u32 cmd_header);
8187a2b7 ZN	215	};
8187a2b7 ZN	216
b4519513	217	static inline bool
a4872ba6	218	intel_ring_initialized(struct intel_engine_cs *ring)
b4519513 CW	219	{
	220	return ring->obj != NULL;
	221	}
	222
96154f2f	223	static inline unsigned
a4872ba6	224	intel_ring_flag(struct intel_engine_cs *ring)
96154f2f DV	225	{
	226	return 1 << ring->id;
	227	}
	228
1ec14ad3	229	static inline u32
a4872ba6 OM	230	intel_ring_sync_index(struct intel_engine_cs *ring,
a4872ba6 OM	231	struct intel_engine_cs *other)
1ec14ad3 CW	232	{
	233	int idx;
	234
	235	/*
	236	* cs -> 0 = vcs, 1 = bcs
	237	* vcs -> 0 = bcs, 1 = cs,
	238	* bcs -> 0 = cs, 1 = vcs.
	239	*/
	240
	241	idx = (other - ring) - 1;
	242	if (idx < 0)
	243	idx += I915_NUM_RINGS;
	244
	245	return idx;
	246	}
	247
8187a2b7	248	static inline u32
a4872ba6	249	intel_read_status_page(struct intel_engine_cs *ring,
78501eac	250	int reg)
8187a2b7	251	{
4225d0f2 DV	252	/* Ensure that the compiler doesn't optimize away the load. */
	253	barrier();
	254	return ring->status_page.page_addr[reg];
8187a2b7 ZN	255	}
8187a2b7 ZN	256
b70ec5bf	257	static inline void
a4872ba6	258	intel_write_status_page(struct intel_engine_cs *ring,
b70ec5bf MK	259	int reg, u32 value)
	260	{
	261	ring->status_page.page_addr[reg] = value;
	262	}
	263
311bd68e CW	264	/**
	265	* Reads a dword out of the status page, which is written to from the command
	266	* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
	267	* MI_STORE_DATA_IMM.
	268	*
	269	* The following dwords have a reserved meaning:
	270	* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
	271	* 0x04: ring 0 head pointer
	272	* 0x05: ring 1 head pointer (915-class)
	273	* 0x06: ring 2 head pointer (915-class)
	274	* 0x10-0x1b: Context status DWords (GM45)
	275	* 0x1f: Last written status offset. (GM45)
	276	*
	277	* The area from dword 0x20 to 0x3ff is available for driver usage.
	278	*/
311bd68e	279	#define I915_GEM_HWS_INDEX 0x20
9a289771 JB	280	#define I915_GEM_HWS_SCRATCH_INDEX 0x30
9a289771 JB	281	#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
311bd68e	282
a4872ba6 OM	283	void intel_stop_ring_buffer(struct intel_engine_cs *ring);
a4872ba6 OM	284	void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
96f298aa	285
a4872ba6 OM	286	int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
	287	int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
	288	static inline void intel_ring_emit(struct intel_engine_cs *ring,
78501eac	289	u32 data)
e898cd22	290	{
78501eac	291	iowrite32(data, ring->virtual_start + ring->tail);
e898cd22 CW	292	ring->tail += 4;
e898cd22 CW	293	}
a4872ba6	294	static inline void intel_ring_advance(struct intel_engine_cs *ring)
09246732 CW	295	{
	296	ring->tail &= ring->size - 1;
	297	}
a4872ba6	298	void __intel_ring_advance(struct intel_engine_cs *ring);
09246732	299
a4872ba6 OM	300	int __must_check intel_ring_idle(struct intel_engine_cs *ring);
	301	void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
	302	int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
	303	int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
8187a2b7	304
5c1143bb XH	305	int intel_init_render_ring_buffer(struct drm_device *dev);
5c1143bb XH	306	int intel_init_bsd_ring_buffer(struct drm_device *dev);
845f74a7	307	int intel_init_bsd2_ring_buffer(struct drm_device *dev);
549f7365	308	int intel_init_blt_ring_buffer(struct drm_device *dev);
9a8a2213	309	int intel_init_vebox_ring_buffer(struct drm_device *dev);
8187a2b7	310
a4872ba6 OM	311	u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
a4872ba6 OM	312	void intel_ring_setup_status_page(struct intel_engine_cs *ring);
79f321b7	313
a4872ba6	314	static inline u32 intel_ring_get_tail(struct intel_engine_cs *ring)
a71d8d94 CW	315	{
	316	return ring->tail;
	317	}
	318
a4872ba6	319	static inline u32 intel_ring_get_seqno(struct intel_engine_cs *ring)
9d773091	320	{
1823521d CW	321	BUG_ON(ring->outstanding_lazy_seqno == 0);
1823521d CW	322	return ring->outstanding_lazy_seqno;
9d773091 CW	323	}
9d773091 CW	324
a4872ba6	325	static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
db53a302 CW	326	{
	327	if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
	328	ring->trace_irq_seqno = seqno;
	329	}
	330
e8616b6c CW	331	/* DRI warts */
	332	int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
	333
8187a2b7	334	#endif /* _INTEL_RINGBUFFER_H_ */